1 /* Disassembler interface for targets using CGEN. -*- C -*-
2 CGEN: Cpu tools GENerator
4 THIS FILE IS USED TO GENERATE m32r-dis.c.
6 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
8 This file is part of the GNU Binutils and GDB, the GNU debugger.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software Foundation, Inc.,
22 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
35 #define INLINE __inline__
40 /* Default text to print if an instruction isn't recognized. */
41 #define UNKNOWN_INSN_MSG _("*unknown*")
43 /* Used by the ifield rtx function. */
44 #define FLD(f) (fields->f)
46 static int extract_normal
47 PARAMS ((CGEN_OPCODE_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT,
48 unsigned int, unsigned int, unsigned int, unsigned int,
49 unsigned int, unsigned int, bfd_vma, long *));
50 static void print_normal
51 PARAMS ((CGEN_OPCODE_DESC, PTR, long, unsigned int, bfd_vma, int));
52 static void print_address
53 PARAMS ((CGEN_OPCODE_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int));
54 static void print_keyword
55 PARAMS ((CGEN_OPCODE_DESC, PTR, CGEN_KEYWORD *, long, unsigned int));
56 static int extract_insn_normal
57 PARAMS ((CGEN_OPCODE_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *,
58 CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma));
59 static void print_insn_normal
60 PARAMS ((CGEN_OPCODE_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *,
62 static int print_insn PARAMS ((CGEN_OPCODE_DESC, bfd_vma,
63 disassemble_info *, char *, int));
64 static int default_print_insn
65 PARAMS ((CGEN_OPCODE_DESC, bfd_vma, disassemble_info *));
67 /* -- disassembler routines inserted here */
70 /* Immediate values are prefixed with '#'. */
72 #define CGEN_PRINT_NORMAL(od, info, value, attrs, pc, length) \
74 if ((attrs) & (1 << CGEN_OPERAND_HASH_PREFIX)) \
75 (*info->fprintf_func) (info->stream, "#"); \
78 /* Handle '#' prefixes as operands. */
81 print_hash (od, dis_info, value, attrs, pc, length)
89 disassemble_info *info = (disassemble_info *) dis_info;
90 (*info->fprintf_func) (info->stream, "#");
93 #undef CGEN_PRINT_INSN
94 #define CGEN_PRINT_INSN my_print_insn
97 my_print_insn (od, pc, info)
100 disassemble_info *info;
102 char buffer[CGEN_MAX_INSN_SIZE];
105 int buflen = (pc & 3) == 0 ? 4 : 2;
107 /* Read the base part of the insn. */
109 status = (*info->read_memory_func) (pc, buf, buflen, info);
112 (*info->memory_error_func) (status, pc, info);
117 if ((pc & 3) == 0 && (buf[0] & 0x80) != 0)
118 return print_insn (od, pc, info, buf, buflen);
120 /* Print the first insn. */
123 if (print_insn (od, pc, info, buf, 2) == 0)
124 (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
131 (*info->fprintf_func) (info->stream, " || ");
135 (*info->fprintf_func) (info->stream, " -> ");
137 /* The "& 3" is to pass a consistent address.
138 Parallel insns arguably both begin on the word boundary.
139 Also, branch insns are calculated relative to the word boundary. */
140 if (print_insn (od, pc & ~ (bfd_vma) 3, info, buf, 2) == 0)
141 (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
143 return (pc & 3) ? 2 : 4;
148 /* Main entry point for operand extraction.
150 This function is basically just a big switch statement. Earlier versions
151 used tables to look up the function to use, but
152 - if the table contains both assembler and disassembler functions then
153 the disassembler contains much of the assembler and vice-versa,
154 - there's a lot of inlining possibilities as things grow,
155 - using a switch statement avoids the function call overhead.
157 This function could be moved into `print_insn_normal', but keeping it
158 separate makes clear the interface between `print_insn_normal' and each of
163 m32r_cgen_extract_operand (od, opindex, ex_info, insn_value, fields, pc)
166 CGEN_EXTRACT_INFO *ex_info;
167 CGEN_INSN_INT insn_value;
168 CGEN_FIELDS * fields;
172 unsigned int total_length = CGEN_FIELDS_BITSIZE (fields);
176 case M32R_OPERAND_SR :
177 length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 12, 4, 32, total_length, pc, & fields->f_r2);
179 case M32R_OPERAND_DR :
180 length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 4, 4, 32, total_length, pc, & fields->f_r1);
182 case M32R_OPERAND_SRC1 :
183 length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 4, 4, 32, total_length, pc, & fields->f_r1);
185 case M32R_OPERAND_SRC2 :
186 length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 12, 4, 32, total_length, pc, & fields->f_r2);
188 case M32R_OPERAND_SCR :
189 length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 12, 4, 32, total_length, pc, & fields->f_r2);
191 case M32R_OPERAND_DCR :
192 length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 4, 4, 32, total_length, pc, & fields->f_r1);
194 case M32R_OPERAND_SIMM8 :
195 length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX), 0, 8, 8, 32, total_length, pc, & fields->f_simm8);
197 case M32R_OPERAND_SIMM16 :
198 length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX), 0, 16, 16, 32, total_length, pc, & fields->f_simm16);
200 case M32R_OPERAND_UIMM4 :
201 length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 0, 12, 4, 32, total_length, pc, & fields->f_uimm4);
203 case M32R_OPERAND_UIMM5 :
204 length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 0, 11, 5, 32, total_length, pc, & fields->f_uimm5);
206 case M32R_OPERAND_UIMM16 :
207 length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 0, 16, 16, 32, total_length, pc, & fields->f_uimm16);
209 /* start-sanitize-m32rx */
210 case M32R_OPERAND_IMM1 :
213 length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), 0, 15, 1, 32, total_length, pc, & value);
214 value = ((value) + (1));
215 fields->f_imm1 = value;
218 /* end-sanitize-m32rx */
219 /* start-sanitize-m32rx */
220 case M32R_OPERAND_ACCD :
221 length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 4, 2, 32, total_length, pc, & fields->f_accd);
223 /* end-sanitize-m32rx */
224 /* start-sanitize-m32rx */
225 case M32R_OPERAND_ACCS :
226 length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 12, 2, 32, total_length, pc, & fields->f_accs);
228 /* end-sanitize-m32rx */
229 /* start-sanitize-m32rx */
230 case M32R_OPERAND_ACC :
231 length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 1, 32, total_length, pc, & fields->f_acc);
233 /* end-sanitize-m32rx */
234 case M32R_OPERAND_HASH :
235 length = extract_normal (od, ex_info, insn_value, 0, 0, 0, 0, 0, total_length, pc, & fields->f_nil);
237 case M32R_OPERAND_HI16 :
238 length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), 0, 16, 16, 32, total_length, pc, & fields->f_hi16);
240 case M32R_OPERAND_SLO16 :
241 length = extract_normal (od, ex_info, insn_value, 0, 0, 16, 16, 32, total_length, pc, & fields->f_simm16);
243 case M32R_OPERAND_ULO16 :
244 length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_UNSIGNED), 0, 16, 16, 32, total_length, pc, & fields->f_uimm16);
246 case M32R_OPERAND_UIMM24 :
247 length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), 0, 8, 24, 32, total_length, pc, & fields->f_uimm24);
249 case M32R_OPERAND_DISP8 :
252 length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 0, 8, 8, 32, total_length, pc, & value);
253 value = ((((value) << (2))) + (((pc) & (-4))));
254 fields->f_disp8 = value;
257 case M32R_OPERAND_DISP16 :
260 length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 0, 16, 16, 32, total_length, pc, & value);
261 value = ((((value) << (2))) + (pc));
262 fields->f_disp16 = value;
265 case M32R_OPERAND_DISP24 :
268 length = extract_normal (od, ex_info, insn_value, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), 0, 8, 24, 32, total_length, pc, & value);
269 value = ((((value) << (2))) + (pc));
270 fields->f_disp24 = value;
275 /* xgettext:c-format */
276 fprintf (stderr, _("Unrecognized field %d while decoding insn.\n"),
284 /* Main entry point for printing operands.
286 This function is basically just a big switch statement. Earlier versions
287 used tables to look up the function to use, but
288 - if the table contains both assembler and disassembler functions then
289 the disassembler contains much of the assembler and vice-versa,
290 - there's a lot of inlining possibilities as things grow,
291 - using a switch statement avoids the function call overhead.
293 This function could be moved into `print_insn_normal', but keeping it
294 separate makes clear the interface between `print_insn_normal' and each of
299 m32r_cgen_print_operand (od, opindex, info, fields, attrs, pc, length)
302 disassemble_info * info;
303 CGEN_FIELDS * fields;
310 case M32R_OPERAND_SR :
311 print_keyword (od, info, & m32r_cgen_opval_h_gr, fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED));
313 case M32R_OPERAND_DR :
314 print_keyword (od, info, & m32r_cgen_opval_h_gr, fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED));
316 case M32R_OPERAND_SRC1 :
317 print_keyword (od, info, & m32r_cgen_opval_h_gr, fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED));
319 case M32R_OPERAND_SRC2 :
320 print_keyword (od, info, & m32r_cgen_opval_h_gr, fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED));
322 case M32R_OPERAND_SCR :
323 print_keyword (od, info, & m32r_cgen_opval_h_cr, fields->f_r2, 0|(1<<CGEN_OPERAND_UNSIGNED));
325 case M32R_OPERAND_DCR :
326 print_keyword (od, info, & m32r_cgen_opval_h_cr, fields->f_r1, 0|(1<<CGEN_OPERAND_UNSIGNED));
328 case M32R_OPERAND_SIMM8 :
329 print_normal (od, info, fields->f_simm8, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
331 case M32R_OPERAND_SIMM16 :
332 print_normal (od, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
334 case M32R_OPERAND_UIMM4 :
335 print_normal (od, info, fields->f_uimm4, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
337 case M32R_OPERAND_UIMM5 :
338 print_normal (od, info, fields->f_uimm5, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
340 case M32R_OPERAND_UIMM16 :
341 print_normal (od, info, fields->f_uimm16, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
343 /* start-sanitize-m32rx */
344 case M32R_OPERAND_IMM1 :
345 print_normal (od, info, fields->f_imm1, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
347 /* end-sanitize-m32rx */
348 /* start-sanitize-m32rx */
349 case M32R_OPERAND_ACCD :
350 print_keyword (od, info, & m32r_cgen_opval_h_accums, fields->f_accd, 0|(1<<CGEN_OPERAND_UNSIGNED));
352 /* end-sanitize-m32rx */
353 /* start-sanitize-m32rx */
354 case M32R_OPERAND_ACCS :
355 print_keyword (od, info, & m32r_cgen_opval_h_accums, fields->f_accs, 0|(1<<CGEN_OPERAND_UNSIGNED));
357 /* end-sanitize-m32rx */
358 /* start-sanitize-m32rx */
359 case M32R_OPERAND_ACC :
360 print_keyword (od, info, & m32r_cgen_opval_h_accums, fields->f_acc, 0|(1<<CGEN_OPERAND_UNSIGNED));
362 /* end-sanitize-m32rx */
363 case M32R_OPERAND_HASH :
364 print_hash (od, info, fields->f_nil, 0, pc, length);
366 case M32R_OPERAND_HI16 :
367 print_normal (od, info, fields->f_hi16, 0|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
369 case M32R_OPERAND_SLO16 :
370 print_normal (od, info, fields->f_simm16, 0, pc, length);
372 case M32R_OPERAND_ULO16 :
373 print_normal (od, info, fields->f_uimm16, 0|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
375 case M32R_OPERAND_UIMM24 :
376 print_address (od, info, fields->f_uimm24, 0|(1<<CGEN_OPERAND_HASH_PREFIX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_UNSIGNED), pc, length);
378 case M32R_OPERAND_DISP8 :
379 print_address (od, info, fields->f_disp8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
381 case M32R_OPERAND_DISP16 :
382 print_address (od, info, fields->f_disp16, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
384 case M32R_OPERAND_DISP24 :
385 print_address (od, info, fields->f_disp24, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
389 /* xgettext:c-format */
390 fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
396 cgen_extract_fn * const m32r_cgen_extract_handlers[] =
402 cgen_print_fn * const m32r_cgen_print_handlers[] =
410 m32r_cgen_init_dis (od)
416 #if ! CGEN_INT_INSN_P
418 /* Subroutine of extract_normal.
419 Ensure sufficient bytes are cached in EX_INFO.
420 OFFSET is the offset in bytes from the start of the insn of the value.
421 BYTES is the length of the needed value.
422 Returns 1 for success, 0 for failure. */
425 fill_cache (od, ex_info, offset, bytes, pc)
427 CGEN_EXTRACT_INFO *ex_info;
431 /* It's doubtful that the middle part has already been fetched so
432 we don't optimize that case. kiss. */
434 disassemble_info *info = (disassemble_info *) ex_info->dis_info;
436 /* First do a quick check. */
437 mask = (1 << bytes) - 1;
438 if (((ex_info->valid >> offset) & mask) == mask)
441 /* Search for the first byte we need to read. */
442 for (mask = 1 << offset; bytes > 0; --bytes, ++offset, mask <<= 1)
443 if (! (mask & ex_info->valid))
451 status = (*info->read_memory_func)
452 (pc, ex_info->insn_bytes + offset, bytes, info);
456 (*info->memory_error_func) (status, pc, info);
460 ex_info->valid |= ((1 << bytes) - 1) << offset;
466 /* Subroutine of extract_normal. */
469 extract_1 (od, ex_info, start, length, word_length, bufp, pc)
471 CGEN_EXTRACT_INFO *ex_info;
472 int start,length,word_length;
476 unsigned long x,mask;
478 int big_p = CGEN_OPCODE_INSN_ENDIAN (od) == CGEN_ENDIAN_BIG;
487 x = bfd_getb16 (bufp);
489 x = bfd_getl16 (bufp);
492 /* ??? This may need reworking as these cases don't necessarily
493 want the first byte and the last two bytes handled like this. */
495 x = (bufp[0] << 16) | bfd_getb16 (bufp + 1);
497 x = bfd_getl16 (bufp) | (bufp[2] << 16);
501 x = bfd_getb32 (bufp);
503 x = bfd_getl32 (bufp);
509 /* Written this way to avoid undefined behaviour. */
510 mask = (((1L << (length - 1)) - 1) << 1) | 1;
511 if (CGEN_INSN_LSB0_P)
512 shift = (start + 1) - length;
514 shift = (word_length - (start + length));
515 return (x >> shift) & mask;
518 #endif /* ! CGEN_INT_INSN_P */
520 /* Default extraction routine.
522 INSN_VALUE is the first CGEN_BASE_INSN_SIZE bits of the insn in host order,
523 or sometimes less for cases like the m32r where the base insn size is 32
524 but some insns are 16 bits.
525 ATTRS is a mask of the boolean attributes. We only need `UNSIGNED',
526 but for generality we take a bitmask of all of them.
527 WORD_OFFSET is the offset in bits from the start of the insn of the value.
528 WORD_LENGTH is the length of the word in bits in which the value resides.
529 START is the starting bit number in the word, architecture origin.
530 LENGTH is the length of VALUE in bits.
531 TOTAL_LENGTH is the total length of the insn in bits.
533 Returns 1 for success, 0 for failure. */
535 /* ??? The return code isn't properly used. wip. */
537 /* ??? This doesn't handle bfd_vma's. Create another function when
541 extract_normal (od, ex_info, insn_value, attrs, word_offset, start, length,
542 word_length, total_length, pc, valuep)
544 CGEN_EXTRACT_INFO *ex_info;
545 CGEN_INSN_INT insn_value;
547 unsigned int word_offset, start, length, word_length, total_length;
553 /* If LENGTH is zero, this operand doesn't contribute to the value
554 so give it a standard value of zero. */
565 if (word_length > 32)
568 /* For architectures with insns smaller than the insn-base-bitsize,
569 word_length may be too big. */
570 #if CGEN_MIN_INSN_BITSIZE < CGEN_BASE_INSN_BITSIZE
572 && word_length > total_length)
573 word_length = total_length;
576 /* Does the value reside in INSN_VALUE? */
578 if (word_offset == 0)
580 /* Written this way to avoid undefined behaviour. */
581 CGEN_INSN_INT mask = (((1L << (length - 1)) - 1) << 1) | 1;
583 if (CGEN_INSN_LSB0_P)
584 value = insn_value >> ((start + 1) - length);
586 value = insn_value >> (word_length - (start + length));
589 if (! CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_UNSIGNED)
590 && (value & (1L << (length - 1))))
594 #if ! CGEN_INT_INSN_P
598 unsigned char *bufp = ex_info->insn_bytes + word_offset / 8;
600 if (word_length > 32)
603 if (fill_cache (od, ex_info, word_offset / 8, word_length / 8, pc) == 0)
606 value = extract_1 (od, ex_info, start, length, word_length, bufp, pc);
609 #endif /* ! CGEN_INT_INSN_P */
616 /* Default print handler. */
619 print_normal (od, dis_info, value, attrs, pc, length)
627 disassemble_info *info = (disassemble_info *) dis_info;
629 #ifdef CGEN_PRINT_NORMAL
630 CGEN_PRINT_NORMAL (od, info, value, attrs, pc, length);
633 /* Print the operand as directed by the attributes. */
634 if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
635 ; /* nothing to do */
636 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_UNSIGNED))
637 (*info->fprintf_func) (info->stream, "0x%lx", value);
639 (*info->fprintf_func) (info->stream, "%ld", value);
642 /* Default address handler. */
645 print_address (od, dis_info, value, attrs, pc, length)
653 disassemble_info *info = (disassemble_info *) dis_info;
655 #ifdef CGEN_PRINT_ADDRESS
656 CGEN_PRINT_ADDRESS (od, info, value, attrs, pc, length);
659 /* Print the operand as directed by the attributes. */
660 if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
661 ; /* nothing to do */
662 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
663 (*info->print_address_func) (value, info);
664 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
665 (*info->print_address_func) (value, info);
666 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_UNSIGNED))
667 (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
669 (*info->fprintf_func) (info->stream, "%ld", (long) value);
672 /* Keyword print handler. */
675 print_keyword (od, dis_info, keyword_table, value, attrs)
678 CGEN_KEYWORD *keyword_table;
682 disassemble_info *info = (disassemble_info *) dis_info;
683 const CGEN_KEYWORD_ENTRY *ke;
685 ke = cgen_keyword_lookup_value (keyword_table, value);
687 (*info->fprintf_func) (info->stream, "%s", ke->name);
689 (*info->fprintf_func) (info->stream, "???");
692 /* Default insn extractor.
694 INSN_VALUE is the first CGEN_BASE_INSN_SIZE bytes, translated to host order.
695 The extracted fields are stored in FIELDS.
696 EX_INFO is used to handle reading variable length insns.
697 Return the length of the insn in bits, or 0 if no match,
698 or -1 if an error occurs fetching data (memory_error_func will have
702 extract_insn_normal (od, insn, ex_info, insn_value, fields, pc)
704 const CGEN_INSN *insn;
705 CGEN_EXTRACT_INFO *ex_info;
706 CGEN_INSN_INT insn_value;
710 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
711 const unsigned char *syn;
713 CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn);
715 CGEN_INIT_EXTRACT (od);
717 for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
721 if (CGEN_SYNTAX_CHAR_P (*syn))
724 length = m32r_cgen_extract_operand (od, CGEN_SYNTAX_FIELD (*syn),
725 ex_info, insn_value, fields, pc);
730 /* We recognized and successfully extracted this insn. */
731 return CGEN_INSN_BITSIZE (insn);
734 /* Default insn printer.
736 DIS_INFO is defined as `PTR' so the disassembler needn't know anything
737 about disassemble_info. */
740 print_insn_normal (od, dis_info, insn, fields, pc, length)
743 const CGEN_INSN *insn;
748 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
749 disassemble_info *info = (disassemble_info *) dis_info;
750 const unsigned char *syn;
752 CGEN_INIT_PRINT (od);
754 for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
756 if (CGEN_SYNTAX_MNEMONIC_P (*syn))
758 (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
761 if (CGEN_SYNTAX_CHAR_P (*syn))
763 (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
767 /* We have an operand. */
768 m32r_cgen_print_operand (od, CGEN_SYNTAX_FIELD (*syn), info,
769 fields, CGEN_INSN_ATTRS (insn), pc, length);
773 /* Utility to print an insn.
774 BUF is the base part of the insn, target byte order, BUFLEN bytes long.
775 The result is the size of the insn in bytes or zero for an unknown insn
776 or -1 if an error occurs fetching data (memory_error_func will have
780 print_insn (od, pc, info, buf, buflen)
783 disassemble_info *info;
787 unsigned long insn_value;
788 const CGEN_INSN_LIST *insn_list;
789 CGEN_EXTRACT_INFO ex_info;
791 ex_info.dis_info = info;
792 ex_info.valid = (1 << CGEN_BASE_INSN_SIZE) - 1;
793 ex_info.insn_bytes = buf;
801 insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb16 (buf) : bfd_getl16 (buf);
804 insn_value = info->endian == BFD_ENDIAN_BIG ? bfd_getb32 (buf) : bfd_getl32 (buf);
810 /* The instructions are stored in hash lists.
811 Pick the first one and keep trying until we find the right one. */
813 insn_list = CGEN_DIS_LOOKUP_INSN (od, buf, insn_value);
814 while (insn_list != NULL)
816 const CGEN_INSN *insn = insn_list->insn;
820 #if 0 /* not needed as insn shouldn't be in hash lists if not supported */
821 /* Supported by this cpu? */
822 if (! m32r_cgen_insn_supported (od, insn))
826 /* Basic bit mask must be correct. */
827 /* ??? May wish to allow target to defer this check until the extract
829 if ((insn_value & CGEN_INSN_BASE_MASK (insn))
830 == CGEN_INSN_BASE_VALUE (insn))
832 /* Printing is handled in two passes. The first pass parses the
833 machine insn and extracts the fields. The second pass prints
836 length = (*CGEN_EXTRACT_FN (insn)) (od, insn, &ex_info, insn_value,
838 /* length < 0 -> error */
843 (*CGEN_PRINT_FN (insn)) (od, info, insn, &fields, pc, length);
844 /* length is in bits, result is in bytes */
849 insn_list = CGEN_DIS_NEXT_INSN (insn_list);
855 /* Default value for CGEN_PRINT_INSN.
856 The result is the size of the insn in bytes or zero for an unknown insn
857 or -1 if an error occured fetching bytes. */
859 #ifndef CGEN_PRINT_INSN
860 #define CGEN_PRINT_INSN default_print_insn
864 default_print_insn (od, pc, info)
867 disassemble_info *info;
869 char buf[CGEN_MAX_INSN_SIZE];
872 /* Read the base part of the insn. */
874 status = (*info->read_memory_func) (pc, buf, CGEN_BASE_INSN_SIZE, info);
877 (*info->memory_error_func) (status, pc, info);
881 return print_insn (od, pc, info, buf, CGEN_BASE_INSN_SIZE);
885 Print one instruction from PC on INFO->STREAM.
886 Return the size of the instruction (in bytes). */
889 print_insn_m32r (pc, info)
891 disassemble_info *info;
894 static CGEN_OPCODE_DESC od = 0;
895 int mach = info->mach;
896 int big_p = info->endian == BFD_ENDIAN_BIG;
898 /* If we haven't initialized yet, initialize the opcode table. */
901 od = m32r_cgen_opcode_open (mach,
904 : CGEN_ENDIAN_LITTLE);
905 m32r_cgen_init_dis (od);
907 /* If we've switched cpu's, re-initialize. */
908 /* ??? Perhaps we should use BFD_ENDIAN. */
909 else if (mach != CGEN_OPCODE_MACH (od)
910 || (CGEN_OPCODE_ENDIAN (od)
911 != (big_p ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE)))
913 cgen_set_cpu (od, mach, big_p ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE);
916 /* We try to have as much common code as possible.
917 But at this point some targets need to take over. */
918 /* ??? Some targets may need a hook elsewhere. Try to avoid this,
919 but if not possible try to move this hook elsewhere rather than
921 length = CGEN_PRINT_INSN (od, pc, info);
927 (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
928 return CGEN_DEFAULT_INSN_SIZE;