opcodes/m32c-desc.c

   1 /* CPU data for m32c.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996-2005 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #include "sysdep.h"
  26 #include <stdio.h>
  27 #include <stdarg.h>
  28 #include "ansidecl.h"
  29 #include "bfd.h"
  30 #include "symcat.h"
  31 #include "m32c-desc.h"
  32 #include "m32c-opc.h"
  33 #include "opintl.h"
  34 #include "libiberty.h"
  35 #include "xregex.h"
  36
  37 /* Attributes.  */
  38
  39 static const CGEN_ATTR_ENTRY bool_attr[] =
  40 {
  41   { "#f", 0 },
  42   { "#t", 1 },
  43   { 0, 0 }
  44 };
  45
  46 static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
  47 {
  48   { "base", MACH_BASE },
  49   { "m16c", MACH_M16C },
  50   { "m32c", MACH_M32C },
  51   { "max", MACH_MAX },
  52   { 0, 0 }
  53 };
  54
  55 static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
  56 {
  57   { "m16c", ISA_M16C },
  58   { "m32c", ISA_M32C },
  59   { "max", ISA_MAX },
  60   { 0, 0 }
  61 };
  62
  63 const CGEN_ATTR_TABLE m32c_cgen_ifield_attr_table[] =
  64 {
  65   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  66   { "ISA", & ISA_attr[0], & ISA_attr[0] },
  67   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  68   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  69   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
  70   { "RESERVED", &bool_attr[0], &bool_attr[0] },
  71   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
  72   { "SIGNED", &bool_attr[0], &bool_attr[0] },
  73   { 0, 0, 0 }
  74 };
  75
  76 const CGEN_ATTR_TABLE m32c_cgen_hardware_attr_table[] =
  77 {
  78   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  79   { "ISA", & ISA_attr[0], & ISA_attr[0] },
  80   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  81   { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
  82   { "PC", &bool_attr[0], &bool_attr[0] },
  83   { "PROFILE", &bool_attr[0], &bool_attr[0] },
  84   { 0, 0, 0 }
  85 };
  86
  87 const CGEN_ATTR_TABLE m32c_cgen_operand_attr_table[] =
  88 {
  89   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  90   { "ISA", & ISA_attr[0], & ISA_attr[0] },
  91   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  92   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  93   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
  94   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
  95   { "SIGNED", &bool_attr[0], &bool_attr[0] },
  96   { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
  97   { "RELAX", &bool_attr[0], &bool_attr[0] },
  98   { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
  99   { 0, 0, 0 }
 100 };
 101
 102 const CGEN_ATTR_TABLE m32c_cgen_insn_attr_table[] =
 103 {
 104   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 105   { "ISA", & ISA_attr[0], & ISA_attr[0] },
 106   { "ALIAS", &bool_attr[0], &bool_attr[0] },
 107   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 108   { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
 109   { "COND-CTI", &bool_attr[0], &bool_attr[0] },
 110   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
 111   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
 112   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
 113   { "RELAXED", &bool_attr[0], &bool_attr[0] },
 114   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
 115   { "PBB", &bool_attr[0], &bool_attr[0] },
 116   { 0, 0, 0 }
 117 };
 118
 119 /* Instruction set variants.  */
 120
 121 static const CGEN_ISA m32c_cgen_isa_table[] = {
 122   { "m16c", 32, 32, 8, 56 },
 123   { "m32c", 32, 32, 8, 80 },
 124   { 0, 0, 0, 0, 0 }
 125 };
 126
 127 /* Machine variants.  */
 128
 129 static const CGEN_MACH m32c_cgen_mach_table[] = {
 130   { "m16c", "m16c", MACH_M16C, 0 },
 131   { "m32c", "m32c", MACH_M32C, 0 },
 132   { 0, 0, 0, 0 }
 133 };
 134
 135 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_entries[] =
 136 {
 137   { "r0", 0, {0, {0}}, 0, 0 },
 138   { "r1", 1, {0, {0}}, 0, 0 },
 139   { "r2", 2, {0, {0}}, 0, 0 },
 140   { "r3", 3, {0, {0}}, 0, 0 }
 141 };
 142
 143 CGEN_KEYWORD m32c_cgen_opval_h_gr =
 144 {
 145   & m32c_cgen_opval_h_gr_entries[0],
 146   4,
 147   0, 0, 0, 0, ""
 148 };
 149
 150 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_QI_entries[] =
 151 {
 152   { "r0l", 0, {0, {0}}, 0, 0 },
 153   { "r0h", 1, {0, {0}}, 0, 0 },
 154   { "r1l", 2, {0, {0}}, 0, 0 },
 155   { "r1h", 3, {0, {0}}, 0, 0 }
 156 };
 157
 158 CGEN_KEYWORD m32c_cgen_opval_h_gr_QI =
 159 {
 160   & m32c_cgen_opval_h_gr_QI_entries[0],
 161   4,
 162   0, 0, 0, 0, ""
 163 };
 164
 165 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_HI_entries[] =
 166 {
 167   { "r0", 0, {0, {0}}, 0, 0 },
 168   { "r1", 1, {0, {0}}, 0, 0 },
 169   { "r2", 2, {0, {0}}, 0, 0 },
 170   { "r3", 3, {0, {0}}, 0, 0 }
 171 };
 172
 173 CGEN_KEYWORD m32c_cgen_opval_h_gr_HI =
 174 {
 175   & m32c_cgen_opval_h_gr_HI_entries[0],
 176   4,
 177   0, 0, 0, 0, ""
 178 };
 179
 180 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_SI_entries[] =
 181 {
 182   { "r2r0", 0, {0, {0}}, 0, 0 },
 183   { "r3r1", 1, {0, {0}}, 0, 0 }
 184 };
 185
 186 CGEN_KEYWORD m32c_cgen_opval_h_gr_SI =
 187 {
 188   & m32c_cgen_opval_h_gr_SI_entries[0],
 189   2,
 190   0, 0, 0, 0, ""
 191 };
 192
 193 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_ext_QI_entries[] =
 194 {
 195   { "r0l", 0, {0, {0}}, 0, 0 },
 196   { "r1l", 1, {0, {0}}, 0, 0 }
 197 };
 198
 199 CGEN_KEYWORD m32c_cgen_opval_h_gr_ext_QI =
 200 {
 201   & m32c_cgen_opval_h_gr_ext_QI_entries[0],
 202   2,
 203   0, 0, 0, 0, ""
 204 };
 205
 206 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_ext_HI_entries[] =
 207 {
 208   { "r0", 0, {0, {0}}, 0, 0 },
 209   { "r1", 1, {0, {0}}, 0, 0 }
 210 };
 211
 212 CGEN_KEYWORD m32c_cgen_opval_h_gr_ext_HI =
 213 {
 214   & m32c_cgen_opval_h_gr_ext_HI_entries[0],
 215   2,
 216   0, 0, 0, 0, ""
 217 };
 218
 219 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0l_entries[] =
 220 {
 221   { "r0l", 0, {0, {0}}, 0, 0 }
 222 };
 223
 224 CGEN_KEYWORD m32c_cgen_opval_h_r0l =
 225 {
 226   & m32c_cgen_opval_h_r0l_entries[0],
 227   1,
 228   0, 0, 0, 0, ""
 229 };
 230
 231 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0h_entries[] =
 232 {
 233   { "r0h", 0, {0, {0}}, 0, 0 }
 234 };
 235
 236 CGEN_KEYWORD m32c_cgen_opval_h_r0h =
 237 {
 238   & m32c_cgen_opval_h_r0h_entries[0],
 239   1,
 240   0, 0, 0, 0, ""
 241 };
 242
 243 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1l_entries[] =
 244 {
 245   { "r1l", 0, {0, {0}}, 0, 0 }
 246 };
 247
 248 CGEN_KEYWORD m32c_cgen_opval_h_r1l =
 249 {
 250   & m32c_cgen_opval_h_r1l_entries[0],
 251   1,
 252   0, 0, 0, 0, ""
 253 };
 254
 255 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1h_entries[] =
 256 {
 257   { "r1h", 0, {0, {0}}, 0, 0 }
 258 };
 259
 260 CGEN_KEYWORD m32c_cgen_opval_h_r1h =
 261 {
 262   & m32c_cgen_opval_h_r1h_entries[0],
 263   1,
 264   0, 0, 0, 0, ""
 265 };
 266
 267 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0_entries[] =
 268 {
 269   { "r0", 0, {0, {0}}, 0, 0 }
 270 };
 271
 272 CGEN_KEYWORD m32c_cgen_opval_h_r0 =
 273 {
 274   & m32c_cgen_opval_h_r0_entries[0],
 275   1,
 276   0, 0, 0, 0, ""
 277 };
 278
 279 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1_entries[] =
 280 {
 281   { "r1", 0, {0, {0}}, 0, 0 }
 282 };
 283
 284 CGEN_KEYWORD m32c_cgen_opval_h_r1 =
 285 {
 286   & m32c_cgen_opval_h_r1_entries[0],
 287   1,
 288   0, 0, 0, 0, ""
 289 };
 290
 291 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r2_entries[] =
 292 {
 293   { "r2", 0, {0, {0}}, 0, 0 }
 294 };
 295
 296 CGEN_KEYWORD m32c_cgen_opval_h_r2 =
 297 {
 298   & m32c_cgen_opval_h_r2_entries[0],
 299   1,
 300   0, 0, 0, 0, ""
 301 };
 302
 303 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r3_entries[] =
 304 {
 305   { "r3", 0, {0, {0}}, 0, 0 }
 306 };
 307
 308 CGEN_KEYWORD m32c_cgen_opval_h_r3 =
 309 {
 310   & m32c_cgen_opval_h_r3_entries[0],
 311   1,
 312   0, 0, 0, 0, ""
 313 };
 314
 315 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0l_r0h_entries[] =
 316 {
 317   { "r0l", 0, {0, {0}}, 0, 0 },
 318   { "r0h", 1, {0, {0}}, 0, 0 }
 319 };
 320
 321 CGEN_KEYWORD m32c_cgen_opval_h_r0l_r0h =
 322 {
 323   & m32c_cgen_opval_h_r0l_r0h_entries[0],
 324   2,
 325   0, 0, 0, 0, ""
 326 };
 327
 328 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r2r0_entries[] =
 329 {
 330   { "r2r0", 0, {0, {0}}, 0, 0 }
 331 };
 332
 333 CGEN_KEYWORD m32c_cgen_opval_h_r2r0 =
 334 {
 335   & m32c_cgen_opval_h_r2r0_entries[0],
 336   1,
 337   0, 0, 0, 0, ""
 338 };
 339
 340 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r3r1_entries[] =
 341 {
 342   { "r3r1", 0, {0, {0}}, 0, 0 }
 343 };
 344
 345 CGEN_KEYWORD m32c_cgen_opval_h_r3r1 =
 346 {
 347   & m32c_cgen_opval_h_r3r1_entries[0],
 348   1,
 349   0, 0, 0, 0, ""
 350 };
 351
 352 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1r2r0_entries[] =
 353 {
 354   { "r1r2r0", 0, {0, {0}}, 0, 0 }
 355 };
 356
 357 CGEN_KEYWORD m32c_cgen_opval_h_r1r2r0 =
 358 {
 359   & m32c_cgen_opval_h_r1r2r0_entries[0],
 360   1,
 361   0, 0, 0, 0, ""
 362 };
 363
 364 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_entries[] =
 365 {
 366   { "a0", 0, {0, {0}}, 0, 0 },
 367   { "a1", 1, {0, {0}}, 0, 0 }
 368 };
 369
 370 CGEN_KEYWORD m32c_cgen_opval_h_ar =
 371 {
 372   & m32c_cgen_opval_h_ar_entries[0],
 373   2,
 374   0, 0, 0, 0, ""
 375 };
 376
 377 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_QI_entries[] =
 378 {
 379   { "a0", 0, {0, {0}}, 0, 0 },
 380   { "a1", 1, {0, {0}}, 0, 0 }
 381 };
 382
 383 CGEN_KEYWORD m32c_cgen_opval_h_ar_QI =
 384 {
 385   & m32c_cgen_opval_h_ar_QI_entries[0],
 386   2,
 387   0, 0, 0, 0, ""
 388 };
 389
 390 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_HI_entries[] =
 391 {
 392   { "a0", 0, {0, {0}}, 0, 0 },
 393   { "a1", 1, {0, {0}}, 0, 0 }
 394 };
 395
 396 CGEN_KEYWORD m32c_cgen_opval_h_ar_HI =
 397 {
 398   & m32c_cgen_opval_h_ar_HI_entries[0],
 399   2,
 400   0, 0, 0, 0, ""
 401 };
 402
 403 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_SI_entries[] =
 404 {
 405   { "a1a0", 0, {0, {0}}, 0, 0 }
 406 };
 407
 408 CGEN_KEYWORD m32c_cgen_opval_h_ar_SI =
 409 {
 410   & m32c_cgen_opval_h_ar_SI_entries[0],
 411   1,
 412   0, 0, 0, 0, ""
 413 };
 414
 415 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_a0_entries[] =
 416 {
 417   { "a0", 0, {0, {0}}, 0, 0 }
 418 };
 419
 420 CGEN_KEYWORD m32c_cgen_opval_h_a0 =
 421 {
 422   & m32c_cgen_opval_h_a0_entries[0],
 423   1,
 424   0, 0, 0, 0, ""
 425 };
 426
 427 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_a1_entries[] =
 428 {
 429   { "a1", 1, {0, {0}}, 0, 0 }
 430 };
 431
 432 CGEN_KEYWORD m32c_cgen_opval_h_a1 =
 433 {
 434   & m32c_cgen_opval_h_a1_entries[0],
 435   1,
 436   0, 0, 0, 0, ""
 437 };
 438
 439 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16_entries[] =
 440 {
 441   { "geu", 0, {0, {0}}, 0, 0 },
 442   { "c", 0, {0, {0}}, 0, 0 },
 443   { "gtu", 1, {0, {0}}, 0, 0 },
 444   { "eq", 2, {0, {0}}, 0, 0 },
 445   { "z", 2, {0, {0}}, 0, 0 },
 446   { "n", 3, {0, {0}}, 0, 0 },
 447   { "le", 4, {0, {0}}, 0, 0 },
 448   { "o", 5, {0, {0}}, 0, 0 },
 449   { "ge", 6, {0, {0}}, 0, 0 },
 450   { "ltu", 248, {0, {0}}, 0, 0 },
 451   { "nc", 248, {0, {0}}, 0, 0 },
 452   { "leu", 249, {0, {0}}, 0, 0 },
 453   { "ne", 250, {0, {0}}, 0, 0 },
 454   { "nz", 250, {0, {0}}, 0, 0 },
 455   { "pz", 251, {0, {0}}, 0, 0 },
 456   { "gt", 252, {0, {0}}, 0, 0 },
 457   { "no", 253, {0, {0}}, 0, 0 },
 458   { "lt", 254, {0, {0}}, 0, 0 }
 459 };
 460
 461 CGEN_KEYWORD m32c_cgen_opval_h_cond16 =
 462 {
 463   & m32c_cgen_opval_h_cond16_entries[0],
 464   18,
 465   0, 0, 0, 0, ""
 466 };
 467
 468 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16c_entries[] =
 469 {
 470   { "geu", 0, {0, {0}}, 0, 0 },
 471   { "c", 0, {0, {0}}, 0, 0 },
 472   { "gtu", 1, {0, {0}}, 0, 0 },
 473   { "eq", 2, {0, {0}}, 0, 0 },
 474   { "z", 2, {0, {0}}, 0, 0 },
 475   { "n", 3, {0, {0}}, 0, 0 },
 476   { "ltu", 4, {0, {0}}, 0, 0 },
 477   { "nc", 4, {0, {0}}, 0, 0 },
 478   { "leu", 5, {0, {0}}, 0, 0 },
 479   { "ne", 6, {0, {0}}, 0, 0 },
 480   { "nz", 6, {0, {0}}, 0, 0 },
 481   { "pz", 7, {0, {0}}, 0, 0 },
 482   { "le", 8, {0, {0}}, 0, 0 },
 483   { "o", 9, {0, {0}}, 0, 0 },
 484   { "ge", 10, {0, {0}}, 0, 0 },
 485   { "gt", 12, {0, {0}}, 0, 0 },
 486   { "no", 13, {0, {0}}, 0, 0 },
 487   { "lt", 14, {0, {0}}, 0, 0 }
 488 };
 489
 490 CGEN_KEYWORD m32c_cgen_opval_h_cond16c =
 491 {
 492   & m32c_cgen_opval_h_cond16c_entries[0],
 493   18,
 494   0, 0, 0, 0, ""
 495 };
 496
 497 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16j_entries[] =
 498 {
 499   { "le", 8, {0, {0}}, 0, 0 },
 500   { "o", 9, {0, {0}}, 0, 0 },
 501   { "ge", 10, {0, {0}}, 0, 0 },
 502   { "gt", 12, {0, {0}}, 0, 0 },
 503   { "no", 13, {0, {0}}, 0, 0 },
 504   { "lt", 14, {0, {0}}, 0, 0 }
 505 };
 506
 507 CGEN_KEYWORD m32c_cgen_opval_h_cond16j =
 508 {
 509   & m32c_cgen_opval_h_cond16j_entries[0],
 510   6,
 511   0, 0, 0, 0, ""
 512 };
 513
 514 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16j_5_entries[] =
 515 {
 516   { "geu", 0, {0, {0}}, 0, 0 },
 517   { "c", 0, {0, {0}}, 0, 0 },
 518   { "gtu", 1, {0, {0}}, 0, 0 },
 519   { "eq", 2, {0, {0}}, 0, 0 },
 520   { "z", 2, {0, {0}}, 0, 0 },
 521   { "n", 3, {0, {0}}, 0, 0 },
 522   { "ltu", 4, {0, {0}}, 0, 0 },
 523   { "nc", 4, {0, {0}}, 0, 0 },
 524   { "leu", 5, {0, {0}}, 0, 0 },
 525   { "ne", 6, {0, {0}}, 0, 0 },
 526   { "nz", 6, {0, {0}}, 0, 0 },
 527   { "pz", 7, {0, {0}}, 0, 0 }
 528 };
 529
 530 CGEN_KEYWORD m32c_cgen_opval_h_cond16j_5 =
 531 {
 532   & m32c_cgen_opval_h_cond16j_5_entries[0],
 533   12,
 534   0, 0, 0, 0, ""
 535 };
 536
 537 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond32_entries[] =
 538 {
 539   { "ltu", 0, {0, {0}}, 0, 0 },
 540   { "nc", 0, {0, {0}}, 0, 0 },
 541   { "leu", 1, {0, {0}}, 0, 0 },
 542   { "ne", 2, {0, {0}}, 0, 0 },
 543   { "nz", 2, {0, {0}}, 0, 0 },
 544   { "pz", 3, {0, {0}}, 0, 0 },
 545   { "no", 4, {0, {0}}, 0, 0 },
 546   { "gt", 5, {0, {0}}, 0, 0 },
 547   { "ge", 6, {0, {0}}, 0, 0 },
 548   { "geu", 8, {0, {0}}, 0, 0 },
 549   { "c", 8, {0, {0}}, 0, 0 },
 550   { "gtu", 9, {0, {0}}, 0, 0 },
 551   { "eq", 10, {0, {0}}, 0, 0 },
 552   { "z", 10, {0, {0}}, 0, 0 },
 553   { "n", 11, {0, {0}}, 0, 0 },
 554   { "o", 12, {0, {0}}, 0, 0 },
 555   { "le", 13, {0, {0}}, 0, 0 },
 556   { "lt", 14, {0, {0}}, 0, 0 }
 557 };
 558
 559 CGEN_KEYWORD m32c_cgen_opval_h_cond32 =
 560 {
 561   & m32c_cgen_opval_h_cond32_entries[0],
 562   18,
 563   0, 0, 0, 0, ""
 564 };
 565
 566 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr1_32_entries[] =
 567 {
 568   { "dct0", 0, {0, {0}}, 0, 0 },
 569   { "dct1", 1, {0, {0}}, 0, 0 },
 570   { "flg", 2, {0, {0}}, 0, 0 },
 571   { "svf", 3, {0, {0}}, 0, 0 },
 572   { "drc0", 4, {0, {0}}, 0, 0 },
 573   { "drc1", 5, {0, {0}}, 0, 0 },
 574   { "dmd0", 6, {0, {0}}, 0, 0 },
 575   { "dmd1", 7, {0, {0}}, 0, 0 }
 576 };
 577
 578 CGEN_KEYWORD m32c_cgen_opval_h_cr1_32 =
 579 {
 580   & m32c_cgen_opval_h_cr1_32_entries[0],
 581   8,
 582   0, 0, 0, 0, ""
 583 };
 584
 585 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr2_32_entries[] =
 586 {
 587   { "intb", 0, {0, {0}}, 0, 0 },
 588   { "sp", 1, {0, {0}}, 0, 0 },
 589   { "sb", 2, {0, {0}}, 0, 0 },
 590   { "fb", 3, {0, {0}}, 0, 0 },
 591   { "svp", 4, {0, {0}}, 0, 0 },
 592   { "vct", 5, {0, {0}}, 0, 0 },
 593   { "isp", 7, {0, {0}}, 0, 0 }
 594 };
 595
 596 CGEN_KEYWORD m32c_cgen_opval_h_cr2_32 =
 597 {
 598   & m32c_cgen_opval_h_cr2_32_entries[0],
 599   7,
 600   0, 0, 0, 0, ""
 601 };
 602
 603 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr3_32_entries[] =
 604 {
 605   { "dma0", 2, {0, {0}}, 0, 0 },
 606   { "dma1", 3, {0, {0}}, 0, 0 },
 607   { "dra0", 4, {0, {0}}, 0, 0 },
 608   { "dra1", 5, {0, {0}}, 0, 0 },
 609   { "dsa0", 6, {0, {0}}, 0, 0 },
 610   { "dsa1", 7, {0, {0}}, 0, 0 }
 611 };
 612
 613 CGEN_KEYWORD m32c_cgen_opval_h_cr3_32 =
 614 {
 615   & m32c_cgen_opval_h_cr3_32_entries[0],
 616   6,
 617   0, 0, 0, 0, ""
 618 };
 619
 620 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr_16_entries[] =
 621 {
 622   { "intbl", 1, {0, {0}}, 0, 0 },
 623   { "intbh", 2, {0, {0}}, 0, 0 },
 624   { "flg", 3, {0, {0}}, 0, 0 },
 625   { "isp", 4, {0, {0}}, 0, 0 },
 626   { "sp", 5, {0, {0}}, 0, 0 },
 627   { "sb", 6, {0, {0}}, 0, 0 },
 628   { "fb", 7, {0, {0}}, 0, 0 }
 629 };
 630
 631 CGEN_KEYWORD m32c_cgen_opval_h_cr_16 =
 632 {
 633   & m32c_cgen_opval_h_cr_16_entries[0],
 634   7,
 635   0, 0, 0, 0, ""
 636 };
 637
 638 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_flags_entries[] =
 639 {
 640   { "c", 0, {0, {0}}, 0, 0 },
 641   { "d", 1, {0, {0}}, 0, 0 },
 642   { "z", 2, {0, {0}}, 0, 0 },
 643   { "s", 3, {0, {0}}, 0, 0 },
 644   { "b", 4, {0, {0}}, 0, 0 },
 645   { "o", 5, {0, {0}}, 0, 0 },
 646   { "i", 6, {0, {0}}, 0, 0 },
 647   { "u", 7, {0, {0}}, 0, 0 }
 648 };
 649
 650 CGEN_KEYWORD m32c_cgen_opval_h_flags =
 651 {
 652   & m32c_cgen_opval_h_flags_entries[0],
 653   8,
 654   0, 0, 0, 0, ""
 655 };
 656
 657 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_shimm_entries[] =
 658 {
 659   { "1", 0, {0, {0}}, 0, 0 },
 660   { "2", 1, {0, {0}}, 0, 0 },
 661   { "3", 2, {0, {0}}, 0, 0 },
 662   { "4", 3, {0, {0}}, 0, 0 },
 663   { "5", 4, {0, {0}}, 0, 0 },
 664   { "6", 5, {0, {0}}, 0, 0 },
 665   { "7", 6, {0, {0}}, 0, 0 },
 666   { "8", 7, {0, {0}}, 0, 0 },
 667   { "-1", -8, {0, {0}}, 0, 0 },
 668   { "-2", -7, {0, {0}}, 0, 0 },
 669   { "-3", -6, {0, {0}}, 0, 0 },
 670   { "-4", -5, {0, {0}}, 0, 0 },
 671   { "-5", -4, {0, {0}}, 0, 0 },
 672   { "-6", -3, {0, {0}}, 0, 0 },
 673   { "-7", -2, {0, {0}}, 0, 0 },
 674   { "-8", -1, {0, {0}}, 0, 0 }
 675 };
 676
 677 CGEN_KEYWORD m32c_cgen_opval_h_shimm =
 678 {
 679   & m32c_cgen_opval_h_shimm_entries[0],
 680   16,
 681   0, 0, 0, 0, ""
 682 };
 683
 684
 685 /* The hardware table.  */
 686
 687 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 688 #define A(a) (1 << CGEN_HW_##a)
 689 #else
 690 #define A(a) (1 << CGEN_HW_/**/a)
 691 #endif
 692
 693 const CGEN_HW_ENTRY m32c_cgen_hw_table[] =
 694 {
 695   { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 696   { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 697   { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 698   { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 699   { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 700   { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 701   { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr, { 0|A(CACHE_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 702   { "h-gr-QI", HW_H_GR_QI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_QI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 703   { "h-gr-HI", HW_H_GR_HI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_HI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 704   { "h-gr-SI", HW_H_GR_SI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_SI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 705   { "h-gr-ext-QI", HW_H_GR_EXT_QI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_ext_QI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 706   { "h-gr-ext-HI", HW_H_GR_EXT_HI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_ext_HI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 707   { "h-r0l", HW_H_R0L, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r0l, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 708   { "h-r0h", HW_H_R0H, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r0h, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 709   { "h-r1l", HW_H_R1L, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r1l, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 710   { "h-r1h", HW_H_R1H, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r1h, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 711   { "h-r0", HW_H_R0, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r0, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 712   { "h-r1", HW_H_R1, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r1, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 713   { "h-r2", HW_H_R2, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r2, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 714   { "h-r3", HW_H_R3, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r3, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 715   { "h-r0l-r0h", HW_H_R0L_R0H, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r0l_r0h, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 716   { "h-r2r0", HW_H_R2R0, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r2r0, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 717   { "h-r3r1", HW_H_R3R1, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r3r1, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 718   { "h-r1r2r0", HW_H_R1R2R0, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r1r2r0, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 719   { "h-ar", HW_H_AR, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_ar, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 720   { "h-ar-QI", HW_H_AR_QI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_ar_QI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 721   { "h-ar-HI", HW_H_AR_HI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_ar_HI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 722   { "h-ar-SI", HW_H_AR_SI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_ar_SI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 723   { "h-a0", HW_H_A0, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_a0, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 724   { "h-a1", HW_H_A1, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_a1, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 725   { "h-sb", HW_H_SB, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 726   { "h-fb", HW_H_FB, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 727   { "h-sp", HW_H_SP, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 728   { "h-sbit", HW_H_SBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 729   { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 730   { "h-obit", HW_H_OBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 731   { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 732   { "h-ubit", HW_H_UBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 733   { "h-ibit", HW_H_IBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 734   { "h-bbit", HW_H_BBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 735   { "h-dbit", HW_H_DBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 736   { "h-dct0", HW_H_DCT0, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 737   { "h-dct1", HW_H_DCT1, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 738   { "h-svf", HW_H_SVF, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 739   { "h-drc0", HW_H_DRC0, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 740   { "h-drc1", HW_H_DRC1, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 741   { "h-dmd0", HW_H_DMD0, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 742   { "h-dmd1", HW_H_DMD1, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 743   { "h-intb", HW_H_INTB, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 744   { "h-svp", HW_H_SVP, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 745   { "h-vct", HW_H_VCT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 746   { "h-isp", HW_H_ISP, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 747   { "h-dma0", HW_H_DMA0, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 748   { "h-dma1", HW_H_DMA1, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 749   { "h-dra0", HW_H_DRA0, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 750   { "h-dra1", HW_H_DRA1, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 751   { "h-dsa0", HW_H_DSA0, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 752   { "h-dsa1", HW_H_DSA1, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 753   { "h-cond16", HW_H_COND16, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond16, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
 754   { "h-cond16c", HW_H_COND16C, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond16c, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
 755   { "h-cond16j", HW_H_COND16J, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond16j, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
 756   { "h-cond16j-5", HW_H_COND16J_5, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond16j_5, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
 757   { "h-cond32", HW_H_COND32, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond32, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
 758   { "h-cr1-32", HW_H_CR1_32, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cr1_32, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
 759   { "h-cr2-32", HW_H_CR2_32, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cr2_32, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
 760   { "h-cr3-32", HW_H_CR3_32, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cr3_32, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
 761   { "h-cr-16", HW_H_CR_16, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cr_16, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
 762   { "h-flags", HW_H_FLAGS, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_flags, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 763   { "h-shimm", HW_H_SHIMM, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_shimm, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 764   { "h-bit-index", HW_H_BIT_INDEX, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
 765   { "h-src-index", HW_H_SRC_INDEX, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
 766   { "h-dst-index", HW_H_DST_INDEX, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
 767   { "h-src-indirect", HW_H_SRC_INDIRECT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 768   { "h-dst-indirect", HW_H_DST_INDIRECT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
 769   { "h-none", HW_H_NONE, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
 770   { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
 771 };
 772
 773 #undef A
 774
 775
 776 /* The instruction field table.  */
 777
 778 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 779 #define A(a) (1 << CGEN_IFLD_##a)
 780 #else
 781 #define A(a) (1 << CGEN_IFLD_/**/a)
 782 #endif
 783
 784 const CGEN_IFLD m32c_cgen_ifld_table[] =
 785 {
 786   { M32C_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }  },
 787   { M32C_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }  },
 788   { M32C_F_0_1, "f-0-1", 0, 32, 0, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 789   { M32C_F_0_2, "f-0-2", 0, 32, 0, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 790   { M32C_F_0_3, "f-0-3", 0, 32, 0, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 791   { M32C_F_0_4, "f-0-4", 0, 32, 0, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 792   { M32C_F_1_3, "f-1-3", 0, 32, 1, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 793   { M32C_F_2_2, "f-2-2", 0, 32, 2, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 794   { M32C_F_3_4, "f-3-4", 0, 32, 3, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 795   { M32C_F_3_1, "f-3-1", 0, 32, 3, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 796   { M32C_F_4_1, "f-4-1", 0, 32, 4, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 797   { M32C_F_4_3, "f-4-3", 0, 32, 4, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 798   { M32C_F_4_4, "f-4-4", 0, 32, 4, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 799   { M32C_F_4_6, "f-4-6", 0, 32, 4, 6, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 800   { M32C_F_5_1, "f-5-1", 0, 32, 5, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 801   { M32C_F_5_3, "f-5-3", 0, 32, 5, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 802   { M32C_F_6_2, "f-6-2", 0, 32, 6, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 803   { M32C_F_7_1, "f-7-1", 0, 32, 7, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 804   { M32C_F_8_1, "f-8-1", 0, 32, 8, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 805   { M32C_F_8_2, "f-8-2", 0, 32, 8, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 806   { M32C_F_8_3, "f-8-3", 0, 32, 8, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 807   { M32C_F_8_4, "f-8-4", 0, 32, 8, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 808   { M32C_F_8_8, "f-8-8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 809   { M32C_F_9_3, "f-9-3", 0, 32, 9, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 810   { M32C_F_9_1, "f-9-1", 0, 32, 9, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 811   { M32C_F_10_1, "f-10-1", 0, 32, 10, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 812   { M32C_F_10_2, "f-10-2", 0, 32, 10, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 813   { M32C_F_10_3, "f-10-3", 0, 32, 10, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 814   { M32C_F_11_1, "f-11-1", 0, 32, 11, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 815   { M32C_F_12_1, "f-12-1", 0, 32, 12, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 816   { M32C_F_12_2, "f-12-2", 0, 32, 12, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 817   { M32C_F_12_3, "f-12-3", 0, 32, 12, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 818   { M32C_F_12_4, "f-12-4", 0, 32, 12, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 819   { M32C_F_12_6, "f-12-6", 0, 32, 12, 6, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 820   { M32C_F_13_3, "f-13-3", 0, 32, 13, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 821   { M32C_F_14_1, "f-14-1", 0, 32, 14, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 822   { M32C_F_14_2, "f-14-2", 0, 32, 14, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 823   { M32C_F_15_1, "f-15-1", 0, 32, 15, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 824   { M32C_F_16_1, "f-16-1", 0, 32, 16, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 825   { M32C_F_16_2, "f-16-2", 0, 32, 16, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 826   { M32C_F_16_4, "f-16-4", 0, 32, 16, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 827   { M32C_F_16_8, "f-16-8", 0, 32, 16, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 828   { M32C_F_18_1, "f-18-1", 0, 32, 18, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 829   { M32C_F_18_2, "f-18-2", 0, 32, 18, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 830   { M32C_F_18_3, "f-18-3", 0, 32, 18, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 831   { M32C_F_20_1, "f-20-1", 0, 32, 20, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 832   { M32C_F_20_3, "f-20-3", 0, 32, 20, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 833   { M32C_F_20_2, "f-20-2", 0, 32, 20, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 834   { M32C_F_20_4, "f-20-4", 0, 32, 20, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 835   { M32C_F_21_3, "f-21-3", 0, 32, 21, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 836   { M32C_F_24_2, "f-24-2", 0, 32, 24, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 837   { M32C_F_24_8, "f-24-8", 0, 32, 24, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 838   { M32C_F_32_16, "f-32-16", 32, 32, 0, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 839   { M32C_F_SRC16_RN, "f-src16-rn", 0, 32, 10, 2, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
 840   { M32C_F_SRC16_AN, "f-src16-an", 0, 32, 11, 1, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
 841   { M32C_F_SRC32_AN_UNPREFIXED, "f-src32-an-unprefixed", 0, 32, 11, 1, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
 842   { M32C_F_SRC32_AN_PREFIXED, "f-src32-an-prefixed", 0, 32, 19, 1, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
 843   { M32C_F_SRC32_RN_UNPREFIXED_QI, "f-src32-rn-unprefixed-QI", 0, 32, 10, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
 844   { M32C_F_SRC32_RN_PREFIXED_QI, "f-src32-rn-prefixed-QI", 0, 32, 18, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
 845   { M32C_F_SRC32_RN_UNPREFIXED_HI, "f-src32-rn-unprefixed-HI", 0, 32, 10, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
 846   { M32C_F_SRC32_RN_PREFIXED_HI, "f-src32-rn-prefixed-HI", 0, 32, 18, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
 847   { M32C_F_SRC32_RN_UNPREFIXED_SI, "f-src32-rn-unprefixed-SI", 0, 32, 10, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
 848   { M32C_F_SRC32_RN_PREFIXED_SI, "f-src32-rn-prefixed-SI", 0, 32, 18, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
 849   { M32C_F_DST32_RN_EXT_UNPREFIXED, "f-dst32-rn-ext-unprefixed", 0, 32, 9, 1, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
 850   { M32C_F_DST16_RN, "f-dst16-rn", 0, 32, 14, 2, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
 851   { M32C_F_DST16_RN_EXT, "f-dst16-rn-ext", 0, 32, 14, 1, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
 852   { M32C_F_DST16_RN_QI_S, "f-dst16-rn-QI-s", 0, 32, 5, 1, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
 853   { M32C_F_DST16_AN, "f-dst16-an", 0, 32, 15, 1, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
 854   { M32C_F_DST16_AN_S, "f-dst16-an-s", 0, 32, 4, 1, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
 855   { M32C_F_DST32_AN_UNPREFIXED, "f-dst32-an-unprefixed", 0, 32, 9, 1, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
 856   { M32C_F_DST32_AN_PREFIXED, "f-dst32-an-prefixed", 0, 32, 17, 1, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
 857   { M32C_F_DST32_RN_UNPREFIXED_QI, "f-dst32-rn-unprefixed-QI", 0, 32, 8, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
 858   { M32C_F_DST32_RN_PREFIXED_QI, "f-dst32-rn-prefixed-QI", 0, 32, 16, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
 859   { M32C_F_DST32_RN_UNPREFIXED_HI, "f-dst32-rn-unprefixed-HI", 0, 32, 8, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
 860   { M32C_F_DST32_RN_PREFIXED_HI, "f-dst32-rn-prefixed-HI", 0, 32, 16, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
 861   { M32C_F_DST32_RN_UNPREFIXED_SI, "f-dst32-rn-unprefixed-SI", 0, 32, 8, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
 862   { M32C_F_DST32_RN_PREFIXED_SI, "f-dst32-rn-prefixed-SI", 0, 32, 16, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
 863   { M32C_F_DST16_1_S, "f-dst16-1-S", 0, 32, 5, 1, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
 864   { M32C_F_IMM_8_S4, "f-imm-8-s4", 0, 32, 8, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 865   { M32C_F_IMM_12_S4, "f-imm-12-s4", 0, 32, 12, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 866   { M32C_F_IMM_13_U3, "f-imm-13-u3", 0, 32, 13, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 867   { M32C_F_IMM_20_S4, "f-imm-20-s4", 0, 32, 20, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 868   { M32C_F_IMM1_S, "f-imm1-S", 0, 32, 2, 1, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
 869   { M32C_F_IMM3_S, "f-imm3-S", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 870   { M32C_F_DSP_8_U6, "f-dsp-8-u6", 0, 32, 8, 6, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 871   { M32C_F_DSP_8_U8, "f-dsp-8-u8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 872   { M32C_F_DSP_8_S8, "f-dsp-8-s8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 873   { M32C_F_DSP_10_U6, "f-dsp-10-u6", 0, 32, 10, 6, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 874   { M32C_F_DSP_16_U8, "f-dsp-16-u8", 0, 32, 16, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 875   { M32C_F_DSP_16_S8, "f-dsp-16-s8", 0, 32, 16, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 876   { M32C_F_DSP_24_U8, "f-dsp-24-u8", 0, 32, 24, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 877   { M32C_F_DSP_24_S8, "f-dsp-24-s8", 0, 32, 24, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 878   { M32C_F_DSP_32_U8, "f-dsp-32-u8", 32, 32, 0, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 879   { M32C_F_DSP_32_S8, "f-dsp-32-s8", 32, 32, 0, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 880   { M32C_F_DSP_40_U8, "f-dsp-40-u8", 32, 32, 8, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 881   { M32C_F_DSP_40_S8, "f-dsp-40-s8", 32, 32, 8, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 882   { M32C_F_DSP_48_U8, "f-dsp-48-u8", 32, 32, 16, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 883   { M32C_F_DSP_48_S8, "f-dsp-48-s8", 32, 32, 16, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 884   { M32C_F_DSP_56_U8, "f-dsp-56-u8", 32, 32, 24, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 885   { M32C_F_DSP_56_S8, "f-dsp-56-s8", 32, 32, 24, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 886   { M32C_F_DSP_64_U8, "f-dsp-64-u8", 64, 32, 0, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 887   { M32C_F_DSP_64_S8, "f-dsp-64-s8", 64, 32, 0, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 888   { M32C_F_DSP_8_U16, "f-dsp-8-u16", 0, 32, 8, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 889   { M32C_F_DSP_8_S16, "f-dsp-8-s16", 0, 32, 8, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 890   { M32C_F_DSP_16_U16, "f-dsp-16-u16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 891   { M32C_F_DSP_16_S16, "f-dsp-16-s16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 892   { M32C_F_DSP_24_U16, "f-dsp-24-u16", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 893   { M32C_F_DSP_24_S16, "f-dsp-24-s16", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 894   { M32C_F_DSP_32_U16, "f-dsp-32-u16", 32, 32, 0, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 895   { M32C_F_DSP_32_S16, "f-dsp-32-s16", 32, 32, 0, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 896   { M32C_F_DSP_40_U16, "f-dsp-40-u16", 32, 32, 8, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 897   { M32C_F_DSP_40_S16, "f-dsp-40-s16", 32, 32, 8, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 898   { M32C_F_DSP_48_U16, "f-dsp-48-u16", 32, 32, 16, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 899   { M32C_F_DSP_48_S16, "f-dsp-48-s16", 32, 32, 16, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 900   { M32C_F_DSP_64_U16, "f-dsp-64-u16", 64, 32, 0, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 901   { M32C_F_DSP_8_U24, "f-dsp-8-u24", 0, 32, 8, 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 902   { M32C_F_DSP_16_U24, "f-dsp-16-u24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 903   { M32C_F_DSP_24_U24, "f-dsp-24-u24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 904   { M32C_F_DSP_32_U24, "f-dsp-32-u24", 32, 32, 0, 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 905   { M32C_F_DSP_40_U24, "f-dsp-40-u24", 32, 32, 8, 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 906   { M32C_F_DSP_40_S32, "f-dsp-40-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 907   { M32C_F_DSP_48_U24, "f-dsp-48-u24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 908   { M32C_F_DSP_16_S32, "f-dsp-16-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 909   { M32C_F_DSP_24_S32, "f-dsp-24-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 910   { M32C_F_DSP_32_S32, "f-dsp-32-s32", 32, 32, 0, 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 911   { M32C_F_DSP_48_U32, "f-dsp-48-u32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 912   { M32C_F_DSP_48_S32, "f-dsp-48-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 913   { M32C_F_DSP_56_S16, "f-dsp-56-s16", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 914   { M32C_F_DSP_64_S16, "f-dsp-64-s16", 64, 32, 0, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 915   { M32C_F_BITNO16_S, "f-bitno16-S", 0, 32, 5, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 916   { M32C_F_BITNO32_PREFIXED, "f-bitno32-prefixed", 0, 32, 21, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 917   { M32C_F_BITNO32_UNPREFIXED, "f-bitno32-unprefixed", 0, 32, 13, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 918   { M32C_F_BITBASE16_U11_S, "f-bitbase16-u11-S", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 919   { M32C_F_BITBASE32_16_U11_UNPREFIXED, "f-bitbase32-16-u11-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 920   { M32C_F_BITBASE32_16_S11_UNPREFIXED, "f-bitbase32-16-s11-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 921   { M32C_F_BITBASE32_16_U19_UNPREFIXED, "f-bitbase32-16-u19-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 922   { M32C_F_BITBASE32_16_S19_UNPREFIXED, "f-bitbase32-16-s19-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 923   { M32C_F_BITBASE32_16_U27_UNPREFIXED, "f-bitbase32-16-u27-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 924   { M32C_F_BITBASE32_24_U11_PREFIXED, "f-bitbase32-24-u11-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 925   { M32C_F_BITBASE32_24_S11_PREFIXED, "f-bitbase32-24-s11-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 926   { M32C_F_BITBASE32_24_U19_PREFIXED, "f-bitbase32-24-u19-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 927   { M32C_F_BITBASE32_24_S19_PREFIXED, "f-bitbase32-24-s19-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 928   { M32C_F_BITBASE32_24_U27_PREFIXED, "f-bitbase32-24-u27-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 929   { M32C_F_LAB_5_3, "f-lab-5-3", 0, 32, 5, 3, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 930   { M32C_F_LAB32_JMP_S, "f-lab32-jmp-s", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 931   { M32C_F_LAB_8_8, "f-lab-8-8", 0, 32, 8, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 932   { M32C_F_LAB_8_16, "f-lab-8-16", 0, 32, 8, 16, { 0|A(SIGN_OPT)|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 933   { M32C_F_LAB_8_24, "f-lab-8-24", 0, 32, 8, 24, { 0|A(ABS_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 934   { M32C_F_LAB_16_8, "f-lab-16-8", 0, 32, 16, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 935   { M32C_F_LAB_24_8, "f-lab-24-8", 0, 32, 24, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 936   { M32C_F_LAB_32_8, "f-lab-32-8", 32, 32, 0, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 937   { M32C_F_LAB_40_8, "f-lab-40-8", 32, 32, 8, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 938   { M32C_F_COND16, "f-cond16", 0, 32, 12, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 939   { M32C_F_COND16J_5, "f-cond16j-5", 0, 32, 5, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 940   { M32C_F_COND32, "f-cond32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 941   { M32C_F_COND32J, "f-cond32j", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
 942   { 0, 0, 0, 0, 0, 0, {0, {0}} }
 943 };
 944
 945 #undef A
 946
 947
 948
 949 /* multi ifield declarations */
 950
 951 const CGEN_MAYBE_MULTI_IFLD M32C_F_IMM3_S_MULTI_IFIELD [];
 952 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_U16_MULTI_IFIELD [];
 953 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_S16_MULTI_IFIELD [];
 954 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_16_U24_MULTI_IFIELD [];
 955 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_U24_MULTI_IFIELD [];
 956 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_40_S32_MULTI_IFIELD [];
 957 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_U24_MULTI_IFIELD [];
 958 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_16_S32_MULTI_IFIELD [];
 959 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_S32_MULTI_IFIELD [];
 960 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_U32_MULTI_IFIELD [];
 961 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_S32_MULTI_IFIELD [];
 962 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_56_S16_MULTI_IFIELD [];
 963 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE16_U11_S_MULTI_IFIELD [];
 964 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U11_UNPREFIXED_MULTI_IFIELD [];
 965 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_S11_UNPREFIXED_MULTI_IFIELD [];
 966 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U19_UNPREFIXED_MULTI_IFIELD [];
 967 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_S19_UNPREFIXED_MULTI_IFIELD [];
 968 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U27_UNPREFIXED_MULTI_IFIELD [];
 969 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U11_PREFIXED_MULTI_IFIELD [];
 970 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_S11_PREFIXED_MULTI_IFIELD [];
 971 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U19_PREFIXED_MULTI_IFIELD [];
 972 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_S19_PREFIXED_MULTI_IFIELD [];
 973 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U27_PREFIXED_MULTI_IFIELD [];
 974 const CGEN_MAYBE_MULTI_IFLD M32C_F_LAB32_JMP_S_MULTI_IFIELD [];
 975 const CGEN_MAYBE_MULTI_IFLD M32C_F_COND32_MULTI_IFIELD [];
 976 const CGEN_MAYBE_MULTI_IFLD M32C_F_COND32J_MULTI_IFIELD [];
 977
 978
 979 /* multi ifield definitions */
 980
 981 const CGEN_MAYBE_MULTI_IFLD M32C_F_IMM3_S_MULTI_IFIELD [] =
 982 {
 983     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_2_2] } },
 984     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_7_1] } },
 985     { 0, { (const PTR) 0 } }
 986 };
 987 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_U16_MULTI_IFIELD [] =
 988 {
 989     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
 990     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
 991     { 0, { (const PTR) 0 } }
 992 };
 993 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_S16_MULTI_IFIELD [] =
 994 {
 995     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
 996     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
 997     { 0, { (const PTR) 0 } }
 998 };
 999 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_16_U24_MULTI_IFIELD [] =
1000 {
1001     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
1002     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
1003     { 0, { (const PTR) 0 } }
1004 };
1005 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_U24_MULTI_IFIELD [] =
1006 {
1007     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
1008     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U16] } },
1009     { 0, { (const PTR) 0 } }
1010 };
1011 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_40_S32_MULTI_IFIELD [] =
1012 {
1013     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U24] } },
1014     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_U8] } },
1015     { 0, { (const PTR) 0 } }
1016 };
1017 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_U24_MULTI_IFIELD [] =
1018 {
1019     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U16] } },
1020     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_U8] } },
1021     { 0, { (const PTR) 0 } }
1022 };
1023 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_16_S32_MULTI_IFIELD [] =
1024 {
1025     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
1026     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U16] } },
1027     { 0, { (const PTR) 0 } }
1028 };
1029 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_S32_MULTI_IFIELD [] =
1030 {
1031     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
1032     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U24] } },
1033     { 0, { (const PTR) 0 } }
1034 };
1035 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_U32_MULTI_IFIELD [] =
1036 {
1037     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U16] } },
1038     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_U16] } },
1039     { 0, { (const PTR) 0 } }
1040 };
1041 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_S32_MULTI_IFIELD [] =
1042 {
1043     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U16] } },
1044     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_U16] } },
1045     { 0, { (const PTR) 0 } }
1046 };
1047 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_56_S16_MULTI_IFIELD [] =
1048 {
1049     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_56_U8] } },
1050     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_U8] } },
1051     { 0, { (const PTR) 0 } }
1052 };
1053 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE16_U11_S_MULTI_IFIELD [] =
1054 {
1055     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO16_S] } },
1056     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U8] } },
1057     { 0, { (const PTR) 0 } }
1058 };
1059 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U11_UNPREFIXED_MULTI_IFIELD [] =
1060 {
1061     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } },
1062     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
1063     { 0, { (const PTR) 0 } }
1064 };
1065 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_S11_UNPREFIXED_MULTI_IFIELD [] =
1066 {
1067     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } },
1068     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S8] } },
1069     { 0, { (const PTR) 0 } }
1070 };
1071 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U19_UNPREFIXED_MULTI_IFIELD [] =
1072 {
1073     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } },
1074     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
1075     { 0, { (const PTR) 0 } }
1076 };
1077 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_S19_UNPREFIXED_MULTI_IFIELD [] =
1078 {
1079     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } },
1080     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S16] } },
1081     { 0, { (const PTR) 0 } }
1082 };
1083 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U27_UNPREFIXED_MULTI_IFIELD [] =
1084 {
1085     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } },
1086     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
1087     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
1088     { 0, { (const PTR) 0 } }
1089 };
1090 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U11_PREFIXED_MULTI_IFIELD [] =
1091 {
1092     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } },
1093     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
1094     { 0, { (const PTR) 0 } }
1095 };
1096 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_S11_PREFIXED_MULTI_IFIELD [] =
1097 {
1098     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } },
1099     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_S8] } },
1100     { 0, { (const PTR) 0 } }
1101 };
1102 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U19_PREFIXED_MULTI_IFIELD [] =
1103 {
1104     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } },
1105     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
1106     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
1107     { 0, { (const PTR) 0 } }
1108 };
1109 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_S19_PREFIXED_MULTI_IFIELD [] =
1110 {
1111     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } },
1112     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
1113     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S8] } },
1114     { 0, { (const PTR) 0 } }
1115 };
1116 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U27_PREFIXED_MULTI_IFIELD [] =
1117 {
1118     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } },
1119     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
1120     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U16] } },
1121     { 0, { (const PTR) 0 } }
1122 };
1123 const CGEN_MAYBE_MULTI_IFLD M32C_F_LAB32_JMP_S_MULTI_IFIELD [] =
1124 {
1125     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_2_2] } },
1126     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_7_1] } },
1127     { 0, { (const PTR) 0 } }
1128 };
1129 const CGEN_MAYBE_MULTI_IFLD M32C_F_COND32_MULTI_IFIELD [] =
1130 {
1131     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_9_1] } },
1132     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } },
1133     { 0, { (const PTR) 0 } }
1134 };
1135 const CGEN_MAYBE_MULTI_IFLD M32C_F_COND32J_MULTI_IFIELD [] =
1136 {
1137     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_1_3] } },
1138     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_7_1] } },
1139     { 0, { (const PTR) 0 } }
1140 };
1141
1142 /* The operand table.  */
1143
1144 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1145 #define A(a) (1 << CGEN_OPERAND_##a)
1146 #else
1147 #define A(a) (1 << CGEN_OPERAND_/**/a)
1148 #endif
1149 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1150 #define OPERAND(op) M32C_OPERAND_##op
1151 #else
1152 #define OPERAND(op) M32C_OPERAND_/**/op
1153 #endif
1154
1155 const CGEN_OPERAND m32c_cgen_operand_table[] =
1156 {
1157 /* pc: program counter */
1158   { "pc", M32C_OPERAND_PC, HW_H_PC, 0, 0,
1159     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_NIL] } },
1160     { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C) } }  },
1161 /* Src16RnQI: general register QI view */
1162   { "Src16RnQI", M32C_OPERAND_SRC16RNQI, HW_H_GR_QI, 10, 2,
1163     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_RN] } },
1164     { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
1165 /* Src16RnHI: general register QH view */
1166   { "Src16RnHI", M32C_OPERAND_SRC16RNHI, HW_H_GR_HI, 10, 2,
1167     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_RN] } },
1168     { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
1169 /* Src32RnUnprefixedQI: general register QI view */
1170   { "Src32RnUnprefixedQI", M32C_OPERAND_SRC32RNUNPREFIXEDQI, HW_H_GR_QI, 10, 2,
1171     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_UNPREFIXED_QI] } },
1172     { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
1173 /* Src32RnUnprefixedHI: general register HI view */
1174   { "Src32RnUnprefixedHI", M32C_OPERAND_SRC32RNUNPREFIXEDHI, HW_H_GR_HI, 10, 2,
1175     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_UNPREFIXED_HI] } },
1176     { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
1177 /* Src32RnUnprefixedSI: general register SI view */
1178   { "Src32RnUnprefixedSI", M32C_OPERAND_SRC32RNUNPREFIXEDSI, HW_H_GR_SI, 10, 2,
1179     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_UNPREFIXED_SI] } },
1180     { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
1181 /* Src32RnPrefixedQI: general register QI view */
1182   { "Src32RnPrefixedQI", M32C_OPERAND_SRC32RNPREFIXEDQI, HW_H_GR_QI, 18, 2,
1183     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_PREFIXED_QI] } },
1184     { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
1185 /* Src32RnPrefixedHI: general register HI view */
1186   { "Src32RnPrefixedHI", M32C_OPERAND_SRC32RNPREFIXEDHI, HW_H_GR_HI, 18, 2,
1187     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_PREFIXED_HI] } },
1188     { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
1189 /* Src32RnPrefixedSI: general register SI view */
1190   { "Src32RnPrefixedSI", M32C_OPERAND_SRC32RNPREFIXEDSI, HW_H_GR_SI, 18, 2,
1191     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_PREFIXED_SI] } },
1192     { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
1193 /* Src16An: address register */
1194   { "Src16An", M32C_OPERAND_SRC16AN, HW_H_AR, 11, 1,
1195     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_AN] } },
1196     { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
1197 /* Src16AnQI: address register QI view */
1198   { "Src16AnQI", M32C_OPERAND_SRC16ANQI, HW_H_AR_QI, 11, 1,
1199     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_AN] } },
1200     { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
1201 /* Src16AnHI: address register HI view */
1202   { "Src16AnHI", M32C_OPERAND_SRC16ANHI, HW_H_AR_HI, 11, 1,
1203     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_AN] } },
1204     { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
1205 /* Src32AnUnprefixed: address register */
1206   { "Src32AnUnprefixed", M32C_OPERAND_SRC32ANUNPREFIXED, HW_H_AR, 11, 1,
1207     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_UNPREFIXED] } },
1208     { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
1209 /* Src32AnUnprefixedQI: address register QI view */
1210   { "Src32AnUnprefixedQI", M32C_OPERAND_SRC32ANUNPREFIXEDQI, HW_H_AR_QI, 11, 1,
1211     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_UNPREFIXED] } },
1212     { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
1213 /* Src32AnUnprefixedHI: address register HI view */
1214   { "Src32AnUnprefixedHI", M32C_OPERAND_SRC32ANUNPREFIXEDHI, HW_H_AR_HI, 11, 1,
1215     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_UNPREFIXED] } },
1216     { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
1217 /* Src32AnUnprefixedSI: address register SI view */
1218   { "Src32AnUnprefixedSI", M32C_OPERAND_SRC32ANUNPREFIXEDSI, HW_H_AR, 11, 1,
1219     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_UNPREFIXED] } },
1220     { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
1221 /* Src32AnPrefixed: address register */
1222   { "Src32AnPrefixed", M32C_OPERAND_SRC32ANPREFIXED, HW_H_AR, 19, 1,
1223     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_PREFIXED] } },
1224     { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
1225 /* Src32AnPrefixedQI: address register QI view */
1226   { "Src32AnPrefixedQI", M32C_OPERAND_SRC32ANPREFIXEDQI, HW_H_AR_QI, 19, 1,
1227     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_PREFIXED] } },
1228     { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
1229 /* Src32AnPrefixedHI: address register HI view */
1230   { "Src32AnPrefixedHI", M32C_OPERAND_SRC32ANPREFIXEDHI, HW_H_AR_HI, 19, 1,
1231     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_PREFIXED] } },
1232     { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
1233 /* Src32AnPrefixedSI: address register SI view */
1234   { "Src32AnPrefixedSI", M32C_OPERAND_SRC32ANPREFIXEDSI, HW_H_AR, 19, 1,
1235     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_PREFIXED] } },
1236     { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
1237 /* Dst16RnQI: general register QI view */
1238   { "Dst16RnQI", M32C_OPERAND_DST16RNQI, HW_H_GR_QI, 14, 2,
1239     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN] } },
1240     { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
1241 /* Dst16RnHI: general register HI view */
1242   { "Dst16RnHI", M32C_OPERAND_DST16RNHI, HW_H_GR_HI, 14, 2,
1243     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN] } },
1244     { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
1245 /* Dst16RnSI: general register SI view */
1246   { "Dst16RnSI", M32C_OPERAND_DST16RNSI, HW_H_GR_SI, 14, 2,
1247     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN] } },
1248     { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
1249 /* Dst16RnExtQI: general register QI/HI view for 'ext' insns */
1250   { "Dst16RnExtQI", M32C_OPERAND_DST16RNEXTQI, HW_H_GR_EXT_QI, 14, 1,
1251     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN_EXT] } },
1252     { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
1253 /* Dst32R0QI-S: general register QI view */
1254   { "Dst32R0QI-S", M32C_OPERAND_DST32R0QI_S, HW_H_R0L, 0, 0,
1255     { 0, { (const PTR) 0 } },
1256     { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
1257 /* Dst32R0HI-S: general register HI view */
1258   { "Dst32R0HI-S", M32C_OPERAND_DST32R0HI_S, HW_H_R0, 0, 0,
1259     { 0, { (const PTR) 0 } },
1260     { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
1261 /* Dst32RnUnprefixedQI: general register QI view */
1262   { "Dst32RnUnprefixedQI", M32C_OPERAND_DST32RNUNPREFIXEDQI, HW_H_GR_QI, 8, 2,
1263     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_UNPREFIXED_QI] } },
1264     { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
1265 /* Dst32RnUnprefixedHI: general register HI view */
1266   { "Dst32RnUnprefixedHI", M32C_OPERAND_DST32RNUNPREFIXEDHI, HW_H_GR_HI, 8, 2,
1267     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_UNPREFIXED_HI] } },
1268     { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
1269 /* Dst32RnUnprefixedSI: general register SI view */
1270   { "Dst32RnUnprefixedSI", M32C_OPERAND_DST32RNUNPREFIXEDSI, HW_H_GR_SI, 8, 2,
1271     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_UNPREFIXED_SI] } },
1272     { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
1273 /* Dst32RnExtUnprefixedQI: general register QI view */
1274   { "Dst32RnExtUnprefixedQI", M32C_OPERAND_DST32RNEXTUNPREFIXEDQI, HW_H_GR_EXT_QI, 9, 1,
1275     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_EXT_UNPREFIXED] } },
1276     { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
1277 /* Dst32RnExtUnprefixedHI: general register HI view */
1278   { "Dst32RnExtUnprefixedHI", M32C_OPERAND_DST32RNEXTUNPREFIXEDHI, HW_H_GR_EXT_HI, 9, 1,
1279     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_EXT_UNPREFIXED] } },
1280     { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
1281 /* Dst32RnPrefixedQI: general register QI view */
1282   { "Dst32RnPrefixedQI", M32C_OPERAND_DST32RNPREFIXEDQI, HW_H_GR_QI, 16, 2,
1283     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_PREFIXED_QI] } },
1284     { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
1285 /* Dst32RnPrefixedHI: general register HI view */
1286   { "Dst32RnPrefixedHI", M32C_OPERAND_DST32RNPREFIXEDHI, HW_H_GR_HI, 16, 2,
1287     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_PREFIXED_HI] } },
1288     { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
1289 /* Dst32RnPrefixedSI: general register SI view */
1290   { "Dst32RnPrefixedSI", M32C_OPERAND_DST32RNPREFIXEDSI, HW_H_GR_SI, 16, 2,
1291     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_PREFIXED_SI] } },
1292     { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
1293 /* Dst16RnQI-S: general register QI view */
1294   { "Dst16RnQI-S", M32C_OPERAND_DST16RNQI_S, HW_H_R0L_R0H, 5, 1,
1295     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN_QI_S] } },
1296     { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
1297 /* Dst16AnQI-S: address register QI view */
1298   { "Dst16AnQI-S", M32C_OPERAND_DST16ANQI_S, HW_H_AR_QI, 5, 1,
1299     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN_QI_S] } },
1300     { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
1301 /* Bit16Rn: general register bit view */
1302   { "Bit16Rn", M32C_OPERAND_BIT16RN, HW_H_GR_HI, 14, 2,
1303     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN] } },
1304     { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
1305 /* Bit32RnPrefixed: general register bit view */
1306   { "Bit32RnPrefixed", M32C_OPERAND_BIT32RNPREFIXED, HW_H_GR_QI, 16, 2,
1307     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_PREFIXED_QI] } },
1308     { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
1309 /* Bit32RnUnprefixed: general register bit view */
1310   { "Bit32RnUnprefixed", M32C_OPERAND_BIT32RNUNPREFIXED, HW_H_GR_QI, 8, 2,
1311     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_UNPREFIXED_QI] } },
1312     { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
1313 /* R0: r0 */
1314   { "R0", M32C_OPERAND_R0, HW_H_R0, 0, 0,
1315     { 0, { (const PTR) 0 } },
1316     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1317 /* R1: r1 */
1318   { "R1", M32C_OPERAND_R1, HW_H_R1, 0, 0,
1319     { 0, { (const PTR) 0 } },
1320     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1321 /* R2: r2 */
1322   { "R2", M32C_OPERAND_R2, HW_H_R2, 0, 0,
1323     { 0, { (const PTR) 0 } },
1324     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1325 /* R3: r3 */
1326   { "R3", M32C_OPERAND_R3, HW_H_R3, 0, 0,
1327     { 0, { (const PTR) 0 } },
1328     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1329 /* R0l: r0l */
1330   { "R0l", M32C_OPERAND_R0L, HW_H_R0L, 0, 0,
1331     { 0, { (const PTR) 0 } },
1332     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1333 /* R0h: r0h */
1334   { "R0h", M32C_OPERAND_R0H, HW_H_R0H, 0, 0,
1335     { 0, { (const PTR) 0 } },
1336     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1337 /* R2R0: r2r0 */
1338   { "R2R0", M32C_OPERAND_R2R0, HW_H_R2R0, 0, 0,
1339     { 0, { (const PTR) 0 } },
1340     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1341 /* R3R1: r3r1 */
1342   { "R3R1", M32C_OPERAND_R3R1, HW_H_R3R1, 0, 0,
1343     { 0, { (const PTR) 0 } },
1344     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1345 /* R1R2R0: r1r2r0 */
1346   { "R1R2R0", M32C_OPERAND_R1R2R0, HW_H_R1R2R0, 0, 0,
1347     { 0, { (const PTR) 0 } },
1348     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1349 /* Dst16An: address register */
1350   { "Dst16An", M32C_OPERAND_DST16AN, HW_H_AR, 15, 1,
1351     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } },
1352     { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
1353 /* Dst16AnQI: address register QI view */
1354   { "Dst16AnQI", M32C_OPERAND_DST16ANQI, HW_H_AR_QI, 15, 1,
1355     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } },
1356     { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
1357 /* Dst16AnHI: address register HI view */
1358   { "Dst16AnHI", M32C_OPERAND_DST16ANHI, HW_H_AR_HI, 15, 1,
1359     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } },
1360     { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
1361 /* Dst16AnSI: address register SI view */
1362   { "Dst16AnSI", M32C_OPERAND_DST16ANSI, HW_H_AR_SI, 15, 1,
1363     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } },
1364     { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
1365 /* Dst16An-S: address register HI view */
1366   { "Dst16An-S", M32C_OPERAND_DST16AN_S, HW_H_AR_HI, 4, 1,
1367     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN_S] } },
1368     { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
1369 /* Dst32AnUnprefixed: address register */
1370   { "Dst32AnUnprefixed", M32C_OPERAND_DST32ANUNPREFIXED, HW_H_AR, 9, 1,
1371     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
1372     { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
1373 /* Dst32AnUnprefixedQI: address register QI view */
1374   { "Dst32AnUnprefixedQI", M32C_OPERAND_DST32ANUNPREFIXEDQI, HW_H_AR_QI, 9, 1,
1375     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
1376     { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
1377 /* Dst32AnUnprefixedHI: address register HI view */
1378   { "Dst32AnUnprefixedHI", M32C_OPERAND_DST32ANUNPREFIXEDHI, HW_H_AR_HI, 9, 1,
1379     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
1380     { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
1381 /* Dst32AnUnprefixedSI: address register SI view */
1382   { "Dst32AnUnprefixedSI", M32C_OPERAND_DST32ANUNPREFIXEDSI, HW_H_AR, 9, 1,
1383     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
1384     { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
1385 /* Dst32AnExtUnprefixed: address register */
1386   { "Dst32AnExtUnprefixed", M32C_OPERAND_DST32ANEXTUNPREFIXED, HW_H_AR, 9, 1,
1387     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
1388     { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
1389 /* Dst32AnPrefixed: address register */
1390   { "Dst32AnPrefixed", M32C_OPERAND_DST32ANPREFIXED, HW_H_AR, 17, 1,
1391     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } },
1392     { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
1393 /* Dst32AnPrefixedQI: address register QI view */
1394   { "Dst32AnPrefixedQI", M32C_OPERAND_DST32ANPREFIXEDQI, HW_H_AR_QI, 17, 1,
1395     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } },
1396     { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
1397 /* Dst32AnPrefixedHI: address register HI view */
1398   { "Dst32AnPrefixedHI", M32C_OPERAND_DST32ANPREFIXEDHI, HW_H_AR_HI, 17, 1,
1399     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } },
1400     { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
1401 /* Dst32AnPrefixedSI: address register SI view */
1402   { "Dst32AnPrefixedSI", M32C_OPERAND_DST32ANPREFIXEDSI, HW_H_AR, 17, 1,
1403     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } },
1404     { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
1405 /* Bit16An: address register bit view */
1406   { "Bit16An", M32C_OPERAND_BIT16AN, HW_H_AR, 15, 1,
1407     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } },
1408     { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
1409 /* Bit32AnPrefixed: address register bit */
1410   { "Bit32AnPrefixed", M32C_OPERAND_BIT32ANPREFIXED, HW_H_AR, 17, 1,
1411     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } },
1412     { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
1413 /* Bit32AnUnprefixed: address register bit */
1414   { "Bit32AnUnprefixed", M32C_OPERAND_BIT32ANUNPREFIXED, HW_H_AR, 9, 1,
1415     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
1416     { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
1417 /* A0: a0 */
1418   { "A0", M32C_OPERAND_A0, HW_H_A0, 0, 0,
1419     { 0, { (const PTR) 0 } },
1420     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1421 /* A1: a1 */
1422   { "A1", M32C_OPERAND_A1, HW_H_A1, 0, 0,
1423     { 0, { (const PTR) 0 } },
1424     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1425 /* A1A0: a1a0 */
1426   { "A1A0", M32C_OPERAND_A1A0, HW_H_AR_SI, 0, 0,
1427     { 0, { (const PTR) 0 } },
1428     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1429 /* sb: SB register */
1430   { "sb", M32C_OPERAND_SB, HW_H_SB, 0, 0,
1431     { 0, { (const PTR) 0 } },
1432     { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1433 /* fb: FB register */
1434   { "fb", M32C_OPERAND_FB, HW_H_FB, 0, 0,
1435     { 0, { (const PTR) 0 } },
1436     { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1437 /* sp: SP register */
1438   { "sp", M32C_OPERAND_SP, HW_H_SP, 0, 0,
1439     { 0, { (const PTR) 0 } },
1440     { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1441 /* SrcDst16-r0l-r0h-S-normal: r0l/r0h pair */
1442   { "SrcDst16-r0l-r0h-S-normal", M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL, HW_H_SINT, 5, 1,
1443     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_5_1] } },
1444     { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
1445 /* Regsetpop: popm regset */
1446   { "Regsetpop", M32C_OPERAND_REGSETPOP, HW_H_UINT, 8, 8,
1447     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_8_8] } },
1448     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1449 /* Regsetpush: pushm regset */
1450   { "Regsetpush", M32C_OPERAND_REGSETPUSH, HW_H_UINT, 8, 8,
1451     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_8_8] } },
1452     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1453 /* Rn16-push-S: r0[lh] */
1454   { "Rn16-push-S", M32C_OPERAND_RN16_PUSH_S, HW_H_GR_QI, 4, 1,
1455     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_4_1] } },
1456     { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
1457 /* An16-push-S: a[01] */
1458   { "An16-push-S", M32C_OPERAND_AN16_PUSH_S, HW_H_AR_HI, 4, 1,
1459     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_4_1] } },
1460     { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } }  },
1461 /* Dsp-8-u6: unsigned 6 bit displacement at offset 8 bits */
1462   { "Dsp-8-u6", M32C_OPERAND_DSP_8_U6, HW_H_UINT, 8, 6,
1463     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U6] } },
1464     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1465 /* Dsp-8-u8: unsigned 8 bit displacement at offset 8 bits */
1466   { "Dsp-8-u8", M32C_OPERAND_DSP_8_U8, HW_H_UINT, 8, 8,
1467     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U8] } },
1468     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1469 /* Dsp-8-u16: unsigned 16 bit displacement at offset 8 bits */
1470   { "Dsp-8-u16", M32C_OPERAND_DSP_8_U16, HW_H_UINT, 8, 16,
1471     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U16] } },
1472     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1473 /* Dsp-8-s8: signed 8 bit displacement at offset 8 bits */
1474   { "Dsp-8-s8", M32C_OPERAND_DSP_8_S8, HW_H_SINT, 8, 8,
1475     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_S8] } },
1476     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1477 /* Dsp-8-u24: unsigned 24 bit displacement at offset 8 bits */
1478   { "Dsp-8-u24", M32C_OPERAND_DSP_8_U24, HW_H_UINT, 8, 24,
1479     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U24] } },
1480     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1481 /* Dsp-10-u6: unsigned 6 bit displacement at offset 10 bits */
1482   { "Dsp-10-u6", M32C_OPERAND_DSP_10_U6, HW_H_UINT, 10, 6,
1483     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_10_U6] } },
1484     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1485 /* Dsp-16-u8: unsigned 8 bit displacement at offset 16 bits */
1486   { "Dsp-16-u8", M32C_OPERAND_DSP_16_U8, HW_H_UINT, 16, 8,
1487     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
1488     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1489 /* Dsp-16-u16: unsigned 16 bit displacement at offset 16 bits */
1490   { "Dsp-16-u16", M32C_OPERAND_DSP_16_U16, HW_H_UINT, 16, 16,
1491     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
1492     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1493 /* Dsp-16-u20: unsigned 20 bit displacement at offset 16 bits */
1494   { "Dsp-16-u20", M32C_OPERAND_DSP_16_U20, HW_H_UINT, 0, 24,
1495     { 2, { (const PTR) &M32C_F_DSP_16_U24_MULTI_IFIELD[0] } },
1496     { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1497 /* Dsp-16-u24: unsigned 24 bit displacement at offset 16 bits */
1498   { "Dsp-16-u24", M32C_OPERAND_DSP_16_U24, HW_H_UINT, 0, 24,
1499     { 2, { (const PTR) &M32C_F_DSP_16_U24_MULTI_IFIELD[0] } },
1500     { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1501 /* Dsp-16-s8: signed 8 bit displacement at offset 16 bits */
1502   { "Dsp-16-s8", M32C_OPERAND_DSP_16_S8, HW_H_SINT, 16, 8,
1503     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S8] } },
1504     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1505 /* Dsp-16-s16: signed 16 bit displacement at offset 16 bits */
1506   { "Dsp-16-s16", M32C_OPERAND_DSP_16_S16, HW_H_SINT, 16, 16,
1507     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S16] } },
1508     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1509 /* Dsp-24-u8: unsigned 8 bit displacement at offset 24 bits */
1510   { "Dsp-24-u8", M32C_OPERAND_DSP_24_U8, HW_H_UINT, 24, 8,
1511     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
1512     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1513 /* Dsp-24-u16: unsigned 16 bit displacement at offset 24 bits */
1514   { "Dsp-24-u16", M32C_OPERAND_DSP_24_U16, HW_H_UINT, 0, 16,
1515     { 2, { (const PTR) &M32C_F_DSP_24_U16_MULTI_IFIELD[0] } },
1516     { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1517 /* Dsp-24-u20: unsigned 20 bit displacement at offset 24 bits */
1518   { "Dsp-24-u20", M32C_OPERAND_DSP_24_U20, HW_H_UINT, 0, 24,
1519     { 2, { (const PTR) &M32C_F_DSP_24_U24_MULTI_IFIELD[0] } },
1520     { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1521 /* Dsp-24-u24: unsigned 24 bit displacement at offset 24 bits */
1522   { "Dsp-24-u24", M32C_OPERAND_DSP_24_U24, HW_H_UINT, 0, 24,
1523     { 2, { (const PTR) &M32C_F_DSP_24_U24_MULTI_IFIELD[0] } },
1524     { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1525 /* Dsp-24-s8: signed 8 bit displacement at offset 24 bits */
1526   { "Dsp-24-s8", M32C_OPERAND_DSP_24_S8, HW_H_SINT, 24, 8,
1527     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_S8] } },
1528     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1529 /* Dsp-24-s16: signed 16 bit displacement at offset 24 bits */
1530   { "Dsp-24-s16", M32C_OPERAND_DSP_24_S16, HW_H_SINT, 0, 16,
1531     { 2, { (const PTR) &M32C_F_DSP_24_S16_MULTI_IFIELD[0] } },
1532     { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1533 /* Dsp-32-u8: unsigned 8 bit displacement at offset 32 bits */
1534   { "Dsp-32-u8", M32C_OPERAND_DSP_32_U8, HW_H_UINT, 0, 8,
1535     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
1536     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1537 /* Dsp-32-u16: unsigned 16 bit displacement at offset 32 bits */
1538   { "Dsp-32-u16", M32C_OPERAND_DSP_32_U16, HW_H_UINT, 0, 16,
1539     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U16] } },
1540     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1541 /* Dsp-32-u24: unsigned 24 bit displacement at offset 32 bits */
1542   { "Dsp-32-u24", M32C_OPERAND_DSP_32_U24, HW_H_UINT, 0, 24,
1543     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U24] } },
1544     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1545 /* Dsp-32-u20: unsigned 20 bit displacement at offset 32 bits */
1546   { "Dsp-32-u20", M32C_OPERAND_DSP_32_U20, HW_H_UINT, 0, 24,
1547     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U24] } },
1548     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1549 /* Dsp-32-s8: signed 8 bit displacement at offset 32 bits */
1550   { "Dsp-32-s8", M32C_OPERAND_DSP_32_S8, HW_H_SINT, 0, 8,
1551     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S8] } },
1552     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1553 /* Dsp-32-s16: signed 16 bit displacement at offset 32 bits */
1554   { "Dsp-32-s16", M32C_OPERAND_DSP_32_S16, HW_H_SINT, 0, 16,
1555     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S16] } },
1556     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1557 /* Dsp-40-u8: unsigned 8 bit displacement at offset 40 bits */
1558   { "Dsp-40-u8", M32C_OPERAND_DSP_40_U8, HW_H_UINT, 8, 8,
1559     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U8] } },
1560     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1561 /* Dsp-40-s8: signed 8 bit displacement at offset 40 bits */
1562   { "Dsp-40-s8", M32C_OPERAND_DSP_40_S8, HW_H_SINT, 8, 8,
1563     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S8] } },
1564     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1565 /* Dsp-40-u16: unsigned 16 bit displacement at offset 40 bits */
1566   { "Dsp-40-u16", M32C_OPERAND_DSP_40_U16, HW_H_UINT, 8, 16,
1567     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U16] } },
1568     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1569 /* Dsp-40-s16: signed 16 bit displacement at offset 40 bits */
1570   { "Dsp-40-s16", M32C_OPERAND_DSP_40_S16, HW_H_SINT, 8, 16,
1571     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S16] } },
1572     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1573 /* Dsp-40-u24: unsigned 24 bit displacement at offset 40 bits */
1574   { "Dsp-40-u24", M32C_OPERAND_DSP_40_U24, HW_H_UINT, 8, 24,
1575     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U24] } },
1576     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1577 /* Dsp-48-u8: unsigned 8 bit displacement at offset 48 bits */
1578   { "Dsp-48-u8", M32C_OPERAND_DSP_48_U8, HW_H_UINT, 16, 8,
1579     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U8] } },
1580     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1581 /* Dsp-48-s8: signed 8 bit displacement at offset 48 bits */
1582   { "Dsp-48-s8", M32C_OPERAND_DSP_48_S8, HW_H_SINT, 16, 8,
1583     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S8] } },
1584     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1585 /* Dsp-48-u16: unsigned 16 bit displacement at offset 48 bits */
1586   { "Dsp-48-u16", M32C_OPERAND_DSP_48_U16, HW_H_UINT, 16, 16,
1587     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U16] } },
1588     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1589 /* Dsp-48-s16: signed 16 bit displacement at offset 48 bits */
1590   { "Dsp-48-s16", M32C_OPERAND_DSP_48_S16, HW_H_SINT, 16, 16,
1591     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S16] } },
1592     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1593 /* Dsp-48-u24: unsigned 24 bit displacement at offset 48 bits */
1594   { "Dsp-48-u24", M32C_OPERAND_DSP_48_U24, HW_H_UINT, 0, 24,
1595     { 2, { (const PTR) &M32C_F_DSP_48_U24_MULTI_IFIELD[0] } },
1596     { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1597 /* Imm-8-s4: signed 4 bit immediate at offset 8 bits */
1598   { "Imm-8-s4", M32C_OPERAND_IMM_8_S4, HW_H_SINT, 8, 4,
1599     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_8_S4] } },
1600     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1601 /* Imm-sh-8-s4: signed 4 bit shift immediate at offset 8 bits */
1602   { "Imm-sh-8-s4", M32C_OPERAND_IMM_SH_8_S4, HW_H_SHIMM, 8, 4,
1603     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_8_S4] } },
1604     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1605 /* Imm-8-QI: signed 8 bit immediate at offset 8 bits */
1606   { "Imm-8-QI", M32C_OPERAND_IMM_8_QI, HW_H_SINT, 8, 8,
1607     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_S8] } },
1608     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1609 /* Imm-8-HI: signed 16 bit immediate at offset 8 bits */
1610   { "Imm-8-HI", M32C_OPERAND_IMM_8_HI, HW_H_SINT, 8, 16,
1611     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_S16] } },
1612     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1613 /* Imm-12-s4: signed 4 bit immediate at offset 12 bits */
1614   { "Imm-12-s4", M32C_OPERAND_IMM_12_S4, HW_H_SINT, 12, 4,
1615     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_12_S4] } },
1616     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1617 /* Imm-sh-12-s4: signed 4 bit shift immediate at offset 12 bits */
1618   { "Imm-sh-12-s4", M32C_OPERAND_IMM_SH_12_S4, HW_H_SHIMM, 12, 4,
1619     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_12_S4] } },
1620     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1621 /* Imm-13-u3: signed 3 bit immediate at offset 13 bits */
1622   { "Imm-13-u3", M32C_OPERAND_IMM_13_U3, HW_H_SINT, 13, 3,
1623     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_13_U3] } },
1624     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1625 /* Imm-20-s4: signed 4 bit immediate at offset 20 bits */
1626   { "Imm-20-s4", M32C_OPERAND_IMM_20_S4, HW_H_SINT, 20, 4,
1627     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_20_S4] } },
1628     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1629 /* Imm-sh-20-s4: signed 4 bit shift immediate at offset 12 bits */
1630   { "Imm-sh-20-s4", M32C_OPERAND_IMM_SH_20_S4, HW_H_SHIMM, 20, 4,
1631     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_20_S4] } },
1632     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1633 /* Imm-16-QI: signed 8 bit immediate at offset 16 bits */
1634   { "Imm-16-QI", M32C_OPERAND_IMM_16_QI, HW_H_SINT, 16, 8,
1635     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S8] } },
1636     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1637 /* Imm-16-HI: signed 16 bit immediate at offset 16 bits */
1638   { "Imm-16-HI", M32C_OPERAND_IMM_16_HI, HW_H_SINT, 16, 16,
1639     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S16] } },
1640     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1641 /* Imm-16-SI: signed 32 bit immediate at offset 16 bits */
1642   { "Imm-16-SI", M32C_OPERAND_IMM_16_SI, HW_H_SINT, 0, 32,
1643     { 2, { (const PTR) &M32C_F_DSP_16_S32_MULTI_IFIELD[0] } },
1644     { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1645 /* Imm-24-QI: signed 8 bit immediate at offset 24 bits */
1646   { "Imm-24-QI", M32C_OPERAND_IMM_24_QI, HW_H_SINT, 24, 8,
1647     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_S8] } },
1648     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1649 /* Imm-24-HI: signed 16 bit immediate at offset 24 bits */
1650   { "Imm-24-HI", M32C_OPERAND_IMM_24_HI, HW_H_SINT, 0, 16,
1651     { 2, { (const PTR) &M32C_F_DSP_24_S16_MULTI_IFIELD[0] } },
1652     { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1653 /* Imm-24-SI: signed 32 bit immediate at offset 24 bits */
1654   { "Imm-24-SI", M32C_OPERAND_IMM_24_SI, HW_H_SINT, 0, 32,
1655     { 2, { (const PTR) &M32C_F_DSP_24_S32_MULTI_IFIELD[0] } },
1656     { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1657 /* Imm-32-QI: signed 8 bit immediate at offset 32 bits */
1658   { "Imm-32-QI", M32C_OPERAND_IMM_32_QI, HW_H_SINT, 0, 8,
1659     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S8] } },
1660     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1661 /* Imm-32-SI: signed 32 bit immediate at offset 32 bits */
1662   { "Imm-32-SI", M32C_OPERAND_IMM_32_SI, HW_H_SINT, 0, 32,
1663     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S32] } },
1664     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1665 /* Imm-32-HI: signed 16 bit immediate at offset 32 bits */
1666   { "Imm-32-HI", M32C_OPERAND_IMM_32_HI, HW_H_SINT, 0, 16,
1667     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S16] } },
1668     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1669 /* Imm-40-QI: signed 8 bit immediate at offset 40 bits */
1670   { "Imm-40-QI", M32C_OPERAND_IMM_40_QI, HW_H_SINT, 8, 8,
1671     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S8] } },
1672     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1673 /* Imm-40-HI: signed 16 bit immediate at offset 40 bits */
1674   { "Imm-40-HI", M32C_OPERAND_IMM_40_HI, HW_H_SINT, 8, 16,
1675     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S16] } },
1676     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1677 /* Imm-40-SI: signed 32 bit immediate at offset 40 bits */
1678   { "Imm-40-SI", M32C_OPERAND_IMM_40_SI, HW_H_SINT, 0, 32,
1679     { 2, { (const PTR) &M32C_F_DSP_40_S32_MULTI_IFIELD[0] } },
1680     { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1681 /* Imm-48-QI: signed 8 bit immediate at offset 48 bits */
1682   { "Imm-48-QI", M32C_OPERAND_IMM_48_QI, HW_H_SINT, 16, 8,
1683     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S8] } },
1684     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1685 /* Imm-48-HI: signed 16 bit immediate at offset 48 bits */
1686   { "Imm-48-HI", M32C_OPERAND_IMM_48_HI, HW_H_SINT, 16, 16,
1687     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S16] } },
1688     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1689 /* Imm-48-SI: signed 32 bit immediate at offset 48 bits */
1690   { "Imm-48-SI", M32C_OPERAND_IMM_48_SI, HW_H_SINT, 0, 32,
1691     { 2, { (const PTR) &M32C_F_DSP_48_S32_MULTI_IFIELD[0] } },
1692     { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1693 /* Imm-56-QI: signed 8 bit immediate at offset 56 bits */
1694   { "Imm-56-QI", M32C_OPERAND_IMM_56_QI, HW_H_SINT, 24, 8,
1695     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_56_S8] } },
1696     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1697 /* Imm-56-HI: signed 16 bit immediate at offset 56 bits */
1698   { "Imm-56-HI", M32C_OPERAND_IMM_56_HI, HW_H_SINT, 0, 16,
1699     { 2, { (const PTR) &M32C_F_DSP_56_S16_MULTI_IFIELD[0] } },
1700     { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1701 /* Imm-64-HI: signed 16 bit immediate at offset 64 bits */
1702   { "Imm-64-HI", M32C_OPERAND_IMM_64_HI, HW_H_SINT, 0, 16,
1703     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_S16] } },
1704     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1705 /* Imm1-S: signed 1 bit immediate for short format binary insns */
1706   { "Imm1-S", M32C_OPERAND_IMM1_S, HW_H_SINT, 2, 1,
1707     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM1_S] } },
1708     { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
1709 /* Imm3-S: signed 3 bit immediate for short format binary insns */
1710   { "Imm3-S", M32C_OPERAND_IMM3_S, HW_H_SINT, 2, 3,
1711     { 2, { (const PTR) &M32C_F_IMM3_S_MULTI_IFIELD[0] } },
1712     { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
1713 /* Bitno16R: bit number for indexing registers */
1714   { "Bitno16R", M32C_OPERAND_BITNO16R, HW_H_UINT, 16, 8,
1715     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
1716     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }  },
1717 /* Bitno32Prefixed: bit number for indexing objects */
1718   { "Bitno32Prefixed", M32C_OPERAND_BITNO32PREFIXED, HW_H_UINT, 21, 3,
1719     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } },
1720     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
1721 /* Bitno32Unprefixed: bit number for indexing objects */
1722   { "Bitno32Unprefixed", M32C_OPERAND_BITNO32UNPREFIXED, HW_H_UINT, 13, 3,
1723     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } },
1724     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
1725 /* BitBase16-16-u8: unsigned bit,base:8 at offset 16for m16c */
1726   { "BitBase16-16-u8", M32C_OPERAND_BITBASE16_16_U8, HW_H_UINT, 16, 8,
1727     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
1728     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }  },
1729 /* BitBase16-16-s8: signed bit,base:8 at offset 16for m16c */
1730   { "BitBase16-16-s8", M32C_OPERAND_BITBASE16_16_S8, HW_H_SINT, 16, 8,
1731     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S8] } },
1732     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }  },
1733 /* BitBase16-16-u16: unsigned bit,base:16 at offset 16 for m16c */
1734   { "BitBase16-16-u16", M32C_OPERAND_BITBASE16_16_U16, HW_H_UINT, 16, 16,
1735     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
1736     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }  },
1737 /* BitBase16-8-u11-S: signed bit,base:11 at offset 16 for m16c */
1738   { "BitBase16-8-u11-S", M32C_OPERAND_BITBASE16_8_U11_S, HW_H_UINT, 5, 11,
1739     { 2, { (const PTR) &M32C_F_BITBASE16_U11_S_MULTI_IFIELD[0] } },
1740     { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C) } }  },
1741 /* BitBase32-16-u11-Unprefixed: unsigned bit,base:11 at offset 16 for m32c */
1742   { "BitBase32-16-u11-Unprefixed", M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED, HW_H_UINT, 13, 11,
1743     { 2, { (const PTR) &M32C_F_BITBASE32_16_U11_UNPREFIXED_MULTI_IFIELD[0] } },
1744     { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
1745 /* BitBase32-16-s11-Unprefixed: signed bit,base:11 at offset 16 for m32c */
1746   { "BitBase32-16-s11-Unprefixed", M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED, HW_H_SINT, 13, 11,
1747     { 2, { (const PTR) &M32C_F_BITBASE32_16_S11_UNPREFIXED_MULTI_IFIELD[0] } },
1748     { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
1749 /* BitBase32-16-u19-Unprefixed: unsigned bit,base:19 at offset 16 for m32c */
1750   { "BitBase32-16-u19-Unprefixed", M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED, HW_H_UINT, 13, 19,
1751     { 2, { (const PTR) &M32C_F_BITBASE32_16_U19_UNPREFIXED_MULTI_IFIELD[0] } },
1752     { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
1753 /* BitBase32-16-s19-Unprefixed: signed bit,base:19 at offset 16 for m32c */
1754   { "BitBase32-16-s19-Unprefixed", M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED, HW_H_SINT, 13, 19,
1755     { 2, { (const PTR) &M32C_F_BITBASE32_16_S19_UNPREFIXED_MULTI_IFIELD[0] } },
1756     { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
1757 /* BitBase32-16-u27-Unprefixed: unsigned bit,base:27 at offset 16 for m32c */
1758   { "BitBase32-16-u27-Unprefixed", M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED, HW_H_UINT, 0, 27,
1759     { 3, { (const PTR) &M32C_F_BITBASE32_16_U27_UNPREFIXED_MULTI_IFIELD[0] } },
1760     { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
1761 /* BitBase32-24-u11-Prefixed: unsigned bit,base:11 at offset 24 for m32c */
1762   { "BitBase32-24-u11-Prefixed", M32C_OPERAND_BITBASE32_24_U11_PREFIXED, HW_H_UINT, 21, 11,
1763     { 2, { (const PTR) &M32C_F_BITBASE32_24_U11_PREFIXED_MULTI_IFIELD[0] } },
1764     { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
1765 /* BitBase32-24-s11-Prefixed: signed bit,base:11 at offset 24 for m32c */
1766   { "BitBase32-24-s11-Prefixed", M32C_OPERAND_BITBASE32_24_S11_PREFIXED, HW_H_SINT, 21, 11,
1767     { 2, { (const PTR) &M32C_F_BITBASE32_24_S11_PREFIXED_MULTI_IFIELD[0] } },
1768     { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
1769 /* BitBase32-24-u19-Prefixed: unsigned bit,base:19 at offset 24 for m32c */
1770   { "BitBase32-24-u19-Prefixed", M32C_OPERAND_BITBASE32_24_U19_PREFIXED, HW_H_UINT, 0, 19,
1771     { 3, { (const PTR) &M32C_F_BITBASE32_24_U19_PREFIXED_MULTI_IFIELD[0] } },
1772     { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
1773 /* BitBase32-24-s19-Prefixed: signed bit,base:19 at offset 24 for m32c */
1774   { "BitBase32-24-s19-Prefixed", M32C_OPERAND_BITBASE32_24_S19_PREFIXED, HW_H_SINT, 0, 19,
1775     { 3, { (const PTR) &M32C_F_BITBASE32_24_S19_PREFIXED_MULTI_IFIELD[0] } },
1776     { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
1777 /* BitBase32-24-u27-Prefixed: unsigned bit,base:27 at offset 24 for m32c */
1778   { "BitBase32-24-u27-Prefixed", M32C_OPERAND_BITBASE32_24_U27_PREFIXED, HW_H_UINT, 0, 27,
1779     { 3, { (const PTR) &M32C_F_BITBASE32_24_U27_PREFIXED_MULTI_IFIELD[0] } },
1780     { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
1781 /* Lab-5-3: 3 bit label */
1782   { "Lab-5-3", M32C_OPERAND_LAB_5_3, HW_H_IADDR, 5, 3,
1783     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_5_3] } },
1784     { 0|A(RELAX)|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1785 /* Lab32-jmp-s: 3 bit label */
1786   { "Lab32-jmp-s", M32C_OPERAND_LAB32_JMP_S, HW_H_IADDR, 2, 3,
1787     { 2, { (const PTR) &M32C_F_LAB32_JMP_S_MULTI_IFIELD[0] } },
1788     { 0|A(RELAX)|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1789 /* Lab-8-8: 8 bit label */
1790   { "Lab-8-8", M32C_OPERAND_LAB_8_8, HW_H_IADDR, 8, 8,
1791     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_8_8] } },
1792     { 0|A(RELAX)|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1793 /* Lab-8-16: 16 bit label */
1794   { "Lab-8-16", M32C_OPERAND_LAB_8_16, HW_H_IADDR, 8, 16,
1795     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_8_16] } },
1796     { 0|A(RELAX)|A(SIGN_OPT)|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1797 /* Lab-8-24: 24 bit label */
1798   { "Lab-8-24", M32C_OPERAND_LAB_8_24, HW_H_IADDR, 8, 24,
1799     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_8_24] } },
1800     { 0|A(ABS_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1801 /* Lab-16-8: 8 bit label */
1802   { "Lab-16-8", M32C_OPERAND_LAB_16_8, HW_H_IADDR, 16, 8,
1803     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_16_8] } },
1804     { 0|A(RELAX)|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1805 /* Lab-24-8: 8 bit label */
1806   { "Lab-24-8", M32C_OPERAND_LAB_24_8, HW_H_IADDR, 24, 8,
1807     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_24_8] } },
1808     { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1809 /* Lab-32-8: 8 bit label */
1810   { "Lab-32-8", M32C_OPERAND_LAB_32_8, HW_H_IADDR, 0, 8,
1811     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_32_8] } },
1812     { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1813 /* Lab-40-8: 8 bit label */
1814   { "Lab-40-8", M32C_OPERAND_LAB_40_8, HW_H_IADDR, 8, 8,
1815     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_40_8] } },
1816     { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1817 /* sbit: negative    bit */
1818   { "sbit", M32C_OPERAND_SBIT, HW_H_SBIT, 0, 0,
1819     { 0, { (const PTR) 0 } },
1820     { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1821 /* obit: overflow    bit */
1822   { "obit", M32C_OPERAND_OBIT, HW_H_OBIT, 0, 0,
1823     { 0, { (const PTR) 0 } },
1824     { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1825 /* zbit: zero        bit */
1826   { "zbit", M32C_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
1827     { 0, { (const PTR) 0 } },
1828     { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1829 /* cbit: carry       bit */
1830   { "cbit", M32C_OPERAND_CBIT, HW_H_CBIT, 0, 0,
1831     { 0, { (const PTR) 0 } },
1832     { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1833 /* ubit: stack ptr select bit */
1834   { "ubit", M32C_OPERAND_UBIT, HW_H_UBIT, 0, 0,
1835     { 0, { (const PTR) 0 } },
1836     { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1837 /* ibit: interrupt enable bit */
1838   { "ibit", M32C_OPERAND_IBIT, HW_H_IBIT, 0, 0,
1839     { 0, { (const PTR) 0 } },
1840     { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1841 /* bbit: reg bank select bit */
1842   { "bbit", M32C_OPERAND_BBIT, HW_H_BBIT, 0, 0,
1843     { 0, { (const PTR) 0 } },
1844     { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1845 /* dbit: debug       bit */
1846   { "dbit", M32C_OPERAND_DBIT, HW_H_DBIT, 0, 0,
1847     { 0, { (const PTR) 0 } },
1848     { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1849 /* cond16-16: condition */
1850   { "cond16-16", M32C_OPERAND_COND16_16, HW_H_COND16, 16, 8,
1851     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
1852     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }  },
1853 /* cond16-24: condition */
1854   { "cond16-24", M32C_OPERAND_COND16_24, HW_H_COND16, 24, 8,
1855     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
1856     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }  },
1857 /* cond16-32: condition */
1858   { "cond16-32", M32C_OPERAND_COND16_32, HW_H_COND16, 0, 8,
1859     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
1860     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }  },
1861 /* cond32-16: condition */
1862   { "cond32-16", M32C_OPERAND_COND32_16, HW_H_COND32, 16, 8,
1863     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
1864     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
1865 /* cond32-24: condition */
1866   { "cond32-24", M32C_OPERAND_COND32_24, HW_H_COND32, 24, 8,
1867     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
1868     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
1869 /* cond32-32: condition */
1870   { "cond32-32", M32C_OPERAND_COND32_32, HW_H_COND32, 0, 8,
1871     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
1872     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
1873 /* cond32-40: condition */
1874   { "cond32-40", M32C_OPERAND_COND32_40, HW_H_COND32, 8, 8,
1875     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U8] } },
1876     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
1877 /* cond16c: condition */
1878   { "cond16c", M32C_OPERAND_COND16C, HW_H_COND16C, 12, 4,
1879     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_COND16] } },
1880     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }  },
1881 /* cond16j: condition */
1882   { "cond16j", M32C_OPERAND_COND16J, HW_H_COND16J, 12, 4,
1883     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_COND16] } },
1884     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }  },
1885 /* cond16j5: condition */
1886   { "cond16j5", M32C_OPERAND_COND16J5, HW_H_COND16J_5, 5, 3,
1887     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_COND16J_5] } },
1888     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }  },
1889 /* cond32: condition */
1890   { "cond32", M32C_OPERAND_COND32, HW_H_COND32, 9, 4,
1891     { 2, { (const PTR) &M32C_F_COND32_MULTI_IFIELD[0] } },
1892     { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
1893 /* cond32j: condition */
1894   { "cond32j", M32C_OPERAND_COND32J, HW_H_COND32, 1, 4,
1895     { 2, { (const PTR) &M32C_F_COND32J_MULTI_IFIELD[0] } },
1896     { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
1897 /* sccond32: scCND condition */
1898   { "sccond32", M32C_OPERAND_SCCOND32, HW_H_COND32, 12, 4,
1899     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_COND16] } },
1900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
1901 /* flags16: flags */
1902   { "flags16", M32C_OPERAND_FLAGS16, HW_H_FLAGS, 9, 3,
1903     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_9_3] } },
1904     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }  },
1905 /* flags32: flags */
1906   { "flags32", M32C_OPERAND_FLAGS32, HW_H_FLAGS, 13, 3,
1907     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } },
1908     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
1909 /* cr16: control */
1910   { "cr16", M32C_OPERAND_CR16, HW_H_CR_16, 9, 3,
1911     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_9_3] } },
1912     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }  },
1913 /* cr1-Unprefixed-32: control */
1914   { "cr1-Unprefixed-32", M32C_OPERAND_CR1_UNPREFIXED_32, HW_H_CR1_32, 13, 3,
1915     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } },
1916     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
1917 /* cr1-Prefixed-32: control */
1918   { "cr1-Prefixed-32", M32C_OPERAND_CR1_PREFIXED_32, HW_H_CR1_32, 21, 3,
1919     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_21_3] } },
1920     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
1921 /* cr2-32: control */
1922   { "cr2-32", M32C_OPERAND_CR2_32, HW_H_CR2_32, 13, 3,
1923     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } },
1924     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
1925 /* cr3-Unprefixed-32: control */
1926   { "cr3-Unprefixed-32", M32C_OPERAND_CR3_UNPREFIXED_32, HW_H_CR3_32, 13, 3,
1927     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } },
1928     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
1929 /* cr3-Prefixed-32: control */
1930   { "cr3-Prefixed-32", M32C_OPERAND_CR3_PREFIXED_32, HW_H_CR3_32, 21, 3,
1931     { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_21_3] } },
1932     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }  },
1933 /* Z: Suffix for zero format insns */
1934   { "Z", M32C_OPERAND_Z, HW_H_SINT, 0, 0,
1935     { 0, { (const PTR) 0 } },
1936     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1937 /* S: Suffix for short format insns */
1938   { "S", M32C_OPERAND_S, HW_H_SINT, 0, 0,
1939     { 0, { (const PTR) 0 } },
1940     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1941 /* Q: Suffix for quick format insns */
1942   { "Q", M32C_OPERAND_Q, HW_H_SINT, 0, 0,
1943     { 0, { (const PTR) 0 } },
1944     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1945 /* G: Suffix for general format insns */
1946   { "G", M32C_OPERAND_G, HW_H_SINT, 0, 0,
1947     { 0, { (const PTR) 0 } },
1948     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1949 /* X: Empty suffix */
1950   { "X", M32C_OPERAND_X, HW_H_SINT, 0, 0,
1951     { 0, { (const PTR) 0 } },
1952     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1953 /* size: any size specifier */
1954   { "size", M32C_OPERAND_SIZE, HW_H_SINT, 0, 0,
1955     { 0, { (const PTR) 0 } },
1956     { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } }  },
1957 /* BitIndex: Bit Index for the next insn */
1958   { "BitIndex", M32C_OPERAND_BITINDEX, HW_H_BIT_INDEX, 0, 0,
1959     { 0, { (const PTR) 0 } },
1960     { 0|A(SEM_ONLY), { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
1961 /* SrcIndex: Source Index for the next insn */
1962   { "SrcIndex", M32C_OPERAND_SRCINDEX, HW_H_SRC_INDEX, 0, 0,
1963     { 0, { (const PTR) 0 } },
1964     { 0|A(SEM_ONLY), { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
1965 /* DstIndex: Destination Index for the next insn */
1966   { "DstIndex", M32C_OPERAND_DSTINDEX, HW_H_DST_INDEX, 0, 0,
1967     { 0, { (const PTR) 0 } },
1968     { 0|A(SEM_ONLY), { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
1969 /* NoRemainder: Place holder for when the remainder is not kept */
1970   { "NoRemainder", M32C_OPERAND_NOREMAINDER, HW_H_NONE, 0, 0,
1971     { 0, { (const PTR) 0 } },
1972     { 0|A(SEM_ONLY), { (1<<MACH_M32C), (1<<ISA_M32C) } }  },
1973 /* src16-Rn-direct-QI: m16c Rn direct source QI */
1974 /* src16-Rn-direct-HI: m16c Rn direct source HI */
1975 /* src32-Rn-direct-Unprefixed-QI: m32c Rn direct source QI */
1976 /* src32-Rn-direct-Prefixed-QI: m32c Rn direct source QI */
1977 /* src32-Rn-direct-Unprefixed-HI: m32c Rn direct source HI */
1978 /* src32-Rn-direct-Prefixed-HI: m32c Rn direct source HI */
1979 /* src32-Rn-direct-Unprefixed-SI: m32c Rn direct source SI */
1980 /* src32-Rn-direct-Prefixed-SI: m32c Rn direct source SI */
1981 /* src16-An-direct-QI: m16c An direct destination QI */
1982 /* src16-An-direct-HI: m16c An direct destination HI */
1983 /* src32-An-direct-Unprefixed-QI: m32c An direct destination QI */
1984 /* src32-An-direct-Unprefixed-HI: m32c An direct destination HI */
1985 /* src32-An-direct-Unprefixed-SI: m32c An direct destination SI */
1986 /* src32-An-direct-Prefixed-QI: m32c An direct destination QI */
1987 /* src32-An-direct-Prefixed-HI: m32c An direct destination HI */
1988 /* src32-An-direct-Prefixed-SI: m32c An direct destination SI */
1989 /* src16-An-indirect-QI: m16c An indirect destination QI */
1990 /* src16-An-indirect-HI: m16c An indirect destination HI */
1991 /* src32-An-indirect-Unprefixed-QI: m32c An indirect destination QI */
1992 /* src32-An-indirect-Unprefixed-HI: m32c An indirect destination HI */
1993 /* src32-An-indirect-Unprefixed-SI: m32c An indirect destination SI */
1994 /* src32-An-indirect-Prefixed-QI: m32c An indirect destination QI */
1995 /* src32-An-indirect-Prefixed-HI: m32c An indirect destination HI */
1996 /* src32-An-indirect-Prefixed-SI: m32c An indirect destination SI */
1997 /* src16-16-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */
1998 /* src16-16-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */
1999 /* src16-16-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */
2000 /* src16-16-8-An-relative-QI: m16c dsp:8[An] relative destination QI */
2001 /* src16-16-16-An-relative-QI: m16c dsp:16[An] relative destination QI */
2002 /* src16-16-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */
2003 /* src16-16-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */
2004 /* src16-16-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */
2005 /* src16-16-8-An-relative-HI: m16c dsp:8[An] relative destination HI */
2006 /* src16-16-16-An-relative-HI: m16c dsp:16[An] relative destination HI */
2007 /* src32-16-8-SB-relative-Unprefixed-QI: m32c dsp:8[sb] relative destination QI */
2008 /* src32-16-16-SB-relative-Unprefixed-QI: m32c dsp:16[sb] relative destination QI */
2009 /* src32-16-8-FB-relative-Unprefixed-QI: m32c dsp:8[fb] relative destination QI */
2010 /* src32-16-16-FB-relative-Unprefixed-QI: m32c dsp:16[fb] relative destination QI */
2011 /* src32-16-8-An-relative-Unprefixed-QI: m32c dsp:8[An] relative destination QI */
2012 /* src32-16-16-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2013 /* src32-16-24-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2014 /* src32-16-8-SB-relative-Unprefixed-HI: m32c dsp:8[sb] relative destination HI */
2015 /* src32-16-16-SB-relative-Unprefixed-HI: m32c dsp:16[sb] relative destination HI */
2016 /* src32-16-8-FB-relative-Unprefixed-HI: m32c dsp:8[fb] relative destination HI */
2017 /* src32-16-16-FB-relative-Unprefixed-HI: m32c dsp:16[fb] relative destination HI */
2018 /* src32-16-8-An-relative-Unprefixed-HI: m32c dsp:8[An] relative destination HI */
2019 /* src32-16-16-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2020 /* src32-16-24-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2021 /* src32-16-8-SB-relative-Unprefixed-SI: m32c dsp:8[sb] relative destination SI */
2022 /* src32-16-16-SB-relative-Unprefixed-SI: m32c dsp:16[sb] relative destination SI */
2023 /* src32-16-8-FB-relative-Unprefixed-SI: m32c dsp:8[fb] relative destination SI */
2024 /* src32-16-16-FB-relative-Unprefixed-SI: m32c dsp:16[fb] relative destination SI */
2025 /* src32-16-8-An-relative-Unprefixed-SI: m32c dsp:8[An] relative destination SI */
2026 /* src32-16-16-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2027 /* src32-16-24-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2028 /* src32-24-8-SB-relative-Prefixed-QI: m32c dsp:8[sb] relative destination QI */
2029 /* src32-24-16-SB-relative-Prefixed-QI: m32c dsp:16[sb] relative destination QI */
2030 /* src32-24-8-FB-relative-Prefixed-QI: m32c dsp:8[fb] relative destination QI */
2031 /* src32-24-16-FB-relative-Prefixed-QI: m32c dsp:16[fb] relative destination QI */
2032 /* src32-24-8-An-relative-Prefixed-QI: m32c dsp:8[An] relative destination QI */
2033 /* src32-24-16-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2034 /* src32-24-24-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2035 /* src32-24-8-SB-relative-Prefixed-HI: m32c dsp:8[sb] relative destination HI */
2036 /* src32-24-16-SB-relative-Prefixed-HI: m32c dsp:16[sb] relative destination HI */
2037 /* src32-24-8-FB-relative-Prefixed-HI: m32c dsp:8[fb] relative destination HI */
2038 /* src32-24-16-FB-relative-Prefixed-HI: m32c dsp:16[fb] relative destination HI */
2039 /* src32-24-8-An-relative-Prefixed-HI: m32c dsp:8[An] relative destination HI */
2040 /* src32-24-16-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2041 /* src32-24-24-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2042 /* src32-24-8-SB-relative-Prefixed-SI: m32c dsp:8[sb] relative destination SI */
2043 /* src32-24-16-SB-relative-Prefixed-SI: m32c dsp:16[sb] relative destination SI */
2044 /* src32-24-8-FB-relative-Prefixed-SI: m32c dsp:8[fb] relative destination SI */
2045 /* src32-24-16-FB-relative-Prefixed-SI: m32c dsp:16[fb] relative destination SI */
2046 /* src32-24-8-An-relative-Prefixed-SI: m32c dsp:8[An] relative destination SI */
2047 /* src32-24-16-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2048 /* src32-24-24-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2049 /* dsp20-16-u20-QI: m16c dsp:20 absolute destination QI */
2050 /* dsp20-16-u20-A0-QI: m16c dsp:20[A0] relative destination QI */
2051 /* dsp20-16-A1A0-QI: m16c [A1A0] relative destination QI */
2052 /* dsp20-24-u20-QI: m16c dsp:20 absolute destination QI */
2053 /* dsp20-24-u20-A0-QI: m16c dsp:20[A0] relative destination QI */
2054 /* dsp20-24-A1A0-QI: m16c [A1A0] relative destination QI */
2055 /* dsp20-32-u20-QI: m16c dsp:20 absolute destination QI */
2056 /* dsp20-32-u20-A0-QI: m16c dsp:20[A0] relative destination QI */
2057 /* dsp20-32-A1A0-QI: m16c [A1A0] relative destination QI */
2058 /* dsp20-16-u20-HI: m16c dsp:20 absolute destination HI */
2059 /* dsp20-16-u20-A0-HI: m16c dsp:20[A0] relative destination HI */
2060 /* dsp20-16-A1A0-HI: m16c [A1A0] relative destination HI */
2061 /* dsp20-24-u20-HI: m16c dsp:20 absolute destination HI */
2062 /* dsp20-24-u20-A0-HI: m16c dsp:20[A0] relative destination HI */
2063 /* dsp20-24-A1A0-HI: m16c [A1A0] relative destination HI */
2064 /* dsp20-32-u20-HI: m16c dsp:20 absolute destination HI */
2065 /* dsp20-32-u20-A0-HI: m16c dsp:20[A0] relative destination HI */
2066 /* dsp20-32-A1A0-HI: m16c [A1A0] relative destination HI */
2067 /* src16-16-16-absolute-QI: m16c absolute address QI */
2068 /* src16-16-16-absolute-HI: m16c absolute address HI */
2069 /* src32-16-16-absolute-Unprefixed-QI: m32c absolute address QI */
2070 /* src32-16-24-absolute-Unprefixed-QI: m32c absolute address QI */
2071 /* src32-16-16-absolute-Unprefixed-HI: m32c absolute address HI */
2072 /* src32-16-24-absolute-Unprefixed-HI: m32c absolute address HI */
2073 /* src32-16-16-absolute-Unprefixed-SI: m32c absolute address SI */
2074 /* src32-16-24-absolute-Unprefixed-SI: m32c absolute address SI */
2075 /* src32-24-16-absolute-Prefixed-QI: m32c absolute address QI */
2076 /* src32-24-24-absolute-Prefixed-QI: m32c absolute address QI */
2077 /* src32-24-16-absolute-Prefixed-HI: m32c absolute address HI */
2078 /* src32-24-24-absolute-Prefixed-HI: m32c absolute address HI */
2079 /* src32-24-16-absolute-Prefixed-SI: m32c absolute address SI */
2080 /* src32-24-24-absolute-Prefixed-SI: m32c absolute address SI */
2081 /* src16-2-S-8-SB-relative-QI: m16c SB relative address */
2082 /* src16-2-S-8-FB-relative-QI: m16c FB relative address */
2083 /* src16-2-S-16-absolute-QI: m16c absolute address */
2084 /* src32-2-S-8-SB-relative-QI: m32c SB relative address */
2085 /* src32-2-S-8-FB-relative-QI: m32c FB relative address */
2086 /* src32-2-S-16-absolute-QI: m32c absolute address */
2087 /* src32-2-S-8-SB-relative-HI: m32c SB relative address */
2088 /* src32-2-S-8-FB-relative-HI: m32c FB relative address */
2089 /* src32-2-S-16-absolute-HI: m32c absolute address */
2090 /* dst16-Rn-direct-QI: m16c Rn direct destination QI */
2091 /* dst16-Rn-direct-HI: m16c Rn direct destination HI */
2092 /* dst16-Rn-direct-SI: m16c Rn direct destination SI */
2093 /* dst16-Rn-direct-Ext-QI: m16c Rn direct destination QI */
2094 /* dst32-Rn-direct-Unprefixed-QI: m32c Rn direct destination QI */
2095 /* dst32-Rn-direct-Prefixed-QI: m32c Rn direct destination QI */
2096 /* dst32-Rn-direct-Unprefixed-HI: m32c Rn direct destination HI */
2097 /* dst32-Rn-direct-Prefixed-HI: m32c Rn direct destination HI */
2098 /* dst32-Rn-direct-Unprefixed-SI: m32c Rn direct destination SI */
2099 /* dst32-Rn-direct-Prefixed-SI: m32c Rn direct destination SI */
2100 /* dst32-Rn-direct-ExtUnprefixed-QI: m32c Rn direct destination QI */
2101 /* dst32-Rn-direct-ExtUnprefixed-HI: m32c Rn direct destination HI */
2102 /* dst32-R3-direct-Unprefixed-HI: m32c R3 direct HI */
2103 /* dst16-An-direct-QI: m16c An direct destination QI */
2104 /* dst16-An-direct-HI: m16c An direct destination HI */
2105 /* dst16-An-direct-SI: m16c An direct destination SI */
2106 /* dst32-An-direct-Unprefixed-QI: m32c An direct destination QI */
2107 /* dst32-An-direct-Prefixed-QI: m32c An direct destination QI */
2108 /* dst32-An-direct-Unprefixed-HI: m32c An direct destination HI */
2109 /* dst32-An-direct-Prefixed-HI: m32c An direct destination HI */
2110 /* dst32-An-direct-Unprefixed-SI: m32c An direct destination SI */
2111 /* dst32-An-direct-Prefixed-SI: m32c An direct destination SI */
2112 /* dst16-An-indirect-QI: m16c An indirect destination QI */
2113 /* dst16-An-indirect-HI: m16c An indirect destination HI */
2114 /* dst16-An-indirect-SI: m16c An indirect destination SI */
2115 /* dst16-An-indirect-Ext-QI: m16c An indirect destination QI */
2116 /* dst32-An-indirect-Unprefixed-QI: m32c An indirect destination QI */
2117 /* dst32-An-indirect-Prefixed-QI: m32c An indirect destination QI */
2118 /* dst32-An-indirect-Unprefixed-HI: m32c An indirect destination HI */
2119 /* dst32-An-indirect-Prefixed-HI: m32c An indirect destination HI */
2120 /* dst32-An-indirect-Unprefixed-SI: m32c An indirect destination SI */
2121 /* dst32-An-indirect-Prefixed-SI: m32c An indirect destination SI */
2122 /* dst32-An-indirect-ExtUnprefixed-QI: m32c An indirect destination QI */
2123 /* dst32-An-indirect-ExtUnprefixed-HI: m32c An indirect destination HI */
2124 /* dst16-16-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */
2125 /* dst16-16-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */
2126 /* dst16-16-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */
2127 /* dst16-16-8-An-relative-QI: m16c dsp:8[An] relative destination QI */
2128 /* dst16-16-16-An-relative-QI: m16c dsp:16[An] relative destination QI */
2129 /* dst16-24-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */
2130 /* dst16-24-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */
2131 /* dst16-24-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */
2132 /* dst16-24-8-An-relative-QI: m16c dsp:8[An] relative destination QI */
2133 /* dst16-24-16-An-relative-QI: m16c dsp:16[An] relative destination QI */
2134 /* dst16-32-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */
2135 /* dst16-32-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */
2136 /* dst16-32-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */
2137 /* dst16-32-8-An-relative-QI: m16c dsp:8[An] relative destination QI */
2138 /* dst16-32-16-An-relative-QI: m16c dsp:16[An] relative destination QI */
2139 /* dst16-40-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */
2140 /* dst16-40-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */
2141 /* dst16-40-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */
2142 /* dst16-40-8-An-relative-QI: m16c dsp:8[An] relative destination QI */
2143 /* dst16-40-16-An-relative-QI: m16c dsp:16[An] relative destination QI */
2144 /* dst16-48-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */
2145 /* dst16-48-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */
2146 /* dst16-48-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */
2147 /* dst16-48-8-An-relative-QI: m16c dsp:8[An] relative destination QI */
2148 /* dst16-48-16-An-relative-QI: m16c dsp:16[An] relative destination QI */
2149 /* dst16-16-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */
2150 /* dst16-16-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */
2151 /* dst16-16-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */
2152 /* dst16-16-8-An-relative-HI: m16c dsp:8[An] relative destination HI */
2153 /* dst16-16-16-An-relative-HI: m16c dsp:16[An] relative destination HI */
2154 /* dst16-24-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */
2155 /* dst16-24-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */
2156 /* dst16-24-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */
2157 /* dst16-24-8-An-relative-HI: m16c dsp:8[An] relative destination HI */
2158 /* dst16-24-16-An-relative-HI: m16c dsp:16[An] relative destination HI */
2159 /* dst16-32-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */
2160 /* dst16-32-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */
2161 /* dst16-32-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */
2162 /* dst16-32-8-An-relative-HI: m16c dsp:8[An] relative destination HI */
2163 /* dst16-32-16-An-relative-HI: m16c dsp:16[An] relative destination HI */
2164 /* dst16-40-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */
2165 /* dst16-40-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */
2166 /* dst16-40-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */
2167 /* dst16-40-8-An-relative-HI: m16c dsp:8[An] relative destination HI */
2168 /* dst16-40-16-An-relative-HI: m16c dsp:16[An] relative destination HI */
2169 /* dst16-48-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */
2170 /* dst16-48-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */
2171 /* dst16-48-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */
2172 /* dst16-48-8-An-relative-HI: m16c dsp:8[An] relative destination HI */
2173 /* dst16-48-16-An-relative-HI: m16c dsp:16[An] relative destination HI */
2174 /* dst16-16-8-SB-relative-SI: m16c dsp:8[sb] relative destination SI */
2175 /* dst16-16-16-SB-relative-SI: m16c dsp:16[sb] relative destination SI */
2176 /* dst16-16-8-FB-relative-SI: m16c dsp:8[fb] relative destination SI */
2177 /* dst16-16-8-An-relative-SI: m16c dsp:8[An] relative destination SI */
2178 /* dst16-16-16-An-relative-SI: m16c dsp:16[An] relative destination SI */
2179 /* dst16-24-8-SB-relative-SI: m16c dsp:8[sb] relative destination SI */
2180 /* dst16-24-16-SB-relative-SI: m16c dsp:16[sb] relative destination SI */
2181 /* dst16-24-8-FB-relative-SI: m16c dsp:8[fb] relative destination SI */
2182 /* dst16-24-8-An-relative-SI: m16c dsp:8[An] relative destination SI */
2183 /* dst16-24-16-An-relative-SI: m16c dsp:16[An] relative destination SI */
2184 /* dst16-32-8-SB-relative-SI: m16c dsp:8[sb] relative destination SI */
2185 /* dst16-32-16-SB-relative-SI: m16c dsp:16[sb] relative destination SI */
2186 /* dst16-32-8-FB-relative-SI: m16c dsp:8[fb] relative destination SI */
2187 /* dst16-32-8-An-relative-SI: m16c dsp:8[An] relative destination SI */
2188 /* dst16-32-16-An-relative-SI: m16c dsp:16[An] relative destination SI */
2189 /* dst16-40-8-SB-relative-SI: m16c dsp:8[sb] relative destination SI */
2190 /* dst16-40-16-SB-relative-SI: m16c dsp:16[sb] relative destination SI */
2191 /* dst16-40-8-FB-relative-SI: m16c dsp:8[fb] relative destination SI */
2192 /* dst16-40-8-An-relative-SI: m16c dsp:8[An] relative destination SI */
2193 /* dst16-40-16-An-relative-SI: m16c dsp:16[An] relative destination SI */
2194 /* dst16-48-8-SB-relative-SI: m16c dsp:8[sb] relative destination SI */
2195 /* dst16-48-16-SB-relative-SI: m16c dsp:16[sb] relative destination SI */
2196 /* dst16-48-8-FB-relative-SI: m16c dsp:8[fb] relative destination SI */
2197 /* dst16-48-8-An-relative-SI: m16c dsp:8[An] relative destination SI */
2198 /* dst16-48-16-An-relative-SI: m16c dsp:16[An] relative destination SI */
2199 /* dst16-16-8-SB-relative-Ext-QI: m16c dsp:8[sb] relative destination QI */
2200 /* dst16-16-16-SB-relative-Ext-QI: m16c dsp:16[sb] relative destination QI */
2201 /* dst16-16-8-FB-relative-Ext-QI: m16c dsp:8[fb] relative destination QI */
2202 /* dst16-16-8-An-relative-Ext-QI: m16c dsp:8[An] relative destination QI */
2203 /* dst16-16-16-An-relative-Ext-QI: m16c dsp:16[An] relative destination QI */
2204 /* dst32-16-8-SB-relative-Unprefixed-QI: m32c dsp:8[sb] relative destination QI */
2205 /* dst32-16-16-SB-relative-Unprefixed-QI: m32c dsp:16[sb] relative destination QI */
2206 /* dst32-16-8-FB-relative-Unprefixed-QI: m32c dsp:8[fb] relative destination QI */
2207 /* dst32-16-16-FB-relative-Unprefixed-QI: m32c dsp:16[fb] relative destination QI */
2208 /* dst32-16-8-An-relative-Unprefixed-QI: m32c dsp:8[An] relative destination QI */
2209 /* dst32-16-16-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2210 /* dst32-16-24-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2211 /* dst32-24-8-SB-relative-Unprefixed-QI: m32c dsp:8[sb] relative destination QI */
2212 /* dst32-24-16-SB-relative-Unprefixed-QI: m32c dsp:16[sb] relative destination QI */
2213 /* dst32-24-8-FB-relative-Unprefixed-QI: m32c dsp:8[fb] relative destination QI */
2214 /* dst32-24-16-FB-relative-Unprefixed-QI: m32c dsp:16[fb] relative destination QI */
2215 /* dst32-24-8-An-relative-Unprefixed-QI: m32c dsp:8[An] relative destination QI */
2216 /* dst32-24-16-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2217 /* dst32-24-24-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2218 /* dst32-32-8-SB-relative-Unprefixed-QI: m32c dsp:8[sb] relative destination QI */
2219 /* dst32-32-16-SB-relative-Unprefixed-QI: m32c dsp:16[sb] relative destination QI */
2220 /* dst32-32-8-FB-relative-Unprefixed-QI: m32c dsp:8[fb] relative destination QI */
2221 /* dst32-32-16-FB-relative-Unprefixed-QI: m32c dsp:16[fb] relative destination QI */
2222 /* dst32-32-8-An-relative-Unprefixed-QI: m32c dsp:8[An] relative destination QI */
2223 /* dst32-32-16-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2224 /* dst32-32-24-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2225 /* dst32-40-8-SB-relative-Unprefixed-QI: m32c dsp:8[sb] relative destination QI */
2226 /* dst32-40-16-SB-relative-Unprefixed-QI: m32c dsp:16[sb] relative destination QI */
2227 /* dst32-40-8-FB-relative-Unprefixed-QI: m32c dsp:8[fb] relative destination QI */
2228 /* dst32-40-16-FB-relative-Unprefixed-QI: m32c dsp:16[fb] relative destination QI */
2229 /* dst32-40-8-An-relative-Unprefixed-QI: m32c dsp:8[An] relative destination QI */
2230 /* dst32-40-16-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2231 /* dst32-40-24-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2232 /* dst32-16-8-SB-relative-Unprefixed-HI: m32c dsp:8[sb] relative destination HI */
2233 /* dst32-16-16-SB-relative-Unprefixed-HI: m32c dsp:16[sb] relative destination HI */
2234 /* dst32-16-8-FB-relative-Unprefixed-HI: m32c dsp:8[fb] relative destination HI */
2235 /* dst32-16-16-FB-relative-Unprefixed-HI: m32c dsp:16[fb] relative destination HI */
2236 /* dst32-16-8-An-relative-Unprefixed-HI: m32c dsp:8[An] relative destination HI */
2237 /* dst32-16-16-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2238 /* dst32-16-24-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2239 /* dst32-24-8-SB-relative-Unprefixed-HI: m32c dsp:8[sb] relative destination HI */
2240 /* dst32-24-16-SB-relative-Unprefixed-HI: m32c dsp:16[sb] relative destination HI */
2241 /* dst32-24-8-FB-relative-Unprefixed-HI: m32c dsp:8[fb] relative destination HI */
2242 /* dst32-24-16-FB-relative-Unprefixed-HI: m32c dsp:16[fb] relative destination HI */
2243 /* dst32-24-8-An-relative-Unprefixed-HI: m32c dsp:8[An] relative destination HI */
2244 /* dst32-24-16-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2245 /* dst32-24-24-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2246 /* dst32-32-8-SB-relative-Unprefixed-HI: m32c dsp:8[sb] relative destination HI */
2247 /* dst32-32-16-SB-relative-Unprefixed-HI: m32c dsp:16[sb] relative destination HI */
2248 /* dst32-32-8-FB-relative-Unprefixed-HI: m32c dsp:8[fb] relative destination HI */
2249 /* dst32-32-16-FB-relative-Unprefixed-HI: m32c dsp:16[fb] relative destination HI */
2250 /* dst32-32-8-An-relative-Unprefixed-HI: m32c dsp:8[An] relative destination HI */
2251 /* dst32-32-16-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2252 /* dst32-32-24-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2253 /* dst32-40-8-SB-relative-Unprefixed-HI: m32c dsp:8[sb] relative destination HI */
2254 /* dst32-40-16-SB-relative-Unprefixed-HI: m32c dsp:16[sb] relative destination HI */
2255 /* dst32-40-8-FB-relative-Unprefixed-HI: m32c dsp:8[fb] relative destination HI */
2256 /* dst32-40-16-FB-relative-Unprefixed-HI: m32c dsp:16[fb] relative destination HI */
2257 /* dst32-40-8-An-relative-Unprefixed-HI: m32c dsp:8[An] relative destination HI */
2258 /* dst32-40-16-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2259 /* dst32-40-24-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2260 /* dst32-16-8-SB-relative-Unprefixed-SI: m32c dsp:8[sb] relative destination SI */
2261 /* dst32-16-16-SB-relative-Unprefixed-SI: m32c dsp:16[sb] relative destination SI */
2262 /* dst32-16-8-FB-relative-Unprefixed-SI: m32c dsp:8[fb] relative destination SI */
2263 /* dst32-16-16-FB-relative-Unprefixed-SI: m32c dsp:16[fb] relative destination SI */
2264 /* dst32-16-8-An-relative-Unprefixed-SI: m32c dsp:8[An] relative destination SI */
2265 /* dst32-16-16-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2266 /* dst32-16-24-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2267 /* dst32-24-8-SB-relative-Unprefixed-SI: m32c dsp:8[sb] relative destination SI */
2268 /* dst32-24-16-SB-relative-Unprefixed-SI: m32c dsp:16[sb] relative destination SI */
2269 /* dst32-24-8-FB-relative-Unprefixed-SI: m32c dsp:8[fb] relative destination SI */
2270 /* dst32-24-16-FB-relative-Unprefixed-SI: m32c dsp:16[fb] relative destination SI */
2271 /* dst32-24-8-An-relative-Unprefixed-SI: m32c dsp:8[An] relative destination SI */
2272 /* dst32-24-16-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2273 /* dst32-24-24-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2274 /* dst32-32-8-SB-relative-Unprefixed-SI: m32c dsp:8[sb] relative destination SI */
2275 /* dst32-32-16-SB-relative-Unprefixed-SI: m32c dsp:16[sb] relative destination SI */
2276 /* dst32-32-8-FB-relative-Unprefixed-SI: m32c dsp:8[fb] relative destination SI */
2277 /* dst32-32-16-FB-relative-Unprefixed-SI: m32c dsp:16[fb] relative destination SI */
2278 /* dst32-32-8-An-relative-Unprefixed-SI: m32c dsp:8[An] relative destination SI */
2279 /* dst32-32-16-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2280 /* dst32-32-24-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2281 /* dst32-40-8-SB-relative-Unprefixed-SI: m32c dsp:8[sb] relative destination SI */
2282 /* dst32-40-16-SB-relative-Unprefixed-SI: m32c dsp:16[sb] relative destination SI */
2283 /* dst32-40-8-FB-relative-Unprefixed-SI: m32c dsp:8[fb] relative destination SI */
2284 /* dst32-40-16-FB-relative-Unprefixed-SI: m32c dsp:16[fb] relative destination SI */
2285 /* dst32-40-8-An-relative-Unprefixed-SI: m32c dsp:8[An] relative destination SI */
2286 /* dst32-40-16-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2287 /* dst32-40-24-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2288 /* dst32-24-8-SB-relative-Prefixed-QI: m32c dsp:8[sb] relative destination QI */
2289 /* dst32-24-16-SB-relative-Prefixed-QI: m32c dsp:16[sb] relative destination QI */
2290 /* dst32-24-8-FB-relative-Prefixed-QI: m32c dsp:8[fb] relative destination QI */
2291 /* dst32-24-16-FB-relative-Prefixed-QI: m32c dsp:16[fb] relative destination QI */
2292 /* dst32-24-8-An-relative-Prefixed-QI: m32c dsp:8[An] relative destination QI */
2293 /* dst32-24-16-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2294 /* dst32-24-24-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2295 /* dst32-32-8-SB-relative-Prefixed-QI: m32c dsp:8[sb] relative destination QI */
2296 /* dst32-32-16-SB-relative-Prefixed-QI: m32c dsp:16[sb] relative destination QI */
2297 /* dst32-32-8-FB-relative-Prefixed-QI: m32c dsp:8[fb] relative destination QI */
2298 /* dst32-32-16-FB-relative-Prefixed-QI: m32c dsp:16[fb] relative destination QI */
2299 /* dst32-32-8-An-relative-Prefixed-QI: m32c dsp:8[An] relative destination QI */
2300 /* dst32-32-16-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2301 /* dst32-32-24-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2302 /* dst32-40-8-SB-relative-Prefixed-QI: m32c dsp:8[sb] relative destination QI */
2303 /* dst32-40-16-SB-relative-Prefixed-QI: m32c dsp:16[sb] relative destination QI */
2304 /* dst32-40-8-FB-relative-Prefixed-QI: m32c dsp:8[fb] relative destination QI */
2305 /* dst32-40-16-FB-relative-Prefixed-QI: m32c dsp:16[fb] relative destination QI */
2306 /* dst32-40-8-An-relative-Prefixed-QI: m32c dsp:8[An] relative destination QI */
2307 /* dst32-40-16-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2308 /* dst32-40-24-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2309 /* dst32-48-8-SB-relative-Prefixed-QI: m32c dsp:8[sb] relative destination QI */
2310 /* dst32-48-16-SB-relative-Prefixed-QI: m32c dsp:16[sb] relative destination QI */
2311 /* dst32-48-8-FB-relative-Prefixed-QI: m32c dsp:8[fb] relative destination QI */
2312 /* dst32-48-16-FB-relative-Prefixed-QI: m32c dsp:16[fb] relative destination QI */
2313 /* dst32-48-8-An-relative-Prefixed-QI: m32c dsp:8[An] relative destination QI */
2314 /* dst32-48-16-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2315 /* dst32-48-24-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2316 /* dst32-24-8-SB-relative-Prefixed-HI: m32c dsp:8[sb] relative destination HI */
2317 /* dst32-24-16-SB-relative-Prefixed-HI: m32c dsp:16[sb] relative destination HI */
2318 /* dst32-24-8-FB-relative-Prefixed-HI: m32c dsp:8[fb] relative destination HI */
2319 /* dst32-24-16-FB-relative-Prefixed-HI: m32c dsp:16[fb] relative destination HI */
2320 /* dst32-24-8-An-relative-Prefixed-HI: m32c dsp:8[An] relative destination HI */
2321 /* dst32-24-16-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2322 /* dst32-24-24-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2323 /* dst32-32-8-SB-relative-Prefixed-HI: m32c dsp:8[sb] relative destination HI */
2324 /* dst32-32-16-SB-relative-Prefixed-HI: m32c dsp:16[sb] relative destination HI */
2325 /* dst32-32-8-FB-relative-Prefixed-HI: m32c dsp:8[fb] relative destination HI */
2326 /* dst32-32-16-FB-relative-Prefixed-HI: m32c dsp:16[fb] relative destination HI */
2327 /* dst32-32-8-An-relative-Prefixed-HI: m32c dsp:8[An] relative destination HI */
2328 /* dst32-32-16-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2329 /* dst32-32-24-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2330 /* dst32-40-8-SB-relative-Prefixed-HI: m32c dsp:8[sb] relative destination HI */
2331 /* dst32-40-16-SB-relative-Prefixed-HI: m32c dsp:16[sb] relative destination HI */
2332 /* dst32-40-8-FB-relative-Prefixed-HI: m32c dsp:8[fb] relative destination HI */
2333 /* dst32-40-16-FB-relative-Prefixed-HI: m32c dsp:16[fb] relative destination HI */
2334 /* dst32-40-8-An-relative-Prefixed-HI: m32c dsp:8[An] relative destination HI */
2335 /* dst32-40-16-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2336 /* dst32-40-24-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2337 /* dst32-48-8-SB-relative-Prefixed-HI: m32c dsp:8[sb] relative destination HI */
2338 /* dst32-48-16-SB-relative-Prefixed-HI: m32c dsp:16[sb] relative destination HI */
2339 /* dst32-48-8-FB-relative-Prefixed-HI: m32c dsp:8[fb] relative destination HI */
2340 /* dst32-48-16-FB-relative-Prefixed-HI: m32c dsp:16[fb] relative destination HI */
2341 /* dst32-48-8-An-relative-Prefixed-HI: m32c dsp:8[An] relative destination HI */
2342 /* dst32-48-16-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2343 /* dst32-48-24-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2344 /* dst32-24-8-SB-relative-Prefixed-SI: m32c dsp:8[sb] relative destination SI */
2345 /* dst32-24-16-SB-relative-Prefixed-SI: m32c dsp:16[sb] relative destination SI */
2346 /* dst32-24-8-FB-relative-Prefixed-SI: m32c dsp:8[fb] relative destination SI */
2347 /* dst32-24-16-FB-relative-Prefixed-SI: m32c dsp:16[fb] relative destination SI */
2348 /* dst32-24-8-An-relative-Prefixed-SI: m32c dsp:8[An] relative destination SI */
2349 /* dst32-24-16-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2350 /* dst32-24-24-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2351 /* dst32-32-8-SB-relative-Prefixed-SI: m32c dsp:8[sb] relative destination SI */
2352 /* dst32-32-16-SB-relative-Prefixed-SI: m32c dsp:16[sb] relative destination SI */
2353 /* dst32-32-8-FB-relative-Prefixed-SI: m32c dsp:8[fb] relative destination SI */
2354 /* dst32-32-16-FB-relative-Prefixed-SI: m32c dsp:16[fb] relative destination SI */
2355 /* dst32-32-8-An-relative-Prefixed-SI: m32c dsp:8[An] relative destination SI */
2356 /* dst32-32-16-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2357 /* dst32-32-24-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2358 /* dst32-40-8-SB-relative-Prefixed-SI: m32c dsp:8[sb] relative destination SI */
2359 /* dst32-40-16-SB-relative-Prefixed-SI: m32c dsp:16[sb] relative destination SI */
2360 /* dst32-40-8-FB-relative-Prefixed-SI: m32c dsp:8[fb] relative destination SI */
2361 /* dst32-40-16-FB-relative-Prefixed-SI: m32c dsp:16[fb] relative destination SI */
2362 /* dst32-40-8-An-relative-Prefixed-SI: m32c dsp:8[An] relative destination SI */
2363 /* dst32-40-16-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2364 /* dst32-40-24-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2365 /* dst32-48-8-SB-relative-Prefixed-SI: m32c dsp:8[sb] relative destination SI */
2366 /* dst32-48-16-SB-relative-Prefixed-SI: m32c dsp:16[sb] relative destination SI */
2367 /* dst32-48-8-FB-relative-Prefixed-SI: m32c dsp:8[fb] relative destination SI */
2368 /* dst32-48-16-FB-relative-Prefixed-SI: m32c dsp:16[fb] relative destination SI */
2369 /* dst32-48-8-An-relative-Prefixed-SI: m32c dsp:8[An] relative destination SI */
2370 /* dst32-48-16-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2371 /* dst32-48-24-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2372 /* dst32-16-8-SB-relative-ExtUnprefixed-QI: m32c dsp:8[sb] relative destination QI */
2373 /* dst32-16-16-SB-relative-ExtUnprefixed-QI: m32c dsp:16[sb] relative destination QI */
2374 /* dst32-16-8-FB-relative-ExtUnprefixed-QI: m32c dsp:8[fb] relative destination QI */
2375 /* dst32-16-16-FB-relative-ExtUnprefixed-QI: m32c dsp:16[fb] relative destination QI */
2376 /* dst32-16-8-An-relative-ExtUnprefixed-QI: m32c dsp:8[An] relative destination QI */
2377 /* dst32-16-16-An-relative-ExtUnprefixed-QI: m32c dsp:16[An] relative destination QI */
2378 /* dst32-16-24-An-relative-ExtUnprefixed-QI: m32c dsp:16[An] relative destination QI */
2379 /* dst32-16-8-SB-relative-ExtUnprefixed-HI: m32c dsp:8[sb] relative destination HI */
2380 /* dst32-16-16-SB-relative-ExtUnprefixed-HI: m32c dsp:16[sb] relative destination HI */
2381 /* dst32-16-8-FB-relative-ExtUnprefixed-HI: m32c dsp:8[fb] relative destination HI */
2382 /* dst32-16-16-FB-relative-ExtUnprefixed-HI: m32c dsp:16[fb] relative destination HI */
2383 /* dst32-16-8-An-relative-ExtUnprefixed-HI: m32c dsp:8[An] relative destination HI */
2384 /* dst32-16-16-An-relative-ExtUnprefixed-HI: m32c dsp:16[An] relative destination HI */
2385 /* dst32-16-24-An-relative-ExtUnprefixed-HI: m32c dsp:16[An] relative destination HI */
2386 /* dst16-16-16-absolute-QI: m16c absolute address QI */
2387 /* dst16-24-16-absolute-QI: m16c absolute address QI */
2388 /* dst16-32-16-absolute-QI: m16c absolute address QI */
2389 /* dst16-40-16-absolute-QI: m16c absolute address QI */
2390 /* dst16-48-16-absolute-QI: m16c absolute address QI */
2391 /* dst16-16-16-absolute-HI: m16c absolute address HI */
2392 /* dst16-24-16-absolute-HI: m16c absolute address HI */
2393 /* dst16-32-16-absolute-HI: m16c absolute address HI */
2394 /* dst16-40-16-absolute-HI: m16c absolute address HI */
2395 /* dst16-48-16-absolute-HI: m16c absolute address HI */
2396 /* dst16-16-16-absolute-SI: m16c absolute address SI */
2397 /* dst16-24-16-absolute-SI: m16c absolute address SI */
2398 /* dst16-32-16-absolute-SI: m16c absolute address SI */
2399 /* dst16-40-16-absolute-SI: m16c absolute address SI */
2400 /* dst16-48-16-absolute-SI: m16c absolute address SI */
2401 /* dst16-16-16-absolute-Ext-QI: m16c absolute address QI */
2402 /* dst32-16-16-absolute-Unprefixed-QI: m32c absolute address QI */
2403 /* dst32-16-24-absolute-Unprefixed-QI: m32c absolute address QI */
2404 /* dst32-24-16-absolute-Unprefixed-QI: m32c absolute address QI */
2405 /* dst32-24-24-absolute-Unprefixed-QI: m32c absolute address QI */
2406 /* dst32-32-16-absolute-Unprefixed-QI: m32c absolute address QI */
2407 /* dst32-32-24-absolute-Unprefixed-QI: m32c absolute address QI */
2408 /* dst32-40-16-absolute-Unprefixed-QI: m32c absolute address QI */
2409 /* dst32-40-24-absolute-Unprefixed-QI: m32c absolute address QI */
2410 /* dst32-16-16-absolute-Unprefixed-HI: m32c absolute address HI */
2411 /* dst32-16-24-absolute-Unprefixed-HI: m32c absolute address HI */
2412 /* dst32-24-16-absolute-Unprefixed-HI: m32c absolute address HI */
2413 /* dst32-24-24-absolute-Unprefixed-HI: m32c absolute address HI */
2414 /* dst32-32-16-absolute-Unprefixed-HI: m32c absolute address HI */
2415 /* dst32-32-24-absolute-Unprefixed-HI: m32c absolute address HI */
2416 /* dst32-40-16-absolute-Unprefixed-HI: m32c absolute address HI */
2417 /* dst32-40-24-absolute-Unprefixed-HI: m32c absolute address HI */
2418 /* dst32-16-16-absolute-Unprefixed-SI: m32c absolute address SI */
2419 /* dst32-16-24-absolute-Unprefixed-SI: m32c absolute address SI */
2420 /* dst32-24-16-absolute-Unprefixed-SI: m32c absolute address SI */
2421 /* dst32-24-24-absolute-Unprefixed-SI: m32c absolute address SI */
2422 /* dst32-32-16-absolute-Unprefixed-SI: m32c absolute address SI */
2423 /* dst32-32-24-absolute-Unprefixed-SI: m32c absolute address SI */
2424 /* dst32-40-16-absolute-Unprefixed-SI: m32c absolute address SI */
2425 /* dst32-40-24-absolute-Unprefixed-SI: m32c absolute address SI */
2426 /* dst32-24-16-absolute-Prefixed-QI: m32c absolute address QI */
2427 /* dst32-24-24-absolute-Prefixed-QI: m32c absolute address QI */
2428 /* dst32-32-16-absolute-Prefixed-QI: m32c absolute address QI */
2429 /* dst32-32-24-absolute-Prefixed-QI: m32c absolute address QI */
2430 /* dst32-40-16-absolute-Prefixed-QI: m32c absolute address QI */
2431 /* dst32-40-24-absolute-Prefixed-QI: m32c absolute address QI */
2432 /* dst32-48-16-absolute-Prefixed-QI: m32c absolute address QI */
2433 /* dst32-48-24-absolute-Prefixed-QI: m32c absolute address QI */
2434 /* dst32-24-16-absolute-Prefixed-HI: m32c absolute address HI */
2435 /* dst32-24-24-absolute-Prefixed-HI: m32c absolute address HI */
2436 /* dst32-32-16-absolute-Prefixed-HI: m32c absolute address HI */
2437 /* dst32-32-24-absolute-Prefixed-HI: m32c absolute address HI */
2438 /* dst32-40-16-absolute-Prefixed-HI: m32c absolute address HI */
2439 /* dst32-40-24-absolute-Prefixed-HI: m32c absolute address HI */
2440 /* dst32-48-16-absolute-Prefixed-HI: m32c absolute address HI */
2441 /* dst32-48-24-absolute-Prefixed-HI: m32c absolute address HI */
2442 /* dst32-24-16-absolute-Prefixed-SI: m32c absolute address SI */
2443 /* dst32-24-24-absolute-Prefixed-SI: m32c absolute address SI */
2444 /* dst32-32-16-absolute-Prefixed-SI: m32c absolute address SI */
2445 /* dst32-32-24-absolute-Prefixed-SI: m32c absolute address SI */
2446 /* dst32-40-16-absolute-Prefixed-SI: m32c absolute address SI */
2447 /* dst32-40-24-absolute-Prefixed-SI: m32c absolute address SI */
2448 /* dst32-48-16-absolute-Prefixed-SI: m32c absolute address SI */
2449 /* dst32-48-24-absolute-Prefixed-SI: m32c absolute address SI */
2450 /* dst32-16-16-absolute-ExtUnprefixed-QI: m32c absolute address QI */
2451 /* dst32-16-24-absolute-ExtUnprefixed-QI: m32c absolute address QI */
2452 /* dst32-16-16-absolute-ExtUnprefixed-HI: m32c absolute address HI */
2453 /* dst32-16-24-absolute-ExtUnprefixed-HI: m32c absolute address HI */
2454 /* bit16-Rn-direct: m16c Rn direct bit */
2455 /* bit32-Rn-direct-Unprefixed: m32c Rn direct bit */
2456 /* bit32-Rn-direct-Prefixed: m32c Rn direct bit */
2457 /* bit16-An-direct: m16c An direct bit */
2458 /* bit32-An-direct-Unprefixed: m32c An direct bit */
2459 /* bit32-An-direct-Prefixed: m32c An direct bit */
2460 /* bit16-An-indirect: m16c An indirect bit */
2461 /* bit32-An-indirect-Unprefixed: m32c An indirect destination  */
2462 /* bit32-An-indirect-Prefixed: m32c An indirect destination  */
2463 /* bit16-16-8-SB-relative: m16c dsp:8[sb] relative bit xmode */
2464 /* bit16-16-16-SB-relative: m16c dsp:16[sb] relative bit xmode */
2465 /* bit16-16-8-FB-relative: m16c dsp:8[fb] relative bit xmode */
2466 /* bit16-16-8-An-relative: m16c dsp:8[An] relative bit xmode */
2467 /* bit16-16-16-An-relative: m16c dsp:16[An] relative bit xmode */
2468 /* bit32-16-11-SB-relative-Unprefixed: m32c bit,base:11[sb] relative bit */
2469 /* bit32-16-19-SB-relative-Unprefixed: m32c bit,base:19[sb] relative bit */
2470 /* bit32-16-11-FB-relative-Unprefixed: m32c bit,base:11[fb] relative bit */
2471 /* bit32-16-19-FB-relative-Unprefixed: m32c bit,base:19[fb] relative bit */
2472 /* bit32-16-11-An-relative-Unprefixed: m32c bit,base:11[An] relative bit */
2473 /* bit32-16-19-An-relative-Unprefixed: m32c bit,base:19[An] relative bit */
2474 /* bit32-16-27-An-relative-Unprefixed: m32c bit,base:27[An] relative bit */
2475 /* bit32-24-11-SB-relative-Prefixed: m32c bit,base:11[sb] relative bit */
2476 /* bit32-24-19-SB-relative-Prefixed: m32c bit,base:19[sb] relative bit */
2477 /* bit32-24-11-FB-relative-Prefixed: m32c bit,base:11[fb] relative bit */
2478 /* bit32-24-19-FB-relative-Prefixed: m32c bit,base:19[fb] relative bit */
2479 /* bit32-24-11-An-relative-Prefixed: m32c bit,base:11[An] relative bit */
2480 /* bit32-24-19-An-relative-Prefixed: m32c bit,base:19[An] relative bit */
2481 /* bit32-24-27-An-relative-Prefixed: m32c bit,base:27[An] relative bit */
2482 /* bit16-11-SB-relative-S: m16c bit,base:11[sb] relative bit */
2483 /* Rn16-push-S-derived: m16c r0[lh] for push,pop short version */
2484 /* An16-push-S-derived: m16c r0[lh] for push,pop short version */
2485 /* bit16-16-16-absolute: m16c absolute address */
2486 /* bit32-16-19-absolute-Unprefixed: m32c absolute address bit */
2487 /* bit32-16-27-absolute-Unprefixed: m32c absolute address bit */
2488 /* bit32-24-19-absolute-Prefixed: m32c absolute address bit */
2489 /* bit32-24-27-absolute-Prefixed: m32c absolute address bit */
2490 /* dst16-3-S-R0l-direct-QI: m16c R0l direct QI */
2491 /* dst16-3-S-R0h-direct-QI: m16c R0h direct QI */
2492 /* dst16-3-S-8-8-SB-relative-QI: m16c SB relative QI */
2493 /* dst16-3-S-8-8-FB-relative-QI: m16c FB relative QI */
2494 /* dst16-3-S-8-16-absolute-QI: m16c absolute address QI */
2495 /* dst16-3-S-16-8-SB-relative-QI: m16c SB relative QI */
2496 /* dst16-3-S-16-8-FB-relative-QI: m16c FB relative QI */
2497 /* dst16-3-S-16-16-absolute-QI: m16c absolute address QI */
2498 /* srcdst16-r0l-r0h-S-derived: m16c r0l/r0h operand for short format insns */
2499 /* dst32-2-S-R0l-direct-QI: m32c R0l direct QI */
2500 /* dst32-2-S-R0-direct-HI: m32c R0 direct HI */
2501 /* dst32-1-S-A0-direct-HI: m32c A0 direct HI */
2502 /* dst32-1-S-A1-direct-HI: m32c A1 direct HI */
2503 /* dst32-2-S-8-SB-relative-QI: m32c SB relative for short binary insns */
2504 /* dst32-2-S-8-FB-relative-QI: m32c FB relative for short binary insns */
2505 /* dst32-2-S-16-absolute-QI: m32c absolute address for short binary insns */
2506 /* dst32-2-S-8-SB-relative-HI: m32c SB relative for short binary insns */
2507 /* dst32-2-S-8-FB-relative-HI: m32c FB relative for short binary insns */
2508 /* dst32-2-S-16-absolute-HI: m32c absolute address for short binary insns */
2509 /* dst32-2-S-8-SB-relative-SI: m32c SB relative for short binary insns */
2510 /* dst32-2-S-8-FB-relative-SI: m32c FB relative for short binary insns */
2511 /* dst32-2-S-16-absolute-SI: m32c absolute address for short binary insns */
2512 /* src16-basic-QI: m16c source operand of size QI with no additional fields */
2513 /* src16-basic-HI: m16c source operand of size HI with no additional fields */
2514 /* src32-basic-Unprefixed-QI: m32c destination operand of size QI with no additional fields */
2515 /* src32-basic-Prefixed-QI: m32c destination operand of size QI with no additional fields */
2516 /* src32-basic-Unprefixed-HI: m32c destination operand of size HI with no additional fields */
2517 /* src32-basic-Prefixed-HI: m32c destination operand of size HI with no additional fields */
2518 /* src32-basic-Unprefixed-SI: m32c destination operand of size SI with no additional fields */
2519 /* src32-basic-Prefixed-SI: m32c destination operand of size SI with no additional fields */
2520 /* src32-basic-ExtPrefixed-QI: m32c source operand of size QI with no additional fields */
2521 /* src16-16-8-QI: m16c source operand of size QI with additional 8 bit fields at offset 16 */
2522 /* src16-16-16-QI: m16c source operand of size QI with additional 16 bit fields at offset 16 */
2523 /* src16-16-8-HI: m16c source operand of size HI with additional 8 bit fields at offset 16 */
2524 /* src16-16-16-HI: m16c source operand of size HI with additional 16 bit fields at offset 16 */
2525 /* src32-16-8-Unprefixed-QI: m32c source operand of size QI with additional 8 bit fields at offset 16 */
2526 /* src32-16-16-Unprefixed-QI: m32c source operand of size QI with additional 16 bit fields at offset 16 */
2527 /* src32-16-24-Unprefixed-QI: m32c source operand of size QI with additional 24 bit fields at offset 16 */
2528 /* src32-16-8-Unprefixed-HI: m32c source operand of size HI with additional 8 bit fields at offset 16 */
2529 /* src32-16-16-Unprefixed-HI: m32c source operand of size HI with additional 16 bit fields at offset 16 */
2530 /* src32-16-24-Unprefixed-HI: m32c source operand of size HI with additional 24 bit fields at offset 16 */
2531 /* src32-16-8-Unprefixed-SI: m32c source operand of size SI with additional 8 bit fields at offset 16 */
2532 /* src32-16-16-Unprefixed-SI: m32c source operand of size SI with additional 16 bit fields at offset 16 */
2533 /* src32-16-24-Unprefixed-SI: m32c source operand of size SI with additional 24 bit fields at offset 16 */
2534 /* src32-24-8-Prefixed-QI: m32c source operand of size QI with additional 8 bit fields at offset 24 */
2535 /* src32-24-16-Prefixed-QI: m32c source operand of size QI with additional 16 bit fields at offset 16 */
2536 /* src32-24-24-Prefixed-QI: m32c source operand of size QI with additional 24 bit fields at offset 16 */
2537 /* src32-24-8-Prefixed-HI: m32c source operand of size HI with additional 8 bit fields at offset 24 */
2538 /* src32-24-16-Prefixed-HI: m32c source operand of size HI with additional 16 bit fields at offset 16 */
2539 /* src32-24-24-Prefixed-HI: m32c source operand of size HI with additional 24 bit fields at offset 16 */
2540 /* src32-24-8-Prefixed-SI: m32c source operand of size SI with additional 8 bit fields at offset 24 */
2541 /* src32-24-16-Prefixed-SI: m32c source operand of size SI with additional 16 bit fields at offset 16 */
2542 /* src32-24-24-Prefixed-SI: m32c source operand of size SI with additional 24 bit fields at offset 16 */
2543 /* dst16-basic-QI: m16c destination operand of size QI with no additional fields */
2544 /* dst16-basic-HI: m16c destination operand of size HI with no additional fields */
2545 /* dst16-basic-SI: m16c destination operand of size SI with no additional fields */
2546 /* dst32-basic-Unprefixed-QI: m32c destination operand of size QI with no additional fields */
2547 /* dst32-basic-Prefixed-QI: m32c destination operand of size QI with no additional fields */
2548 /* dst32-basic-Unprefixed-HI: m32c destination operand of size HI with no additional fields */
2549 /* dst32-basic-Prefixed-HI: m32c destination operand of size HI with no additional fields */
2550 /* dst32-basic-Unprefixed-SI: m32c destination operand of size SI with no additional fields */
2551 /* dst32-basic-Prefixed-SI: m32c destination operand of size SI with no additional fields */
2552 /* dst16-16-QI: m16c destination operand of size QI with additional fields at offset 16 */
2553 /* dst16-16-8-QI: m16c destination operand of size QI with additional fields at offset 16 */
2554 /* dst16-16-16-QI: m16c destination operand of size QI with additional fields at offset 16 */
2555 /* dst16-16-HI: m16c destination operand of size HI with additional fields at offset 16 */
2556 /* dst16-16-8-HI: m16c destination operand of size HI with additional fields at offset 16 */
2557 /* dst16-16-16-HI: m16c destination operand of size HI with additional fields at offset 16 */
2558 /* dst16-16-SI: m16c destination operand of size SI with additional fields at offset 16 */
2559 /* dst16-16-8-SI: m16c destination operand of size SI with additional fields at offset 16 */
2560 /* dst16-16-16-SI: m16c destination operand of size SI with additional fields at offset 16 */
2561 /* dst16-16-Ext-QI: m16c destination operand of size QI for 'ext' insns with additional fields at offset 16 */
2562 /* dst16-An-indirect-Mova-HI: m16c addressof An indirect destination HI */
2563 /* dst16-16-8-An-relative-Mova-HI: m16c addressof dsp:8[An] relative destination HI */
2564 /* dst16-16-16-An-relative-Mova-HI: m16c addressof dsp:16[An] relative destination HI */
2565 /* dst16-16-8-SB-relative-Mova-HI: m16c addressof dsp:8[sb] relative destination HI */
2566 /* dst16-16-16-SB-relative-Mova-HI: m16c addressof dsp:16[sb] relative destination HI */
2567 /* dst16-16-8-FB-relative-Mova-HI: m16c addressof dsp:8[fb] relative destination HI */
2568 /* dst16-16-16-absolute-Mova-HI: m16c addressof absolute address HI */
2569 /* dst16-16-Mova-HI: m16c addressof destination operand of size HI with additional fields at offset 16 */
2570 /* dst32-An-indirect-Unprefixed-Mova-SI: m32c addressof An indirect destination SI */
2571 /* dst32-16-8-An-relative-Unprefixed-Mova-SI: m32c addressof dsp:8[An] relative destination SI */
2572 /* dst32-16-16-An-relative-Unprefixed-Mova-SI: m32c addressof dsp:16[An] relative destination SI */
2573 /* dst32-16-24-An-relative-Unprefixed-Mova-SI: addressof m32c dsp:16[An] relative destination SI */
2574 /* dst32-16-8-SB-relative-Unprefixed-Mova-SI: m32c addressof dsp:8[sb] relative destination SI */
2575 /* dst32-16-16-SB-relative-Unprefixed-Mova-SI: m32c addressof dsp:16[sb] relative destination SI */
2576 /* dst32-16-8-FB-relative-Unprefixed-Mova-SI: m32c addressof dsp:8[fb] relative destination SI */
2577 /* dst32-16-16-FB-relative-Unprefixed-Mova-SI: m32c addressof dsp:16[fb] relative destination SI */
2578 /* dst32-16-16-absolute-Unprefixed-Mova-SI: m32c addressof absolute address SI */
2579 /* dst32-16-24-absolute-Unprefixed-Mova-SI: m32c addressof absolute address SI */
2580 /* dst32-16-Unprefixed-Mova-SI: m32c addressof destination operand of size SI with additional fields at offset 16 */
2581 /* dst32-16-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 16 */
2582 /* dst32-16-8-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 16 */
2583 /* dst32-16-16-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 16 */
2584 /* dst32-16-24-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 16 */
2585 /* dst32-16-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 16 */
2586 /* dst32-16-8-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 16 */
2587 /* dst32-16-16-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 16 */
2588 /* dst32-16-24-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 16 */
2589 /* dst32-16-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 16 */
2590 /* dst32-16-8-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 16 */
2591 /* dst32-16-16-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 16 */
2592 /* dst32-16-24-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 16 */
2593 /* dst32-16-ExtUnprefixed-QI: m32c destination operand of size QI with additional fields at offset 16 */
2594 /* dst32-16-ExtUnprefixed-HI: m32c destination operand of size HI with additional fields at offset 16 */
2595 /* dst32-16-Unprefixed-Mulex-HI: m32c destination operand of size HI with additional fields at offset 16 */
2596 /* dst16-24-QI: m16c destination operand of size QI with additional fields at offset 24 */
2597 /* dst16-24-HI: m16c destination operand of size HI with additional fields at offset 24 */
2598 /* dst32-24-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 24 */
2599 /* dst32-24-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 24 */
2600 /* dst32-24-8-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 24 */
2601 /* dst32-24-16-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 24 */
2602 /* dst32-24-24-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 24 */
2603 /* dst32-24-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 24 */
2604 /* dst32-24-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 24 */
2605 /* dst32-24-8-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 24 */
2606 /* dst32-24-16-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 24 */
2607 /* dst32-24-24-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 24 */
2608 /* dst32-24-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 24 */
2609 /* dst32-24-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 24 */
2610 /* dst32-24-8-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 24 */
2611 /* dst32-24-16-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 24 */
2612 /* dst32-24-24-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 24 */
2613 /* dst16-32-QI: m16c destination operand of size QI with additional fields at offset 32 */
2614 /* dst16-32-HI: m16c destination operand of size HI with additional fields at offset 32 */
2615 /* dst32-32-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 32 */
2616 /* dst32-32-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 32 */
2617 /* dst32-32-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 32 */
2618 /* dst32-32-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 32 */
2619 /* dst32-32-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 32 */
2620 /* dst32-32-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 32 */
2621 /* dst32-40-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 32 */
2622 /* dst32-40-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 32 */
2623 /* dst32-40-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 32 */
2624 /* dst32-40-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 32 */
2625 /* dst32-40-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 32 */
2626 /* dst32-40-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 32 */
2627 /* dst32-48-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 32 */
2628 /* dst32-48-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 32 */
2629 /* dst32-48-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 32 */
2630 /* bit16-16: m16c bit operand with possible additional fields at offset 24 */
2631 /* bit16-16-basic: m16c bit operand with no additional fields */
2632 /* bit16-16-8: m16c bit operand with possible additional fields at offset 24 */
2633 /* bit16-16-16: m16c bit operand with possible additional fields at offset 24 */
2634 /* bit32-16-Unprefixed: m32c bit operand with possible additional fields at offset 24 */
2635 /* bit32-24-Prefixed: m32c bit operand with possible additional fields at offset 24 */
2636 /* bit32-basic-Unprefixed: m32c bit operand with no additional fields */
2637 /* bit32-16-8-Unprefixed: m32c bit operand with 8 bit additional fields */
2638 /* bit32-16-16-Unprefixed: m32c bit operand with 16 bit additional fields */
2639 /* bit32-16-24-Unprefixed: m32c bit operand with 24 bit additional fields */
2640 /* src16-2-S: m16c source operand of size QI for short format insns */
2641 /* src32-2-S-QI: m32c source operand of size QI for short format insns */
2642 /* src32-2-S-HI: m32c source operand of size QI for short format insns */
2643 /* Dst16-3-S-8: m16c destination operand of size QI for short format insns */
2644 /* Dst16-3-S-16: m16c destination operand of size QI for short format insns */
2645 /* srcdst16-r0l-r0h-S: m16c r0l/r0h operand of size QI for short format insns */
2646 /* dst32-2-S-basic-QI: m32c r0l operand of size QI for short format binary insns */
2647 /* dst32-2-S-basic-HI: m32c r0 operand of size HI for short format binary insns */
2648 /* dst32-2-S-8-QI: m32c operand of size  */
2649 /* dst32-2-S-16-QI: m32c operand of size  */
2650 /* dst32-2-S-8-HI: m32c operand of size  */
2651 /* dst32-2-S-16-HI: m32c operand of size  */
2652 /* dst32-2-S-8-SI: m32c operand of size  */
2653 /* dst32-2-S-16-SI: m32c operand of size  */
2654 /* dst32-an-S: m32c An operand for short format binary insns */
2655 /* bit16-11-S: m16c bit operand for short format insns */
2656 /* Rn16-push-S-anyof: m16c bit operand for short format insns */
2657 /* An16-push-S-anyof: m16c bit operand for short format insns */
2658 /* sentinel */
2659   { 0, 0, 0, 0, 0,
2660     { 0, { (const PTR) 0 } },
2661     { 0, { 0 } } }
2662 };
2663
2664 #undef A
2665
2666
2667 /* The instruction table.  */
2668
2669 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
2670 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
2671 #define A(a) (1 << CGEN_INSN_##a)
2672 #else
2673 #define A(a) (1 << CGEN_INSN_/**/a)
2674 #endif
2675
2676 static const CGEN_IBASE m32c_cgen_insn_table[MAX_INSNS] =
2677 {
2678   /* Special null first entry.
2679      A `num' value of zero is thus invalid.
2680      Also, the special `invalid' insn resides here.  */
2681   { 0, 0, 0, 0, {0, {0}} },
2682 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
2683   {
2684     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 32,
2685     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2686   },
2687 /* extz ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
2688   {
2689     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 32,
2690     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2691   },
2692 /* extz ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
2693   {
2694     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 32,
2695     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2696   },
2697 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
2698   {
2699     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 32,
2700     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2701   },
2702 /* extz ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
2703   {
2704     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 32,
2705     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2706   },
2707 /* extz ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
2708   {
2709     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 32,
2710     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2711   },
2712 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
2713   {
2714     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 32,
2715     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2716   },
2717 /* extz ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
2718   {
2719     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 32,
2720     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2721   },
2722 /* extz ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
2723   {
2724     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 32,
2725     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2726   },
2727 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
2728   {
2729     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "extz", 40,
2730     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2731   },
2732 /* extz ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
2733   {
2734     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "extz", 40,
2735     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2736   },
2737 /* extz ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
2738   {
2739     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "extz", 40,
2740     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2741   },
2742 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
2743   {
2744     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "extz", 48,
2745     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2746   },
2747 /* extz ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
2748   {
2749     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "extz", 48,
2750     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2751   },
2752 /* extz ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
2753   {
2754     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "extz", 48,
2755     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2756   },
2757 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
2758   {
2759     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "extz", 56,
2760     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2761   },
2762 /* extz ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
2763   {
2764     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "extz", 56,
2765     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2766   },
2767 /* extz ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
2768   {
2769     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "extz", 56,
2770     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2771   },
2772 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
2773   {
2774     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "extz", 40,
2775     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2776   },
2777 /* extz ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
2778   {
2779     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "extz", 40,
2780     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2781   },
2782 /* extz ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
2783   {
2784     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "extz", 40,
2785     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2786   },
2787 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
2788   {
2789     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "extz", 48,
2790     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2791   },
2792 /* extz ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
2793   {
2794     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "extz", 48,
2795     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2796   },
2797 /* extz ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
2798   {
2799     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "extz", 48,
2800     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2801   },
2802 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
2803   {
2804     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "extz", 40,
2805     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2806   },
2807 /* extz ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
2808   {
2809     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "extz", 40,
2810     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2811   },
2812 /* extz ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
2813   {
2814     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "extz", 40,
2815     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2816   },
2817 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
2818   {
2819     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "extz", 48,
2820     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2821   },
2822 /* extz ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
2823   {
2824     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "extz", 48,
2825     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2826   },
2827 /* extz ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
2828   {
2829     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "extz", 48,
2830     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2831   },
2832 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
2833   {
2834     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "extz", 48,
2835     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2836   },
2837 /* extz ${Dsp-24-u8}[sb],${Dsp-32-u16} */
2838   {
2839     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "extz", 48,
2840     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2841   },
2842 /* extz ${Dsp-24-s8}[fb],${Dsp-32-u16} */
2843   {
2844     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "extz", 48,
2845     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2846   },
2847 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
2848   {
2849     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "extz", 56,
2850     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2851   },
2852 /* extz ${Dsp-24-u8}[sb],${Dsp-32-u24} */
2853   {
2854     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "extz", 56,
2855     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2856   },
2857 /* extz ${Dsp-24-s8}[fb],${Dsp-32-u24} */
2858   {
2859     M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "extz", 56,
2860     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2861   },
2862 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
2863   {
2864     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 40,
2865     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2866   },
2867 /* extz ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
2868   {
2869     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 40,
2870     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2871   },
2872 /* extz ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
2873   {
2874     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 40,
2875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2876   },
2877 /* extz ${Dsp-24-u16},$Dst32RnPrefixedHI */
2878   {
2879     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 40,
2880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2881   },
2882 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
2883   {
2884     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 40,
2885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2886   },
2887 /* extz ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
2888   {
2889     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 40,
2890     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2891   },
2892 /* extz ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
2893   {
2894     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 40,
2895     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2896   },
2897 /* extz ${Dsp-24-u16},$Dst32AnPrefixedHI */
2898   {
2899     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 40,
2900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2901   },
2902 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
2903   {
2904     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 40,
2905     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2906   },
2907 /* extz ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
2908   {
2909     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 40,
2910     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2911   },
2912 /* extz ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
2913   {
2914     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 40,
2915     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2916   },
2917 /* extz ${Dsp-24-u16},[$Dst32AnPrefixed] */
2918   {
2919     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 40,
2920     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2921   },
2922 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
2923   {
2924     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "extz", 48,
2925     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2926   },
2927 /* extz ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
2928   {
2929     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "extz", 48,
2930     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2931   },
2932 /* extz ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
2933   {
2934     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "extz", 48,
2935     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2936   },
2937 /* extz ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
2938   {
2939     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "extz", 48,
2940     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2941   },
2942 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
2943   {
2944     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "extz", 56,
2945     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2946   },
2947 /* extz ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
2948   {
2949     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "extz", 56,
2950     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2951   },
2952 /* extz ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
2953   {
2954     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "extz", 56,
2955     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2956   },
2957 /* extz ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
2958   {
2959     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "extz", 56,
2960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2961   },
2962 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
2963   {
2964     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "extz", 64,
2965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2966   },
2967 /* extz ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
2968   {
2969     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "extz", 64,
2970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2971   },
2972 /* extz ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
2973   {
2974     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "extz", 64,
2975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2976   },
2977 /* extz ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
2978   {
2979     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "extz", 64,
2980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2981   },
2982 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
2983   {
2984     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "extz", 48,
2985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2986   },
2987 /* extz ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
2988   {
2989     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "extz", 48,
2990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2991   },
2992 /* extz ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
2993   {
2994     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "extz", 48,
2995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2996   },
2997 /* extz ${Dsp-24-u16},${Dsp-40-u8}[sb] */
2998   {
2999     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "extz", 48,
3000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3001   },
3002 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
3003   {
3004     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "extz", 56,
3005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3006   },
3007 /* extz ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
3008   {
3009     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "extz", 56,
3010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3011   },
3012 /* extz ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
3013   {
3014     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "extz", 56,
3015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3016   },
3017 /* extz ${Dsp-24-u16},${Dsp-40-u16}[sb] */
3018   {
3019     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "extz", 56,
3020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3021   },
3022 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
3023   {
3024     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "extz", 48,
3025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3026   },
3027 /* extz ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
3028   {
3029     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "extz", 48,
3030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3031   },
3032 /* extz ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
3033   {
3034     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "extz", 48,
3035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3036   },
3037 /* extz ${Dsp-24-u16},${Dsp-40-s8}[fb] */
3038   {
3039     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "extz", 48,
3040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3041   },
3042 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
3043   {
3044     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "extz", 56,
3045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3046   },
3047 /* extz ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
3048   {
3049     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "extz", 56,
3050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3051   },
3052 /* extz ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
3053   {
3054     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "extz", 56,
3055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3056   },
3057 /* extz ${Dsp-24-u16},${Dsp-40-s16}[fb] */
3058   {
3059     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "extz", 56,
3060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3061   },
3062 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
3063   {
3064     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "extz", 56,
3065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3066   },
3067 /* extz ${Dsp-24-u16}[sb],${Dsp-40-u16} */
3068   {
3069     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "extz", 56,
3070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3071   },
3072 /* extz ${Dsp-24-s16}[fb],${Dsp-40-u16} */
3073   {
3074     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "extz", 56,
3075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3076   },
3077 /* extz ${Dsp-24-u16},${Dsp-40-u16} */
3078   {
3079     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "extz", 56,
3080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3081   },
3082 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
3083   {
3084     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "extz", 64,
3085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3086   },
3087 /* extz ${Dsp-24-u16}[sb],${Dsp-40-u24} */
3088   {
3089     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "extz", 64,
3090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3091   },
3092 /* extz ${Dsp-24-s16}[fb],${Dsp-40-u24} */
3093   {
3094     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "extz", 64,
3095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3096   },
3097 /* extz ${Dsp-24-u16},${Dsp-40-u24} */
3098   {
3099     M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "extz", 64,
3100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3101   },
3102 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
3103   {
3104     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 48,
3105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3106   },
3107 /* extz ${Dsp-24-u24},$Dst32RnPrefixedHI */
3108   {
3109     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 48,
3110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3111   },
3112 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
3113   {
3114     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 48,
3115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3116   },
3117 /* extz ${Dsp-24-u24},$Dst32AnPrefixedHI */
3118   {
3119     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 48,
3120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3121   },
3122 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
3123   {
3124     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 48,
3125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3126   },
3127 /* extz ${Dsp-24-u24},[$Dst32AnPrefixed] */
3128   {
3129     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 48,
3130     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3131   },
3132 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
3133   {
3134     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-HI", "extz", 56,
3135     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3136   },
3137 /* extz ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
3138   {
3139     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-HI", "extz", 56,
3140     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3141   },
3142 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
3143   {
3144     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-HI", "extz", 64,
3145     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3146   },
3147 /* extz ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
3148   {
3149     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-HI", "extz", 64,
3150     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3151   },
3152 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
3153   {
3154     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-HI", "extz", 72,
3155     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3156   },
3157 /* extz ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
3158   {
3159     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-HI", "extz", 72,
3160     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3161   },
3162 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
3163   {
3164     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-HI", "extz", 56,
3165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3166   },
3167 /* extz ${Dsp-24-u24},${Dsp-48-u8}[sb] */
3168   {
3169     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-HI", "extz", 56,
3170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3171   },
3172 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
3173   {
3174     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-HI", "extz", 64,
3175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3176   },
3177 /* extz ${Dsp-24-u24},${Dsp-48-u16}[sb] */
3178   {
3179     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-HI", "extz", 64,
3180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3181   },
3182 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
3183   {
3184     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-HI", "extz", 56,
3185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3186   },
3187 /* extz ${Dsp-24-u24},${Dsp-48-s8}[fb] */
3188   {
3189     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-HI", "extz", 56,
3190     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3191   },
3192 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
3193   {
3194     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-HI", "extz", 64,
3195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3196   },
3197 /* extz ${Dsp-24-u24},${Dsp-48-s16}[fb] */
3198   {
3199     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-HI", "extz", 64,
3200     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3201   },
3202 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
3203   {
3204     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-HI", "extz", 64,
3205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3206   },
3207 /* extz ${Dsp-24-u24},${Dsp-48-u16} */
3208   {
3209     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-HI", "extz", 64,
3210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3211   },
3212 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
3213   {
3214     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-HI", "extz", 72,
3215     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3216   },
3217 /* extz ${Dsp-24-u24},${Dsp-48-u24} */
3218   {
3219     M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-HI", "extz", 72,
3220     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3221   },
3222 /* extz $Src32RnPrefixedQI,$Dst32RnPrefixedHI */
3223   {
3224     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 24,
3225     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3226   },
3227 /* extz [$Src32AnPrefixed],$Dst32RnPrefixedHI */
3228   {
3229     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 24,
3230     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3231   },
3232 /* extz $Src32RnPrefixedQI,$Dst32AnPrefixedHI */
3233   {
3234     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 24,
3235     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3236   },
3237 /* extz [$Src32AnPrefixed],$Dst32AnPrefixedHI */
3238   {
3239     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 24,
3240     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3241   },
3242 /* extz $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
3243   {
3244     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 24,
3245     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3246   },
3247 /* extz [$Src32AnPrefixed],[$Dst32AnPrefixed] */
3248   {
3249     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 24,
3250     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3251   },
3252 /* extz $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
3253   {
3254     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-HI", "extz", 32,
3255     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3256   },
3257 /* extz [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
3258   {
3259     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-HI", "extz", 32,
3260     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3261   },
3262 /* extz $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
3263   {
3264     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-HI", "extz", 40,
3265     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3266   },
3267 /* extz [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
3268   {
3269     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-HI", "extz", 40,
3270     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3271   },
3272 /* extz $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
3273   {
3274     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-HI", "extz", 48,
3275     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3276   },
3277 /* extz [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
3278   {
3279     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-HI", "extz", 48,
3280     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3281   },
3282 /* extz $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
3283   {
3284     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-HI", "extz", 32,
3285     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3286   },
3287 /* extz [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
3288   {
3289     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-HI", "extz", 32,
3290     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3291   },
3292 /* extz $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
3293   {
3294     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-HI", "extz", 40,
3295     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3296   },
3297 /* extz [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
3298   {
3299     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-HI", "extz", 40,
3300     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3301   },
3302 /* extz $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
3303   {
3304     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-HI", "extz", 32,
3305     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3306   },
3307 /* extz [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
3308   {
3309     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-HI", "extz", 32,
3310     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3311   },
3312 /* extz $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
3313   {
3314     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-HI", "extz", 40,
3315     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3316   },
3317 /* extz [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
3318   {
3319     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-HI", "extz", 40,
3320     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3321   },
3322 /* extz $Src32RnPrefixedQI,${Dsp-24-u16} */
3323   {
3324     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-HI", "extz", 40,
3325     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3326   },
3327 /* extz [$Src32AnPrefixed],${Dsp-24-u16} */
3328   {
3329     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-HI", "extz", 40,
3330     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3331   },
3332 /* extz $Src32RnPrefixedQI,${Dsp-24-u24} */
3333   {
3334     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-HI", "extz", 48,
3335     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3336   },
3337 /* extz [$Src32AnPrefixed],${Dsp-24-u24} */
3338   {
3339     M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-HI", "extz", 48,
3340     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3341   },
3342 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
3343   {
3344     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 32,
3345     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3346   },
3347 /* exts.b ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
3348   {
3349     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 32,
3350     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3351   },
3352 /* exts.b ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
3353   {
3354     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 32,
3355     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3356   },
3357 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
3358   {
3359     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 32,
3360     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3361   },
3362 /* exts.b ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
3363   {
3364     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 32,
3365     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3366   },
3367 /* exts.b ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
3368   {
3369     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 32,
3370     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3371   },
3372 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
3373   {
3374     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 32,
3375     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3376   },
3377 /* exts.b ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
3378   {
3379     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 32,
3380     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3381   },
3382 /* exts.b ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
3383   {
3384     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 32,
3385     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3386   },
3387 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
3388   {
3389     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "exts.b", 40,
3390     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3391   },
3392 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
3393   {
3394     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "exts.b", 40,
3395     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3396   },
3397 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
3398   {
3399     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "exts.b", 40,
3400     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3401   },
3402 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
3403   {
3404     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "exts.b", 48,
3405     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3406   },
3407 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
3408   {
3409     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "exts.b", 48,
3410     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3411   },
3412 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
3413   {
3414     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "exts.b", 48,
3415     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3416   },
3417 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
3418   {
3419     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "exts.b", 56,
3420     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3421   },
3422 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
3423   {
3424     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "exts.b", 56,
3425     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3426   },
3427 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
3428   {
3429     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "exts.b", 56,
3430     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3431   },
3432 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
3433   {
3434     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "exts.b", 40,
3435     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3436   },
3437 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
3438   {
3439     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "exts.b", 40,
3440     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3441   },
3442 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
3443   {
3444     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "exts.b", 40,
3445     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3446   },
3447 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
3448   {
3449     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "exts.b", 48,
3450     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3451   },
3452 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
3453   {
3454     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "exts.b", 48,
3455     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3456   },
3457 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
3458   {
3459     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "exts.b", 48,
3460     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3461   },
3462 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
3463   {
3464     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "exts.b", 40,
3465     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3466   },
3467 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
3468   {
3469     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "exts.b", 40,
3470     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3471   },
3472 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
3473   {
3474     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "exts.b", 40,
3475     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3476   },
3477 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
3478   {
3479     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "exts.b", 48,
3480     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3481   },
3482 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
3483   {
3484     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "exts.b", 48,
3485     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3486   },
3487 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
3488   {
3489     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "exts.b", 48,
3490     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3491   },
3492 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
3493   {
3494     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "exts.b", 48,
3495     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3496   },
3497 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u16} */
3498   {
3499     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "exts.b", 48,
3500     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3501   },
3502 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u16} */
3503   {
3504     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "exts.b", 48,
3505     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3506   },
3507 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
3508   {
3509     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "exts.b", 56,
3510     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3511   },
3512 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u24} */
3513   {
3514     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "exts.b", 56,
3515     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3516   },
3517 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u24} */
3518   {
3519     M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "exts.b", 56,
3520     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3521   },
3522 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
3523   {
3524     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 40,
3525     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3526   },
3527 /* exts.b ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
3528   {
3529     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 40,
3530     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3531   },
3532 /* exts.b ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
3533   {
3534     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 40,
3535     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3536   },
3537 /* exts.b ${Dsp-24-u16},$Dst32RnPrefixedHI */
3538   {
3539     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 40,
3540     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3541   },
3542 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
3543   {
3544     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 40,
3545     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3546   },
3547 /* exts.b ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
3548   {
3549     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 40,
3550     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3551   },
3552 /* exts.b ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
3553   {
3554     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 40,
3555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3556   },
3557 /* exts.b ${Dsp-24-u16},$Dst32AnPrefixedHI */
3558   {
3559     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 40,
3560     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3561   },
3562 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
3563   {
3564     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 40,
3565     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3566   },
3567 /* exts.b ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
3568   {
3569     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 40,
3570     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3571   },
3572 /* exts.b ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
3573   {
3574     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 40,
3575     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3576   },
3577 /* exts.b ${Dsp-24-u16},[$Dst32AnPrefixed] */
3578   {
3579     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 40,
3580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3581   },
3582 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
3583   {
3584     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "exts.b", 48,
3585     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3586   },
3587 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
3588   {
3589     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "exts.b", 48,
3590     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3591   },
3592 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
3593   {
3594     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "exts.b", 48,
3595     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3596   },
3597 /* exts.b ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
3598   {
3599     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "exts.b", 48,
3600     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3601   },
3602 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
3603   {
3604     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "exts.b", 56,
3605     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3606   },
3607 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
3608   {
3609     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "exts.b", 56,
3610     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3611   },
3612 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
3613   {
3614     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "exts.b", 56,
3615     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3616   },
3617 /* exts.b ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
3618   {
3619     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "exts.b", 56,
3620     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3621   },
3622 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
3623   {
3624     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "exts.b", 64,
3625     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3626   },
3627 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
3628   {
3629     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "exts.b", 64,
3630     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3631   },
3632 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
3633   {
3634     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "exts.b", 64,
3635     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3636   },
3637 /* exts.b ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
3638   {
3639     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "exts.b", 64,
3640     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3641   },
3642 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
3643   {
3644     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "exts.b", 48,
3645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3646   },
3647 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
3648   {
3649     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "exts.b", 48,
3650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3651   },
3652 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
3653   {
3654     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "exts.b", 48,
3655     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3656   },
3657 /* exts.b ${Dsp-24-u16},${Dsp-40-u8}[sb] */
3658   {
3659     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "exts.b", 48,
3660     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3661   },
3662 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
3663   {
3664     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "exts.b", 56,
3665     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3666   },
3667 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
3668   {
3669     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "exts.b", 56,
3670     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3671   },
3672 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
3673   {
3674     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "exts.b", 56,
3675     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3676   },
3677 /* exts.b ${Dsp-24-u16},${Dsp-40-u16}[sb] */
3678   {
3679     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "exts.b", 56,
3680     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3681   },
3682 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
3683   {
3684     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "exts.b", 48,
3685     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3686   },
3687 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
3688   {
3689     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "exts.b", 48,
3690     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3691   },
3692 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
3693   {
3694     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "exts.b", 48,
3695     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3696   },
3697 /* exts.b ${Dsp-24-u16},${Dsp-40-s8}[fb] */
3698   {
3699     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "exts.b", 48,
3700     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3701   },
3702 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
3703   {
3704     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "exts.b", 56,
3705     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3706   },
3707 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
3708   {
3709     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "exts.b", 56,
3710     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3711   },
3712 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
3713   {
3714     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "exts.b", 56,
3715     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3716   },
3717 /* exts.b ${Dsp-24-u16},${Dsp-40-s16}[fb] */
3718   {
3719     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "exts.b", 56,
3720     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3721   },
3722 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
3723   {
3724     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "exts.b", 56,
3725     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3726   },
3727 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u16} */
3728   {
3729     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "exts.b", 56,
3730     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3731   },
3732 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u16} */
3733   {
3734     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "exts.b", 56,
3735     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3736   },
3737 /* exts.b ${Dsp-24-u16},${Dsp-40-u16} */
3738   {
3739     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "exts.b", 56,
3740     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3741   },
3742 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
3743   {
3744     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "exts.b", 64,
3745     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3746   },
3747 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u24} */
3748   {
3749     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "exts.b", 64,
3750     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3751   },
3752 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u24} */
3753   {
3754     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "exts.b", 64,
3755     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3756   },
3757 /* exts.b ${Dsp-24-u16},${Dsp-40-u24} */
3758   {
3759     M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "exts.b", 64,
3760     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3761   },
3762 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
3763   {
3764     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 48,
3765     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3766   },
3767 /* exts.b ${Dsp-24-u24},$Dst32RnPrefixedHI */
3768   {
3769     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 48,
3770     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3771   },
3772 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
3773   {
3774     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 48,
3775     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3776   },
3777 /* exts.b ${Dsp-24-u24},$Dst32AnPrefixedHI */
3778   {
3779     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 48,
3780     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3781   },
3782 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
3783   {
3784     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 48,
3785     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3786   },
3787 /* exts.b ${Dsp-24-u24},[$Dst32AnPrefixed] */
3788   {
3789     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 48,
3790     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3791   },
3792 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
3793   {
3794     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-HI", "exts.b", 56,
3795     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3796   },
3797 /* exts.b ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
3798   {
3799     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-HI", "exts.b", 56,
3800     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3801   },
3802 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
3803   {
3804     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-HI", "exts.b", 64,
3805     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3806   },
3807 /* exts.b ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
3808   {
3809     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-HI", "exts.b", 64,
3810     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3811   },
3812 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
3813   {
3814     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-HI", "exts.b", 72,
3815     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3816   },
3817 /* exts.b ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
3818   {
3819     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-HI", "exts.b", 72,
3820     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3821   },
3822 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
3823   {
3824     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-HI", "exts.b", 56,
3825     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3826   },
3827 /* exts.b ${Dsp-24-u24},${Dsp-48-u8}[sb] */
3828   {
3829     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-HI", "exts.b", 56,
3830     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3831   },
3832 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
3833   {
3834     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-HI", "exts.b", 64,
3835     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3836   },
3837 /* exts.b ${Dsp-24-u24},${Dsp-48-u16}[sb] */
3838   {
3839     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-HI", "exts.b", 64,
3840     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3841   },
3842 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
3843   {
3844     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-HI", "exts.b", 56,
3845     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3846   },
3847 /* exts.b ${Dsp-24-u24},${Dsp-48-s8}[fb] */
3848   {
3849     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-HI", "exts.b", 56,
3850     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3851   },
3852 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
3853   {
3854     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-HI", "exts.b", 64,
3855     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3856   },
3857 /* exts.b ${Dsp-24-u24},${Dsp-48-s16}[fb] */
3858   {
3859     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-HI", "exts.b", 64,
3860     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3861   },
3862 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
3863   {
3864     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-HI", "exts.b", 64,
3865     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3866   },
3867 /* exts.b ${Dsp-24-u24},${Dsp-48-u16} */
3868   {
3869     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-HI", "exts.b", 64,
3870     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3871   },
3872 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
3873   {
3874     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-HI", "exts.b", 72,
3875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3876   },
3877 /* exts.b ${Dsp-24-u24},${Dsp-48-u24} */
3878   {
3879     M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-HI", "exts.b", 72,
3880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3881   },
3882 /* exts.b $Src32RnPrefixedQI,$Dst32RnPrefixedHI */
3883   {
3884     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 24,
3885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3886   },
3887 /* exts.b [$Src32AnPrefixed],$Dst32RnPrefixedHI */
3888   {
3889     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 24,
3890     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3891   },
3892 /* exts.b $Src32RnPrefixedQI,$Dst32AnPrefixedHI */
3893   {
3894     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 24,
3895     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3896   },
3897 /* exts.b [$Src32AnPrefixed],$Dst32AnPrefixedHI */
3898   {
3899     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 24,
3900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3901   },
3902 /* exts.b $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
3903   {
3904     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 24,
3905     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3906   },
3907 /* exts.b [$Src32AnPrefixed],[$Dst32AnPrefixed] */
3908   {
3909     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 24,
3910     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3911   },
3912 /* exts.b $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
3913   {
3914     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-HI", "exts.b", 32,
3915     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3916   },
3917 /* exts.b [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
3918   {
3919     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-HI", "exts.b", 32,
3920     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3921   },
3922 /* exts.b $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
3923   {
3924     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-HI", "exts.b", 40,
3925     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3926   },
3927 /* exts.b [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
3928   {
3929     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-HI", "exts.b", 40,
3930     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3931   },
3932 /* exts.b $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
3933   {
3934     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-HI", "exts.b", 48,
3935     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3936   },
3937 /* exts.b [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
3938   {
3939     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-HI", "exts.b", 48,
3940     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3941   },
3942 /* exts.b $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
3943   {
3944     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-HI", "exts.b", 32,
3945     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3946   },
3947 /* exts.b [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
3948   {
3949     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-HI", "exts.b", 32,
3950     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3951   },
3952 /* exts.b $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
3953   {
3954     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-HI", "exts.b", 40,
3955     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3956   },
3957 /* exts.b [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
3958   {
3959     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-HI", "exts.b", 40,
3960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3961   },
3962 /* exts.b $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
3963   {
3964     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-HI", "exts.b", 32,
3965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3966   },
3967 /* exts.b [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
3968   {
3969     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-HI", "exts.b", 32,
3970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3971   },
3972 /* exts.b $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
3973   {
3974     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-HI", "exts.b", 40,
3975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3976   },
3977 /* exts.b [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
3978   {
3979     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-HI", "exts.b", 40,
3980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3981   },
3982 /* exts.b $Src32RnPrefixedQI,${Dsp-24-u16} */
3983   {
3984     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-HI", "exts.b", 40,
3985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3986   },
3987 /* exts.b [$Src32AnPrefixed],${Dsp-24-u16} */
3988   {
3989     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-HI", "exts.b", 40,
3990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3991   },
3992 /* exts.b $Src32RnPrefixedQI,${Dsp-24-u24} */
3993   {
3994     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-HI", "exts.b", 48,
3995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3996   },
3997 /* exts.b [$Src32AnPrefixed],${Dsp-24-u24} */
3998   {
3999     M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-HI", "exts.b", 48,
4000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4001   },
4002 /* exts.w $Dst32RnExtUnprefixedHI */
4003   {
4004     M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_RN_DIRECT_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-Rn-direct-ExtUnprefixed-HI", "exts.w", 16,
4005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4006   },
4007 /* exts.w $Dst32AnUnprefixedSI */
4008   {
4009     M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "exts32.w-16-ExtUnprefixed-dst32-An-direct-Unprefixed-SI", "exts.w", 16,
4010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4011   },
4012 /* exts.w [$Dst32AnExtUnprefixed] */
4013   {
4014     M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_AN_INDIRECT_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-An-indirect-ExtUnprefixed-HI", "exts.w", 16,
4015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4016   },
4017 /* exts.w ${Dsp-16-u8}[$Dst32AnExtUnprefixed] */
4018   {
4019     M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-8-An-relative-ExtUnprefixed-HI", "exts.w", 24,
4020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4021   },
4022 /* exts.w ${Dsp-16-u16}[$Dst32AnExtUnprefixed] */
4023   {
4024     M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-16-An-relative-ExtUnprefixed-HI", "exts.w", 32,
4025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4026   },
4027 /* exts.w ${Dsp-16-u24}[$Dst32AnExtUnprefixed] */
4028   {
4029     M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-24-An-relative-ExtUnprefixed-HI", "exts.w", 40,
4030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4031   },
4032 /* exts.w ${Dsp-16-u8}[sb] */
4033   {
4034     M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-8-SB-relative-ExtUnprefixed-HI", "exts.w", 24,
4035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4036   },
4037 /* exts.w ${Dsp-16-u16}[sb] */
4038   {
4039     M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-16-SB-relative-ExtUnprefixed-HI", "exts.w", 32,
4040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4041   },
4042 /* exts.w ${Dsp-16-s8}[fb] */
4043   {
4044     M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-8-FB-relative-ExtUnprefixed-HI", "exts.w", 24,
4045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4046   },
4047 /* exts.w ${Dsp-16-s16}[fb] */
4048   {
4049     M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-16-FB-relative-ExtUnprefixed-HI", "exts.w", 32,
4050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4051   },
4052 /* exts.w ${Dsp-16-u16} */
4053   {
4054     M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-16-absolute-ExtUnprefixed-HI", "exts.w", 32,
4055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4056   },
4057 /* exts.w ${Dsp-16-u24} */
4058   {
4059     M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-24-absolute-ExtUnprefixed-HI", "exts.w", 40,
4060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4061   },
4062 /* exts.b $Dst32RnExtUnprefixedQI */
4063   {
4064     M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_RN_DIRECT_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-Rn-direct-ExtUnprefixed-QI", "exts.b", 16,
4065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4066   },
4067 /* exts.b $Dst32AnUnprefixedHI */
4068   {
4069     M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "exts32.b-16-ExtUnprefixed-dst32-An-direct-Unprefixed-HI", "exts.b", 16,
4070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4071   },
4072 /* exts.b [$Dst32AnExtUnprefixed] */
4073   {
4074     M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_AN_INDIRECT_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-An-indirect-ExtUnprefixed-QI", "exts.b", 16,
4075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4076   },
4077 /* exts.b ${Dsp-16-u8}[$Dst32AnExtUnprefixed] */
4078   {
4079     M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-8-An-relative-ExtUnprefixed-QI", "exts.b", 24,
4080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4081   },
4082 /* exts.b ${Dsp-16-u16}[$Dst32AnExtUnprefixed] */
4083   {
4084     M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-16-An-relative-ExtUnprefixed-QI", "exts.b", 32,
4085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4086   },
4087 /* exts.b ${Dsp-16-u24}[$Dst32AnExtUnprefixed] */
4088   {
4089     M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-24-An-relative-ExtUnprefixed-QI", "exts.b", 40,
4090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4091   },
4092 /* exts.b ${Dsp-16-u8}[sb] */
4093   {
4094     M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-8-SB-relative-ExtUnprefixed-QI", "exts.b", 24,
4095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4096   },
4097 /* exts.b ${Dsp-16-u16}[sb] */
4098   {
4099     M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-16-SB-relative-ExtUnprefixed-QI", "exts.b", 32,
4100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4101   },
4102 /* exts.b ${Dsp-16-s8}[fb] */
4103   {
4104     M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-8-FB-relative-ExtUnprefixed-QI", "exts.b", 24,
4105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4106   },
4107 /* exts.b ${Dsp-16-s16}[fb] */
4108   {
4109     M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-16-FB-relative-ExtUnprefixed-QI", "exts.b", 32,
4110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4111   },
4112 /* exts.b ${Dsp-16-u16} */
4113   {
4114     M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-16-absolute-ExtUnprefixed-QI", "exts.b", 32,
4115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4116   },
4117 /* exts.b ${Dsp-16-u24} */
4118   {
4119     M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-24-absolute-ExtUnprefixed-QI", "exts.b", 40,
4120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4121   },
4122 /* exts.b $Dst16RnExtQI */
4123   {
4124     M32C_INSN_EXTS16_B_16_EXT_DST16_RN_DIRECT_EXT_QI, "exts16.b-16-Ext-dst16-Rn-direct-Ext-QI", "exts.b", 16,
4125     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
4126   },
4127 /* exts.b [$Dst16An] */
4128   {
4129     M32C_INSN_EXTS16_B_16_EXT_DST16_AN_INDIRECT_EXT_QI, "exts16.b-16-Ext-dst16-An-indirect-Ext-QI", "exts.b", 16,
4130     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
4131   },
4132 /* exts.b ${Dsp-16-u8}[$Dst16An] */
4133   {
4134     M32C_INSN_EXTS16_B_16_EXT_DST16_16_8_AN_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-8-An-relative-Ext-QI", "exts.b", 24,
4135     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
4136   },
4137 /* exts.b ${Dsp-16-u16}[$Dst16An] */
4138   {
4139     M32C_INSN_EXTS16_B_16_EXT_DST16_16_16_AN_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-16-An-relative-Ext-QI", "exts.b", 32,
4140     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
4141   },
4142 /* exts.b ${Dsp-16-u8}[sb] */
4143   {
4144     M32C_INSN_EXTS16_B_16_EXT_DST16_16_8_SB_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-8-SB-relative-Ext-QI", "exts.b", 24,
4145     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
4146   },
4147 /* exts.b ${Dsp-16-u16}[sb] */
4148   {
4149     M32C_INSN_EXTS16_B_16_EXT_DST16_16_16_SB_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-16-SB-relative-Ext-QI", "exts.b", 32,
4150     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
4151   },
4152 /* exts.b ${Dsp-16-s8}[fb] */
4153   {
4154     M32C_INSN_EXTS16_B_16_EXT_DST16_16_8_FB_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-8-FB-relative-Ext-QI", "exts.b", 24,
4155     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
4156   },
4157 /* exts.b ${Dsp-16-u16} */
4158   {
4159     M32C_INSN_EXTS16_B_16_EXT_DST16_16_16_ABSOLUTE_EXT_QI, "exts16.b-16-Ext-dst16-16-16-absolute-Ext-QI", "exts.b", 32,
4160     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
4161   },
4162 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
4163   {
4164     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 24,
4165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4166   },
4167 /* xor.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
4168   {
4169     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 24,
4170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4171   },
4172 /* xor.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
4173   {
4174     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 24,
4175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4176   },
4177 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
4178   {
4179     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 24,
4180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4181   },
4182 /* xor.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
4183   {
4184     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 24,
4185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4186   },
4187 /* xor.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
4188   {
4189     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 24,
4190     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4191   },
4192 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
4193   {
4194     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 24,
4195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4196   },
4197 /* xor.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
4198   {
4199     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 24,
4200     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4201   },
4202 /* xor.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
4203   {
4204     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 24,
4205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4206   },
4207 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
4208   {
4209     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "xor.w", 32,
4210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4211   },
4212 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
4213   {
4214     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "xor.w", 32,
4215     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4216   },
4217 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
4218   {
4219     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "xor.w", 32,
4220     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4221   },
4222 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
4223   {
4224     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "xor.w", 40,
4225     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4226   },
4227 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
4228   {
4229     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "xor.w", 40,
4230     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4231   },
4232 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
4233   {
4234     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "xor.w", 40,
4235     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4236   },
4237 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
4238   {
4239     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "xor.w", 48,
4240     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4241   },
4242 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
4243   {
4244     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "xor.w", 48,
4245     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4246   },
4247 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
4248   {
4249     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "xor.w", 48,
4250     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4251   },
4252 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
4253   {
4254     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "xor.w", 32,
4255     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4256   },
4257 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
4258   {
4259     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "xor.w", 32,
4260     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4261   },
4262 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
4263   {
4264     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "xor.w", 32,
4265     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4266   },
4267 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
4268   {
4269     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "xor.w", 40,
4270     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4271   },
4272 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
4273   {
4274     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "xor.w", 40,
4275     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4276   },
4277 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
4278   {
4279     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "xor.w", 40,
4280     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4281   },
4282 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
4283   {
4284     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "xor.w", 32,
4285     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4286   },
4287 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
4288   {
4289     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "xor.w", 32,
4290     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4291   },
4292 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
4293   {
4294     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "xor.w", 32,
4295     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4296   },
4297 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
4298   {
4299     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "xor.w", 40,
4300     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4301   },
4302 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
4303   {
4304     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "xor.w", 40,
4305     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4306   },
4307 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
4308   {
4309     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "xor.w", 40,
4310     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4311   },
4312 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
4313   {
4314     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "xor.w", 40,
4315     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4316   },
4317 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
4318   {
4319     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "xor.w", 40,
4320     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4321   },
4322 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
4323   {
4324     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "xor.w", 40,
4325     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4326   },
4327 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
4328   {
4329     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "xor.w", 48,
4330     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4331   },
4332 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
4333   {
4334     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "xor.w", 48,
4335     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4336   },
4337 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
4338   {
4339     M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "xor.w", 48,
4340     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4341   },
4342 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
4343   {
4344     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32,
4345     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4346   },
4347 /* xor.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
4348   {
4349     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32,
4350     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4351   },
4352 /* xor.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
4353   {
4354     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32,
4355     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4356   },
4357 /* xor.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
4358   {
4359     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32,
4360     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4361   },
4362 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
4363   {
4364     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 32,
4365     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4366   },
4367 /* xor.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
4368   {
4369     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 32,
4370     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4371   },
4372 /* xor.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
4373   {
4374     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 32,
4375     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4376   },
4377 /* xor.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
4378   {
4379     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 32,
4380     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4381   },
4382 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
4383   {
4384     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 32,
4385     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4386   },
4387 /* xor.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
4388   {
4389     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 32,
4390     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4391   },
4392 /* xor.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
4393   {
4394     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 32,
4395     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4396   },
4397 /* xor.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
4398   {
4399     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 32,
4400     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4401   },
4402 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
4403   {
4404     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "xor.w", 40,
4405     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4406   },
4407 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
4408   {
4409     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "xor.w", 40,
4410     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4411   },
4412 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
4413   {
4414     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "xor.w", 40,
4415     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4416   },
4417 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
4418   {
4419     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "xor.w", 40,
4420     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4421   },
4422 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
4423   {
4424     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "xor.w", 48,
4425     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4426   },
4427 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
4428   {
4429     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "xor.w", 48,
4430     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4431   },
4432 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
4433   {
4434     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "xor.w", 48,
4435     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4436   },
4437 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
4438   {
4439     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "xor.w", 48,
4440     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4441   },
4442 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
4443   {
4444     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "xor.w", 56,
4445     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4446   },
4447 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
4448   {
4449     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "xor.w", 56,
4450     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4451   },
4452 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
4453   {
4454     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "xor.w", 56,
4455     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4456   },
4457 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
4458   {
4459     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "xor.w", 56,
4460     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4461   },
4462 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
4463   {
4464     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "xor.w", 40,
4465     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4466   },
4467 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
4468   {
4469     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "xor.w", 40,
4470     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4471   },
4472 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
4473   {
4474     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "xor.w", 40,
4475     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4476   },
4477 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
4478   {
4479     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "xor.w", 40,
4480     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4481   },
4482 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
4483   {
4484     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "xor.w", 48,
4485     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4486   },
4487 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
4488   {
4489     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "xor.w", 48,
4490     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4491   },
4492 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
4493   {
4494     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "xor.w", 48,
4495     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4496   },
4497 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
4498   {
4499     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "xor.w", 48,
4500     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4501   },
4502 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
4503   {
4504     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "xor.w", 40,
4505     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4506   },
4507 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
4508   {
4509     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "xor.w", 40,
4510     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4511   },
4512 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
4513   {
4514     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "xor.w", 40,
4515     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4516   },
4517 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
4518   {
4519     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "xor.w", 40,
4520     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4521   },
4522 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
4523   {
4524     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "xor.w", 48,
4525     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4526   },
4527 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
4528   {
4529     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "xor.w", 48,
4530     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4531   },
4532 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
4533   {
4534     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "xor.w", 48,
4535     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4536   },
4537 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
4538   {
4539     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "xor.w", 48,
4540     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4541   },
4542 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
4543   {
4544     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "xor.w", 48,
4545     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4546   },
4547 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
4548   {
4549     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "xor.w", 48,
4550     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4551   },
4552 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
4553   {
4554     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "xor.w", 48,
4555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4556   },
4557 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
4558   {
4559     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "xor.w", 48,
4560     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4561   },
4562 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
4563   {
4564     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "xor.w", 56,
4565     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4566   },
4567 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
4568   {
4569     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "xor.w", 56,
4570     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4571   },
4572 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
4573   {
4574     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "xor.w", 56,
4575     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4576   },
4577 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
4578   {
4579     M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "xor.w", 56,
4580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4581   },
4582 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
4583   {
4584     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 40,
4585     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4586   },
4587 /* xor.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
4588   {
4589     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 40,
4590     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4591   },
4592 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
4593   {
4594     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 40,
4595     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4596   },
4597 /* xor.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
4598   {
4599     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 40,
4600     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4601   },
4602 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
4603   {
4604     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 40,
4605     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4606   },
4607 /* xor.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
4608   {
4609     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 40,
4610     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4611   },
4612 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
4613   {
4614     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "xor.w", 48,
4615     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4616   },
4617 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
4618   {
4619     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "xor.w", 48,
4620     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4621   },
4622 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
4623   {
4624     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "xor.w", 56,
4625     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4626   },
4627 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
4628   {
4629     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "xor.w", 56,
4630     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4631   },
4632 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
4633   {
4634     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "xor.w", 64,
4635     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4636   },
4637 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
4638   {
4639     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "xor.w", 64,
4640     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4641   },
4642 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
4643   {
4644     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "xor.w", 48,
4645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4646   },
4647 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
4648   {
4649     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "xor.w", 48,
4650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4651   },
4652 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
4653   {
4654     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "xor.w", 56,
4655     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4656   },
4657 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
4658   {
4659     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "xor.w", 56,
4660     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4661   },
4662 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
4663   {
4664     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "xor.w", 48,
4665     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4666   },
4667 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
4668   {
4669     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "xor.w", 48,
4670     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4671   },
4672 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
4673   {
4674     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "xor.w", 56,
4675     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4676   },
4677 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
4678   {
4679     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "xor.w", 56,
4680     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4681   },
4682 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
4683   {
4684     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "xor.w", 56,
4685     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4686   },
4687 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
4688   {
4689     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "xor.w", 56,
4690     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4691   },
4692 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
4693   {
4694     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "xor.w", 64,
4695     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4696   },
4697 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
4698   {
4699     M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "xor.w", 64,
4700     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4701   },
4702 /* xor.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
4703   {
4704     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 16,
4705     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4706   },
4707 /* xor.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
4708   {
4709     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 16,
4710     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4711   },
4712 /* xor.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
4713   {
4714     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 16,
4715     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4716   },
4717 /* xor.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
4718   {
4719     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 16,
4720     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4721   },
4722 /* xor.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
4723   {
4724     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 16,
4725     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4726   },
4727 /* xor.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
4728   {
4729     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 16,
4730     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4731   },
4732 /* xor.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
4733   {
4734     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 16,
4735     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4736   },
4737 /* xor.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
4738   {
4739     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 16,
4740     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4741   },
4742 /* xor.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
4743   {
4744     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 16,
4745     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4746   },
4747 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
4748   {
4749     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "xor.w", 24,
4750     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4751   },
4752 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
4753   {
4754     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "xor.w", 24,
4755     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4756   },
4757 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
4758   {
4759     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "xor.w", 24,
4760     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4761   },
4762 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
4763   {
4764     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "xor.w", 32,
4765     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4766   },
4767 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
4768   {
4769     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "xor.w", 32,
4770     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4771   },
4772 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
4773   {
4774     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "xor.w", 32,
4775     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4776   },
4777 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
4778   {
4779     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "xor.w", 40,
4780     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4781   },
4782 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
4783   {
4784     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "xor.w", 40,
4785     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4786   },
4787 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
4788   {
4789     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "xor.w", 40,
4790     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4791   },
4792 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
4793   {
4794     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "xor.w", 24,
4795     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4796   },
4797 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
4798   {
4799     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "xor.w", 24,
4800     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4801   },
4802 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
4803   {
4804     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "xor.w", 24,
4805     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4806   },
4807 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
4808   {
4809     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "xor.w", 32,
4810     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4811   },
4812 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
4813   {
4814     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "xor.w", 32,
4815     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4816   },
4817 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
4818   {
4819     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "xor.w", 32,
4820     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4821   },
4822 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
4823   {
4824     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "xor.w", 24,
4825     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4826   },
4827 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
4828   {
4829     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "xor.w", 24,
4830     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4831   },
4832 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
4833   {
4834     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "xor.w", 24,
4835     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4836   },
4837 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
4838   {
4839     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "xor.w", 32,
4840     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4841   },
4842 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
4843   {
4844     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "xor.w", 32,
4845     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4846   },
4847 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
4848   {
4849     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "xor.w", 32,
4850     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4851   },
4852 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
4853   {
4854     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "xor.w", 32,
4855     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4856   },
4857 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
4858   {
4859     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "xor.w", 32,
4860     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4861   },
4862 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
4863   {
4864     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "xor.w", 32,
4865     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4866   },
4867 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
4868   {
4869     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "xor.w", 40,
4870     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4871   },
4872 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
4873   {
4874     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "xor.w", 40,
4875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4876   },
4877 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
4878   {
4879     M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "xor.w", 40,
4880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4881   },
4882 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
4883   {
4884     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 24,
4885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4886   },
4887 /* xor.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
4888   {
4889     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 24,
4890     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4891   },
4892 /* xor.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
4893   {
4894     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 24,
4895     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4896   },
4897 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
4898   {
4899     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 24,
4900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4901   },
4902 /* xor.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
4903   {
4904     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 24,
4905     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4906   },
4907 /* xor.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
4908   {
4909     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 24,
4910     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4911   },
4912 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
4913   {
4914     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 24,
4915     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4916   },
4917 /* xor.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
4918   {
4919     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 24,
4920     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4921   },
4922 /* xor.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
4923   {
4924     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 24,
4925     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4926   },
4927 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
4928   {
4929     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "xor.b", 32,
4930     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4931   },
4932 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
4933   {
4934     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "xor.b", 32,
4935     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4936   },
4937 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
4938   {
4939     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "xor.b", 32,
4940     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4941   },
4942 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
4943   {
4944     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "xor.b", 40,
4945     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4946   },
4947 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
4948   {
4949     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "xor.b", 40,
4950     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4951   },
4952 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
4953   {
4954     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "xor.b", 40,
4955     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4956   },
4957 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
4958   {
4959     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "xor.b", 48,
4960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4961   },
4962 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
4963   {
4964     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "xor.b", 48,
4965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4966   },
4967 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
4968   {
4969     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "xor.b", 48,
4970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4971   },
4972 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
4973   {
4974     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "xor.b", 32,
4975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4976   },
4977 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
4978   {
4979     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "xor.b", 32,
4980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4981   },
4982 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
4983   {
4984     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "xor.b", 32,
4985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4986   },
4987 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
4988   {
4989     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "xor.b", 40,
4990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4991   },
4992 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
4993   {
4994     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "xor.b", 40,
4995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4996   },
4997 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
4998   {
4999     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "xor.b", 40,
5000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5001   },
5002 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
5003   {
5004     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "xor.b", 32,
5005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5006   },
5007 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
5008   {
5009     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "xor.b", 32,
5010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5011   },
5012 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
5013   {
5014     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "xor.b", 32,
5015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5016   },
5017 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
5018   {
5019     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "xor.b", 40,
5020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5021   },
5022 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
5023   {
5024     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "xor.b", 40,
5025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5026   },
5027 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
5028   {
5029     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "xor.b", 40,
5030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5031   },
5032 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
5033   {
5034     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "xor.b", 40,
5035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5036   },
5037 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
5038   {
5039     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "xor.b", 40,
5040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5041   },
5042 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
5043   {
5044     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "xor.b", 40,
5045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5046   },
5047 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
5048   {
5049     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "xor.b", 48,
5050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5051   },
5052 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
5053   {
5054     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "xor.b", 48,
5055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5056   },
5057 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
5058   {
5059     M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "xor.b", 48,
5060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5061   },
5062 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
5063   {
5064     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 32,
5065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5066   },
5067 /* xor.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
5068   {
5069     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 32,
5070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5071   },
5072 /* xor.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
5073   {
5074     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 32,
5075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5076   },
5077 /* xor.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
5078   {
5079     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 32,
5080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5081   },
5082 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
5083   {
5084     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 32,
5085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5086   },
5087 /* xor.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
5088   {
5089     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 32,
5090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5091   },
5092 /* xor.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
5093   {
5094     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 32,
5095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5096   },
5097 /* xor.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
5098   {
5099     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 32,
5100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5101   },
5102 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
5103   {
5104     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 32,
5105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5106   },
5107 /* xor.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
5108   {
5109     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 32,
5110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5111   },
5112 /* xor.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
5113   {
5114     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 32,
5115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5116   },
5117 /* xor.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
5118   {
5119     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 32,
5120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5121   },
5122 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
5123   {
5124     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "xor.b", 40,
5125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5126   },
5127 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
5128   {
5129     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "xor.b", 40,
5130     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5131   },
5132 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
5133   {
5134     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "xor.b", 40,
5135     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5136   },
5137 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
5138   {
5139     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "xor.b", 40,
5140     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5141   },
5142 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
5143   {
5144     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "xor.b", 48,
5145     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5146   },
5147 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
5148   {
5149     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "xor.b", 48,
5150     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5151   },
5152 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
5153   {
5154     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "xor.b", 48,
5155     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5156   },
5157 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
5158   {
5159     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "xor.b", 48,
5160     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5161   },
5162 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
5163   {
5164     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "xor.b", 56,
5165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5166   },
5167 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
5168   {
5169     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "xor.b", 56,
5170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5171   },
5172 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
5173   {
5174     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "xor.b", 56,
5175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5176   },
5177 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
5178   {
5179     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "xor.b", 56,
5180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5181   },
5182 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
5183   {
5184     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "xor.b", 40,
5185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5186   },
5187 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
5188   {
5189     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "xor.b", 40,
5190     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5191   },
5192 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
5193   {
5194     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "xor.b", 40,
5195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5196   },
5197 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
5198   {
5199     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "xor.b", 40,
5200     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5201   },
5202 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
5203   {
5204     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "xor.b", 48,
5205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5206   },
5207 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
5208   {
5209     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "xor.b", 48,
5210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5211   },
5212 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
5213   {
5214     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "xor.b", 48,
5215     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5216   },
5217 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
5218   {
5219     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "xor.b", 48,
5220     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5221   },
5222 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
5223   {
5224     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "xor.b", 40,
5225     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5226   },
5227 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
5228   {
5229     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "xor.b", 40,
5230     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5231   },
5232 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
5233   {
5234     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "xor.b", 40,
5235     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5236   },
5237 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
5238   {
5239     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "xor.b", 40,
5240     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5241   },
5242 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
5243   {
5244     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "xor.b", 48,
5245     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5246   },
5247 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
5248   {
5249     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "xor.b", 48,
5250     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5251   },
5252 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
5253   {
5254     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "xor.b", 48,
5255     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5256   },
5257 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
5258   {
5259     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "xor.b", 48,
5260     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5261   },
5262 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
5263   {
5264     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "xor.b", 48,
5265     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5266   },
5267 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
5268   {
5269     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "xor.b", 48,
5270     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5271   },
5272 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
5273   {
5274     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "xor.b", 48,
5275     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5276   },
5277 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
5278   {
5279     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "xor.b", 48,
5280     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5281   },
5282 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
5283   {
5284     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "xor.b", 56,
5285     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5286   },
5287 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
5288   {
5289     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "xor.b", 56,
5290     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5291   },
5292 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
5293   {
5294     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "xor.b", 56,
5295     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5296   },
5297 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
5298   {
5299     M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "xor.b", 56,
5300     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5301   },
5302 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
5303   {
5304     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 40,
5305     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5306   },
5307 /* xor.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
5308   {
5309     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 40,
5310     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5311   },
5312 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
5313   {
5314     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 40,
5315     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5316   },
5317 /* xor.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
5318   {
5319     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 40,
5320     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5321   },
5322 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
5323   {
5324     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 40,
5325     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5326   },
5327 /* xor.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
5328   {
5329     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 40,
5330     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5331   },
5332 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
5333   {
5334     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "xor.b", 48,
5335     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5336   },
5337 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
5338   {
5339     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "xor.b", 48,
5340     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5341   },
5342 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
5343   {
5344     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "xor.b", 56,
5345     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5346   },
5347 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
5348   {
5349     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "xor.b", 56,
5350     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5351   },
5352 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
5353   {
5354     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "xor.b", 64,
5355     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5356   },
5357 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
5358   {
5359     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "xor.b", 64,
5360     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5361   },
5362 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
5363   {
5364     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "xor.b", 48,
5365     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5366   },
5367 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
5368   {
5369     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "xor.b", 48,
5370     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5371   },
5372 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
5373   {
5374     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "xor.b", 56,
5375     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5376   },
5377 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
5378   {
5379     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "xor.b", 56,
5380     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5381   },
5382 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
5383   {
5384     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "xor.b", 48,
5385     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5386   },
5387 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
5388   {
5389     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "xor.b", 48,
5390     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5391   },
5392 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
5393   {
5394     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "xor.b", 56,
5395     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5396   },
5397 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
5398   {
5399     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "xor.b", 56,
5400     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5401   },
5402 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
5403   {
5404     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "xor.b", 56,
5405     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5406   },
5407 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
5408   {
5409     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "xor.b", 56,
5410     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5411   },
5412 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
5413   {
5414     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "xor.b", 64,
5415     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5416   },
5417 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
5418   {
5419     M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "xor.b", 64,
5420     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5421   },
5422 /* xor.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
5423   {
5424     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 16,
5425     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5426   },
5427 /* xor.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
5428   {
5429     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 16,
5430     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5431   },
5432 /* xor.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
5433   {
5434     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 16,
5435     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5436   },
5437 /* xor.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
5438   {
5439     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 16,
5440     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5441   },
5442 /* xor.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
5443   {
5444     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 16,
5445     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5446   },
5447 /* xor.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
5448   {
5449     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 16,
5450     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5451   },
5452 /* xor.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
5453   {
5454     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 16,
5455     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5456   },
5457 /* xor.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
5458   {
5459     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 16,
5460     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5461   },
5462 /* xor.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
5463   {
5464     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 16,
5465     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5466   },
5467 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
5468   {
5469     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "xor.b", 24,
5470     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5471   },
5472 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
5473   {
5474     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "xor.b", 24,
5475     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5476   },
5477 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
5478   {
5479     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "xor.b", 24,
5480     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5481   },
5482 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
5483   {
5484     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "xor.b", 32,
5485     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5486   },
5487 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
5488   {
5489     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "xor.b", 32,
5490     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5491   },
5492 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
5493   {
5494     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "xor.b", 32,
5495     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5496   },
5497 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
5498   {
5499     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "xor.b", 40,
5500     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5501   },
5502 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
5503   {
5504     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "xor.b", 40,
5505     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5506   },
5507 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
5508   {
5509     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "xor.b", 40,
5510     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5511   },
5512 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
5513   {
5514     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "xor.b", 24,
5515     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5516   },
5517 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
5518   {
5519     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "xor.b", 24,
5520     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5521   },
5522 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
5523   {
5524     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "xor.b", 24,
5525     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5526   },
5527 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
5528   {
5529     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "xor.b", 32,
5530     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5531   },
5532 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
5533   {
5534     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "xor.b", 32,
5535     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5536   },
5537 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
5538   {
5539     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "xor.b", 32,
5540     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5541   },
5542 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
5543   {
5544     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "xor.b", 24,
5545     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5546   },
5547 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
5548   {
5549     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "xor.b", 24,
5550     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5551   },
5552 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
5553   {
5554     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "xor.b", 24,
5555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5556   },
5557 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
5558   {
5559     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "xor.b", 32,
5560     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5561   },
5562 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
5563   {
5564     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "xor.b", 32,
5565     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5566   },
5567 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
5568   {
5569     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "xor.b", 32,
5570     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5571   },
5572 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
5573   {
5574     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "xor.b", 32,
5575     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5576   },
5577 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
5578   {
5579     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "xor.b", 32,
5580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5581   },
5582 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
5583   {
5584     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "xor.b", 32,
5585     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5586   },
5587 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
5588   {
5589     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "xor.b", 40,
5590     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5591   },
5592 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
5593   {
5594     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "xor.b", 40,
5595     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5596   },
5597 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
5598   {
5599     M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "xor.b", 40,
5600     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5601   },
5602 /* xor.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
5603   {
5604     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "xor.w", 24,
5605     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5606   },
5607 /* xor.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
5608   {
5609     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "xor.w", 24,
5610     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5611   },
5612 /* xor.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
5613   {
5614     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "xor.w", 24,
5615     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5616   },
5617 /* xor.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
5618   {
5619     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "xor.w", 24,
5620     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5621   },
5622 /* xor.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
5623   {
5624     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "xor.w", 24,
5625     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5626   },
5627 /* xor.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
5628   {
5629     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "xor.w", 24,
5630     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5631   },
5632 /* xor.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
5633   {
5634     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "xor.w", 24,
5635     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5636   },
5637 /* xor.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
5638   {
5639     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "xor.w", 24,
5640     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5641   },
5642 /* xor.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
5643   {
5644     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "xor.w", 24,
5645     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5646   },
5647 /* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
5648   {
5649     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "xor.w", 32,
5650     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5651   },
5652 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
5653   {
5654     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "xor.w", 32,
5655     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5656   },
5657 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
5658   {
5659     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "xor.w", 32,
5660     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5661   },
5662 /* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
5663   {
5664     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "xor.w", 40,
5665     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5666   },
5667 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
5668   {
5669     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "xor.w", 40,
5670     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5671   },
5672 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
5673   {
5674     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "xor.w", 40,
5675     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5676   },
5677 /* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
5678   {
5679     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "xor.w", 32,
5680     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5681   },
5682 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
5683   {
5684     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "xor.w", 32,
5685     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5686   },
5687 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
5688   {
5689     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "xor.w", 32,
5690     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5691   },
5692 /* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
5693   {
5694     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "xor.w", 40,
5695     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5696   },
5697 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
5698   {
5699     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "xor.w", 40,
5700     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5701   },
5702 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
5703   {
5704     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "xor.w", 40,
5705     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5706   },
5707 /* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
5708   {
5709     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "xor.w", 32,
5710     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5711   },
5712 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
5713   {
5714     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "xor.w", 32,
5715     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5716   },
5717 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
5718   {
5719     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "xor.w", 32,
5720     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5721   },
5722 /* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
5723   {
5724     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "xor.w", 40,
5725     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5726   },
5727 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
5728   {
5729     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "xor.w", 40,
5730     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5731   },
5732 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
5733   {
5734     M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "xor.w", 40,
5735     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5736   },
5737 /* xor.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
5738   {
5739     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "xor.w", 32,
5740     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5741   },
5742 /* xor.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
5743   {
5744     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "xor.w", 32,
5745     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5746   },
5747 /* xor.w${G} ${Dsp-16-u16},$Dst16RnHI */
5748   {
5749     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "xor.w", 32,
5750     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5751   },
5752 /* xor.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
5753   {
5754     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "xor.w", 32,
5755     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5756   },
5757 /* xor.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
5758   {
5759     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "xor.w", 32,
5760     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5761   },
5762 /* xor.w${G} ${Dsp-16-u16},$Dst16AnHI */
5763   {
5764     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "xor.w", 32,
5765     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5766   },
5767 /* xor.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
5768   {
5769     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "xor.w", 32,
5770     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5771   },
5772 /* xor.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
5773   {
5774     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "xor.w", 32,
5775     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5776   },
5777 /* xor.w${G} ${Dsp-16-u16},[$Dst16An] */
5778   {
5779     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "xor.w", 32,
5780     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5781   },
5782 /* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
5783   {
5784     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "xor.w", 40,
5785     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5786   },
5787 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
5788   {
5789     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "xor.w", 40,
5790     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5791   },
5792 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
5793   {
5794     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "xor.w", 40,
5795     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5796   },
5797 /* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
5798   {
5799     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "xor.w", 48,
5800     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5801   },
5802 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
5803   {
5804     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "xor.w", 48,
5805     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5806   },
5807 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
5808   {
5809     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "xor.w", 48,
5810     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5811   },
5812 /* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
5813   {
5814     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "xor.w", 40,
5815     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5816   },
5817 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
5818   {
5819     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "xor.w", 40,
5820     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5821   },
5822 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
5823   {
5824     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "xor.w", 40,
5825     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5826   },
5827 /* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
5828   {
5829     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "xor.w", 48,
5830     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5831   },
5832 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
5833   {
5834     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "xor.w", 48,
5835     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5836   },
5837 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
5838   {
5839     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "xor.w", 48,
5840     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5841   },
5842 /* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
5843   {
5844     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "xor.w", 40,
5845     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5846   },
5847 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
5848   {
5849     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "xor.w", 40,
5850     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5851   },
5852 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
5853   {
5854     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "xor.w", 40,
5855     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5856   },
5857 /* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
5858   {
5859     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "xor.w", 48,
5860     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5861   },
5862 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
5863   {
5864     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "xor.w", 48,
5865     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5866   },
5867 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
5868   {
5869     M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "xor.w", 48,
5870     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5871   },
5872 /* xor.w${G} $Src16RnHI,$Dst16RnHI */
5873   {
5874     M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "xor.w", 16,
5875     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5876   },
5877 /* xor.w${G} $Src16AnHI,$Dst16RnHI */
5878   {
5879     M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "xor.w", 16,
5880     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5881   },
5882 /* xor.w${G} [$Src16An],$Dst16RnHI */
5883   {
5884     M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "xor.w", 16,
5885     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5886   },
5887 /* xor.w${G} $Src16RnHI,$Dst16AnHI */
5888   {
5889     M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "xor.w", 16,
5890     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5891   },
5892 /* xor.w${G} $Src16AnHI,$Dst16AnHI */
5893   {
5894     M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "xor.w", 16,
5895     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5896   },
5897 /* xor.w${G} [$Src16An],$Dst16AnHI */
5898   {
5899     M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "xor.w", 16,
5900     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5901   },
5902 /* xor.w${G} $Src16RnHI,[$Dst16An] */
5903   {
5904     M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "xor.w", 16,
5905     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5906   },
5907 /* xor.w${G} $Src16AnHI,[$Dst16An] */
5908   {
5909     M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "xor.w", 16,
5910     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5911   },
5912 /* xor.w${G} [$Src16An],[$Dst16An] */
5913   {
5914     M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "xor.w", 16,
5915     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5916   },
5917 /* xor.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
5918   {
5919     M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "xor.w", 24,
5920     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5921   },
5922 /* xor.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
5923   {
5924     M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "xor.w", 24,
5925     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5926   },
5927 /* xor.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
5928   {
5929     M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "xor.w", 24,
5930     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5931   },
5932 /* xor.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
5933   {
5934     M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "xor.w", 32,
5935     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5936   },
5937 /* xor.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
5938   {
5939     M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "xor.w", 32,
5940     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5941   },
5942 /* xor.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
5943   {
5944     M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "xor.w", 32,
5945     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5946   },
5947 /* xor.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
5948   {
5949     M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "xor.w", 24,
5950     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5951   },
5952 /* xor.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
5953   {
5954     M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "xor.w", 24,
5955     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5956   },
5957 /* xor.w${G} [$Src16An],${Dsp-16-u8}[sb] */
5958   {
5959     M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "xor.w", 24,
5960     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5961   },
5962 /* xor.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
5963   {
5964     M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "xor.w", 32,
5965     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5966   },
5967 /* xor.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
5968   {
5969     M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "xor.w", 32,
5970     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5971   },
5972 /* xor.w${G} [$Src16An],${Dsp-16-u16}[sb] */
5973   {
5974     M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "xor.w", 32,
5975     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5976   },
5977 /* xor.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
5978   {
5979     M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "xor.w", 24,
5980     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5981   },
5982 /* xor.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
5983   {
5984     M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "xor.w", 24,
5985     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5986   },
5987 /* xor.w${G} [$Src16An],${Dsp-16-s8}[fb] */
5988   {
5989     M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "xor.w", 24,
5990     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5991   },
5992 /* xor.w${G} $Src16RnHI,${Dsp-16-u16} */
5993   {
5994     M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "xor.w", 32,
5995     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5996   },
5997 /* xor.w${G} $Src16AnHI,${Dsp-16-u16} */
5998   {
5999     M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "xor.w", 32,
6000     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6001   },
6002 /* xor.w${G} [$Src16An],${Dsp-16-u16} */
6003   {
6004     M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "xor.w", 32,
6005     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6006   },
6007 /* xor.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
6008   {
6009     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "xor.b", 24,
6010     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6011   },
6012 /* xor.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
6013   {
6014     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "xor.b", 24,
6015     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6016   },
6017 /* xor.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
6018   {
6019     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "xor.b", 24,
6020     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6021   },
6022 /* xor.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
6023   {
6024     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "xor.b", 24,
6025     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6026   },
6027 /* xor.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
6028   {
6029     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "xor.b", 24,
6030     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6031   },
6032 /* xor.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
6033   {
6034     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "xor.b", 24,
6035     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6036   },
6037 /* xor.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
6038   {
6039     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "xor.b", 24,
6040     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6041   },
6042 /* xor.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
6043   {
6044     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "xor.b", 24,
6045     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6046   },
6047 /* xor.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
6048   {
6049     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "xor.b", 24,
6050     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6051   },
6052 /* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
6053   {
6054     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "xor.b", 32,
6055     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6056   },
6057 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
6058   {
6059     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "xor.b", 32,
6060     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6061   },
6062 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
6063   {
6064     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "xor.b", 32,
6065     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6066   },
6067 /* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
6068   {
6069     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "xor.b", 40,
6070     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6071   },
6072 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
6073   {
6074     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "xor.b", 40,
6075     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6076   },
6077 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
6078   {
6079     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "xor.b", 40,
6080     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6081   },
6082 /* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
6083   {
6084     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "xor.b", 32,
6085     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6086   },
6087 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
6088   {
6089     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "xor.b", 32,
6090     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6091   },
6092 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
6093   {
6094     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "xor.b", 32,
6095     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6096   },
6097 /* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
6098   {
6099     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "xor.b", 40,
6100     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6101   },
6102 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
6103   {
6104     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "xor.b", 40,
6105     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6106   },
6107 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
6108   {
6109     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "xor.b", 40,
6110     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6111   },
6112 /* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
6113   {
6114     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "xor.b", 32,
6115     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6116   },
6117 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
6118   {
6119     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "xor.b", 32,
6120     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6121   },
6122 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
6123   {
6124     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "xor.b", 32,
6125     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6126   },
6127 /* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
6128   {
6129     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "xor.b", 40,
6130     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6131   },
6132 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
6133   {
6134     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "xor.b", 40,
6135     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6136   },
6137 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
6138   {
6139     M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "xor.b", 40,
6140     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6141   },
6142 /* xor.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
6143   {
6144     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "xor.b", 32,
6145     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6146   },
6147 /* xor.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
6148   {
6149     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "xor.b", 32,
6150     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6151   },
6152 /* xor.b${G} ${Dsp-16-u16},$Dst16RnQI */
6153   {
6154     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "xor.b", 32,
6155     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6156   },
6157 /* xor.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
6158   {
6159     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "xor.b", 32,
6160     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6161   },
6162 /* xor.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
6163   {
6164     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "xor.b", 32,
6165     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6166   },
6167 /* xor.b${G} ${Dsp-16-u16},$Dst16AnQI */
6168   {
6169     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "xor.b", 32,
6170     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6171   },
6172 /* xor.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
6173   {
6174     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "xor.b", 32,
6175     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6176   },
6177 /* xor.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
6178   {
6179     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "xor.b", 32,
6180     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6181   },
6182 /* xor.b${G} ${Dsp-16-u16},[$Dst16An] */
6183   {
6184     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "xor.b", 32,
6185     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6186   },
6187 /* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
6188   {
6189     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "xor.b", 40,
6190     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6191   },
6192 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
6193   {
6194     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "xor.b", 40,
6195     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6196   },
6197 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
6198   {
6199     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "xor.b", 40,
6200     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6201   },
6202 /* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
6203   {
6204     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "xor.b", 48,
6205     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6206   },
6207 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
6208   {
6209     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "xor.b", 48,
6210     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6211   },
6212 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
6213   {
6214     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "xor.b", 48,
6215     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6216   },
6217 /* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
6218   {
6219     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "xor.b", 40,
6220     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6221   },
6222 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
6223   {
6224     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "xor.b", 40,
6225     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6226   },
6227 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
6228   {
6229     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "xor.b", 40,
6230     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6231   },
6232 /* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
6233   {
6234     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "xor.b", 48,
6235     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6236   },
6237 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
6238   {
6239     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "xor.b", 48,
6240     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6241   },
6242 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
6243   {
6244     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "xor.b", 48,
6245     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6246   },
6247 /* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
6248   {
6249     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "xor.b", 40,
6250     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6251   },
6252 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
6253   {
6254     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "xor.b", 40,
6255     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6256   },
6257 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
6258   {
6259     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "xor.b", 40,
6260     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6261   },
6262 /* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
6263   {
6264     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "xor.b", 48,
6265     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6266   },
6267 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
6268   {
6269     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "xor.b", 48,
6270     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6271   },
6272 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
6273   {
6274     M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "xor.b", 48,
6275     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6276   },
6277 /* xor.b${G} $Src16RnQI,$Dst16RnQI */
6278   {
6279     M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "xor.b", 16,
6280     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6281   },
6282 /* xor.b${G} $Src16AnQI,$Dst16RnQI */
6283   {
6284     M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "xor.b", 16,
6285     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6286   },
6287 /* xor.b${G} [$Src16An],$Dst16RnQI */
6288   {
6289     M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "xor.b", 16,
6290     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6291   },
6292 /* xor.b${G} $Src16RnQI,$Dst16AnQI */
6293   {
6294     M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "xor.b", 16,
6295     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6296   },
6297 /* xor.b${G} $Src16AnQI,$Dst16AnQI */
6298   {
6299     M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "xor.b", 16,
6300     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6301   },
6302 /* xor.b${G} [$Src16An],$Dst16AnQI */
6303   {
6304     M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "xor.b", 16,
6305     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6306   },
6307 /* xor.b${G} $Src16RnQI,[$Dst16An] */
6308   {
6309     M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "xor.b", 16,
6310     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6311   },
6312 /* xor.b${G} $Src16AnQI,[$Dst16An] */
6313   {
6314     M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "xor.b", 16,
6315     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6316   },
6317 /* xor.b${G} [$Src16An],[$Dst16An] */
6318   {
6319     M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "xor.b", 16,
6320     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6321   },
6322 /* xor.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
6323   {
6324     M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "xor.b", 24,
6325     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6326   },
6327 /* xor.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
6328   {
6329     M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "xor.b", 24,
6330     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6331   },
6332 /* xor.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
6333   {
6334     M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "xor.b", 24,
6335     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6336   },
6337 /* xor.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
6338   {
6339     M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "xor.b", 32,
6340     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6341   },
6342 /* xor.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
6343   {
6344     M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "xor.b", 32,
6345     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6346   },
6347 /* xor.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
6348   {
6349     M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "xor.b", 32,
6350     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6351   },
6352 /* xor.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
6353   {
6354     M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "xor.b", 24,
6355     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6356   },
6357 /* xor.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
6358   {
6359     M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "xor.b", 24,
6360     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6361   },
6362 /* xor.b${G} [$Src16An],${Dsp-16-u8}[sb] */
6363   {
6364     M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "xor.b", 24,
6365     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6366   },
6367 /* xor.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
6368   {
6369     M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "xor.b", 32,
6370     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6371   },
6372 /* xor.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
6373   {
6374     M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "xor.b", 32,
6375     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6376   },
6377 /* xor.b${G} [$Src16An],${Dsp-16-u16}[sb] */
6378   {
6379     M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "xor.b", 32,
6380     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6381   },
6382 /* xor.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
6383   {
6384     M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "xor.b", 24,
6385     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6386   },
6387 /* xor.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
6388   {
6389     M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "xor.b", 24,
6390     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6391   },
6392 /* xor.b${G} [$Src16An],${Dsp-16-s8}[fb] */
6393   {
6394     M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "xor.b", 24,
6395     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6396   },
6397 /* xor.b${G} $Src16RnQI,${Dsp-16-u16} */
6398   {
6399     M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "xor.b", 32,
6400     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6401   },
6402 /* xor.b${G} $Src16AnQI,${Dsp-16-u16} */
6403   {
6404     M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "xor.b", 32,
6405     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6406   },
6407 /* xor.b${G} [$Src16An],${Dsp-16-u16} */
6408   {
6409     M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "xor.b", 32,
6410     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6411   },
6412 /* xor.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
6413   {
6414     M32C_INSN_XOR32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32,
6415     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6416   },
6417 /* xor.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
6418   {
6419     M32C_INSN_XOR32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "xor.w", 32,
6420     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6421   },
6422 /* xor.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
6423   {
6424     M32C_INSN_XOR32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "xor.w", 32,
6425     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6426   },
6427 /* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
6428   {
6429     M32C_INSN_XOR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "xor.w", 40,
6430     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6431   },
6432 /* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
6433   {
6434     M32C_INSN_XOR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "xor.w", 40,
6435     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6436   },
6437 /* xor.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
6438   {
6439     M32C_INSN_XOR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "xor.w", 40,
6440     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6441   },
6442 /* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
6443   {
6444     M32C_INSN_XOR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "xor.w", 48,
6445     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6446   },
6447 /* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
6448   {
6449     M32C_INSN_XOR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "xor.w", 48,
6450     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6451   },
6452 /* xor.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
6453   {
6454     M32C_INSN_XOR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "xor.w", 48,
6455     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6456   },
6457 /* xor.w${G} #${Imm-32-HI},${Dsp-16-u16} */
6458   {
6459     M32C_INSN_XOR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "xor.w", 48,
6460     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6461   },
6462 /* xor.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
6463   {
6464     M32C_INSN_XOR32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "xor.w", 56,
6465     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6466   },
6467 /* xor.w${G} #${Imm-40-HI},${Dsp-16-u24} */
6468   {
6469     M32C_INSN_XOR32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "xor.w", 56,
6470     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6471   },
6472 /* xor.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
6473   {
6474     M32C_INSN_XOR32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "xor.b", 24,
6475     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6476   },
6477 /* xor.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
6478   {
6479     M32C_INSN_XOR32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "xor.b", 24,
6480     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6481   },
6482 /* xor.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
6483   {
6484     M32C_INSN_XOR32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "xor.b", 24,
6485     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6486   },
6487 /* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
6488   {
6489     M32C_INSN_XOR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "xor.b", 32,
6490     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6491   },
6492 /* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
6493   {
6494     M32C_INSN_XOR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "xor.b", 32,
6495     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6496   },
6497 /* xor.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
6498   {
6499     M32C_INSN_XOR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "xor.b", 32,
6500     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6501   },
6502 /* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
6503   {
6504     M32C_INSN_XOR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "xor.b", 40,
6505     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6506   },
6507 /* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
6508   {
6509     M32C_INSN_XOR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "xor.b", 40,
6510     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6511   },
6512 /* xor.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
6513   {
6514     M32C_INSN_XOR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "xor.b", 40,
6515     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6516   },
6517 /* xor.b${G} #${Imm-32-QI},${Dsp-16-u16} */
6518   {
6519     M32C_INSN_XOR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "xor.b", 40,
6520     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6521   },
6522 /* xor.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
6523   {
6524     M32C_INSN_XOR32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "xor.b", 48,
6525     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6526   },
6527 /* xor.b${G} #${Imm-40-QI},${Dsp-16-u24} */
6528   {
6529     M32C_INSN_XOR32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "xor.b", 48,
6530     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6531   },
6532 /* xor.w${G} #${Imm-16-HI},$Dst16RnHI */
6533   {
6534     M32C_INSN_XOR16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "xor16.w-imm-G-basic-dst16-Rn-direct-HI", "xor.w", 32,
6535     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6536   },
6537 /* xor.w${G} #${Imm-16-HI},$Dst16AnHI */
6538   {
6539     M32C_INSN_XOR16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "xor16.w-imm-G-basic-dst16-An-direct-HI", "xor.w", 32,
6540     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6541   },
6542 /* xor.w${G} #${Imm-16-HI},[$Dst16An] */
6543   {
6544     M32C_INSN_XOR16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "xor16.w-imm-G-basic-dst16-An-indirect-HI", "xor.w", 32,
6545     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6546   },
6547 /* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
6548   {
6549     M32C_INSN_XOR16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "xor16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "xor.w", 40,
6550     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6551   },
6552 /* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
6553   {
6554     M32C_INSN_XOR16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "xor16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "xor.w", 40,
6555     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6556   },
6557 /* xor.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
6558   {
6559     M32C_INSN_XOR16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "xor16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "xor.w", 40,
6560     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6561   },
6562 /* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
6563   {
6564     M32C_INSN_XOR16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "xor16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "xor.w", 48,
6565     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6566   },
6567 /* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
6568   {
6569     M32C_INSN_XOR16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "xor16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "xor.w", 48,
6570     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6571   },
6572 /* xor.w${G} #${Imm-32-HI},${Dsp-16-u16} */
6573   {
6574     M32C_INSN_XOR16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "xor16.w-imm-G-16-16-dst16-16-16-absolute-HI", "xor.w", 48,
6575     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6576   },
6577 /* xor.b${G} #${Imm-16-QI},$Dst16RnQI */
6578   {
6579     M32C_INSN_XOR16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "xor16.b-imm-G-basic-dst16-Rn-direct-QI", "xor.b", 24,
6580     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6581   },
6582 /* xor.b${G} #${Imm-16-QI},$Dst16AnQI */
6583   {
6584     M32C_INSN_XOR16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "xor16.b-imm-G-basic-dst16-An-direct-QI", "xor.b", 24,
6585     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6586   },
6587 /* xor.b${G} #${Imm-16-QI},[$Dst16An] */
6588   {
6589     M32C_INSN_XOR16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "xor16.b-imm-G-basic-dst16-An-indirect-QI", "xor.b", 24,
6590     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6591   },
6592 /* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
6593   {
6594     M32C_INSN_XOR16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "xor16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "xor.b", 32,
6595     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6596   },
6597 /* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
6598   {
6599     M32C_INSN_XOR16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "xor16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "xor.b", 32,
6600     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6601   },
6602 /* xor.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
6603   {
6604     M32C_INSN_XOR16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "xor16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "xor.b", 32,
6605     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6606   },
6607 /* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
6608   {
6609     M32C_INSN_XOR16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "xor16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "xor.b", 40,
6610     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6611   },
6612 /* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
6613   {
6614     M32C_INSN_XOR16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "xor16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "xor.b", 40,
6615     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6616   },
6617 /* xor.b${G} #${Imm-32-QI},${Dsp-16-u16} */
6618   {
6619     M32C_INSN_XOR16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "xor16.b-imm-G-16-16-dst16-16-16-absolute-QI", "xor.b", 40,
6620     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6621   },
6622 /* xchg.w r3,$Dst32RnUnprefixedHI */
6623   {
6624     M32C_INSN_XCHG32W_R3_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-r3-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16,
6625     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6626   },
6627 /* xchg.w r3,$Dst32AnUnprefixedHI */
6628   {
6629     M32C_INSN_XCHG32W_R3_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-r3-dst32-An-direct-Unprefixed-HI", "xchg.w", 16,
6630     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6631   },
6632 /* xchg.w r3,[$Dst32AnUnprefixed] */
6633   {
6634     M32C_INSN_XCHG32W_R3_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-r3-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16,
6635     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6636   },
6637 /* xchg.w r3,${Dsp-16-u8}[$Dst32AnUnprefixed] */
6638   {
6639     M32C_INSN_XCHG32W_R3_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24,
6640     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6641   },
6642 /* xchg.w r3,${Dsp-16-u16}[$Dst32AnUnprefixed] */
6643   {
6644     M32C_INSN_XCHG32W_R3_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32,
6645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6646   },
6647 /* xchg.w r3,${Dsp-16-u24}[$Dst32AnUnprefixed] */
6648   {
6649     M32C_INSN_XCHG32W_R3_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40,
6650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6651   },
6652 /* xchg.w r3,${Dsp-16-u8}[sb] */
6653   {
6654     M32C_INSN_XCHG32W_R3_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24,
6655     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6656   },
6657 /* xchg.w r3,${Dsp-16-u16}[sb] */
6658   {
6659     M32C_INSN_XCHG32W_R3_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32,
6660     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6661   },
6662 /* xchg.w r3,${Dsp-16-s8}[fb] */
6663   {
6664     M32C_INSN_XCHG32W_R3_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24,
6665     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6666   },
6667 /* xchg.w r3,${Dsp-16-s16}[fb] */
6668   {
6669     M32C_INSN_XCHG32W_R3_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32,
6670     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6671   },
6672 /* xchg.w r3,${Dsp-16-u16} */
6673   {
6674     M32C_INSN_XCHG32W_R3_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32,
6675     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6676   },
6677 /* xchg.w r3,${Dsp-16-u24} */
6678   {
6679     M32C_INSN_XCHG32W_R3_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40,
6680     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6681   },
6682 /* xchg.w r2,$Dst32RnUnprefixedHI */
6683   {
6684     M32C_INSN_XCHG32W_R2_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-r2-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16,
6685     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6686   },
6687 /* xchg.w r2,$Dst32AnUnprefixedHI */
6688   {
6689     M32C_INSN_XCHG32W_R2_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-r2-dst32-An-direct-Unprefixed-HI", "xchg.w", 16,
6690     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6691   },
6692 /* xchg.w r2,[$Dst32AnUnprefixed] */
6693   {
6694     M32C_INSN_XCHG32W_R2_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-r2-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16,
6695     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6696   },
6697 /* xchg.w r2,${Dsp-16-u8}[$Dst32AnUnprefixed] */
6698   {
6699     M32C_INSN_XCHG32W_R2_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24,
6700     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6701   },
6702 /* xchg.w r2,${Dsp-16-u16}[$Dst32AnUnprefixed] */
6703   {
6704     M32C_INSN_XCHG32W_R2_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32,
6705     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6706   },
6707 /* xchg.w r2,${Dsp-16-u24}[$Dst32AnUnprefixed] */
6708   {
6709     M32C_INSN_XCHG32W_R2_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40,
6710     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6711   },
6712 /* xchg.w r2,${Dsp-16-u8}[sb] */
6713   {
6714     M32C_INSN_XCHG32W_R2_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24,
6715     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6716   },
6717 /* xchg.w r2,${Dsp-16-u16}[sb] */
6718   {
6719     M32C_INSN_XCHG32W_R2_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32,
6720     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6721   },
6722 /* xchg.w r2,${Dsp-16-s8}[fb] */
6723   {
6724     M32C_INSN_XCHG32W_R2_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24,
6725     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6726   },
6727 /* xchg.w r2,${Dsp-16-s16}[fb] */
6728   {
6729     M32C_INSN_XCHG32W_R2_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32,
6730     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6731   },
6732 /* xchg.w r2,${Dsp-16-u16} */
6733   {
6734     M32C_INSN_XCHG32W_R2_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32,
6735     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6736   },
6737 /* xchg.w r2,${Dsp-16-u24} */
6738   {
6739     M32C_INSN_XCHG32W_R2_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40,
6740     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6741   },
6742 /* xchg.w a1,$Dst32RnUnprefixedHI */
6743   {
6744     M32C_INSN_XCHG32W_A1_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-a1-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16,
6745     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6746   },
6747 /* xchg.w a1,$Dst32AnUnprefixedHI */
6748   {
6749     M32C_INSN_XCHG32W_A1_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-a1-dst32-An-direct-Unprefixed-HI", "xchg.w", 16,
6750     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6751   },
6752 /* xchg.w a1,[$Dst32AnUnprefixed] */
6753   {
6754     M32C_INSN_XCHG32W_A1_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-a1-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16,
6755     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6756   },
6757 /* xchg.w a1,${Dsp-16-u8}[$Dst32AnUnprefixed] */
6758   {
6759     M32C_INSN_XCHG32W_A1_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24,
6760     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6761   },
6762 /* xchg.w a1,${Dsp-16-u16}[$Dst32AnUnprefixed] */
6763   {
6764     M32C_INSN_XCHG32W_A1_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32,
6765     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6766   },
6767 /* xchg.w a1,${Dsp-16-u24}[$Dst32AnUnprefixed] */
6768   {
6769     M32C_INSN_XCHG32W_A1_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40,
6770     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6771   },
6772 /* xchg.w a1,${Dsp-16-u8}[sb] */
6773   {
6774     M32C_INSN_XCHG32W_A1_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24,
6775     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6776   },
6777 /* xchg.w a1,${Dsp-16-u16}[sb] */
6778   {
6779     M32C_INSN_XCHG32W_A1_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32,
6780     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6781   },
6782 /* xchg.w a1,${Dsp-16-s8}[fb] */
6783   {
6784     M32C_INSN_XCHG32W_A1_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24,
6785     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6786   },
6787 /* xchg.w a1,${Dsp-16-s16}[fb] */
6788   {
6789     M32C_INSN_XCHG32W_A1_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32,
6790     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6791   },
6792 /* xchg.w a1,${Dsp-16-u16} */
6793   {
6794     M32C_INSN_XCHG32W_A1_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32,
6795     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6796   },
6797 /* xchg.w a1,${Dsp-16-u24} */
6798   {
6799     M32C_INSN_XCHG32W_A1_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40,
6800     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6801   },
6802 /* xchg.w a0,$Dst32RnUnprefixedHI */
6803   {
6804     M32C_INSN_XCHG32W_A0_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-a0-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16,
6805     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6806   },
6807 /* xchg.w a0,$Dst32AnUnprefixedHI */
6808   {
6809     M32C_INSN_XCHG32W_A0_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-a0-dst32-An-direct-Unprefixed-HI", "xchg.w", 16,
6810     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6811   },
6812 /* xchg.w a0,[$Dst32AnUnprefixed] */
6813   {
6814     M32C_INSN_XCHG32W_A0_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-a0-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16,
6815     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6816   },
6817 /* xchg.w a0,${Dsp-16-u8}[$Dst32AnUnprefixed] */
6818   {
6819     M32C_INSN_XCHG32W_A0_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24,
6820     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6821   },
6822 /* xchg.w a0,${Dsp-16-u16}[$Dst32AnUnprefixed] */
6823   {
6824     M32C_INSN_XCHG32W_A0_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32,
6825     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6826   },
6827 /* xchg.w a0,${Dsp-16-u24}[$Dst32AnUnprefixed] */
6828   {
6829     M32C_INSN_XCHG32W_A0_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40,
6830     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6831   },
6832 /* xchg.w a0,${Dsp-16-u8}[sb] */
6833   {
6834     M32C_INSN_XCHG32W_A0_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24,
6835     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6836   },
6837 /* xchg.w a0,${Dsp-16-u16}[sb] */
6838   {
6839     M32C_INSN_XCHG32W_A0_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32,
6840     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6841   },
6842 /* xchg.w a0,${Dsp-16-s8}[fb] */
6843   {
6844     M32C_INSN_XCHG32W_A0_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24,
6845     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6846   },
6847 /* xchg.w a0,${Dsp-16-s16}[fb] */
6848   {
6849     M32C_INSN_XCHG32W_A0_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32,
6850     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6851   },
6852 /* xchg.w a0,${Dsp-16-u16} */
6853   {
6854     M32C_INSN_XCHG32W_A0_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32,
6855     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6856   },
6857 /* xchg.w a0,${Dsp-16-u24} */
6858   {
6859     M32C_INSN_XCHG32W_A0_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40,
6860     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6861   },
6862 /* xchg.w r1,$Dst32RnUnprefixedHI */
6863   {
6864     M32C_INSN_XCHG32W_R1_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-r1-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16,
6865     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6866   },
6867 /* xchg.w r1,$Dst32AnUnprefixedHI */
6868   {
6869     M32C_INSN_XCHG32W_R1_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-r1-dst32-An-direct-Unprefixed-HI", "xchg.w", 16,
6870     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6871   },
6872 /* xchg.w r1,[$Dst32AnUnprefixed] */
6873   {
6874     M32C_INSN_XCHG32W_R1_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-r1-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16,
6875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6876   },
6877 /* xchg.w r1,${Dsp-16-u8}[$Dst32AnUnprefixed] */
6878   {
6879     M32C_INSN_XCHG32W_R1_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24,
6880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6881   },
6882 /* xchg.w r1,${Dsp-16-u16}[$Dst32AnUnprefixed] */
6883   {
6884     M32C_INSN_XCHG32W_R1_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32,
6885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6886   },
6887 /* xchg.w r1,${Dsp-16-u24}[$Dst32AnUnprefixed] */
6888   {
6889     M32C_INSN_XCHG32W_R1_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40,
6890     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6891   },
6892 /* xchg.w r1,${Dsp-16-u8}[sb] */
6893   {
6894     M32C_INSN_XCHG32W_R1_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24,
6895     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6896   },
6897 /* xchg.w r1,${Dsp-16-u16}[sb] */
6898   {
6899     M32C_INSN_XCHG32W_R1_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32,
6900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6901   },
6902 /* xchg.w r1,${Dsp-16-s8}[fb] */
6903   {
6904     M32C_INSN_XCHG32W_R1_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24,
6905     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6906   },
6907 /* xchg.w r1,${Dsp-16-s16}[fb] */
6908   {
6909     M32C_INSN_XCHG32W_R1_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32,
6910     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6911   },
6912 /* xchg.w r1,${Dsp-16-u16} */
6913   {
6914     M32C_INSN_XCHG32W_R1_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32,
6915     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6916   },
6917 /* xchg.w r1,${Dsp-16-u24} */
6918   {
6919     M32C_INSN_XCHG32W_R1_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40,
6920     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6921   },
6922 /* xchg.w r0,$Dst32RnUnprefixedHI */
6923   {
6924     M32C_INSN_XCHG32W_R0_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-r0-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16,
6925     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6926   },
6927 /* xchg.w r0,$Dst32AnUnprefixedHI */
6928   {
6929     M32C_INSN_XCHG32W_R0_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-r0-dst32-An-direct-Unprefixed-HI", "xchg.w", 16,
6930     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6931   },
6932 /* xchg.w r0,[$Dst32AnUnprefixed] */
6933   {
6934     M32C_INSN_XCHG32W_R0_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-r0-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16,
6935     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6936   },
6937 /* xchg.w r0,${Dsp-16-u8}[$Dst32AnUnprefixed] */
6938   {
6939     M32C_INSN_XCHG32W_R0_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24,
6940     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6941   },
6942 /* xchg.w r0,${Dsp-16-u16}[$Dst32AnUnprefixed] */
6943   {
6944     M32C_INSN_XCHG32W_R0_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32,
6945     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6946   },
6947 /* xchg.w r0,${Dsp-16-u24}[$Dst32AnUnprefixed] */
6948   {
6949     M32C_INSN_XCHG32W_R0_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40,
6950     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6951   },
6952 /* xchg.w r0,${Dsp-16-u8}[sb] */
6953   {
6954     M32C_INSN_XCHG32W_R0_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24,
6955     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6956   },
6957 /* xchg.w r0,${Dsp-16-u16}[sb] */
6958   {
6959     M32C_INSN_XCHG32W_R0_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32,
6960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6961   },
6962 /* xchg.w r0,${Dsp-16-s8}[fb] */
6963   {
6964     M32C_INSN_XCHG32W_R0_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24,
6965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6966   },
6967 /* xchg.w r0,${Dsp-16-s16}[fb] */
6968   {
6969     M32C_INSN_XCHG32W_R0_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32,
6970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6971   },
6972 /* xchg.w r0,${Dsp-16-u16} */
6973   {
6974     M32C_INSN_XCHG32W_R0_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32,
6975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6976   },
6977 /* xchg.w r0,${Dsp-16-u24} */
6978   {
6979     M32C_INSN_XCHG32W_R0_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40,
6980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6981   },
6982 /* xchg.b r1h,$Dst32RnUnprefixedQI */
6983   {
6984     M32C_INSN_XCHG32B_R1H_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-r1h-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16,
6985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6986   },
6987 /* xchg.b r1h,$Dst32AnUnprefixedQI */
6988   {
6989     M32C_INSN_XCHG32B_R1H_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-r1h-dst32-An-direct-Unprefixed-QI", "xchg.b", 16,
6990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6991   },
6992 /* xchg.b r1h,[$Dst32AnUnprefixed] */
6993   {
6994     M32C_INSN_XCHG32B_R1H_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-r1h-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16,
6995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6996   },
6997 /* xchg.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
6998   {
6999     M32C_INSN_XCHG32B_R1H_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24,
7000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7001   },
7002 /* xchg.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
7003   {
7004     M32C_INSN_XCHG32B_R1H_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32,
7005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7006   },
7007 /* xchg.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
7008   {
7009     M32C_INSN_XCHG32B_R1H_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40,
7010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7011   },
7012 /* xchg.b r1h,${Dsp-16-u8}[sb] */
7013   {
7014     M32C_INSN_XCHG32B_R1H_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24,
7015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7016   },
7017 /* xchg.b r1h,${Dsp-16-u16}[sb] */
7018   {
7019     M32C_INSN_XCHG32B_R1H_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32,
7020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7021   },
7022 /* xchg.b r1h,${Dsp-16-s8}[fb] */
7023   {
7024     M32C_INSN_XCHG32B_R1H_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24,
7025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7026   },
7027 /* xchg.b r1h,${Dsp-16-s16}[fb] */
7028   {
7029     M32C_INSN_XCHG32B_R1H_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32,
7030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7031   },
7032 /* xchg.b r1h,${Dsp-16-u16} */
7033   {
7034     M32C_INSN_XCHG32B_R1H_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32,
7035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7036   },
7037 /* xchg.b r1h,${Dsp-16-u24} */
7038   {
7039     M32C_INSN_XCHG32B_R1H_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40,
7040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7041   },
7042 /* xchg.b r0h,$Dst32RnUnprefixedQI */
7043   {
7044     M32C_INSN_XCHG32B_R0H_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-r0h-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16,
7045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7046   },
7047 /* xchg.b r0h,$Dst32AnUnprefixedQI */
7048   {
7049     M32C_INSN_XCHG32B_R0H_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-r0h-dst32-An-direct-Unprefixed-QI", "xchg.b", 16,
7050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7051   },
7052 /* xchg.b r0h,[$Dst32AnUnprefixed] */
7053   {
7054     M32C_INSN_XCHG32B_R0H_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-r0h-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16,
7055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7056   },
7057 /* xchg.b r0h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
7058   {
7059     M32C_INSN_XCHG32B_R0H_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24,
7060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7061   },
7062 /* xchg.b r0h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
7063   {
7064     M32C_INSN_XCHG32B_R0H_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32,
7065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7066   },
7067 /* xchg.b r0h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
7068   {
7069     M32C_INSN_XCHG32B_R0H_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40,
7070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7071   },
7072 /* xchg.b r0h,${Dsp-16-u8}[sb] */
7073   {
7074     M32C_INSN_XCHG32B_R0H_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24,
7075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7076   },
7077 /* xchg.b r0h,${Dsp-16-u16}[sb] */
7078   {
7079     M32C_INSN_XCHG32B_R0H_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32,
7080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7081   },
7082 /* xchg.b r0h,${Dsp-16-s8}[fb] */
7083   {
7084     M32C_INSN_XCHG32B_R0H_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24,
7085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7086   },
7087 /* xchg.b r0h,${Dsp-16-s16}[fb] */
7088   {
7089     M32C_INSN_XCHG32B_R0H_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32,
7090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7091   },
7092 /* xchg.b r0h,${Dsp-16-u16} */
7093   {
7094     M32C_INSN_XCHG32B_R0H_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32,
7095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7096   },
7097 /* xchg.b r0h,${Dsp-16-u24} */
7098   {
7099     M32C_INSN_XCHG32B_R0H_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40,
7100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7101   },
7102 /* xchg.b a1,$Dst32RnUnprefixedQI */
7103   {
7104     M32C_INSN_XCHG32B_A1_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-a1-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16,
7105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7106   },
7107 /* xchg.b a1,$Dst32AnUnprefixedQI */
7108   {
7109     M32C_INSN_XCHG32B_A1_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-a1-dst32-An-direct-Unprefixed-QI", "xchg.b", 16,
7110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7111   },
7112 /* xchg.b a1,[$Dst32AnUnprefixed] */
7113   {
7114     M32C_INSN_XCHG32B_A1_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-a1-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16,
7115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7116   },
7117 /* xchg.b a1,${Dsp-16-u8}[$Dst32AnUnprefixed] */
7118   {
7119     M32C_INSN_XCHG32B_A1_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24,
7120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7121   },
7122 /* xchg.b a1,${Dsp-16-u16}[$Dst32AnUnprefixed] */
7123   {
7124     M32C_INSN_XCHG32B_A1_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32,
7125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7126   },
7127 /* xchg.b a1,${Dsp-16-u24}[$Dst32AnUnprefixed] */
7128   {
7129     M32C_INSN_XCHG32B_A1_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40,
7130     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7131   },
7132 /* xchg.b a1,${Dsp-16-u8}[sb] */
7133   {
7134     M32C_INSN_XCHG32B_A1_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24,
7135     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7136   },
7137 /* xchg.b a1,${Dsp-16-u16}[sb] */
7138   {
7139     M32C_INSN_XCHG32B_A1_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32,
7140     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7141   },
7142 /* xchg.b a1,${Dsp-16-s8}[fb] */
7143   {
7144     M32C_INSN_XCHG32B_A1_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24,
7145     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7146   },
7147 /* xchg.b a1,${Dsp-16-s16}[fb] */
7148   {
7149     M32C_INSN_XCHG32B_A1_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32,
7150     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7151   },
7152 /* xchg.b a1,${Dsp-16-u16} */
7153   {
7154     M32C_INSN_XCHG32B_A1_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32,
7155     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7156   },
7157 /* xchg.b a1,${Dsp-16-u24} */
7158   {
7159     M32C_INSN_XCHG32B_A1_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40,
7160     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7161   },
7162 /* xchg.b a0,$Dst32RnUnprefixedQI */
7163   {
7164     M32C_INSN_XCHG32B_A0_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-a0-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16,
7165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7166   },
7167 /* xchg.b a0,$Dst32AnUnprefixedQI */
7168   {
7169     M32C_INSN_XCHG32B_A0_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-a0-dst32-An-direct-Unprefixed-QI", "xchg.b", 16,
7170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7171   },
7172 /* xchg.b a0,[$Dst32AnUnprefixed] */
7173   {
7174     M32C_INSN_XCHG32B_A0_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-a0-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16,
7175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7176   },
7177 /* xchg.b a0,${Dsp-16-u8}[$Dst32AnUnprefixed] */
7178   {
7179     M32C_INSN_XCHG32B_A0_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24,
7180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7181   },
7182 /* xchg.b a0,${Dsp-16-u16}[$Dst32AnUnprefixed] */
7183   {
7184     M32C_INSN_XCHG32B_A0_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32,
7185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7186   },
7187 /* xchg.b a0,${Dsp-16-u24}[$Dst32AnUnprefixed] */
7188   {
7189     M32C_INSN_XCHG32B_A0_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40,
7190     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7191   },
7192 /* xchg.b a0,${Dsp-16-u8}[sb] */
7193   {
7194     M32C_INSN_XCHG32B_A0_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24,
7195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7196   },
7197 /* xchg.b a0,${Dsp-16-u16}[sb] */
7198   {
7199     M32C_INSN_XCHG32B_A0_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32,
7200     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7201   },
7202 /* xchg.b a0,${Dsp-16-s8}[fb] */
7203   {
7204     M32C_INSN_XCHG32B_A0_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24,
7205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7206   },
7207 /* xchg.b a0,${Dsp-16-s16}[fb] */
7208   {
7209     M32C_INSN_XCHG32B_A0_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32,
7210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7211   },
7212 /* xchg.b a0,${Dsp-16-u16} */
7213   {
7214     M32C_INSN_XCHG32B_A0_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32,
7215     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7216   },
7217 /* xchg.b a0,${Dsp-16-u24} */
7218   {
7219     M32C_INSN_XCHG32B_A0_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40,
7220     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7221   },
7222 /* xchg.b r1l,$Dst32RnUnprefixedQI */
7223   {
7224     M32C_INSN_XCHG32B_R1L_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-r1l-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16,
7225     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7226   },
7227 /* xchg.b r1l,$Dst32AnUnprefixedQI */
7228   {
7229     M32C_INSN_XCHG32B_R1L_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-r1l-dst32-An-direct-Unprefixed-QI", "xchg.b", 16,
7230     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7231   },
7232 /* xchg.b r1l,[$Dst32AnUnprefixed] */
7233   {
7234     M32C_INSN_XCHG32B_R1L_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-r1l-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16,
7235     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7236   },
7237 /* xchg.b r1l,${Dsp-16-u8}[$Dst32AnUnprefixed] */
7238   {
7239     M32C_INSN_XCHG32B_R1L_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24,
7240     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7241   },
7242 /* xchg.b r1l,${Dsp-16-u16}[$Dst32AnUnprefixed] */
7243   {
7244     M32C_INSN_XCHG32B_R1L_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32,
7245     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7246   },
7247 /* xchg.b r1l,${Dsp-16-u24}[$Dst32AnUnprefixed] */
7248   {
7249     M32C_INSN_XCHG32B_R1L_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40,
7250     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7251   },
7252 /* xchg.b r1l,${Dsp-16-u8}[sb] */
7253   {
7254     M32C_INSN_XCHG32B_R1L_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24,
7255     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7256   },
7257 /* xchg.b r1l,${Dsp-16-u16}[sb] */
7258   {
7259     M32C_INSN_XCHG32B_R1L_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32,
7260     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7261   },
7262 /* xchg.b r1l,${Dsp-16-s8}[fb] */
7263   {
7264     M32C_INSN_XCHG32B_R1L_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24,
7265     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7266   },
7267 /* xchg.b r1l,${Dsp-16-s16}[fb] */
7268   {
7269     M32C_INSN_XCHG32B_R1L_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32,
7270     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7271   },
7272 /* xchg.b r1l,${Dsp-16-u16} */
7273   {
7274     M32C_INSN_XCHG32B_R1L_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32,
7275     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7276   },
7277 /* xchg.b r1l,${Dsp-16-u24} */
7278   {
7279     M32C_INSN_XCHG32B_R1L_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40,
7280     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7281   },
7282 /* xchg.b r0l,$Dst32RnUnprefixedQI */
7283   {
7284     M32C_INSN_XCHG32B_R0L_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-r0l-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16,
7285     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7286   },
7287 /* xchg.b r0l,$Dst32AnUnprefixedQI */
7288   {
7289     M32C_INSN_XCHG32B_R0L_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-r0l-dst32-An-direct-Unprefixed-QI", "xchg.b", 16,
7290     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7291   },
7292 /* xchg.b r0l,[$Dst32AnUnprefixed] */
7293   {
7294     M32C_INSN_XCHG32B_R0L_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-r0l-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16,
7295     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7296   },
7297 /* xchg.b r0l,${Dsp-16-u8}[$Dst32AnUnprefixed] */
7298   {
7299     M32C_INSN_XCHG32B_R0L_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24,
7300     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7301   },
7302 /* xchg.b r0l,${Dsp-16-u16}[$Dst32AnUnprefixed] */
7303   {
7304     M32C_INSN_XCHG32B_R0L_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32,
7305     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7306   },
7307 /* xchg.b r0l,${Dsp-16-u24}[$Dst32AnUnprefixed] */
7308   {
7309     M32C_INSN_XCHG32B_R0L_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40,
7310     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7311   },
7312 /* xchg.b r0l,${Dsp-16-u8}[sb] */
7313   {
7314     M32C_INSN_XCHG32B_R0L_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24,
7315     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7316   },
7317 /* xchg.b r0l,${Dsp-16-u16}[sb] */
7318   {
7319     M32C_INSN_XCHG32B_R0L_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32,
7320     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7321   },
7322 /* xchg.b r0l,${Dsp-16-s8}[fb] */
7323   {
7324     M32C_INSN_XCHG32B_R0L_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24,
7325     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7326   },
7327 /* xchg.b r0l,${Dsp-16-s16}[fb] */
7328   {
7329     M32C_INSN_XCHG32B_R0L_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32,
7330     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7331   },
7332 /* xchg.b r0l,${Dsp-16-u16} */
7333   {
7334     M32C_INSN_XCHG32B_R0L_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32,
7335     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7336   },
7337 /* xchg.b r0l,${Dsp-16-u24} */
7338   {
7339     M32C_INSN_XCHG32B_R0L_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40,
7340     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7341   },
7342 /* xchg.w r3,$Dst16RnHI */
7343   {
7344     M32C_INSN_XCHG16W_R3_DST16_RN_DIRECT_HI, "xchg16w-r3-dst16-Rn-direct-HI", "xchg.w", 16,
7345     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7346   },
7347 /* xchg.w r3,$Dst16AnHI */
7348   {
7349     M32C_INSN_XCHG16W_R3_DST16_AN_DIRECT_HI, "xchg16w-r3-dst16-An-direct-HI", "xchg.w", 16,
7350     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7351   },
7352 /* xchg.w r3,[$Dst16An] */
7353   {
7354     M32C_INSN_XCHG16W_R3_DST16_AN_INDIRECT_HI, "xchg16w-r3-dst16-An-indirect-HI", "xchg.w", 16,
7355     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7356   },
7357 /* xchg.w r3,${Dsp-16-u8}[$Dst16An] */
7358   {
7359     M32C_INSN_XCHG16W_R3_DST16_16_8_AN_RELATIVE_HI, "xchg16w-r3-dst16-16-8-An-relative-HI", "xchg.w", 24,
7360     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7361   },
7362 /* xchg.w r3,${Dsp-16-u16}[$Dst16An] */
7363   {
7364     M32C_INSN_XCHG16W_R3_DST16_16_16_AN_RELATIVE_HI, "xchg16w-r3-dst16-16-16-An-relative-HI", "xchg.w", 32,
7365     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7366   },
7367 /* xchg.w r3,${Dsp-16-u8}[sb] */
7368   {
7369     M32C_INSN_XCHG16W_R3_DST16_16_8_SB_RELATIVE_HI, "xchg16w-r3-dst16-16-8-SB-relative-HI", "xchg.w", 24,
7370     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7371   },
7372 /* xchg.w r3,${Dsp-16-u16}[sb] */
7373   {
7374     M32C_INSN_XCHG16W_R3_DST16_16_16_SB_RELATIVE_HI, "xchg16w-r3-dst16-16-16-SB-relative-HI", "xchg.w", 32,
7375     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7376   },
7377 /* xchg.w r3,${Dsp-16-s8}[fb] */
7378   {
7379     M32C_INSN_XCHG16W_R3_DST16_16_8_FB_RELATIVE_HI, "xchg16w-r3-dst16-16-8-FB-relative-HI", "xchg.w", 24,
7380     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7381   },
7382 /* xchg.w r3,${Dsp-16-u16} */
7383   {
7384     M32C_INSN_XCHG16W_R3_DST16_16_16_ABSOLUTE_HI, "xchg16w-r3-dst16-16-16-absolute-HI", "xchg.w", 32,
7385     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7386   },
7387 /* xchg.w r2,$Dst16RnHI */
7388   {
7389     M32C_INSN_XCHG16W_R2_DST16_RN_DIRECT_HI, "xchg16w-r2-dst16-Rn-direct-HI", "xchg.w", 16,
7390     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7391   },
7392 /* xchg.w r2,$Dst16AnHI */
7393   {
7394     M32C_INSN_XCHG16W_R2_DST16_AN_DIRECT_HI, "xchg16w-r2-dst16-An-direct-HI", "xchg.w", 16,
7395     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7396   },
7397 /* xchg.w r2,[$Dst16An] */
7398   {
7399     M32C_INSN_XCHG16W_R2_DST16_AN_INDIRECT_HI, "xchg16w-r2-dst16-An-indirect-HI", "xchg.w", 16,
7400     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7401   },
7402 /* xchg.w r2,${Dsp-16-u8}[$Dst16An] */
7403   {
7404     M32C_INSN_XCHG16W_R2_DST16_16_8_AN_RELATIVE_HI, "xchg16w-r2-dst16-16-8-An-relative-HI", "xchg.w", 24,
7405     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7406   },
7407 /* xchg.w r2,${Dsp-16-u16}[$Dst16An] */
7408   {
7409     M32C_INSN_XCHG16W_R2_DST16_16_16_AN_RELATIVE_HI, "xchg16w-r2-dst16-16-16-An-relative-HI", "xchg.w", 32,
7410     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7411   },
7412 /* xchg.w r2,${Dsp-16-u8}[sb] */
7413   {
7414     M32C_INSN_XCHG16W_R2_DST16_16_8_SB_RELATIVE_HI, "xchg16w-r2-dst16-16-8-SB-relative-HI", "xchg.w", 24,
7415     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7416   },
7417 /* xchg.w r2,${Dsp-16-u16}[sb] */
7418   {
7419     M32C_INSN_XCHG16W_R2_DST16_16_16_SB_RELATIVE_HI, "xchg16w-r2-dst16-16-16-SB-relative-HI", "xchg.w", 32,
7420     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7421   },
7422 /* xchg.w r2,${Dsp-16-s8}[fb] */
7423   {
7424     M32C_INSN_XCHG16W_R2_DST16_16_8_FB_RELATIVE_HI, "xchg16w-r2-dst16-16-8-FB-relative-HI", "xchg.w", 24,
7425     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7426   },
7427 /* xchg.w r2,${Dsp-16-u16} */
7428   {
7429     M32C_INSN_XCHG16W_R2_DST16_16_16_ABSOLUTE_HI, "xchg16w-r2-dst16-16-16-absolute-HI", "xchg.w", 32,
7430     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7431   },
7432 /* xchg.w r1,$Dst16RnHI */
7433   {
7434     M32C_INSN_XCHG16W_R1_DST16_RN_DIRECT_HI, "xchg16w-r1-dst16-Rn-direct-HI", "xchg.w", 16,
7435     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7436   },
7437 /* xchg.w r1,$Dst16AnHI */
7438   {
7439     M32C_INSN_XCHG16W_R1_DST16_AN_DIRECT_HI, "xchg16w-r1-dst16-An-direct-HI", "xchg.w", 16,
7440     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7441   },
7442 /* xchg.w r1,[$Dst16An] */
7443   {
7444     M32C_INSN_XCHG16W_R1_DST16_AN_INDIRECT_HI, "xchg16w-r1-dst16-An-indirect-HI", "xchg.w", 16,
7445     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7446   },
7447 /* xchg.w r1,${Dsp-16-u8}[$Dst16An] */
7448   {
7449     M32C_INSN_XCHG16W_R1_DST16_16_8_AN_RELATIVE_HI, "xchg16w-r1-dst16-16-8-An-relative-HI", "xchg.w", 24,
7450     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7451   },
7452 /* xchg.w r1,${Dsp-16-u16}[$Dst16An] */
7453   {
7454     M32C_INSN_XCHG16W_R1_DST16_16_16_AN_RELATIVE_HI, "xchg16w-r1-dst16-16-16-An-relative-HI", "xchg.w", 32,
7455     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7456   },
7457 /* xchg.w r1,${Dsp-16-u8}[sb] */
7458   {
7459     M32C_INSN_XCHG16W_R1_DST16_16_8_SB_RELATIVE_HI, "xchg16w-r1-dst16-16-8-SB-relative-HI", "xchg.w", 24,
7460     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7461   },
7462 /* xchg.w r1,${Dsp-16-u16}[sb] */
7463   {
7464     M32C_INSN_XCHG16W_R1_DST16_16_16_SB_RELATIVE_HI, "xchg16w-r1-dst16-16-16-SB-relative-HI", "xchg.w", 32,
7465     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7466   },
7467 /* xchg.w r1,${Dsp-16-s8}[fb] */
7468   {
7469     M32C_INSN_XCHG16W_R1_DST16_16_8_FB_RELATIVE_HI, "xchg16w-r1-dst16-16-8-FB-relative-HI", "xchg.w", 24,
7470     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7471   },
7472 /* xchg.w r1,${Dsp-16-u16} */
7473   {
7474     M32C_INSN_XCHG16W_R1_DST16_16_16_ABSOLUTE_HI, "xchg16w-r1-dst16-16-16-absolute-HI", "xchg.w", 32,
7475     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7476   },
7477 /* xchg.w r0,$Dst16RnHI */
7478   {
7479     M32C_INSN_XCHG16W_R0_DST16_RN_DIRECT_HI, "xchg16w-r0-dst16-Rn-direct-HI", "xchg.w", 16,
7480     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7481   },
7482 /* xchg.w r0,$Dst16AnHI */
7483   {
7484     M32C_INSN_XCHG16W_R0_DST16_AN_DIRECT_HI, "xchg16w-r0-dst16-An-direct-HI", "xchg.w", 16,
7485     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7486   },
7487 /* xchg.w r0,[$Dst16An] */
7488   {
7489     M32C_INSN_XCHG16W_R0_DST16_AN_INDIRECT_HI, "xchg16w-r0-dst16-An-indirect-HI", "xchg.w", 16,
7490     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7491   },
7492 /* xchg.w r0,${Dsp-16-u8}[$Dst16An] */
7493   {
7494     M32C_INSN_XCHG16W_R0_DST16_16_8_AN_RELATIVE_HI, "xchg16w-r0-dst16-16-8-An-relative-HI", "xchg.w", 24,
7495     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7496   },
7497 /* xchg.w r0,${Dsp-16-u16}[$Dst16An] */
7498   {
7499     M32C_INSN_XCHG16W_R0_DST16_16_16_AN_RELATIVE_HI, "xchg16w-r0-dst16-16-16-An-relative-HI", "xchg.w", 32,
7500     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7501   },
7502 /* xchg.w r0,${Dsp-16-u8}[sb] */
7503   {
7504     M32C_INSN_XCHG16W_R0_DST16_16_8_SB_RELATIVE_HI, "xchg16w-r0-dst16-16-8-SB-relative-HI", "xchg.w", 24,
7505     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7506   },
7507 /* xchg.w r0,${Dsp-16-u16}[sb] */
7508   {
7509     M32C_INSN_XCHG16W_R0_DST16_16_16_SB_RELATIVE_HI, "xchg16w-r0-dst16-16-16-SB-relative-HI", "xchg.w", 32,
7510     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7511   },
7512 /* xchg.w r0,${Dsp-16-s8}[fb] */
7513   {
7514     M32C_INSN_XCHG16W_R0_DST16_16_8_FB_RELATIVE_HI, "xchg16w-r0-dst16-16-8-FB-relative-HI", "xchg.w", 24,
7515     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7516   },
7517 /* xchg.w r0,${Dsp-16-u16} */
7518   {
7519     M32C_INSN_XCHG16W_R0_DST16_16_16_ABSOLUTE_HI, "xchg16w-r0-dst16-16-16-absolute-HI", "xchg.w", 32,
7520     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7521   },
7522 /* xchg.b r1h,$Dst16RnQI */
7523   {
7524     M32C_INSN_XCHG16B_R1H_DST16_RN_DIRECT_QI, "xchg16b-r1h-dst16-Rn-direct-QI", "xchg.b", 16,
7525     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7526   },
7527 /* xchg.b r1h,$Dst16AnQI */
7528   {
7529     M32C_INSN_XCHG16B_R1H_DST16_AN_DIRECT_QI, "xchg16b-r1h-dst16-An-direct-QI", "xchg.b", 16,
7530     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7531   },
7532 /* xchg.b r1h,[$Dst16An] */
7533   {
7534     M32C_INSN_XCHG16B_R1H_DST16_AN_INDIRECT_QI, "xchg16b-r1h-dst16-An-indirect-QI", "xchg.b", 16,
7535     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7536   },
7537 /* xchg.b r1h,${Dsp-16-u8}[$Dst16An] */
7538   {
7539     M32C_INSN_XCHG16B_R1H_DST16_16_8_AN_RELATIVE_QI, "xchg16b-r1h-dst16-16-8-An-relative-QI", "xchg.b", 24,
7540     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7541   },
7542 /* xchg.b r1h,${Dsp-16-u16}[$Dst16An] */
7543   {
7544     M32C_INSN_XCHG16B_R1H_DST16_16_16_AN_RELATIVE_QI, "xchg16b-r1h-dst16-16-16-An-relative-QI", "xchg.b", 32,
7545     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7546   },
7547 /* xchg.b r1h,${Dsp-16-u8}[sb] */
7548   {
7549     M32C_INSN_XCHG16B_R1H_DST16_16_8_SB_RELATIVE_QI, "xchg16b-r1h-dst16-16-8-SB-relative-QI", "xchg.b", 24,
7550     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7551   },
7552 /* xchg.b r1h,${Dsp-16-u16}[sb] */
7553   {
7554     M32C_INSN_XCHG16B_R1H_DST16_16_16_SB_RELATIVE_QI, "xchg16b-r1h-dst16-16-16-SB-relative-QI", "xchg.b", 32,
7555     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7556   },
7557 /* xchg.b r1h,${Dsp-16-s8}[fb] */
7558   {
7559     M32C_INSN_XCHG16B_R1H_DST16_16_8_FB_RELATIVE_QI, "xchg16b-r1h-dst16-16-8-FB-relative-QI", "xchg.b", 24,
7560     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7561   },
7562 /* xchg.b r1h,${Dsp-16-u16} */
7563   {
7564     M32C_INSN_XCHG16B_R1H_DST16_16_16_ABSOLUTE_QI, "xchg16b-r1h-dst16-16-16-absolute-QI", "xchg.b", 32,
7565     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7566   },
7567 /* xchg.b r1l,$Dst16RnQI */
7568   {
7569     M32C_INSN_XCHG16B_R1L_DST16_RN_DIRECT_QI, "xchg16b-r1l-dst16-Rn-direct-QI", "xchg.b", 16,
7570     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7571   },
7572 /* xchg.b r1l,$Dst16AnQI */
7573   {
7574     M32C_INSN_XCHG16B_R1L_DST16_AN_DIRECT_QI, "xchg16b-r1l-dst16-An-direct-QI", "xchg.b", 16,
7575     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7576   },
7577 /* xchg.b r1l,[$Dst16An] */
7578   {
7579     M32C_INSN_XCHG16B_R1L_DST16_AN_INDIRECT_QI, "xchg16b-r1l-dst16-An-indirect-QI", "xchg.b", 16,
7580     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7581   },
7582 /* xchg.b r1l,${Dsp-16-u8}[$Dst16An] */
7583   {
7584     M32C_INSN_XCHG16B_R1L_DST16_16_8_AN_RELATIVE_QI, "xchg16b-r1l-dst16-16-8-An-relative-QI", "xchg.b", 24,
7585     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7586   },
7587 /* xchg.b r1l,${Dsp-16-u16}[$Dst16An] */
7588   {
7589     M32C_INSN_XCHG16B_R1L_DST16_16_16_AN_RELATIVE_QI, "xchg16b-r1l-dst16-16-16-An-relative-QI", "xchg.b", 32,
7590     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7591   },
7592 /* xchg.b r1l,${Dsp-16-u8}[sb] */
7593   {
7594     M32C_INSN_XCHG16B_R1L_DST16_16_8_SB_RELATIVE_QI, "xchg16b-r1l-dst16-16-8-SB-relative-QI", "xchg.b", 24,
7595     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7596   },
7597 /* xchg.b r1l,${Dsp-16-u16}[sb] */
7598   {
7599     M32C_INSN_XCHG16B_R1L_DST16_16_16_SB_RELATIVE_QI, "xchg16b-r1l-dst16-16-16-SB-relative-QI", "xchg.b", 32,
7600     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7601   },
7602 /* xchg.b r1l,${Dsp-16-s8}[fb] */
7603   {
7604     M32C_INSN_XCHG16B_R1L_DST16_16_8_FB_RELATIVE_QI, "xchg16b-r1l-dst16-16-8-FB-relative-QI", "xchg.b", 24,
7605     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7606   },
7607 /* xchg.b r1l,${Dsp-16-u16} */
7608   {
7609     M32C_INSN_XCHG16B_R1L_DST16_16_16_ABSOLUTE_QI, "xchg16b-r1l-dst16-16-16-absolute-QI", "xchg.b", 32,
7610     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7611   },
7612 /* xchg.b r0h,$Dst16RnQI */
7613   {
7614     M32C_INSN_XCHG16B_R0H_DST16_RN_DIRECT_QI, "xchg16b-r0h-dst16-Rn-direct-QI", "xchg.b", 16,
7615     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7616   },
7617 /* xchg.b r0h,$Dst16AnQI */
7618   {
7619     M32C_INSN_XCHG16B_R0H_DST16_AN_DIRECT_QI, "xchg16b-r0h-dst16-An-direct-QI", "xchg.b", 16,
7620     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7621   },
7622 /* xchg.b r0h,[$Dst16An] */
7623   {
7624     M32C_INSN_XCHG16B_R0H_DST16_AN_INDIRECT_QI, "xchg16b-r0h-dst16-An-indirect-QI", "xchg.b", 16,
7625     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7626   },
7627 /* xchg.b r0h,${Dsp-16-u8}[$Dst16An] */
7628   {
7629     M32C_INSN_XCHG16B_R0H_DST16_16_8_AN_RELATIVE_QI, "xchg16b-r0h-dst16-16-8-An-relative-QI", "xchg.b", 24,
7630     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7631   },
7632 /* xchg.b r0h,${Dsp-16-u16}[$Dst16An] */
7633   {
7634     M32C_INSN_XCHG16B_R0H_DST16_16_16_AN_RELATIVE_QI, "xchg16b-r0h-dst16-16-16-An-relative-QI", "xchg.b", 32,
7635     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7636   },
7637 /* xchg.b r0h,${Dsp-16-u8}[sb] */
7638   {
7639     M32C_INSN_XCHG16B_R0H_DST16_16_8_SB_RELATIVE_QI, "xchg16b-r0h-dst16-16-8-SB-relative-QI", "xchg.b", 24,
7640     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7641   },
7642 /* xchg.b r0h,${Dsp-16-u16}[sb] */
7643   {
7644     M32C_INSN_XCHG16B_R0H_DST16_16_16_SB_RELATIVE_QI, "xchg16b-r0h-dst16-16-16-SB-relative-QI", "xchg.b", 32,
7645     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7646   },
7647 /* xchg.b r0h,${Dsp-16-s8}[fb] */
7648   {
7649     M32C_INSN_XCHG16B_R0H_DST16_16_8_FB_RELATIVE_QI, "xchg16b-r0h-dst16-16-8-FB-relative-QI", "xchg.b", 24,
7650     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7651   },
7652 /* xchg.b r0h,${Dsp-16-u16} */
7653   {
7654     M32C_INSN_XCHG16B_R0H_DST16_16_16_ABSOLUTE_QI, "xchg16b-r0h-dst16-16-16-absolute-QI", "xchg.b", 32,
7655     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7656   },
7657 /* xchg.b r0l,$Dst16RnQI */
7658   {
7659     M32C_INSN_XCHG16B_R0L_DST16_RN_DIRECT_QI, "xchg16b-r0l-dst16-Rn-direct-QI", "xchg.b", 16,
7660     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7661   },
7662 /* xchg.b r0l,$Dst16AnQI */
7663   {
7664     M32C_INSN_XCHG16B_R0L_DST16_AN_DIRECT_QI, "xchg16b-r0l-dst16-An-direct-QI", "xchg.b", 16,
7665     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7666   },
7667 /* xchg.b r0l,[$Dst16An] */
7668   {
7669     M32C_INSN_XCHG16B_R0L_DST16_AN_INDIRECT_QI, "xchg16b-r0l-dst16-An-indirect-QI", "xchg.b", 16,
7670     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7671   },
7672 /* xchg.b r0l,${Dsp-16-u8}[$Dst16An] */
7673   {
7674     M32C_INSN_XCHG16B_R0L_DST16_16_8_AN_RELATIVE_QI, "xchg16b-r0l-dst16-16-8-An-relative-QI", "xchg.b", 24,
7675     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7676   },
7677 /* xchg.b r0l,${Dsp-16-u16}[$Dst16An] */
7678   {
7679     M32C_INSN_XCHG16B_R0L_DST16_16_16_AN_RELATIVE_QI, "xchg16b-r0l-dst16-16-16-An-relative-QI", "xchg.b", 32,
7680     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7681   },
7682 /* xchg.b r0l,${Dsp-16-u8}[sb] */
7683   {
7684     M32C_INSN_XCHG16B_R0L_DST16_16_8_SB_RELATIVE_QI, "xchg16b-r0l-dst16-16-8-SB-relative-QI", "xchg.b", 24,
7685     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7686   },
7687 /* xchg.b r0l,${Dsp-16-u16}[sb] */
7688   {
7689     M32C_INSN_XCHG16B_R0L_DST16_16_16_SB_RELATIVE_QI, "xchg16b-r0l-dst16-16-16-SB-relative-QI", "xchg.b", 32,
7690     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7691   },
7692 /* xchg.b r0l,${Dsp-16-s8}[fb] */
7693   {
7694     M32C_INSN_XCHG16B_R0L_DST16_16_8_FB_RELATIVE_QI, "xchg16b-r0l-dst16-16-8-FB-relative-QI", "xchg.b", 24,
7695     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7696   },
7697 /* xchg.b r0l,${Dsp-16-u16} */
7698   {
7699     M32C_INSN_XCHG16B_R0L_DST16_16_16_ABSOLUTE_QI, "xchg16b-r0l-dst16-16-16-absolute-QI", "xchg.b", 32,
7700     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7701   },
7702 /* tst.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
7703   {
7704     M32C_INSN_TST32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "tst32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "tst.w", 32,
7705     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7706   },
7707 /* tst.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
7708   {
7709     M32C_INSN_TST32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "tst32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "tst.w", 32,
7710     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7711   },
7712 /* tst.w${S} #${Imm-24-HI},${Dsp-8-u16} */
7713   {
7714     M32C_INSN_TST32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "tst32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "tst.w", 40,
7715     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7716   },
7717 /* tst.w${S} #${Imm-8-HI},r0 */
7718   {
7719     M32C_INSN_TST32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "tst32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "tst.w", 24,
7720     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7721   },
7722 /* tst.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
7723   {
7724     M32C_INSN_TST32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "tst32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "tst.b", 24,
7725     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7726   },
7727 /* tst.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
7728   {
7729     M32C_INSN_TST32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "tst32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "tst.b", 24,
7730     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7731   },
7732 /* tst.b${S} #${Imm-24-QI},${Dsp-8-u16} */
7733   {
7734     M32C_INSN_TST32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "tst32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "tst.b", 32,
7735     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7736   },
7737 /* tst.b${S} #${Imm-8-QI},r0l */
7738   {
7739     M32C_INSN_TST32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "tst32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "tst.b", 16,
7740     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7741   },
7742 /* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
7743   {
7744     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 32,
7745     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7746   },
7747 /* tst.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
7748   {
7749     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 32,
7750     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7751   },
7752 /* tst.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
7753   {
7754     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 32,
7755     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7756   },
7757 /* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
7758   {
7759     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 32,
7760     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7761   },
7762 /* tst.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
7763   {
7764     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 32,
7765     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7766   },
7767 /* tst.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
7768   {
7769     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 32,
7770     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7771   },
7772 /* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
7773   {
7774     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 32,
7775     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7776   },
7777 /* tst.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
7778   {
7779     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 32,
7780     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7781   },
7782 /* tst.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
7783   {
7784     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 32,
7785     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7786   },
7787 /* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
7788   {
7789     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "tst.w", 40,
7790     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7791   },
7792 /* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
7793   {
7794     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "tst.w", 40,
7795     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7796   },
7797 /* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
7798   {
7799     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "tst.w", 40,
7800     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7801   },
7802 /* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
7803   {
7804     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "tst.w", 48,
7805     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7806   },
7807 /* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
7808   {
7809     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "tst.w", 48,
7810     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7811   },
7812 /* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
7813   {
7814     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "tst.w", 48,
7815     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7816   },
7817 /* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
7818   {
7819     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "tst.w", 56,
7820     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7821   },
7822 /* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
7823   {
7824     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "tst.w", 56,
7825     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7826   },
7827 /* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
7828   {
7829     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "tst.w", 56,
7830     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7831   },
7832 /* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
7833   {
7834     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "tst.w", 40,
7835     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7836   },
7837 /* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
7838   {
7839     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "tst.w", 40,
7840     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7841   },
7842 /* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
7843   {
7844     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "tst.w", 40,
7845     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7846   },
7847 /* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
7848   {
7849     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "tst.w", 48,
7850     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7851   },
7852 /* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
7853   {
7854     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "tst.w", 48,
7855     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7856   },
7857 /* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
7858   {
7859     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "tst.w", 48,
7860     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7861   },
7862 /* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
7863   {
7864     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "tst.w", 40,
7865     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7866   },
7867 /* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
7868   {
7869     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "tst.w", 40,
7870     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7871   },
7872 /* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
7873   {
7874     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "tst.w", 40,
7875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7876   },
7877 /* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
7878   {
7879     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "tst.w", 48,
7880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7881   },
7882 /* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
7883   {
7884     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "tst.w", 48,
7885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7886   },
7887 /* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
7888   {
7889     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "tst.w", 48,
7890     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7891   },
7892 /* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
7893   {
7894     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "tst.w", 48,
7895     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7896   },
7897 /* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
7898   {
7899     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "tst.w", 48,
7900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7901   },
7902 /* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
7903   {
7904     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "tst.w", 48,
7905     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7906   },
7907 /* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
7908   {
7909     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "tst.w", 56,
7910     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7911   },
7912 /* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
7913   {
7914     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "tst.w", 56,
7915     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7916   },
7917 /* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
7918   {
7919     M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "tst.w", 56,
7920     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7921   },
7922 /* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
7923   {
7924     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 40,
7925     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7926   },
7927 /* tst.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
7928   {
7929     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 40,
7930     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7931   },
7932 /* tst.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
7933   {
7934     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 40,
7935     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7936   },
7937 /* tst.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
7938   {
7939     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 40,
7940     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7941   },
7942 /* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
7943   {
7944     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 40,
7945     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7946   },
7947 /* tst.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
7948   {
7949     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 40,
7950     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7951   },
7952 /* tst.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
7953   {
7954     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 40,
7955     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7956   },
7957 /* tst.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
7958   {
7959     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 40,
7960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7961   },
7962 /* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
7963   {
7964     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 40,
7965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7966   },
7967 /* tst.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
7968   {
7969     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 40,
7970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7971   },
7972 /* tst.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
7973   {
7974     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 40,
7975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7976   },
7977 /* tst.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
7978   {
7979     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 40,
7980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7981   },
7982 /* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
7983   {
7984     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "tst.w", 48,
7985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7986   },
7987 /* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
7988   {
7989     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "tst.w", 48,
7990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7991   },
7992 /* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
7993   {
7994     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "tst.w", 48,
7995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7996   },
7997 /* tst.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
7998   {
7999     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "tst.w", 48,
8000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8001   },
8002 /* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
8003   {
8004     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "tst.w", 56,
8005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8006   },
8007 /* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
8008   {
8009     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "tst.w", 56,
8010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8011   },
8012 /* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
8013   {
8014     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "tst.w", 56,
8015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8016   },
8017 /* tst.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
8018   {
8019     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "tst.w", 56,
8020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8021   },
8022 /* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
8023   {
8024     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "tst.w", 64,
8025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8026   },
8027 /* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
8028   {
8029     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "tst.w", 64,
8030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8031   },
8032 /* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
8033   {
8034     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "tst.w", 64,
8035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8036   },
8037 /* tst.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
8038   {
8039     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "tst.w", 64,
8040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8041   },
8042 /* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
8043   {
8044     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "tst.w", 48,
8045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8046   },
8047 /* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
8048   {
8049     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "tst.w", 48,
8050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8051   },
8052 /* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
8053   {
8054     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "tst.w", 48,
8055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8056   },
8057 /* tst.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
8058   {
8059     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "tst.w", 48,
8060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8061   },
8062 /* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
8063   {
8064     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "tst.w", 56,
8065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8066   },
8067 /* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
8068   {
8069     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "tst.w", 56,
8070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8071   },
8072 /* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
8073   {
8074     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "tst.w", 56,
8075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8076   },
8077 /* tst.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
8078   {
8079     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "tst.w", 56,
8080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8081   },
8082 /* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
8083   {
8084     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "tst.w", 48,
8085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8086   },
8087 /* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
8088   {
8089     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "tst.w", 48,
8090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8091   },
8092 /* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
8093   {
8094     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "tst.w", 48,
8095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8096   },
8097 /* tst.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
8098   {
8099     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "tst.w", 48,
8100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8101   },
8102 /* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
8103   {
8104     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "tst.w", 56,
8105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8106   },
8107 /* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
8108   {
8109     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "tst.w", 56,
8110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8111   },
8112 /* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
8113   {
8114     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "tst.w", 56,
8115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8116   },
8117 /* tst.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
8118   {
8119     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "tst.w", 56,
8120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8121   },
8122 /* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
8123   {
8124     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "tst.w", 56,
8125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8126   },
8127 /* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
8128   {
8129     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "tst.w", 56,
8130     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8131   },
8132 /* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
8133   {
8134     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "tst.w", 56,
8135     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8136   },
8137 /* tst.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
8138   {
8139     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "tst.w", 56,
8140     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8141   },
8142 /* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
8143   {
8144     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "tst.w", 64,
8145     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8146   },
8147 /* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
8148   {
8149     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "tst.w", 64,
8150     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8151   },
8152 /* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
8153   {
8154     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "tst.w", 64,
8155     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8156   },
8157 /* tst.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
8158   {
8159     M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "tst.w", 64,
8160     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8161   },
8162 /* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
8163   {
8164     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 48,
8165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8166   },
8167 /* tst.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
8168   {
8169     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 48,
8170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8171   },
8172 /* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
8173   {
8174     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 48,
8175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8176   },
8177 /* tst.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
8178   {
8179     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 48,
8180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8181   },
8182 /* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
8183   {
8184     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 48,
8185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8186   },
8187 /* tst.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
8188   {
8189     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 48,
8190     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8191   },
8192 /* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
8193   {
8194     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "tst.w", 56,
8195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8196   },
8197 /* tst.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
8198   {
8199     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "tst.w", 56,
8200     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8201   },
8202 /* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
8203   {
8204     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "tst.w", 64,
8205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8206   },
8207 /* tst.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
8208   {
8209     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "tst.w", 64,
8210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8211   },
8212 /* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
8213   {
8214     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "tst.w", 72,
8215     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8216   },
8217 /* tst.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
8218   {
8219     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "tst.w", 72,
8220     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8221   },
8222 /* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
8223   {
8224     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "tst.w", 56,
8225     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8226   },
8227 /* tst.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
8228   {
8229     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "tst.w", 56,
8230     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8231   },
8232 /* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
8233   {
8234     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "tst.w", 64,
8235     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8236   },
8237 /* tst.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
8238   {
8239     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "tst.w", 64,
8240     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8241   },
8242 /* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
8243   {
8244     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "tst.w", 56,
8245     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8246   },
8247 /* tst.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
8248   {
8249     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "tst.w", 56,
8250     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8251   },
8252 /* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
8253   {
8254     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "tst.w", 64,
8255     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8256   },
8257 /* tst.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
8258   {
8259     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "tst.w", 64,
8260     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8261   },
8262 /* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
8263   {
8264     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "tst.w", 64,
8265     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8266   },
8267 /* tst.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
8268   {
8269     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "tst.w", 64,
8270     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8271   },
8272 /* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
8273   {
8274     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "tst.w", 72,
8275     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8276   },
8277 /* tst.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
8278   {
8279     M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "tst.w", 72,
8280     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8281   },
8282 /* tst.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
8283   {
8284     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 24,
8285     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8286   },
8287 /* tst.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
8288   {
8289     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 24,
8290     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8291   },
8292 /* tst.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
8293   {
8294     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 24,
8295     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8296   },
8297 /* tst.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
8298   {
8299     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 24,
8300     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8301   },
8302 /* tst.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
8303   {
8304     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 24,
8305     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8306   },
8307 /* tst.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
8308   {
8309     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 24,
8310     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8311   },
8312 /* tst.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
8313   {
8314     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 24,
8315     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8316   },
8317 /* tst.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
8318   {
8319     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 24,
8320     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8321   },
8322 /* tst.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
8323   {
8324     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 24,
8325     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8326   },
8327 /* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
8328   {
8329     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "tst.w", 32,
8330     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8331   },
8332 /* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
8333   {
8334     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "tst.w", 32,
8335     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8336   },
8337 /* tst.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
8338   {
8339     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "tst.w", 32,
8340     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8341   },
8342 /* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
8343   {
8344     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "tst.w", 40,
8345     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8346   },
8347 /* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
8348   {
8349     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "tst.w", 40,
8350     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8351   },
8352 /* tst.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
8353   {
8354     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "tst.w", 40,
8355     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8356   },
8357 /* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
8358   {
8359     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "tst.w", 48,
8360     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8361   },
8362 /* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
8363   {
8364     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "tst.w", 48,
8365     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8366   },
8367 /* tst.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
8368   {
8369     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "tst.w", 48,
8370     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8371   },
8372 /* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
8373   {
8374     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "tst.w", 32,
8375     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8376   },
8377 /* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
8378   {
8379     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "tst.w", 32,
8380     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8381   },
8382 /* tst.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
8383   {
8384     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "tst.w", 32,
8385     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8386   },
8387 /* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
8388   {
8389     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "tst.w", 40,
8390     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8391   },
8392 /* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
8393   {
8394     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "tst.w", 40,
8395     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8396   },
8397 /* tst.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
8398   {
8399     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "tst.w", 40,
8400     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8401   },
8402 /* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
8403   {
8404     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "tst.w", 32,
8405     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8406   },
8407 /* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
8408   {
8409     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "tst.w", 32,
8410     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8411   },
8412 /* tst.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
8413   {
8414     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "tst.w", 32,
8415     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8416   },
8417 /* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
8418   {
8419     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "tst.w", 40,
8420     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8421   },
8422 /* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
8423   {
8424     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "tst.w", 40,
8425     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8426   },
8427 /* tst.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
8428   {
8429     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "tst.w", 40,
8430     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8431   },
8432 /* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
8433   {
8434     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "tst.w", 40,
8435     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8436   },
8437 /* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
8438   {
8439     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "tst.w", 40,
8440     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8441   },
8442 /* tst.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
8443   {
8444     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "tst.w", 40,
8445     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8446   },
8447 /* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
8448   {
8449     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "tst.w", 48,
8450     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8451   },
8452 /* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
8453   {
8454     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "tst.w", 48,
8455     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8456   },
8457 /* tst.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
8458   {
8459     M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "tst.w", 48,
8460     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8461   },
8462 /* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
8463   {
8464     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 32,
8465     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8466   },
8467 /* tst.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
8468   {
8469     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 32,
8470     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8471   },
8472 /* tst.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
8473   {
8474     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 32,
8475     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8476   },
8477 /* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
8478   {
8479     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 32,
8480     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8481   },
8482 /* tst.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
8483   {
8484     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 32,
8485     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8486   },
8487 /* tst.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
8488   {
8489     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 32,
8490     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8491   },
8492 /* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
8493   {
8494     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 32,
8495     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8496   },
8497 /* tst.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
8498   {
8499     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 32,
8500     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8501   },
8502 /* tst.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
8503   {
8504     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 32,
8505     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8506   },
8507 /* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
8508   {
8509     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "tst.b", 40,
8510     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8511   },
8512 /* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
8513   {
8514     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "tst.b", 40,
8515     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8516   },
8517 /* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
8518   {
8519     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "tst.b", 40,
8520     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8521   },
8522 /* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
8523   {
8524     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "tst.b", 48,
8525     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8526   },
8527 /* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
8528   {
8529     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "tst.b", 48,
8530     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8531   },
8532 /* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
8533   {
8534     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "tst.b", 48,
8535     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8536   },
8537 /* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
8538   {
8539     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "tst.b", 56,
8540     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8541   },
8542 /* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
8543   {
8544     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "tst.b", 56,
8545     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8546   },
8547 /* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
8548   {
8549     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "tst.b", 56,
8550     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8551   },
8552 /* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
8553   {
8554     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "tst.b", 40,
8555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8556   },
8557 /* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
8558   {
8559     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "tst.b", 40,
8560     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8561   },
8562 /* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
8563   {
8564     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "tst.b", 40,
8565     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8566   },
8567 /* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
8568   {
8569     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "tst.b", 48,
8570     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8571   },
8572 /* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
8573   {
8574     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "tst.b", 48,
8575     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8576   },
8577 /* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
8578   {
8579     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "tst.b", 48,
8580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8581   },
8582 /* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
8583   {
8584     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "tst.b", 40,
8585     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8586   },
8587 /* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
8588   {
8589     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "tst.b", 40,
8590     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8591   },
8592 /* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
8593   {
8594     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "tst.b", 40,
8595     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8596   },
8597 /* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
8598   {
8599     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "tst.b", 48,
8600     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8601   },
8602 /* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
8603   {
8604     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "tst.b", 48,
8605     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8606   },
8607 /* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
8608   {
8609     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "tst.b", 48,
8610     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8611   },
8612 /* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
8613   {
8614     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "tst.b", 48,
8615     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8616   },
8617 /* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
8618   {
8619     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "tst.b", 48,
8620     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8621   },
8622 /* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
8623   {
8624     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "tst.b", 48,
8625     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8626   },
8627 /* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
8628   {
8629     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "tst.b", 56,
8630     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8631   },
8632 /* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
8633   {
8634     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "tst.b", 56,
8635     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8636   },
8637 /* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
8638   {
8639     M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "tst.b", 56,
8640     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8641   },
8642 /* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
8643   {
8644     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 40,
8645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8646   },
8647 /* tst.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
8648   {
8649     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 40,
8650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8651   },
8652 /* tst.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
8653   {
8654     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 40,
8655     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8656   },
8657 /* tst.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
8658   {
8659     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 40,
8660     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8661   },
8662 /* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
8663   {
8664     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 40,
8665     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8666   },
8667 /* tst.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
8668   {
8669     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 40,
8670     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8671   },
8672 /* tst.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
8673   {
8674     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 40,
8675     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8676   },
8677 /* tst.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
8678   {
8679     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 40,
8680     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8681   },
8682 /* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
8683   {
8684     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 40,
8685     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8686   },
8687 /* tst.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
8688   {
8689     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 40,
8690     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8691   },
8692 /* tst.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
8693   {
8694     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 40,
8695     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8696   },
8697 /* tst.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
8698   {
8699     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 40,
8700     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8701   },
8702 /* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
8703   {
8704     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "tst.b", 48,
8705     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8706   },
8707 /* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
8708   {
8709     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "tst.b", 48,
8710     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8711   },
8712 /* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
8713   {
8714     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "tst.b", 48,
8715     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8716   },
8717 /* tst.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
8718   {
8719     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "tst.b", 48,
8720     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8721   },
8722 /* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
8723   {
8724     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "tst.b", 56,
8725     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8726   },
8727 /* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
8728   {
8729     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "tst.b", 56,
8730     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8731   },
8732 /* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
8733   {
8734     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "tst.b", 56,
8735     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8736   },
8737 /* tst.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
8738   {
8739     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "tst.b", 56,
8740     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8741   },
8742 /* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
8743   {
8744     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "tst.b", 64,
8745     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8746   },
8747 /* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
8748   {
8749     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "tst.b", 64,
8750     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8751   },
8752 /* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
8753   {
8754     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "tst.b", 64,
8755     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8756   },
8757 /* tst.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
8758   {
8759     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "tst.b", 64,
8760     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8761   },
8762 /* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
8763   {
8764     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "tst.b", 48,
8765     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8766   },
8767 /* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
8768   {
8769     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "tst.b", 48,
8770     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8771   },
8772 /* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
8773   {
8774     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "tst.b", 48,
8775     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8776   },
8777 /* tst.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
8778   {
8779     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "tst.b", 48,
8780     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8781   },
8782 /* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
8783   {
8784     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "tst.b", 56,
8785     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8786   },
8787 /* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
8788   {
8789     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "tst.b", 56,
8790     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8791   },
8792 /* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
8793   {
8794     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "tst.b", 56,
8795     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8796   },
8797 /* tst.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
8798   {
8799     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "tst.b", 56,
8800     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8801   },
8802 /* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
8803   {
8804     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "tst.b", 48,
8805     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8806   },
8807 /* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
8808   {
8809     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "tst.b", 48,
8810     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8811   },
8812 /* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
8813   {
8814     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "tst.b", 48,
8815     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8816   },
8817 /* tst.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
8818   {
8819     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "tst.b", 48,
8820     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8821   },
8822 /* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
8823   {
8824     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "tst.b", 56,
8825     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8826   },
8827 /* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
8828   {
8829     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "tst.b", 56,
8830     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8831   },
8832 /* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
8833   {
8834     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "tst.b", 56,
8835     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8836   },
8837 /* tst.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
8838   {
8839     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "tst.b", 56,
8840     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8841   },
8842 /* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
8843   {
8844     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "tst.b", 56,
8845     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8846   },
8847 /* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
8848   {
8849     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "tst.b", 56,
8850     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8851   },
8852 /* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
8853   {
8854     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "tst.b", 56,
8855     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8856   },
8857 /* tst.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
8858   {
8859     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "tst.b", 56,
8860     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8861   },
8862 /* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
8863   {
8864     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "tst.b", 64,
8865     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8866   },
8867 /* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
8868   {
8869     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "tst.b", 64,
8870     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8871   },
8872 /* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
8873   {
8874     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "tst.b", 64,
8875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8876   },
8877 /* tst.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
8878   {
8879     M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "tst.b", 64,
8880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8881   },
8882 /* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
8883   {
8884     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 48,
8885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8886   },
8887 /* tst.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
8888   {
8889     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 48,
8890     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8891   },
8892 /* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
8893   {
8894     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 48,
8895     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8896   },
8897 /* tst.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
8898   {
8899     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 48,
8900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8901   },
8902 /* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
8903   {
8904     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 48,
8905     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8906   },
8907 /* tst.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
8908   {
8909     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 48,
8910     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8911   },
8912 /* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
8913   {
8914     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "tst.b", 56,
8915     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8916   },
8917 /* tst.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
8918   {
8919     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "tst.b", 56,
8920     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8921   },
8922 /* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
8923   {
8924     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "tst.b", 64,
8925     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8926   },
8927 /* tst.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
8928   {
8929     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "tst.b", 64,
8930     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8931   },
8932 /* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
8933   {
8934     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "tst.b", 72,
8935     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8936   },
8937 /* tst.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
8938   {
8939     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "tst.b", 72,
8940     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8941   },
8942 /* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
8943   {
8944     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "tst.b", 56,
8945     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8946   },
8947 /* tst.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
8948   {
8949     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "tst.b", 56,
8950     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8951   },
8952 /* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
8953   {
8954     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "tst.b", 64,
8955     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8956   },
8957 /* tst.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
8958   {
8959     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "tst.b", 64,
8960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8961   },
8962 /* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
8963   {
8964     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "tst.b", 56,
8965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8966   },
8967 /* tst.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
8968   {
8969     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "tst.b", 56,
8970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8971   },
8972 /* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
8973   {
8974     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "tst.b", 64,
8975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8976   },
8977 /* tst.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
8978   {
8979     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "tst.b", 64,
8980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8981   },
8982 /* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
8983   {
8984     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "tst.b", 64,
8985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8986   },
8987 /* tst.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
8988   {
8989     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "tst.b", 64,
8990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8991   },
8992 /* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
8993   {
8994     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "tst.b", 72,
8995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8996   },
8997 /* tst.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
8998   {
8999     M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "tst.b", 72,
9000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9001   },
9002 /* tst.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
9003   {
9004     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 24,
9005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9006   },
9007 /* tst.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
9008   {
9009     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 24,
9010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9011   },
9012 /* tst.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
9013   {
9014     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 24,
9015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9016   },
9017 /* tst.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
9018   {
9019     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 24,
9020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9021   },
9022 /* tst.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
9023   {
9024     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 24,
9025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9026   },
9027 /* tst.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
9028   {
9029     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 24,
9030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9031   },
9032 /* tst.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
9033   {
9034     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 24,
9035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9036   },
9037 /* tst.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
9038   {
9039     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 24,
9040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9041   },
9042 /* tst.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
9043   {
9044     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 24,
9045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9046   },
9047 /* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
9048   {
9049     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "tst.b", 32,
9050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9051   },
9052 /* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
9053   {
9054     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "tst.b", 32,
9055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9056   },
9057 /* tst.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
9058   {
9059     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "tst.b", 32,
9060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9061   },
9062 /* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
9063   {
9064     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "tst.b", 40,
9065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9066   },
9067 /* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
9068   {
9069     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "tst.b", 40,
9070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9071   },
9072 /* tst.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
9073   {
9074     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "tst.b", 40,
9075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9076   },
9077 /* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
9078   {
9079     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "tst.b", 48,
9080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9081   },
9082 /* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
9083   {
9084     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "tst.b", 48,
9085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9086   },
9087 /* tst.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
9088   {
9089     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "tst.b", 48,
9090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9091   },
9092 /* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
9093   {
9094     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "tst.b", 32,
9095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9096   },
9097 /* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
9098   {
9099     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "tst.b", 32,
9100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9101   },
9102 /* tst.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
9103   {
9104     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "tst.b", 32,
9105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9106   },
9107 /* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
9108   {
9109     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "tst.b", 40,
9110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9111   },
9112 /* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
9113   {
9114     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "tst.b", 40,
9115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9116   },
9117 /* tst.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
9118   {
9119     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "tst.b", 40,
9120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9121   },
9122 /* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
9123   {
9124     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "tst.b", 32,
9125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9126   },
9127 /* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
9128   {
9129     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "tst.b", 32,
9130     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9131   },
9132 /* tst.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
9133   {
9134     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "tst.b", 32,
9135     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9136   },
9137 /* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
9138   {
9139     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "tst.b", 40,
9140     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9141   },
9142 /* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
9143   {
9144     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "tst.b", 40,
9145     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9146   },
9147 /* tst.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
9148   {
9149     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "tst.b", 40,
9150     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9151   },
9152 /* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
9153   {
9154     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "tst.b", 40,
9155     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9156   },
9157 /* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
9158   {
9159     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "tst.b", 40,
9160     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9161   },
9162 /* tst.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
9163   {
9164     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "tst.b", 40,
9165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9166   },
9167 /* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
9168   {
9169     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "tst.b", 48,
9170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9171   },
9172 /* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
9173   {
9174     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "tst.b", 48,
9175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9176   },
9177 /* tst.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
9178   {
9179     M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "tst.b", 48,
9180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9181   },
9182 /* tst.w${X} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
9183   {
9184     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "tst.w", 24,
9185     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9186   },
9187 /* tst.w${X} ${Dsp-16-u8}[sb],$Dst16RnHI */
9188   {
9189     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "tst.w", 24,
9190     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9191   },
9192 /* tst.w${X} ${Dsp-16-s8}[fb],$Dst16RnHI */
9193   {
9194     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "tst.w", 24,
9195     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9196   },
9197 /* tst.w${X} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
9198   {
9199     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "tst.w", 24,
9200     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9201   },
9202 /* tst.w${X} ${Dsp-16-u8}[sb],$Dst16AnHI */
9203   {
9204     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "tst.w", 24,
9205     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9206   },
9207 /* tst.w${X} ${Dsp-16-s8}[fb],$Dst16AnHI */
9208   {
9209     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "tst.w", 24,
9210     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9211   },
9212 /* tst.w${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
9213   {
9214     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "tst.w", 24,
9215     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9216   },
9217 /* tst.w${X} ${Dsp-16-u8}[sb],[$Dst16An] */
9218   {
9219     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "tst.w", 24,
9220     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9221   },
9222 /* tst.w${X} ${Dsp-16-s8}[fb],[$Dst16An] */
9223   {
9224     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "tst.w", 24,
9225     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9226   },
9227 /* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
9228   {
9229     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "tst.w", 32,
9230     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9231   },
9232 /* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
9233   {
9234     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "tst.w", 32,
9235     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9236   },
9237 /* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
9238   {
9239     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "tst.w", 32,
9240     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9241   },
9242 /* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
9243   {
9244     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "tst.w", 40,
9245     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9246   },
9247 /* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
9248   {
9249     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "tst.w", 40,
9250     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9251   },
9252 /* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
9253   {
9254     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "tst.w", 40,
9255     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9256   },
9257 /* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
9258   {
9259     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "tst.w", 32,
9260     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9261   },
9262 /* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
9263   {
9264     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "tst.w", 32,
9265     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9266   },
9267 /* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
9268   {
9269     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "tst.w", 32,
9270     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9271   },
9272 /* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
9273   {
9274     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "tst.w", 40,
9275     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9276   },
9277 /* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
9278   {
9279     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "tst.w", 40,
9280     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9281   },
9282 /* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
9283   {
9284     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "tst.w", 40,
9285     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9286   },
9287 /* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
9288   {
9289     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "tst.w", 32,
9290     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9291   },
9292 /* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
9293   {
9294     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "tst.w", 32,
9295     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9296   },
9297 /* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
9298   {
9299     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "tst.w", 32,
9300     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9301   },
9302 /* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
9303   {
9304     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "tst.w", 40,
9305     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9306   },
9307 /* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
9308   {
9309     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "tst.w", 40,
9310     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9311   },
9312 /* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
9313   {
9314     M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "tst.w", 40,
9315     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9316   },
9317 /* tst.w${X} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
9318   {
9319     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "tst.w", 32,
9320     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9321   },
9322 /* tst.w${X} ${Dsp-16-u16}[sb],$Dst16RnHI */
9323   {
9324     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "tst.w", 32,
9325     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9326   },
9327 /* tst.w${X} ${Dsp-16-u16},$Dst16RnHI */
9328   {
9329     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "tst.w", 32,
9330     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9331   },
9332 /* tst.w${X} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
9333   {
9334     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "tst.w", 32,
9335     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9336   },
9337 /* tst.w${X} ${Dsp-16-u16}[sb],$Dst16AnHI */
9338   {
9339     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "tst.w", 32,
9340     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9341   },
9342 /* tst.w${X} ${Dsp-16-u16},$Dst16AnHI */
9343   {
9344     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "tst.w", 32,
9345     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9346   },
9347 /* tst.w${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
9348   {
9349     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "tst.w", 32,
9350     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9351   },
9352 /* tst.w${X} ${Dsp-16-u16}[sb],[$Dst16An] */
9353   {
9354     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "tst.w", 32,
9355     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9356   },
9357 /* tst.w${X} ${Dsp-16-u16},[$Dst16An] */
9358   {
9359     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "tst.w", 32,
9360     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9361   },
9362 /* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
9363   {
9364     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "tst.w", 40,
9365     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9366   },
9367 /* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
9368   {
9369     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "tst.w", 40,
9370     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9371   },
9372 /* tst.w${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
9373   {
9374     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "tst.w", 40,
9375     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9376   },
9377 /* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
9378   {
9379     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "tst.w", 48,
9380     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9381   },
9382 /* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
9383   {
9384     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "tst.w", 48,
9385     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9386   },
9387 /* tst.w${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
9388   {
9389     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "tst.w", 48,
9390     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9391   },
9392 /* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
9393   {
9394     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "tst.w", 40,
9395     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9396   },
9397 /* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
9398   {
9399     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "tst.w", 40,
9400     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9401   },
9402 /* tst.w${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
9403   {
9404     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "tst.w", 40,
9405     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9406   },
9407 /* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
9408   {
9409     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "tst.w", 48,
9410     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9411   },
9412 /* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
9413   {
9414     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "tst.w", 48,
9415     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9416   },
9417 /* tst.w${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
9418   {
9419     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "tst.w", 48,
9420     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9421   },
9422 /* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
9423   {
9424     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "tst.w", 40,
9425     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9426   },
9427 /* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
9428   {
9429     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "tst.w", 40,
9430     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9431   },
9432 /* tst.w${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
9433   {
9434     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "tst.w", 40,
9435     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9436   },
9437 /* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
9438   {
9439     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "tst.w", 48,
9440     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9441   },
9442 /* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
9443   {
9444     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "tst.w", 48,
9445     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9446   },
9447 /* tst.w${X} ${Dsp-16-u16},${Dsp-32-u16} */
9448   {
9449     M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "tst.w", 48,
9450     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9451   },
9452 /* tst.w${X} $Src16RnHI,$Dst16RnHI */
9453   {
9454     M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "tst.w", 16,
9455     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9456   },
9457 /* tst.w${X} $Src16AnHI,$Dst16RnHI */
9458   {
9459     M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "tst.w", 16,
9460     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9461   },
9462 /* tst.w${X} [$Src16An],$Dst16RnHI */
9463   {
9464     M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "tst.w", 16,
9465     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9466   },
9467 /* tst.w${X} $Src16RnHI,$Dst16AnHI */
9468   {
9469     M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "tst.w", 16,
9470     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9471   },
9472 /* tst.w${X} $Src16AnHI,$Dst16AnHI */
9473   {
9474     M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "tst.w", 16,
9475     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9476   },
9477 /* tst.w${X} [$Src16An],$Dst16AnHI */
9478   {
9479     M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "tst.w", 16,
9480     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9481   },
9482 /* tst.w${X} $Src16RnHI,[$Dst16An] */
9483   {
9484     M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "tst.w", 16,
9485     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9486   },
9487 /* tst.w${X} $Src16AnHI,[$Dst16An] */
9488   {
9489     M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "tst.w", 16,
9490     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9491   },
9492 /* tst.w${X} [$Src16An],[$Dst16An] */
9493   {
9494     M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "tst.w", 16,
9495     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9496   },
9497 /* tst.w${X} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
9498   {
9499     M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "tst.w", 24,
9500     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9501   },
9502 /* tst.w${X} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
9503   {
9504     M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "tst.w", 24,
9505     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9506   },
9507 /* tst.w${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
9508   {
9509     M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "tst.w", 24,
9510     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9511   },
9512 /* tst.w${X} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
9513   {
9514     M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "tst.w", 32,
9515     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9516   },
9517 /* tst.w${X} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
9518   {
9519     M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "tst.w", 32,
9520     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9521   },
9522 /* tst.w${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
9523   {
9524     M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "tst.w", 32,
9525     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9526   },
9527 /* tst.w${X} $Src16RnHI,${Dsp-16-u8}[sb] */
9528   {
9529     M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "tst.w", 24,
9530     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9531   },
9532 /* tst.w${X} $Src16AnHI,${Dsp-16-u8}[sb] */
9533   {
9534     M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "tst.w", 24,
9535     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9536   },
9537 /* tst.w${X} [$Src16An],${Dsp-16-u8}[sb] */
9538   {
9539     M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "tst.w", 24,
9540     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9541   },
9542 /* tst.w${X} $Src16RnHI,${Dsp-16-u16}[sb] */
9543   {
9544     M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "tst.w", 32,
9545     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9546   },
9547 /* tst.w${X} $Src16AnHI,${Dsp-16-u16}[sb] */
9548   {
9549     M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "tst.w", 32,
9550     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9551   },
9552 /* tst.w${X} [$Src16An],${Dsp-16-u16}[sb] */
9553   {
9554     M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "tst.w", 32,
9555     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9556   },
9557 /* tst.w${X} $Src16RnHI,${Dsp-16-s8}[fb] */
9558   {
9559     M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "tst.w", 24,
9560     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9561   },
9562 /* tst.w${X} $Src16AnHI,${Dsp-16-s8}[fb] */
9563   {
9564     M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "tst.w", 24,
9565     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9566   },
9567 /* tst.w${X} [$Src16An],${Dsp-16-s8}[fb] */
9568   {
9569     M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "tst.w", 24,
9570     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9571   },
9572 /* tst.w${X} $Src16RnHI,${Dsp-16-u16} */
9573   {
9574     M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "tst.w", 32,
9575     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9576   },
9577 /* tst.w${X} $Src16AnHI,${Dsp-16-u16} */
9578   {
9579     M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "tst.w", 32,
9580     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9581   },
9582 /* tst.w${X} [$Src16An],${Dsp-16-u16} */
9583   {
9584     M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "tst.w", 32,
9585     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9586   },
9587 /* tst.b${X} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
9588   {
9589     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "tst.b", 24,
9590     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9591   },
9592 /* tst.b${X} ${Dsp-16-u8}[sb],$Dst16RnQI */
9593   {
9594     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "tst.b", 24,
9595     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9596   },
9597 /* tst.b${X} ${Dsp-16-s8}[fb],$Dst16RnQI */
9598   {
9599     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "tst.b", 24,
9600     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9601   },
9602 /* tst.b${X} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
9603   {
9604     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "tst.b", 24,
9605     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9606   },
9607 /* tst.b${X} ${Dsp-16-u8}[sb],$Dst16AnQI */
9608   {
9609     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "tst.b", 24,
9610     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9611   },
9612 /* tst.b${X} ${Dsp-16-s8}[fb],$Dst16AnQI */
9613   {
9614     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "tst.b", 24,
9615     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9616   },
9617 /* tst.b${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
9618   {
9619     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "tst.b", 24,
9620     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9621   },
9622 /* tst.b${X} ${Dsp-16-u8}[sb],[$Dst16An] */
9623   {
9624     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "tst.b", 24,
9625     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9626   },
9627 /* tst.b${X} ${Dsp-16-s8}[fb],[$Dst16An] */
9628   {
9629     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "tst.b", 24,
9630     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9631   },
9632 /* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
9633   {
9634     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "tst.b", 32,
9635     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9636   },
9637 /* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
9638   {
9639     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "tst.b", 32,
9640     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9641   },
9642 /* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
9643   {
9644     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "tst.b", 32,
9645     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9646   },
9647 /* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
9648   {
9649     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "tst.b", 40,
9650     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9651   },
9652 /* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
9653   {
9654     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "tst.b", 40,
9655     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9656   },
9657 /* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
9658   {
9659     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "tst.b", 40,
9660     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9661   },
9662 /* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
9663   {
9664     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "tst.b", 32,
9665     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9666   },
9667 /* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
9668   {
9669     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "tst.b", 32,
9670     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9671   },
9672 /* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
9673   {
9674     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "tst.b", 32,
9675     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9676   },
9677 /* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
9678   {
9679     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "tst.b", 40,
9680     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9681   },
9682 /* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
9683   {
9684     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "tst.b", 40,
9685     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9686   },
9687 /* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
9688   {
9689     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "tst.b", 40,
9690     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9691   },
9692 /* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
9693   {
9694     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "tst.b", 32,
9695     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9696   },
9697 /* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
9698   {
9699     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "tst.b", 32,
9700     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9701   },
9702 /* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
9703   {
9704     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "tst.b", 32,
9705     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9706   },
9707 /* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
9708   {
9709     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "tst.b", 40,
9710     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9711   },
9712 /* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
9713   {
9714     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "tst.b", 40,
9715     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9716   },
9717 /* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
9718   {
9719     M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "tst.b", 40,
9720     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9721   },
9722 /* tst.b${X} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
9723   {
9724     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "tst.b", 32,
9725     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9726   },
9727 /* tst.b${X} ${Dsp-16-u16}[sb],$Dst16RnQI */
9728   {
9729     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "tst.b", 32,
9730     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9731   },
9732 /* tst.b${X} ${Dsp-16-u16},$Dst16RnQI */
9733   {
9734     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "tst.b", 32,
9735     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9736   },
9737 /* tst.b${X} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
9738   {
9739     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "tst.b", 32,
9740     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9741   },
9742 /* tst.b${X} ${Dsp-16-u16}[sb],$Dst16AnQI */
9743   {
9744     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "tst.b", 32,
9745     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9746   },
9747 /* tst.b${X} ${Dsp-16-u16},$Dst16AnQI */
9748   {
9749     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "tst.b", 32,
9750     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9751   },
9752 /* tst.b${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
9753   {
9754     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "tst.b", 32,
9755     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9756   },
9757 /* tst.b${X} ${Dsp-16-u16}[sb],[$Dst16An] */
9758   {
9759     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "tst.b", 32,
9760     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9761   },
9762 /* tst.b${X} ${Dsp-16-u16},[$Dst16An] */
9763   {
9764     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "tst.b", 32,
9765     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9766   },
9767 /* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
9768   {
9769     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "tst.b", 40,
9770     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9771   },
9772 /* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
9773   {
9774     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "tst.b", 40,
9775     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9776   },
9777 /* tst.b${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
9778   {
9779     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "tst.b", 40,
9780     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9781   },
9782 /* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
9783   {
9784     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "tst.b", 48,
9785     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9786   },
9787 /* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
9788   {
9789     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "tst.b", 48,
9790     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9791   },
9792 /* tst.b${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
9793   {
9794     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "tst.b", 48,
9795     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9796   },
9797 /* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
9798   {
9799     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "tst.b", 40,
9800     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9801   },
9802 /* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
9803   {
9804     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "tst.b", 40,
9805     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9806   },
9807 /* tst.b${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
9808   {
9809     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "tst.b", 40,
9810     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9811   },
9812 /* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
9813   {
9814     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "tst.b", 48,
9815     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9816   },
9817 /* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
9818   {
9819     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "tst.b", 48,
9820     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9821   },
9822 /* tst.b${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
9823   {
9824     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "tst.b", 48,
9825     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9826   },
9827 /* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
9828   {
9829     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "tst.b", 40,
9830     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9831   },
9832 /* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
9833   {
9834     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "tst.b", 40,
9835     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9836   },
9837 /* tst.b${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
9838   {
9839     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "tst.b", 40,
9840     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9841   },
9842 /* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
9843   {
9844     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "tst.b", 48,
9845     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9846   },
9847 /* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
9848   {
9849     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "tst.b", 48,
9850     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9851   },
9852 /* tst.b${X} ${Dsp-16-u16},${Dsp-32-u16} */
9853   {
9854     M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "tst.b", 48,
9855     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9856   },
9857 /* tst.b${X} $Src16RnQI,$Dst16RnQI */
9858   {
9859     M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "tst.b", 16,
9860     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9861   },
9862 /* tst.b${X} $Src16AnQI,$Dst16RnQI */
9863   {
9864     M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "tst.b", 16,
9865     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9866   },
9867 /* tst.b${X} [$Src16An],$Dst16RnQI */
9868   {
9869     M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "tst.b", 16,
9870     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9871   },
9872 /* tst.b${X} $Src16RnQI,$Dst16AnQI */
9873   {
9874     M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "tst.b", 16,
9875     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9876   },
9877 /* tst.b${X} $Src16AnQI,$Dst16AnQI */
9878   {
9879     M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "tst.b", 16,
9880     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9881   },
9882 /* tst.b${X} [$Src16An],$Dst16AnQI */
9883   {
9884     M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "tst.b", 16,
9885     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9886   },
9887 /* tst.b${X} $Src16RnQI,[$Dst16An] */
9888   {
9889     M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "tst.b", 16,
9890     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9891   },
9892 /* tst.b${X} $Src16AnQI,[$Dst16An] */
9893   {
9894     M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "tst.b", 16,
9895     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9896   },
9897 /* tst.b${X} [$Src16An],[$Dst16An] */
9898   {
9899     M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "tst.b", 16,
9900     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9901   },
9902 /* tst.b${X} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
9903   {
9904     M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "tst.b", 24,
9905     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9906   },
9907 /* tst.b${X} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
9908   {
9909     M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "tst.b", 24,
9910     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9911   },
9912 /* tst.b${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
9913   {
9914     M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "tst.b", 24,
9915     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9916   },
9917 /* tst.b${X} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
9918   {
9919     M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "tst.b", 32,
9920     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9921   },
9922 /* tst.b${X} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
9923   {
9924     M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "tst.b", 32,
9925     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9926   },
9927 /* tst.b${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
9928   {
9929     M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "tst.b", 32,
9930     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9931   },
9932 /* tst.b${X} $Src16RnQI,${Dsp-16-u8}[sb] */
9933   {
9934     M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "tst.b", 24,
9935     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9936   },
9937 /* tst.b${X} $Src16AnQI,${Dsp-16-u8}[sb] */
9938   {
9939     M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "tst.b", 24,
9940     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9941   },
9942 /* tst.b${X} [$Src16An],${Dsp-16-u8}[sb] */
9943   {
9944     M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "tst.b", 24,
9945     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9946   },
9947 /* tst.b${X} $Src16RnQI,${Dsp-16-u16}[sb] */
9948   {
9949     M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "tst.b", 32,
9950     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9951   },
9952 /* tst.b${X} $Src16AnQI,${Dsp-16-u16}[sb] */
9953   {
9954     M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "tst.b", 32,
9955     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9956   },
9957 /* tst.b${X} [$Src16An],${Dsp-16-u16}[sb] */
9958   {
9959     M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "tst.b", 32,
9960     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9961   },
9962 /* tst.b${X} $Src16RnQI,${Dsp-16-s8}[fb] */
9963   {
9964     M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "tst.b", 24,
9965     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9966   },
9967 /* tst.b${X} $Src16AnQI,${Dsp-16-s8}[fb] */
9968   {
9969     M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "tst.b", 24,
9970     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9971   },
9972 /* tst.b${X} [$Src16An],${Dsp-16-s8}[fb] */
9973   {
9974     M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "tst.b", 24,
9975     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9976   },
9977 /* tst.b${X} $Src16RnQI,${Dsp-16-u16} */
9978   {
9979     M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "tst.b", 32,
9980     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9981   },
9982 /* tst.b${X} $Src16AnQI,${Dsp-16-u16} */
9983   {
9984     M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "tst.b", 32,
9985     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9986   },
9987 /* tst.b${X} [$Src16An],${Dsp-16-u16} */
9988   {
9989     M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "tst.b", 32,
9990     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9991   },
9992 /* tst.w${X} #${Imm-16-HI},$Dst32RnUnprefixedHI */
9993   {
9994     M32C_INSN_TST32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "tst32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "tst.w", 32,
9995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9996   },
9997 /* tst.w${X} #${Imm-16-HI},$Dst32AnUnprefixedHI */
9998   {
9999     M32C_INSN_TST32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "tst32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "tst.w", 32,
10000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10001   },
10002 /* tst.w${X} #${Imm-16-HI},[$Dst32AnUnprefixed] */
10003   {
10004     M32C_INSN_TST32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "tst32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "tst.w", 32,
10005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10006   },
10007 /* tst.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
10008   {
10009     M32C_INSN_TST32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "tst.w", 40,
10010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10011   },
10012 /* tst.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
10013   {
10014     M32C_INSN_TST32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "tst.w", 40,
10015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10016   },
10017 /* tst.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
10018   {
10019     M32C_INSN_TST32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "tst.w", 40,
10020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10021   },
10022 /* tst.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
10023   {
10024     M32C_INSN_TST32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "tst.w", 48,
10025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10026   },
10027 /* tst.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
10028   {
10029     M32C_INSN_TST32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "tst.w", 48,
10030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10031   },
10032 /* tst.w${X} #${Imm-32-HI},${Dsp-16-s16}[fb] */
10033   {
10034     M32C_INSN_TST32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "tst.w", 48,
10035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10036   },
10037 /* tst.w${X} #${Imm-32-HI},${Dsp-16-u16} */
10038   {
10039     M32C_INSN_TST32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "tst32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "tst.w", 48,
10040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10041   },
10042 /* tst.w${X} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
10043   {
10044     M32C_INSN_TST32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "tst.w", 56,
10045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10046   },
10047 /* tst.w${X} #${Imm-40-HI},${Dsp-16-u24} */
10048   {
10049     M32C_INSN_TST32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "tst32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "tst.w", 56,
10050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10051   },
10052 /* tst.b${X} #${Imm-16-QI},$Dst32RnUnprefixedQI */
10053   {
10054     M32C_INSN_TST32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "tst32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "tst.b", 24,
10055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10056   },
10057 /* tst.b${X} #${Imm-16-QI},$Dst32AnUnprefixedQI */
10058   {
10059     M32C_INSN_TST32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "tst32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "tst.b", 24,
10060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10061   },
10062 /* tst.b${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
10063   {
10064     M32C_INSN_TST32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "tst32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "tst.b", 24,
10065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10066   },
10067 /* tst.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
10068   {
10069     M32C_INSN_TST32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "tst.b", 32,
10070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10071   },
10072 /* tst.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
10073   {
10074     M32C_INSN_TST32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "tst.b", 32,
10075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10076   },
10077 /* tst.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
10078   {
10079     M32C_INSN_TST32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "tst.b", 32,
10080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10081   },
10082 /* tst.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
10083   {
10084     M32C_INSN_TST32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "tst.b", 40,
10085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10086   },
10087 /* tst.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
10088   {
10089     M32C_INSN_TST32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "tst.b", 40,
10090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10091   },
10092 /* tst.b${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
10093   {
10094     M32C_INSN_TST32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "tst.b", 40,
10095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10096   },
10097 /* tst.b${X} #${Imm-32-QI},${Dsp-16-u16} */
10098   {
10099     M32C_INSN_TST32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "tst32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "tst.b", 40,
10100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10101   },
10102 /* tst.b${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
10103   {
10104     M32C_INSN_TST32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "tst.b", 48,
10105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10106   },
10107 /* tst.b${X} #${Imm-40-QI},${Dsp-16-u24} */
10108   {
10109     M32C_INSN_TST32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "tst32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "tst.b", 48,
10110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10111   },
10112 /* tst.w${X} #${Imm-16-HI},$Dst16RnHI */
10113   {
10114     M32C_INSN_TST16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "tst16.w-imm-G-basic-dst16-Rn-direct-HI", "tst.w", 32,
10115     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10116   },
10117 /* tst.w${X} #${Imm-16-HI},$Dst16AnHI */
10118   {
10119     M32C_INSN_TST16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "tst16.w-imm-G-basic-dst16-An-direct-HI", "tst.w", 32,
10120     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10121   },
10122 /* tst.w${X} #${Imm-16-HI},[$Dst16An] */
10123   {
10124     M32C_INSN_TST16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "tst16.w-imm-G-basic-dst16-An-indirect-HI", "tst.w", 32,
10125     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10126   },
10127 /* tst.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
10128   {
10129     M32C_INSN_TST16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "tst16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "tst.w", 40,
10130     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10131   },
10132 /* tst.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
10133   {
10134     M32C_INSN_TST16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "tst16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "tst.w", 40,
10135     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10136   },
10137 /* tst.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
10138   {
10139     M32C_INSN_TST16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "tst16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "tst.w", 40,
10140     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10141   },
10142 /* tst.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
10143   {
10144     M32C_INSN_TST16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "tst16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "tst.w", 48,
10145     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10146   },
10147 /* tst.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
10148   {
10149     M32C_INSN_TST16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "tst16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "tst.w", 48,
10150     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10151   },
10152 /* tst.w${X} #${Imm-32-HI},${Dsp-16-u16} */
10153   {
10154     M32C_INSN_TST16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "tst16.w-imm-G-16-16-dst16-16-16-absolute-HI", "tst.w", 48,
10155     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10156   },
10157 /* tst.b${X} #${Imm-16-QI},$Dst16RnQI */
10158   {
10159     M32C_INSN_TST16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "tst16.b-imm-G-basic-dst16-Rn-direct-QI", "tst.b", 24,
10160     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10161   },
10162 /* tst.b${X} #${Imm-16-QI},$Dst16AnQI */
10163   {
10164     M32C_INSN_TST16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "tst16.b-imm-G-basic-dst16-An-direct-QI", "tst.b", 24,
10165     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10166   },
10167 /* tst.b${X} #${Imm-16-QI},[$Dst16An] */
10168   {
10169     M32C_INSN_TST16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "tst16.b-imm-G-basic-dst16-An-indirect-QI", "tst.b", 24,
10170     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10171   },
10172 /* tst.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
10173   {
10174     M32C_INSN_TST16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "tst16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "tst.b", 32,
10175     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10176   },
10177 /* tst.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
10178   {
10179     M32C_INSN_TST16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "tst16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "tst.b", 32,
10180     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10181   },
10182 /* tst.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
10183   {
10184     M32C_INSN_TST16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "tst16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "tst.b", 32,
10185     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10186   },
10187 /* tst.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
10188   {
10189     M32C_INSN_TST16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "tst16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "tst.b", 40,
10190     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10191   },
10192 /* tst.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
10193   {
10194     M32C_INSN_TST16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "tst16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "tst.b", 40,
10195     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10196   },
10197 /* tst.b${X} #${Imm-32-QI},${Dsp-16-u16} */
10198   {
10199     M32C_INSN_TST16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "tst16.b-imm-G-16-16-dst16-16-16-absolute-QI", "tst.b", 40,
10200     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10201   },
10202 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
10203   {
10204     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 24,
10205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10206   },
10207 /* subx${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
10208   {
10209     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 24,
10210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10211   },
10212 /* subx${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
10213   {
10214     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 24,
10215     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10216   },
10217 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
10218   {
10219     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 24,
10220     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10221   },
10222 /* subx${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
10223   {
10224     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 24,
10225     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10226   },
10227 /* subx${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
10228   {
10229     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 24,
10230     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10231   },
10232 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
10233   {
10234     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 24,
10235     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10236   },
10237 /* subx${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
10238   {
10239     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 24,
10240     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10241   },
10242 /* subx${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
10243   {
10244     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 24,
10245     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10246   },
10247 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
10248   {
10249     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "subx", 32,
10250     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10251   },
10252 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
10253   {
10254     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "subx", 32,
10255     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10256   },
10257 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
10258   {
10259     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "subx", 32,
10260     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10261   },
10262 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
10263   {
10264     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "subx", 40,
10265     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10266   },
10267 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
10268   {
10269     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "subx", 40,
10270     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10271   },
10272 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
10273   {
10274     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "subx", 40,
10275     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10276   },
10277 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
10278   {
10279     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "subx", 48,
10280     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10281   },
10282 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
10283   {
10284     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "subx", 48,
10285     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10286   },
10287 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
10288   {
10289     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "subx", 48,
10290     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10291   },
10292 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
10293   {
10294     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "subx", 32,
10295     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10296   },
10297 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
10298   {
10299     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "subx", 32,
10300     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10301   },
10302 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
10303   {
10304     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "subx", 32,
10305     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10306   },
10307 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
10308   {
10309     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "subx", 40,
10310     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10311   },
10312 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
10313   {
10314     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "subx", 40,
10315     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10316   },
10317 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
10318   {
10319     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "subx", 40,
10320     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10321   },
10322 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
10323   {
10324     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "subx", 32,
10325     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10326   },
10327 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
10328   {
10329     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "subx", 32,
10330     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10331   },
10332 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
10333   {
10334     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "subx", 32,
10335     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10336   },
10337 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
10338   {
10339     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "subx", 40,
10340     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10341   },
10342 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
10343   {
10344     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "subx", 40,
10345     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10346   },
10347 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
10348   {
10349     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "subx", 40,
10350     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10351   },
10352 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
10353   {
10354     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "subx", 40,
10355     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10356   },
10357 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
10358   {
10359     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "subx", 40,
10360     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10361   },
10362 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
10363   {
10364     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "subx", 40,
10365     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10366   },
10367 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
10368   {
10369     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "subx", 48,
10370     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10371   },
10372 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
10373   {
10374     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "subx", 48,
10375     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10376   },
10377 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
10378   {
10379     M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "subx", 48,
10380     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10381   },
10382 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
10383   {
10384     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 32,
10385     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10386   },
10387 /* subx${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
10388   {
10389     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 32,
10390     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10391   },
10392 /* subx${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
10393   {
10394     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 32,
10395     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10396   },
10397 /* subx${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
10398   {
10399     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 32,
10400     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10401   },
10402 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
10403   {
10404     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 32,
10405     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10406   },
10407 /* subx${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
10408   {
10409     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 32,
10410     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10411   },
10412 /* subx${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
10413   {
10414     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 32,
10415     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10416   },
10417 /* subx${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
10418   {
10419     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 32,
10420     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10421   },
10422 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
10423   {
10424     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 32,
10425     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10426   },
10427 /* subx${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
10428   {
10429     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 32,
10430     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10431   },
10432 /* subx${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
10433   {
10434     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 32,
10435     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10436   },
10437 /* subx${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
10438   {
10439     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 32,
10440     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10441   },
10442 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
10443   {
10444     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "subx", 40,
10445     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10446   },
10447 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
10448   {
10449     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "subx", 40,
10450     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10451   },
10452 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
10453   {
10454     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "subx", 40,
10455     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10456   },
10457 /* subx${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
10458   {
10459     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "subx", 40,
10460     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10461   },
10462 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
10463   {
10464     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "subx", 48,
10465     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10466   },
10467 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
10468   {
10469     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "subx", 48,
10470     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10471   },
10472 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
10473   {
10474     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "subx", 48,
10475     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10476   },
10477 /* subx${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
10478   {
10479     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "subx", 48,
10480     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10481   },
10482 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
10483   {
10484     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "subx", 56,
10485     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10486   },
10487 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
10488   {
10489     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "subx", 56,
10490     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10491   },
10492 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
10493   {
10494     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "subx", 56,
10495     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10496   },
10497 /* subx${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
10498   {
10499     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "subx", 56,
10500     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10501   },
10502 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
10503   {
10504     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "subx", 40,
10505     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10506   },
10507 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
10508   {
10509     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "subx", 40,
10510     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10511   },
10512 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
10513   {
10514     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "subx", 40,
10515     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10516   },
10517 /* subx${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
10518   {
10519     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "subx", 40,
10520     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10521   },
10522 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
10523   {
10524     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "subx", 48,
10525     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10526   },
10527 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
10528   {
10529     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "subx", 48,
10530     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10531   },
10532 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
10533   {
10534     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "subx", 48,
10535     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10536   },
10537 /* subx${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
10538   {
10539     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "subx", 48,
10540     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10541   },
10542 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
10543   {
10544     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "subx", 40,
10545     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10546   },
10547 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
10548   {
10549     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "subx", 40,
10550     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10551   },
10552 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
10553   {
10554     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "subx", 40,
10555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10556   },
10557 /* subx${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
10558   {
10559     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "subx", 40,
10560     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10561   },
10562 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
10563   {
10564     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "subx", 48,
10565     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10566   },
10567 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
10568   {
10569     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "subx", 48,
10570     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10571   },
10572 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
10573   {
10574     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "subx", 48,
10575     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10576   },
10577 /* subx${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
10578   {
10579     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "subx", 48,
10580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10581   },
10582 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
10583   {
10584     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "subx", 48,
10585     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10586   },
10587 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
10588   {
10589     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "subx", 48,
10590     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10591   },
10592 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
10593   {
10594     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "subx", 48,
10595     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10596   },
10597 /* subx${G} ${Dsp-16-u16},${Dsp-32-u16} */
10598   {
10599     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "subx", 48,
10600     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10601   },
10602 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
10603   {
10604     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "subx", 56,
10605     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10606   },
10607 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
10608   {
10609     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "subx", 56,
10610     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10611   },
10612 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
10613   {
10614     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "subx", 56,
10615     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10616   },
10617 /* subx${G} ${Dsp-16-u16},${Dsp-32-u24} */
10618   {
10619     M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "subx", 56,
10620     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10621   },
10622 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
10623   {
10624     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 40,
10625     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10626   },
10627 /* subx${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
10628   {
10629     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 40,
10630     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10631   },
10632 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
10633   {
10634     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 40,
10635     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10636   },
10637 /* subx${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
10638   {
10639     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 40,
10640     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10641   },
10642 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
10643   {
10644     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 40,
10645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10646   },
10647 /* subx${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
10648   {
10649     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 40,
10650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10651   },
10652 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
10653   {
10654     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-SI", "subx", 48,
10655     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10656   },
10657 /* subx${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
10658   {
10659     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-SI", "subx", 48,
10660     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10661   },
10662 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
10663   {
10664     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-SI", "subx", 56,
10665     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10666   },
10667 /* subx${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
10668   {
10669     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-SI", "subx", 56,
10670     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10671   },
10672 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
10673   {
10674     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-SI", "subx", 64,
10675     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10676   },
10677 /* subx${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
10678   {
10679     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-SI", "subx", 64,
10680     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10681   },
10682 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
10683   {
10684     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-SI", "subx", 48,
10685     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10686   },
10687 /* subx${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
10688   {
10689     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-SI", "subx", 48,
10690     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10691   },
10692 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
10693   {
10694     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-SI", "subx", 56,
10695     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10696   },
10697 /* subx${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
10698   {
10699     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-SI", "subx", 56,
10700     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10701   },
10702 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
10703   {
10704     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-SI", "subx", 48,
10705     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10706   },
10707 /* subx${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
10708   {
10709     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-SI", "subx", 48,
10710     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10711   },
10712 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
10713   {
10714     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-SI", "subx", 56,
10715     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10716   },
10717 /* subx${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
10718   {
10719     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-SI", "subx", 56,
10720     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10721   },
10722 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
10723   {
10724     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-SI", "subx", 56,
10725     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10726   },
10727 /* subx${G} ${Dsp-16-u24},${Dsp-40-u16} */
10728   {
10729     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-SI", "subx", 56,
10730     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10731   },
10732 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
10733   {
10734     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-SI", "subx", 64,
10735     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10736   },
10737 /* subx${G} ${Dsp-16-u24},${Dsp-40-u24} */
10738   {
10739     M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-SI", "subx", 64,
10740     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10741   },
10742 /* subx${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedSI */
10743   {
10744     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 16,
10745     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10746   },
10747 /* subx${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedSI */
10748   {
10749     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 16,
10750     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10751   },
10752 /* subx${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
10753   {
10754     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 16,
10755     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10756   },
10757 /* subx${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedSI */
10758   {
10759     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 16,
10760     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10761   },
10762 /* subx${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedSI */
10763   {
10764     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 16,
10765     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10766   },
10767 /* subx${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
10768   {
10769     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 16,
10770     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10771   },
10772 /* subx${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
10773   {
10774     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 16,
10775     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10776   },
10777 /* subx${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
10778   {
10779     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 16,
10780     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10781   },
10782 /* subx${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
10783   {
10784     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 16,
10785     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10786   },
10787 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
10788   {
10789     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "subx", 24,
10790     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10791   },
10792 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
10793   {
10794     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "subx", 24,
10795     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10796   },
10797 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
10798   {
10799     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "subx", 24,
10800     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10801   },
10802 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
10803   {
10804     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "subx", 32,
10805     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10806   },
10807 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
10808   {
10809     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "subx", 32,
10810     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10811   },
10812 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
10813   {
10814     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "subx", 32,
10815     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10816   },
10817 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
10818   {
10819     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "subx", 40,
10820     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10821   },
10822 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
10823   {
10824     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "subx", 40,
10825     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10826   },
10827 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
10828   {
10829     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "subx", 40,
10830     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10831   },
10832 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
10833   {
10834     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "subx", 24,
10835     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10836   },
10837 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
10838   {
10839     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "subx", 24,
10840     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10841   },
10842 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
10843   {
10844     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "subx", 24,
10845     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10846   },
10847 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
10848   {
10849     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "subx", 32,
10850     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10851   },
10852 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
10853   {
10854     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "subx", 32,
10855     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10856   },
10857 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
10858   {
10859     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "subx", 32,
10860     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10861   },
10862 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
10863   {
10864     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "subx", 24,
10865     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10866   },
10867 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
10868   {
10869     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "subx", 24,
10870     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10871   },
10872 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
10873   {
10874     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "subx", 24,
10875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10876   },
10877 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
10878   {
10879     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "subx", 32,
10880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10881   },
10882 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
10883   {
10884     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "subx", 32,
10885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10886   },
10887 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
10888   {
10889     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "subx", 32,
10890     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10891   },
10892 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
10893   {
10894     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "subx", 32,
10895     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10896   },
10897 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
10898   {
10899     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "subx", 32,
10900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10901   },
10902 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
10903   {
10904     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "subx", 32,
10905     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10906   },
10907 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
10908   {
10909     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "subx", 40,
10910     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10911   },
10912 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
10913   {
10914     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "subx", 40,
10915     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10916   },
10917 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
10918   {
10919     M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "subx", 40,
10920     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10921   },
10922 /* subx${G} #${Imm-16-QI},$Dst32RnUnprefixedSI */
10923   {
10924     M32C_INSN_SUBX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "subx", 24,
10925     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10926   },
10927 /* subx${G} #${Imm-16-QI},$Dst32AnUnprefixedSI */
10928   {
10929     M32C_INSN_SUBX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "subx", 24,
10930     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10931   },
10932 /* subx${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
10933   {
10934     M32C_INSN_SUBX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "subx", 24,
10935     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10936   },
10937 /* subx${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
10938   {
10939     M32C_INSN_SUBX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "subx", 32,
10940     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10941   },
10942 /* subx${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
10943   {
10944     M32C_INSN_SUBX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "subx", 32,
10945     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10946   },
10947 /* subx${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
10948   {
10949     M32C_INSN_SUBX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "subx", 32,
10950     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10951   },
10952 /* subx${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
10953   {
10954     M32C_INSN_SUBX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "subx", 40,
10955     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10956   },
10957 /* subx${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
10958   {
10959     M32C_INSN_SUBX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "subx", 40,
10960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10961   },
10962 /* subx${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
10963   {
10964     M32C_INSN_SUBX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "subx", 40,
10965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10966   },
10967 /* subx${G} #${Imm-32-QI},${Dsp-16-u16} */
10968   {
10969     M32C_INSN_SUBX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "subx32-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "subx", 40,
10970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10971   },
10972 /* subx${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
10973   {
10974     M32C_INSN_SUBX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "subx", 48,
10975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10976   },
10977 /* subx${G} #${Imm-40-QI},${Dsp-16-u24} */
10978   {
10979     M32C_INSN_SUBX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "subx32-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "subx", 48,
10980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10981   },
10982 /* stzx.w #${Imm-16-HI},#${Imm-32-HI},$Dst32RnUnprefixedHI */
10983   {
10984     M32C_INSN_STZX32_W_IMM_16_HI_IMM_32_HI_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "stzx32.w-Imm-16-HI-Imm-32-HI-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "stzx.w", 48,
10985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10986   },
10987 /* stzx.w #${Imm-16-HI},#${Imm-32-HI},$Dst32AnUnprefixedHI */
10988   {
10989     M32C_INSN_STZX32_W_IMM_16_HI_IMM_32_HI_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "stzx32.w-Imm-16-HI-Imm-32-HI-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "stzx.w", 48,
10990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10991   },
10992 /* stzx.w #${Imm-16-HI},#${Imm-32-HI},[$Dst32AnUnprefixed] */
10993   {
10994     M32C_INSN_STZX32_W_IMM_16_HI_IMM_32_HI_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "stzx32.w-Imm-16-HI-Imm-32-HI-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "stzx.w", 48,
10995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10996   },
10997 /* stzx.w #${Imm-24-HI},#${Imm-40-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
10998   {
10999     M32C_INSN_STZX32_W_IMM_24_HI_IMM_40_HI_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-24-HI-Imm-40-HI-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "stzx.w", 56,
11000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11001   },
11002 /* stzx.w #${Imm-24-HI},#${Imm-40-HI},${Dsp-16-u8}[sb] */
11003   {
11004     M32C_INSN_STZX32_W_IMM_24_HI_IMM_40_HI_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-24-HI-Imm-40-HI-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "stzx.w", 56,
11005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11006   },
11007 /* stzx.w #${Imm-24-HI},#${Imm-40-HI},${Dsp-16-s8}[fb] */
11008   {
11009     M32C_INSN_STZX32_W_IMM_24_HI_IMM_40_HI_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-24-HI-Imm-40-HI-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "stzx.w", 56,
11010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11011   },
11012 /* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11013   {
11014     M32C_INSN_STZX32_W_IMM_32_HI_IMM_48_HI_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-32-HI-Imm-48-HI-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "stzx.w", 64,
11015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11016   },
11017 /* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-u16}[sb] */
11018   {
11019     M32C_INSN_STZX32_W_IMM_32_HI_IMM_48_HI_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-32-HI-Imm-48-HI-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "stzx.w", 64,
11020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11021   },
11022 /* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-s16}[fb] */
11023   {
11024     M32C_INSN_STZX32_W_IMM_32_HI_IMM_48_HI_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-32-HI-Imm-48-HI-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "stzx.w", 64,
11025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11026   },
11027 /* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-u16} */
11028   {
11029     M32C_INSN_STZX32_W_IMM_32_HI_IMM_48_HI_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "stzx32.w-Imm-32-HI-Imm-48-HI-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "stzx.w", 64,
11030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11031   },
11032 /* stzx.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11033   {
11034     M32C_INSN_STZX32_W_IMM_40_HI_IMM_56_HI_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-40-HI-Imm-56-HI-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "stzx.w", 72,
11035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11036   },
11037 /* stzx.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-16-u24} */
11038   {
11039     M32C_INSN_STZX32_W_IMM_40_HI_IMM_56_HI_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "stzx32.w-Imm-40-HI-Imm-56-HI-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "stzx.w", 72,
11040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11041   },
11042 /* stzx.b #${Imm-16-QI},#${Imm-24-QI},$Dst32RnUnprefixedQI */
11043   {
11044     M32C_INSN_STZX32_B_IMM_16_QI_IMM_24_QI_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "stzx32.b-Imm-16-QI-Imm-24-QI-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "stzx.b", 32,
11045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11046   },
11047 /* stzx.b #${Imm-16-QI},#${Imm-24-QI},$Dst32AnUnprefixedQI */
11048   {
11049     M32C_INSN_STZX32_B_IMM_16_QI_IMM_24_QI_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "stzx32.b-Imm-16-QI-Imm-24-QI-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "stzx.b", 32,
11050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11051   },
11052 /* stzx.b #${Imm-16-QI},#${Imm-24-QI},[$Dst32AnUnprefixed] */
11053   {
11054     M32C_INSN_STZX32_B_IMM_16_QI_IMM_24_QI_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "stzx32.b-Imm-16-QI-Imm-24-QI-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "stzx.b", 32,
11055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11056   },
11057 /* stzx.b #${Imm-24-QI},#${Imm-32-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11058   {
11059     M32C_INSN_STZX32_B_IMM_24_QI_IMM_32_QI_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-24-QI-Imm-32-QI-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "stzx.b", 40,
11060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11061   },
11062 /* stzx.b #${Imm-24-QI},#${Imm-32-QI},${Dsp-16-u8}[sb] */
11063   {
11064     M32C_INSN_STZX32_B_IMM_24_QI_IMM_32_QI_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-24-QI-Imm-32-QI-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "stzx.b", 40,
11065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11066   },
11067 /* stzx.b #${Imm-24-QI},#${Imm-32-QI},${Dsp-16-s8}[fb] */
11068   {
11069     M32C_INSN_STZX32_B_IMM_24_QI_IMM_32_QI_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-24-QI-Imm-32-QI-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "stzx.b", 40,
11070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11071   },
11072 /* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11073   {
11074     M32C_INSN_STZX32_B_IMM_32_QI_IMM_40_QI_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-32-QI-Imm-40-QI-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "stzx.b", 48,
11075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11076   },
11077 /* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-u16}[sb] */
11078   {
11079     M32C_INSN_STZX32_B_IMM_32_QI_IMM_40_QI_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-32-QI-Imm-40-QI-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "stzx.b", 48,
11080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11081   },
11082 /* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-s16}[fb] */
11083   {
11084     M32C_INSN_STZX32_B_IMM_32_QI_IMM_40_QI_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-32-QI-Imm-40-QI-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "stzx.b", 48,
11085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11086   },
11087 /* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-u16} */
11088   {
11089     M32C_INSN_STZX32_B_IMM_32_QI_IMM_40_QI_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "stzx32.b-Imm-32-QI-Imm-40-QI-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "stzx.b", 48,
11090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11091   },
11092 /* stzx.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11093   {
11094     M32C_INSN_STZX32_B_IMM_40_QI_IMM_48_QI_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-40-QI-Imm-48-QI-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "stzx.b", 56,
11095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11096   },
11097 /* stzx.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-16-u24} */
11098   {
11099     M32C_INSN_STZX32_B_IMM_40_QI_IMM_48_QI_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "stzx32.b-Imm-40-QI-Imm-48-QI-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "stzx.b", 56,
11100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11101   },
11102 /* stz.w${X} #${Imm-16-HI},$Dst32RnUnprefixedHI */
11103   {
11104     M32C_INSN_STZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "stz32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "stz.w", 32,
11105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11106   },
11107 /* stz.w${X} #${Imm-16-HI},$Dst32AnUnprefixedHI */
11108   {
11109     M32C_INSN_STZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "stz32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "stz.w", 32,
11110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11111   },
11112 /* stz.w${X} #${Imm-16-HI},[$Dst32AnUnprefixed] */
11113   {
11114     M32C_INSN_STZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "stz32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "stz.w", 32,
11115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11116   },
11117 /* stz.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11118   {
11119     M32C_INSN_STZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "stz.w", 40,
11120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11121   },
11122 /* stz.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
11123   {
11124     M32C_INSN_STZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "stz.w", 40,
11125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11126   },
11127 /* stz.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
11128   {
11129     M32C_INSN_STZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "stz.w", 40,
11130     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11131   },
11132 /* stz.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11133   {
11134     M32C_INSN_STZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "stz.w", 48,
11135     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11136   },
11137 /* stz.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
11138   {
11139     M32C_INSN_STZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "stz.w", 48,
11140     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11141   },
11142 /* stz.w${X} #${Imm-32-HI},${Dsp-16-s16}[fb] */
11143   {
11144     M32C_INSN_STZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "stz.w", 48,
11145     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11146   },
11147 /* stz.w${X} #${Imm-32-HI},${Dsp-16-u16} */
11148   {
11149     M32C_INSN_STZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "stz32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "stz.w", 48,
11150     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11151   },
11152 /* stz.w${X} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11153   {
11154     M32C_INSN_STZ32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "stz.w", 56,
11155     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11156   },
11157 /* stz.w${X} #${Imm-40-HI},${Dsp-16-u24} */
11158   {
11159     M32C_INSN_STZ32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "stz32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "stz.w", 56,
11160     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11161   },
11162 /* stz.b${X} #${Imm-16-QI},$Dst32RnUnprefixedQI */
11163   {
11164     M32C_INSN_STZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "stz32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "stz.b", 24,
11165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11166   },
11167 /* stz.b${X} #${Imm-16-QI},$Dst32AnUnprefixedQI */
11168   {
11169     M32C_INSN_STZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "stz32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "stz.b", 24,
11170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11171   },
11172 /* stz.b${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
11173   {
11174     M32C_INSN_STZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "stz32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "stz.b", 24,
11175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11176   },
11177 /* stz.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11178   {
11179     M32C_INSN_STZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "stz.b", 32,
11180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11181   },
11182 /* stz.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
11183   {
11184     M32C_INSN_STZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "stz.b", 32,
11185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11186   },
11187 /* stz.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
11188   {
11189     M32C_INSN_STZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "stz.b", 32,
11190     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11191   },
11192 /* stz.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11193   {
11194     M32C_INSN_STZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "stz.b", 40,
11195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11196   },
11197 /* stz.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
11198   {
11199     M32C_INSN_STZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "stz.b", 40,
11200     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11201   },
11202 /* stz.b${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
11203   {
11204     M32C_INSN_STZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "stz.b", 40,
11205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11206   },
11207 /* stz.b${X} #${Imm-32-QI},${Dsp-16-u16} */
11208   {
11209     M32C_INSN_STZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "stz32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "stz.b", 40,
11210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11211   },
11212 /* stz.b${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11213   {
11214     M32C_INSN_STZ32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "stz.b", 48,
11215     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11216   },
11217 /* stz.b${X} #${Imm-40-QI},${Dsp-16-u24} */
11218   {
11219     M32C_INSN_STZ32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "stz32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "stz.b", 48,
11220     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11221   },
11222 /* stz${S} #${Imm-8-QI},r0l */
11223   {
11224     M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "stz16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "stz", 16,
11225     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11226   },
11227 /* stz${S} #${Imm-8-QI},r0h */
11228   {
11229     M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "stz16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "stz", 16,
11230     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11231   },
11232 /* stz${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
11233   {
11234     M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "stz16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "stz", 24,
11235     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11236   },
11237 /* stz${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
11238   {
11239     M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "stz16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "stz", 24,
11240     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11241   },
11242 /* stz${S} #${Imm-8-QI},${Dsp-16-u16} */
11243   {
11244     M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "stz16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "stz", 32,
11245     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11246   },
11247 /* stnz.w${X} #${Imm-16-HI},$Dst32RnUnprefixedHI */
11248   {
11249     M32C_INSN_STNZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "stnz32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "stnz.w", 32,
11250     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11251   },
11252 /* stnz.w${X} #${Imm-16-HI},$Dst32AnUnprefixedHI */
11253   {
11254     M32C_INSN_STNZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "stnz32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "stnz.w", 32,
11255     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11256   },
11257 /* stnz.w${X} #${Imm-16-HI},[$Dst32AnUnprefixed] */
11258   {
11259     M32C_INSN_STNZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "stnz32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "stnz.w", 32,
11260     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11261   },
11262 /* stnz.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11263   {
11264     M32C_INSN_STNZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "stnz.w", 40,
11265     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11266   },
11267 /* stnz.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
11268   {
11269     M32C_INSN_STNZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "stnz.w", 40,
11270     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11271   },
11272 /* stnz.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
11273   {
11274     M32C_INSN_STNZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "stnz.w", 40,
11275     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11276   },
11277 /* stnz.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11278   {
11279     M32C_INSN_STNZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "stnz.w", 48,
11280     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11281   },
11282 /* stnz.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
11283   {
11284     M32C_INSN_STNZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "stnz.w", 48,
11285     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11286   },
11287 /* stnz.w${X} #${Imm-32-HI},${Dsp-16-s16}[fb] */
11288   {
11289     M32C_INSN_STNZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "stnz.w", 48,
11290     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11291   },
11292 /* stnz.w${X} #${Imm-32-HI},${Dsp-16-u16} */
11293   {
11294     M32C_INSN_STNZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "stnz32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "stnz.w", 48,
11295     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11296   },
11297 /* stnz.w${X} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11298   {
11299     M32C_INSN_STNZ32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "stnz.w", 56,
11300     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11301   },
11302 /* stnz.w${X} #${Imm-40-HI},${Dsp-16-u24} */
11303   {
11304     M32C_INSN_STNZ32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "stnz32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "stnz.w", 56,
11305     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11306   },
11307 /* stnz.b${X} #${Imm-16-QI},$Dst32RnUnprefixedQI */
11308   {
11309     M32C_INSN_STNZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "stnz32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "stnz.b", 24,
11310     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11311   },
11312 /* stnz.b${X} #${Imm-16-QI},$Dst32AnUnprefixedQI */
11313   {
11314     M32C_INSN_STNZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "stnz32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "stnz.b", 24,
11315     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11316   },
11317 /* stnz.b${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
11318   {
11319     M32C_INSN_STNZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "stnz32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "stnz.b", 24,
11320     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11321   },
11322 /* stnz.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11323   {
11324     M32C_INSN_STNZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "stnz.b", 32,
11325     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11326   },
11327 /* stnz.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
11328   {
11329     M32C_INSN_STNZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "stnz.b", 32,
11330     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11331   },
11332 /* stnz.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
11333   {
11334     M32C_INSN_STNZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "stnz.b", 32,
11335     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11336   },
11337 /* stnz.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11338   {
11339     M32C_INSN_STNZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "stnz.b", 40,
11340     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11341   },
11342 /* stnz.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
11343   {
11344     M32C_INSN_STNZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "stnz.b", 40,
11345     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11346   },
11347 /* stnz.b${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
11348   {
11349     M32C_INSN_STNZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "stnz.b", 40,
11350     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11351   },
11352 /* stnz.b${X} #${Imm-32-QI},${Dsp-16-u16} */
11353   {
11354     M32C_INSN_STNZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "stnz32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "stnz.b", 40,
11355     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11356   },
11357 /* stnz.b${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11358   {
11359     M32C_INSN_STNZ32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "stnz.b", 48,
11360     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11361   },
11362 /* stnz.b${X} #${Imm-40-QI},${Dsp-16-u24} */
11363   {
11364     M32C_INSN_STNZ32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "stnz32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "stnz.b", 48,
11365     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11366   },
11367 /* stnz${S} #${Imm-8-QI},r0l */
11368   {
11369     M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "stnz", 16,
11370     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11371   },
11372 /* stnz${S} #${Imm-8-QI},r0h */
11373   {
11374     M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "stnz", 16,
11375     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11376   },
11377 /* stnz${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
11378   {
11379     M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "stnz", 24,
11380     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11381   },
11382 /* stnz${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
11383   {
11384     M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "stnz", 24,
11385     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11386   },
11387 /* stnz${S} #${Imm-8-QI},${Dsp-16-u16} */
11388   {
11389     M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "stnz", 32,
11390     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11391   },
11392 /* shlnc.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
11393   {
11394     M32C_INSN_SHLNC32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "shlnc32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "shlnc.l", 24,
11395     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11396   },
11397 /* shlnc.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
11398   {
11399     M32C_INSN_SHLNC32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "shlnc32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "shlnc.l", 24,
11400     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11401   },
11402 /* shlnc.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
11403   {
11404     M32C_INSN_SHLNC32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "shlnc32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "shlnc.l", 24,
11405     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11406   },
11407 /* shlnc.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11408   {
11409     M32C_INSN_SHLNC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "shlnc.l", 32,
11410     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11411   },
11412 /* shlnc.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
11413   {
11414     M32C_INSN_SHLNC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "shlnc.l", 32,
11415     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11416   },
11417 /* shlnc.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
11418   {
11419     M32C_INSN_SHLNC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "shlnc.l", 32,
11420     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11421   },
11422 /* shlnc.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11423   {
11424     M32C_INSN_SHLNC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "shlnc.l", 40,
11425     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11426   },
11427 /* shlnc.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
11428   {
11429     M32C_INSN_SHLNC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "shlnc.l", 40,
11430     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11431   },
11432 /* shlnc.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
11433   {
11434     M32C_INSN_SHLNC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "shlnc.l", 40,
11435     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11436   },
11437 /* shlnc.l${X} #${Imm-32-QI},${Dsp-16-u16} */
11438   {
11439     M32C_INSN_SHLNC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "shlnc.l", 40,
11440     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11441   },
11442 /* shlnc.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11443   {
11444     M32C_INSN_SHLNC32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "shlnc.l", 48,
11445     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11446   },
11447 /* shlnc.l${X} #${Imm-40-QI},${Dsp-16-u24} */
11448   {
11449     M32C_INSN_SHLNC32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "shlnc.l", 48,
11450     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11451   },
11452 /* shl.l r1h,$Dst32RnUnprefixedSI */
11453   {
11454     M32C_INSN_SHL32_L_DST_DST32_RN_DIRECT_UNPREFIXED_SI, "shl32.l-dst-dst32-Rn-direct-Unprefixed-SI", "shl.l", 16,
11455     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11456   },
11457 /* shl.l r1h,$Dst32AnUnprefixedSI */
11458   {
11459     M32C_INSN_SHL32_L_DST_DST32_AN_DIRECT_UNPREFIXED_SI, "shl32.l-dst-dst32-An-direct-Unprefixed-SI", "shl.l", 16,
11460     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11461   },
11462 /* shl.l r1h,[$Dst32AnUnprefixed] */
11463   {
11464     M32C_INSN_SHL32_L_DST_DST32_AN_INDIRECT_UNPREFIXED_SI, "shl32.l-dst-dst32-An-indirect-Unprefixed-SI", "shl.l", 16,
11465     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11466   },
11467 /* shl.l r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
11468   {
11469     M32C_INSN_SHL32_L_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-8-An-relative-Unprefixed-SI", "shl.l", 24,
11470     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11471   },
11472 /* shl.l r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
11473   {
11474     M32C_INSN_SHL32_L_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-16-An-relative-Unprefixed-SI", "shl.l", 32,
11475     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11476   },
11477 /* shl.l r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
11478   {
11479     M32C_INSN_SHL32_L_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-24-An-relative-Unprefixed-SI", "shl.l", 40,
11480     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11481   },
11482 /* shl.l r1h,${Dsp-16-u8}[sb] */
11483   {
11484     M32C_INSN_SHL32_L_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-8-SB-relative-Unprefixed-SI", "shl.l", 24,
11485     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11486   },
11487 /* shl.l r1h,${Dsp-16-u16}[sb] */
11488   {
11489     M32C_INSN_SHL32_L_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-16-SB-relative-Unprefixed-SI", "shl.l", 32,
11490     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11491   },
11492 /* shl.l r1h,${Dsp-16-s8}[fb] */
11493   {
11494     M32C_INSN_SHL32_L_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-8-FB-relative-Unprefixed-SI", "shl.l", 24,
11495     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11496   },
11497 /* shl.l r1h,${Dsp-16-s16}[fb] */
11498   {
11499     M32C_INSN_SHL32_L_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-16-FB-relative-Unprefixed-SI", "shl.l", 32,
11500     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11501   },
11502 /* shl.l r1h,${Dsp-16-u16} */
11503   {
11504     M32C_INSN_SHL32_L_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-16-absolute-Unprefixed-SI", "shl.l", 32,
11505     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11506   },
11507 /* shl.l r1h,${Dsp-16-u24} */
11508   {
11509     M32C_INSN_SHL32_L_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-24-absolute-Unprefixed-SI", "shl.l", 40,
11510     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11511   },
11512 /* shl.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
11513   {
11514     M32C_INSN_SHL32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "shl32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "shl.l", 24,
11515     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11516   },
11517 /* shl.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
11518   {
11519     M32C_INSN_SHL32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "shl32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "shl.l", 24,
11520     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11521   },
11522 /* shl.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
11523   {
11524     M32C_INSN_SHL32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "shl32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "shl.l", 24,
11525     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11526   },
11527 /* shl.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11528   {
11529     M32C_INSN_SHL32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "shl.l", 32,
11530     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11531   },
11532 /* shl.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
11533   {
11534     M32C_INSN_SHL32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "shl.l", 32,
11535     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11536   },
11537 /* shl.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
11538   {
11539     M32C_INSN_SHL32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "shl.l", 32,
11540     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11541   },
11542 /* shl.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11543   {
11544     M32C_INSN_SHL32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "shl.l", 40,
11545     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11546   },
11547 /* shl.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
11548   {
11549     M32C_INSN_SHL32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "shl.l", 40,
11550     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11551   },
11552 /* shl.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
11553   {
11554     M32C_INSN_SHL32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "shl.l", 40,
11555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11556   },
11557 /* shl.l${X} #${Imm-32-QI},${Dsp-16-u16} */
11558   {
11559     M32C_INSN_SHL32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "shl32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "shl.l", 40,
11560     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11561   },
11562 /* shl.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11563   {
11564     M32C_INSN_SHL32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "shl.l", 48,
11565     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11566   },
11567 /* shl.l${X} #${Imm-40-QI},${Dsp-16-u24} */
11568   {
11569     M32C_INSN_SHL32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "shl32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "shl.l", 48,
11570     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11571   },
11572 /* shl.w r1h,$Dst32RnUnprefixedHI */
11573   {
11574     M32C_INSN_SHL32_W_DST_DST32_RN_DIRECT_UNPREFIXED_HI, "shl32.w-dst-dst32-Rn-direct-Unprefixed-HI", "shl.w", 16,
11575     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11576   },
11577 /* shl.w r1h,$Dst32AnUnprefixedHI */
11578   {
11579     M32C_INSN_SHL32_W_DST_DST32_AN_DIRECT_UNPREFIXED_HI, "shl32.w-dst-dst32-An-direct-Unprefixed-HI", "shl.w", 16,
11580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11581   },
11582 /* shl.w r1h,[$Dst32AnUnprefixed] */
11583   {
11584     M32C_INSN_SHL32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_HI, "shl32.w-dst-dst32-An-indirect-Unprefixed-HI", "shl.w", 16,
11585     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11586   },
11587 /* shl.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
11588   {
11589     M32C_INSN_SHL32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-8-An-relative-Unprefixed-HI", "shl.w", 24,
11590     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11591   },
11592 /* shl.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
11593   {
11594     M32C_INSN_SHL32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-16-An-relative-Unprefixed-HI", "shl.w", 32,
11595     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11596   },
11597 /* shl.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
11598   {
11599     M32C_INSN_SHL32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-24-An-relative-Unprefixed-HI", "shl.w", 40,
11600     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11601   },
11602 /* shl.w r1h,${Dsp-16-u8}[sb] */
11603   {
11604     M32C_INSN_SHL32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-8-SB-relative-Unprefixed-HI", "shl.w", 24,
11605     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11606   },
11607 /* shl.w r1h,${Dsp-16-u16}[sb] */
11608   {
11609     M32C_INSN_SHL32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-16-SB-relative-Unprefixed-HI", "shl.w", 32,
11610     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11611   },
11612 /* shl.w r1h,${Dsp-16-s8}[fb] */
11613   {
11614     M32C_INSN_SHL32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-8-FB-relative-Unprefixed-HI", "shl.w", 24,
11615     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11616   },
11617 /* shl.w r1h,${Dsp-16-s16}[fb] */
11618   {
11619     M32C_INSN_SHL32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-16-FB-relative-Unprefixed-HI", "shl.w", 32,
11620     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11621   },
11622 /* shl.w r1h,${Dsp-16-u16} */
11623   {
11624     M32C_INSN_SHL32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-16-absolute-Unprefixed-HI", "shl.w", 32,
11625     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11626   },
11627 /* shl.w r1h,${Dsp-16-u24} */
11628   {
11629     M32C_INSN_SHL32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-24-absolute-Unprefixed-HI", "shl.w", 40,
11630     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11631   },
11632 /* shl.b r1h,$Dst32RnUnprefixedQI */
11633   {
11634     M32C_INSN_SHL32_B_DST_DST32_RN_DIRECT_UNPREFIXED_QI, "shl32.b-dst-dst32-Rn-direct-Unprefixed-QI", "shl.b", 16,
11635     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11636   },
11637 /* shl.b r1h,$Dst32AnUnprefixedQI */
11638   {
11639     M32C_INSN_SHL32_B_DST_DST32_AN_DIRECT_UNPREFIXED_QI, "shl32.b-dst-dst32-An-direct-Unprefixed-QI", "shl.b", 16,
11640     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11641   },
11642 /* shl.b r1h,[$Dst32AnUnprefixed] */
11643   {
11644     M32C_INSN_SHL32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_QI, "shl32.b-dst-dst32-An-indirect-Unprefixed-QI", "shl.b", 16,
11645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11646   },
11647 /* shl.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
11648   {
11649     M32C_INSN_SHL32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-8-An-relative-Unprefixed-QI", "shl.b", 24,
11650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11651   },
11652 /* shl.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
11653   {
11654     M32C_INSN_SHL32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-16-An-relative-Unprefixed-QI", "shl.b", 32,
11655     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11656   },
11657 /* shl.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
11658   {
11659     M32C_INSN_SHL32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-24-An-relative-Unprefixed-QI", "shl.b", 40,
11660     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11661   },
11662 /* shl.b r1h,${Dsp-16-u8}[sb] */
11663   {
11664     M32C_INSN_SHL32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-8-SB-relative-Unprefixed-QI", "shl.b", 24,
11665     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11666   },
11667 /* shl.b r1h,${Dsp-16-u16}[sb] */
11668   {
11669     M32C_INSN_SHL32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-16-SB-relative-Unprefixed-QI", "shl.b", 32,
11670     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11671   },
11672 /* shl.b r1h,${Dsp-16-s8}[fb] */
11673   {
11674     M32C_INSN_SHL32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-8-FB-relative-Unprefixed-QI", "shl.b", 24,
11675     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11676   },
11677 /* shl.b r1h,${Dsp-16-s16}[fb] */
11678   {
11679     M32C_INSN_SHL32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-16-FB-relative-Unprefixed-QI", "shl.b", 32,
11680     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11681   },
11682 /* shl.b r1h,${Dsp-16-u16} */
11683   {
11684     M32C_INSN_SHL32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-16-absolute-Unprefixed-QI", "shl.b", 32,
11685     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11686   },
11687 /* shl.b r1h,${Dsp-16-u24} */
11688   {
11689     M32C_INSN_SHL32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-24-absolute-Unprefixed-QI", "shl.b", 40,
11690     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11691   },
11692 /* shl.w r1h,$Dst16RnHI */
11693   {
11694     M32C_INSN_SHL16_W_DST_DST16_RN_DIRECT_HI, "shl16.w-dst-dst16-Rn-direct-HI", "shl.w", 16,
11695     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11696   },
11697 /* shl.w r1h,$Dst16AnHI */
11698   {
11699     M32C_INSN_SHL16_W_DST_DST16_AN_DIRECT_HI, "shl16.w-dst-dst16-An-direct-HI", "shl.w", 16,
11700     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11701   },
11702 /* shl.w r1h,[$Dst16An] */
11703   {
11704     M32C_INSN_SHL16_W_DST_DST16_AN_INDIRECT_HI, "shl16.w-dst-dst16-An-indirect-HI", "shl.w", 16,
11705     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11706   },
11707 /* shl.w r1h,${Dsp-16-u8}[$Dst16An] */
11708   {
11709     M32C_INSN_SHL16_W_DST_DST16_16_8_AN_RELATIVE_HI, "shl16.w-dst-dst16-16-8-An-relative-HI", "shl.w", 24,
11710     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11711   },
11712 /* shl.w r1h,${Dsp-16-u16}[$Dst16An] */
11713   {
11714     M32C_INSN_SHL16_W_DST_DST16_16_16_AN_RELATIVE_HI, "shl16.w-dst-dst16-16-16-An-relative-HI", "shl.w", 32,
11715     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11716   },
11717 /* shl.w r1h,${Dsp-16-u8}[sb] */
11718   {
11719     M32C_INSN_SHL16_W_DST_DST16_16_8_SB_RELATIVE_HI, "shl16.w-dst-dst16-16-8-SB-relative-HI", "shl.w", 24,
11720     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11721   },
11722 /* shl.w r1h,${Dsp-16-u16}[sb] */
11723   {
11724     M32C_INSN_SHL16_W_DST_DST16_16_16_SB_RELATIVE_HI, "shl16.w-dst-dst16-16-16-SB-relative-HI", "shl.w", 32,
11725     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11726   },
11727 /* shl.w r1h,${Dsp-16-s8}[fb] */
11728   {
11729     M32C_INSN_SHL16_W_DST_DST16_16_8_FB_RELATIVE_HI, "shl16.w-dst-dst16-16-8-FB-relative-HI", "shl.w", 24,
11730     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11731   },
11732 /* shl.w r1h,${Dsp-16-u16} */
11733   {
11734     M32C_INSN_SHL16_W_DST_DST16_16_16_ABSOLUTE_HI, "shl16.w-dst-dst16-16-16-absolute-HI", "shl.w", 32,
11735     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11736   },
11737 /* shl.b r1h,$Dst16RnQI */
11738   {
11739     M32C_INSN_SHL16_B_DST_DST16_RN_DIRECT_QI, "shl16.b-dst-dst16-Rn-direct-QI", "shl.b", 16,
11740     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11741   },
11742 /* shl.b r1h,$Dst16AnQI */
11743   {
11744     M32C_INSN_SHL16_B_DST_DST16_AN_DIRECT_QI, "shl16.b-dst-dst16-An-direct-QI", "shl.b", 16,
11745     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11746   },
11747 /* shl.b r1h,[$Dst16An] */
11748   {
11749     M32C_INSN_SHL16_B_DST_DST16_AN_INDIRECT_QI, "shl16.b-dst-dst16-An-indirect-QI", "shl.b", 16,
11750     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11751   },
11752 /* shl.b r1h,${Dsp-16-u8}[$Dst16An] */
11753   {
11754     M32C_INSN_SHL16_B_DST_DST16_16_8_AN_RELATIVE_QI, "shl16.b-dst-dst16-16-8-An-relative-QI", "shl.b", 24,
11755     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11756   },
11757 /* shl.b r1h,${Dsp-16-u16}[$Dst16An] */
11758   {
11759     M32C_INSN_SHL16_B_DST_DST16_16_16_AN_RELATIVE_QI, "shl16.b-dst-dst16-16-16-An-relative-QI", "shl.b", 32,
11760     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11761   },
11762 /* shl.b r1h,${Dsp-16-u8}[sb] */
11763   {
11764     M32C_INSN_SHL16_B_DST_DST16_16_8_SB_RELATIVE_QI, "shl16.b-dst-dst16-16-8-SB-relative-QI", "shl.b", 24,
11765     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11766   },
11767 /* shl.b r1h,${Dsp-16-u16}[sb] */
11768   {
11769     M32C_INSN_SHL16_B_DST_DST16_16_16_SB_RELATIVE_QI, "shl16.b-dst-dst16-16-16-SB-relative-QI", "shl.b", 32,
11770     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11771   },
11772 /* shl.b r1h,${Dsp-16-s8}[fb] */
11773   {
11774     M32C_INSN_SHL16_B_DST_DST16_16_8_FB_RELATIVE_QI, "shl16.b-dst-dst16-16-8-FB-relative-QI", "shl.b", 24,
11775     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11776   },
11777 /* shl.b r1h,${Dsp-16-u16} */
11778   {
11779     M32C_INSN_SHL16_B_DST_DST16_16_16_ABSOLUTE_QI, "shl16.b-dst-dst16-16-16-absolute-QI", "shl.b", 32,
11780     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11781   },
11782 /* shl.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */
11783   {
11784     M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "shl.w", 16,
11785     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11786   },
11787 /* shl.w${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedHI */
11788   {
11789     M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "shl.w", 16,
11790     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11791   },
11792 /* shl.w${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
11793   {
11794     M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "shl.w", 16,
11795     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11796   },
11797 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11798   {
11799     M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "shl.w", 24,
11800     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11801   },
11802 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11803   {
11804     M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "shl.w", 32,
11805     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11806   },
11807 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11808   {
11809     M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "shl.w", 40,
11810     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11811   },
11812 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
11813   {
11814     M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "shl.w", 24,
11815     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11816   },
11817 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
11818   {
11819     M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "shl.w", 32,
11820     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11821   },
11822 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
11823   {
11824     M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "shl.w", 24,
11825     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11826   },
11827 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
11828   {
11829     M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "shl.w", 32,
11830     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11831   },
11832 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
11833   {
11834     M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "shl.w", 32,
11835     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11836   },
11837 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
11838   {
11839     M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "shl.w", 40,
11840     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11841   },
11842 /* shl.b${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedQI */
11843   {
11844     M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "shl.b", 16,
11845     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11846   },
11847 /* shl.b${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedQI */
11848   {
11849     M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "shl.b", 16,
11850     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11851   },
11852 /* shl.b${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
11853   {
11854     M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "shl.b", 16,
11855     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11856   },
11857 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11858   {
11859     M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "shl.b", 24,
11860     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11861   },
11862 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11863   {
11864     M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "shl.b", 32,
11865     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11866   },
11867 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11868   {
11869     M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "shl.b", 40,
11870     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11871   },
11872 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
11873   {
11874     M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "shl.b", 24,
11875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11876   },
11877 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
11878   {
11879     M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "shl.b", 32,
11880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11881   },
11882 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
11883   {
11884     M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "shl.b", 24,
11885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11886   },
11887 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
11888   {
11889     M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "shl.b", 32,
11890     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11891   },
11892 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
11893   {
11894     M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "shl.b", 32,
11895     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11896   },
11897 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
11898   {
11899     M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "shl.b", 40,
11900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11901   },
11902 /* shl.w${Q} #${Imm-sh-8-s4},$Dst16RnHI */
11903   {
11904     M32C_INSN_SHL16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "shl16.w-imm4-Q-16-dst16-Rn-direct-HI", "shl.w", 16,
11905     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11906   },
11907 /* shl.w${Q} #${Imm-sh-8-s4},$Dst16AnHI */
11908   {
11909     M32C_INSN_SHL16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "shl16.w-imm4-Q-16-dst16-An-direct-HI", "shl.w", 16,
11910     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11911   },
11912 /* shl.w${Q} #${Imm-sh-8-s4},[$Dst16An] */
11913   {
11914     M32C_INSN_SHL16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "shl16.w-imm4-Q-16-dst16-An-indirect-HI", "shl.w", 16,
11915     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11916   },
11917 /* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
11918   {
11919     M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "shl.w", 24,
11920     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11921   },
11922 /* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
11923   {
11924     M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "shl.w", 32,
11925     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11926   },
11927 /* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
11928   {
11929     M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "shl.w", 24,
11930     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11931   },
11932 /* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
11933   {
11934     M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "shl.w", 32,
11935     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11936   },
11937 /* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
11938   {
11939     M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "shl.w", 24,
11940     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11941   },
11942 /* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
11943   {
11944     M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "shl16.w-imm4-Q-16-dst16-16-16-absolute-HI", "shl.w", 32,
11945     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11946   },
11947 /* shl.b${Q} #${Imm-sh-8-s4},$Dst16RnQI */
11948   {
11949     M32C_INSN_SHL16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "shl16.b-imm4-Q-16-dst16-Rn-direct-QI", "shl.b", 16,
11950     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11951   },
11952 /* shl.b${Q} #${Imm-sh-8-s4},$Dst16AnQI */
11953   {
11954     M32C_INSN_SHL16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "shl16.b-imm4-Q-16-dst16-An-direct-QI", "shl.b", 16,
11955     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11956   },
11957 /* shl.b${Q} #${Imm-sh-8-s4},[$Dst16An] */
11958   {
11959     M32C_INSN_SHL16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "shl16.b-imm4-Q-16-dst16-An-indirect-QI", "shl.b", 16,
11960     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11961   },
11962 /* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
11963   {
11964     M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "shl.b", 24,
11965     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11966   },
11967 /* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
11968   {
11969     M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "shl.b", 32,
11970     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11971   },
11972 /* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
11973   {
11974     M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "shl.b", 24,
11975     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11976   },
11977 /* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
11978   {
11979     M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "shl.b", 32,
11980     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11981   },
11982 /* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
11983   {
11984     M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "shl.b", 24,
11985     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11986   },
11987 /* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
11988   {
11989     M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "shl16.b-imm4-Q-16-dst16-16-16-absolute-QI", "shl.b", 32,
11990     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11991   },
11992 /* shanc.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
11993   {
11994     M32C_INSN_SHANC32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "shanc32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "shanc.l", 24,
11995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11996   },
11997 /* shanc.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
11998   {
11999     M32C_INSN_SHANC32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "shanc32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "shanc.l", 24,
12000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12001   },
12002 /* shanc.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
12003   {
12004     M32C_INSN_SHANC32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "shanc32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "shanc.l", 24,
12005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12006   },
12007 /* shanc.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
12008   {
12009     M32C_INSN_SHANC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "shanc.l", 32,
12010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12011   },
12012 /* shanc.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
12013   {
12014     M32C_INSN_SHANC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "shanc.l", 32,
12015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12016   },
12017 /* shanc.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
12018   {
12019     M32C_INSN_SHANC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "shanc.l", 32,
12020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12021   },
12022 /* shanc.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
12023   {
12024     M32C_INSN_SHANC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "shanc.l", 40,
12025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12026   },
12027 /* shanc.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
12028   {
12029     M32C_INSN_SHANC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "shanc.l", 40,
12030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12031   },
12032 /* shanc.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
12033   {
12034     M32C_INSN_SHANC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "shanc.l", 40,
12035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12036   },
12037 /* shanc.l${X} #${Imm-32-QI},${Dsp-16-u16} */
12038   {
12039     M32C_INSN_SHANC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "shanc32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "shanc.l", 40,
12040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12041   },
12042 /* shanc.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
12043   {
12044     M32C_INSN_SHANC32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "shanc.l", 48,
12045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12046   },
12047 /* shanc.l${X} #${Imm-40-QI},${Dsp-16-u24} */
12048   {
12049     M32C_INSN_SHANC32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "shanc32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "shanc.l", 48,
12050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12051   },
12052 /* sha.l r1h,$Dst32RnUnprefixedSI */
12053   {
12054     M32C_INSN_SHA32_L_DST_DST32_RN_DIRECT_UNPREFIXED_SI, "sha32.l-dst-dst32-Rn-direct-Unprefixed-SI", "sha.l", 16,
12055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12056   },
12057 /* sha.l r1h,$Dst32AnUnprefixedSI */
12058   {
12059     M32C_INSN_SHA32_L_DST_DST32_AN_DIRECT_UNPREFIXED_SI, "sha32.l-dst-dst32-An-direct-Unprefixed-SI", "sha.l", 16,
12060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12061   },
12062 /* sha.l r1h,[$Dst32AnUnprefixed] */
12063   {
12064     M32C_INSN_SHA32_L_DST_DST32_AN_INDIRECT_UNPREFIXED_SI, "sha32.l-dst-dst32-An-indirect-Unprefixed-SI", "sha.l", 16,
12065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12066   },
12067 /* sha.l r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
12068   {
12069     M32C_INSN_SHA32_L_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-8-An-relative-Unprefixed-SI", "sha.l", 24,
12070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12071   },
12072 /* sha.l r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
12073   {
12074     M32C_INSN_SHA32_L_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-16-An-relative-Unprefixed-SI", "sha.l", 32,
12075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12076   },
12077 /* sha.l r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
12078   {
12079     M32C_INSN_SHA32_L_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-24-An-relative-Unprefixed-SI", "sha.l", 40,
12080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12081   },
12082 /* sha.l r1h,${Dsp-16-u8}[sb] */
12083   {
12084     M32C_INSN_SHA32_L_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-8-SB-relative-Unprefixed-SI", "sha.l", 24,
12085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12086   },
12087 /* sha.l r1h,${Dsp-16-u16}[sb] */
12088   {
12089     M32C_INSN_SHA32_L_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-16-SB-relative-Unprefixed-SI", "sha.l", 32,
12090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12091   },
12092 /* sha.l r1h,${Dsp-16-s8}[fb] */
12093   {
12094     M32C_INSN_SHA32_L_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-8-FB-relative-Unprefixed-SI", "sha.l", 24,
12095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12096   },
12097 /* sha.l r1h,${Dsp-16-s16}[fb] */
12098   {
12099     M32C_INSN_SHA32_L_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-16-FB-relative-Unprefixed-SI", "sha.l", 32,
12100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12101   },
12102 /* sha.l r1h,${Dsp-16-u16} */
12103   {
12104     M32C_INSN_SHA32_L_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-16-absolute-Unprefixed-SI", "sha.l", 32,
12105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12106   },
12107 /* sha.l r1h,${Dsp-16-u24} */
12108   {
12109     M32C_INSN_SHA32_L_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-24-absolute-Unprefixed-SI", "sha.l", 40,
12110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12111   },
12112 /* sha.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
12113   {
12114     M32C_INSN_SHA32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "sha32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "sha.l", 24,
12115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12116   },
12117 /* sha.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
12118   {
12119     M32C_INSN_SHA32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "sha32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "sha.l", 24,
12120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12121   },
12122 /* sha.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
12123   {
12124     M32C_INSN_SHA32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "sha32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "sha.l", 24,
12125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12126   },
12127 /* sha.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
12128   {
12129     M32C_INSN_SHA32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "sha.l", 32,
12130     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12131   },
12132 /* sha.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
12133   {
12134     M32C_INSN_SHA32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "sha.l", 32,
12135     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12136   },
12137 /* sha.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
12138   {
12139     M32C_INSN_SHA32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "sha.l", 32,
12140     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12141   },
12142 /* sha.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
12143   {
12144     M32C_INSN_SHA32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "sha.l", 40,
12145     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12146   },
12147 /* sha.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
12148   {
12149     M32C_INSN_SHA32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "sha.l", 40,
12150     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12151   },
12152 /* sha.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
12153   {
12154     M32C_INSN_SHA32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "sha.l", 40,
12155     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12156   },
12157 /* sha.l${X} #${Imm-32-QI},${Dsp-16-u16} */
12158   {
12159     M32C_INSN_SHA32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sha32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "sha.l", 40,
12160     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12161   },
12162 /* sha.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
12163   {
12164     M32C_INSN_SHA32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "sha.l", 48,
12165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12166   },
12167 /* sha.l${X} #${Imm-40-QI},${Dsp-16-u24} */
12168   {
12169     M32C_INSN_SHA32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sha32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "sha.l", 48,
12170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12171   },
12172 /* sha.w r1h,$Dst32RnUnprefixedHI */
12173   {
12174     M32C_INSN_SHA32_W_DST_DST32_RN_DIRECT_UNPREFIXED_HI, "sha32.w-dst-dst32-Rn-direct-Unprefixed-HI", "sha.w", 16,
12175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12176   },
12177 /* sha.w r1h,$Dst32AnUnprefixedHI */
12178   {
12179     M32C_INSN_SHA32_W_DST_DST32_AN_DIRECT_UNPREFIXED_HI, "sha32.w-dst-dst32-An-direct-Unprefixed-HI", "sha.w", 16,
12180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12181   },
12182 /* sha.w r1h,[$Dst32AnUnprefixed] */
12183   {
12184     M32C_INSN_SHA32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_HI, "sha32.w-dst-dst32-An-indirect-Unprefixed-HI", "sha.w", 16,
12185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12186   },
12187 /* sha.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
12188   {
12189     M32C_INSN_SHA32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-8-An-relative-Unprefixed-HI", "sha.w", 24,
12190     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12191   },
12192 /* sha.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
12193   {
12194     M32C_INSN_SHA32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-16-An-relative-Unprefixed-HI", "sha.w", 32,
12195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12196   },
12197 /* sha.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
12198   {
12199     M32C_INSN_SHA32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-24-An-relative-Unprefixed-HI", "sha.w", 40,
12200     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12201   },
12202 /* sha.w r1h,${Dsp-16-u8}[sb] */
12203   {
12204     M32C_INSN_SHA32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-8-SB-relative-Unprefixed-HI", "sha.w", 24,
12205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12206   },
12207 /* sha.w r1h,${Dsp-16-u16}[sb] */
12208   {
12209     M32C_INSN_SHA32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-16-SB-relative-Unprefixed-HI", "sha.w", 32,
12210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12211   },
12212 /* sha.w r1h,${Dsp-16-s8}[fb] */
12213   {
12214     M32C_INSN_SHA32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-8-FB-relative-Unprefixed-HI", "sha.w", 24,
12215     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12216   },
12217 /* sha.w r1h,${Dsp-16-s16}[fb] */
12218   {
12219     M32C_INSN_SHA32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-16-FB-relative-Unprefixed-HI", "sha.w", 32,
12220     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12221   },
12222 /* sha.w r1h,${Dsp-16-u16} */
12223   {
12224     M32C_INSN_SHA32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-16-absolute-Unprefixed-HI", "sha.w", 32,
12225     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12226   },
12227 /* sha.w r1h,${Dsp-16-u24} */
12228   {
12229     M32C_INSN_SHA32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-24-absolute-Unprefixed-HI", "sha.w", 40,
12230     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12231   },
12232 /* sha.b r1h,$Dst32RnUnprefixedQI */
12233   {
12234     M32C_INSN_SHA32_B_DST_DST32_RN_DIRECT_UNPREFIXED_QI, "sha32.b-dst-dst32-Rn-direct-Unprefixed-QI", "sha.b", 16,
12235     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12236   },
12237 /* sha.b r1h,$Dst32AnUnprefixedQI */
12238   {
12239     M32C_INSN_SHA32_B_DST_DST32_AN_DIRECT_UNPREFIXED_QI, "sha32.b-dst-dst32-An-direct-Unprefixed-QI", "sha.b", 16,
12240     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12241   },
12242 /* sha.b r1h,[$Dst32AnUnprefixed] */
12243   {
12244     M32C_INSN_SHA32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_QI, "sha32.b-dst-dst32-An-indirect-Unprefixed-QI", "sha.b", 16,
12245     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12246   },
12247 /* sha.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
12248   {
12249     M32C_INSN_SHA32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-8-An-relative-Unprefixed-QI", "sha.b", 24,
12250     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12251   },
12252 /* sha.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
12253   {
12254     M32C_INSN_SHA32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-16-An-relative-Unprefixed-QI", "sha.b", 32,
12255     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12256   },
12257 /* sha.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
12258   {
12259     M32C_INSN_SHA32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-24-An-relative-Unprefixed-QI", "sha.b", 40,
12260     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12261   },
12262 /* sha.b r1h,${Dsp-16-u8}[sb] */
12263   {
12264     M32C_INSN_SHA32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-8-SB-relative-Unprefixed-QI", "sha.b", 24,
12265     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12266   },
12267 /* sha.b r1h,${Dsp-16-u16}[sb] */
12268   {
12269     M32C_INSN_SHA32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-16-SB-relative-Unprefixed-QI", "sha.b", 32,
12270     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12271   },
12272 /* sha.b r1h,${Dsp-16-s8}[fb] */
12273   {
12274     M32C_INSN_SHA32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-8-FB-relative-Unprefixed-QI", "sha.b", 24,
12275     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12276   },
12277 /* sha.b r1h,${Dsp-16-s16}[fb] */
12278   {
12279     M32C_INSN_SHA32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-16-FB-relative-Unprefixed-QI", "sha.b", 32,
12280     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12281   },
12282 /* sha.b r1h,${Dsp-16-u16} */
12283   {
12284     M32C_INSN_SHA32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-16-absolute-Unprefixed-QI", "sha.b", 32,
12285     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12286   },
12287 /* sha.b r1h,${Dsp-16-u24} */
12288   {
12289     M32C_INSN_SHA32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-24-absolute-Unprefixed-QI", "sha.b", 40,
12290     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12291   },
12292 /* sha.w r1h,$Dst16RnHI */
12293   {
12294     M32C_INSN_SHA16_W_DST_DST16_RN_DIRECT_HI, "sha16.w-dst-dst16-Rn-direct-HI", "sha.w", 16,
12295     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12296   },
12297 /* sha.w r1h,$Dst16AnHI */
12298   {
12299     M32C_INSN_SHA16_W_DST_DST16_AN_DIRECT_HI, "sha16.w-dst-dst16-An-direct-HI", "sha.w", 16,
12300     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12301   },
12302 /* sha.w r1h,[$Dst16An] */
12303   {
12304     M32C_INSN_SHA16_W_DST_DST16_AN_INDIRECT_HI, "sha16.w-dst-dst16-An-indirect-HI", "sha.w", 16,
12305     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12306   },
12307 /* sha.w r1h,${Dsp-16-u8}[$Dst16An] */
12308   {
12309     M32C_INSN_SHA16_W_DST_DST16_16_8_AN_RELATIVE_HI, "sha16.w-dst-dst16-16-8-An-relative-HI", "sha.w", 24,
12310     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12311   },
12312 /* sha.w r1h,${Dsp-16-u16}[$Dst16An] */
12313   {
12314     M32C_INSN_SHA16_W_DST_DST16_16_16_AN_RELATIVE_HI, "sha16.w-dst-dst16-16-16-An-relative-HI", "sha.w", 32,
12315     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12316   },
12317 /* sha.w r1h,${Dsp-16-u8}[sb] */
12318   {
12319     M32C_INSN_SHA16_W_DST_DST16_16_8_SB_RELATIVE_HI, "sha16.w-dst-dst16-16-8-SB-relative-HI", "sha.w", 24,
12320     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12321   },
12322 /* sha.w r1h,${Dsp-16-u16}[sb] */
12323   {
12324     M32C_INSN_SHA16_W_DST_DST16_16_16_SB_RELATIVE_HI, "sha16.w-dst-dst16-16-16-SB-relative-HI", "sha.w", 32,
12325     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12326   },
12327 /* sha.w r1h,${Dsp-16-s8}[fb] */
12328   {
12329     M32C_INSN_SHA16_W_DST_DST16_16_8_FB_RELATIVE_HI, "sha16.w-dst-dst16-16-8-FB-relative-HI", "sha.w", 24,
12330     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12331   },
12332 /* sha.w r1h,${Dsp-16-u16} */
12333   {
12334     M32C_INSN_SHA16_W_DST_DST16_16_16_ABSOLUTE_HI, "sha16.w-dst-dst16-16-16-absolute-HI", "sha.w", 32,
12335     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12336   },
12337 /* sha.b r1h,$Dst16RnQI */
12338   {
12339     M32C_INSN_SHA16_B_DST_DST16_RN_DIRECT_QI, "sha16.b-dst-dst16-Rn-direct-QI", "sha.b", 16,
12340     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12341   },
12342 /* sha.b r1h,$Dst16AnQI */
12343   {
12344     M32C_INSN_SHA16_B_DST_DST16_AN_DIRECT_QI, "sha16.b-dst-dst16-An-direct-QI", "sha.b", 16,
12345     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12346   },
12347 /* sha.b r1h,[$Dst16An] */
12348   {
12349     M32C_INSN_SHA16_B_DST_DST16_AN_INDIRECT_QI, "sha16.b-dst-dst16-An-indirect-QI", "sha.b", 16,
12350     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12351   },
12352 /* sha.b r1h,${Dsp-16-u8}[$Dst16An] */
12353   {
12354     M32C_INSN_SHA16_B_DST_DST16_16_8_AN_RELATIVE_QI, "sha16.b-dst-dst16-16-8-An-relative-QI", "sha.b", 24,
12355     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12356   },
12357 /* sha.b r1h,${Dsp-16-u16}[$Dst16An] */
12358   {
12359     M32C_INSN_SHA16_B_DST_DST16_16_16_AN_RELATIVE_QI, "sha16.b-dst-dst16-16-16-An-relative-QI", "sha.b", 32,
12360     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12361   },
12362 /* sha.b r1h,${Dsp-16-u8}[sb] */
12363   {
12364     M32C_INSN_SHA16_B_DST_DST16_16_8_SB_RELATIVE_QI, "sha16.b-dst-dst16-16-8-SB-relative-QI", "sha.b", 24,
12365     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12366   },
12367 /* sha.b r1h,${Dsp-16-u16}[sb] */
12368   {
12369     M32C_INSN_SHA16_B_DST_DST16_16_16_SB_RELATIVE_QI, "sha16.b-dst-dst16-16-16-SB-relative-QI", "sha.b", 32,
12370     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12371   },
12372 /* sha.b r1h,${Dsp-16-s8}[fb] */
12373   {
12374     M32C_INSN_SHA16_B_DST_DST16_16_8_FB_RELATIVE_QI, "sha16.b-dst-dst16-16-8-FB-relative-QI", "sha.b", 24,
12375     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12376   },
12377 /* sha.b r1h,${Dsp-16-u16} */
12378   {
12379     M32C_INSN_SHA16_B_DST_DST16_16_16_ABSOLUTE_QI, "sha16.b-dst-dst16-16-16-absolute-QI", "sha.b", 32,
12380     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12381   },
12382 /* sha.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */
12383   {
12384     M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "sha.w", 16,
12385     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12386   },
12387 /* sha.w${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedHI */
12388   {
12389     M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "sha.w", 16,
12390     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12391   },
12392 /* sha.w${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
12393   {
12394     M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "sha.w", 16,
12395     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12396   },
12397 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
12398   {
12399     M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "sha.w", 24,
12400     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12401   },
12402 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
12403   {
12404     M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "sha.w", 32,
12405     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12406   },
12407 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
12408   {
12409     M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "sha.w", 40,
12410     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12411   },
12412 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
12413   {
12414     M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "sha.w", 24,
12415     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12416   },
12417 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
12418   {
12419     M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "sha.w", 32,
12420     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12421   },
12422 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
12423   {
12424     M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "sha.w", 24,
12425     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12426   },
12427 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
12428   {
12429     M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "sha.w", 32,
12430     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12431   },
12432 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
12433   {
12434     M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "sha.w", 32,
12435     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12436   },
12437 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
12438   {
12439     M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "sha.w", 40,
12440     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12441   },
12442 /* sha.b${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedQI */
12443   {
12444     M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "sha.b", 16,
12445     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12446   },
12447 /* sha.b${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedQI */
12448   {
12449     M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "sha.b", 16,
12450     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12451   },
12452 /* sha.b${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
12453   {
12454     M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "sha.b", 16,
12455     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12456   },
12457 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
12458   {
12459     M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "sha.b", 24,
12460     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12461   },
12462 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
12463   {
12464     M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "sha.b", 32,
12465     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12466   },
12467 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
12468   {
12469     M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "sha.b", 40,
12470     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12471   },
12472 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
12473   {
12474     M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "sha.b", 24,
12475     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12476   },
12477 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
12478   {
12479     M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "sha.b", 32,
12480     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12481   },
12482 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
12483   {
12484     M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "sha.b", 24,
12485     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12486   },
12487 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
12488   {
12489     M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "sha.b", 32,
12490     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12491   },
12492 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
12493   {
12494     M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "sha.b", 32,
12495     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12496   },
12497 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
12498   {
12499     M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "sha.b", 40,
12500     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12501   },
12502 /* sha.w${Q} #${Imm-sh-8-s4},$Dst16RnHI */
12503   {
12504     M32C_INSN_SHA16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "sha16.w-imm4-Q-16-dst16-Rn-direct-HI", "sha.w", 16,
12505     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12506   },
12507 /* sha.w${Q} #${Imm-sh-8-s4},$Dst16AnHI */
12508   {
12509     M32C_INSN_SHA16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "sha16.w-imm4-Q-16-dst16-An-direct-HI", "sha.w", 16,
12510     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12511   },
12512 /* sha.w${Q} #${Imm-sh-8-s4},[$Dst16An] */
12513   {
12514     M32C_INSN_SHA16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "sha16.w-imm4-Q-16-dst16-An-indirect-HI", "sha.w", 16,
12515     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12516   },
12517 /* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
12518   {
12519     M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "sha.w", 24,
12520     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12521   },
12522 /* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
12523   {
12524     M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "sha.w", 32,
12525     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12526   },
12527 /* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
12528   {
12529     M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "sha.w", 24,
12530     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12531   },
12532 /* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
12533   {
12534     M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "sha.w", 32,
12535     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12536   },
12537 /* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
12538   {
12539     M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "sha.w", 24,
12540     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12541   },
12542 /* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
12543   {
12544     M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "sha16.w-imm4-Q-16-dst16-16-16-absolute-HI", "sha.w", 32,
12545     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12546   },
12547 /* sha.b${Q} #${Imm-sh-8-s4},$Dst16RnQI */
12548   {
12549     M32C_INSN_SHA16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "sha16.b-imm4-Q-16-dst16-Rn-direct-QI", "sha.b", 16,
12550     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12551   },
12552 /* sha.b${Q} #${Imm-sh-8-s4},$Dst16AnQI */
12553   {
12554     M32C_INSN_SHA16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "sha16.b-imm4-Q-16-dst16-An-direct-QI", "sha.b", 16,
12555     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12556   },
12557 /* sha.b${Q} #${Imm-sh-8-s4},[$Dst16An] */
12558   {
12559     M32C_INSN_SHA16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "sha16.b-imm4-Q-16-dst16-An-indirect-QI", "sha.b", 16,
12560     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12561   },
12562 /* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
12563   {
12564     M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "sha.b", 24,
12565     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12566   },
12567 /* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
12568   {
12569     M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "sha.b", 32,
12570     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12571   },
12572 /* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
12573   {
12574     M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "sha.b", 24,
12575     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12576   },
12577 /* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
12578   {
12579     M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "sha.b", 32,
12580     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12581   },
12582 /* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
12583   {
12584     M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "sha.b", 24,
12585     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12586   },
12587 /* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
12588   {
12589     M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "sha16.b-imm4-Q-16-dst16-16-16-absolute-QI", "sha.b", 32,
12590     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12591   },
12592 /* sc${sccond32} $Dst32RnUnprefixedHI */
12593   {
12594     M32C_INSN_SCCND_DST32_RN_DIRECT_UNPREFIXED_HI, "sccnd-dst32-Rn-direct-Unprefixed-HI", "sc", 16,
12595     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12596   },
12597 /* sc${sccond32} $Dst32AnUnprefixedHI */
12598   {
12599     M32C_INSN_SCCND_DST32_AN_DIRECT_UNPREFIXED_HI, "sccnd-dst32-An-direct-Unprefixed-HI", "sc", 16,
12600     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12601   },
12602 /* sc${sccond32} [$Dst32AnUnprefixed] */
12603   {
12604     M32C_INSN_SCCND_DST32_AN_INDIRECT_UNPREFIXED_HI, "sccnd-dst32-An-indirect-Unprefixed-HI", "sc", 16,
12605     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12606   },
12607 /* sc${sccond32} ${Dsp-16-u8}[$Dst32AnUnprefixed] */
12608   {
12609     M32C_INSN_SCCND_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-8-An-relative-Unprefixed-HI", "sc", 24,
12610     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12611   },
12612 /* sc${sccond32} ${Dsp-16-u16}[$Dst32AnUnprefixed] */
12613   {
12614     M32C_INSN_SCCND_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-16-An-relative-Unprefixed-HI", "sc", 32,
12615     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12616   },
12617 /* sc${sccond32} ${Dsp-16-u24}[$Dst32AnUnprefixed] */
12618   {
12619     M32C_INSN_SCCND_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-24-An-relative-Unprefixed-HI", "sc", 40,
12620     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12621   },
12622 /* sc${sccond32} ${Dsp-16-u8}[sb] */
12623   {
12624     M32C_INSN_SCCND_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-8-SB-relative-Unprefixed-HI", "sc", 24,
12625     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12626   },
12627 /* sc${sccond32} ${Dsp-16-u16}[sb] */
12628   {
12629     M32C_INSN_SCCND_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-16-SB-relative-Unprefixed-HI", "sc", 32,
12630     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12631   },
12632 /* sc${sccond32} ${Dsp-16-s8}[fb] */
12633   {
12634     M32C_INSN_SCCND_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-8-FB-relative-Unprefixed-HI", "sc", 24,
12635     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12636   },
12637 /* sc${sccond32} ${Dsp-16-s16}[fb] */
12638   {
12639     M32C_INSN_SCCND_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-16-FB-relative-Unprefixed-HI", "sc", 32,
12640     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12641   },
12642 /* sc${sccond32} ${Dsp-16-u16} */
12643   {
12644     M32C_INSN_SCCND_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sccnd-dst32-16-16-absolute-Unprefixed-HI", "sc", 32,
12645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12646   },
12647 /* sc${sccond32} ${Dsp-16-u24} */
12648   {
12649     M32C_INSN_SCCND_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sccnd-dst32-16-24-absolute-Unprefixed-HI", "sc", 40,
12650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12651   },
12652 /* sbjnz.w #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
12653   {
12654     M32C_INSN_SBJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "sbjnz.w", 32,
12655     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12656   },
12657 /* sbjnz.w #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
12658   {
12659     M32C_INSN_SBJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "sbjnz.w", 32,
12660     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12661   },
12662 /* sbjnz.w #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
12663   {
12664     M32C_INSN_SBJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "sbjnz.w", 32,
12665     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12666   },
12667 /* sbjnz.w #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
12668   {
12669     M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "sbjnz.w", 40,
12670     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12671   },
12672 /* sbjnz.w #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
12673   {
12674     M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "sbjnz.w", 40,
12675     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12676   },
12677 /* sbjnz.w #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */
12678   {
12679     M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "sbjnz.w", 40,
12680     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12681   },
12682 /* sbjnz.w #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */
12683   {
12684     M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "sbjnz.w", 40,
12685     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12686   },
12687 /* sbjnz.w #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
12688   {
12689     M32C_INSN_SBJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "sbjnz.w", 48,
12690     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12691   },
12692 /* sbjnz.w #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */
12693   {
12694     M32C_INSN_SBJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "sbjnz.w", 48,
12695     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12696   },
12697 /* sbjnz.w #${Imm-12-s4},$Dst32RnUnprefixedHI,${Lab-16-8} */
12698   {
12699     M32C_INSN_SBJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "sbjnz32.w-imm4-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "sbjnz.w", 24,
12700     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12701   },
12702 /* sbjnz.w #${Imm-12-s4},$Dst32AnUnprefixedHI,${Lab-16-8} */
12703   {
12704     M32C_INSN_SBJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "sbjnz32.w-imm4-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "sbjnz.w", 24,
12705     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12706   },
12707 /* sbjnz.w #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */
12708   {
12709     M32C_INSN_SBJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "sbjnz32.w-imm4-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "sbjnz.w", 24,
12710     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12711   },
12712 /* sbjnz.b #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
12713   {
12714     M32C_INSN_SBJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "sbjnz.b", 32,
12715     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12716   },
12717 /* sbjnz.b #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
12718   {
12719     M32C_INSN_SBJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "sbjnz.b", 32,
12720     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12721   },
12722 /* sbjnz.b #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
12723   {
12724     M32C_INSN_SBJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "sbjnz.b", 32,
12725     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12726   },
12727 /* sbjnz.b #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
12728   {
12729     M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "sbjnz.b", 40,
12730     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12731   },
12732 /* sbjnz.b #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
12733   {
12734     M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "sbjnz.b", 40,
12735     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12736   },
12737 /* sbjnz.b #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */
12738   {
12739     M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "sbjnz.b", 40,
12740     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12741   },
12742 /* sbjnz.b #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */
12743   {
12744     M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "sbjnz.b", 40,
12745     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12746   },
12747 /* sbjnz.b #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
12748   {
12749     M32C_INSN_SBJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "sbjnz.b", 48,
12750     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12751   },
12752 /* sbjnz.b #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */
12753   {
12754     M32C_INSN_SBJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "sbjnz.b", 48,
12755     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12756   },
12757 /* sbjnz.b #${Imm-12-s4},$Dst32RnUnprefixedQI,${Lab-16-8} */
12758   {
12759     M32C_INSN_SBJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "sbjnz32.b-imm4-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "sbjnz.b", 24,
12760     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12761   },
12762 /* sbjnz.b #${Imm-12-s4},$Dst32AnUnprefixedQI,${Lab-16-8} */
12763   {
12764     M32C_INSN_SBJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "sbjnz32.b-imm4-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "sbjnz.b", 24,
12765     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12766   },
12767 /* sbjnz.b #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */
12768   {
12769     M32C_INSN_SBJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "sbjnz32.b-imm4-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "sbjnz.b", 24,
12770     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12771   },
12772 /* sbjnz.w #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
12773   {
12774     M32C_INSN_SBJNZ16_W_IMM4_16_8_DST16_16_8_AN_RELATIVE_HI, "sbjnz16.w-imm4-16-8-dst16-16-8-An-relative-HI", "sbjnz.w", 32,
12775     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12776   },
12777 /* sbjnz.w #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
12778   {
12779     M32C_INSN_SBJNZ16_W_IMM4_16_8_DST16_16_8_SB_RELATIVE_HI, "sbjnz16.w-imm4-16-8-dst16-16-8-SB-relative-HI", "sbjnz.w", 32,
12780     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12781   },
12782 /* sbjnz.w #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
12783   {
12784     M32C_INSN_SBJNZ16_W_IMM4_16_8_DST16_16_8_FB_RELATIVE_HI, "sbjnz16.w-imm4-16-8-dst16-16-8-FB-relative-HI", "sbjnz.w", 32,
12785     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12786   },
12787 /* sbjnz.w #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
12788   {
12789     M32C_INSN_SBJNZ16_W_IMM4_16_16_DST16_16_16_AN_RELATIVE_HI, "sbjnz16.w-imm4-16-16-dst16-16-16-An-relative-HI", "sbjnz.w", 40,
12790     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12791   },
12792 /* sbjnz.w #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
12793   {
12794     M32C_INSN_SBJNZ16_W_IMM4_16_16_DST16_16_16_SB_RELATIVE_HI, "sbjnz16.w-imm4-16-16-dst16-16-16-SB-relative-HI", "sbjnz.w", 40,
12795     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12796   },
12797 /* sbjnz.w #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */
12798   {
12799     M32C_INSN_SBJNZ16_W_IMM4_16_16_DST16_16_16_ABSOLUTE_HI, "sbjnz16.w-imm4-16-16-dst16-16-16-absolute-HI", "sbjnz.w", 40,
12800     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12801   },
12802 /* sbjnz.w #${Imm-8-s4},$Dst16RnHI,${Lab-16-8} */
12803   {
12804     M32C_INSN_SBJNZ16_W_IMM4_BASIC_DST16_RN_DIRECT_HI, "sbjnz16.w-imm4-basic-dst16-Rn-direct-HI", "sbjnz.w", 24,
12805     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12806   },
12807 /* sbjnz.w #${Imm-8-s4},$Dst16AnHI,${Lab-16-8} */
12808   {
12809     M32C_INSN_SBJNZ16_W_IMM4_BASIC_DST16_AN_DIRECT_HI, "sbjnz16.w-imm4-basic-dst16-An-direct-HI", "sbjnz.w", 24,
12810     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12811   },
12812 /* sbjnz.w #${Imm-8-s4},[$Dst16An],${Lab-16-8} */
12813   {
12814     M32C_INSN_SBJNZ16_W_IMM4_BASIC_DST16_AN_INDIRECT_HI, "sbjnz16.w-imm4-basic-dst16-An-indirect-HI", "sbjnz.w", 24,
12815     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12816   },
12817 /* sbjnz.b #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
12818   {
12819     M32C_INSN_SBJNZ16_B_IMM4_16_8_DST16_16_8_AN_RELATIVE_QI, "sbjnz16.b-imm4-16-8-dst16-16-8-An-relative-QI", "sbjnz.b", 32,
12820     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12821   },
12822 /* sbjnz.b #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
12823   {
12824     M32C_INSN_SBJNZ16_B_IMM4_16_8_DST16_16_8_SB_RELATIVE_QI, "sbjnz16.b-imm4-16-8-dst16-16-8-SB-relative-QI", "sbjnz.b", 32,
12825     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12826   },
12827 /* sbjnz.b #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
12828   {
12829     M32C_INSN_SBJNZ16_B_IMM4_16_8_DST16_16_8_FB_RELATIVE_QI, "sbjnz16.b-imm4-16-8-dst16-16-8-FB-relative-QI", "sbjnz.b", 32,
12830     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12831   },
12832 /* sbjnz.b #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
12833   {
12834     M32C_INSN_SBJNZ16_B_IMM4_16_16_DST16_16_16_AN_RELATIVE_QI, "sbjnz16.b-imm4-16-16-dst16-16-16-An-relative-QI", "sbjnz.b", 40,
12835     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12836   },
12837 /* sbjnz.b #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
12838   {
12839     M32C_INSN_SBJNZ16_B_IMM4_16_16_DST16_16_16_SB_RELATIVE_QI, "sbjnz16.b-imm4-16-16-dst16-16-16-SB-relative-QI", "sbjnz.b", 40,
12840     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12841   },
12842 /* sbjnz.b #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */
12843   {
12844     M32C_INSN_SBJNZ16_B_IMM4_16_16_DST16_16_16_ABSOLUTE_QI, "sbjnz16.b-imm4-16-16-dst16-16-16-absolute-QI", "sbjnz.b", 40,
12845     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12846   },
12847 /* sbjnz.b #${Imm-8-s4},$Dst16RnQI,${Lab-16-8} */
12848   {
12849     M32C_INSN_SBJNZ16_B_IMM4_BASIC_DST16_RN_DIRECT_QI, "sbjnz16.b-imm4-basic-dst16-Rn-direct-QI", "sbjnz.b", 24,
12850     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12851   },
12852 /* sbjnz.b #${Imm-8-s4},$Dst16AnQI,${Lab-16-8} */
12853   {
12854     M32C_INSN_SBJNZ16_B_IMM4_BASIC_DST16_AN_DIRECT_QI, "sbjnz16.b-imm4-basic-dst16-An-direct-QI", "sbjnz.b", 24,
12855     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12856   },
12857 /* sbjnz.b #${Imm-8-s4},[$Dst16An],${Lab-16-8} */
12858   {
12859     M32C_INSN_SBJNZ16_B_IMM4_BASIC_DST16_AN_INDIRECT_QI, "sbjnz16.b-imm4-basic-dst16-An-indirect-QI", "sbjnz.b", 24,
12860     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12861   },
12862 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
12863   {
12864     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 32,
12865     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12866   },
12867 /* sbb.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
12868   {
12869     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 32,
12870     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12871   },
12872 /* sbb.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
12873   {
12874     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 32,
12875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12876   },
12877 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
12878   {
12879     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 32,
12880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12881   },
12882 /* sbb.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
12883   {
12884     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 32,
12885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12886   },
12887 /* sbb.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
12888   {
12889     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 32,
12890     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12891   },
12892 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
12893   {
12894     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 32,
12895     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12896   },
12897 /* sbb.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
12898   {
12899     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 32,
12900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12901   },
12902 /* sbb.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
12903   {
12904     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 32,
12905     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12906   },
12907 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
12908   {
12909     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "sbb.w", 40,
12910     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12911   },
12912 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
12913   {
12914     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "sbb.w", 40,
12915     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12916   },
12917 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
12918   {
12919     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "sbb.w", 40,
12920     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12921   },
12922 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
12923   {
12924     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "sbb.w", 48,
12925     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12926   },
12927 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
12928   {
12929     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "sbb.w", 48,
12930     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12931   },
12932 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
12933   {
12934     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "sbb.w", 48,
12935     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12936   },
12937 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
12938   {
12939     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "sbb.w", 56,
12940     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12941   },
12942 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
12943   {
12944     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "sbb.w", 56,
12945     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12946   },
12947 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
12948   {
12949     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "sbb.w", 56,
12950     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12951   },
12952 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
12953   {
12954     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "sbb.w", 40,
12955     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12956   },
12957 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
12958   {
12959     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "sbb.w", 40,
12960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12961   },
12962 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
12963   {
12964     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "sbb.w", 40,
12965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12966   },
12967 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
12968   {
12969     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "sbb.w", 48,
12970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12971   },
12972 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
12973   {
12974     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "sbb.w", 48,
12975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12976   },
12977 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
12978   {
12979     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "sbb.w", 48,
12980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12981   },
12982 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
12983   {
12984     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "sbb.w", 40,
12985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12986   },
12987 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
12988   {
12989     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "sbb.w", 40,
12990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12991   },
12992 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
12993   {
12994     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "sbb.w", 40,
12995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12996   },
12997 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
12998   {
12999     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "sbb.w", 48,
13000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13001   },
13002 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
13003   {
13004     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "sbb.w", 48,
13005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13006   },
13007 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
13008   {
13009     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "sbb.w", 48,
13010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13011   },
13012 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
13013   {
13014     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "sbb.w", 48,
13015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13016   },
13017 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
13018   {
13019     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "sbb.w", 48,
13020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13021   },
13022 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
13023   {
13024     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "sbb.w", 48,
13025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13026   },
13027 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
13028   {
13029     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "sbb.w", 56,
13030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13031   },
13032 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
13033   {
13034     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "sbb.w", 56,
13035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13036   },
13037 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
13038   {
13039     M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "sbb.w", 56,
13040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13041   },
13042 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
13043   {
13044     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40,
13045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13046   },
13047 /* sbb.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
13048   {
13049     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40,
13050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13051   },
13052 /* sbb.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
13053   {
13054     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40,
13055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13056   },
13057 /* sbb.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
13058   {
13059     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40,
13060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13061   },
13062 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
13063   {
13064     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 40,
13065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13066   },
13067 /* sbb.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
13068   {
13069     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 40,
13070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13071   },
13072 /* sbb.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
13073   {
13074     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 40,
13075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13076   },
13077 /* sbb.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
13078   {
13079     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 40,
13080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13081   },
13082 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
13083   {
13084     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 40,
13085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13086   },
13087 /* sbb.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
13088   {
13089     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 40,
13090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13091   },
13092 /* sbb.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
13093   {
13094     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 40,
13095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13096   },
13097 /* sbb.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
13098   {
13099     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 40,
13100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13101   },
13102 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
13103   {
13104     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "sbb.w", 48,
13105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13106   },
13107 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
13108   {
13109     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "sbb.w", 48,
13110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13111   },
13112 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
13113   {
13114     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "sbb.w", 48,
13115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13116   },
13117 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
13118   {
13119     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "sbb.w", 48,
13120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13121   },
13122 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
13123   {
13124     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "sbb.w", 56,
13125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13126   },
13127 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
13128   {
13129     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "sbb.w", 56,
13130     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13131   },
13132 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
13133   {
13134     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "sbb.w", 56,
13135     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13136   },
13137 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
13138   {
13139     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "sbb.w", 56,
13140     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13141   },
13142 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
13143   {
13144     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "sbb.w", 64,
13145     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13146   },
13147 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
13148   {
13149     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "sbb.w", 64,
13150     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13151   },
13152 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
13153   {
13154     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "sbb.w", 64,
13155     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13156   },
13157 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
13158   {
13159     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "sbb.w", 64,
13160     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13161   },
13162 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
13163   {
13164     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "sbb.w", 48,
13165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13166   },
13167 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
13168   {
13169     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "sbb.w", 48,
13170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13171   },
13172 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
13173   {
13174     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "sbb.w", 48,
13175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13176   },
13177 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
13178   {
13179     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "sbb.w", 48,
13180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13181   },
13182 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
13183   {
13184     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "sbb.w", 56,
13185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13186   },
13187 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
13188   {
13189     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "sbb.w", 56,
13190     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13191   },
13192 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
13193   {
13194     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "sbb.w", 56,
13195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13196   },
13197 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
13198   {
13199     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "sbb.w", 56,
13200     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13201   },
13202 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
13203   {
13204     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "sbb.w", 48,
13205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13206   },
13207 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
13208   {
13209     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "sbb.w", 48,
13210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13211   },
13212 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
13213   {
13214     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "sbb.w", 48,
13215     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13216   },
13217 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
13218   {
13219     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "sbb.w", 48,
13220     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13221   },
13222 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
13223   {
13224     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "sbb.w", 56,
13225     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13226   },
13227 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
13228   {
13229     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "sbb.w", 56,
13230     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13231   },
13232 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
13233   {
13234     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "sbb.w", 56,
13235     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13236   },
13237 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
13238   {
13239     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "sbb.w", 56,
13240     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13241   },
13242 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
13243   {
13244     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "sbb.w", 56,
13245     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13246   },
13247 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
13248   {
13249     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "sbb.w", 56,
13250     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13251   },
13252 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
13253   {
13254     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "sbb.w", 56,
13255     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13256   },
13257 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
13258   {
13259     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "sbb.w", 56,
13260     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13261   },
13262 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
13263   {
13264     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "sbb.w", 64,
13265     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13266   },
13267 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
13268   {
13269     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "sbb.w", 64,
13270     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13271   },
13272 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
13273   {
13274     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "sbb.w", 64,
13275     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13276   },
13277 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
13278   {
13279     M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "sbb.w", 64,
13280     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13281   },
13282 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
13283   {
13284     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 48,
13285     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13286   },
13287 /* sbb.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
13288   {
13289     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 48,
13290     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13291   },
13292 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
13293   {
13294     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 48,
13295     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13296   },
13297 /* sbb.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
13298   {
13299     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 48,
13300     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13301   },
13302 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
13303   {
13304     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 48,
13305     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13306   },
13307 /* sbb.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
13308   {
13309     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 48,
13310     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13311   },
13312 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
13313   {
13314     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "sbb.w", 56,
13315     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13316   },
13317 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
13318   {
13319     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "sbb.w", 56,
13320     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13321   },
13322 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
13323   {
13324     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "sbb.w", 64,
13325     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13326   },
13327 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
13328   {
13329     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "sbb.w", 64,
13330     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13331   },
13332 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
13333   {
13334     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "sbb.w", 72,
13335     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13336   },
13337 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
13338   {
13339     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "sbb.w", 72,
13340     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13341   },
13342 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
13343   {
13344     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "sbb.w", 56,
13345     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13346   },
13347 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
13348   {
13349     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "sbb.w", 56,
13350     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13351   },
13352 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
13353   {
13354     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "sbb.w", 64,
13355     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13356   },
13357 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
13358   {
13359     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "sbb.w", 64,
13360     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13361   },
13362 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
13363   {
13364     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "sbb.w", 56,
13365     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13366   },
13367 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
13368   {
13369     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "sbb.w", 56,
13370     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13371   },
13372 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
13373   {
13374     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "sbb.w", 64,
13375     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13376   },
13377 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
13378   {
13379     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "sbb.w", 64,
13380     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13381   },
13382 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
13383   {
13384     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "sbb.w", 64,
13385     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13386   },
13387 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
13388   {
13389     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "sbb.w", 64,
13390     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13391   },
13392 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
13393   {
13394     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "sbb.w", 72,
13395     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13396   },
13397 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
13398   {
13399     M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "sbb.w", 72,
13400     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13401   },
13402 /* sbb.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
13403   {
13404     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 24,
13405     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13406   },
13407 /* sbb.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
13408   {
13409     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 24,
13410     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13411   },
13412 /* sbb.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
13413   {
13414     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 24,
13415     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13416   },
13417 /* sbb.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
13418   {
13419     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 24,
13420     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13421   },
13422 /* sbb.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
13423   {
13424     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 24,
13425     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13426   },
13427 /* sbb.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
13428   {
13429     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 24,
13430     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13431   },
13432 /* sbb.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
13433   {
13434     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 24,
13435     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13436   },
13437 /* sbb.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
13438   {
13439     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 24,
13440     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13441   },
13442 /* sbb.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
13443   {
13444     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 24,
13445     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13446   },
13447 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
13448   {
13449     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "sbb.w", 32,
13450     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13451   },
13452 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
13453   {
13454     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "sbb.w", 32,
13455     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13456   },
13457 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
13458   {
13459     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "sbb.w", 32,
13460     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13461   },
13462 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
13463   {
13464     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "sbb.w", 40,
13465     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13466   },
13467 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
13468   {
13469     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "sbb.w", 40,
13470     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13471   },
13472 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
13473   {
13474     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "sbb.w", 40,
13475     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13476   },
13477 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
13478   {
13479     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "sbb.w", 48,
13480     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13481   },
13482 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
13483   {
13484     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "sbb.w", 48,
13485     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13486   },
13487 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
13488   {
13489     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "sbb.w", 48,
13490     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13491   },
13492 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
13493   {
13494     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "sbb.w", 32,
13495     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13496   },
13497 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
13498   {
13499     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "sbb.w", 32,
13500     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13501   },
13502 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
13503   {
13504     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "sbb.w", 32,
13505     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13506   },
13507 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
13508   {
13509     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "sbb.w", 40,
13510     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13511   },
13512 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
13513   {
13514     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "sbb.w", 40,
13515     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13516   },
13517 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
13518   {
13519     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "sbb.w", 40,
13520     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13521   },
13522 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
13523   {
13524     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "sbb.w", 32,
13525     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13526   },
13527 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
13528   {
13529     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "sbb.w", 32,
13530     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13531   },
13532 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
13533   {
13534     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "sbb.w", 32,
13535     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13536   },
13537 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
13538   {
13539     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "sbb.w", 40,
13540     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13541   },
13542 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
13543   {
13544     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "sbb.w", 40,
13545     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13546   },
13547 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
13548   {
13549     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "sbb.w", 40,
13550     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13551   },
13552 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
13553   {
13554     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "sbb.w", 40,
13555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13556   },
13557 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
13558   {
13559     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "sbb.w", 40,
13560     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13561   },
13562 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
13563   {
13564     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "sbb.w", 40,
13565     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13566   },
13567 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
13568   {
13569     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "sbb.w", 48,
13570     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13571   },
13572 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
13573   {
13574     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "sbb.w", 48,
13575     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13576   },
13577 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
13578   {
13579     M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "sbb.w", 48,
13580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13581   },
13582 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
13583   {
13584     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 32,
13585     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13586   },
13587 /* sbb.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
13588   {
13589     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 32,
13590     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13591   },
13592 /* sbb.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
13593   {
13594     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 32,
13595     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13596   },
13597 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
13598   {
13599     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 32,
13600     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13601   },
13602 /* sbb.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
13603   {
13604     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 32,
13605     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13606   },
13607 /* sbb.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
13608   {
13609     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 32,
13610     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13611   },
13612 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
13613   {
13614     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 32,
13615     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13616   },
13617 /* sbb.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
13618   {
13619     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 32,
13620     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13621   },
13622 /* sbb.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
13623   {
13624     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 32,
13625     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13626   },
13627 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
13628   {
13629     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "sbb.b", 40,
13630     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13631   },
13632 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
13633   {
13634     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "sbb.b", 40,
13635     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13636   },
13637 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
13638   {
13639     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "sbb.b", 40,
13640     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13641   },
13642 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
13643   {
13644     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "sbb.b", 48,
13645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13646   },
13647 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
13648   {
13649     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "sbb.b", 48,
13650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13651   },
13652 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
13653   {
13654     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "sbb.b", 48,
13655     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13656   },
13657 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
13658   {
13659     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "sbb.b", 56,
13660     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13661   },
13662 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
13663   {
13664     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "sbb.b", 56,
13665     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13666   },
13667 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
13668   {
13669     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "sbb.b", 56,
13670     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13671   },
13672 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
13673   {
13674     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "sbb.b", 40,
13675     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13676   },
13677 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
13678   {
13679     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "sbb.b", 40,
13680     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13681   },
13682 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
13683   {
13684     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "sbb.b", 40,
13685     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13686   },
13687 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
13688   {
13689     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "sbb.b", 48,
13690     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13691   },
13692 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
13693   {
13694     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "sbb.b", 48,
13695     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13696   },
13697 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
13698   {
13699     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "sbb.b", 48,
13700     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13701   },
13702 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
13703   {
13704     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "sbb.b", 40,
13705     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13706   },
13707 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
13708   {
13709     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "sbb.b", 40,
13710     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13711   },
13712 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
13713   {
13714     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "sbb.b", 40,
13715     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13716   },
13717 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
13718   {
13719     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "sbb.b", 48,
13720     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13721   },
13722 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
13723   {
13724     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "sbb.b", 48,
13725     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13726   },
13727 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
13728   {
13729     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "sbb.b", 48,
13730     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13731   },
13732 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
13733   {
13734     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "sbb.b", 48,
13735     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13736   },
13737 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
13738   {
13739     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "sbb.b", 48,
13740     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13741   },
13742 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
13743   {
13744     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "sbb.b", 48,
13745     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13746   },
13747 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
13748   {
13749     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "sbb.b", 56,
13750     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13751   },
13752 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
13753   {
13754     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "sbb.b", 56,
13755     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13756   },
13757 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
13758   {
13759     M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "sbb.b", 56,
13760     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13761   },
13762 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
13763   {
13764     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 40,
13765     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13766   },
13767 /* sbb.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
13768   {
13769     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 40,
13770     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13771   },
13772 /* sbb.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
13773   {
13774     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 40,
13775     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13776   },
13777 /* sbb.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
13778   {
13779     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 40,
13780     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13781   },
13782 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
13783   {
13784     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 40,
13785     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13786   },
13787 /* sbb.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
13788   {
13789     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 40,
13790     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13791   },
13792 /* sbb.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
13793   {
13794     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 40,
13795     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13796   },
13797 /* sbb.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
13798   {
13799     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 40,
13800     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13801   },
13802 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
13803   {
13804     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 40,
13805     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13806   },
13807 /* sbb.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
13808   {
13809     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 40,
13810     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13811   },
13812 /* sbb.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
13813   {
13814     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 40,
13815     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13816   },
13817 /* sbb.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
13818   {
13819     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 40,
13820     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13821   },
13822 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
13823   {
13824     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "sbb.b", 48,
13825     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13826   },
13827 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
13828   {
13829     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "sbb.b", 48,
13830     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13831   },
13832 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
13833   {
13834     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "sbb.b", 48,
13835     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13836   },
13837 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
13838   {
13839     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "sbb.b", 48,
13840     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13841   },
13842 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
13843   {
13844     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "sbb.b", 56,
13845     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13846   },
13847 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
13848   {
13849     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "sbb.b", 56,
13850     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13851   },
13852 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
13853   {
13854     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "sbb.b", 56,
13855     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13856   },
13857 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
13858   {
13859     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "sbb.b", 56,
13860     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13861   },
13862 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
13863   {
13864     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "sbb.b", 64,
13865     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13866   },
13867 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
13868   {
13869     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "sbb.b", 64,
13870     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13871   },
13872 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
13873   {
13874     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "sbb.b", 64,
13875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13876   },
13877 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
13878   {
13879     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "sbb.b", 64,
13880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13881   },
13882 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
13883   {
13884     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "sbb.b", 48,
13885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13886   },
13887 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
13888   {
13889     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "sbb.b", 48,
13890     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13891   },
13892 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
13893   {
13894     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "sbb.b", 48,
13895     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13896   },
13897 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
13898   {
13899     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "sbb.b", 48,
13900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13901   },
13902 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
13903   {
13904     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "sbb.b", 56,
13905     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13906   },
13907 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
13908   {
13909     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "sbb.b", 56,
13910     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13911   },
13912 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
13913   {
13914     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "sbb.b", 56,
13915     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13916   },
13917 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
13918   {
13919     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "sbb.b", 56,
13920     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13921   },
13922 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
13923   {
13924     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "sbb.b", 48,
13925     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13926   },
13927 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
13928   {
13929     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "sbb.b", 48,
13930     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13931   },
13932 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
13933   {
13934     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "sbb.b", 48,
13935     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13936   },
13937 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
13938   {
13939     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "sbb.b", 48,
13940     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13941   },
13942 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
13943   {
13944     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "sbb.b", 56,
13945     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13946   },
13947 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
13948   {
13949     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "sbb.b", 56,
13950     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13951   },
13952 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
13953   {
13954     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "sbb.b", 56,
13955     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13956   },
13957 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
13958   {
13959     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "sbb.b", 56,
13960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13961   },
13962 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
13963   {
13964     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "sbb.b", 56,
13965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13966   },
13967 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
13968   {
13969     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "sbb.b", 56,
13970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13971   },
13972 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
13973   {
13974     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "sbb.b", 56,
13975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13976   },
13977 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
13978   {
13979     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "sbb.b", 56,
13980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13981   },
13982 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
13983   {
13984     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "sbb.b", 64,
13985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13986   },
13987 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
13988   {
13989     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "sbb.b", 64,
13990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13991   },
13992 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
13993   {
13994     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "sbb.b", 64,
13995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13996   },
13997 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
13998   {
13999     M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "sbb.b", 64,
14000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14001   },
14002 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
14003   {
14004     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 48,
14005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14006   },
14007 /* sbb.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
14008   {
14009     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 48,
14010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14011   },
14012 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
14013   {
14014     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 48,
14015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14016   },
14017 /* sbb.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
14018   {
14019     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 48,
14020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14021   },
14022 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
14023   {
14024     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 48,
14025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14026   },
14027 /* sbb.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
14028   {
14029     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 48,
14030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14031   },
14032 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
14033   {
14034     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "sbb.b", 56,
14035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14036   },
14037 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
14038   {
14039     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "sbb.b", 56,
14040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14041   },
14042 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
14043   {
14044     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "sbb.b", 64,
14045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14046   },
14047 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
14048   {
14049     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "sbb.b", 64,
14050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14051   },
14052 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
14053   {
14054     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "sbb.b", 72,
14055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14056   },
14057 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
14058   {
14059     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "sbb.b", 72,
14060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14061   },
14062 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
14063   {
14064     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "sbb.b", 56,
14065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14066   },
14067 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
14068   {
14069     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "sbb.b", 56,
14070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14071   },
14072 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
14073   {
14074     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "sbb.b", 64,
14075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14076   },
14077 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
14078   {
14079     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "sbb.b", 64,
14080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14081   },
14082 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
14083   {
14084     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "sbb.b", 56,
14085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14086   },
14087 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
14088   {
14089     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "sbb.b", 56,
14090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14091   },
14092 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
14093   {
14094     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "sbb.b", 64,
14095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14096   },
14097 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
14098   {
14099     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "sbb.b", 64,
14100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14101   },
14102 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
14103   {
14104     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "sbb.b", 64,
14105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14106   },
14107 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
14108   {
14109     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "sbb.b", 64,
14110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14111   },
14112 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
14113   {
14114     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "sbb.b", 72,
14115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14116   },
14117 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
14118   {
14119     M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "sbb.b", 72,
14120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14121   },
14122 /* sbb.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
14123   {
14124     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 24,
14125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14126   },
14127 /* sbb.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
14128   {
14129     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 24,
14130     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14131   },
14132 /* sbb.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
14133   {
14134     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 24,
14135     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14136   },
14137 /* sbb.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
14138   {
14139     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 24,
14140     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14141   },
14142 /* sbb.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
14143   {
14144     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 24,
14145     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14146   },
14147 /* sbb.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
14148   {
14149     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 24,
14150     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14151   },
14152 /* sbb.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
14153   {
14154     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 24,
14155     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14156   },
14157 /* sbb.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
14158   {
14159     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 24,
14160     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14161   },
14162 /* sbb.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
14163   {
14164     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 24,
14165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14166   },
14167 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
14168   {
14169     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "sbb.b", 32,
14170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14171   },
14172 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
14173   {
14174     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "sbb.b", 32,
14175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14176   },
14177 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
14178   {
14179     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "sbb.b", 32,
14180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14181   },
14182 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
14183   {
14184     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "sbb.b", 40,
14185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14186   },
14187 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
14188   {
14189     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "sbb.b", 40,
14190     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14191   },
14192 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
14193   {
14194     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "sbb.b", 40,
14195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14196   },
14197 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
14198   {
14199     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "sbb.b", 48,
14200     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14201   },
14202 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
14203   {
14204     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "sbb.b", 48,
14205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14206   },
14207 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
14208   {
14209     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "sbb.b", 48,
14210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14211   },
14212 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
14213   {
14214     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "sbb.b", 32,
14215     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14216   },
14217 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
14218   {
14219     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "sbb.b", 32,
14220     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14221   },
14222 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
14223   {
14224     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "sbb.b", 32,
14225     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14226   },
14227 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
14228   {
14229     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "sbb.b", 40,
14230     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14231   },
14232 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
14233   {
14234     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "sbb.b", 40,
14235     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14236   },
14237 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
14238   {
14239     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "sbb.b", 40,
14240     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14241   },
14242 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
14243   {
14244     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "sbb.b", 32,
14245     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14246   },
14247 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
14248   {
14249     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "sbb.b", 32,
14250     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14251   },
14252 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
14253   {
14254     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "sbb.b", 32,
14255     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14256   },
14257 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
14258   {
14259     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "sbb.b", 40,
14260     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14261   },
14262 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
14263   {
14264     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "sbb.b", 40,
14265     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14266   },
14267 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
14268   {
14269     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "sbb.b", 40,
14270     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14271   },
14272 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
14273   {
14274     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "sbb.b", 40,
14275     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14276   },
14277 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
14278   {
14279     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "sbb.b", 40,
14280     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14281   },
14282 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
14283   {
14284     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "sbb.b", 40,
14285     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14286   },
14287 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
14288   {
14289     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "sbb.b", 48,
14290     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14291   },
14292 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
14293   {
14294     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "sbb.b", 48,
14295     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14296   },
14297 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
14298   {
14299     M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "sbb.b", 48,
14300     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14301   },
14302 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
14303   {
14304     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "sbb.w", 24,
14305     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14306   },
14307 /* sbb.w${X} ${Dsp-16-u8}[sb],$Dst16RnHI */
14308   {
14309     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "sbb.w", 24,
14310     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14311   },
14312 /* sbb.w${X} ${Dsp-16-s8}[fb],$Dst16RnHI */
14313   {
14314     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "sbb.w", 24,
14315     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14316   },
14317 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
14318   {
14319     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "sbb.w", 24,
14320     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14321   },
14322 /* sbb.w${X} ${Dsp-16-u8}[sb],$Dst16AnHI */
14323   {
14324     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "sbb.w", 24,
14325     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14326   },
14327 /* sbb.w${X} ${Dsp-16-s8}[fb],$Dst16AnHI */
14328   {
14329     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "sbb.w", 24,
14330     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14331   },
14332 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
14333   {
14334     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "sbb.w", 24,
14335     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14336   },
14337 /* sbb.w${X} ${Dsp-16-u8}[sb],[$Dst16An] */
14338   {
14339     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "sbb.w", 24,
14340     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14341   },
14342 /* sbb.w${X} ${Dsp-16-s8}[fb],[$Dst16An] */
14343   {
14344     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "sbb.w", 24,
14345     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14346   },
14347 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
14348   {
14349     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "sbb.w", 32,
14350     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14351   },
14352 /* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
14353   {
14354     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "sbb.w", 32,
14355     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14356   },
14357 /* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
14358   {
14359     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "sbb.w", 32,
14360     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14361   },
14362 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
14363   {
14364     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "sbb.w", 40,
14365     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14366   },
14367 /* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
14368   {
14369     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "sbb.w", 40,
14370     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14371   },
14372 /* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
14373   {
14374     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "sbb.w", 40,
14375     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14376   },
14377 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
14378   {
14379     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "sbb.w", 32,
14380     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14381   },
14382 /* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
14383   {
14384     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "sbb.w", 32,
14385     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14386   },
14387 /* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
14388   {
14389     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "sbb.w", 32,
14390     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14391   },
14392 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
14393   {
14394     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "sbb.w", 40,
14395     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14396   },
14397 /* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
14398   {
14399     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "sbb.w", 40,
14400     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14401   },
14402 /* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
14403   {
14404     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "sbb.w", 40,
14405     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14406   },
14407 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
14408   {
14409     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "sbb.w", 32,
14410     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14411   },
14412 /* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
14413   {
14414     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "sbb.w", 32,
14415     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14416   },
14417 /* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
14418   {
14419     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "sbb.w", 32,
14420     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14421   },
14422 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
14423   {
14424     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "sbb.w", 40,
14425     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14426   },
14427 /* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
14428   {
14429     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "sbb.w", 40,
14430     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14431   },
14432 /* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
14433   {
14434     M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "sbb.w", 40,
14435     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14436   },
14437 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
14438   {
14439     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "sbb.w", 32,
14440     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14441   },
14442 /* sbb.w${X} ${Dsp-16-u16}[sb],$Dst16RnHI */
14443   {
14444     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "sbb.w", 32,
14445     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14446   },
14447 /* sbb.w${X} ${Dsp-16-u16},$Dst16RnHI */
14448   {
14449     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "sbb.w", 32,
14450     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14451   },
14452 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
14453   {
14454     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "sbb.w", 32,
14455     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14456   },
14457 /* sbb.w${X} ${Dsp-16-u16}[sb],$Dst16AnHI */
14458   {
14459     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "sbb.w", 32,
14460     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14461   },
14462 /* sbb.w${X} ${Dsp-16-u16},$Dst16AnHI */
14463   {
14464     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "sbb.w", 32,
14465     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14466   },
14467 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
14468   {
14469     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "sbb.w", 32,
14470     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14471   },
14472 /* sbb.w${X} ${Dsp-16-u16}[sb],[$Dst16An] */
14473   {
14474     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "sbb.w", 32,
14475     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14476   },
14477 /* sbb.w${X} ${Dsp-16-u16},[$Dst16An] */
14478   {
14479     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "sbb.w", 32,
14480     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14481   },
14482 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
14483   {
14484     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "sbb.w", 40,
14485     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14486   },
14487 /* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
14488   {
14489     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "sbb.w", 40,
14490     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14491   },
14492 /* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
14493   {
14494     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "sbb.w", 40,
14495     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14496   },
14497 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
14498   {
14499     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "sbb.w", 48,
14500     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14501   },
14502 /* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
14503   {
14504     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "sbb.w", 48,
14505     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14506   },
14507 /* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
14508   {
14509     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "sbb.w", 48,
14510     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14511   },
14512 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
14513   {
14514     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "sbb.w", 40,
14515     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14516   },
14517 /* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
14518   {
14519     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "sbb.w", 40,
14520     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14521   },
14522 /* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
14523   {
14524     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "sbb.w", 40,
14525     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14526   },
14527 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
14528   {
14529     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "sbb.w", 48,
14530     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14531   },
14532 /* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
14533   {
14534     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "sbb.w", 48,
14535     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14536   },
14537 /* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
14538   {
14539     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "sbb.w", 48,
14540     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14541   },
14542 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
14543   {
14544     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "sbb.w", 40,
14545     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14546   },
14547 /* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
14548   {
14549     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "sbb.w", 40,
14550     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14551   },
14552 /* sbb.w${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
14553   {
14554     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "sbb.w", 40,
14555     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14556   },
14557 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
14558   {
14559     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "sbb.w", 48,
14560     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14561   },
14562 /* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
14563   {
14564     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "sbb.w", 48,
14565     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14566   },
14567 /* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u16} */
14568   {
14569     M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "sbb.w", 48,
14570     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14571   },
14572 /* sbb.w${X} $Src16RnHI,$Dst16RnHI */
14573   {
14574     M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "sbb.w", 16,
14575     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14576   },
14577 /* sbb.w${X} $Src16AnHI,$Dst16RnHI */
14578   {
14579     M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "sbb.w", 16,
14580     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14581   },
14582 /* sbb.w${X} [$Src16An],$Dst16RnHI */
14583   {
14584     M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "sbb.w", 16,
14585     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14586   },
14587 /* sbb.w${X} $Src16RnHI,$Dst16AnHI */
14588   {
14589     M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "sbb.w", 16,
14590     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14591   },
14592 /* sbb.w${X} $Src16AnHI,$Dst16AnHI */
14593   {
14594     M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "sbb.w", 16,
14595     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14596   },
14597 /* sbb.w${X} [$Src16An],$Dst16AnHI */
14598   {
14599     M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "sbb.w", 16,
14600     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14601   },
14602 /* sbb.w${X} $Src16RnHI,[$Dst16An] */
14603   {
14604     M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "sbb.w", 16,
14605     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14606   },
14607 /* sbb.w${X} $Src16AnHI,[$Dst16An] */
14608   {
14609     M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "sbb.w", 16,
14610     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14611   },
14612 /* sbb.w${X} [$Src16An],[$Dst16An] */
14613   {
14614     M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "sbb.w", 16,
14615     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14616   },
14617 /* sbb.w${X} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
14618   {
14619     M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "sbb.w", 24,
14620     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14621   },
14622 /* sbb.w${X} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
14623   {
14624     M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "sbb.w", 24,
14625     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14626   },
14627 /* sbb.w${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
14628   {
14629     M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "sbb.w", 24,
14630     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14631   },
14632 /* sbb.w${X} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
14633   {
14634     M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "sbb.w", 32,
14635     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14636   },
14637 /* sbb.w${X} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
14638   {
14639     M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "sbb.w", 32,
14640     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14641   },
14642 /* sbb.w${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
14643   {
14644     M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "sbb.w", 32,
14645     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14646   },
14647 /* sbb.w${X} $Src16RnHI,${Dsp-16-u8}[sb] */
14648   {
14649     M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "sbb.w", 24,
14650     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14651   },
14652 /* sbb.w${X} $Src16AnHI,${Dsp-16-u8}[sb] */
14653   {
14654     M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "sbb.w", 24,
14655     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14656   },
14657 /* sbb.w${X} [$Src16An],${Dsp-16-u8}[sb] */
14658   {
14659     M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "sbb.w", 24,
14660     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14661   },
14662 /* sbb.w${X} $Src16RnHI,${Dsp-16-u16}[sb] */
14663   {
14664     M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "sbb.w", 32,
14665     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14666   },
14667 /* sbb.w${X} $Src16AnHI,${Dsp-16-u16}[sb] */
14668   {
14669     M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "sbb.w", 32,
14670     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14671   },
14672 /* sbb.w${X} [$Src16An],${Dsp-16-u16}[sb] */
14673   {
14674     M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "sbb.w", 32,
14675     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14676   },
14677 /* sbb.w${X} $Src16RnHI,${Dsp-16-s8}[fb] */
14678   {
14679     M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "sbb.w", 24,
14680     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14681   },
14682 /* sbb.w${X} $Src16AnHI,${Dsp-16-s8}[fb] */
14683   {
14684     M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "sbb.w", 24,
14685     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14686   },
14687 /* sbb.w${X} [$Src16An],${Dsp-16-s8}[fb] */
14688   {
14689     M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "sbb.w", 24,
14690     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14691   },
14692 /* sbb.w${X} $Src16RnHI,${Dsp-16-u16} */
14693   {
14694     M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "sbb.w", 32,
14695     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14696   },
14697 /* sbb.w${X} $Src16AnHI,${Dsp-16-u16} */
14698   {
14699     M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "sbb.w", 32,
14700     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14701   },
14702 /* sbb.w${X} [$Src16An],${Dsp-16-u16} */
14703   {
14704     M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "sbb.w", 32,
14705     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14706   },
14707 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
14708   {
14709     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "sbb.b", 24,
14710     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14711   },
14712 /* sbb.b${X} ${Dsp-16-u8}[sb],$Dst16RnQI */
14713   {
14714     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "sbb.b", 24,
14715     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14716   },
14717 /* sbb.b${X} ${Dsp-16-s8}[fb],$Dst16RnQI */
14718   {
14719     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "sbb.b", 24,
14720     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14721   },
14722 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
14723   {
14724     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "sbb.b", 24,
14725     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14726   },
14727 /* sbb.b${X} ${Dsp-16-u8}[sb],$Dst16AnQI */
14728   {
14729     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "sbb.b", 24,
14730     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14731   },
14732 /* sbb.b${X} ${Dsp-16-s8}[fb],$Dst16AnQI */
14733   {
14734     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "sbb.b", 24,
14735     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14736   },
14737 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
14738   {
14739     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "sbb.b", 24,
14740     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14741   },
14742 /* sbb.b${X} ${Dsp-16-u8}[sb],[$Dst16An] */
14743   {
14744     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "sbb.b", 24,
14745     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14746   },
14747 /* sbb.b${X} ${Dsp-16-s8}[fb],[$Dst16An] */
14748   {
14749     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "sbb.b", 24,
14750     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14751   },
14752 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
14753   {
14754     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "sbb.b", 32,
14755     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14756   },
14757 /* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
14758   {
14759     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "sbb.b", 32,
14760     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14761   },
14762 /* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
14763   {
14764     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "sbb.b", 32,
14765     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14766   },
14767 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
14768   {
14769     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "sbb.b", 40,
14770     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14771   },
14772 /* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
14773   {
14774     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "sbb.b", 40,
14775     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14776   },
14777 /* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
14778   {
14779     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "sbb.b", 40,
14780     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14781   },
14782 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
14783   {
14784     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "sbb.b", 32,
14785     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14786   },
14787 /* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
14788   {
14789     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "sbb.b", 32,
14790     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14791   },
14792 /* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
14793   {
14794     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "sbb.b", 32,
14795     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14796   },
14797 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
14798   {
14799     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "sbb.b", 40,
14800     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14801   },
14802 /* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
14803   {
14804     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "sbb.b", 40,
14805     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14806   },
14807 /* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
14808   {
14809     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "sbb.b", 40,
14810     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14811   },
14812 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
14813   {
14814     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "sbb.b", 32,
14815     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14816   },
14817 /* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
14818   {
14819     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "sbb.b", 32,
14820     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14821   },
14822 /* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
14823   {
14824     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "sbb.b", 32,
14825     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14826   },
14827 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
14828   {
14829     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "sbb.b", 40,
14830     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14831   },
14832 /* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
14833   {
14834     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "sbb.b", 40,
14835     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14836   },
14837 /* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
14838   {
14839     M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "sbb.b", 40,
14840     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14841   },
14842 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
14843   {
14844     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "sbb.b", 32,
14845     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14846   },
14847 /* sbb.b${X} ${Dsp-16-u16}[sb],$Dst16RnQI */
14848   {
14849     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "sbb.b", 32,
14850     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14851   },
14852 /* sbb.b${X} ${Dsp-16-u16},$Dst16RnQI */
14853   {
14854     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "sbb.b", 32,
14855     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14856   },
14857 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
14858   {
14859     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "sbb.b", 32,
14860     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14861   },
14862 /* sbb.b${X} ${Dsp-16-u16}[sb],$Dst16AnQI */
14863   {
14864     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "sbb.b", 32,
14865     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14866   },
14867 /* sbb.b${X} ${Dsp-16-u16},$Dst16AnQI */
14868   {
14869     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "sbb.b", 32,
14870     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14871   },
14872 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
14873   {
14874     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "sbb.b", 32,
14875     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14876   },
14877 /* sbb.b${X} ${Dsp-16-u16}[sb],[$Dst16An] */
14878   {
14879     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "sbb.b", 32,
14880     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14881   },
14882 /* sbb.b${X} ${Dsp-16-u16},[$Dst16An] */
14883   {
14884     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "sbb.b", 32,
14885     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14886   },
14887 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
14888   {
14889     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "sbb.b", 40,
14890     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14891   },
14892 /* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
14893   {
14894     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "sbb.b", 40,
14895     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14896   },
14897 /* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
14898   {
14899     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "sbb.b", 40,
14900     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14901   },
14902 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
14903   {
14904     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "sbb.b", 48,
14905     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14906   },
14907 /* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
14908   {
14909     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "sbb.b", 48,
14910     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14911   },
14912 /* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
14913   {
14914     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "sbb.b", 48,
14915     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14916   },
14917 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
14918   {
14919     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "sbb.b", 40,
14920     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14921   },
14922 /* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
14923   {
14924     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "sbb.b", 40,
14925     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14926   },
14927 /* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
14928   {
14929     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "sbb.b", 40,
14930     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14931   },
14932 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
14933   {
14934     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "sbb.b", 48,
14935     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14936   },
14937 /* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
14938   {
14939     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "sbb.b", 48,
14940     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14941   },
14942 /* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
14943   {
14944     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "sbb.b", 48,
14945     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14946   },
14947 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
14948   {
14949     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "sbb.b", 40,
14950     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14951   },
14952 /* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
14953   {
14954     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "sbb.b", 40,
14955     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14956   },
14957 /* sbb.b${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
14958   {
14959     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "sbb.b", 40,
14960     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14961   },
14962 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
14963   {
14964     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "sbb.b", 48,
14965     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14966   },
14967 /* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
14968   {
14969     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "sbb.b", 48,
14970     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14971   },
14972 /* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u16} */
14973   {
14974     M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "sbb.b", 48,
14975     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14976   },
14977 /* sbb.b${X} $Src16RnQI,$Dst16RnQI */
14978   {
14979     M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "sbb.b", 16,
14980     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14981   },
14982 /* sbb.b${X} $Src16AnQI,$Dst16RnQI */
14983   {
14984     M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "sbb.b", 16,
14985     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14986   },
14987 /* sbb.b${X} [$Src16An],$Dst16RnQI */
14988   {
14989     M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "sbb.b", 16,
14990     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14991   },
14992 /* sbb.b${X} $Src16RnQI,$Dst16AnQI */
14993   {
14994     M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "sbb.b", 16,
14995     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14996   },
14997 /* sbb.b${X} $Src16AnQI,$Dst16AnQI */
14998   {
14999     M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "sbb.b", 16,
15000     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15001   },
15002 /* sbb.b${X} [$Src16An],$Dst16AnQI */
15003   {
15004     M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "sbb.b", 16,
15005     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15006   },
15007 /* sbb.b${X} $Src16RnQI,[$Dst16An] */
15008   {
15009     M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "sbb.b", 16,
15010     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15011   },
15012 /* sbb.b${X} $Src16AnQI,[$Dst16An] */
15013   {
15014     M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "sbb.b", 16,
15015     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15016   },
15017 /* sbb.b${X} [$Src16An],[$Dst16An] */
15018   {
15019     M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "sbb.b", 16,
15020     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15021   },
15022 /* sbb.b${X} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
15023   {
15024     M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "sbb.b", 24,
15025     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15026   },
15027 /* sbb.b${X} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
15028   {
15029     M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "sbb.b", 24,
15030     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15031   },
15032 /* sbb.b${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
15033   {
15034     M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "sbb.b", 24,
15035     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15036   },
15037 /* sbb.b${X} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
15038   {
15039     M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "sbb.b", 32,
15040     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15041   },
15042 /* sbb.b${X} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
15043   {
15044     M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "sbb.b", 32,
15045     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15046   },
15047 /* sbb.b${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
15048   {
15049     M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "sbb.b", 32,
15050     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15051   },
15052 /* sbb.b${X} $Src16RnQI,${Dsp-16-u8}[sb] */
15053   {
15054     M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "sbb.b", 24,
15055     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15056   },
15057 /* sbb.b${X} $Src16AnQI,${Dsp-16-u8}[sb] */
15058   {
15059     M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "sbb.b", 24,
15060     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15061   },
15062 /* sbb.b${X} [$Src16An],${Dsp-16-u8}[sb] */
15063   {
15064     M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "sbb.b", 24,
15065     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15066   },
15067 /* sbb.b${X} $Src16RnQI,${Dsp-16-u16}[sb] */
15068   {
15069     M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "sbb.b", 32,
15070     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15071   },
15072 /* sbb.b${X} $Src16AnQI,${Dsp-16-u16}[sb] */
15073   {
15074     M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "sbb.b", 32,
15075     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15076   },
15077 /* sbb.b${X} [$Src16An],${Dsp-16-u16}[sb] */
15078   {
15079     M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "sbb.b", 32,
15080     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15081   },
15082 /* sbb.b${X} $Src16RnQI,${Dsp-16-s8}[fb] */
15083   {
15084     M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "sbb.b", 24,
15085     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15086   },
15087 /* sbb.b${X} $Src16AnQI,${Dsp-16-s8}[fb] */
15088   {
15089     M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "sbb.b", 24,
15090     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15091   },
15092 /* sbb.b${X} [$Src16An],${Dsp-16-s8}[fb] */
15093   {
15094     M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "sbb.b", 24,
15095     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15096   },
15097 /* sbb.b${X} $Src16RnQI,${Dsp-16-u16} */
15098   {
15099     M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "sbb.b", 32,
15100     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15101   },
15102 /* sbb.b${X} $Src16AnQI,${Dsp-16-u16} */
15103   {
15104     M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "sbb.b", 32,
15105     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15106   },
15107 /* sbb.b${X} [$Src16An],${Dsp-16-u16} */
15108   {
15109     M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "sbb.b", 32,
15110     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15111   },
15112 /* sbb.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
15113   {
15114     M32C_INSN_SBB32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40,
15115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15116   },
15117 /* sbb.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
15118   {
15119     M32C_INSN_SBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "sbb.w", 40,
15120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15121   },
15122 /* sbb.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
15123   {
15124     M32C_INSN_SBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "sbb.w", 40,
15125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15126   },
15127 /* sbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
15128   {
15129     M32C_INSN_SBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "sbb.w", 48,
15130     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15131   },
15132 /* sbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
15133   {
15134     M32C_INSN_SBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "sbb.w", 48,
15135     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15136   },
15137 /* sbb.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
15138   {
15139     M32C_INSN_SBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "sbb.w", 48,
15140     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15141   },
15142 /* sbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
15143   {
15144     M32C_INSN_SBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "sbb.w", 56,
15145     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15146   },
15147 /* sbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
15148   {
15149     M32C_INSN_SBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "sbb.w", 56,
15150     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15151   },
15152 /* sbb.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
15153   {
15154     M32C_INSN_SBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "sbb.w", 56,
15155     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15156   },
15157 /* sbb.w${X} #${Imm-40-HI},${Dsp-24-u16} */
15158   {
15159     M32C_INSN_SBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "sbb.w", 56,
15160     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15161   },
15162 /* sbb.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
15163   {
15164     M32C_INSN_SBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "sbb.w", 64,
15165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15166   },
15167 /* sbb.w${X} #${Imm-48-HI},${Dsp-24-u24} */
15168   {
15169     M32C_INSN_SBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "sbb.w", 64,
15170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15171   },
15172 /* sbb.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
15173   {
15174     M32C_INSN_SBB32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "sbb.b", 32,
15175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15176   },
15177 /* sbb.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
15178   {
15179     M32C_INSN_SBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "sbb.b", 32,
15180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15181   },
15182 /* sbb.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
15183   {
15184     M32C_INSN_SBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "sbb.b", 32,
15185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15186   },
15187 /* sbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
15188   {
15189     M32C_INSN_SBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "sbb.b", 40,
15190     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15191   },
15192 /* sbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
15193   {
15194     M32C_INSN_SBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "sbb.b", 40,
15195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15196   },
15197 /* sbb.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
15198   {
15199     M32C_INSN_SBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "sbb.b", 40,
15200     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15201   },
15202 /* sbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
15203   {
15204     M32C_INSN_SBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "sbb.b", 48,
15205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15206   },
15207 /* sbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
15208   {
15209     M32C_INSN_SBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "sbb.b", 48,
15210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15211   },
15212 /* sbb.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
15213   {
15214     M32C_INSN_SBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "sbb.b", 48,
15215     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15216   },
15217 /* sbb.b${X} #${Imm-40-QI},${Dsp-24-u16} */
15218   {
15219     M32C_INSN_SBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "sbb.b", 48,
15220     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15221   },
15222 /* sbb.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
15223   {
15224     M32C_INSN_SBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "sbb.b", 56,
15225     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15226   },
15227 /* sbb.b${X} #${Imm-48-QI},${Dsp-24-u24} */
15228   {
15229     M32C_INSN_SBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "sbb.b", 56,
15230     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15231   },
15232 /* sbb.w${X} #${Imm-16-HI},$Dst16RnHI */
15233   {
15234     M32C_INSN_SBB16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "sbb16.w-imm-G-basic-dst16-Rn-direct-HI", "sbb.w", 32,
15235     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15236   },
15237 /* sbb.w${X} #${Imm-16-HI},$Dst16AnHI */
15238   {
15239     M32C_INSN_SBB16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "sbb16.w-imm-G-basic-dst16-An-direct-HI", "sbb.w", 32,
15240     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15241   },
15242 /* sbb.w${X} #${Imm-16-HI},[$Dst16An] */
15243   {
15244     M32C_INSN_SBB16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "sbb16.w-imm-G-basic-dst16-An-indirect-HI", "sbb.w", 32,
15245     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15246   },
15247 /* sbb.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
15248   {
15249     M32C_INSN_SBB16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "sbb16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "sbb.w", 40,
15250     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15251   },
15252 /* sbb.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
15253   {
15254     M32C_INSN_SBB16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "sbb16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "sbb.w", 40,
15255     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15256   },
15257 /* sbb.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
15258   {
15259     M32C_INSN_SBB16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "sbb16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "sbb.w", 40,
15260     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15261   },
15262 /* sbb.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
15263   {
15264     M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "sbb16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "sbb.w", 48,
15265     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15266   },
15267 /* sbb.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
15268   {
15269     M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "sbb16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "sbb.w", 48,
15270     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15271   },
15272 /* sbb.w${X} #${Imm-32-HI},${Dsp-16-u16} */
15273   {
15274     M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "sbb16.w-imm-G-16-16-dst16-16-16-absolute-HI", "sbb.w", 48,
15275     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15276   },
15277 /* sbb.b${X} #${Imm-16-QI},$Dst16RnQI */
15278   {
15279     M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "sbb16.b-imm-G-basic-dst16-Rn-direct-QI", "sbb.b", 24,
15280     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15281   },
15282 /* sbb.b${X} #${Imm-16-QI},$Dst16AnQI */
15283   {
15284     M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "sbb16.b-imm-G-basic-dst16-An-direct-QI", "sbb.b", 24,
15285     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15286   },
15287 /* sbb.b${X} #${Imm-16-QI},[$Dst16An] */
15288   {
15289     M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "sbb16.b-imm-G-basic-dst16-An-indirect-QI", "sbb.b", 24,
15290     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15291   },
15292 /* sbb.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
15293   {
15294     M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "sbb16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "sbb.b", 32,
15295     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15296   },
15297 /* sbb.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
15298   {
15299     M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "sbb16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "sbb.b", 32,
15300     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15301   },
15302 /* sbb.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
15303   {
15304     M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "sbb16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "sbb.b", 32,
15305     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15306   },
15307 /* sbb.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
15308   {
15309     M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "sbb16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "sbb.b", 40,
15310     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15311   },
15312 /* sbb.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
15313   {
15314     M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "sbb16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "sbb.b", 40,
15315     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15316   },
15317 /* sbb.b${X} #${Imm-32-QI},${Dsp-16-u16} */
15318   {
15319     M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "sbb16.b-imm-G-16-16-dst16-16-16-absolute-QI", "sbb.b", 40,
15320     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15321   },
15322 /* rot.w r1h,$Dst32RnUnprefixedHI */
15323   {
15324     M32C_INSN_ROT32_W_DST_DST32_RN_DIRECT_UNPREFIXED_HI, "rot32.w-dst-dst32-Rn-direct-Unprefixed-HI", "rot.w", 16,
15325     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15326   },
15327 /* rot.w r1h,$Dst32AnUnprefixedHI */
15328   {
15329     M32C_INSN_ROT32_W_DST_DST32_AN_DIRECT_UNPREFIXED_HI, "rot32.w-dst-dst32-An-direct-Unprefixed-HI", "rot.w", 16,
15330     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15331   },
15332 /* rot.w r1h,[$Dst32AnUnprefixed] */
15333   {
15334     M32C_INSN_ROT32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_HI, "rot32.w-dst-dst32-An-indirect-Unprefixed-HI", "rot.w", 16,
15335     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15336   },
15337 /* rot.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
15338   {
15339     M32C_INSN_ROT32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-8-An-relative-Unprefixed-HI", "rot.w", 24,
15340     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15341   },
15342 /* rot.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
15343   {
15344     M32C_INSN_ROT32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-16-An-relative-Unprefixed-HI", "rot.w", 32,
15345     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15346   },
15347 /* rot.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
15348   {
15349     M32C_INSN_ROT32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-24-An-relative-Unprefixed-HI", "rot.w", 40,
15350     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15351   },
15352 /* rot.w r1h,${Dsp-16-u8}[sb] */
15353   {
15354     M32C_INSN_ROT32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-8-SB-relative-Unprefixed-HI", "rot.w", 24,
15355     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15356   },
15357 /* rot.w r1h,${Dsp-16-u16}[sb] */
15358   {
15359     M32C_INSN_ROT32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-16-SB-relative-Unprefixed-HI", "rot.w", 32,
15360     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15361   },
15362 /* rot.w r1h,${Dsp-16-s8}[fb] */
15363   {
15364     M32C_INSN_ROT32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-8-FB-relative-Unprefixed-HI", "rot.w", 24,
15365     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15366   },
15367 /* rot.w r1h,${Dsp-16-s16}[fb] */
15368   {
15369     M32C_INSN_ROT32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-16-FB-relative-Unprefixed-HI", "rot.w", 32,
15370     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15371   },
15372 /* rot.w r1h,${Dsp-16-u16} */
15373   {
15374     M32C_INSN_ROT32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-16-absolute-Unprefixed-HI", "rot.w", 32,
15375     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15376   },
15377 /* rot.w r1h,${Dsp-16-u24} */
15378   {
15379     M32C_INSN_ROT32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "rot32.w-dst-dst32-16-24-absolute-Unprefixed-HI", "rot.w", 40,
15380     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15381   },
15382 /* rot.b r1h,$Dst32RnUnprefixedQI */
15383   {
15384     M32C_INSN_ROT32_B_DST_DST32_RN_DIRECT_UNPREFIXED_QI, "rot32.b-dst-dst32-Rn-direct-Unprefixed-QI", "rot.b", 16,
15385     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15386   },
15387 /* rot.b r1h,$Dst32AnUnprefixedQI */
15388   {
15389     M32C_INSN_ROT32_B_DST_DST32_AN_DIRECT_UNPREFIXED_QI, "rot32.b-dst-dst32-An-direct-Unprefixed-QI", "rot.b", 16,
15390     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15391   },
15392 /* rot.b r1h,[$Dst32AnUnprefixed] */
15393   {
15394     M32C_INSN_ROT32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_QI, "rot32.b-dst-dst32-An-indirect-Unprefixed-QI", "rot.b", 16,
15395     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15396   },
15397 /* rot.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
15398   {
15399     M32C_INSN_ROT32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-8-An-relative-Unprefixed-QI", "rot.b", 24,
15400     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15401   },
15402 /* rot.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
15403   {
15404     M32C_INSN_ROT32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-16-An-relative-Unprefixed-QI", "rot.b", 32,
15405     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15406   },
15407 /* rot.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
15408   {
15409     M32C_INSN_ROT32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-24-An-relative-Unprefixed-QI", "rot.b", 40,
15410     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15411   },
15412 /* rot.b r1h,${Dsp-16-u8}[sb] */
15413   {
15414     M32C_INSN_ROT32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-8-SB-relative-Unprefixed-QI", "rot.b", 24,
15415     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15416   },
15417 /* rot.b r1h,${Dsp-16-u16}[sb] */
15418   {
15419     M32C_INSN_ROT32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-16-SB-relative-Unprefixed-QI", "rot.b", 32,
15420     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15421   },
15422 /* rot.b r1h,${Dsp-16-s8}[fb] */
15423   {
15424     M32C_INSN_ROT32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-8-FB-relative-Unprefixed-QI", "rot.b", 24,
15425     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15426   },
15427 /* rot.b r1h,${Dsp-16-s16}[fb] */
15428   {
15429     M32C_INSN_ROT32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-16-FB-relative-Unprefixed-QI", "rot.b", 32,
15430     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15431   },
15432 /* rot.b r1h,${Dsp-16-u16} */
15433   {
15434     M32C_INSN_ROT32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-16-absolute-Unprefixed-QI", "rot.b", 32,
15435     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15436   },
15437 /* rot.b r1h,${Dsp-16-u24} */
15438   {
15439     M32C_INSN_ROT32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "rot32.b-dst-dst32-16-24-absolute-Unprefixed-QI", "rot.b", 40,
15440     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15441   },
15442 /* rot.w r1h,$Dst16RnHI */
15443   {
15444     M32C_INSN_ROT16_W_DST_DST16_RN_DIRECT_HI, "rot16.w-dst-dst16-Rn-direct-HI", "rot.w", 16,
15445     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15446   },
15447 /* rot.w r1h,$Dst16AnHI */
15448   {
15449     M32C_INSN_ROT16_W_DST_DST16_AN_DIRECT_HI, "rot16.w-dst-dst16-An-direct-HI", "rot.w", 16,
15450     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15451   },
15452 /* rot.w r1h,[$Dst16An] */
15453   {
15454     M32C_INSN_ROT16_W_DST_DST16_AN_INDIRECT_HI, "rot16.w-dst-dst16-An-indirect-HI", "rot.w", 16,
15455     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15456   },
15457 /* rot.w r1h,${Dsp-16-u8}[$Dst16An] */
15458   {
15459     M32C_INSN_ROT16_W_DST_DST16_16_8_AN_RELATIVE_HI, "rot16.w-dst-dst16-16-8-An-relative-HI", "rot.w", 24,
15460     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15461   },
15462 /* rot.w r1h,${Dsp-16-u16}[$Dst16An] */
15463   {
15464     M32C_INSN_ROT16_W_DST_DST16_16_16_AN_RELATIVE_HI, "rot16.w-dst-dst16-16-16-An-relative-HI", "rot.w", 32,
15465     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15466   },
15467 /* rot.w r1h,${Dsp-16-u8}[sb] */
15468   {
15469     M32C_INSN_ROT16_W_DST_DST16_16_8_SB_RELATIVE_HI, "rot16.w-dst-dst16-16-8-SB-relative-HI", "rot.w", 24,
15470     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15471   },
15472 /* rot.w r1h,${Dsp-16-u16}[sb] */
15473   {
15474     M32C_INSN_ROT16_W_DST_DST16_16_16_SB_RELATIVE_HI, "rot16.w-dst-dst16-16-16-SB-relative-HI", "rot.w", 32,
15475     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15476   },
15477 /* rot.w r1h,${Dsp-16-s8}[fb] */
15478   {
15479     M32C_INSN_ROT16_W_DST_DST16_16_8_FB_RELATIVE_HI, "rot16.w-dst-dst16-16-8-FB-relative-HI", "rot.w", 24,
15480     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15481   },
15482 /* rot.w r1h,${Dsp-16-u16} */
15483   {
15484     M32C_INSN_ROT16_W_DST_DST16_16_16_ABSOLUTE_HI, "rot16.w-dst-dst16-16-16-absolute-HI", "rot.w", 32,
15485     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15486   },
15487 /* rot.b r1h,$Dst16RnQI */
15488   {
15489     M32C_INSN_ROT16_B_DST_DST16_RN_DIRECT_QI, "rot16.b-dst-dst16-Rn-direct-QI", "rot.b", 16,
15490     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15491   },
15492 /* rot.b r1h,$Dst16AnQI */
15493   {
15494     M32C_INSN_ROT16_B_DST_DST16_AN_DIRECT_QI, "rot16.b-dst-dst16-An-direct-QI", "rot.b", 16,
15495     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15496   },
15497 /* rot.b r1h,[$Dst16An] */
15498   {
15499     M32C_INSN_ROT16_B_DST_DST16_AN_INDIRECT_QI, "rot16.b-dst-dst16-An-indirect-QI", "rot.b", 16,
15500     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15501   },
15502 /* rot.b r1h,${Dsp-16-u8}[$Dst16An] */
15503   {
15504     M32C_INSN_ROT16_B_DST_DST16_16_8_AN_RELATIVE_QI, "rot16.b-dst-dst16-16-8-An-relative-QI", "rot.b", 24,
15505     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15506   },
15507 /* rot.b r1h,${Dsp-16-u16}[$Dst16An] */
15508   {
15509     M32C_INSN_ROT16_B_DST_DST16_16_16_AN_RELATIVE_QI, "rot16.b-dst-dst16-16-16-An-relative-QI", "rot.b", 32,
15510     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15511   },
15512 /* rot.b r1h,${Dsp-16-u8}[sb] */
15513   {
15514     M32C_INSN_ROT16_B_DST_DST16_16_8_SB_RELATIVE_QI, "rot16.b-dst-dst16-16-8-SB-relative-QI", "rot.b", 24,
15515     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15516   },
15517 /* rot.b r1h,${Dsp-16-u16}[sb] */
15518   {
15519     M32C_INSN_ROT16_B_DST_DST16_16_16_SB_RELATIVE_QI, "rot16.b-dst-dst16-16-16-SB-relative-QI", "rot.b", 32,
15520     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15521   },
15522 /* rot.b r1h,${Dsp-16-s8}[fb] */
15523   {
15524     M32C_INSN_ROT16_B_DST_DST16_16_8_FB_RELATIVE_QI, "rot16.b-dst-dst16-16-8-FB-relative-QI", "rot.b", 24,
15525     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15526   },
15527 /* rot.b r1h,${Dsp-16-u16} */
15528   {
15529     M32C_INSN_ROT16_B_DST_DST16_16_16_ABSOLUTE_QI, "rot16.b-dst-dst16-16-16-absolute-QI", "rot.b", 32,
15530     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15531   },
15532 /* rot.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */
15533   {
15534     M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "rot.w", 16,
15535     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15536   },
15537 /* rot.w${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedHI */
15538   {
15539     M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "rot.w", 16,
15540     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15541   },
15542 /* rot.w${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
15543   {
15544     M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "rot.w", 16,
15545     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15546   },
15547 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
15548   {
15549     M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "rot.w", 24,
15550     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15551   },
15552 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
15553   {
15554     M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "rot.w", 32,
15555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15556   },
15557 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
15558   {
15559     M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "rot.w", 40,
15560     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15561   },
15562 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
15563   {
15564     M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "rot.w", 24,
15565     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15566   },
15567 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
15568   {
15569     M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "rot.w", 32,
15570     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15571   },
15572 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
15573   {
15574     M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "rot.w", 24,
15575     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15576   },
15577 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
15578   {
15579     M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "rot.w", 32,
15580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15581   },
15582 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
15583   {
15584     M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "rot.w", 32,
15585     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15586   },
15587 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
15588   {
15589     M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "rot.w", 40,
15590     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15591   },
15592 /* rot.b${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedQI */
15593   {
15594     M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "rot.b", 16,
15595     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15596   },
15597 /* rot.b${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedQI */
15598   {
15599     M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "rot.b", 16,
15600     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15601   },
15602 /* rot.b${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
15603   {
15604     M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "rot.b", 16,
15605     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15606   },
15607 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
15608   {
15609     M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "rot.b", 24,
15610     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15611   },
15612 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
15613   {
15614     M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "rot.b", 32,
15615     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15616   },
15617 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
15618   {
15619     M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "rot.b", 40,
15620     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15621   },
15622 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
15623   {
15624     M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "rot.b", 24,
15625     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15626   },
15627 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
15628   {
15629     M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "rot.b", 32,
15630     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15631   },
15632 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
15633   {
15634     M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "rot.b", 24,
15635     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15636   },
15637 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
15638   {
15639     M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "rot.b", 32,
15640     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15641   },
15642 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
15643   {
15644     M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "rot.b", 32,
15645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15646   },
15647 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
15648   {
15649     M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "rot.b", 40,
15650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15651   },
15652 /* rot.w${Q} #${Imm-sh-8-s4},$Dst16RnHI */
15653   {
15654     M32C_INSN_ROT16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "rot16.w-imm4-Q-16-dst16-Rn-direct-HI", "rot.w", 16,
15655     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15656   },
15657 /* rot.w${Q} #${Imm-sh-8-s4},$Dst16AnHI */
15658   {
15659     M32C_INSN_ROT16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "rot16.w-imm4-Q-16-dst16-An-direct-HI", "rot.w", 16,
15660     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15661   },
15662 /* rot.w${Q} #${Imm-sh-8-s4},[$Dst16An] */
15663   {
15664     M32C_INSN_ROT16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "rot16.w-imm4-Q-16-dst16-An-indirect-HI", "rot.w", 16,
15665     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15666   },
15667 /* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
15668   {
15669     M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "rot.w", 24,
15670     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15671   },
15672 /* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
15673   {
15674     M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "rot.w", 32,
15675     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15676   },
15677 /* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
15678   {
15679     M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "rot.w", 24,
15680     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15681   },
15682 /* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
15683   {
15684     M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "rot.w", 32,
15685     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15686   },
15687 /* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
15688   {
15689     M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "rot.w", 24,
15690     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15691   },
15692 /* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
15693   {
15694     M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "rot16.w-imm4-Q-16-dst16-16-16-absolute-HI", "rot.w", 32,
15695     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15696   },
15697 /* rot.b${Q} #${Imm-sh-8-s4},$Dst16RnQI */
15698   {
15699     M32C_INSN_ROT16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "rot16.b-imm4-Q-16-dst16-Rn-direct-QI", "rot.b", 16,
15700     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15701   },
15702 /* rot.b${Q} #${Imm-sh-8-s4},$Dst16AnQI */
15703   {
15704     M32C_INSN_ROT16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "rot16.b-imm4-Q-16-dst16-An-direct-QI", "rot.b", 16,
15705     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15706   },
15707 /* rot.b${Q} #${Imm-sh-8-s4},[$Dst16An] */
15708   {
15709     M32C_INSN_ROT16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "rot16.b-imm4-Q-16-dst16-An-indirect-QI", "rot.b", 16,
15710     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15711   },
15712 /* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
15713   {
15714     M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "rot.b", 24,
15715     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15716   },
15717 /* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
15718   {
15719     M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "rot.b", 32,
15720     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15721   },
15722 /* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
15723   {
15724     M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "rot.b", 24,
15725     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15726   },
15727 /* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
15728   {
15729     M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "rot.b", 32,
15730     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15731   },
15732 /* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
15733   {
15734     M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "rot.b", 24,
15735     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15736   },
15737 /* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
15738   {
15739     M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "rot16.b-imm4-Q-16-dst16-16-16-absolute-QI", "rot.b", 32,
15740     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15741   },
15742 /* rorc.w $Dst32RnUnprefixedHI */
15743   {
15744     M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "rorc.w", 16,
15745     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15746   },
15747 /* rorc.w $Dst32AnUnprefixedHI */
15748   {
15749     M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "rorc.w", 16,
15750     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15751   },
15752 /* rorc.w [$Dst32AnUnprefixed] */
15753   {
15754     M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "rorc.w", 16,
15755     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15756   },
15757 /* rorc.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
15758   {
15759     M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "rorc.w", 24,
15760     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15761   },
15762 /* rorc.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
15763   {
15764     M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "rorc.w", 32,
15765     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15766   },
15767 /* rorc.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
15768   {
15769     M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "rorc.w", 40,
15770     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15771   },
15772 /* rorc.w ${Dsp-16-u8}[sb] */
15773   {
15774     M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "rorc.w", 24,
15775     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15776   },
15777 /* rorc.w ${Dsp-16-u16}[sb] */
15778   {
15779     M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "rorc.w", 32,
15780     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15781   },
15782 /* rorc.w ${Dsp-16-s8}[fb] */
15783   {
15784     M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "rorc.w", 24,
15785     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15786   },
15787 /* rorc.w ${Dsp-16-s16}[fb] */
15788   {
15789     M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "rorc.w", 32,
15790     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15791   },
15792 /* rorc.w ${Dsp-16-u16} */
15793   {
15794     M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "rorc.w", 32,
15795     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15796   },
15797 /* rorc.w ${Dsp-16-u24} */
15798   {
15799     M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "rorc.w", 40,
15800     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15801   },
15802 /* rorc.b $Dst32RnUnprefixedQI */
15803   {
15804     M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "rorc.b", 16,
15805     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15806   },
15807 /* rorc.b $Dst32AnUnprefixedQI */
15808   {
15809     M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "rorc.b", 16,
15810     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15811   },
15812 /* rorc.b [$Dst32AnUnprefixed] */
15813   {
15814     M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "rorc.b", 16,
15815     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15816   },
15817 /* rorc.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
15818   {
15819     M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "rorc.b", 24,
15820     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15821   },
15822 /* rorc.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
15823   {
15824     M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "rorc.b", 32,
15825     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15826   },
15827 /* rorc.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
15828   {
15829     M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "rorc.b", 40,
15830     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15831   },
15832 /* rorc.b ${Dsp-16-u8}[sb] */
15833   {
15834     M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "rorc.b", 24,
15835     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15836   },
15837 /* rorc.b ${Dsp-16-u16}[sb] */
15838   {
15839     M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "rorc.b", 32,
15840     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15841   },
15842 /* rorc.b ${Dsp-16-s8}[fb] */
15843   {
15844     M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "rorc.b", 24,
15845     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15846   },
15847 /* rorc.b ${Dsp-16-s16}[fb] */
15848   {
15849     M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "rorc.b", 32,
15850     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15851   },
15852 /* rorc.b ${Dsp-16-u16} */
15853   {
15854     M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "rorc.b", 32,
15855     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15856   },
15857 /* rorc.b ${Dsp-16-u24} */
15858   {
15859     M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "rorc.b", 40,
15860     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15861   },
15862 /* rorc.w $Dst16RnHI */
15863   {
15864     M32C_INSN_RORC16_W_16_DST16_RN_DIRECT_HI, "rorc16.w-16-dst16-Rn-direct-HI", "rorc.w", 16,
15865     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15866   },
15867 /* rorc.w $Dst16AnHI */
15868   {
15869     M32C_INSN_RORC16_W_16_DST16_AN_DIRECT_HI, "rorc16.w-16-dst16-An-direct-HI", "rorc.w", 16,
15870     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15871   },
15872 /* rorc.w [$Dst16An] */
15873   {
15874     M32C_INSN_RORC16_W_16_DST16_AN_INDIRECT_HI, "rorc16.w-16-dst16-An-indirect-HI", "rorc.w", 16,
15875     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15876   },
15877 /* rorc.w ${Dsp-16-u8}[$Dst16An] */
15878   {
15879     M32C_INSN_RORC16_W_16_DST16_16_8_AN_RELATIVE_HI, "rorc16.w-16-dst16-16-8-An-relative-HI", "rorc.w", 24,
15880     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15881   },
15882 /* rorc.w ${Dsp-16-u16}[$Dst16An] */
15883   {
15884     M32C_INSN_RORC16_W_16_DST16_16_16_AN_RELATIVE_HI, "rorc16.w-16-dst16-16-16-An-relative-HI", "rorc.w", 32,
15885     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15886   },
15887 /* rorc.w ${Dsp-16-u8}[sb] */
15888   {
15889     M32C_INSN_RORC16_W_16_DST16_16_8_SB_RELATIVE_HI, "rorc16.w-16-dst16-16-8-SB-relative-HI", "rorc.w", 24,
15890     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15891   },
15892 /* rorc.w ${Dsp-16-u16}[sb] */
15893   {
15894     M32C_INSN_RORC16_W_16_DST16_16_16_SB_RELATIVE_HI, "rorc16.w-16-dst16-16-16-SB-relative-HI", "rorc.w", 32,
15895     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15896   },
15897 /* rorc.w ${Dsp-16-s8}[fb] */
15898   {
15899     M32C_INSN_RORC16_W_16_DST16_16_8_FB_RELATIVE_HI, "rorc16.w-16-dst16-16-8-FB-relative-HI", "rorc.w", 24,
15900     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15901   },
15902 /* rorc.w ${Dsp-16-u16} */
15903   {
15904     M32C_INSN_RORC16_W_16_DST16_16_16_ABSOLUTE_HI, "rorc16.w-16-dst16-16-16-absolute-HI", "rorc.w", 32,
15905     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15906   },
15907 /* rorc.b $Dst16RnQI */
15908   {
15909     M32C_INSN_RORC16_B_16_DST16_RN_DIRECT_QI, "rorc16.b-16-dst16-Rn-direct-QI", "rorc.b", 16,
15910     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15911   },
15912 /* rorc.b $Dst16AnQI */
15913   {
15914     M32C_INSN_RORC16_B_16_DST16_AN_DIRECT_QI, "rorc16.b-16-dst16-An-direct-QI", "rorc.b", 16,
15915     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15916   },
15917 /* rorc.b [$Dst16An] */
15918   {
15919     M32C_INSN_RORC16_B_16_DST16_AN_INDIRECT_QI, "rorc16.b-16-dst16-An-indirect-QI", "rorc.b", 16,
15920     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15921   },
15922 /* rorc.b ${Dsp-16-u8}[$Dst16An] */
15923   {
15924     M32C_INSN_RORC16_B_16_DST16_16_8_AN_RELATIVE_QI, "rorc16.b-16-dst16-16-8-An-relative-QI", "rorc.b", 24,
15925     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15926   },
15927 /* rorc.b ${Dsp-16-u16}[$Dst16An] */
15928   {
15929     M32C_INSN_RORC16_B_16_DST16_16_16_AN_RELATIVE_QI, "rorc16.b-16-dst16-16-16-An-relative-QI", "rorc.b", 32,
15930     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15931   },
15932 /* rorc.b ${Dsp-16-u8}[sb] */
15933   {
15934     M32C_INSN_RORC16_B_16_DST16_16_8_SB_RELATIVE_QI, "rorc16.b-16-dst16-16-8-SB-relative-QI", "rorc.b", 24,
15935     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15936   },
15937 /* rorc.b ${Dsp-16-u16}[sb] */
15938   {
15939     M32C_INSN_RORC16_B_16_DST16_16_16_SB_RELATIVE_QI, "rorc16.b-16-dst16-16-16-SB-relative-QI", "rorc.b", 32,
15940     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15941   },
15942 /* rorc.b ${Dsp-16-s8}[fb] */
15943   {
15944     M32C_INSN_RORC16_B_16_DST16_16_8_FB_RELATIVE_QI, "rorc16.b-16-dst16-16-8-FB-relative-QI", "rorc.b", 24,
15945     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15946   },
15947 /* rorc.b ${Dsp-16-u16} */
15948   {
15949     M32C_INSN_RORC16_B_16_DST16_16_16_ABSOLUTE_QI, "rorc16.b-16-dst16-16-16-absolute-QI", "rorc.b", 32,
15950     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15951   },
15952 /* rolc.w $Dst32RnUnprefixedHI */
15953   {
15954     M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "rolc.w", 16,
15955     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15956   },
15957 /* rolc.w $Dst32AnUnprefixedHI */
15958   {
15959     M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "rolc.w", 16,
15960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15961   },
15962 /* rolc.w [$Dst32AnUnprefixed] */
15963   {
15964     M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "rolc.w", 16,
15965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15966   },
15967 /* rolc.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
15968   {
15969     M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "rolc.w", 24,
15970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15971   },
15972 /* rolc.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
15973   {
15974     M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "rolc.w", 32,
15975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15976   },
15977 /* rolc.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
15978   {
15979     M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "rolc.w", 40,
15980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15981   },
15982 /* rolc.w ${Dsp-16-u8}[sb] */
15983   {
15984     M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "rolc.w", 24,
15985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15986   },
15987 /* rolc.w ${Dsp-16-u16}[sb] */
15988   {
15989     M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "rolc.w", 32,
15990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15991   },
15992 /* rolc.w ${Dsp-16-s8}[fb] */
15993   {
15994     M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "rolc.w", 24,
15995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15996   },
15997 /* rolc.w ${Dsp-16-s16}[fb] */
15998   {
15999     M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "rolc.w", 32,
16000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16001   },
16002 /* rolc.w ${Dsp-16-u16} */
16003   {
16004     M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "rolc.w", 32,
16005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16006   },
16007 /* rolc.w ${Dsp-16-u24} */
16008   {
16009     M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "rolc.w", 40,
16010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16011   },
16012 /* rolc.b $Dst32RnUnprefixedQI */
16013   {
16014     M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "rolc.b", 16,
16015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16016   },
16017 /* rolc.b $Dst32AnUnprefixedQI */
16018   {
16019     M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "rolc.b", 16,
16020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16021   },
16022 /* rolc.b [$Dst32AnUnprefixed] */
16023   {
16024     M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "rolc.b", 16,
16025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16026   },
16027 /* rolc.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
16028   {
16029     M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "rolc.b", 24,
16030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16031   },
16032 /* rolc.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
16033   {
16034     M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "rolc.b", 32,
16035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16036   },
16037 /* rolc.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
16038   {
16039     M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "rolc.b", 40,
16040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16041   },
16042 /* rolc.b ${Dsp-16-u8}[sb] */
16043   {
16044     M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "rolc.b", 24,
16045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16046   },
16047 /* rolc.b ${Dsp-16-u16}[sb] */
16048   {
16049     M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "rolc.b", 32,
16050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16051   },
16052 /* rolc.b ${Dsp-16-s8}[fb] */
16053   {
16054     M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "rolc.b", 24,
16055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16056   },
16057 /* rolc.b ${Dsp-16-s16}[fb] */
16058   {
16059     M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "rolc.b", 32,
16060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16061   },
16062 /* rolc.b ${Dsp-16-u16} */
16063   {
16064     M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "rolc.b", 32,
16065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16066   },
16067 /* rolc.b ${Dsp-16-u24} */
16068   {
16069     M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "rolc.b", 40,
16070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16071   },
16072 /* rolc.w $Dst16RnHI */
16073   {
16074     M32C_INSN_ROLC16_W_16_DST16_RN_DIRECT_HI, "rolc16.w-16-dst16-Rn-direct-HI", "rolc.w", 16,
16075     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16076   },
16077 /* rolc.w $Dst16AnHI */
16078   {
16079     M32C_INSN_ROLC16_W_16_DST16_AN_DIRECT_HI, "rolc16.w-16-dst16-An-direct-HI", "rolc.w", 16,
16080     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16081   },
16082 /* rolc.w [$Dst16An] */
16083   {
16084     M32C_INSN_ROLC16_W_16_DST16_AN_INDIRECT_HI, "rolc16.w-16-dst16-An-indirect-HI", "rolc.w", 16,
16085     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16086   },
16087 /* rolc.w ${Dsp-16-u8}[$Dst16An] */
16088   {
16089     M32C_INSN_ROLC16_W_16_DST16_16_8_AN_RELATIVE_HI, "rolc16.w-16-dst16-16-8-An-relative-HI", "rolc.w", 24,
16090     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16091   },
16092 /* rolc.w ${Dsp-16-u16}[$Dst16An] */
16093   {
16094     M32C_INSN_ROLC16_W_16_DST16_16_16_AN_RELATIVE_HI, "rolc16.w-16-dst16-16-16-An-relative-HI", "rolc.w", 32,
16095     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16096   },
16097 /* rolc.w ${Dsp-16-u8}[sb] */
16098   {
16099     M32C_INSN_ROLC16_W_16_DST16_16_8_SB_RELATIVE_HI, "rolc16.w-16-dst16-16-8-SB-relative-HI", "rolc.w", 24,
16100     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16101   },
16102 /* rolc.w ${Dsp-16-u16}[sb] */
16103   {
16104     M32C_INSN_ROLC16_W_16_DST16_16_16_SB_RELATIVE_HI, "rolc16.w-16-dst16-16-16-SB-relative-HI", "rolc.w", 32,
16105     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16106   },
16107 /* rolc.w ${Dsp-16-s8}[fb] */
16108   {
16109     M32C_INSN_ROLC16_W_16_DST16_16_8_FB_RELATIVE_HI, "rolc16.w-16-dst16-16-8-FB-relative-HI", "rolc.w", 24,
16110     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16111   },
16112 /* rolc.w ${Dsp-16-u16} */
16113   {
16114     M32C_INSN_ROLC16_W_16_DST16_16_16_ABSOLUTE_HI, "rolc16.w-16-dst16-16-16-absolute-HI", "rolc.w", 32,
16115     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16116   },
16117 /* rolc.b $Dst16RnQI */
16118   {
16119     M32C_INSN_ROLC16_B_16_DST16_RN_DIRECT_QI, "rolc16.b-16-dst16-Rn-direct-QI", "rolc.b", 16,
16120     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16121   },
16122 /* rolc.b $Dst16AnQI */
16123   {
16124     M32C_INSN_ROLC16_B_16_DST16_AN_DIRECT_QI, "rolc16.b-16-dst16-An-direct-QI", "rolc.b", 16,
16125     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16126   },
16127 /* rolc.b [$Dst16An] */
16128   {
16129     M32C_INSN_ROLC16_B_16_DST16_AN_INDIRECT_QI, "rolc16.b-16-dst16-An-indirect-QI", "rolc.b", 16,
16130     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16131   },
16132 /* rolc.b ${Dsp-16-u8}[$Dst16An] */
16133   {
16134     M32C_INSN_ROLC16_B_16_DST16_16_8_AN_RELATIVE_QI, "rolc16.b-16-dst16-16-8-An-relative-QI", "rolc.b", 24,
16135     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16136   },
16137 /* rolc.b ${Dsp-16-u16}[$Dst16An] */
16138   {
16139     M32C_INSN_ROLC16_B_16_DST16_16_16_AN_RELATIVE_QI, "rolc16.b-16-dst16-16-16-An-relative-QI", "rolc.b", 32,
16140     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16141   },
16142 /* rolc.b ${Dsp-16-u8}[sb] */
16143   {
16144     M32C_INSN_ROLC16_B_16_DST16_16_8_SB_RELATIVE_QI, "rolc16.b-16-dst16-16-8-SB-relative-QI", "rolc.b", 24,
16145     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16146   },
16147 /* rolc.b ${Dsp-16-u16}[sb] */
16148   {
16149     M32C_INSN_ROLC16_B_16_DST16_16_16_SB_RELATIVE_QI, "rolc16.b-16-dst16-16-16-SB-relative-QI", "rolc.b", 32,
16150     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16151   },
16152 /* rolc.b ${Dsp-16-s8}[fb] */
16153   {
16154     M32C_INSN_ROLC16_B_16_DST16_16_8_FB_RELATIVE_QI, "rolc16.b-16-dst16-16-8-FB-relative-QI", "rolc.b", 24,
16155     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16156   },
16157 /* rolc.b ${Dsp-16-u16} */
16158   {
16159     M32C_INSN_ROLC16_B_16_DST16_16_16_ABSOLUTE_QI, "rolc16.b-16-dst16-16-16-absolute-QI", "rolc.b", 32,
16160     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16161   },
16162 /* pusha [$Dst32AnUnprefixed] */
16163   {
16164     M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-An-indirect-Unprefixed-Mova-SI", "pusha", 16,
16165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16166   },
16167 /* pusha ${Dsp-16-u8}[$Dst32AnUnprefixed] */
16168   {
16169     M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-8-An-relative-Unprefixed-Mova-SI", "pusha", 24,
16170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16171   },
16172 /* pusha ${Dsp-16-u16}[$Dst32AnUnprefixed] */
16173   {
16174     M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-16-An-relative-Unprefixed-Mova-SI", "pusha", 32,
16175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16176   },
16177 /* pusha ${Dsp-16-u24}[$Dst32AnUnprefixed] */
16178   {
16179     M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-24-An-relative-Unprefixed-Mova-SI", "pusha", 40,
16180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16181   },
16182 /* pusha ${Dsp-16-u8}[sb] */
16183   {
16184     M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "pusha", 24,
16185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16186   },
16187 /* pusha ${Dsp-16-u16}[sb] */
16188   {
16189     M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "pusha", 32,
16190     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16191   },
16192 /* pusha ${Dsp-16-s8}[fb] */
16193   {
16194     M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "pusha", 24,
16195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16196   },
16197 /* pusha ${Dsp-16-s16}[fb] */
16198   {
16199     M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "pusha", 32,
16200     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16201   },
16202 /* pusha ${Dsp-16-u16} */
16203   {
16204     M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-16-absolute-Unprefixed-Mova-SI", "pusha", 32,
16205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16206   },
16207 /* pusha ${Dsp-16-u24} */
16208   {
16209     M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-24-absolute-Unprefixed-Mova-SI", "pusha", 40,
16210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16211   },
16212 /* pusha [$Dst16An] */
16213   {
16214     M32C_INSN_PUSHA16_16_MOVA_DST16_AN_INDIRECT_MOVA_HI, "pusha16-16-Mova-dst16-An-indirect-Mova-HI", "pusha", 16,
16215     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16216   },
16217 /* pusha ${Dsp-16-u8}[$Dst16An] */
16218   {
16219     M32C_INSN_PUSHA16_16_MOVA_DST16_16_8_AN_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-8-An-relative-Mova-HI", "pusha", 24,
16220     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16221   },
16222 /* pusha ${Dsp-16-u16}[$Dst16An] */
16223   {
16224     M32C_INSN_PUSHA16_16_MOVA_DST16_16_16_AN_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-16-An-relative-Mova-HI", "pusha", 32,
16225     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16226   },
16227 /* pusha ${Dsp-16-u8}[sb] */
16228   {
16229     M32C_INSN_PUSHA16_16_MOVA_DST16_16_8_SB_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-8-SB-relative-Mova-HI", "pusha", 24,
16230     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16231   },
16232 /* pusha ${Dsp-16-u16}[sb] */
16233   {
16234     M32C_INSN_PUSHA16_16_MOVA_DST16_16_16_SB_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-16-SB-relative-Mova-HI", "pusha", 32,
16235     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16236   },
16237 /* pusha ${Dsp-16-s8}[fb] */
16238   {
16239     M32C_INSN_PUSHA16_16_MOVA_DST16_16_8_FB_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-8-FB-relative-Mova-HI", "pusha", 24,
16240     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16241   },
16242 /* pusha ${Dsp-16-u16} */
16243   {
16244     M32C_INSN_PUSHA16_16_MOVA_DST16_16_16_ABSOLUTE_MOVA_HI, "pusha16-16-Mova-dst16-16-16-absolute-Mova-HI", "pusha", 32,
16245     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16246   },
16247 /* push.l $Dst32RnUnprefixedSI */
16248   {
16249     M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "push.l", 16,
16250     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16251   },
16252 /* push.l $Dst32AnUnprefixedSI */
16253   {
16254     M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-An-direct-Unprefixed-SI", "push.l", 16,
16255     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16256   },
16257 /* push.l [$Dst32AnUnprefixed] */
16258   {
16259     M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-An-indirect-Unprefixed-SI", "push.l", 16,
16260     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16261   },
16262 /* push.l ${Dsp-16-u8}[$Dst32AnUnprefixed] */
16263   {
16264     M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "push.l", 24,
16265     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16266   },
16267 /* push.l ${Dsp-16-u16}[$Dst32AnUnprefixed] */
16268   {
16269     M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "push.l", 32,
16270     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16271   },
16272 /* push.l ${Dsp-16-u24}[$Dst32AnUnprefixed] */
16273   {
16274     M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "push.l", 40,
16275     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16276   },
16277 /* push.l ${Dsp-16-u8}[sb] */
16278   {
16279     M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "push.l", 24,
16280     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16281   },
16282 /* push.l ${Dsp-16-u16}[sb] */
16283   {
16284     M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "push.l", 32,
16285     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16286   },
16287 /* push.l ${Dsp-16-s8}[fb] */
16288   {
16289     M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "push.l", 24,
16290     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16291   },
16292 /* push.l ${Dsp-16-s16}[fb] */
16293   {
16294     M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "push.l", 32,
16295     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16296   },
16297 /* push.l ${Dsp-16-u16} */
16298   {
16299     M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "push.l", 32,
16300     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16301   },
16302 /* push.l ${Dsp-16-u24} */
16303   {
16304     M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "push.l", 40,
16305     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16306   },
16307 /* push.w${S} ${An16-push-S} */
16308   {
16309     M32C_INSN_PUSH16_B_S_AN_AN16_PUSH_S_DERIVED, "push16.b-s-an-An16-push-S-derived", "push.w", 8,
16310     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16311   },
16312 /* push.b${S} ${Rn16-push-S} */
16313   {
16314     M32C_INSN_PUSH16_B_S_RN_RN16_PUSH_S_DERIVED, "push16.b-s-rn-Rn16-push-S-derived", "push.b", 8,
16315     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16316   },
16317 /* push.w $Dst32RnUnprefixedHI */
16318   {
16319     M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "push.w", 16,
16320     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16321   },
16322 /* push.w $Dst32AnUnprefixedHI */
16323   {
16324     M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "push.w", 16,
16325     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16326   },
16327 /* push.w [$Dst32AnUnprefixed] */
16328   {
16329     M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "push.w", 16,
16330     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16331   },
16332 /* push.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
16333   {
16334     M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "push.w", 24,
16335     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16336   },
16337 /* push.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
16338   {
16339     M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "push.w", 32,
16340     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16341   },
16342 /* push.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
16343   {
16344     M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "push.w", 40,
16345     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16346   },
16347 /* push.w ${Dsp-16-u8}[sb] */
16348   {
16349     M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "push.w", 24,
16350     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16351   },
16352 /* push.w ${Dsp-16-u16}[sb] */
16353   {
16354     M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "push.w", 32,
16355     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16356   },
16357 /* push.w ${Dsp-16-s8}[fb] */
16358   {
16359     M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "push.w", 24,
16360     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16361   },
16362 /* push.w ${Dsp-16-s16}[fb] */
16363   {
16364     M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "push.w", 32,
16365     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16366   },
16367 /* push.w ${Dsp-16-u16} */
16368   {
16369     M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "push.w", 32,
16370     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16371   },
16372 /* push.w ${Dsp-16-u24} */
16373   {
16374     M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "push.w", 40,
16375     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16376   },
16377 /* push.b $Dst32RnUnprefixedQI */
16378   {
16379     M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "push.b", 16,
16380     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16381   },
16382 /* push.b $Dst32AnUnprefixedQI */
16383   {
16384     M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "push.b", 16,
16385     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16386   },
16387 /* push.b [$Dst32AnUnprefixed] */
16388   {
16389     M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "push.b", 16,
16390     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16391   },
16392 /* push.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
16393   {
16394     M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "push.b", 24,
16395     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16396   },
16397 /* push.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
16398   {
16399     M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "push.b", 32,
16400     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16401   },
16402 /* push.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
16403   {
16404     M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "push.b", 40,
16405     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16406   },
16407 /* push.b ${Dsp-16-u8}[sb] */
16408   {
16409     M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "push.b", 24,
16410     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16411   },
16412 /* push.b ${Dsp-16-u16}[sb] */
16413   {
16414     M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "push.b", 32,
16415     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16416   },
16417 /* push.b ${Dsp-16-s8}[fb] */
16418   {
16419     M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "push.b", 24,
16420     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16421   },
16422 /* push.b ${Dsp-16-s16}[fb] */
16423   {
16424     M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "push.b", 32,
16425     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16426   },
16427 /* push.b ${Dsp-16-u16} */
16428   {
16429     M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "push.b", 32,
16430     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16431   },
16432 /* push.b ${Dsp-16-u24} */
16433   {
16434     M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "push.b", 40,
16435     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16436   },
16437 /* push.w $Dst16RnHI */
16438   {
16439     M32C_INSN_PUSH16_W_16_DST16_RN_DIRECT_HI, "push16.w-16-dst16-Rn-direct-HI", "push.w", 16,
16440     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16441   },
16442 /* push.w $Dst16AnHI */
16443   {
16444     M32C_INSN_PUSH16_W_16_DST16_AN_DIRECT_HI, "push16.w-16-dst16-An-direct-HI", "push.w", 16,
16445     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16446   },
16447 /* push.w [$Dst16An] */
16448   {
16449     M32C_INSN_PUSH16_W_16_DST16_AN_INDIRECT_HI, "push16.w-16-dst16-An-indirect-HI", "push.w", 16,
16450     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16451   },
16452 /* push.w ${Dsp-16-u8}[$Dst16An] */
16453   {
16454     M32C_INSN_PUSH16_W_16_DST16_16_8_AN_RELATIVE_HI, "push16.w-16-dst16-16-8-An-relative-HI", "push.w", 24,
16455     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16456   },
16457 /* push.w ${Dsp-16-u16}[$Dst16An] */
16458   {
16459     M32C_INSN_PUSH16_W_16_DST16_16_16_AN_RELATIVE_HI, "push16.w-16-dst16-16-16-An-relative-HI", "push.w", 32,
16460     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16461   },
16462 /* push.w ${Dsp-16-u8}[sb] */
16463   {
16464     M32C_INSN_PUSH16_W_16_DST16_16_8_SB_RELATIVE_HI, "push16.w-16-dst16-16-8-SB-relative-HI", "push.w", 24,
16465     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16466   },
16467 /* push.w ${Dsp-16-u16}[sb] */
16468   {
16469     M32C_INSN_PUSH16_W_16_DST16_16_16_SB_RELATIVE_HI, "push16.w-16-dst16-16-16-SB-relative-HI", "push.w", 32,
16470     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16471   },
16472 /* push.w ${Dsp-16-s8}[fb] */
16473   {
16474     M32C_INSN_PUSH16_W_16_DST16_16_8_FB_RELATIVE_HI, "push16.w-16-dst16-16-8-FB-relative-HI", "push.w", 24,
16475     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16476   },
16477 /* push.w ${Dsp-16-u16} */
16478   {
16479     M32C_INSN_PUSH16_W_16_DST16_16_16_ABSOLUTE_HI, "push16.w-16-dst16-16-16-absolute-HI", "push.w", 32,
16480     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16481   },
16482 /* push.b $Dst16RnQI */
16483   {
16484     M32C_INSN_PUSH16_B_16_DST16_RN_DIRECT_QI, "push16.b-16-dst16-Rn-direct-QI", "push.b", 16,
16485     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16486   },
16487 /* push.b $Dst16AnQI */
16488   {
16489     M32C_INSN_PUSH16_B_16_DST16_AN_DIRECT_QI, "push16.b-16-dst16-An-direct-QI", "push.b", 16,
16490     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16491   },
16492 /* push.b [$Dst16An] */
16493   {
16494     M32C_INSN_PUSH16_B_16_DST16_AN_INDIRECT_QI, "push16.b-16-dst16-An-indirect-QI", "push.b", 16,
16495     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16496   },
16497 /* push.b ${Dsp-16-u8}[$Dst16An] */
16498   {
16499     M32C_INSN_PUSH16_B_16_DST16_16_8_AN_RELATIVE_QI, "push16.b-16-dst16-16-8-An-relative-QI", "push.b", 24,
16500     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16501   },
16502 /* push.b ${Dsp-16-u16}[$Dst16An] */
16503   {
16504     M32C_INSN_PUSH16_B_16_DST16_16_16_AN_RELATIVE_QI, "push16.b-16-dst16-16-16-An-relative-QI", "push.b", 32,
16505     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16506   },
16507 /* push.b ${Dsp-16-u8}[sb] */
16508   {
16509     M32C_INSN_PUSH16_B_16_DST16_16_8_SB_RELATIVE_QI, "push16.b-16-dst16-16-8-SB-relative-QI", "push.b", 24,
16510     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16511   },
16512 /* push.b ${Dsp-16-u16}[sb] */
16513   {
16514     M32C_INSN_PUSH16_B_16_DST16_16_16_SB_RELATIVE_QI, "push16.b-16-dst16-16-16-SB-relative-QI", "push.b", 32,
16515     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16516   },
16517 /* push.b ${Dsp-16-s8}[fb] */
16518   {
16519     M32C_INSN_PUSH16_B_16_DST16_16_8_FB_RELATIVE_QI, "push16.b-16-dst16-16-8-FB-relative-QI", "push.b", 24,
16520     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16521   },
16522 /* push.b ${Dsp-16-u16} */
16523   {
16524     M32C_INSN_PUSH16_B_16_DST16_16_16_ABSOLUTE_QI, "push16.b-16-dst16-16-16-absolute-QI", "push.b", 32,
16525     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16526   },
16527 /* pop.w${S} ${An16-push-S} */
16528   {
16529     M32C_INSN_POP16_B_S_AN_AN16_PUSH_S_DERIVED, "pop16.b-s-an-An16-push-S-derived", "pop.w", 8,
16530     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16531   },
16532 /* pop.b${S} ${Rn16-push-S} */
16533   {
16534     M32C_INSN_POP16_B_S_RN_RN16_PUSH_S_DERIVED, "pop16.b-s-rn-Rn16-push-S-derived", "pop.b", 8,
16535     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16536   },
16537 /* pop.w $Dst32RnUnprefixedHI */
16538   {
16539     M32C_INSN_POP32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "pop.w", 16,
16540     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16541   },
16542 /* pop.w $Dst32AnUnprefixedHI */
16543   {
16544     M32C_INSN_POP32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "pop.w", 16,
16545     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16546   },
16547 /* pop.w [$Dst32AnUnprefixed] */
16548   {
16549     M32C_INSN_POP32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "pop.w", 16,
16550     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16551   },
16552 /* pop.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
16553   {
16554     M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "pop.w", 24,
16555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16556   },
16557 /* pop.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
16558   {
16559     M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "pop.w", 32,
16560     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16561   },
16562 /* pop.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
16563   {
16564     M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "pop.w", 40,
16565     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16566   },
16567 /* pop.w ${Dsp-16-u8}[sb] */
16568   {
16569     M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "pop.w", 24,
16570     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16571   },
16572 /* pop.w ${Dsp-16-u16}[sb] */
16573   {
16574     M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "pop.w", 32,
16575     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16576   },
16577 /* pop.w ${Dsp-16-s8}[fb] */
16578   {
16579     M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "pop.w", 24,
16580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16581   },
16582 /* pop.w ${Dsp-16-s16}[fb] */
16583   {
16584     M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "pop.w", 32,
16585     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16586   },
16587 /* pop.w ${Dsp-16-u16} */
16588   {
16589     M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "pop.w", 32,
16590     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16591   },
16592 /* pop.w ${Dsp-16-u24} */
16593   {
16594     M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "pop.w", 40,
16595     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16596   },
16597 /* pop.b $Dst32RnUnprefixedQI */
16598   {
16599     M32C_INSN_POP32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "pop.b", 16,
16600     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16601   },
16602 /* pop.b $Dst32AnUnprefixedQI */
16603   {
16604     M32C_INSN_POP32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "pop.b", 16,
16605     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16606   },
16607 /* pop.b [$Dst32AnUnprefixed] */
16608   {
16609     M32C_INSN_POP32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "pop.b", 16,
16610     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16611   },
16612 /* pop.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
16613   {
16614     M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "pop.b", 24,
16615     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16616   },
16617 /* pop.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
16618   {
16619     M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "pop.b", 32,
16620     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16621   },
16622 /* pop.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
16623   {
16624     M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "pop.b", 40,
16625     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16626   },
16627 /* pop.b ${Dsp-16-u8}[sb] */
16628   {
16629     M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "pop.b", 24,
16630     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16631   },
16632 /* pop.b ${Dsp-16-u16}[sb] */
16633   {
16634     M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "pop.b", 32,
16635     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16636   },
16637 /* pop.b ${Dsp-16-s8}[fb] */
16638   {
16639     M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "pop.b", 24,
16640     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16641   },
16642 /* pop.b ${Dsp-16-s16}[fb] */
16643   {
16644     M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "pop.b", 32,
16645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16646   },
16647 /* pop.b ${Dsp-16-u16} */
16648   {
16649     M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "pop.b", 32,
16650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16651   },
16652 /* pop.b ${Dsp-16-u24} */
16653   {
16654     M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "pop.b", 40,
16655     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16656   },
16657 /* pop.w $Dst16RnHI */
16658   {
16659     M32C_INSN_POP16_W_16_DST16_RN_DIRECT_HI, "pop16.w-16-dst16-Rn-direct-HI", "pop.w", 16,
16660     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16661   },
16662 /* pop.w $Dst16AnHI */
16663   {
16664     M32C_INSN_POP16_W_16_DST16_AN_DIRECT_HI, "pop16.w-16-dst16-An-direct-HI", "pop.w", 16,
16665     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16666   },
16667 /* pop.w [$Dst16An] */
16668   {
16669     M32C_INSN_POP16_W_16_DST16_AN_INDIRECT_HI, "pop16.w-16-dst16-An-indirect-HI", "pop.w", 16,
16670     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16671   },
16672 /* pop.w ${Dsp-16-u8}[$Dst16An] */
16673   {
16674     M32C_INSN_POP16_W_16_DST16_16_8_AN_RELATIVE_HI, "pop16.w-16-dst16-16-8-An-relative-HI", "pop.w", 24,
16675     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16676   },
16677 /* pop.w ${Dsp-16-u16}[$Dst16An] */
16678   {
16679     M32C_INSN_POP16_W_16_DST16_16_16_AN_RELATIVE_HI, "pop16.w-16-dst16-16-16-An-relative-HI", "pop.w", 32,
16680     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16681   },
16682 /* pop.w ${Dsp-16-u8}[sb] */
16683   {
16684     M32C_INSN_POP16_W_16_DST16_16_8_SB_RELATIVE_HI, "pop16.w-16-dst16-16-8-SB-relative-HI", "pop.w", 24,
16685     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16686   },
16687 /* pop.w ${Dsp-16-u16}[sb] */
16688   {
16689     M32C_INSN_POP16_W_16_DST16_16_16_SB_RELATIVE_HI, "pop16.w-16-dst16-16-16-SB-relative-HI", "pop.w", 32,
16690     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16691   },
16692 /* pop.w ${Dsp-16-s8}[fb] */
16693   {
16694     M32C_INSN_POP16_W_16_DST16_16_8_FB_RELATIVE_HI, "pop16.w-16-dst16-16-8-FB-relative-HI", "pop.w", 24,
16695     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16696   },
16697 /* pop.w ${Dsp-16-u16} */
16698   {
16699     M32C_INSN_POP16_W_16_DST16_16_16_ABSOLUTE_HI, "pop16.w-16-dst16-16-16-absolute-HI", "pop.w", 32,
16700     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16701   },
16702 /* pop.b $Dst16RnQI */
16703   {
16704     M32C_INSN_POP16_B_16_DST16_RN_DIRECT_QI, "pop16.b-16-dst16-Rn-direct-QI", "pop.b", 16,
16705     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16706   },
16707 /* pop.b $Dst16AnQI */
16708   {
16709     M32C_INSN_POP16_B_16_DST16_AN_DIRECT_QI, "pop16.b-16-dst16-An-direct-QI", "pop.b", 16,
16710     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16711   },
16712 /* pop.b [$Dst16An] */
16713   {
16714     M32C_INSN_POP16_B_16_DST16_AN_INDIRECT_QI, "pop16.b-16-dst16-An-indirect-QI", "pop.b", 16,
16715     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16716   },
16717 /* pop.b ${Dsp-16-u8}[$Dst16An] */
16718   {
16719     M32C_INSN_POP16_B_16_DST16_16_8_AN_RELATIVE_QI, "pop16.b-16-dst16-16-8-An-relative-QI", "pop.b", 24,
16720     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16721   },
16722 /* pop.b ${Dsp-16-u16}[$Dst16An] */
16723   {
16724     M32C_INSN_POP16_B_16_DST16_16_16_AN_RELATIVE_QI, "pop16.b-16-dst16-16-16-An-relative-QI", "pop.b", 32,
16725     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16726   },
16727 /* pop.b ${Dsp-16-u8}[sb] */
16728   {
16729     M32C_INSN_POP16_B_16_DST16_16_8_SB_RELATIVE_QI, "pop16.b-16-dst16-16-8-SB-relative-QI", "pop.b", 24,
16730     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16731   },
16732 /* pop.b ${Dsp-16-u16}[sb] */
16733   {
16734     M32C_INSN_POP16_B_16_DST16_16_16_SB_RELATIVE_QI, "pop16.b-16-dst16-16-16-SB-relative-QI", "pop.b", 32,
16735     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16736   },
16737 /* pop.b ${Dsp-16-s8}[fb] */
16738   {
16739     M32C_INSN_POP16_B_16_DST16_16_8_FB_RELATIVE_QI, "pop16.b-16-dst16-16-8-FB-relative-QI", "pop.b", 24,
16740     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16741   },
16742 /* pop.b ${Dsp-16-u16} */
16743   {
16744     M32C_INSN_POP16_B_16_DST16_16_16_ABSOLUTE_QI, "pop16.b-16-dst16-16-16-absolute-QI", "pop.b", 32,
16745     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16746   },
16747 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
16748   {
16749     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 24,
16750     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16751   },
16752 /* or.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
16753   {
16754     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 24,
16755     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16756   },
16757 /* or.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
16758   {
16759     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 24,
16760     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16761   },
16762 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
16763   {
16764     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 24,
16765     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16766   },
16767 /* or.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
16768   {
16769     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 24,
16770     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16771   },
16772 /* or.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
16773   {
16774     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 24,
16775     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16776   },
16777 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
16778   {
16779     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 24,
16780     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16781   },
16782 /* or.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
16783   {
16784     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 24,
16785     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16786   },
16787 /* or.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
16788   {
16789     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 24,
16790     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16791   },
16792 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
16793   {
16794     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "or.w", 32,
16795     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16796   },
16797 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
16798   {
16799     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "or.w", 32,
16800     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16801   },
16802 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
16803   {
16804     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "or.w", 32,
16805     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16806   },
16807 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
16808   {
16809     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "or.w", 40,
16810     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16811   },
16812 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
16813   {
16814     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "or.w", 40,
16815     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16816   },
16817 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
16818   {
16819     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "or.w", 40,
16820     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16821   },
16822 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
16823   {
16824     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "or.w", 48,
16825     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16826   },
16827 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
16828   {
16829     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "or.w", 48,
16830     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16831   },
16832 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
16833   {
16834     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "or.w", 48,
16835     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16836   },
16837 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
16838   {
16839     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "or.w", 32,
16840     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16841   },
16842 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
16843   {
16844     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "or.w", 32,
16845     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16846   },
16847 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
16848   {
16849     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "or.w", 32,
16850     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16851   },
16852 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
16853   {
16854     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "or.w", 40,
16855     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16856   },
16857 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
16858   {
16859     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "or.w", 40,
16860     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16861   },
16862 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
16863   {
16864     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "or.w", 40,
16865     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16866   },
16867 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
16868   {
16869     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "or.w", 32,
16870     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16871   },
16872 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
16873   {
16874     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "or.w", 32,
16875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16876   },
16877 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
16878   {
16879     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "or.w", 32,
16880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16881   },
16882 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
16883   {
16884     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "or.w", 40,
16885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16886   },
16887 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
16888   {
16889     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "or.w", 40,
16890     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16891   },
16892 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
16893   {
16894     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "or.w", 40,
16895     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16896   },
16897 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
16898   {
16899     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "or.w", 40,
16900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16901   },
16902 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
16903   {
16904     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "or.w", 40,
16905     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16906   },
16907 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
16908   {
16909     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "or.w", 40,
16910     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16911   },
16912 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
16913   {
16914     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "or.w", 48,
16915     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16916   },
16917 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
16918   {
16919     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "or.w", 48,
16920     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16921   },
16922 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
16923   {
16924     M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "or.w", 48,
16925     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16926   },
16927 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
16928   {
16929     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 32,
16930     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16931   },
16932 /* or.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
16933   {
16934     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 32,
16935     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16936   },
16937 /* or.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
16938   {
16939     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 32,
16940     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16941   },
16942 /* or.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
16943   {
16944     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 32,
16945     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16946   },
16947 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
16948   {
16949     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 32,
16950     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16951   },
16952 /* or.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
16953   {
16954     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 32,
16955     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16956   },
16957 /* or.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
16958   {
16959     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 32,
16960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16961   },
16962 /* or.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
16963   {
16964     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 32,
16965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16966   },
16967 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
16968   {
16969     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 32,
16970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16971   },
16972 /* or.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
16973   {
16974     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 32,
16975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16976   },
16977 /* or.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
16978   {
16979     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 32,
16980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16981   },
16982 /* or.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
16983   {
16984     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 32,
16985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16986   },
16987 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
16988   {
16989     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "or.w", 40,
16990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16991   },
16992 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
16993   {
16994     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "or.w", 40,
16995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16996   },
16997 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
16998   {
16999     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "or.w", 40,
17000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17001   },
17002 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
17003   {
17004     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "or.w", 40,
17005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17006   },
17007 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
17008   {
17009     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "or.w", 48,
17010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17011   },
17012 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
17013   {
17014     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "or.w", 48,
17015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17016   },
17017 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
17018   {
17019     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "or.w", 48,
17020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17021   },
17022 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
17023   {
17024     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "or.w", 48,
17025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17026   },
17027 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
17028   {
17029     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "or.w", 56,
17030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17031   },
17032 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
17033   {
17034     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "or.w", 56,
17035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17036   },
17037 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
17038   {
17039     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "or.w", 56,
17040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17041   },
17042 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
17043   {
17044     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "or.w", 56,
17045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17046   },
17047 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
17048   {
17049     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "or.w", 40,
17050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17051   },
17052 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
17053   {
17054     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "or.w", 40,
17055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17056   },
17057 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
17058   {
17059     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "or.w", 40,
17060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17061   },
17062 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
17063   {
17064     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "or.w", 40,
17065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17066   },
17067 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
17068   {
17069     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "or.w", 48,
17070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17071   },
17072 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
17073   {
17074     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "or.w", 48,
17075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17076   },
17077 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
17078   {
17079     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "or.w", 48,
17080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17081   },
17082 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
17083   {
17084     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "or.w", 48,
17085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17086   },
17087 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
17088   {
17089     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "or.w", 40,
17090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17091   },
17092 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
17093   {
17094     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "or.w", 40,
17095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17096   },
17097 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
17098   {
17099     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "or.w", 40,
17100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17101   },
17102 /* or.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
17103   {
17104     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "or.w", 40,
17105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17106   },
17107 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
17108   {
17109     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "or.w", 48,
17110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17111   },
17112 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
17113   {
17114     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "or.w", 48,
17115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17116   },
17117 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
17118   {
17119     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "or.w", 48,
17120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17121   },
17122 /* or.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
17123   {
17124     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "or.w", 48,
17125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17126   },
17127 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
17128   {
17129     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "or.w", 48,
17130     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17131   },
17132 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
17133   {
17134     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "or.w", 48,
17135     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17136   },
17137 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
17138   {
17139     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "or.w", 48,
17140     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17141   },
17142 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
17143   {
17144     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "or.w", 48,
17145     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17146   },
17147 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
17148   {
17149     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "or.w", 56,
17150     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17151   },
17152 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
17153   {
17154     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "or.w", 56,
17155     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17156   },
17157 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
17158   {
17159     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "or.w", 56,
17160     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17161   },
17162 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
17163   {
17164     M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "or.w", 56,
17165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17166   },
17167 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
17168   {
17169     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 40,
17170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17171   },
17172 /* or.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
17173   {
17174     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 40,
17175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17176   },
17177 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
17178   {
17179     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 40,
17180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17181   },
17182 /* or.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
17183   {
17184     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 40,
17185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17186   },
17187 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
17188   {
17189     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 40,
17190     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17191   },
17192 /* or.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
17193   {
17194     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 40,
17195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17196   },
17197 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
17198   {
17199     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "or.w", 48,
17200     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17201   },
17202 /* or.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
17203   {
17204     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "or.w", 48,
17205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17206   },
17207 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
17208   {
17209     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "or.w", 56,
17210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17211   },
17212 /* or.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
17213   {
17214     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "or.w", 56,
17215     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17216   },
17217 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
17218   {
17219     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "or.w", 64,
17220     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17221   },
17222 /* or.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
17223   {
17224     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "or.w", 64,
17225     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17226   },
17227 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
17228   {
17229     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "or.w", 48,
17230     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17231   },
17232 /* or.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
17233   {
17234     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "or.w", 48,
17235     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17236   },
17237 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
17238   {
17239     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "or.w", 56,
17240     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17241   },
17242 /* or.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
17243   {
17244     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "or.w", 56,
17245     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17246   },
17247 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
17248   {
17249     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "or.w", 48,
17250     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17251   },
17252 /* or.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
17253   {
17254     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "or.w", 48,
17255     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17256   },
17257 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
17258   {
17259     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "or.w", 56,
17260     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17261   },
17262 /* or.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
17263   {
17264     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "or.w", 56,
17265     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17266   },
17267 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
17268   {
17269     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "or.w", 56,
17270     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17271   },
17272 /* or.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
17273   {
17274     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "or.w", 56,
17275     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17276   },
17277 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
17278   {
17279     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "or.w", 64,
17280     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17281   },
17282 /* or.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
17283   {
17284     M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "or.w", 64,
17285     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17286   },
17287 /* or.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
17288   {
17289     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 16,
17290     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17291   },
17292 /* or.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
17293   {
17294     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 16,
17295     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17296   },
17297 /* or.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
17298   {
17299     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 16,
17300     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17301   },
17302 /* or.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
17303   {
17304     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 16,
17305     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17306   },
17307 /* or.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
17308   {
17309     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 16,
17310     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17311   },
17312 /* or.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
17313   {
17314     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 16,
17315     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17316   },
17317 /* or.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
17318   {
17319     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 16,
17320     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17321   },
17322 /* or.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
17323   {
17324     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 16,
17325     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17326   },
17327 /* or.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
17328   {
17329     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 16,
17330     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17331   },
17332 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
17333   {
17334     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "or.w", 24,
17335     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17336   },
17337 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
17338   {
17339     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "or.w", 24,
17340     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17341   },
17342 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
17343   {
17344     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "or.w", 24,
17345     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17346   },
17347 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
17348   {
17349     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "or.w", 32,
17350     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17351   },
17352 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
17353   {
17354     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "or.w", 32,
17355     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17356   },
17357 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
17358   {
17359     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "or.w", 32,
17360     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17361   },
17362 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
17363   {
17364     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "or.w", 40,
17365     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17366   },
17367 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
17368   {
17369     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "or.w", 40,
17370     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17371   },
17372 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
17373   {
17374     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "or.w", 40,
17375     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17376   },
17377 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
17378   {
17379     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "or.w", 24,
17380     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17381   },
17382 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
17383   {
17384     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "or.w", 24,
17385     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17386   },
17387 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
17388   {
17389     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "or.w", 24,
17390     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17391   },
17392 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
17393   {
17394     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "or.w", 32,
17395     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17396   },
17397 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
17398   {
17399     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "or.w", 32,
17400     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17401   },
17402 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
17403   {
17404     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "or.w", 32,
17405     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17406   },
17407 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
17408   {
17409     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "or.w", 24,
17410     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17411   },
17412 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
17413   {
17414     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "or.w", 24,
17415     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17416   },
17417 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
17418   {
17419     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "or.w", 24,
17420     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17421   },
17422 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
17423   {
17424     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "or.w", 32,
17425     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17426   },
17427 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
17428   {
17429     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "or.w", 32,
17430     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17431   },
17432 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
17433   {
17434     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "or.w", 32,
17435     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17436   },
17437 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
17438   {
17439     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "or.w", 32,
17440     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17441   },
17442 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
17443   {
17444     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "or.w", 32,
17445     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17446   },
17447 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
17448   {
17449     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "or.w", 32,
17450     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17451   },
17452 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
17453   {
17454     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "or.w", 40,
17455     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17456   },
17457 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
17458   {
17459     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "or.w", 40,
17460     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17461   },
17462 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
17463   {
17464     M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "or.w", 40,
17465     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17466   },
17467 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
17468   {
17469     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 24,
17470     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17471   },
17472 /* or.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
17473   {
17474     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 24,
17475     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17476   },
17477 /* or.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
17478   {
17479     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 24,
17480     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17481   },
17482 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
17483   {
17484     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 24,
17485     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17486   },
17487 /* or.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
17488   {
17489     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 24,
17490     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17491   },
17492 /* or.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
17493   {
17494     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 24,
17495     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17496   },
17497 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
17498   {
17499     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 24,
17500     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17501   },
17502 /* or.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
17503   {
17504     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 24,
17505     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17506   },
17507 /* or.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
17508   {
17509     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 24,
17510     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17511   },
17512 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
17513   {
17514     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "or.b", 32,
17515     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17516   },
17517 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
17518   {
17519     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "or.b", 32,
17520     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17521   },
17522 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
17523   {
17524     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "or.b", 32,
17525     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17526   },
17527 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
17528   {
17529     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "or.b", 40,
17530     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17531   },
17532 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
17533   {
17534     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "or.b", 40,
17535     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17536   },
17537 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
17538   {
17539     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "or.b", 40,
17540     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17541   },
17542 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
17543   {
17544     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "or.b", 48,
17545     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17546   },
17547 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
17548   {
17549     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "or.b", 48,
17550     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17551   },
17552 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
17553   {
17554     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "or.b", 48,
17555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17556   },
17557 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
17558   {
17559     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "or.b", 32,
17560     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17561   },
17562 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
17563   {
17564     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "or.b", 32,
17565     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17566   },
17567 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
17568   {
17569     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "or.b", 32,
17570     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17571   },
17572 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
17573   {
17574     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "or.b", 40,
17575     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17576   },
17577 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
17578   {
17579     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "or.b", 40,
17580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17581   },
17582 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
17583   {
17584     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "or.b", 40,
17585     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17586   },
17587 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
17588   {
17589     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "or.b", 32,
17590     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17591   },
17592 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
17593   {
17594     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "or.b", 32,
17595     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17596   },
17597 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
17598   {
17599     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "or.b", 32,
17600     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17601   },
17602 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
17603   {
17604     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "or.b", 40,
17605     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17606   },
17607 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
17608   {
17609     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "or.b", 40,
17610     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17611   },
17612 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
17613   {
17614     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "or.b", 40,
17615     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17616   },
17617 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
17618   {
17619     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "or.b", 40,
17620     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17621   },
17622 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
17623   {
17624     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "or.b", 40,
17625     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17626   },
17627 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
17628   {
17629     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "or.b", 40,
17630     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17631   },
17632 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
17633   {
17634     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "or.b", 48,
17635     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17636   },
17637 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
17638   {
17639     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "or.b", 48,
17640     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17641   },
17642 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
17643   {
17644     M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "or.b", 48,
17645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17646   },
17647 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
17648   {
17649     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 32,
17650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17651   },
17652 /* or.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
17653   {
17654     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 32,
17655     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17656   },
17657 /* or.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
17658   {
17659     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 32,
17660     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17661   },
17662 /* or.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
17663   {
17664     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 32,
17665     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17666   },
17667 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
17668   {
17669     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 32,
17670     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17671   },
17672 /* or.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
17673   {
17674     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 32,
17675     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17676   },
17677 /* or.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
17678   {
17679     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 32,
17680     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17681   },
17682 /* or.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
17683   {
17684     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 32,
17685     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17686   },
17687 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
17688   {
17689     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 32,
17690     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17691   },
17692 /* or.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
17693   {
17694     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 32,
17695     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17696   },
17697 /* or.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
17698   {
17699     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 32,
17700     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17701   },
17702 /* or.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
17703   {
17704     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 32,
17705     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17706   },
17707 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
17708   {
17709     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "or.b", 40,
17710     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17711   },
17712 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
17713   {
17714     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "or.b", 40,
17715     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17716   },
17717 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
17718   {
17719     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "or.b", 40,
17720     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17721   },
17722 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
17723   {
17724     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "or.b", 40,
17725     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17726   },
17727 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
17728   {
17729     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "or.b", 48,
17730     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17731   },
17732 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
17733   {
17734     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "or.b", 48,
17735     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17736   },
17737 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
17738   {
17739     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "or.b", 48,
17740     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17741   },
17742 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
17743   {
17744     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "or.b", 48,
17745     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17746   },
17747 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
17748   {
17749     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "or.b", 56,
17750     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17751   },
17752 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
17753   {
17754     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "or.b", 56,
17755     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17756   },
17757 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
17758   {
17759     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "or.b", 56,
17760     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17761   },
17762 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
17763   {
17764     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "or.b", 56,
17765     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17766   },
17767 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
17768   {
17769     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "or.b", 40,
17770     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17771   },
17772 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
17773   {
17774     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "or.b", 40,
17775     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17776   },
17777 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
17778   {
17779     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "or.b", 40,
17780     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17781   },
17782 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
17783   {
17784     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "or.b", 40,
17785     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17786   },
17787 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
17788   {
17789     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "or.b", 48,
17790     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17791   },
17792 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
17793   {
17794     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "or.b", 48,
17795     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17796   },
17797 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
17798   {
17799     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "or.b", 48,
17800     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17801   },
17802 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
17803   {
17804     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "or.b", 48,
17805     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17806   },
17807 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
17808   {
17809     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "or.b", 40,
17810     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17811   },
17812 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
17813   {
17814     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "or.b", 40,
17815     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17816   },
17817 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
17818   {
17819     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "or.b", 40,
17820     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17821   },
17822 /* or.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
17823   {
17824     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "or.b", 40,
17825     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17826   },
17827 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
17828   {
17829     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "or.b", 48,
17830     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17831   },
17832 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
17833   {
17834     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "or.b", 48,
17835     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17836   },
17837 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
17838   {
17839     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "or.b", 48,
17840     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17841   },
17842 /* or.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
17843   {
17844     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "or.b", 48,
17845     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17846   },
17847 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
17848   {
17849     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "or.b", 48,
17850     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17851   },
17852 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
17853   {
17854     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "or.b", 48,
17855     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17856   },
17857 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
17858   {
17859     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "or.b", 48,
17860     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17861   },
17862 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
17863   {
17864     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "or.b", 48,
17865     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17866   },
17867 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
17868   {
17869     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "or.b", 56,
17870     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17871   },
17872 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
17873   {
17874     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "or.b", 56,
17875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17876   },
17877 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
17878   {
17879     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "or.b", 56,
17880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17881   },
17882 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
17883   {
17884     M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "or.b", 56,
17885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17886   },
17887 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
17888   {
17889     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 40,
17890     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17891   },
17892 /* or.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
17893   {
17894     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 40,
17895     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17896   },
17897 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
17898   {
17899     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 40,
17900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17901   },
17902 /* or.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
17903   {
17904     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 40,
17905     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17906   },
17907 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
17908   {
17909     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 40,
17910     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17911   },
17912 /* or.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
17913   {
17914     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 40,
17915     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17916   },
17917 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
17918   {
17919     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "or.b", 48,
17920     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17921   },
17922 /* or.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
17923   {
17924     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "or.b", 48,
17925     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17926   },
17927 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
17928   {
17929     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "or.b", 56,
17930     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17931   },
17932 /* or.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
17933   {
17934     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "or.b", 56,
17935     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17936   },
17937 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
17938   {
17939     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "or.b", 64,
17940     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17941   },
17942 /* or.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
17943   {
17944     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "or.b", 64,
17945     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17946   },
17947 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
17948   {
17949     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "or.b", 48,
17950     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17951   },
17952 /* or.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
17953   {
17954     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "or.b", 48,
17955     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17956   },
17957 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
17958   {
17959     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "or.b", 56,
17960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17961   },
17962 /* or.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
17963   {
17964     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "or.b", 56,
17965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17966   },
17967 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
17968   {
17969     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "or.b", 48,
17970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17971   },
17972 /* or.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
17973   {
17974     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "or.b", 48,
17975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17976   },
17977 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
17978   {
17979     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "or.b", 56,
17980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17981   },
17982 /* or.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
17983   {
17984     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "or.b", 56,
17985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17986   },
17987 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
17988   {
17989     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "or.b", 56,
17990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17991   },
17992 /* or.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
17993   {
17994     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "or.b", 56,
17995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17996   },
17997 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
17998   {
17999     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "or.b", 64,
18000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18001   },
18002 /* or.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
18003   {
18004     M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "or.b", 64,
18005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18006   },
18007 /* or.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
18008   {
18009     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 16,
18010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18011   },
18012 /* or.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
18013   {
18014     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 16,
18015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18016   },
18017 /* or.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
18018   {
18019     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 16,
18020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18021   },
18022 /* or.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
18023   {
18024     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 16,
18025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18026   },
18027 /* or.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
18028   {
18029     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 16,
18030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18031   },
18032 /* or.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
18033   {
18034     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 16,
18035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18036   },
18037 /* or.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
18038   {
18039     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 16,
18040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18041   },
18042 /* or.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
18043   {
18044     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 16,
18045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18046   },
18047 /* or.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
18048   {
18049     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 16,
18050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18051   },
18052 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
18053   {
18054     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "or.b", 24,
18055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18056   },
18057 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
18058   {
18059     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "or.b", 24,
18060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18061   },
18062 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
18063   {
18064     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "or.b", 24,
18065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18066   },
18067 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
18068   {
18069     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "or.b", 32,
18070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18071   },
18072 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
18073   {
18074     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "or.b", 32,
18075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18076   },
18077 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
18078   {
18079     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "or.b", 32,
18080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18081   },
18082 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
18083   {
18084     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "or.b", 40,
18085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18086   },
18087 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
18088   {
18089     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "or.b", 40,
18090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18091   },
18092 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
18093   {
18094     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "or.b", 40,
18095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18096   },
18097 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
18098   {
18099     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "or.b", 24,
18100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18101   },
18102 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
18103   {
18104     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "or.b", 24,
18105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18106   },
18107 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
18108   {
18109     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "or.b", 24,
18110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18111   },
18112 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
18113   {
18114     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "or.b", 32,
18115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18116   },
18117 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
18118   {
18119     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "or.b", 32,
18120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18121   },
18122 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
18123   {
18124     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "or.b", 32,
18125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18126   },
18127 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
18128   {
18129     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "or.b", 24,
18130     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18131   },
18132 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
18133   {
18134     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "or.b", 24,
18135     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18136   },
18137 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
18138   {
18139     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "or.b", 24,
18140     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18141   },
18142 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
18143   {
18144     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "or.b", 32,
18145     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18146   },
18147 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
18148   {
18149     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "or.b", 32,
18150     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18151   },
18152 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
18153   {
18154     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "or.b", 32,
18155     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18156   },
18157 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
18158   {
18159     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "or.b", 32,
18160     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18161   },
18162 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
18163   {
18164     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "or.b", 32,
18165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18166   },
18167 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
18168   {
18169     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "or.b", 32,
18170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18171   },
18172 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
18173   {
18174     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "or.b", 40,
18175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18176   },
18177 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
18178   {
18179     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "or.b", 40,
18180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18181   },
18182 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
18183   {
18184     M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "or.b", 40,
18185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18186   },
18187 /* or.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
18188   {
18189     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "or.w", 24,
18190     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18191   },
18192 /* or.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
18193   {
18194     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "or.w", 24,
18195     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18196   },
18197 /* or.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
18198   {
18199     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "or.w", 24,
18200     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18201   },
18202 /* or.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
18203   {
18204     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "or.w", 24,
18205     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18206   },
18207 /* or.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
18208   {
18209     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "or.w", 24,
18210     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18211   },
18212 /* or.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
18213   {
18214     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "or.w", 24,
18215     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18216   },
18217 /* or.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
18218   {
18219     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "or.w", 24,
18220     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18221   },
18222 /* or.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
18223   {
18224     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "or.w", 24,
18225     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18226   },
18227 /* or.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
18228   {
18229     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "or.w", 24,
18230     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18231   },
18232 /* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
18233   {
18234     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "or.w", 32,
18235     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18236   },
18237 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
18238   {
18239     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "or.w", 32,
18240     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18241   },
18242 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
18243   {
18244     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "or.w", 32,
18245     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18246   },
18247 /* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
18248   {
18249     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "or.w", 40,
18250     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18251   },
18252 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
18253   {
18254     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "or.w", 40,
18255     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18256   },
18257 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
18258   {
18259     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "or.w", 40,
18260     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18261   },
18262 /* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
18263   {
18264     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "or.w", 32,
18265     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18266   },
18267 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
18268   {
18269     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "or.w", 32,
18270     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18271   },
18272 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
18273   {
18274     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "or.w", 32,
18275     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18276   },
18277 /* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
18278   {
18279     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "or.w", 40,
18280     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18281   },
18282 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
18283   {
18284     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "or.w", 40,
18285     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18286   },
18287 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
18288   {
18289     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "or.w", 40,
18290     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18291   },
18292 /* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
18293   {
18294     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "or.w", 32,
18295     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18296   },
18297 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
18298   {
18299     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "or.w", 32,
18300     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18301   },
18302 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
18303   {
18304     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "or.w", 32,
18305     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18306   },
18307 /* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
18308   {
18309     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "or.w", 40,
18310     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18311   },
18312 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
18313   {
18314     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "or.w", 40,
18315     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18316   },
18317 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
18318   {
18319     M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "or.w", 40,
18320     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18321   },
18322 /* or.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
18323   {
18324     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "or.w", 32,
18325     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18326   },
18327 /* or.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
18328   {
18329     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "or.w", 32,
18330     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18331   },
18332 /* or.w${G} ${Dsp-16-u16},$Dst16RnHI */
18333   {
18334     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "or.w", 32,
18335     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18336   },
18337 /* or.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
18338   {
18339     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "or.w", 32,
18340     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18341   },
18342 /* or.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
18343   {
18344     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "or.w", 32,
18345     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18346   },
18347 /* or.w${G} ${Dsp-16-u16},$Dst16AnHI */
18348   {
18349     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "or.w", 32,
18350     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18351   },
18352 /* or.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
18353   {
18354     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "or.w", 32,
18355     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18356   },
18357 /* or.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
18358   {
18359     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "or.w", 32,
18360     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18361   },
18362 /* or.w${G} ${Dsp-16-u16},[$Dst16An] */
18363   {
18364     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "or.w", 32,
18365     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18366   },
18367 /* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
18368   {
18369     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "or.w", 40,
18370     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18371   },
18372 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
18373   {
18374     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "or.w", 40,
18375     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18376   },
18377 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
18378   {
18379     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "or.w", 40,
18380     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18381   },
18382 /* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
18383   {
18384     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "or.w", 48,
18385     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18386   },
18387 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
18388   {
18389     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "or.w", 48,
18390     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18391   },
18392 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
18393   {
18394     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "or.w", 48,
18395     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18396   },
18397 /* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
18398   {
18399     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "or.w", 40,
18400     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18401   },
18402 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
18403   {
18404     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "or.w", 40,
18405     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18406   },
18407 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
18408   {
18409     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "or.w", 40,
18410     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18411   },
18412 /* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
18413   {
18414     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "or.w", 48,
18415     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18416   },
18417 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
18418   {
18419     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "or.w", 48,
18420     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18421   },
18422 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
18423   {
18424     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "or.w", 48,
18425     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18426   },
18427 /* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
18428   {
18429     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "or.w", 40,
18430     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18431   },
18432 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
18433   {
18434     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "or.w", 40,
18435     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18436   },
18437 /* or.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
18438   {
18439     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "or.w", 40,
18440     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18441   },
18442 /* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
18443   {
18444     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "or.w", 48,
18445     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18446   },
18447 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
18448   {
18449     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "or.w", 48,
18450     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18451   },
18452 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
18453   {
18454     M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "or.w", 48,
18455     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18456   },
18457 /* or.w${G} $Src16RnHI,$Dst16RnHI */
18458   {
18459     M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "or.w", 16,
18460     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18461   },
18462 /* or.w${G} $Src16AnHI,$Dst16RnHI */
18463   {
18464     M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "or.w", 16,
18465     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18466   },
18467 /* or.w${G} [$Src16An],$Dst16RnHI */
18468   {
18469     M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "or.w", 16,
18470     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18471   },
18472 /* or.w${G} $Src16RnHI,$Dst16AnHI */
18473   {
18474     M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "or.w", 16,
18475     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18476   },
18477 /* or.w${G} $Src16AnHI,$Dst16AnHI */
18478   {
18479     M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "or.w", 16,
18480     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18481   },
18482 /* or.w${G} [$Src16An],$Dst16AnHI */
18483   {
18484     M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "or.w", 16,
18485     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18486   },
18487 /* or.w${G} $Src16RnHI,[$Dst16An] */
18488   {
18489     M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "or.w", 16,
18490     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18491   },
18492 /* or.w${G} $Src16AnHI,[$Dst16An] */
18493   {
18494     M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "or.w", 16,
18495     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18496   },
18497 /* or.w${G} [$Src16An],[$Dst16An] */
18498   {
18499     M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "or.w", 16,
18500     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18501   },
18502 /* or.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
18503   {
18504     M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "or.w", 24,
18505     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18506   },
18507 /* or.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
18508   {
18509     M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "or.w", 24,
18510     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18511   },
18512 /* or.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
18513   {
18514     M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "or.w", 24,
18515     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18516   },
18517 /* or.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
18518   {
18519     M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "or.w", 32,
18520     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18521   },
18522 /* or.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
18523   {
18524     M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "or.w", 32,
18525     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18526   },
18527 /* or.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
18528   {
18529     M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "or.w", 32,
18530     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18531   },
18532 /* or.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
18533   {
18534     M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "or.w", 24,
18535     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18536   },
18537 /* or.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
18538   {
18539     M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "or.w", 24,
18540     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18541   },
18542 /* or.w${G} [$Src16An],${Dsp-16-u8}[sb] */
18543   {
18544     M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "or.w", 24,
18545     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18546   },
18547 /* or.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
18548   {
18549     M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "or.w", 32,
18550     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18551   },
18552 /* or.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
18553   {
18554     M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "or.w", 32,
18555     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18556   },
18557 /* or.w${G} [$Src16An],${Dsp-16-u16}[sb] */
18558   {
18559     M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "or.w", 32,
18560     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18561   },
18562 /* or.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
18563   {
18564     M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "or.w", 24,
18565     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18566   },
18567 /* or.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
18568   {
18569     M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "or.w", 24,
18570     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18571   },
18572 /* or.w${G} [$Src16An],${Dsp-16-s8}[fb] */
18573   {
18574     M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "or.w", 24,
18575     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18576   },
18577 /* or.w${G} $Src16RnHI,${Dsp-16-u16} */
18578   {
18579     M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "or.w", 32,
18580     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18581   },
18582 /* or.w${G} $Src16AnHI,${Dsp-16-u16} */
18583   {
18584     M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "or.w", 32,
18585     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18586   },
18587 /* or.w${G} [$Src16An],${Dsp-16-u16} */
18588   {
18589     M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "or.w", 32,
18590     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18591   },
18592 /* or.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
18593   {
18594     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "or.b", 24,
18595     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18596   },
18597 /* or.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
18598   {
18599     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "or.b", 24,
18600     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18601   },
18602 /* or.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
18603   {
18604     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "or.b", 24,
18605     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18606   },
18607 /* or.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
18608   {
18609     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "or.b", 24,
18610     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18611   },
18612 /* or.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
18613   {
18614     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "or.b", 24,
18615     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18616   },
18617 /* or.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
18618   {
18619     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "or.b", 24,
18620     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18621   },
18622 /* or.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
18623   {
18624     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "or.b", 24,
18625     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18626   },
18627 /* or.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
18628   {
18629     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "or.b", 24,
18630     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18631   },
18632 /* or.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
18633   {
18634     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "or.b", 24,
18635     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18636   },
18637 /* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
18638   {
18639     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "or.b", 32,
18640     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18641   },
18642 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
18643   {
18644     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "or.b", 32,
18645     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18646   },
18647 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
18648   {
18649     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "or.b", 32,
18650     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18651   },
18652 /* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
18653   {
18654     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "or.b", 40,
18655     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18656   },
18657 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
18658   {
18659     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "or.b", 40,
18660     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18661   },
18662 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
18663   {
18664     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "or.b", 40,
18665     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18666   },
18667 /* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
18668   {
18669     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "or.b", 32,
18670     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18671   },
18672 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
18673   {
18674     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "or.b", 32,
18675     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18676   },
18677 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
18678   {
18679     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "or.b", 32,
18680     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18681   },
18682 /* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
18683   {
18684     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "or.b", 40,
18685     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18686   },
18687 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
18688   {
18689     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "or.b", 40,
18690     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18691   },
18692 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
18693   {
18694     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "or.b", 40,
18695     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18696   },
18697 /* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
18698   {
18699     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "or.b", 32,
18700     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18701   },
18702 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
18703   {
18704     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "or.b", 32,
18705     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18706   },
18707 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
18708   {
18709     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "or.b", 32,
18710     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18711   },
18712 /* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
18713   {
18714     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "or.b", 40,
18715     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18716   },
18717 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
18718   {
18719     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "or.b", 40,
18720     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18721   },
18722 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
18723   {
18724     M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "or.b", 40,
18725     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18726   },
18727 /* or.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
18728   {
18729     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "or.b", 32,
18730     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18731   },
18732 /* or.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
18733   {
18734     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "or.b", 32,
18735     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18736   },
18737 /* or.b${G} ${Dsp-16-u16},$Dst16RnQI */
18738   {
18739     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "or.b", 32,
18740     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18741   },
18742 /* or.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
18743   {
18744     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "or.b", 32,
18745     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18746   },
18747 /* or.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
18748   {
18749     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "or.b", 32,
18750     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18751   },
18752 /* or.b${G} ${Dsp-16-u16},$Dst16AnQI */
18753   {
18754     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "or.b", 32,
18755     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18756   },
18757 /* or.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
18758   {
18759     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "or.b", 32,
18760     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18761   },
18762 /* or.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
18763   {
18764     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "or.b", 32,
18765     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18766   },
18767 /* or.b${G} ${Dsp-16-u16},[$Dst16An] */
18768   {
18769     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "or.b", 32,
18770     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18771   },
18772 /* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
18773   {
18774     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "or.b", 40,
18775     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18776   },
18777 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
18778   {
18779     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "or.b", 40,
18780     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18781   },
18782 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
18783   {
18784     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "or.b", 40,
18785     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18786   },
18787 /* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
18788   {
18789     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "or.b", 48,
18790     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18791   },
18792 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
18793   {
18794     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "or.b", 48,
18795     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18796   },
18797 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
18798   {
18799     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "or.b", 48,
18800     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18801   },
18802 /* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
18803   {
18804     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "or.b", 40,
18805     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18806   },
18807 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
18808   {
18809     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "or.b", 40,
18810     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18811   },
18812 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
18813   {
18814     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "or.b", 40,
18815     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18816   },
18817 /* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
18818   {
18819     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "or.b", 48,
18820     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18821   },
18822 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
18823   {
18824     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "or.b", 48,
18825     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18826   },
18827 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
18828   {
18829     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "or.b", 48,
18830     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18831   },
18832 /* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
18833   {
18834     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "or.b", 40,
18835     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18836   },
18837 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
18838   {
18839     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "or.b", 40,
18840     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18841   },
18842 /* or.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
18843   {
18844     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "or.b", 40,
18845     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18846   },
18847 /* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
18848   {
18849     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "or.b", 48,
18850     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18851   },
18852 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
18853   {
18854     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "or.b", 48,
18855     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18856   },
18857 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
18858   {
18859     M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "or.b", 48,
18860     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18861   },
18862 /* or.b${G} $Src16RnQI,$Dst16RnQI */
18863   {
18864     M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "or.b", 16,
18865     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18866   },
18867 /* or.b${G} $Src16AnQI,$Dst16RnQI */
18868   {
18869     M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "or.b", 16,
18870     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18871   },
18872 /* or.b${G} [$Src16An],$Dst16RnQI */
18873   {
18874     M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "or.b", 16,
18875     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18876   },
18877 /* or.b${G} $Src16RnQI,$Dst16AnQI */
18878   {
18879     M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "or.b", 16,
18880     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18881   },
18882 /* or.b${G} $Src16AnQI,$Dst16AnQI */
18883   {
18884     M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "or.b", 16,
18885     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18886   },
18887 /* or.b${G} [$Src16An],$Dst16AnQI */
18888   {
18889     M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "or.b", 16,
18890     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18891   },
18892 /* or.b${G} $Src16RnQI,[$Dst16An] */
18893   {
18894     M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "or.b", 16,
18895     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18896   },
18897 /* or.b${G} $Src16AnQI,[$Dst16An] */
18898   {
18899     M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "or.b", 16,
18900     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18901   },
18902 /* or.b${G} [$Src16An],[$Dst16An] */
18903   {
18904     M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "or.b", 16,
18905     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18906   },
18907 /* or.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
18908   {
18909     M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "or.b", 24,
18910     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18911   },
18912 /* or.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
18913   {
18914     M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "or.b", 24,
18915     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18916   },
18917 /* or.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
18918   {
18919     M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "or.b", 24,
18920     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18921   },
18922 /* or.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
18923   {
18924     M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "or.b", 32,
18925     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18926   },
18927 /* or.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
18928   {
18929     M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "or.b", 32,
18930     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18931   },
18932 /* or.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
18933   {
18934     M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "or.b", 32,
18935     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18936   },
18937 /* or.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
18938   {
18939     M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "or.b", 24,
18940     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18941   },
18942 /* or.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
18943   {
18944     M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "or.b", 24,
18945     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18946   },
18947 /* or.b${G} [$Src16An],${Dsp-16-u8}[sb] */
18948   {
18949     M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "or.b", 24,
18950     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18951   },
18952 /* or.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
18953   {
18954     M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "or.b", 32,
18955     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18956   },
18957 /* or.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
18958   {
18959     M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "or.b", 32,
18960     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18961   },
18962 /* or.b${G} [$Src16An],${Dsp-16-u16}[sb] */
18963   {
18964     M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "or.b", 32,
18965     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18966   },
18967 /* or.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
18968   {
18969     M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "or.b", 24,
18970     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18971   },
18972 /* or.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
18973   {
18974     M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "or.b", 24,
18975     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18976   },
18977 /* or.b${G} [$Src16An],${Dsp-16-s8}[fb] */
18978   {
18979     M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "or.b", 24,
18980     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18981   },
18982 /* or.b${G} $Src16RnQI,${Dsp-16-u16} */
18983   {
18984     M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "or.b", 32,
18985     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18986   },
18987 /* or.b${G} $Src16AnQI,${Dsp-16-u16} */
18988   {
18989     M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "or.b", 32,
18990     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18991   },
18992 /* or.b${G} [$Src16An],${Dsp-16-u16} */
18993   {
18994     M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "or.b", 32,
18995     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18996   },
18997 /* or.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
18998   {
18999     M32C_INSN_OR32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "or32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "or.w", 32,
19000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19001   },
19002 /* or.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
19003   {
19004     M32C_INSN_OR32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "or32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "or.w", 32,
19005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19006   },
19007 /* or.w${S} #${Imm-24-HI},${Dsp-8-u16} */
19008   {
19009     M32C_INSN_OR32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "or32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "or.w", 40,
19010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19011   },
19012 /* or.w${S} #${Imm-8-HI},r0 */
19013   {
19014     M32C_INSN_OR32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "or32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "or.w", 24,
19015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19016   },
19017 /* or.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
19018   {
19019     M32C_INSN_OR32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "or32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "or.b", 24,
19020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19021   },
19022 /* or.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
19023   {
19024     M32C_INSN_OR32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "or32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "or.b", 24,
19025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19026   },
19027 /* or.b${S} #${Imm-24-QI},${Dsp-8-u16} */
19028   {
19029     M32C_INSN_OR32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "or32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "or.b", 32,
19030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19031   },
19032 /* or.b${S} #${Imm-8-QI},r0l */
19033   {
19034     M32C_INSN_OR32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "or32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "or.b", 16,
19035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19036   },
19037 /* or.b${S} #${Imm-8-QI},r0l */
19038   {
19039     M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "or16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "or.b", 16,
19040     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19041   },
19042 /* or.b${S} #${Imm-8-QI},r0h */
19043   {
19044     M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "or16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "or.b", 16,
19045     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19046   },
19047 /* or.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
19048   {
19049     M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "or16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "or.b", 24,
19050     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19051   },
19052 /* or.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
19053   {
19054     M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "or16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "or.b", 24,
19055     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19056   },
19057 /* or.b${S} #${Imm-8-QI},${Dsp-16-u16} */
19058   {
19059     M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "or16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "or.b", 32,
19060     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19061   },
19062 /* or.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
19063   {
19064     M32C_INSN_OR32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "or.w", 32,
19065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19066   },
19067 /* or.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
19068   {
19069     M32C_INSN_OR32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "or.w", 32,
19070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19071   },
19072 /* or.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
19073   {
19074     M32C_INSN_OR32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "or.w", 32,
19075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19076   },
19077 /* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
19078   {
19079     M32C_INSN_OR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "or.w", 40,
19080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19081   },
19082 /* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
19083   {
19084     M32C_INSN_OR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "or.w", 40,
19085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19086   },
19087 /* or.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
19088   {
19089     M32C_INSN_OR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "or.w", 40,
19090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19091   },
19092 /* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
19093   {
19094     M32C_INSN_OR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "or.w", 48,
19095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19096   },
19097 /* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
19098   {
19099     M32C_INSN_OR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "or.w", 48,
19100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19101   },
19102 /* or.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
19103   {
19104     M32C_INSN_OR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "or.w", 48,
19105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19106   },
19107 /* or.w${G} #${Imm-32-HI},${Dsp-16-u16} */
19108   {
19109     M32C_INSN_OR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "or.w", 48,
19110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19111   },
19112 /* or.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
19113   {
19114     M32C_INSN_OR32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "or.w", 56,
19115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19116   },
19117 /* or.w${G} #${Imm-40-HI},${Dsp-16-u24} */
19118   {
19119     M32C_INSN_OR32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "or.w", 56,
19120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19121   },
19122 /* or.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
19123   {
19124     M32C_INSN_OR32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "or.b", 24,
19125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19126   },
19127 /* or.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
19128   {
19129     M32C_INSN_OR32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "or.b", 24,
19130     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19131   },
19132 /* or.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
19133   {
19134     M32C_INSN_OR32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "or.b", 24,
19135     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19136   },
19137 /* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
19138   {
19139     M32C_INSN_OR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "or.b", 32,
19140     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19141   },
19142 /* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
19143   {
19144     M32C_INSN_OR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "or.b", 32,
19145     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19146   },
19147 /* or.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
19148   {
19149     M32C_INSN_OR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "or.b", 32,
19150     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19151   },
19152 /* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
19153   {
19154     M32C_INSN_OR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "or.b", 40,
19155     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19156   },
19157 /* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
19158   {
19159     M32C_INSN_OR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "or.b", 40,
19160     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19161   },
19162 /* or.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
19163   {
19164     M32C_INSN_OR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "or.b", 40,
19165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19166   },
19167 /* or.b${G} #${Imm-32-QI},${Dsp-16-u16} */
19168   {
19169     M32C_INSN_OR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "or.b", 40,
19170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19171   },
19172 /* or.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
19173   {
19174     M32C_INSN_OR32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "or.b", 48,
19175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19176   },
19177 /* or.b${G} #${Imm-40-QI},${Dsp-16-u24} */
19178   {
19179     M32C_INSN_OR32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "or.b", 48,
19180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19181   },
19182 /* or.w${G} #${Imm-16-HI},$Dst16RnHI */
19183   {
19184     M32C_INSN_OR16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "or16.w-imm-G-basic-dst16-Rn-direct-HI", "or.w", 32,
19185     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19186   },
19187 /* or.w${G} #${Imm-16-HI},$Dst16AnHI */
19188   {
19189     M32C_INSN_OR16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "or16.w-imm-G-basic-dst16-An-direct-HI", "or.w", 32,
19190     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19191   },
19192 /* or.w${G} #${Imm-16-HI},[$Dst16An] */
19193   {
19194     M32C_INSN_OR16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "or16.w-imm-G-basic-dst16-An-indirect-HI", "or.w", 32,
19195     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19196   },
19197 /* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
19198   {
19199     M32C_INSN_OR16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "or16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "or.w", 40,
19200     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19201   },
19202 /* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
19203   {
19204     M32C_INSN_OR16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "or16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "or.w", 40,
19205     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19206   },
19207 /* or.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
19208   {
19209     M32C_INSN_OR16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "or16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "or.w", 40,
19210     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19211   },
19212 /* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
19213   {
19214     M32C_INSN_OR16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "or16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "or.w", 48,
19215     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19216   },
19217 /* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
19218   {
19219     M32C_INSN_OR16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "or16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "or.w", 48,
19220     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19221   },
19222 /* or.w${G} #${Imm-32-HI},${Dsp-16-u16} */
19223   {
19224     M32C_INSN_OR16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "or16.w-imm-G-16-16-dst16-16-16-absolute-HI", "or.w", 48,
19225     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19226   },
19227 /* or.b${G} #${Imm-16-QI},$Dst16RnQI */
19228   {
19229     M32C_INSN_OR16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "or16.b-imm-G-basic-dst16-Rn-direct-QI", "or.b", 24,
19230     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19231   },
19232 /* or.b${G} #${Imm-16-QI},$Dst16AnQI */
19233   {
19234     M32C_INSN_OR16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "or16.b-imm-G-basic-dst16-An-direct-QI", "or.b", 24,
19235     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19236   },
19237 /* or.b${G} #${Imm-16-QI},[$Dst16An] */
19238   {
19239     M32C_INSN_OR16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "or16.b-imm-G-basic-dst16-An-indirect-QI", "or.b", 24,
19240     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19241   },
19242 /* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
19243   {
19244     M32C_INSN_OR16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "or16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "or.b", 32,
19245     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19246   },
19247 /* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
19248   {
19249     M32C_INSN_OR16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "or16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "or.b", 32,
19250     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19251   },
19252 /* or.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
19253   {
19254     M32C_INSN_OR16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "or16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "or.b", 32,
19255     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19256   },
19257 /* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
19258   {
19259     M32C_INSN_OR16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "or16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "or.b", 40,
19260     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19261   },
19262 /* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
19263   {
19264     M32C_INSN_OR16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "or16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "or.b", 40,
19265     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19266   },
19267 /* or.b${G} #${Imm-32-QI},${Dsp-16-u16} */
19268   {
19269     M32C_INSN_OR16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "or16.b-imm-G-16-16-dst16-16-16-absolute-QI", "or.b", 40,
19270     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19271   },
19272 /* not.w $Dst32RnUnprefixedHI */
19273   {
19274     M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "not.w", 16,
19275     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19276   },
19277 /* not.w $Dst32AnUnprefixedHI */
19278   {
19279     M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "not.w", 16,
19280     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19281   },
19282 /* not.w [$Dst32AnUnprefixed] */
19283   {
19284     M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "not.w", 16,
19285     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19286   },
19287 /* not.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
19288   {
19289     M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "not.w", 24,
19290     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19291   },
19292 /* not.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
19293   {
19294     M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "not.w", 32,
19295     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19296   },
19297 /* not.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
19298   {
19299     M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "not.w", 40,
19300     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19301   },
19302 /* not.w ${Dsp-16-u8}[sb] */
19303   {
19304     M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "not.w", 24,
19305     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19306   },
19307 /* not.w ${Dsp-16-u16}[sb] */
19308   {
19309     M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "not.w", 32,
19310     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19311   },
19312 /* not.w ${Dsp-16-s8}[fb] */
19313   {
19314     M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "not.w", 24,
19315     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19316   },
19317 /* not.w ${Dsp-16-s16}[fb] */
19318   {
19319     M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "not.w", 32,
19320     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19321   },
19322 /* not.w ${Dsp-16-u16} */
19323   {
19324     M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "not.w", 32,
19325     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19326   },
19327 /* not.w ${Dsp-16-u24} */
19328   {
19329     M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "not.w", 40,
19330     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19331   },
19332 /* not.b $Dst32RnUnprefixedQI */
19333   {
19334     M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "not.b", 16,
19335     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19336   },
19337 /* not.b $Dst32AnUnprefixedQI */
19338   {
19339     M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "not.b", 16,
19340     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19341   },
19342 /* not.b [$Dst32AnUnprefixed] */
19343   {
19344     M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "not.b", 16,
19345     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19346   },
19347 /* not.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
19348   {
19349     M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "not.b", 24,
19350     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19351   },
19352 /* not.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
19353   {
19354     M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "not.b", 32,
19355     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19356   },
19357 /* not.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
19358   {
19359     M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "not.b", 40,
19360     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19361   },
19362 /* not.b ${Dsp-16-u8}[sb] */
19363   {
19364     M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "not.b", 24,
19365     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19366   },
19367 /* not.b ${Dsp-16-u16}[sb] */
19368   {
19369     M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "not.b", 32,
19370     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19371   },
19372 /* not.b ${Dsp-16-s8}[fb] */
19373   {
19374     M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "not.b", 24,
19375     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19376   },
19377 /* not.b ${Dsp-16-s16}[fb] */
19378   {
19379     M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "not.b", 32,
19380     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19381   },
19382 /* not.b ${Dsp-16-u16} */
19383   {
19384     M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "not.b", 32,
19385     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19386   },
19387 /* not.b ${Dsp-16-u24} */
19388   {
19389     M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "not.b", 40,
19390     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19391   },
19392 /* not.w $Dst16RnHI */
19393   {
19394     M32C_INSN_NOT16_W_16_DST16_RN_DIRECT_HI, "not16.w-16-dst16-Rn-direct-HI", "not.w", 16,
19395     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19396   },
19397 /* not.w $Dst16AnHI */
19398   {
19399     M32C_INSN_NOT16_W_16_DST16_AN_DIRECT_HI, "not16.w-16-dst16-An-direct-HI", "not.w", 16,
19400     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19401   },
19402 /* not.w [$Dst16An] */
19403   {
19404     M32C_INSN_NOT16_W_16_DST16_AN_INDIRECT_HI, "not16.w-16-dst16-An-indirect-HI", "not.w", 16,
19405     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19406   },
19407 /* not.w ${Dsp-16-u8}[$Dst16An] */
19408   {
19409     M32C_INSN_NOT16_W_16_DST16_16_8_AN_RELATIVE_HI, "not16.w-16-dst16-16-8-An-relative-HI", "not.w", 24,
19410     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19411   },
19412 /* not.w ${Dsp-16-u16}[$Dst16An] */
19413   {
19414     M32C_INSN_NOT16_W_16_DST16_16_16_AN_RELATIVE_HI, "not16.w-16-dst16-16-16-An-relative-HI", "not.w", 32,
19415     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19416   },
19417 /* not.w ${Dsp-16-u8}[sb] */
19418   {
19419     M32C_INSN_NOT16_W_16_DST16_16_8_SB_RELATIVE_HI, "not16.w-16-dst16-16-8-SB-relative-HI", "not.w", 24,
19420     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19421   },
19422 /* not.w ${Dsp-16-u16}[sb] */
19423   {
19424     M32C_INSN_NOT16_W_16_DST16_16_16_SB_RELATIVE_HI, "not16.w-16-dst16-16-16-SB-relative-HI", "not.w", 32,
19425     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19426   },
19427 /* not.w ${Dsp-16-s8}[fb] */
19428   {
19429     M32C_INSN_NOT16_W_16_DST16_16_8_FB_RELATIVE_HI, "not16.w-16-dst16-16-8-FB-relative-HI", "not.w", 24,
19430     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19431   },
19432 /* not.w ${Dsp-16-u16} */
19433   {
19434     M32C_INSN_NOT16_W_16_DST16_16_16_ABSOLUTE_HI, "not16.w-16-dst16-16-16-absolute-HI", "not.w", 32,
19435     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19436   },
19437 /* not.b $Dst16RnQI */
19438   {
19439     M32C_INSN_NOT16_B_16_DST16_RN_DIRECT_QI, "not16.b-16-dst16-Rn-direct-QI", "not.b", 16,
19440     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19441   },
19442 /* not.b $Dst16AnQI */
19443   {
19444     M32C_INSN_NOT16_B_16_DST16_AN_DIRECT_QI, "not16.b-16-dst16-An-direct-QI", "not.b", 16,
19445     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19446   },
19447 /* not.b [$Dst16An] */
19448   {
19449     M32C_INSN_NOT16_B_16_DST16_AN_INDIRECT_QI, "not16.b-16-dst16-An-indirect-QI", "not.b", 16,
19450     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19451   },
19452 /* not.b ${Dsp-16-u8}[$Dst16An] */
19453   {
19454     M32C_INSN_NOT16_B_16_DST16_16_8_AN_RELATIVE_QI, "not16.b-16-dst16-16-8-An-relative-QI", "not.b", 24,
19455     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19456   },
19457 /* not.b ${Dsp-16-u16}[$Dst16An] */
19458   {
19459     M32C_INSN_NOT16_B_16_DST16_16_16_AN_RELATIVE_QI, "not16.b-16-dst16-16-16-An-relative-QI", "not.b", 32,
19460     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19461   },
19462 /* not.b ${Dsp-16-u8}[sb] */
19463   {
19464     M32C_INSN_NOT16_B_16_DST16_16_8_SB_RELATIVE_QI, "not16.b-16-dst16-16-8-SB-relative-QI", "not.b", 24,
19465     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19466   },
19467 /* not.b ${Dsp-16-u16}[sb] */
19468   {
19469     M32C_INSN_NOT16_B_16_DST16_16_16_SB_RELATIVE_QI, "not16.b-16-dst16-16-16-SB-relative-QI", "not.b", 32,
19470     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19471   },
19472 /* not.b ${Dsp-16-s8}[fb] */
19473   {
19474     M32C_INSN_NOT16_B_16_DST16_16_8_FB_RELATIVE_QI, "not16.b-16-dst16-16-8-FB-relative-QI", "not.b", 24,
19475     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19476   },
19477 /* not.b ${Dsp-16-u16} */
19478   {
19479     M32C_INSN_NOT16_B_16_DST16_16_16_ABSOLUTE_QI, "not16.b-16-dst16-16-16-absolute-QI", "not.b", 32,
19480     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19481   },
19482 /* neg.w $Dst32RnUnprefixedHI */
19483   {
19484     M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "neg.w", 16,
19485     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19486   },
19487 /* neg.w $Dst32AnUnprefixedHI */
19488   {
19489     M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "neg.w", 16,
19490     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19491   },
19492 /* neg.w [$Dst32AnUnprefixed] */
19493   {
19494     M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "neg.w", 16,
19495     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19496   },
19497 /* neg.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
19498   {
19499     M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "neg.w", 24,
19500     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19501   },
19502 /* neg.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
19503   {
19504     M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "neg.w", 32,
19505     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19506   },
19507 /* neg.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
19508   {
19509     M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "neg.w", 40,
19510     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19511   },
19512 /* neg.w ${Dsp-16-u8}[sb] */
19513   {
19514     M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "neg.w", 24,
19515     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19516   },
19517 /* neg.w ${Dsp-16-u16}[sb] */
19518   {
19519     M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "neg.w", 32,
19520     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19521   },
19522 /* neg.w ${Dsp-16-s8}[fb] */
19523   {
19524     M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "neg.w", 24,
19525     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19526   },
19527 /* neg.w ${Dsp-16-s16}[fb] */
19528   {
19529     M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "neg.w", 32,
19530     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19531   },
19532 /* neg.w ${Dsp-16-u16} */
19533   {
19534     M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "neg.w", 32,
19535     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19536   },
19537 /* neg.w ${Dsp-16-u24} */
19538   {
19539     M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "neg.w", 40,
19540     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19541   },
19542 /* neg.b $Dst32RnUnprefixedQI */
19543   {
19544     M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "neg.b", 16,
19545     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19546   },
19547 /* neg.b $Dst32AnUnprefixedQI */
19548   {
19549     M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "neg.b", 16,
19550     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19551   },
19552 /* neg.b [$Dst32AnUnprefixed] */
19553   {
19554     M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "neg.b", 16,
19555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19556   },
19557 /* neg.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
19558   {
19559     M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "neg.b", 24,
19560     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19561   },
19562 /* neg.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
19563   {
19564     M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "neg.b", 32,
19565     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19566   },
19567 /* neg.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
19568   {
19569     M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "neg.b", 40,
19570     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19571   },
19572 /* neg.b ${Dsp-16-u8}[sb] */
19573   {
19574     M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "neg.b", 24,
19575     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19576   },
19577 /* neg.b ${Dsp-16-u16}[sb] */
19578   {
19579     M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "neg.b", 32,
19580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19581   },
19582 /* neg.b ${Dsp-16-s8}[fb] */
19583   {
19584     M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "neg.b", 24,
19585     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19586   },
19587 /* neg.b ${Dsp-16-s16}[fb] */
19588   {
19589     M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "neg.b", 32,
19590     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19591   },
19592 /* neg.b ${Dsp-16-u16} */
19593   {
19594     M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "neg.b", 32,
19595     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19596   },
19597 /* neg.b ${Dsp-16-u24} */
19598   {
19599     M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "neg.b", 40,
19600     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19601   },
19602 /* neg.w $Dst16RnHI */
19603   {
19604     M32C_INSN_NEG16_W_16_DST16_RN_DIRECT_HI, "neg16.w-16-dst16-Rn-direct-HI", "neg.w", 16,
19605     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19606   },
19607 /* neg.w $Dst16AnHI */
19608   {
19609     M32C_INSN_NEG16_W_16_DST16_AN_DIRECT_HI, "neg16.w-16-dst16-An-direct-HI", "neg.w", 16,
19610     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19611   },
19612 /* neg.w [$Dst16An] */
19613   {
19614     M32C_INSN_NEG16_W_16_DST16_AN_INDIRECT_HI, "neg16.w-16-dst16-An-indirect-HI", "neg.w", 16,
19615     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19616   },
19617 /* neg.w ${Dsp-16-u8}[$Dst16An] */
19618   {
19619     M32C_INSN_NEG16_W_16_DST16_16_8_AN_RELATIVE_HI, "neg16.w-16-dst16-16-8-An-relative-HI", "neg.w", 24,
19620     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19621   },
19622 /* neg.w ${Dsp-16-u16}[$Dst16An] */
19623   {
19624     M32C_INSN_NEG16_W_16_DST16_16_16_AN_RELATIVE_HI, "neg16.w-16-dst16-16-16-An-relative-HI", "neg.w", 32,
19625     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19626   },
19627 /* neg.w ${Dsp-16-u8}[sb] */
19628   {
19629     M32C_INSN_NEG16_W_16_DST16_16_8_SB_RELATIVE_HI, "neg16.w-16-dst16-16-8-SB-relative-HI", "neg.w", 24,
19630     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19631   },
19632 /* neg.w ${Dsp-16-u16}[sb] */
19633   {
19634     M32C_INSN_NEG16_W_16_DST16_16_16_SB_RELATIVE_HI, "neg16.w-16-dst16-16-16-SB-relative-HI", "neg.w", 32,
19635     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19636   },
19637 /* neg.w ${Dsp-16-s8}[fb] */
19638   {
19639     M32C_INSN_NEG16_W_16_DST16_16_8_FB_RELATIVE_HI, "neg16.w-16-dst16-16-8-FB-relative-HI", "neg.w", 24,
19640     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19641   },
19642 /* neg.w ${Dsp-16-u16} */
19643   {
19644     M32C_INSN_NEG16_W_16_DST16_16_16_ABSOLUTE_HI, "neg16.w-16-dst16-16-16-absolute-HI", "neg.w", 32,
19645     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19646   },
19647 /* neg.b $Dst16RnQI */
19648   {
19649     M32C_INSN_NEG16_B_16_DST16_RN_DIRECT_QI, "neg16.b-16-dst16-Rn-direct-QI", "neg.b", 16,
19650     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19651   },
19652 /* neg.b $Dst16AnQI */
19653   {
19654     M32C_INSN_NEG16_B_16_DST16_AN_DIRECT_QI, "neg16.b-16-dst16-An-direct-QI", "neg.b", 16,
19655     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19656   },
19657 /* neg.b [$Dst16An] */
19658   {
19659     M32C_INSN_NEG16_B_16_DST16_AN_INDIRECT_QI, "neg16.b-16-dst16-An-indirect-QI", "neg.b", 16,
19660     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19661   },
19662 /* neg.b ${Dsp-16-u8}[$Dst16An] */
19663   {
19664     M32C_INSN_NEG16_B_16_DST16_16_8_AN_RELATIVE_QI, "neg16.b-16-dst16-16-8-An-relative-QI", "neg.b", 24,
19665     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19666   },
19667 /* neg.b ${Dsp-16-u16}[$Dst16An] */
19668   {
19669     M32C_INSN_NEG16_B_16_DST16_16_16_AN_RELATIVE_QI, "neg16.b-16-dst16-16-16-An-relative-QI", "neg.b", 32,
19670     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19671   },
19672 /* neg.b ${Dsp-16-u8}[sb] */
19673   {
19674     M32C_INSN_NEG16_B_16_DST16_16_8_SB_RELATIVE_QI, "neg16.b-16-dst16-16-8-SB-relative-QI", "neg.b", 24,
19675     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19676   },
19677 /* neg.b ${Dsp-16-u16}[sb] */
19678   {
19679     M32C_INSN_NEG16_B_16_DST16_16_16_SB_RELATIVE_QI, "neg16.b-16-dst16-16-16-SB-relative-QI", "neg.b", 32,
19680     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19681   },
19682 /* neg.b ${Dsp-16-s8}[fb] */
19683   {
19684     M32C_INSN_NEG16_B_16_DST16_16_8_FB_RELATIVE_QI, "neg16.b-16-dst16-16-8-FB-relative-QI", "neg.b", 24,
19685     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19686   },
19687 /* neg.b ${Dsp-16-u16} */
19688   {
19689     M32C_INSN_NEG16_B_16_DST16_16_16_ABSOLUTE_QI, "neg16.b-16-dst16-16-16-absolute-QI", "neg.b", 32,
19690     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19691   },
19692 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
19693   {
19694     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 24,
19695     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19696   },
19697 /* mulu.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
19698   {
19699     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 24,
19700     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19701   },
19702 /* mulu.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
19703   {
19704     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 24,
19705     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19706   },
19707 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
19708   {
19709     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 24,
19710     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19711   },
19712 /* mulu.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
19713   {
19714     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 24,
19715     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19716   },
19717 /* mulu.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
19718   {
19719     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 24,
19720     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19721   },
19722 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
19723   {
19724     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 24,
19725     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19726   },
19727 /* mulu.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
19728   {
19729     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 24,
19730     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19731   },
19732 /* mulu.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
19733   {
19734     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 24,
19735     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19736   },
19737 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
19738   {
19739     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mulu.w", 32,
19740     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19741   },
19742 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
19743   {
19744     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mulu.w", 32,
19745     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19746   },
19747 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
19748   {
19749     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mulu.w", 32,
19750     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19751   },
19752 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
19753   {
19754     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mulu.w", 40,
19755     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19756   },
19757 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
19758   {
19759     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mulu.w", 40,
19760     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19761   },
19762 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
19763   {
19764     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mulu.w", 40,
19765     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19766   },
19767 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
19768   {
19769     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mulu.w", 48,
19770     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19771   },
19772 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
19773   {
19774     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mulu.w", 48,
19775     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19776   },
19777 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
19778   {
19779     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mulu.w", 48,
19780     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19781   },
19782 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
19783   {
19784     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mulu.w", 32,
19785     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19786   },
19787 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
19788   {
19789     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mulu.w", 32,
19790     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19791   },
19792 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
19793   {
19794     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mulu.w", 32,
19795     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19796   },
19797 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
19798   {
19799     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mulu.w", 40,
19800     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19801   },
19802 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
19803   {
19804     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mulu.w", 40,
19805     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19806   },
19807 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
19808   {
19809     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mulu.w", 40,
19810     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19811   },
19812 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
19813   {
19814     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mulu.w", 32,
19815     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19816   },
19817 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
19818   {
19819     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mulu.w", 32,
19820     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19821   },
19822 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
19823   {
19824     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mulu.w", 32,
19825     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19826   },
19827 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
19828   {
19829     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mulu.w", 40,
19830     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19831   },
19832 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
19833   {
19834     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mulu.w", 40,
19835     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19836   },
19837 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
19838   {
19839     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mulu.w", 40,
19840     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19841   },
19842 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
19843   {
19844     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mulu.w", 40,
19845     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19846   },
19847 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
19848   {
19849     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mulu.w", 40,
19850     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19851   },
19852 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
19853   {
19854     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mulu.w", 40,
19855     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19856   },
19857 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
19858   {
19859     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mulu.w", 48,
19860     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19861   },
19862 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
19863   {
19864     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mulu.w", 48,
19865     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19866   },
19867 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
19868   {
19869     M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mulu.w", 48,
19870     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19871   },
19872 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
19873   {
19874     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32,
19875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19876   },
19877 /* mulu.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
19878   {
19879     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32,
19880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19881   },
19882 /* mulu.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
19883   {
19884     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32,
19885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19886   },
19887 /* mulu.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
19888   {
19889     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32,
19890     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19891   },
19892 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
19893   {
19894     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 32,
19895     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19896   },
19897 /* mulu.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
19898   {
19899     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 32,
19900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19901   },
19902 /* mulu.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
19903   {
19904     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 32,
19905     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19906   },
19907 /* mulu.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
19908   {
19909     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 32,
19910     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19911   },
19912 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
19913   {
19914     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32,
19915     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19916   },
19917 /* mulu.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
19918   {
19919     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32,
19920     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19921   },
19922 /* mulu.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
19923   {
19924     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32,
19925     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19926   },
19927 /* mulu.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
19928   {
19929     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32,
19930     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19931   },
19932 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
19933   {
19934     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mulu.w", 40,
19935     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19936   },
19937 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
19938   {
19939     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mulu.w", 40,
19940     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19941   },
19942 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
19943   {
19944     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mulu.w", 40,
19945     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19946   },
19947 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
19948   {
19949     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mulu.w", 40,
19950     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19951   },
19952 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
19953   {
19954     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mulu.w", 48,
19955     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19956   },
19957 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
19958   {
19959     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mulu.w", 48,
19960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19961   },
19962 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
19963   {
19964     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mulu.w", 48,
19965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19966   },
19967 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
19968   {
19969     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mulu.w", 48,
19970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19971   },
19972 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
19973   {
19974     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mulu.w", 56,
19975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19976   },
19977 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
19978   {
19979     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mulu.w", 56,
19980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19981   },
19982 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
19983   {
19984     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mulu.w", 56,
19985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19986   },
19987 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
19988   {
19989     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mulu.w", 56,
19990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19991   },
19992 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
19993   {
19994     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mulu.w", 40,
19995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19996   },
19997 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
19998   {
19999     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mulu.w", 40,
20000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20001   },
20002 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
20003   {
20004     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mulu.w", 40,
20005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20006   },
20007 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
20008   {
20009     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mulu.w", 40,
20010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20011   },
20012 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
20013   {
20014     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mulu.w", 48,
20015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20016   },
20017 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
20018   {
20019     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mulu.w", 48,
20020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20021   },
20022 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
20023   {
20024     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mulu.w", 48,
20025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20026   },
20027 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
20028   {
20029     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mulu.w", 48,
20030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20031   },
20032 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
20033   {
20034     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mulu.w", 40,
20035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20036   },
20037 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
20038   {
20039     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mulu.w", 40,
20040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20041   },
20042 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
20043   {
20044     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mulu.w", 40,
20045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20046   },
20047 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
20048   {
20049     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mulu.w", 40,
20050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20051   },
20052 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
20053   {
20054     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mulu.w", 48,
20055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20056   },
20057 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
20058   {
20059     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mulu.w", 48,
20060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20061   },
20062 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
20063   {
20064     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mulu.w", 48,
20065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20066   },
20067 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
20068   {
20069     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mulu.w", 48,
20070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20071   },
20072 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
20073   {
20074     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mulu.w", 48,
20075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20076   },
20077 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
20078   {
20079     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mulu.w", 48,
20080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20081   },
20082 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
20083   {
20084     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mulu.w", 48,
20085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20086   },
20087 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
20088   {
20089     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mulu.w", 48,
20090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20091   },
20092 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
20093   {
20094     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mulu.w", 56,
20095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20096   },
20097 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
20098   {
20099     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mulu.w", 56,
20100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20101   },
20102 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
20103   {
20104     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mulu.w", 56,
20105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20106   },
20107 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
20108   {
20109     M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mulu.w", 56,
20110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20111   },
20112 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
20113   {
20114     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 40,
20115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20116   },
20117 /* mulu.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
20118   {
20119     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 40,
20120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20121   },
20122 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
20123   {
20124     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 40,
20125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20126   },
20127 /* mulu.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
20128   {
20129     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 40,
20130     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20131   },
20132 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
20133   {
20134     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 40,
20135     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20136   },
20137 /* mulu.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
20138   {
20139     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 40,
20140     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20141   },
20142 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
20143   {
20144     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mulu.w", 48,
20145     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20146   },
20147 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
20148   {
20149     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mulu.w", 48,
20150     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20151   },
20152 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
20153   {
20154     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mulu.w", 56,
20155     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20156   },
20157 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
20158   {
20159     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mulu.w", 56,
20160     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20161   },
20162 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
20163   {
20164     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mulu.w", 64,
20165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20166   },
20167 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
20168   {
20169     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mulu.w", 64,
20170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20171   },
20172 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
20173   {
20174     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mulu.w", 48,
20175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20176   },
20177 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
20178   {
20179     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mulu.w", 48,
20180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20181   },
20182 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
20183   {
20184     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mulu.w", 56,
20185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20186   },
20187 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
20188   {
20189     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mulu.w", 56,
20190     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20191   },
20192 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
20193   {
20194     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mulu.w", 48,
20195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20196   },
20197 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
20198   {
20199     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mulu.w", 48,
20200     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20201   },
20202 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
20203   {
20204     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mulu.w", 56,
20205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20206   },
20207 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
20208   {
20209     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mulu.w", 56,
20210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20211   },
20212 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
20213   {
20214     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mulu.w", 56,
20215     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20216   },
20217 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
20218   {
20219     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mulu.w", 56,
20220     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20221   },
20222 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
20223   {
20224     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mulu.w", 64,
20225     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20226   },
20227 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
20228   {
20229     M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mulu.w", 64,
20230     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20231   },
20232 /* mulu.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
20233   {
20234     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 16,
20235     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20236   },
20237 /* mulu.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
20238   {
20239     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 16,
20240     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20241   },
20242 /* mulu.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
20243   {
20244     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 16,
20245     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20246   },
20247 /* mulu.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
20248   {
20249     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 16,
20250     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20251   },
20252 /* mulu.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
20253   {
20254     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 16,
20255     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20256   },
20257 /* mulu.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
20258   {
20259     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 16,
20260     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20261   },
20262 /* mulu.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
20263   {
20264     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 16,
20265     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20266   },
20267 /* mulu.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
20268   {
20269     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 16,
20270     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20271   },
20272 /* mulu.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
20273   {
20274     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 16,
20275     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20276   },
20277 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
20278   {
20279     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mulu.w", 24,
20280     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20281   },
20282 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
20283   {
20284     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mulu.w", 24,
20285     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20286   },
20287 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
20288   {
20289     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mulu.w", 24,
20290     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20291   },
20292 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
20293   {
20294     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mulu.w", 32,
20295     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20296   },
20297 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
20298   {
20299     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mulu.w", 32,
20300     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20301   },
20302 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
20303   {
20304     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mulu.w", 32,
20305     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20306   },
20307 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
20308   {
20309     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mulu.w", 40,
20310     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20311   },
20312 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
20313   {
20314     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mulu.w", 40,
20315     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20316   },
20317 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
20318   {
20319     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mulu.w", 40,
20320     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20321   },
20322 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
20323   {
20324     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mulu.w", 24,
20325     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20326   },
20327 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
20328   {
20329     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mulu.w", 24,
20330     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20331   },
20332 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
20333   {
20334     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mulu.w", 24,
20335     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20336   },
20337 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
20338   {
20339     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mulu.w", 32,
20340     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20341   },
20342 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
20343   {
20344     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mulu.w", 32,
20345     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20346   },
20347 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
20348   {
20349     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mulu.w", 32,
20350     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20351   },
20352 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
20353   {
20354     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mulu.w", 24,
20355     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20356   },
20357 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
20358   {
20359     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mulu.w", 24,
20360     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20361   },
20362 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
20363   {
20364     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mulu.w", 24,
20365     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20366   },
20367 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
20368   {
20369     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mulu.w", 32,
20370     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20371   },
20372 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
20373   {
20374     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mulu.w", 32,
20375     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20376   },
20377 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
20378   {
20379     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mulu.w", 32,
20380     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20381   },
20382 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
20383   {
20384     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mulu.w", 32,
20385     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20386   },
20387 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
20388   {
20389     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mulu.w", 32,
20390     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20391   },
20392 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
20393   {
20394     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mulu.w", 32,
20395     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20396   },
20397 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
20398   {
20399     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mulu.w", 40,
20400     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20401   },
20402 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
20403   {
20404     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mulu.w", 40,
20405     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20406   },
20407 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
20408   {
20409     M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mulu.w", 40,
20410     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20411   },
20412 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
20413   {
20414     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 24,
20415     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20416   },
20417 /* mulu.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
20418   {
20419     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 24,
20420     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20421   },
20422 /* mulu.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
20423   {
20424     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 24,
20425     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20426   },
20427 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
20428   {
20429     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 24,
20430     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20431   },
20432 /* mulu.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
20433   {
20434     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 24,
20435     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20436   },
20437 /* mulu.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
20438   {
20439     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 24,
20440     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20441   },
20442 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
20443   {
20444     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 24,
20445     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20446   },
20447 /* mulu.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
20448   {
20449     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 24,
20450     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20451   },
20452 /* mulu.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
20453   {
20454     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 24,
20455     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20456   },
20457 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
20458   {
20459     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mulu.b", 32,
20460     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20461   },
20462 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
20463   {
20464     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mulu.b", 32,
20465     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20466   },
20467 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
20468   {
20469     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mulu.b", 32,
20470     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20471   },
20472 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
20473   {
20474     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mulu.b", 40,
20475     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20476   },
20477 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
20478   {
20479     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mulu.b", 40,
20480     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20481   },
20482 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
20483   {
20484     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mulu.b", 40,
20485     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20486   },
20487 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
20488   {
20489     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mulu.b", 48,
20490     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20491   },
20492 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
20493   {
20494     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mulu.b", 48,
20495     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20496   },
20497 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
20498   {
20499     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mulu.b", 48,
20500     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20501   },
20502 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
20503   {
20504     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mulu.b", 32,
20505     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20506   },
20507 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
20508   {
20509     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mulu.b", 32,
20510     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20511   },
20512 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
20513   {
20514     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mulu.b", 32,
20515     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20516   },
20517 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
20518   {
20519     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mulu.b", 40,
20520     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20521   },
20522 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
20523   {
20524     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mulu.b", 40,
20525     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20526   },
20527 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
20528   {
20529     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mulu.b", 40,
20530     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20531   },
20532 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
20533   {
20534     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mulu.b", 32,
20535     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20536   },
20537 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
20538   {
20539     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mulu.b", 32,
20540     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20541   },
20542 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
20543   {
20544     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mulu.b", 32,
20545     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20546   },
20547 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
20548   {
20549     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mulu.b", 40,
20550     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20551   },
20552 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
20553   {
20554     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mulu.b", 40,
20555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20556   },
20557 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
20558   {
20559     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mulu.b", 40,
20560     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20561   },
20562 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
20563   {
20564     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mulu.b", 40,
20565     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20566   },
20567 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
20568   {
20569     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mulu.b", 40,
20570     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20571   },
20572 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
20573   {
20574     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mulu.b", 40,
20575     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20576   },
20577 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
20578   {
20579     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mulu.b", 48,
20580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20581   },
20582 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
20583   {
20584     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mulu.b", 48,
20585     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20586   },
20587 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
20588   {
20589     M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mulu.b", 48,
20590     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20591   },
20592 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
20593   {
20594     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 32,
20595     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20596   },
20597 /* mulu.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
20598   {
20599     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 32,
20600     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20601   },
20602 /* mulu.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
20603   {
20604     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 32,
20605     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20606   },
20607 /* mulu.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
20608   {
20609     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 32,
20610     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20611   },
20612 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
20613   {
20614     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 32,
20615     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20616   },
20617 /* mulu.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
20618   {
20619     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 32,
20620     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20621   },
20622 /* mulu.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
20623   {
20624     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 32,
20625     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20626   },
20627 /* mulu.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
20628   {
20629     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 32,
20630     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20631   },
20632 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
20633   {
20634     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 32,
20635     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20636   },
20637 /* mulu.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
20638   {
20639     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 32,
20640     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20641   },
20642 /* mulu.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
20643   {
20644     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 32,
20645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20646   },
20647 /* mulu.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
20648   {
20649     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 32,
20650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20651   },
20652 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
20653   {
20654     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mulu.b", 40,
20655     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20656   },
20657 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
20658   {
20659     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mulu.b", 40,
20660     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20661   },
20662 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
20663   {
20664     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mulu.b", 40,
20665     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20666   },
20667 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
20668   {
20669     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mulu.b", 40,
20670     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20671   },
20672 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
20673   {
20674     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mulu.b", 48,
20675     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20676   },
20677 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
20678   {
20679     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mulu.b", 48,
20680     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20681   },
20682 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
20683   {
20684     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mulu.b", 48,
20685     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20686   },
20687 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
20688   {
20689     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mulu.b", 48,
20690     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20691   },
20692 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
20693   {
20694     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mulu.b", 56,
20695     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20696   },
20697 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
20698   {
20699     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mulu.b", 56,
20700     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20701   },
20702 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
20703   {
20704     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mulu.b", 56,
20705     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20706   },
20707 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
20708   {
20709     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mulu.b", 56,
20710     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20711   },
20712 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
20713   {
20714     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mulu.b", 40,
20715     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20716   },
20717 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
20718   {
20719     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mulu.b", 40,
20720     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20721   },
20722 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
20723   {
20724     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mulu.b", 40,
20725     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20726   },
20727 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
20728   {
20729     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mulu.b", 40,
20730     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20731   },
20732 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
20733   {
20734     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mulu.b", 48,
20735     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20736   },
20737 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
20738   {
20739     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mulu.b", 48,
20740     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20741   },
20742 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
20743   {
20744     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mulu.b", 48,
20745     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20746   },
20747 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
20748   {
20749     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mulu.b", 48,
20750     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20751   },
20752 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
20753   {
20754     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mulu.b", 40,
20755     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20756   },
20757 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
20758   {
20759     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mulu.b", 40,
20760     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20761   },
20762 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
20763   {
20764     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mulu.b", 40,
20765     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20766   },
20767 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
20768   {
20769     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mulu.b", 40,
20770     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20771   },
20772 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
20773   {
20774     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mulu.b", 48,
20775     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20776   },
20777 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
20778   {
20779     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mulu.b", 48,
20780     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20781   },
20782 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
20783   {
20784     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mulu.b", 48,
20785     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20786   },
20787 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
20788   {
20789     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mulu.b", 48,
20790     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20791   },
20792 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
20793   {
20794     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mulu.b", 48,
20795     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20796   },
20797 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
20798   {
20799     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mulu.b", 48,
20800     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20801   },
20802 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
20803   {
20804     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mulu.b", 48,
20805     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20806   },
20807 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
20808   {
20809     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mulu.b", 48,
20810     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20811   },
20812 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
20813   {
20814     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mulu.b", 56,
20815     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20816   },
20817 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
20818   {
20819     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mulu.b", 56,
20820     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20821   },
20822 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
20823   {
20824     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mulu.b", 56,
20825     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20826   },
20827 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
20828   {
20829     M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mulu.b", 56,
20830     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20831   },
20832 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
20833   {
20834     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 40,
20835     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20836   },
20837 /* mulu.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
20838   {
20839     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 40,
20840     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20841   },
20842 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
20843   {
20844     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 40,
20845     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20846   },
20847 /* mulu.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
20848   {
20849     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 40,
20850     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20851   },
20852 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
20853   {
20854     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 40,
20855     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20856   },
20857 /* mulu.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
20858   {
20859     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 40,
20860     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20861   },
20862 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
20863   {
20864     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mulu.b", 48,
20865     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20866   },
20867 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
20868   {
20869     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mulu.b", 48,
20870     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20871   },
20872 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
20873   {
20874     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mulu.b", 56,
20875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20876   },
20877 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
20878   {
20879     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mulu.b", 56,
20880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20881   },
20882 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
20883   {
20884     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mulu.b", 64,
20885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20886   },
20887 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
20888   {
20889     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mulu.b", 64,
20890     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20891   },
20892 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
20893   {
20894     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mulu.b", 48,
20895     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20896   },
20897 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
20898   {
20899     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mulu.b", 48,
20900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20901   },
20902 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
20903   {
20904     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mulu.b", 56,
20905     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20906   },
20907 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
20908   {
20909     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mulu.b", 56,
20910     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20911   },
20912 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
20913   {
20914     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mulu.b", 48,
20915     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20916   },
20917 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
20918   {
20919     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mulu.b", 48,
20920     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20921   },
20922 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
20923   {
20924     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mulu.b", 56,
20925     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20926   },
20927 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
20928   {
20929     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mulu.b", 56,
20930     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20931   },
20932 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
20933   {
20934     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mulu.b", 56,
20935     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20936   },
20937 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
20938   {
20939     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mulu.b", 56,
20940     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20941   },
20942 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
20943   {
20944     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mulu.b", 64,
20945     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20946   },
20947 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
20948   {
20949     M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mulu.b", 64,
20950     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20951   },
20952 /* mulu.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
20953   {
20954     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 16,
20955     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20956   },
20957 /* mulu.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
20958   {
20959     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 16,
20960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20961   },
20962 /* mulu.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
20963   {
20964     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 16,
20965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20966   },
20967 /* mulu.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
20968   {
20969     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 16,
20970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20971   },
20972 /* mulu.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
20973   {
20974     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 16,
20975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20976   },
20977 /* mulu.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
20978   {
20979     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 16,
20980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20981   },
20982 /* mulu.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
20983   {
20984     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 16,
20985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20986   },
20987 /* mulu.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
20988   {
20989     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 16,
20990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20991   },
20992 /* mulu.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
20993   {
20994     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 16,
20995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20996   },
20997 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
20998   {
20999     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mulu.b", 24,
21000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21001   },
21002 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
21003   {
21004     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mulu.b", 24,
21005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21006   },
21007 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
21008   {
21009     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mulu.b", 24,
21010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21011   },
21012 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
21013   {
21014     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mulu.b", 32,
21015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21016   },
21017 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
21018   {
21019     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mulu.b", 32,
21020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21021   },
21022 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
21023   {
21024     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mulu.b", 32,
21025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21026   },
21027 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
21028   {
21029     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mulu.b", 40,
21030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21031   },
21032 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
21033   {
21034     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mulu.b", 40,
21035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21036   },
21037 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
21038   {
21039     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mulu.b", 40,
21040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21041   },
21042 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
21043   {
21044     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mulu.b", 24,
21045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21046   },
21047 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
21048   {
21049     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mulu.b", 24,
21050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21051   },
21052 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
21053   {
21054     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mulu.b", 24,
21055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21056   },
21057 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
21058   {
21059     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mulu.b", 32,
21060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21061   },
21062 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
21063   {
21064     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mulu.b", 32,
21065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21066   },
21067 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
21068   {
21069     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mulu.b", 32,
21070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21071   },
21072 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
21073   {
21074     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mulu.b", 24,
21075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21076   },
21077 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
21078   {
21079     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mulu.b", 24,
21080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21081   },
21082 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
21083   {
21084     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mulu.b", 24,
21085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21086   },
21087 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
21088   {
21089     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mulu.b", 32,
21090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21091   },
21092 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
21093   {
21094     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mulu.b", 32,
21095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21096   },
21097 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
21098   {
21099     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mulu.b", 32,
21100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21101   },
21102 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
21103   {
21104     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mulu.b", 32,
21105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21106   },
21107 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
21108   {
21109     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mulu.b", 32,
21110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21111   },
21112 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
21113   {
21114     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mulu.b", 32,
21115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21116   },
21117 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
21118   {
21119     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mulu.b", 40,
21120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21121   },
21122 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
21123   {
21124     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mulu.b", 40,
21125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21126   },
21127 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
21128   {
21129     M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mulu.b", 40,
21130     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21131   },
21132 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
21133   {
21134     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "mulu.w", 24,
21135     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21136   },
21137 /* mulu.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
21138   {
21139     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "mulu.w", 24,
21140     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21141   },
21142 /* mulu.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
21143   {
21144     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "mulu.w", 24,
21145     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21146   },
21147 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
21148   {
21149     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "mulu.w", 24,
21150     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21151   },
21152 /* mulu.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
21153   {
21154     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "mulu.w", 24,
21155     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21156   },
21157 /* mulu.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
21158   {
21159     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "mulu.w", 24,
21160     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21161   },
21162 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
21163   {
21164     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "mulu.w", 24,
21165     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21166   },
21167 /* mulu.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
21168   {
21169     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "mulu.w", 24,
21170     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21171   },
21172 /* mulu.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
21173   {
21174     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "mulu.w", 24,
21175     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21176   },
21177 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
21178   {
21179     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "mulu.w", 32,
21180     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21181   },
21182 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
21183   {
21184     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "mulu.w", 32,
21185     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21186   },
21187 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
21188   {
21189     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "mulu.w", 32,
21190     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21191   },
21192 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
21193   {
21194     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "mulu.w", 40,
21195     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21196   },
21197 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
21198   {
21199     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "mulu.w", 40,
21200     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21201   },
21202 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
21203   {
21204     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "mulu.w", 40,
21205     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21206   },
21207 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
21208   {
21209     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "mulu.w", 32,
21210     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21211   },
21212 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
21213   {
21214     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "mulu.w", 32,
21215     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21216   },
21217 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
21218   {
21219     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "mulu.w", 32,
21220     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21221   },
21222 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
21223   {
21224     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "mulu.w", 40,
21225     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21226   },
21227 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
21228   {
21229     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "mulu.w", 40,
21230     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21231   },
21232 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
21233   {
21234     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "mulu.w", 40,
21235     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21236   },
21237 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
21238   {
21239     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "mulu.w", 32,
21240     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21241   },
21242 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
21243   {
21244     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "mulu.w", 32,
21245     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21246   },
21247 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
21248   {
21249     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "mulu.w", 32,
21250     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21251   },
21252 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
21253   {
21254     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "mulu.w", 40,
21255     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21256   },
21257 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
21258   {
21259     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "mulu.w", 40,
21260     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21261   },
21262 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
21263   {
21264     M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "mulu.w", 40,
21265     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21266   },
21267 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
21268   {
21269     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "mulu.w", 32,
21270     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21271   },
21272 /* mulu.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
21273   {
21274     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "mulu.w", 32,
21275     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21276   },
21277 /* mulu.w${G} ${Dsp-16-u16},$Dst16RnHI */
21278   {
21279     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "mulu.w", 32,
21280     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21281   },
21282 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
21283   {
21284     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "mulu.w", 32,
21285     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21286   },
21287 /* mulu.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
21288   {
21289     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "mulu.w", 32,
21290     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21291   },
21292 /* mulu.w${G} ${Dsp-16-u16},$Dst16AnHI */
21293   {
21294     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "mulu.w", 32,
21295     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21296   },
21297 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
21298   {
21299     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "mulu.w", 32,
21300     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21301   },
21302 /* mulu.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
21303   {
21304     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "mulu.w", 32,
21305     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21306   },
21307 /* mulu.w${G} ${Dsp-16-u16},[$Dst16An] */
21308   {
21309     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "mulu.w", 32,
21310     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21311   },
21312 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
21313   {
21314     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "mulu.w", 40,
21315     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21316   },
21317 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
21318   {
21319     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "mulu.w", 40,
21320     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21321   },
21322 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
21323   {
21324     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "mulu.w", 40,
21325     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21326   },
21327 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
21328   {
21329     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "mulu.w", 48,
21330     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21331   },
21332 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
21333   {
21334     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "mulu.w", 48,
21335     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21336   },
21337 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
21338   {
21339     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "mulu.w", 48,
21340     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21341   },
21342 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
21343   {
21344     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "mulu.w", 40,
21345     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21346   },
21347 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
21348   {
21349     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "mulu.w", 40,
21350     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21351   },
21352 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
21353   {
21354     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "mulu.w", 40,
21355     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21356   },
21357 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
21358   {
21359     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "mulu.w", 48,
21360     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21361   },
21362 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
21363   {
21364     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "mulu.w", 48,
21365     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21366   },
21367 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
21368   {
21369     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "mulu.w", 48,
21370     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21371   },
21372 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
21373   {
21374     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "mulu.w", 40,
21375     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21376   },
21377 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
21378   {
21379     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "mulu.w", 40,
21380     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21381   },
21382 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
21383   {
21384     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "mulu.w", 40,
21385     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21386   },
21387 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
21388   {
21389     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "mulu.w", 48,
21390     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21391   },
21392 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
21393   {
21394     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "mulu.w", 48,
21395     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21396   },
21397 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
21398   {
21399     M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "mulu.w", 48,
21400     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21401   },
21402 /* mulu.w${G} $Src16RnHI,$Dst16RnHI */
21403   {
21404     M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "mulu.w", 16,
21405     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21406   },
21407 /* mulu.w${G} $Src16AnHI,$Dst16RnHI */
21408   {
21409     M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "mulu.w", 16,
21410     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21411   },
21412 /* mulu.w${G} [$Src16An],$Dst16RnHI */
21413   {
21414     M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "mulu.w", 16,
21415     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21416   },
21417 /* mulu.w${G} $Src16RnHI,$Dst16AnHI */
21418   {
21419     M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "mulu.w", 16,
21420     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21421   },
21422 /* mulu.w${G} $Src16AnHI,$Dst16AnHI */
21423   {
21424     M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "mulu.w", 16,
21425     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21426   },
21427 /* mulu.w${G} [$Src16An],$Dst16AnHI */
21428   {
21429     M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "mulu.w", 16,
21430     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21431   },
21432 /* mulu.w${G} $Src16RnHI,[$Dst16An] */
21433   {
21434     M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "mulu.w", 16,
21435     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21436   },
21437 /* mulu.w${G} $Src16AnHI,[$Dst16An] */
21438   {
21439     M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "mulu.w", 16,
21440     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21441   },
21442 /* mulu.w${G} [$Src16An],[$Dst16An] */
21443   {
21444     M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "mulu.w", 16,
21445     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21446   },
21447 /* mulu.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
21448   {
21449     M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "mulu.w", 24,
21450     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21451   },
21452 /* mulu.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
21453   {
21454     M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "mulu.w", 24,
21455     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21456   },
21457 /* mulu.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
21458   {
21459     M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "mulu.w", 24,
21460     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21461   },
21462 /* mulu.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
21463   {
21464     M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "mulu.w", 32,
21465     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21466   },
21467 /* mulu.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
21468   {
21469     M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "mulu.w", 32,
21470     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21471   },
21472 /* mulu.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
21473   {
21474     M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "mulu.w", 32,
21475     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21476   },
21477 /* mulu.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
21478   {
21479     M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "mulu.w", 24,
21480     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21481   },
21482 /* mulu.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
21483   {
21484     M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "mulu.w", 24,
21485     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21486   },
21487 /* mulu.w${G} [$Src16An],${Dsp-16-u8}[sb] */
21488   {
21489     M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "mulu.w", 24,
21490     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21491   },
21492 /* mulu.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
21493   {
21494     M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "mulu.w", 32,
21495     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21496   },
21497 /* mulu.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
21498   {
21499     M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "mulu.w", 32,
21500     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21501   },
21502 /* mulu.w${G} [$Src16An],${Dsp-16-u16}[sb] */
21503   {
21504     M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "mulu.w", 32,
21505     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21506   },
21507 /* mulu.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
21508   {
21509     M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "mulu.w", 24,
21510     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21511   },
21512 /* mulu.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
21513   {
21514     M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "mulu.w", 24,
21515     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21516   },
21517 /* mulu.w${G} [$Src16An],${Dsp-16-s8}[fb] */
21518   {
21519     M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "mulu.w", 24,
21520     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21521   },
21522 /* mulu.w${G} $Src16RnHI,${Dsp-16-u16} */
21523   {
21524     M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "mulu.w", 32,
21525     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21526   },
21527 /* mulu.w${G} $Src16AnHI,${Dsp-16-u16} */
21528   {
21529     M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "mulu.w", 32,
21530     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21531   },
21532 /* mulu.w${G} [$Src16An],${Dsp-16-u16} */
21533   {
21534     M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "mulu.w", 32,
21535     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21536   },
21537 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
21538   {
21539     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "mulu.b", 24,
21540     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21541   },
21542 /* mulu.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
21543   {
21544     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "mulu.b", 24,
21545     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21546   },
21547 /* mulu.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
21548   {
21549     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "mulu.b", 24,
21550     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21551   },
21552 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
21553   {
21554     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "mulu.b", 24,
21555     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21556   },
21557 /* mulu.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
21558   {
21559     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "mulu.b", 24,
21560     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21561   },
21562 /* mulu.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
21563   {
21564     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "mulu.b", 24,
21565     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21566   },
21567 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
21568   {
21569     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "mulu.b", 24,
21570     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21571   },
21572 /* mulu.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
21573   {
21574     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "mulu.b", 24,
21575     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21576   },
21577 /* mulu.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
21578   {
21579     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "mulu.b", 24,
21580     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21581   },
21582 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
21583   {
21584     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "mulu.b", 32,
21585     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21586   },
21587 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
21588   {
21589     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "mulu.b", 32,
21590     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21591   },
21592 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
21593   {
21594     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "mulu.b", 32,
21595     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21596   },
21597 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
21598   {
21599     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "mulu.b", 40,
21600     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21601   },
21602 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
21603   {
21604     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "mulu.b", 40,
21605     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21606   },
21607 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
21608   {
21609     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "mulu.b", 40,
21610     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21611   },
21612 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
21613   {
21614     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "mulu.b", 32,
21615     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21616   },
21617 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
21618   {
21619     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "mulu.b", 32,
21620     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21621   },
21622 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
21623   {
21624     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "mulu.b", 32,
21625     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21626   },
21627 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
21628   {
21629     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "mulu.b", 40,
21630     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21631   },
21632 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
21633   {
21634     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "mulu.b", 40,
21635     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21636   },
21637 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
21638   {
21639     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "mulu.b", 40,
21640     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21641   },
21642 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
21643   {
21644     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "mulu.b", 32,
21645     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21646   },
21647 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
21648   {
21649     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "mulu.b", 32,
21650     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21651   },
21652 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
21653   {
21654     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "mulu.b", 32,
21655     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21656   },
21657 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
21658   {
21659     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "mulu.b", 40,
21660     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21661   },
21662 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
21663   {
21664     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "mulu.b", 40,
21665     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21666   },
21667 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
21668   {
21669     M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "mulu.b", 40,
21670     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21671   },
21672 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
21673   {
21674     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "mulu.b", 32,
21675     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21676   },
21677 /* mulu.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
21678   {
21679     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "mulu.b", 32,
21680     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21681   },
21682 /* mulu.b${G} ${Dsp-16-u16},$Dst16RnQI */
21683   {
21684     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "mulu.b", 32,
21685     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21686   },
21687 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
21688   {
21689     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "mulu.b", 32,
21690     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21691   },
21692 /* mulu.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
21693   {
21694     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "mulu.b", 32,
21695     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21696   },
21697 /* mulu.b${G} ${Dsp-16-u16},$Dst16AnQI */
21698   {
21699     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "mulu.b", 32,
21700     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21701   },
21702 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
21703   {
21704     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "mulu.b", 32,
21705     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21706   },
21707 /* mulu.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
21708   {
21709     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "mulu.b", 32,
21710     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21711   },
21712 /* mulu.b${G} ${Dsp-16-u16},[$Dst16An] */
21713   {
21714     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "mulu.b", 32,
21715     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21716   },
21717 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
21718   {
21719     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "mulu.b", 40,
21720     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21721   },
21722 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
21723   {
21724     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "mulu.b", 40,
21725     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21726   },
21727 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
21728   {
21729     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "mulu.b", 40,
21730     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21731   },
21732 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
21733   {
21734     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "mulu.b", 48,
21735     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21736   },
21737 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
21738   {
21739     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "mulu.b", 48,
21740     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21741   },
21742 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
21743   {
21744     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "mulu.b", 48,
21745     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21746   },
21747 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
21748   {
21749     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "mulu.b", 40,
21750     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21751   },
21752 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
21753   {
21754     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "mulu.b", 40,
21755     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21756   },
21757 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
21758   {
21759     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "mulu.b", 40,
21760     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21761   },
21762 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
21763   {
21764     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "mulu.b", 48,
21765     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21766   },
21767 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
21768   {
21769     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "mulu.b", 48,
21770     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21771   },
21772 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
21773   {
21774     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "mulu.b", 48,
21775     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21776   },
21777 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
21778   {
21779     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "mulu.b", 40,
21780     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21781   },
21782 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
21783   {
21784     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "mulu.b", 40,
21785     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21786   },
21787 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
21788   {
21789     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "mulu.b", 40,
21790     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21791   },
21792 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
21793   {
21794     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "mulu.b", 48,
21795     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21796   },
21797 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
21798   {
21799     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "mulu.b", 48,
21800     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21801   },
21802 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
21803   {
21804     M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "mulu.b", 48,
21805     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21806   },
21807 /* mulu.b${G} $Src16RnQI,$Dst16RnQI */
21808   {
21809     M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "mulu.b", 16,
21810     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21811   },
21812 /* mulu.b${G} $Src16AnQI,$Dst16RnQI */
21813   {
21814     M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "mulu.b", 16,
21815     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21816   },
21817 /* mulu.b${G} [$Src16An],$Dst16RnQI */
21818   {
21819     M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "mulu.b", 16,
21820     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21821   },
21822 /* mulu.b${G} $Src16RnQI,$Dst16AnQI */
21823   {
21824     M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "mulu.b", 16,
21825     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21826   },
21827 /* mulu.b${G} $Src16AnQI,$Dst16AnQI */
21828   {
21829     M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "mulu.b", 16,
21830     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21831   },
21832 /* mulu.b${G} [$Src16An],$Dst16AnQI */
21833   {
21834     M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "mulu.b", 16,
21835     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21836   },
21837 /* mulu.b${G} $Src16RnQI,[$Dst16An] */
21838   {
21839     M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "mulu.b", 16,
21840     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21841   },
21842 /* mulu.b${G} $Src16AnQI,[$Dst16An] */
21843   {
21844     M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "mulu.b", 16,
21845     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21846   },
21847 /* mulu.b${G} [$Src16An],[$Dst16An] */
21848   {
21849     M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "mulu.b", 16,
21850     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21851   },
21852 /* mulu.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
21853   {
21854     M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "mulu.b", 24,
21855     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21856   },
21857 /* mulu.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
21858   {
21859     M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "mulu.b", 24,
21860     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21861   },
21862 /* mulu.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
21863   {
21864     M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "mulu.b", 24,
21865     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21866   },
21867 /* mulu.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
21868   {
21869     M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "mulu.b", 32,
21870     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21871   },
21872 /* mulu.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
21873   {
21874     M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "mulu.b", 32,
21875     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21876   },
21877 /* mulu.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
21878   {
21879     M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "mulu.b", 32,
21880     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21881   },
21882 /* mulu.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
21883   {
21884     M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "mulu.b", 24,
21885     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21886   },
21887 /* mulu.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
21888   {
21889     M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "mulu.b", 24,
21890     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21891   },
21892 /* mulu.b${G} [$Src16An],${Dsp-16-u8}[sb] */
21893   {
21894     M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "mulu.b", 24,
21895     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21896   },
21897 /* mulu.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
21898   {
21899     M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "mulu.b", 32,
21900     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21901   },
21902 /* mulu.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
21903   {
21904     M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "mulu.b", 32,
21905     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21906   },
21907 /* mulu.b${G} [$Src16An],${Dsp-16-u16}[sb] */
21908   {
21909     M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "mulu.b", 32,
21910     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21911   },
21912 /* mulu.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
21913   {
21914     M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "mulu.b", 24,
21915     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21916   },
21917 /* mulu.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
21918   {
21919     M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "mulu.b", 24,
21920     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21921   },
21922 /* mulu.b${G} [$Src16An],${Dsp-16-s8}[fb] */
21923   {
21924     M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "mulu.b", 24,
21925     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21926   },
21927 /* mulu.b${G} $Src16RnQI,${Dsp-16-u16} */
21928   {
21929     M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "mulu.b", 32,
21930     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21931   },
21932 /* mulu.b${G} $Src16AnQI,${Dsp-16-u16} */
21933   {
21934     M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "mulu.b", 32,
21935     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21936   },
21937 /* mulu.b${G} [$Src16An],${Dsp-16-u16} */
21938   {
21939     M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "mulu.b", 32,
21940     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21941   },
21942 /* mulu.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
21943   {
21944     M32C_INSN_MULU32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32,
21945     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21946   },
21947 /* mulu.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
21948   {
21949     M32C_INSN_MULU32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mulu.w", 32,
21950     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21951   },
21952 /* mulu.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
21953   {
21954     M32C_INSN_MULU32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32,
21955     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21956   },
21957 /* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
21958   {
21959     M32C_INSN_MULU32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mulu.w", 40,
21960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21961   },
21962 /* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
21963   {
21964     M32C_INSN_MULU32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mulu.w", 40,
21965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21966   },
21967 /* mulu.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
21968   {
21969     M32C_INSN_MULU32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mulu.w", 40,
21970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21971   },
21972 /* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
21973   {
21974     M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mulu.w", 48,
21975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21976   },
21977 /* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
21978   {
21979     M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mulu.w", 48,
21980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21981   },
21982 /* mulu.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
21983   {
21984     M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mulu.w", 48,
21985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21986   },
21987 /* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16} */
21988   {
21989     M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mulu.w", 48,
21990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21991   },
21992 /* mulu.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
21993   {
21994     M32C_INSN_MULU32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mulu.w", 56,
21995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21996   },
21997 /* mulu.w${G} #${Imm-40-HI},${Dsp-16-u24} */
21998   {
21999     M32C_INSN_MULU32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mulu.w", 56,
22000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22001   },
22002 /* mulu.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
22003   {
22004     M32C_INSN_MULU32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 24,
22005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22006   },
22007 /* mulu.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
22008   {
22009     M32C_INSN_MULU32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mulu.b", 24,
22010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22011   },
22012 /* mulu.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
22013   {
22014     M32C_INSN_MULU32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mulu.b", 24,
22015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22016   },
22017 /* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
22018   {
22019     M32C_INSN_MULU32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mulu.b", 32,
22020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22021   },
22022 /* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
22023   {
22024     M32C_INSN_MULU32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mulu.b", 32,
22025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22026   },
22027 /* mulu.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
22028   {
22029     M32C_INSN_MULU32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mulu.b", 32,
22030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22031   },
22032 /* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
22033   {
22034     M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mulu.b", 40,
22035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22036   },
22037 /* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
22038   {
22039     M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mulu.b", 40,
22040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22041   },
22042 /* mulu.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
22043   {
22044     M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mulu.b", 40,
22045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22046   },
22047 /* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16} */
22048   {
22049     M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mulu.b", 40,
22050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22051   },
22052 /* mulu.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
22053   {
22054     M32C_INSN_MULU32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mulu.b", 48,
22055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22056   },
22057 /* mulu.b${G} #${Imm-40-QI},${Dsp-16-u24} */
22058   {
22059     M32C_INSN_MULU32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mulu.b", 48,
22060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22061   },
22062 /* mulu.w${G} #${Imm-16-HI},$Dst16RnHI */
22063   {
22064     M32C_INSN_MULU16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "mulu16.w-imm-G-basic-dst16-Rn-direct-HI", "mulu.w", 32,
22065     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22066   },
22067 /* mulu.w${G} #${Imm-16-HI},$Dst16AnHI */
22068   {
22069     M32C_INSN_MULU16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "mulu16.w-imm-G-basic-dst16-An-direct-HI", "mulu.w", 32,
22070     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22071   },
22072 /* mulu.w${G} #${Imm-16-HI},[$Dst16An] */
22073   {
22074     M32C_INSN_MULU16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "mulu16.w-imm-G-basic-dst16-An-indirect-HI", "mulu.w", 32,
22075     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22076   },
22077 /* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
22078   {
22079     M32C_INSN_MULU16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "mulu16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "mulu.w", 40,
22080     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22081   },
22082 /* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
22083   {
22084     M32C_INSN_MULU16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "mulu16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "mulu.w", 40,
22085     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22086   },
22087 /* mulu.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
22088   {
22089     M32C_INSN_MULU16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "mulu16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "mulu.w", 40,
22090     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22091   },
22092 /* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
22093   {
22094     M32C_INSN_MULU16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "mulu16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "mulu.w", 48,
22095     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22096   },
22097 /* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
22098   {
22099     M32C_INSN_MULU16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "mulu16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "mulu.w", 48,
22100     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22101   },
22102 /* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16} */
22103   {
22104     M32C_INSN_MULU16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "mulu16.w-imm-G-16-16-dst16-16-16-absolute-HI", "mulu.w", 48,
22105     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22106   },
22107 /* mulu.b${G} #${Imm-16-QI},$Dst16RnQI */
22108   {
22109     M32C_INSN_MULU16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "mulu16.b-imm-G-basic-dst16-Rn-direct-QI", "mulu.b", 24,
22110     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22111   },
22112 /* mulu.b${G} #${Imm-16-QI},$Dst16AnQI */
22113   {
22114     M32C_INSN_MULU16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "mulu16.b-imm-G-basic-dst16-An-direct-QI", "mulu.b", 24,
22115     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22116   },
22117 /* mulu.b${G} #${Imm-16-QI},[$Dst16An] */
22118   {
22119     M32C_INSN_MULU16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "mulu16.b-imm-G-basic-dst16-An-indirect-QI", "mulu.b", 24,
22120     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22121   },
22122 /* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
22123   {
22124     M32C_INSN_MULU16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "mulu16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "mulu.b", 32,
22125     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22126   },
22127 /* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
22128   {
22129     M32C_INSN_MULU16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "mulu16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "mulu.b", 32,
22130     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22131   },
22132 /* mulu.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
22133   {
22134     M32C_INSN_MULU16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "mulu16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "mulu.b", 32,
22135     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22136   },
22137 /* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
22138   {
22139     M32C_INSN_MULU16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "mulu16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "mulu.b", 40,
22140     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22141   },
22142 /* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
22143   {
22144     M32C_INSN_MULU16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "mulu16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "mulu.b", 40,
22145     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22146   },
22147 /* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16} */
22148   {
22149     M32C_INSN_MULU16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "mulu16.b-imm-G-16-16-dst16-16-16-absolute-QI", "mulu.b", 40,
22150     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22151   },
22152 /* mulex $R3 */
22153   {
22154     M32C_INSN_MULEX_DST32_R3_DIRECT_UNPREFIXED_HI, "mulex-dst32-R3-direct-Unprefixed-HI", "mulex", 16,
22155     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22156   },
22157 /* mulex $Dst32AnUnprefixedHI */
22158   {
22159     M32C_INSN_MULEX_DST32_AN_DIRECT_UNPREFIXED_HI, "mulex-dst32-An-direct-Unprefixed-HI", "mulex", 16,
22160     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22161   },
22162 /* mulex [$Dst32AnUnprefixed] */
22163   {
22164     M32C_INSN_MULEX_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulex-dst32-An-indirect-Unprefixed-HI", "mulex", 16,
22165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22166   },
22167 /* mulex ${Dsp-16-u8}[$Dst32AnUnprefixed] */
22168   {
22169     M32C_INSN_MULEX_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-8-An-relative-Unprefixed-HI", "mulex", 24,
22170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22171   },
22172 /* mulex ${Dsp-16-u16}[$Dst32AnUnprefixed] */
22173   {
22174     M32C_INSN_MULEX_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-16-An-relative-Unprefixed-HI", "mulex", 32,
22175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22176   },
22177 /* mulex ${Dsp-16-u24}[$Dst32AnUnprefixed] */
22178   {
22179     M32C_INSN_MULEX_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-24-An-relative-Unprefixed-HI", "mulex", 40,
22180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22181   },
22182 /* mulex ${Dsp-16-u8}[sb] */
22183   {
22184     M32C_INSN_MULEX_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-8-SB-relative-Unprefixed-HI", "mulex", 24,
22185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22186   },
22187 /* mulex ${Dsp-16-u16}[sb] */
22188   {
22189     M32C_INSN_MULEX_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-16-SB-relative-Unprefixed-HI", "mulex", 32,
22190     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22191   },
22192 /* mulex ${Dsp-16-s8}[fb] */
22193   {
22194     M32C_INSN_MULEX_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-8-FB-relative-Unprefixed-HI", "mulex", 24,
22195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22196   },
22197 /* mulex ${Dsp-16-s16}[fb] */
22198   {
22199     M32C_INSN_MULEX_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-16-FB-relative-Unprefixed-HI", "mulex", 32,
22200     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22201   },
22202 /* mulex ${Dsp-16-u16} */
22203   {
22204     M32C_INSN_MULEX_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulex-dst32-16-16-absolute-Unprefixed-HI", "mulex", 32,
22205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22206   },
22207 /* mulex ${Dsp-16-u24} */
22208   {
22209     M32C_INSN_MULEX_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulex-dst32-16-24-absolute-Unprefixed-HI", "mulex", 40,
22210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22211   },
22212 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
22213   {
22214     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 24,
22215     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22216   },
22217 /* mul.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
22218   {
22219     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 24,
22220     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22221   },
22222 /* mul.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
22223   {
22224     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 24,
22225     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22226   },
22227 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
22228   {
22229     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 24,
22230     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22231   },
22232 /* mul.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
22233   {
22234     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 24,
22235     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22236   },
22237 /* mul.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
22238   {
22239     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 24,
22240     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22241   },
22242 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
22243   {
22244     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 24,
22245     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22246   },
22247 /* mul.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
22248   {
22249     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 24,
22250     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22251   },
22252 /* mul.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
22253   {
22254     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 24,
22255     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22256   },
22257 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
22258   {
22259     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mul.w", 32,
22260     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22261   },
22262 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
22263   {
22264     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mul.w", 32,
22265     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22266   },
22267 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
22268   {
22269     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mul.w", 32,
22270     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22271   },
22272 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
22273   {
22274     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mul.w", 40,
22275     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22276   },
22277 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
22278   {
22279     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mul.w", 40,
22280     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22281   },
22282 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
22283   {
22284     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mul.w", 40,
22285     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22286   },
22287 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
22288   {
22289     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mul.w", 48,
22290     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22291   },
22292 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
22293   {
22294     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mul.w", 48,
22295     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22296   },
22297 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
22298   {
22299     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mul.w", 48,
22300     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22301   },
22302 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
22303   {
22304     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mul.w", 32,
22305     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22306   },
22307 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
22308   {
22309     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mul.w", 32,
22310     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22311   },
22312 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
22313   {
22314     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mul.w", 32,
22315     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22316   },
22317 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
22318   {
22319     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mul.w", 40,
22320     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22321   },
22322 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
22323   {
22324     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mul.w", 40,
22325     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22326   },
22327 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
22328   {
22329     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mul.w", 40,
22330     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22331   },
22332 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
22333   {
22334     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mul.w", 32,
22335     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22336   },
22337 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
22338   {
22339     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mul.w", 32,
22340     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22341   },
22342 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
22343   {
22344     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mul.w", 32,
22345     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22346   },
22347 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
22348   {
22349     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mul.w", 40,
22350     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22351   },
22352 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
22353   {
22354     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mul.w", 40,
22355     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22356   },
22357 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
22358   {
22359     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mul.w", 40,
22360     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22361   },
22362 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
22363   {
22364     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mul.w", 40,
22365     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22366   },
22367 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
22368   {
22369     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mul.w", 40,
22370     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22371   },
22372 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
22373   {
22374     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mul.w", 40,
22375     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22376   },
22377 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
22378   {
22379     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mul.w", 48,
22380     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22381   },
22382 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
22383   {
22384     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mul.w", 48,
22385     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22386   },
22387 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
22388   {
22389     M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mul.w", 48,
22390     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22391   },
22392 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
22393   {
22394     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32,
22395     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22396   },
22397 /* mul.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
22398   {
22399     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32,
22400     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22401   },
22402 /* mul.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
22403   {
22404     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32,
22405     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22406   },
22407 /* mul.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
22408   {
22409     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32,
22410     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22411   },
22412 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
22413   {
22414     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 32,
22415     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22416   },
22417 /* mul.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
22418   {
22419     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 32,
22420     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22421   },
22422 /* mul.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
22423   {
22424     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 32,
22425     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22426   },
22427 /* mul.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
22428   {
22429     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 32,
22430     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22431   },
22432 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
22433   {
22434     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 32,
22435     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22436   },
22437 /* mul.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
22438   {
22439     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 32,
22440     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22441   },
22442 /* mul.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
22443   {
22444     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 32,
22445     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22446   },
22447 /* mul.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
22448   {
22449     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 32,
22450     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22451   },
22452 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
22453   {
22454     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mul.w", 40,
22455     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22456   },
22457 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
22458   {
22459     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mul.w", 40,
22460     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22461   },
22462 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
22463   {
22464     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mul.w", 40,
22465     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22466   },
22467 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
22468   {
22469     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mul.w", 40,
22470     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22471   },
22472 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
22473   {
22474     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mul.w", 48,
22475     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22476   },
22477 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
22478   {
22479     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mul.w", 48,
22480     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22481   },
22482 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
22483   {
22484     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mul.w", 48,
22485     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22486   },
22487 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
22488   {
22489     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mul.w", 48,
22490     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22491   },
22492 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
22493   {
22494     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mul.w", 56,
22495     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22496   },
22497 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
22498   {
22499     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mul.w", 56,
22500     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22501   },
22502 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
22503   {
22504     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mul.w", 56,
22505     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22506   },
22507 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
22508   {
22509     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mul.w", 56,
22510     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22511   },
22512 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
22513   {
22514     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mul.w", 40,
22515     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22516   },
22517 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
22518   {
22519     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mul.w", 40,
22520     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22521   },
22522 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
22523   {
22524     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mul.w", 40,
22525     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22526   },
22527 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
22528   {
22529     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mul.w", 40,
22530     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22531   },
22532 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
22533   {
22534     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mul.w", 48,
22535     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22536   },
22537 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
22538   {
22539     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mul.w", 48,
22540     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22541   },
22542 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
22543   {
22544     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mul.w", 48,
22545     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22546   },
22547 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
22548   {
22549     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mul.w", 48,
22550     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22551   },
22552 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
22553   {
22554     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mul.w", 40,
22555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22556   },
22557 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
22558   {
22559     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mul.w", 40,
22560     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22561   },
22562 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
22563   {
22564     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mul.w", 40,
22565     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22566   },
22567 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
22568   {
22569     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mul.w", 40,
22570     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22571   },
22572 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
22573   {
22574     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mul.w", 48,
22575     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22576   },
22577 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
22578   {
22579     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mul.w", 48,
22580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22581   },
22582 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
22583   {
22584     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mul.w", 48,
22585     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22586   },
22587 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
22588   {
22589     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mul.w", 48,
22590     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22591   },
22592 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
22593   {
22594     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mul.w", 48,
22595     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22596   },
22597 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
22598   {
22599     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mul.w", 48,
22600     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22601   },
22602 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
22603   {
22604     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mul.w", 48,
22605     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22606   },
22607 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
22608   {
22609     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mul.w", 48,
22610     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22611   },
22612 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
22613   {
22614     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mul.w", 56,
22615     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22616   },
22617 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
22618   {
22619     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mul.w", 56,
22620     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22621   },
22622 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
22623   {
22624     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mul.w", 56,
22625     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22626   },
22627 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
22628   {
22629     M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mul.w", 56,
22630     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22631   },
22632 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
22633   {
22634     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 40,
22635     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22636   },
22637 /* mul.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
22638   {
22639     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 40,
22640     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22641   },
22642 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
22643   {
22644     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 40,
22645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22646   },
22647 /* mul.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
22648   {
22649     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 40,
22650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22651   },
22652 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
22653   {
22654     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 40,
22655     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22656   },
22657 /* mul.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
22658   {
22659     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 40,
22660     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22661   },
22662 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
22663   {
22664     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mul.w", 48,
22665     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22666   },
22667 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
22668   {
22669     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mul.w", 48,
22670     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22671   },
22672 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
22673   {
22674     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mul.w", 56,
22675     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22676   },
22677 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
22678   {
22679     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mul.w", 56,
22680     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22681   },
22682 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
22683   {
22684     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mul.w", 64,
22685     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22686   },
22687 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
22688   {
22689     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mul.w", 64,
22690     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22691   },
22692 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
22693   {
22694     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mul.w", 48,
22695     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22696   },
22697 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
22698   {
22699     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mul.w", 48,
22700     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22701   },
22702 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
22703   {
22704     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mul.w", 56,
22705     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22706   },
22707 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
22708   {
22709     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mul.w", 56,
22710     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22711   },
22712 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
22713   {
22714     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mul.w", 48,
22715     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22716   },
22717 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
22718   {
22719     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mul.w", 48,
22720     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22721   },
22722 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
22723   {
22724     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mul.w", 56,
22725     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22726   },
22727 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
22728   {
22729     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mul.w", 56,
22730     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22731   },
22732 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
22733   {
22734     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mul.w", 56,
22735     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22736   },
22737 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
22738   {
22739     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mul.w", 56,
22740     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22741   },
22742 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
22743   {
22744     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mul.w", 64,
22745     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22746   },
22747 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
22748   {
22749     M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mul.w", 64,
22750     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22751   },
22752 /* mul.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
22753   {
22754     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 16,
22755     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22756   },
22757 /* mul.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
22758   {
22759     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 16,
22760     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22761   },
22762 /* mul.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
22763   {
22764     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 16,
22765     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22766   },
22767 /* mul.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
22768   {
22769     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 16,
22770     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22771   },
22772 /* mul.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
22773   {
22774     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 16,
22775     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22776   },
22777 /* mul.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
22778   {
22779     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 16,
22780     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22781   },
22782 /* mul.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
22783   {
22784     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 16,
22785     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22786   },
22787 /* mul.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
22788   {
22789     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 16,
22790     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22791   },
22792 /* mul.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
22793   {
22794     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 16,
22795     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22796   },
22797 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
22798   {
22799     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mul.w", 24,
22800     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22801   },
22802 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
22803   {
22804     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mul.w", 24,
22805     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22806   },
22807 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
22808   {
22809     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mul.w", 24,
22810     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22811   },
22812 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
22813   {
22814     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mul.w", 32,
22815     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22816   },
22817 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
22818   {
22819     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mul.w", 32,
22820     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22821   },
22822 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
22823   {
22824     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mul.w", 32,
22825     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22826   },
22827 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
22828   {
22829     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mul.w", 40,
22830     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22831   },
22832 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
22833   {
22834     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mul.w", 40,
22835     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22836   },
22837 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
22838   {
22839     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mul.w", 40,
22840     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22841   },
22842 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
22843   {
22844     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mul.w", 24,
22845     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22846   },
22847 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
22848   {
22849     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mul.w", 24,
22850     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22851   },
22852 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
22853   {
22854     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mul.w", 24,
22855     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22856   },
22857 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
22858   {
22859     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mul.w", 32,
22860     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22861   },
22862 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
22863   {
22864     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mul.w", 32,
22865     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22866   },
22867 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
22868   {
22869     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mul.w", 32,
22870     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22871   },
22872 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
22873   {
22874     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mul.w", 24,
22875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22876   },
22877 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
22878   {
22879     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mul.w", 24,
22880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22881   },
22882 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
22883   {
22884     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mul.w", 24,
22885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22886   },
22887 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
22888   {
22889     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mul.w", 32,
22890     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22891   },
22892 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
22893   {
22894     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mul.w", 32,
22895     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22896   },
22897 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
22898   {
22899     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mul.w", 32,
22900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22901   },
22902 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
22903   {
22904     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mul.w", 32,
22905     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22906   },
22907 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
22908   {
22909     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mul.w", 32,
22910     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22911   },
22912 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
22913   {
22914     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mul.w", 32,
22915     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22916   },
22917 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
22918   {
22919     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mul.w", 40,
22920     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22921   },
22922 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
22923   {
22924     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mul.w", 40,
22925     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22926   },
22927 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
22928   {
22929     M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mul.w", 40,
22930     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22931   },
22932 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
22933   {
22934     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 24,
22935     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22936   },
22937 /* mul.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
22938   {
22939     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 24,
22940     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22941   },
22942 /* mul.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
22943   {
22944     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 24,
22945     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22946   },
22947 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
22948   {
22949     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 24,
22950     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22951   },
22952 /* mul.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
22953   {
22954     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 24,
22955     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22956   },
22957 /* mul.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
22958   {
22959     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 24,
22960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22961   },
22962 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
22963   {
22964     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 24,
22965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22966   },
22967 /* mul.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
22968   {
22969     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 24,
22970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22971   },
22972 /* mul.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
22973   {
22974     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 24,
22975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22976   },
22977 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
22978   {
22979     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mul.b", 32,
22980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22981   },
22982 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
22983   {
22984     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mul.b", 32,
22985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22986   },
22987 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
22988   {
22989     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mul.b", 32,
22990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22991   },
22992 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
22993   {
22994     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mul.b", 40,
22995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22996   },
22997 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
22998   {
22999     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mul.b", 40,
23000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23001   },
23002 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
23003   {
23004     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mul.b", 40,
23005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23006   },
23007 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
23008   {
23009     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mul.b", 48,
23010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23011   },
23012 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
23013   {
23014     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mul.b", 48,
23015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23016   },
23017 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
23018   {
23019     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mul.b", 48,
23020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23021   },
23022 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
23023   {
23024     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mul.b", 32,
23025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23026   },
23027 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
23028   {
23029     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mul.b", 32,
23030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23031   },
23032 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
23033   {
23034     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mul.b", 32,
23035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23036   },
23037 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
23038   {
23039     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mul.b", 40,
23040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23041   },
23042 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
23043   {
23044     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mul.b", 40,
23045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23046   },
23047 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
23048   {
23049     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mul.b", 40,
23050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23051   },
23052 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
23053   {
23054     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mul.b", 32,
23055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23056   },
23057 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
23058   {
23059     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mul.b", 32,
23060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23061   },
23062 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
23063   {
23064     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mul.b", 32,
23065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23066   },
23067 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
23068   {
23069     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mul.b", 40,
23070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23071   },
23072 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
23073   {
23074     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mul.b", 40,
23075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23076   },
23077 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
23078   {
23079     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mul.b", 40,
23080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23081   },
23082 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
23083   {
23084     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mul.b", 40,
23085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23086   },
23087 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
23088   {
23089     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mul.b", 40,
23090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23091   },
23092 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
23093   {
23094     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mul.b", 40,
23095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23096   },
23097 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
23098   {
23099     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mul.b", 48,
23100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23101   },
23102 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
23103   {
23104     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mul.b", 48,
23105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23106   },
23107 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
23108   {
23109     M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mul.b", 48,
23110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23111   },
23112 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
23113   {
23114     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 32,
23115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23116   },
23117 /* mul.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
23118   {
23119     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 32,
23120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23121   },
23122 /* mul.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
23123   {
23124     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 32,
23125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23126   },
23127 /* mul.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
23128   {
23129     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 32,
23130     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23131   },
23132 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
23133   {
23134     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 32,
23135     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23136   },
23137 /* mul.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
23138   {
23139     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 32,
23140     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23141   },
23142 /* mul.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
23143   {
23144     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 32,
23145     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23146   },
23147 /* mul.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
23148   {
23149     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 32,
23150     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23151   },
23152 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
23153   {
23154     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 32,
23155     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23156   },
23157 /* mul.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
23158   {
23159     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 32,
23160     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23161   },
23162 /* mul.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
23163   {
23164     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 32,
23165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23166   },
23167 /* mul.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
23168   {
23169     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 32,
23170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23171   },
23172 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
23173   {
23174     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mul.b", 40,
23175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23176   },
23177 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
23178   {
23179     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mul.b", 40,
23180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23181   },
23182 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
23183   {
23184     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mul.b", 40,
23185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23186   },
23187 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
23188   {
23189     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mul.b", 40,
23190     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23191   },
23192 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
23193   {
23194     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mul.b", 48,
23195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23196   },
23197 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
23198   {
23199     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mul.b", 48,
23200     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23201   },
23202 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
23203   {
23204     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mul.b", 48,
23205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23206   },
23207 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
23208   {
23209     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mul.b", 48,
23210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23211   },
23212 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
23213   {
23214     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mul.b", 56,
23215     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23216   },
23217 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
23218   {
23219     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mul.b", 56,
23220     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23221   },
23222 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
23223   {
23224     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mul.b", 56,
23225     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23226   },
23227 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
23228   {
23229     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mul.b", 56,
23230     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23231   },
23232 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
23233   {
23234     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mul.b", 40,
23235     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23236   },
23237 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
23238   {
23239     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mul.b", 40,
23240     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23241   },
23242 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
23243   {
23244     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mul.b", 40,
23245     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23246   },
23247 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
23248   {
23249     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mul.b", 40,
23250     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23251   },
23252 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
23253   {
23254     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mul.b", 48,
23255     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23256   },
23257 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
23258   {
23259     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mul.b", 48,
23260     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23261   },
23262 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
23263   {
23264     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mul.b", 48,
23265     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23266   },
23267 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
23268   {
23269     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mul.b", 48,
23270     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23271   },
23272 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
23273   {
23274     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mul.b", 40,
23275     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23276   },
23277 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
23278   {
23279     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mul.b", 40,
23280     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23281   },
23282 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
23283   {
23284     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mul.b", 40,
23285     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23286   },
23287 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
23288   {
23289     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mul.b", 40,
23290     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23291   },
23292 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
23293   {
23294     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mul.b", 48,
23295     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23296   },
23297 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
23298   {
23299     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mul.b", 48,
23300     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23301   },
23302 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
23303   {
23304     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mul.b", 48,
23305     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23306   },
23307 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
23308   {
23309     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mul.b", 48,
23310     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23311   },
23312 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
23313   {
23314     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mul.b", 48,
23315     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23316   },
23317 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
23318   {
23319     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mul.b", 48,
23320     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23321   },
23322 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
23323   {
23324     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mul.b", 48,
23325     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23326   },
23327 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
23328   {
23329     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mul.b", 48,
23330     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23331   },
23332 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
23333   {
23334     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mul.b", 56,
23335     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23336   },
23337 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
23338   {
23339     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mul.b", 56,
23340     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23341   },
23342 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
23343   {
23344     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mul.b", 56,
23345     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23346   },
23347 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
23348   {
23349     M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mul.b", 56,
23350     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23351   },
23352 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
23353   {
23354     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 40,
23355     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23356   },
23357 /* mul.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
23358   {
23359     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 40,
23360     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23361   },
23362 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
23363   {
23364     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 40,
23365     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23366   },
23367 /* mul.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
23368   {
23369     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 40,
23370     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23371   },
23372 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
23373   {
23374     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 40,
23375     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23376   },
23377 /* mul.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
23378   {
23379     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 40,
23380     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23381   },
23382 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
23383   {
23384     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mul.b", 48,
23385     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23386   },
23387 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
23388   {
23389     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mul.b", 48,
23390     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23391   },
23392 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
23393   {
23394     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mul.b", 56,
23395     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23396   },
23397 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
23398   {
23399     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mul.b", 56,
23400     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23401   },
23402 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
23403   {
23404     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mul.b", 64,
23405     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23406   },
23407 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
23408   {
23409     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mul.b", 64,
23410     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23411   },
23412 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
23413   {
23414     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mul.b", 48,
23415     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23416   },
23417 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
23418   {
23419     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mul.b", 48,
23420     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23421   },
23422 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
23423   {
23424     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mul.b", 56,
23425     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23426   },
23427 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
23428   {
23429     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mul.b", 56,
23430     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23431   },
23432 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
23433   {
23434     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mul.b", 48,
23435     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23436   },
23437 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
23438   {
23439     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mul.b", 48,
23440     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23441   },
23442 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
23443   {
23444     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mul.b", 56,
23445     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23446   },
23447 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
23448   {
23449     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mul.b", 56,
23450     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23451   },
23452 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
23453   {
23454     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mul.b", 56,
23455     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23456   },
23457 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
23458   {
23459     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mul.b", 56,
23460     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23461   },
23462 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
23463   {
23464     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mul.b", 64,
23465     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23466   },
23467 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
23468   {
23469     M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mul.b", 64,
23470     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23471   },
23472 /* mul.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
23473   {
23474     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 16,
23475     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23476   },
23477 /* mul.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
23478   {
23479     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 16,
23480     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23481   },
23482 /* mul.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
23483   {
23484     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 16,
23485     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23486   },
23487 /* mul.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
23488   {
23489     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 16,
23490     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23491   },
23492 /* mul.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
23493   {
23494     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 16,
23495     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23496   },
23497 /* mul.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
23498   {
23499     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 16,
23500     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23501   },
23502 /* mul.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
23503   {
23504     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 16,
23505     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23506   },
23507 /* mul.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
23508   {
23509     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 16,
23510     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23511   },
23512 /* mul.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
23513   {
23514     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 16,
23515     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23516   },
23517 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
23518   {
23519     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mul.b", 24,
23520     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23521   },
23522 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
23523   {
23524     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mul.b", 24,
23525     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23526   },
23527 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
23528   {
23529     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mul.b", 24,
23530     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23531   },
23532 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
23533   {
23534     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mul.b", 32,
23535     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23536   },
23537 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
23538   {
23539     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mul.b", 32,
23540     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23541   },
23542 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
23543   {
23544     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mul.b", 32,
23545     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23546   },
23547 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
23548   {
23549     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mul.b", 40,
23550     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23551   },
23552 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
23553   {
23554     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mul.b", 40,
23555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23556   },
23557 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
23558   {
23559     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mul.b", 40,
23560     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23561   },
23562 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
23563   {
23564     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mul.b", 24,
23565     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23566   },
23567 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
23568   {
23569     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mul.b", 24,
23570     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23571   },
23572 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
23573   {
23574     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mul.b", 24,
23575     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23576   },
23577 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
23578   {
23579     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mul.b", 32,
23580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23581   },
23582 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
23583   {
23584     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mul.b", 32,
23585     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23586   },
23587 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
23588   {
23589     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mul.b", 32,
23590     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23591   },
23592 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
23593   {
23594     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mul.b", 24,
23595     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23596   },
23597 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
23598   {
23599     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mul.b", 24,
23600     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23601   },
23602 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
23603   {
23604     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mul.b", 24,
23605     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23606   },
23607 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
23608   {
23609     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mul.b", 32,
23610     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23611   },
23612 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
23613   {
23614     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mul.b", 32,
23615     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23616   },
23617 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
23618   {
23619     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mul.b", 32,
23620     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23621   },
23622 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
23623   {
23624     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mul.b", 32,
23625     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23626   },
23627 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
23628   {
23629     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mul.b", 32,
23630     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23631   },
23632 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
23633   {
23634     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mul.b", 32,
23635     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23636   },
23637 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
23638   {
23639     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mul.b", 40,
23640     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23641   },
23642 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
23643   {
23644     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mul.b", 40,
23645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23646   },
23647 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
23648   {
23649     M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mul.b", 40,
23650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23651   },
23652 /* mul.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
23653   {
23654     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "mul.w", 24,
23655     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23656   },
23657 /* mul.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
23658   {
23659     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "mul.w", 24,
23660     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23661   },
23662 /* mul.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
23663   {
23664     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "mul.w", 24,
23665     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23666   },
23667 /* mul.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
23668   {
23669     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "mul.w", 24,
23670     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23671   },
23672 /* mul.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
23673   {
23674     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "mul.w", 24,
23675     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23676   },
23677 /* mul.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
23678   {
23679     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "mul.w", 24,
23680     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23681   },
23682 /* mul.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
23683   {
23684     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "mul.w", 24,
23685     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23686   },
23687 /* mul.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
23688   {
23689     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "mul.w", 24,
23690     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23691   },
23692 /* mul.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
23693   {
23694     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "mul.w", 24,
23695     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23696   },
23697 /* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
23698   {
23699     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "mul.w", 32,
23700     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23701   },
23702 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
23703   {
23704     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "mul.w", 32,
23705     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23706   },
23707 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
23708   {
23709     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "mul.w", 32,
23710     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23711   },
23712 /* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
23713   {
23714     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "mul.w", 40,
23715     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23716   },
23717 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
23718   {
23719     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "mul.w", 40,
23720     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23721   },
23722 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
23723   {
23724     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "mul.w", 40,
23725     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23726   },
23727 /* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
23728   {
23729     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "mul.w", 32,
23730     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23731   },
23732 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
23733   {
23734     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "mul.w", 32,
23735     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23736   },
23737 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
23738   {
23739     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "mul.w", 32,
23740     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23741   },
23742 /* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
23743   {
23744     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "mul.w", 40,
23745     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23746   },
23747 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
23748   {
23749     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "mul.w", 40,
23750     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23751   },
23752 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
23753   {
23754     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "mul.w", 40,
23755     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23756   },
23757 /* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
23758   {
23759     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "mul.w", 32,
23760     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23761   },
23762 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
23763   {
23764     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "mul.w", 32,
23765     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23766   },
23767 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
23768   {
23769     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "mul.w", 32,
23770     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23771   },
23772 /* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
23773   {
23774     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "mul.w", 40,
23775     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23776   },
23777 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
23778   {
23779     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "mul.w", 40,
23780     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23781   },
23782 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
23783   {
23784     M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "mul.w", 40,
23785     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23786   },
23787 /* mul.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
23788   {
23789     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "mul.w", 32,
23790     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23791   },
23792 /* mul.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
23793   {
23794     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "mul.w", 32,
23795     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23796   },
23797 /* mul.w${G} ${Dsp-16-u16},$Dst16RnHI */
23798   {
23799     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "mul.w", 32,
23800     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23801   },
23802 /* mul.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
23803   {
23804     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "mul.w", 32,
23805     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23806   },
23807 /* mul.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
23808   {
23809     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "mul.w", 32,
23810     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23811   },
23812 /* mul.w${G} ${Dsp-16-u16},$Dst16AnHI */
23813   {
23814     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "mul.w", 32,
23815     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23816   },
23817 /* mul.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
23818   {
23819     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "mul.w", 32,
23820     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23821   },
23822 /* mul.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
23823   {
23824     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "mul.w", 32,
23825     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23826   },
23827 /* mul.w${G} ${Dsp-16-u16},[$Dst16An] */
23828   {
23829     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "mul.w", 32,
23830     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23831   },
23832 /* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
23833   {
23834     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "mul.w", 40,
23835     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23836   },
23837 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
23838   {
23839     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "mul.w", 40,
23840     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23841   },
23842 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
23843   {
23844     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "mul.w", 40,
23845     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23846   },
23847 /* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
23848   {
23849     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "mul.w", 48,
23850     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23851   },
23852 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
23853   {
23854     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "mul.w", 48,
23855     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23856   },
23857 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
23858   {
23859     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "mul.w", 48,
23860     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23861   },
23862 /* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
23863   {
23864     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "mul.w", 40,
23865     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23866   },
23867 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
23868   {
23869     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "mul.w", 40,
23870     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23871   },
23872 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
23873   {
23874     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "mul.w", 40,
23875     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23876   },
23877 /* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
23878   {
23879     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "mul.w", 48,
23880     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23881   },
23882 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
23883   {
23884     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "mul.w", 48,
23885     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23886   },
23887 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
23888   {
23889     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "mul.w", 48,
23890     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23891   },
23892 /* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
23893   {
23894     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "mul.w", 40,
23895     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23896   },
23897 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
23898   {
23899     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "mul.w", 40,
23900     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23901   },
23902 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
23903   {
23904     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "mul.w", 40,
23905     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23906   },
23907 /* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
23908   {
23909     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "mul.w", 48,
23910     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23911   },
23912 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
23913   {
23914     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "mul.w", 48,
23915     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23916   },
23917 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
23918   {
23919     M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "mul.w", 48,
23920     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23921   },
23922 /* mul.w${G} $Src16RnHI,$Dst16RnHI */
23923   {
23924     M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "mul.w", 16,
23925     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23926   },
23927 /* mul.w${G} $Src16AnHI,$Dst16RnHI */
23928   {
23929     M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "mul.w", 16,
23930     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23931   },
23932 /* mul.w${G} [$Src16An],$Dst16RnHI */
23933   {
23934     M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "mul.w", 16,
23935     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23936   },
23937 /* mul.w${G} $Src16RnHI,$Dst16AnHI */
23938   {
23939     M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "mul.w", 16,
23940     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23941   },
23942 /* mul.w${G} $Src16AnHI,$Dst16AnHI */
23943   {
23944     M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "mul.w", 16,
23945     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23946   },
23947 /* mul.w${G} [$Src16An],$Dst16AnHI */
23948   {
23949     M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "mul.w", 16,
23950     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23951   },
23952 /* mul.w${G} $Src16RnHI,[$Dst16An] */
23953   {
23954     M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "mul.w", 16,
23955     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23956   },
23957 /* mul.w${G} $Src16AnHI,[$Dst16An] */
23958   {
23959     M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "mul.w", 16,
23960     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23961   },
23962 /* mul.w${G} [$Src16An],[$Dst16An] */
23963   {
23964     M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "mul.w", 16,
23965     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23966   },
23967 /* mul.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
23968   {
23969     M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "mul.w", 24,
23970     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23971   },
23972 /* mul.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
23973   {
23974     M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "mul.w", 24,
23975     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23976   },
23977 /* mul.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
23978   {
23979     M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "mul.w", 24,
23980     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23981   },
23982 /* mul.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
23983   {
23984     M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "mul.w", 32,
23985     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23986   },
23987 /* mul.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
23988   {
23989     M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "mul.w", 32,
23990     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23991   },
23992 /* mul.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
23993   {
23994     M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "mul.w", 32,
23995     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23996   },
23997 /* mul.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
23998   {
23999     M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "mul.w", 24,
24000     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24001   },
24002 /* mul.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
24003   {
24004     M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "mul.w", 24,
24005     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24006   },
24007 /* mul.w${G} [$Src16An],${Dsp-16-u8}[sb] */
24008   {
24009     M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "mul.w", 24,
24010     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24011   },
24012 /* mul.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
24013   {
24014     M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "mul.w", 32,
24015     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24016   },
24017 /* mul.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
24018   {
24019     M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "mul.w", 32,
24020     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24021   },
24022 /* mul.w${G} [$Src16An],${Dsp-16-u16}[sb] */
24023   {
24024     M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "mul.w", 32,
24025     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24026   },
24027 /* mul.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
24028   {
24029     M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "mul.w", 24,
24030     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24031   },
24032 /* mul.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
24033   {
24034     M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "mul.w", 24,
24035     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24036   },
24037 /* mul.w${G} [$Src16An],${Dsp-16-s8}[fb] */
24038   {
24039     M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "mul.w", 24,
24040     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24041   },
24042 /* mul.w${G} $Src16RnHI,${Dsp-16-u16} */
24043   {
24044     M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "mul.w", 32,
24045     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24046   },
24047 /* mul.w${G} $Src16AnHI,${Dsp-16-u16} */
24048   {
24049     M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "mul.w", 32,
24050     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24051   },
24052 /* mul.w${G} [$Src16An],${Dsp-16-u16} */
24053   {
24054     M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "mul.w", 32,
24055     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24056   },
24057 /* mul.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
24058   {
24059     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "mul.b", 24,
24060     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24061   },
24062 /* mul.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
24063   {
24064     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "mul.b", 24,
24065     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24066   },
24067 /* mul.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
24068   {
24069     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "mul.b", 24,
24070     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24071   },
24072 /* mul.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
24073   {
24074     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "mul.b", 24,
24075     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24076   },
24077 /* mul.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
24078   {
24079     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "mul.b", 24,
24080     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24081   },
24082 /* mul.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
24083   {
24084     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "mul.b", 24,
24085     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24086   },
24087 /* mul.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
24088   {
24089     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "mul.b", 24,
24090     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24091   },
24092 /* mul.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
24093   {
24094     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "mul.b", 24,
24095     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24096   },
24097 /* mul.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
24098   {
24099     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "mul.b", 24,
24100     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24101   },
24102 /* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
24103   {
24104     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "mul.b", 32,
24105     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24106   },
24107 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
24108   {
24109     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "mul.b", 32,
24110     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24111   },
24112 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
24113   {
24114     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "mul.b", 32,
24115     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24116   },
24117 /* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
24118   {
24119     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "mul.b", 40,
24120     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24121   },
24122 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
24123   {
24124     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "mul.b", 40,
24125     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24126   },
24127 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
24128   {
24129     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "mul.b", 40,
24130     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24131   },
24132 /* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
24133   {
24134     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "mul.b", 32,
24135     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24136   },
24137 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
24138   {
24139     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "mul.b", 32,
24140     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24141   },
24142 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
24143   {
24144     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "mul.b", 32,
24145     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24146   },
24147 /* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
24148   {
24149     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "mul.b", 40,
24150     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24151   },
24152 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
24153   {
24154     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "mul.b", 40,
24155     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24156   },
24157 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
24158   {
24159     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "mul.b", 40,
24160     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24161   },
24162 /* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
24163   {
24164     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "mul.b", 32,
24165     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24166   },
24167 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
24168   {
24169     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "mul.b", 32,
24170     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24171   },
24172 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
24173   {
24174     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "mul.b", 32,
24175     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24176   },
24177 /* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
24178   {
24179     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "mul.b", 40,
24180     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24181   },
24182 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
24183   {
24184     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "mul.b", 40,
24185     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24186   },
24187 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
24188   {
24189     M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "mul.b", 40,
24190     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24191   },
24192 /* mul.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
24193   {
24194     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "mul.b", 32,
24195     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24196   },
24197 /* mul.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
24198   {
24199     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "mul.b", 32,
24200     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24201   },
24202 /* mul.b${G} ${Dsp-16-u16},$Dst16RnQI */
24203   {
24204     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "mul.b", 32,
24205     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24206   },
24207 /* mul.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
24208   {
24209     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "mul.b", 32,
24210     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24211   },
24212 /* mul.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
24213   {
24214     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "mul.b", 32,
24215     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24216   },
24217 /* mul.b${G} ${Dsp-16-u16},$Dst16AnQI */
24218   {
24219     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "mul.b", 32,
24220     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24221   },
24222 /* mul.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
24223   {
24224     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "mul.b", 32,
24225     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24226   },
24227 /* mul.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
24228   {
24229     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "mul.b", 32,
24230     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24231   },
24232 /* mul.b${G} ${Dsp-16-u16},[$Dst16An] */
24233   {
24234     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "mul.b", 32,
24235     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24236   },
24237 /* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
24238   {
24239     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "mul.b", 40,
24240     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24241   },
24242 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
24243   {
24244     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "mul.b", 40,
24245     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24246   },
24247 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
24248   {
24249     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "mul.b", 40,
24250     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24251   },
24252 /* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
24253   {
24254     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "mul.b", 48,
24255     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24256   },
24257 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
24258   {
24259     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "mul.b", 48,
24260     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24261   },
24262 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
24263   {
24264     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "mul.b", 48,
24265     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24266   },
24267 /* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
24268   {
24269     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "mul.b", 40,
24270     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24271   },
24272 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
24273   {
24274     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "mul.b", 40,
24275     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24276   },
24277 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
24278   {
24279     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "mul.b", 40,
24280     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24281   },
24282 /* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
24283   {
24284     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "mul.b", 48,
24285     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24286   },
24287 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
24288   {
24289     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "mul.b", 48,
24290     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24291   },
24292 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
24293   {
24294     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "mul.b", 48,
24295     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24296   },
24297 /* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
24298   {
24299     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "mul.b", 40,
24300     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24301   },
24302 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
24303   {
24304     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "mul.b", 40,
24305     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24306   },
24307 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
24308   {
24309     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "mul.b", 40,
24310     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24311   },
24312 /* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
24313   {
24314     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "mul.b", 48,
24315     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24316   },
24317 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
24318   {
24319     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "mul.b", 48,
24320     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24321   },
24322 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
24323   {
24324     M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "mul.b", 48,
24325     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24326   },
24327 /* mul.b${G} $Src16RnQI,$Dst16RnQI */
24328   {
24329     M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "mul.b", 16,
24330     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24331   },
24332 /* mul.b${G} $Src16AnQI,$Dst16RnQI */
24333   {
24334     M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "mul.b", 16,
24335     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24336   },
24337 /* mul.b${G} [$Src16An],$Dst16RnQI */
24338   {
24339     M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "mul.b", 16,
24340     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24341   },
24342 /* mul.b${G} $Src16RnQI,$Dst16AnQI */
24343   {
24344     M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "mul.b", 16,
24345     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24346   },
24347 /* mul.b${G} $Src16AnQI,$Dst16AnQI */
24348   {
24349     M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "mul.b", 16,
24350     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24351   },
24352 /* mul.b${G} [$Src16An],$Dst16AnQI */
24353   {
24354     M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "mul.b", 16,
24355     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24356   },
24357 /* mul.b${G} $Src16RnQI,[$Dst16An] */
24358   {
24359     M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "mul.b", 16,
24360     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24361   },
24362 /* mul.b${G} $Src16AnQI,[$Dst16An] */
24363   {
24364     M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "mul.b", 16,
24365     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24366   },
24367 /* mul.b${G} [$Src16An],[$Dst16An] */
24368   {
24369     M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "mul.b", 16,
24370     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24371   },
24372 /* mul.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
24373   {
24374     M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "mul.b", 24,
24375     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24376   },
24377 /* mul.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
24378   {
24379     M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "mul.b", 24,
24380     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24381   },
24382 /* mul.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
24383   {
24384     M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "mul.b", 24,
24385     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24386   },
24387 /* mul.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
24388   {
24389     M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "mul.b", 32,
24390     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24391   },
24392 /* mul.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
24393   {
24394     M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "mul.b", 32,
24395     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24396   },
24397 /* mul.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
24398   {
24399     M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "mul.b", 32,
24400     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24401   },
24402 /* mul.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
24403   {
24404     M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "mul.b", 24,
24405     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24406   },
24407 /* mul.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
24408   {
24409     M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "mul.b", 24,
24410     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24411   },
24412 /* mul.b${G} [$Src16An],${Dsp-16-u8}[sb] */
24413   {
24414     M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "mul.b", 24,
24415     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24416   },
24417 /* mul.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
24418   {
24419     M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "mul.b", 32,
24420     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24421   },
24422 /* mul.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
24423   {
24424     M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "mul.b", 32,
24425     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24426   },
24427 /* mul.b${G} [$Src16An],${Dsp-16-u16}[sb] */
24428   {
24429     M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "mul.b", 32,
24430     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24431   },
24432 /* mul.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
24433   {
24434     M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "mul.b", 24,
24435     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24436   },
24437 /* mul.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
24438   {
24439     M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "mul.b", 24,
24440     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24441   },
24442 /* mul.b${G} [$Src16An],${Dsp-16-s8}[fb] */
24443   {
24444     M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "mul.b", 24,
24445     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24446   },
24447 /* mul.b${G} $Src16RnQI,${Dsp-16-u16} */
24448   {
24449     M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "mul.b", 32,
24450     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24451   },
24452 /* mul.b${G} $Src16AnQI,${Dsp-16-u16} */
24453   {
24454     M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "mul.b", 32,
24455     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24456   },
24457 /* mul.b${G} [$Src16An],${Dsp-16-u16} */
24458   {
24459     M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "mul.b", 32,
24460     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24461   },
24462 /* mul.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
24463   {
24464     M32C_INSN_MUL32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32,
24465     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24466   },
24467 /* mul.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
24468   {
24469     M32C_INSN_MUL32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mul.w", 32,
24470     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24471   },
24472 /* mul.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
24473   {
24474     M32C_INSN_MUL32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mul.w", 32,
24475     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24476   },
24477 /* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
24478   {
24479     M32C_INSN_MUL32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mul.w", 40,
24480     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24481   },
24482 /* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
24483   {
24484     M32C_INSN_MUL32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mul.w", 40,
24485     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24486   },
24487 /* mul.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
24488   {
24489     M32C_INSN_MUL32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mul.w", 40,
24490     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24491   },
24492 /* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
24493   {
24494     M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mul.w", 48,
24495     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24496   },
24497 /* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
24498   {
24499     M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mul.w", 48,
24500     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24501   },
24502 /* mul.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
24503   {
24504     M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mul.w", 48,
24505     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24506   },
24507 /* mul.w${G} #${Imm-32-HI},${Dsp-16-u16} */
24508   {
24509     M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mul.w", 48,
24510     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24511   },
24512 /* mul.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
24513   {
24514     M32C_INSN_MUL32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mul.w", 56,
24515     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24516   },
24517 /* mul.w${G} #${Imm-40-HI},${Dsp-16-u24} */
24518   {
24519     M32C_INSN_MUL32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mul.w", 56,
24520     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24521   },
24522 /* mul.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
24523   {
24524     M32C_INSN_MUL32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mul.b", 24,
24525     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24526   },
24527 /* mul.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
24528   {
24529     M32C_INSN_MUL32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mul.b", 24,
24530     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24531   },
24532 /* mul.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
24533   {
24534     M32C_INSN_MUL32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mul.b", 24,
24535     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24536   },
24537 /* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
24538   {
24539     M32C_INSN_MUL32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mul.b", 32,
24540     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24541   },
24542 /* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
24543   {
24544     M32C_INSN_MUL32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mul.b", 32,
24545     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24546   },
24547 /* mul.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
24548   {
24549     M32C_INSN_MUL32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mul.b", 32,
24550     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24551   },
24552 /* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
24553   {
24554     M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mul.b", 40,
24555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24556   },
24557 /* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
24558   {
24559     M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mul.b", 40,
24560     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24561   },
24562 /* mul.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
24563   {
24564     M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mul.b", 40,
24565     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24566   },
24567 /* mul.b${G} #${Imm-32-QI},${Dsp-16-u16} */
24568   {
24569     M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mul.b", 40,
24570     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24571   },
24572 /* mul.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
24573   {
24574     M32C_INSN_MUL32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mul.b", 48,
24575     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24576   },
24577 /* mul.b${G} #${Imm-40-QI},${Dsp-16-u24} */
24578   {
24579     M32C_INSN_MUL32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mul.b", 48,
24580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24581   },
24582 /* mul.w${G} #${Imm-16-HI},$Dst16RnHI */
24583   {
24584     M32C_INSN_MUL16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "mul16.w-imm-G-basic-dst16-Rn-direct-HI", "mul.w", 32,
24585     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24586   },
24587 /* mul.w${G} #${Imm-16-HI},$Dst16AnHI */
24588   {
24589     M32C_INSN_MUL16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "mul16.w-imm-G-basic-dst16-An-direct-HI", "mul.w", 32,
24590     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24591   },
24592 /* mul.w${G} #${Imm-16-HI},[$Dst16An] */
24593   {
24594     M32C_INSN_MUL16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "mul16.w-imm-G-basic-dst16-An-indirect-HI", "mul.w", 32,
24595     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24596   },
24597 /* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
24598   {
24599     M32C_INSN_MUL16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "mul16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "mul.w", 40,
24600     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24601   },
24602 /* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
24603   {
24604     M32C_INSN_MUL16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "mul16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "mul.w", 40,
24605     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24606   },
24607 /* mul.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
24608   {
24609     M32C_INSN_MUL16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "mul16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "mul.w", 40,
24610     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24611   },
24612 /* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
24613   {
24614     M32C_INSN_MUL16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "mul16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "mul.w", 48,
24615     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24616   },
24617 /* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
24618   {
24619     M32C_INSN_MUL16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "mul16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "mul.w", 48,
24620     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24621   },
24622 /* mul.w${G} #${Imm-32-HI},${Dsp-16-u16} */
24623   {
24624     M32C_INSN_MUL16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "mul16.w-imm-G-16-16-dst16-16-16-absolute-HI", "mul.w", 48,
24625     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24626   },
24627 /* mul.b${G} #${Imm-16-QI},$Dst16RnQI */
24628   {
24629     M32C_INSN_MUL16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "mul16.b-imm-G-basic-dst16-Rn-direct-QI", "mul.b", 24,
24630     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24631   },
24632 /* mul.b${G} #${Imm-16-QI},$Dst16AnQI */
24633   {
24634     M32C_INSN_MUL16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "mul16.b-imm-G-basic-dst16-An-direct-QI", "mul.b", 24,
24635     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24636   },
24637 /* mul.b${G} #${Imm-16-QI},[$Dst16An] */
24638   {
24639     M32C_INSN_MUL16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "mul16.b-imm-G-basic-dst16-An-indirect-QI", "mul.b", 24,
24640     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24641   },
24642 /* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
24643   {
24644     M32C_INSN_MUL16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "mul16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "mul.b", 32,
24645     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24646   },
24647 /* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
24648   {
24649     M32C_INSN_MUL16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "mul16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "mul.b", 32,
24650     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24651   },
24652 /* mul.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
24653   {
24654     M32C_INSN_MUL16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "mul16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "mul.b", 32,
24655     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24656   },
24657 /* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
24658   {
24659     M32C_INSN_MUL16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "mul16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "mul.b", 40,
24660     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24661   },
24662 /* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
24663   {
24664     M32C_INSN_MUL16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "mul16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "mul.b", 40,
24665     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24666   },
24667 /* mul.b${G} #${Imm-32-QI},${Dsp-16-u16} */
24668   {
24669     M32C_INSN_MUL16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "mul16.b-imm-G-16-16-dst16-16-16-absolute-QI", "mul.b", 40,
24670     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24671   },
24672 /* movx${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
24673   {
24674     M32C_INSN_MOVX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "movx32-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "movx", 24,
24675     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24676   },
24677 /* movx${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
24678   {
24679     M32C_INSN_MOVX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "movx32-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "movx", 24,
24680     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24681   },
24682 /* movx${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
24683   {
24684     M32C_INSN_MOVX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "movx32-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "movx", 24,
24685     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24686   },
24687 /* movx${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
24688   {
24689     M32C_INSN_MOVX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "movx", 32,
24690     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24691   },
24692 /* movx${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
24693   {
24694     M32C_INSN_MOVX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "movx", 32,
24695     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24696   },
24697 /* movx${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
24698   {
24699     M32C_INSN_MOVX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "movx", 32,
24700     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24701   },
24702 /* movx${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
24703   {
24704     M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "movx", 40,
24705     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24706   },
24707 /* movx${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
24708   {
24709     M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "movx", 40,
24710     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24711   },
24712 /* movx${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
24713   {
24714     M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "movx", 40,
24715     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24716   },
24717 /* movx${X} #${Imm-32-QI},${Dsp-16-u16} */
24718   {
24719     M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "movx32-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "movx", 40,
24720     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24721   },
24722 /* movx${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
24723   {
24724     M32C_INSN_MOVX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "movx", 48,
24725     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24726   },
24727 /* movx${X} #${Imm-40-QI},${Dsp-16-u24} */
24728   {
24729     M32C_INSN_MOVX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "movx32-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "movx", 48,
24730     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24731   },
24732 /* movhh $Dst32RnPrefixedQI,r0l */
24733   {
24734     M32C_INSN_MOVHH32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI, "movhh32.src-r0l-dst32-Rn-direct-Prefixed-QI", "movhh", 24,
24735     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24736   },
24737 /* movhh $Dst32AnPrefixedQI,r0l */
24738   {
24739     M32C_INSN_MOVHH32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, "movhh32.src-r0l-dst32-An-direct-Prefixed-QI", "movhh", 24,
24740     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24741   },
24742 /* movhh [$Dst32AnPrefixed],r0l */
24743   {
24744     M32C_INSN_MOVHH32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, "movhh32.src-r0l-dst32-An-indirect-Prefixed-QI", "movhh", 24,
24745     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24746   },
24747 /* movhh ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */
24748   {
24749     M32C_INSN_MOVHH32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-8-An-relative-Prefixed-QI", "movhh", 32,
24750     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24751   },
24752 /* movhh ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */
24753   {
24754     M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-16-An-relative-Prefixed-QI", "movhh", 40,
24755     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24756   },
24757 /* movhh ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */
24758   {
24759     M32C_INSN_MOVHH32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-24-An-relative-Prefixed-QI", "movhh", 48,
24760     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24761   },
24762 /* movhh ${Dsp-24-u8}[sb],r0l */
24763   {
24764     M32C_INSN_MOVHH32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-8-SB-relative-Prefixed-QI", "movhh", 32,
24765     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24766   },
24767 /* movhh ${Dsp-24-u16}[sb],r0l */
24768   {
24769     M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-16-SB-relative-Prefixed-QI", "movhh", 40,
24770     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24771   },
24772 /* movhh ${Dsp-24-s8}[fb],r0l */
24773   {
24774     M32C_INSN_MOVHH32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-8-FB-relative-Prefixed-QI", "movhh", 32,
24775     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24776   },
24777 /* movhh ${Dsp-24-s16}[fb],r0l */
24778   {
24779     M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-16-FB-relative-Prefixed-QI", "movhh", 40,
24780     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24781   },
24782 /* movhh ${Dsp-24-u16},r0l */
24783   {
24784     M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-16-absolute-Prefixed-QI", "movhh", 40,
24785     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24786   },
24787 /* movhh ${Dsp-24-u24},r0l */
24788   {
24789     M32C_INSN_MOVHH32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-24-absolute-Prefixed-QI", "movhh", 48,
24790     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24791   },
24792 /* movhl $Dst32RnPrefixedQI,r0l */
24793   {
24794     M32C_INSN_MOVHL32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI, "movhl32.src-r0l-dst32-Rn-direct-Prefixed-QI", "movhl", 24,
24795     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24796   },
24797 /* movhl $Dst32AnPrefixedQI,r0l */
24798   {
24799     M32C_INSN_MOVHL32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, "movhl32.src-r0l-dst32-An-direct-Prefixed-QI", "movhl", 24,
24800     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24801   },
24802 /* movhl [$Dst32AnPrefixed],r0l */
24803   {
24804     M32C_INSN_MOVHL32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, "movhl32.src-r0l-dst32-An-indirect-Prefixed-QI", "movhl", 24,
24805     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24806   },
24807 /* movhl ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */
24808   {
24809     M32C_INSN_MOVHL32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-8-An-relative-Prefixed-QI", "movhl", 32,
24810     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24811   },
24812 /* movhl ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */
24813   {
24814     M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-16-An-relative-Prefixed-QI", "movhl", 40,
24815     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24816   },
24817 /* movhl ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */
24818   {
24819     M32C_INSN_MOVHL32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-24-An-relative-Prefixed-QI", "movhl", 48,
24820     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24821   },
24822 /* movhl ${Dsp-24-u8}[sb],r0l */
24823   {
24824     M32C_INSN_MOVHL32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-8-SB-relative-Prefixed-QI", "movhl", 32,
24825     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24826   },
24827 /* movhl ${Dsp-24-u16}[sb],r0l */
24828   {
24829     M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-16-SB-relative-Prefixed-QI", "movhl", 40,
24830     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24831   },
24832 /* movhl ${Dsp-24-s8}[fb],r0l */
24833   {
24834     M32C_INSN_MOVHL32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-8-FB-relative-Prefixed-QI", "movhl", 32,
24835     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24836   },
24837 /* movhl ${Dsp-24-s16}[fb],r0l */
24838   {
24839     M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-16-FB-relative-Prefixed-QI", "movhl", 40,
24840     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24841   },
24842 /* movhl ${Dsp-24-u16},r0l */
24843   {
24844     M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-16-absolute-Prefixed-QI", "movhl", 40,
24845     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24846   },
24847 /* movhl ${Dsp-24-u24},r0l */
24848   {
24849     M32C_INSN_MOVHL32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-24-absolute-Prefixed-QI", "movhl", 48,
24850     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24851   },
24852 /* movlh $Dst32RnPrefixedQI,r0l */
24853   {
24854     M32C_INSN_MOVLH32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI, "movlh32.src-r0l-dst32-Rn-direct-Prefixed-QI", "movlh", 24,
24855     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24856   },
24857 /* movlh $Dst32AnPrefixedQI,r0l */
24858   {
24859     M32C_INSN_MOVLH32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, "movlh32.src-r0l-dst32-An-direct-Prefixed-QI", "movlh", 24,
24860     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24861   },
24862 /* movlh [$Dst32AnPrefixed],r0l */
24863   {
24864     M32C_INSN_MOVLH32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, "movlh32.src-r0l-dst32-An-indirect-Prefixed-QI", "movlh", 24,
24865     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24866   },
24867 /* movlh ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */
24868   {
24869     M32C_INSN_MOVLH32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-8-An-relative-Prefixed-QI", "movlh", 32,
24870     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24871   },
24872 /* movlh ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */
24873   {
24874     M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-16-An-relative-Prefixed-QI", "movlh", 40,
24875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24876   },
24877 /* movlh ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */
24878   {
24879     M32C_INSN_MOVLH32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-24-An-relative-Prefixed-QI", "movlh", 48,
24880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24881   },
24882 /* movlh ${Dsp-24-u8}[sb],r0l */
24883   {
24884     M32C_INSN_MOVLH32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-8-SB-relative-Prefixed-QI", "movlh", 32,
24885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24886   },
24887 /* movlh ${Dsp-24-u16}[sb],r0l */
24888   {
24889     M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-16-SB-relative-Prefixed-QI", "movlh", 40,
24890     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24891   },
24892 /* movlh ${Dsp-24-s8}[fb],r0l */
24893   {
24894     M32C_INSN_MOVLH32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-8-FB-relative-Prefixed-QI", "movlh", 32,
24895     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24896   },
24897 /* movlh ${Dsp-24-s16}[fb],r0l */
24898   {
24899     M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-16-FB-relative-Prefixed-QI", "movlh", 40,
24900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24901   },
24902 /* movlh ${Dsp-24-u16},r0l */
24903   {
24904     M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-16-absolute-Prefixed-QI", "movlh", 40,
24905     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24906   },
24907 /* movlh ${Dsp-24-u24},r0l */
24908   {
24909     M32C_INSN_MOVLH32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-24-absolute-Prefixed-QI", "movlh", 48,
24910     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24911   },
24912 /* movll $Dst32RnPrefixedQI,r0l */
24913   {
24914     M32C_INSN_MOVLL32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI, "movll32.src-r0l-dst32-Rn-direct-Prefixed-QI", "movll", 24,
24915     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24916   },
24917 /* movll $Dst32AnPrefixedQI,r0l */
24918   {
24919     M32C_INSN_MOVLL32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, "movll32.src-r0l-dst32-An-direct-Prefixed-QI", "movll", 24,
24920     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24921   },
24922 /* movll [$Dst32AnPrefixed],r0l */
24923   {
24924     M32C_INSN_MOVLL32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, "movll32.src-r0l-dst32-An-indirect-Prefixed-QI", "movll", 24,
24925     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24926   },
24927 /* movll ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */
24928   {
24929     M32C_INSN_MOVLL32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-8-An-relative-Prefixed-QI", "movll", 32,
24930     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24931   },
24932 /* movll ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */
24933   {
24934     M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-16-An-relative-Prefixed-QI", "movll", 40,
24935     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24936   },
24937 /* movll ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */
24938   {
24939     M32C_INSN_MOVLL32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-24-An-relative-Prefixed-QI", "movll", 48,
24940     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24941   },
24942 /* movll ${Dsp-24-u8}[sb],r0l */
24943   {
24944     M32C_INSN_MOVLL32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-8-SB-relative-Prefixed-QI", "movll", 32,
24945     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24946   },
24947 /* movll ${Dsp-24-u16}[sb],r0l */
24948   {
24949     M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-16-SB-relative-Prefixed-QI", "movll", 40,
24950     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24951   },
24952 /* movll ${Dsp-24-s8}[fb],r0l */
24953   {
24954     M32C_INSN_MOVLL32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-8-FB-relative-Prefixed-QI", "movll", 32,
24955     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24956   },
24957 /* movll ${Dsp-24-s16}[fb],r0l */
24958   {
24959     M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-16-FB-relative-Prefixed-QI", "movll", 40,
24960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24961   },
24962 /* movll ${Dsp-24-u16},r0l */
24963   {
24964     M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movll32.src-r0l-dst32-24-16-absolute-Prefixed-QI", "movll", 40,
24965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24966   },
24967 /* movll ${Dsp-24-u24},r0l */
24968   {
24969     M32C_INSN_MOVLL32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movll32.src-r0l-dst32-24-24-absolute-Prefixed-QI", "movll", 48,
24970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24971   },
24972 /* movhh r0l,$Dst32RnPrefixedQI */
24973   {
24974     M32C_INSN_MOVHH32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI, "movhh32.r0l-dst-dst32-Rn-direct-Prefixed-QI", "movhh", 24,
24975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24976   },
24977 /* movhh r0l,$Dst32AnPrefixedQI */
24978   {
24979     M32C_INSN_MOVHH32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, "movhh32.r0l-dst-dst32-An-direct-Prefixed-QI", "movhh", 24,
24980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24981   },
24982 /* movhh r0l,[$Dst32AnPrefixed] */
24983   {
24984     M32C_INSN_MOVHH32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, "movhh32.r0l-dst-dst32-An-indirect-Prefixed-QI", "movhh", 24,
24985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24986   },
24987 /* movhh r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */
24988   {
24989     M32C_INSN_MOVHH32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-8-An-relative-Prefixed-QI", "movhh", 32,
24990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24991   },
24992 /* movhh r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */
24993   {
24994     M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-16-An-relative-Prefixed-QI", "movhh", 40,
24995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24996   },
24997 /* movhh r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */
24998   {
24999     M32C_INSN_MOVHH32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-24-An-relative-Prefixed-QI", "movhh", 48,
25000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25001   },
25002 /* movhh r0l,${Dsp-24-u8}[sb] */
25003   {
25004     M32C_INSN_MOVHH32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-8-SB-relative-Prefixed-QI", "movhh", 32,
25005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25006   },
25007 /* movhh r0l,${Dsp-24-u16}[sb] */
25008   {
25009     M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-16-SB-relative-Prefixed-QI", "movhh", 40,
25010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25011   },
25012 /* movhh r0l,${Dsp-24-s8}[fb] */
25013   {
25014     M32C_INSN_MOVHH32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-8-FB-relative-Prefixed-QI", "movhh", 32,
25015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25016   },
25017 /* movhh r0l,${Dsp-24-s16}[fb] */
25018   {
25019     M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-16-FB-relative-Prefixed-QI", "movhh", 40,
25020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25021   },
25022 /* movhh r0l,${Dsp-24-u16} */
25023   {
25024     M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-16-absolute-Prefixed-QI", "movhh", 40,
25025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25026   },
25027 /* movhh r0l,${Dsp-24-u24} */
25028   {
25029     M32C_INSN_MOVHH32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-24-absolute-Prefixed-QI", "movhh", 48,
25030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25031   },
25032 /* movhl r0l,$Dst32RnPrefixedQI */
25033   {
25034     M32C_INSN_MOVHL32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI, "movhl32.r0l-dst-dst32-Rn-direct-Prefixed-QI", "movhl", 24,
25035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25036   },
25037 /* movhl r0l,$Dst32AnPrefixedQI */
25038   {
25039     M32C_INSN_MOVHL32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, "movhl32.r0l-dst-dst32-An-direct-Prefixed-QI", "movhl", 24,
25040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25041   },
25042 /* movhl r0l,[$Dst32AnPrefixed] */
25043   {
25044     M32C_INSN_MOVHL32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, "movhl32.r0l-dst-dst32-An-indirect-Prefixed-QI", "movhl", 24,
25045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25046   },
25047 /* movhl r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */
25048   {
25049     M32C_INSN_MOVHL32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-8-An-relative-Prefixed-QI", "movhl", 32,
25050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25051   },
25052 /* movhl r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */
25053   {
25054     M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-16-An-relative-Prefixed-QI", "movhl", 40,
25055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25056   },
25057 /* movhl r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */
25058   {
25059     M32C_INSN_MOVHL32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-24-An-relative-Prefixed-QI", "movhl", 48,
25060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25061   },
25062 /* movhl r0l,${Dsp-24-u8}[sb] */
25063   {
25064     M32C_INSN_MOVHL32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-8-SB-relative-Prefixed-QI", "movhl", 32,
25065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25066   },
25067 /* movhl r0l,${Dsp-24-u16}[sb] */
25068   {
25069     M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-16-SB-relative-Prefixed-QI", "movhl", 40,
25070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25071   },
25072 /* movhl r0l,${Dsp-24-s8}[fb] */
25073   {
25074     M32C_INSN_MOVHL32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-8-FB-relative-Prefixed-QI", "movhl", 32,
25075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25076   },
25077 /* movhl r0l,${Dsp-24-s16}[fb] */
25078   {
25079     M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-16-FB-relative-Prefixed-QI", "movhl", 40,
25080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25081   },
25082 /* movhl r0l,${Dsp-24-u16} */
25083   {
25084     M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-16-absolute-Prefixed-QI", "movhl", 40,
25085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25086   },
25087 /* movhl r0l,${Dsp-24-u24} */
25088   {
25089     M32C_INSN_MOVHL32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-24-absolute-Prefixed-QI", "movhl", 48,
25090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25091   },
25092 /* movlh r0l,$Dst32RnPrefixedQI */
25093   {
25094     M32C_INSN_MOVLH32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI, "movlh32.r0l-dst-dst32-Rn-direct-Prefixed-QI", "movlh", 24,
25095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25096   },
25097 /* movlh r0l,$Dst32AnPrefixedQI */
25098   {
25099     M32C_INSN_MOVLH32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, "movlh32.r0l-dst-dst32-An-direct-Prefixed-QI", "movlh", 24,
25100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25101   },
25102 /* movlh r0l,[$Dst32AnPrefixed] */
25103   {
25104     M32C_INSN_MOVLH32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, "movlh32.r0l-dst-dst32-An-indirect-Prefixed-QI", "movlh", 24,
25105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25106   },
25107 /* movlh r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */
25108   {
25109     M32C_INSN_MOVLH32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-8-An-relative-Prefixed-QI", "movlh", 32,
25110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25111   },
25112 /* movlh r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */
25113   {
25114     M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-16-An-relative-Prefixed-QI", "movlh", 40,
25115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25116   },
25117 /* movlh r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */
25118   {
25119     M32C_INSN_MOVLH32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-24-An-relative-Prefixed-QI", "movlh", 48,
25120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25121   },
25122 /* movlh r0l,${Dsp-24-u8}[sb] */
25123   {
25124     M32C_INSN_MOVLH32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-8-SB-relative-Prefixed-QI", "movlh", 32,
25125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25126   },
25127 /* movlh r0l,${Dsp-24-u16}[sb] */
25128   {
25129     M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-16-SB-relative-Prefixed-QI", "movlh", 40,
25130     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25131   },
25132 /* movlh r0l,${Dsp-24-s8}[fb] */
25133   {
25134     M32C_INSN_MOVLH32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-8-FB-relative-Prefixed-QI", "movlh", 32,
25135     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25136   },
25137 /* movlh r0l,${Dsp-24-s16}[fb] */
25138   {
25139     M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-16-FB-relative-Prefixed-QI", "movlh", 40,
25140     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25141   },
25142 /* movlh r0l,${Dsp-24-u16} */
25143   {
25144     M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-16-absolute-Prefixed-QI", "movlh", 40,
25145     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25146   },
25147 /* movlh r0l,${Dsp-24-u24} */
25148   {
25149     M32C_INSN_MOVLH32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-24-absolute-Prefixed-QI", "movlh", 48,
25150     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25151   },
25152 /* movll r0l,$Dst32RnPrefixedQI */
25153   {
25154     M32C_INSN_MOVLL32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI, "movll32.r0l-dst-dst32-Rn-direct-Prefixed-QI", "movll", 24,
25155     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25156   },
25157 /* movll r0l,$Dst32AnPrefixedQI */
25158   {
25159     M32C_INSN_MOVLL32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, "movll32.r0l-dst-dst32-An-direct-Prefixed-QI", "movll", 24,
25160     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25161   },
25162 /* movll r0l,[$Dst32AnPrefixed] */
25163   {
25164     M32C_INSN_MOVLL32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, "movll32.r0l-dst-dst32-An-indirect-Prefixed-QI", "movll", 24,
25165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25166   },
25167 /* movll r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */
25168   {
25169     M32C_INSN_MOVLL32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-8-An-relative-Prefixed-QI", "movll", 32,
25170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25171   },
25172 /* movll r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */
25173   {
25174     M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-16-An-relative-Prefixed-QI", "movll", 40,
25175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25176   },
25177 /* movll r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */
25178   {
25179     M32C_INSN_MOVLL32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-24-An-relative-Prefixed-QI", "movll", 48,
25180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25181   },
25182 /* movll r0l,${Dsp-24-u8}[sb] */
25183   {
25184     M32C_INSN_MOVLL32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-8-SB-relative-Prefixed-QI", "movll", 32,
25185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25186   },
25187 /* movll r0l,${Dsp-24-u16}[sb] */
25188   {
25189     M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-16-SB-relative-Prefixed-QI", "movll", 40,
25190     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25191   },
25192 /* movll r0l,${Dsp-24-s8}[fb] */
25193   {
25194     M32C_INSN_MOVLL32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-8-FB-relative-Prefixed-QI", "movll", 32,
25195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25196   },
25197 /* movll r0l,${Dsp-24-s16}[fb] */
25198   {
25199     M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-16-FB-relative-Prefixed-QI", "movll", 40,
25200     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25201   },
25202 /* movll r0l,${Dsp-24-u16} */
25203   {
25204     M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-16-absolute-Prefixed-QI", "movll", 40,
25205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25206   },
25207 /* movll r0l,${Dsp-24-u24} */
25208   {
25209     M32C_INSN_MOVLL32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-24-absolute-Prefixed-QI", "movll", 48,
25210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25211   },
25212 /* movhh $Dst16RnQI,r0l */
25213   {
25214     M32C_INSN_MOVHH16_SRC_R0L_DST16_RN_DIRECT_QI, "movhh16.src-r0l-dst16-Rn-direct-QI", "movhh", 16,
25215     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25216   },
25217 /* movhh $Dst16AnQI,r0l */
25218   {
25219     M32C_INSN_MOVHH16_SRC_R0L_DST16_AN_DIRECT_QI, "movhh16.src-r0l-dst16-An-direct-QI", "movhh", 16,
25220     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25221   },
25222 /* movhh [$Dst16An],r0l */
25223   {
25224     M32C_INSN_MOVHH16_SRC_R0L_DST16_AN_INDIRECT_QI, "movhh16.src-r0l-dst16-An-indirect-QI", "movhh", 16,
25225     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25226   },
25227 /* movhh ${Dsp-16-u8}[$Dst16An],r0l */
25228   {
25229     M32C_INSN_MOVHH16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, "movhh16.src-r0l-dst16-16-8-An-relative-QI", "movhh", 24,
25230     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25231   },
25232 /* movhh ${Dsp-16-u16}[$Dst16An],r0l */
25233   {
25234     M32C_INSN_MOVHH16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, "movhh16.src-r0l-dst16-16-16-An-relative-QI", "movhh", 32,
25235     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25236   },
25237 /* movhh ${Dsp-16-u8}[sb],r0l */
25238   {
25239     M32C_INSN_MOVHH16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, "movhh16.src-r0l-dst16-16-8-SB-relative-QI", "movhh", 24,
25240     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25241   },
25242 /* movhh ${Dsp-16-u16}[sb],r0l */
25243   {
25244     M32C_INSN_MOVHH16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, "movhh16.src-r0l-dst16-16-16-SB-relative-QI", "movhh", 32,
25245     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25246   },
25247 /* movhh ${Dsp-16-s8}[fb],r0l */
25248   {
25249     M32C_INSN_MOVHH16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, "movhh16.src-r0l-dst16-16-8-FB-relative-QI", "movhh", 24,
25250     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25251   },
25252 /* movhh ${Dsp-16-u16},r0l */
25253   {
25254     M32C_INSN_MOVHH16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, "movhh16.src-r0l-dst16-16-16-absolute-QI", "movhh", 32,
25255     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25256   },
25257 /* movhl $Dst16RnQI,r0l */
25258   {
25259     M32C_INSN_MOVHL16_SRC_R0L_DST16_RN_DIRECT_QI, "movhl16.src-r0l-dst16-Rn-direct-QI", "movhl", 16,
25260     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25261   },
25262 /* movhl $Dst16AnQI,r0l */
25263   {
25264     M32C_INSN_MOVHL16_SRC_R0L_DST16_AN_DIRECT_QI, "movhl16.src-r0l-dst16-An-direct-QI", "movhl", 16,
25265     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25266   },
25267 /* movhl [$Dst16An],r0l */
25268   {
25269     M32C_INSN_MOVHL16_SRC_R0L_DST16_AN_INDIRECT_QI, "movhl16.src-r0l-dst16-An-indirect-QI", "movhl", 16,
25270     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25271   },
25272 /* movhl ${Dsp-16-u8}[$Dst16An],r0l */
25273   {
25274     M32C_INSN_MOVHL16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, "movhl16.src-r0l-dst16-16-8-An-relative-QI", "movhl", 24,
25275     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25276   },
25277 /* movhl ${Dsp-16-u16}[$Dst16An],r0l */
25278   {
25279     M32C_INSN_MOVHL16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, "movhl16.src-r0l-dst16-16-16-An-relative-QI", "movhl", 32,
25280     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25281   },
25282 /* movhl ${Dsp-16-u8}[sb],r0l */
25283   {
25284     M32C_INSN_MOVHL16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, "movhl16.src-r0l-dst16-16-8-SB-relative-QI", "movhl", 24,
25285     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25286   },
25287 /* movhl ${Dsp-16-u16}[sb],r0l */
25288   {
25289     M32C_INSN_MOVHL16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, "movhl16.src-r0l-dst16-16-16-SB-relative-QI", "movhl", 32,
25290     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25291   },
25292 /* movhl ${Dsp-16-s8}[fb],r0l */
25293   {
25294     M32C_INSN_MOVHL16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, "movhl16.src-r0l-dst16-16-8-FB-relative-QI", "movhl", 24,
25295     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25296   },
25297 /* movhl ${Dsp-16-u16},r0l */
25298   {
25299     M32C_INSN_MOVHL16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, "movhl16.src-r0l-dst16-16-16-absolute-QI", "movhl", 32,
25300     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25301   },
25302 /* movlh $Dst16RnQI,r0l */
25303   {
25304     M32C_INSN_MOVLH16_SRC_R0L_DST16_RN_DIRECT_QI, "movlh16.src-r0l-dst16-Rn-direct-QI", "movlh", 16,
25305     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25306   },
25307 /* movlh $Dst16AnQI,r0l */
25308   {
25309     M32C_INSN_MOVLH16_SRC_R0L_DST16_AN_DIRECT_QI, "movlh16.src-r0l-dst16-An-direct-QI", "movlh", 16,
25310     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25311   },
25312 /* movlh [$Dst16An],r0l */
25313   {
25314     M32C_INSN_MOVLH16_SRC_R0L_DST16_AN_INDIRECT_QI, "movlh16.src-r0l-dst16-An-indirect-QI", "movlh", 16,
25315     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25316   },
25317 /* movlh ${Dsp-16-u8}[$Dst16An],r0l */
25318   {
25319     M32C_INSN_MOVLH16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, "movlh16.src-r0l-dst16-16-8-An-relative-QI", "movlh", 24,
25320     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25321   },
25322 /* movlh ${Dsp-16-u16}[$Dst16An],r0l */
25323   {
25324     M32C_INSN_MOVLH16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, "movlh16.src-r0l-dst16-16-16-An-relative-QI", "movlh", 32,
25325     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25326   },
25327 /* movlh ${Dsp-16-u8}[sb],r0l */
25328   {
25329     M32C_INSN_MOVLH16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, "movlh16.src-r0l-dst16-16-8-SB-relative-QI", "movlh", 24,
25330     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25331   },
25332 /* movlh ${Dsp-16-u16}[sb],r0l */
25333   {
25334     M32C_INSN_MOVLH16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, "movlh16.src-r0l-dst16-16-16-SB-relative-QI", "movlh", 32,
25335     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25336   },
25337 /* movlh ${Dsp-16-s8}[fb],r0l */
25338   {
25339     M32C_INSN_MOVLH16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, "movlh16.src-r0l-dst16-16-8-FB-relative-QI", "movlh", 24,
25340     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25341   },
25342 /* movlh ${Dsp-16-u16},r0l */
25343   {
25344     M32C_INSN_MOVLH16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, "movlh16.src-r0l-dst16-16-16-absolute-QI", "movlh", 32,
25345     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25346   },
25347 /* movll $Dst16RnQI,r0l */
25348   {
25349     M32C_INSN_MOVLL16_SRC_R0L_DST16_RN_DIRECT_QI, "movll16.src-r0l-dst16-Rn-direct-QI", "movll", 16,
25350     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25351   },
25352 /* movll $Dst16AnQI,r0l */
25353   {
25354     M32C_INSN_MOVLL16_SRC_R0L_DST16_AN_DIRECT_QI, "movll16.src-r0l-dst16-An-direct-QI", "movll", 16,
25355     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25356   },
25357 /* movll [$Dst16An],r0l */
25358   {
25359     M32C_INSN_MOVLL16_SRC_R0L_DST16_AN_INDIRECT_QI, "movll16.src-r0l-dst16-An-indirect-QI", "movll", 16,
25360     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25361   },
25362 /* movll ${Dsp-16-u8}[$Dst16An],r0l */
25363   {
25364     M32C_INSN_MOVLL16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, "movll16.src-r0l-dst16-16-8-An-relative-QI", "movll", 24,
25365     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25366   },
25367 /* movll ${Dsp-16-u16}[$Dst16An],r0l */
25368   {
25369     M32C_INSN_MOVLL16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, "movll16.src-r0l-dst16-16-16-An-relative-QI", "movll", 32,
25370     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25371   },
25372 /* movll ${Dsp-16-u8}[sb],r0l */
25373   {
25374     M32C_INSN_MOVLL16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, "movll16.src-r0l-dst16-16-8-SB-relative-QI", "movll", 24,
25375     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25376   },
25377 /* movll ${Dsp-16-u16}[sb],r0l */
25378   {
25379     M32C_INSN_MOVLL16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, "movll16.src-r0l-dst16-16-16-SB-relative-QI", "movll", 32,
25380     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25381   },
25382 /* movll ${Dsp-16-s8}[fb],r0l */
25383   {
25384     M32C_INSN_MOVLL16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, "movll16.src-r0l-dst16-16-8-FB-relative-QI", "movll", 24,
25385     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25386   },
25387 /* movll ${Dsp-16-u16},r0l */
25388   {
25389     M32C_INSN_MOVLL16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, "movll16.src-r0l-dst16-16-16-absolute-QI", "movll", 32,
25390     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25391   },
25392 /* movhh r0l,$Dst16RnQI */
25393   {
25394     M32C_INSN_MOVHH16_R0L_DST_DST16_RN_DIRECT_QI, "movhh16.r0l-dst-dst16-Rn-direct-QI", "movhh", 16,
25395     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25396   },
25397 /* movhh r0l,$Dst16AnQI */
25398   {
25399     M32C_INSN_MOVHH16_R0L_DST_DST16_AN_DIRECT_QI, "movhh16.r0l-dst-dst16-An-direct-QI", "movhh", 16,
25400     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25401   },
25402 /* movhh r0l,[$Dst16An] */
25403   {
25404     M32C_INSN_MOVHH16_R0L_DST_DST16_AN_INDIRECT_QI, "movhh16.r0l-dst-dst16-An-indirect-QI", "movhh", 16,
25405     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25406   },
25407 /* movhh r0l,${Dsp-16-u8}[$Dst16An] */
25408   {
25409     M32C_INSN_MOVHH16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-8-An-relative-QI", "movhh", 24,
25410     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25411   },
25412 /* movhh r0l,${Dsp-16-u16}[$Dst16An] */
25413   {
25414     M32C_INSN_MOVHH16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-16-An-relative-QI", "movhh", 32,
25415     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25416   },
25417 /* movhh r0l,${Dsp-16-u8}[sb] */
25418   {
25419     M32C_INSN_MOVHH16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-8-SB-relative-QI", "movhh", 24,
25420     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25421   },
25422 /* movhh r0l,${Dsp-16-u16}[sb] */
25423   {
25424     M32C_INSN_MOVHH16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-16-SB-relative-QI", "movhh", 32,
25425     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25426   },
25427 /* movhh r0l,${Dsp-16-s8}[fb] */
25428   {
25429     M32C_INSN_MOVHH16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-8-FB-relative-QI", "movhh", 24,
25430     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25431   },
25432 /* movhh r0l,${Dsp-16-u16} */
25433   {
25434     M32C_INSN_MOVHH16_R0L_DST_DST16_16_16_ABSOLUTE_QI, "movhh16.r0l-dst-dst16-16-16-absolute-QI", "movhh", 32,
25435     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25436   },
25437 /* movhl r0l,$Dst16RnQI */
25438   {
25439     M32C_INSN_MOVHL16_R0L_DST_DST16_RN_DIRECT_QI, "movhl16.r0l-dst-dst16-Rn-direct-QI", "movhl", 16,
25440     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25441   },
25442 /* movhl r0l,$Dst16AnQI */
25443   {
25444     M32C_INSN_MOVHL16_R0L_DST_DST16_AN_DIRECT_QI, "movhl16.r0l-dst-dst16-An-direct-QI", "movhl", 16,
25445     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25446   },
25447 /* movhl r0l,[$Dst16An] */
25448   {
25449     M32C_INSN_MOVHL16_R0L_DST_DST16_AN_INDIRECT_QI, "movhl16.r0l-dst-dst16-An-indirect-QI", "movhl", 16,
25450     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25451   },
25452 /* movhl r0l,${Dsp-16-u8}[$Dst16An] */
25453   {
25454     M32C_INSN_MOVHL16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-8-An-relative-QI", "movhl", 24,
25455     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25456   },
25457 /* movhl r0l,${Dsp-16-u16}[$Dst16An] */
25458   {
25459     M32C_INSN_MOVHL16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-16-An-relative-QI", "movhl", 32,
25460     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25461   },
25462 /* movhl r0l,${Dsp-16-u8}[sb] */
25463   {
25464     M32C_INSN_MOVHL16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-8-SB-relative-QI", "movhl", 24,
25465     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25466   },
25467 /* movhl r0l,${Dsp-16-u16}[sb] */
25468   {
25469     M32C_INSN_MOVHL16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-16-SB-relative-QI", "movhl", 32,
25470     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25471   },
25472 /* movhl r0l,${Dsp-16-s8}[fb] */
25473   {
25474     M32C_INSN_MOVHL16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-8-FB-relative-QI", "movhl", 24,
25475     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25476   },
25477 /* movhl r0l,${Dsp-16-u16} */
25478   {
25479     M32C_INSN_MOVHL16_R0L_DST_DST16_16_16_ABSOLUTE_QI, "movhl16.r0l-dst-dst16-16-16-absolute-QI", "movhl", 32,
25480     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25481   },
25482 /* movlh r0l,$Dst16RnQI */
25483   {
25484     M32C_INSN_MOVLH16_R0L_DST_DST16_RN_DIRECT_QI, "movlh16.r0l-dst-dst16-Rn-direct-QI", "movlh", 16,
25485     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25486   },
25487 /* movlh r0l,$Dst16AnQI */
25488   {
25489     M32C_INSN_MOVLH16_R0L_DST_DST16_AN_DIRECT_QI, "movlh16.r0l-dst-dst16-An-direct-QI", "movlh", 16,
25490     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25491   },
25492 /* movlh r0l,[$Dst16An] */
25493   {
25494     M32C_INSN_MOVLH16_R0L_DST_DST16_AN_INDIRECT_QI, "movlh16.r0l-dst-dst16-An-indirect-QI", "movlh", 16,
25495     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25496   },
25497 /* movlh r0l,${Dsp-16-u8}[$Dst16An] */
25498   {
25499     M32C_INSN_MOVLH16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-8-An-relative-QI", "movlh", 24,
25500     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25501   },
25502 /* movlh r0l,${Dsp-16-u16}[$Dst16An] */
25503   {
25504     M32C_INSN_MOVLH16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-16-An-relative-QI", "movlh", 32,
25505     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25506   },
25507 /* movlh r0l,${Dsp-16-u8}[sb] */
25508   {
25509     M32C_INSN_MOVLH16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-8-SB-relative-QI", "movlh", 24,
25510     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25511   },
25512 /* movlh r0l,${Dsp-16-u16}[sb] */
25513   {
25514     M32C_INSN_MOVLH16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-16-SB-relative-QI", "movlh", 32,
25515     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25516   },
25517 /* movlh r0l,${Dsp-16-s8}[fb] */
25518   {
25519     M32C_INSN_MOVLH16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-8-FB-relative-QI", "movlh", 24,
25520     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25521   },
25522 /* movlh r0l,${Dsp-16-u16} */
25523   {
25524     M32C_INSN_MOVLH16_R0L_DST_DST16_16_16_ABSOLUTE_QI, "movlh16.r0l-dst-dst16-16-16-absolute-QI", "movlh", 32,
25525     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25526   },
25527 /* movll r0l,$Dst16RnQI */
25528   {
25529     M32C_INSN_MOVLL16_R0L_DST_DST16_RN_DIRECT_QI, "movll16.r0l-dst-dst16-Rn-direct-QI", "movll", 16,
25530     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25531   },
25532 /* movll r0l,$Dst16AnQI */
25533   {
25534     M32C_INSN_MOVLL16_R0L_DST_DST16_AN_DIRECT_QI, "movll16.r0l-dst-dst16-An-direct-QI", "movll", 16,
25535     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25536   },
25537 /* movll r0l,[$Dst16An] */
25538   {
25539     M32C_INSN_MOVLL16_R0L_DST_DST16_AN_INDIRECT_QI, "movll16.r0l-dst-dst16-An-indirect-QI", "movll", 16,
25540     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25541   },
25542 /* movll r0l,${Dsp-16-u8}[$Dst16An] */
25543   {
25544     M32C_INSN_MOVLL16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, "movll16.r0l-dst-dst16-16-8-An-relative-QI", "movll", 24,
25545     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25546   },
25547 /* movll r0l,${Dsp-16-u16}[$Dst16An] */
25548   {
25549     M32C_INSN_MOVLL16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, "movll16.r0l-dst-dst16-16-16-An-relative-QI", "movll", 32,
25550     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25551   },
25552 /* movll r0l,${Dsp-16-u8}[sb] */
25553   {
25554     M32C_INSN_MOVLL16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, "movll16.r0l-dst-dst16-16-8-SB-relative-QI", "movll", 24,
25555     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25556   },
25557 /* movll r0l,${Dsp-16-u16}[sb] */
25558   {
25559     M32C_INSN_MOVLL16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, "movll16.r0l-dst-dst16-16-16-SB-relative-QI", "movll", 32,
25560     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25561   },
25562 /* movll r0l,${Dsp-16-s8}[fb] */
25563   {
25564     M32C_INSN_MOVLL16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, "movll16.r0l-dst-dst16-16-8-FB-relative-QI", "movll", 24,
25565     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25566   },
25567 /* movll r0l,${Dsp-16-u16} */
25568   {
25569     M32C_INSN_MOVLL16_R0L_DST_DST16_16_16_ABSOLUTE_QI, "movll16.r0l-dst-dst16-16-16-absolute-QI", "movll", 32,
25570     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25571   },
25572 /* mova [$Dst32AnUnprefixed],a1 */
25573   {
25574     M32C_INSN_MOVA32_SRC_A1_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-An-indirect-Unprefixed-Mova-SI", "mova", 16,
25575     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25576   },
25577 /* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],a1 */
25578   {
25579     M32C_INSN_MOVA32_SRC_A1_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-8-An-relative-Unprefixed-Mova-SI", "mova", 24,
25580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25581   },
25582 /* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],a1 */
25583   {
25584     M32C_INSN_MOVA32_SRC_A1_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-16-An-relative-Unprefixed-Mova-SI", "mova", 32,
25585     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25586   },
25587 /* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],a1 */
25588   {
25589     M32C_INSN_MOVA32_SRC_A1_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-24-An-relative-Unprefixed-Mova-SI", "mova", 40,
25590     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25591   },
25592 /* mova ${Dsp-16-u8}[sb],a1 */
25593   {
25594     M32C_INSN_MOVA32_SRC_A1_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "mova", 24,
25595     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25596   },
25597 /* mova ${Dsp-16-u16}[sb],a1 */
25598   {
25599     M32C_INSN_MOVA32_SRC_A1_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "mova", 32,
25600     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25601   },
25602 /* mova ${Dsp-16-s8}[fb],a1 */
25603   {
25604     M32C_INSN_MOVA32_SRC_A1_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "mova", 24,
25605     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25606   },
25607 /* mova ${Dsp-16-s16}[fb],a1 */
25608   {
25609     M32C_INSN_MOVA32_SRC_A1_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "mova", 32,
25610     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25611   },
25612 /* mova ${Dsp-16-u16},a1 */
25613   {
25614     M32C_INSN_MOVA32_SRC_A1_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-16-absolute-Unprefixed-Mova-SI", "mova", 32,
25615     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25616   },
25617 /* mova ${Dsp-16-u24},a1 */
25618   {
25619     M32C_INSN_MOVA32_SRC_A1_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-24-absolute-Unprefixed-Mova-SI", "mova", 40,
25620     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25621   },
25622 /* mova [$Dst32AnUnprefixed],a0 */
25623   {
25624     M32C_INSN_MOVA32_SRC_A0_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-An-indirect-Unprefixed-Mova-SI", "mova", 16,
25625     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25626   },
25627 /* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],a0 */
25628   {
25629     M32C_INSN_MOVA32_SRC_A0_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-8-An-relative-Unprefixed-Mova-SI", "mova", 24,
25630     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25631   },
25632 /* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],a0 */
25633   {
25634     M32C_INSN_MOVA32_SRC_A0_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-16-An-relative-Unprefixed-Mova-SI", "mova", 32,
25635     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25636   },
25637 /* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],a0 */
25638   {
25639     M32C_INSN_MOVA32_SRC_A0_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-24-An-relative-Unprefixed-Mova-SI", "mova", 40,
25640     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25641   },
25642 /* mova ${Dsp-16-u8}[sb],a0 */
25643   {
25644     M32C_INSN_MOVA32_SRC_A0_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "mova", 24,
25645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25646   },
25647 /* mova ${Dsp-16-u16}[sb],a0 */
25648   {
25649     M32C_INSN_MOVA32_SRC_A0_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "mova", 32,
25650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25651   },
25652 /* mova ${Dsp-16-s8}[fb],a0 */
25653   {
25654     M32C_INSN_MOVA32_SRC_A0_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "mova", 24,
25655     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25656   },
25657 /* mova ${Dsp-16-s16}[fb],a0 */
25658   {
25659     M32C_INSN_MOVA32_SRC_A0_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "mova", 32,
25660     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25661   },
25662 /* mova ${Dsp-16-u16},a0 */
25663   {
25664     M32C_INSN_MOVA32_SRC_A0_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-16-absolute-Unprefixed-Mova-SI", "mova", 32,
25665     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25666   },
25667 /* mova ${Dsp-16-u24},a0 */
25668   {
25669     M32C_INSN_MOVA32_SRC_A0_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-24-absolute-Unprefixed-Mova-SI", "mova", 40,
25670     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25671   },
25672 /* mova [$Dst32AnUnprefixed],r3r1 */
25673   {
25674     M32C_INSN_MOVA32_SRC_R3R1_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-An-indirect-Unprefixed-Mova-SI", "mova", 16,
25675     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25676   },
25677 /* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],r3r1 */
25678   {
25679     M32C_INSN_MOVA32_SRC_R3R1_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-8-An-relative-Unprefixed-Mova-SI", "mova", 24,
25680     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25681   },
25682 /* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],r3r1 */
25683   {
25684     M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-16-An-relative-Unprefixed-Mova-SI", "mova", 32,
25685     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25686   },
25687 /* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],r3r1 */
25688   {
25689     M32C_INSN_MOVA32_SRC_R3R1_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-24-An-relative-Unprefixed-Mova-SI", "mova", 40,
25690     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25691   },
25692 /* mova ${Dsp-16-u8}[sb],r3r1 */
25693   {
25694     M32C_INSN_MOVA32_SRC_R3R1_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "mova", 24,
25695     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25696   },
25697 /* mova ${Dsp-16-u16}[sb],r3r1 */
25698   {
25699     M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "mova", 32,
25700     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25701   },
25702 /* mova ${Dsp-16-s8}[fb],r3r1 */
25703   {
25704     M32C_INSN_MOVA32_SRC_R3R1_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "mova", 24,
25705     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25706   },
25707 /* mova ${Dsp-16-s16}[fb],r3r1 */
25708   {
25709     M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "mova", 32,
25710     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25711   },
25712 /* mova ${Dsp-16-u16},r3r1 */
25713   {
25714     M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-16-absolute-Unprefixed-Mova-SI", "mova", 32,
25715     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25716   },
25717 /* mova ${Dsp-16-u24},r3r1 */
25718   {
25719     M32C_INSN_MOVA32_SRC_R3R1_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-24-absolute-Unprefixed-Mova-SI", "mova", 40,
25720     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25721   },
25722 /* mova [$Dst32AnUnprefixed],r2r0 */
25723   {
25724     M32C_INSN_MOVA32_SRC_R2R0_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-An-indirect-Unprefixed-Mova-SI", "mova", 16,
25725     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25726   },
25727 /* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],r2r0 */
25728   {
25729     M32C_INSN_MOVA32_SRC_R2R0_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-8-An-relative-Unprefixed-Mova-SI", "mova", 24,
25730     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25731   },
25732 /* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],r2r0 */
25733   {
25734     M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-16-An-relative-Unprefixed-Mova-SI", "mova", 32,
25735     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25736   },
25737 /* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],r2r0 */
25738   {
25739     M32C_INSN_MOVA32_SRC_R2R0_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-24-An-relative-Unprefixed-Mova-SI", "mova", 40,
25740     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25741   },
25742 /* mova ${Dsp-16-u8}[sb],r2r0 */
25743   {
25744     M32C_INSN_MOVA32_SRC_R2R0_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "mova", 24,
25745     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25746   },
25747 /* mova ${Dsp-16-u16}[sb],r2r0 */
25748   {
25749     M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "mova", 32,
25750     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25751   },
25752 /* mova ${Dsp-16-s8}[fb],r2r0 */
25753   {
25754     M32C_INSN_MOVA32_SRC_R2R0_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "mova", 24,
25755     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25756   },
25757 /* mova ${Dsp-16-s16}[fb],r2r0 */
25758   {
25759     M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "mova", 32,
25760     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25761   },
25762 /* mova ${Dsp-16-u16},r2r0 */
25763   {
25764     M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-16-absolute-Unprefixed-Mova-SI", "mova", 32,
25765     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25766   },
25767 /* mova ${Dsp-16-u24},r2r0 */
25768   {
25769     M32C_INSN_MOVA32_SRC_R2R0_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-24-absolute-Unprefixed-Mova-SI", "mova", 40,
25770     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25771   },
25772 /* mova [$Dst16An],a1 */
25773   {
25774     M32C_INSN_MOVA16_SRC_A1_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-a1-dst16-An-indirect-Mova-HI", "mova", 16,
25775     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25776   },
25777 /* mova ${Dsp-16-u8}[$Dst16An],a1 */
25778   {
25779     M32C_INSN_MOVA16_SRC_A1_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-8-An-relative-Mova-HI", "mova", 24,
25780     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25781   },
25782 /* mova ${Dsp-16-u16}[$Dst16An],a1 */
25783   {
25784     M32C_INSN_MOVA16_SRC_A1_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-16-An-relative-Mova-HI", "mova", 32,
25785     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25786   },
25787 /* mova ${Dsp-16-u8}[sb],a1 */
25788   {
25789     M32C_INSN_MOVA16_SRC_A1_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-8-SB-relative-Mova-HI", "mova", 24,
25790     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25791   },
25792 /* mova ${Dsp-16-u16}[sb],a1 */
25793   {
25794     M32C_INSN_MOVA16_SRC_A1_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-16-SB-relative-Mova-HI", "mova", 32,
25795     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25796   },
25797 /* mova ${Dsp-16-s8}[fb],a1 */
25798   {
25799     M32C_INSN_MOVA16_SRC_A1_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-8-FB-relative-Mova-HI", "mova", 24,
25800     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25801   },
25802 /* mova ${Dsp-16-u16},a1 */
25803   {
25804     M32C_INSN_MOVA16_SRC_A1_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-a1-dst16-16-16-absolute-Mova-HI", "mova", 32,
25805     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25806   },
25807 /* mova [$Dst16An],a0 */
25808   {
25809     M32C_INSN_MOVA16_SRC_A0_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-a0-dst16-An-indirect-Mova-HI", "mova", 16,
25810     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25811   },
25812 /* mova ${Dsp-16-u8}[$Dst16An],a0 */
25813   {
25814     M32C_INSN_MOVA16_SRC_A0_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-8-An-relative-Mova-HI", "mova", 24,
25815     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25816   },
25817 /* mova ${Dsp-16-u16}[$Dst16An],a0 */
25818   {
25819     M32C_INSN_MOVA16_SRC_A0_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-16-An-relative-Mova-HI", "mova", 32,
25820     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25821   },
25822 /* mova ${Dsp-16-u8}[sb],a0 */
25823   {
25824     M32C_INSN_MOVA16_SRC_A0_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-8-SB-relative-Mova-HI", "mova", 24,
25825     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25826   },
25827 /* mova ${Dsp-16-u16}[sb],a0 */
25828   {
25829     M32C_INSN_MOVA16_SRC_A0_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-16-SB-relative-Mova-HI", "mova", 32,
25830     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25831   },
25832 /* mova ${Dsp-16-s8}[fb],a0 */
25833   {
25834     M32C_INSN_MOVA16_SRC_A0_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-8-FB-relative-Mova-HI", "mova", 24,
25835     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25836   },
25837 /* mova ${Dsp-16-u16},a0 */
25838   {
25839     M32C_INSN_MOVA16_SRC_A0_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-a0-dst16-16-16-absolute-Mova-HI", "mova", 32,
25840     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25841   },
25842 /* mova [$Dst16An],r3 */
25843   {
25844     M32C_INSN_MOVA16_SRC_R3_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-r3-dst16-An-indirect-Mova-HI", "mova", 16,
25845     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25846   },
25847 /* mova ${Dsp-16-u8}[$Dst16An],r3 */
25848   {
25849     M32C_INSN_MOVA16_SRC_R3_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-8-An-relative-Mova-HI", "mova", 24,
25850     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25851   },
25852 /* mova ${Dsp-16-u16}[$Dst16An],r3 */
25853   {
25854     M32C_INSN_MOVA16_SRC_R3_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-16-An-relative-Mova-HI", "mova", 32,
25855     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25856   },
25857 /* mova ${Dsp-16-u8}[sb],r3 */
25858   {
25859     M32C_INSN_MOVA16_SRC_R3_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-8-SB-relative-Mova-HI", "mova", 24,
25860     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25861   },
25862 /* mova ${Dsp-16-u16}[sb],r3 */
25863   {
25864     M32C_INSN_MOVA16_SRC_R3_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-16-SB-relative-Mova-HI", "mova", 32,
25865     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25866   },
25867 /* mova ${Dsp-16-s8}[fb],r3 */
25868   {
25869     M32C_INSN_MOVA16_SRC_R3_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-8-FB-relative-Mova-HI", "mova", 24,
25870     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25871   },
25872 /* mova ${Dsp-16-u16},r3 */
25873   {
25874     M32C_INSN_MOVA16_SRC_R3_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-r3-dst16-16-16-absolute-Mova-HI", "mova", 32,
25875     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25876   },
25877 /* mova [$Dst16An],r2 */
25878   {
25879     M32C_INSN_MOVA16_SRC_R2_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-r2-dst16-An-indirect-Mova-HI", "mova", 16,
25880     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25881   },
25882 /* mova ${Dsp-16-u8}[$Dst16An],r2 */
25883   {
25884     M32C_INSN_MOVA16_SRC_R2_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-8-An-relative-Mova-HI", "mova", 24,
25885     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25886   },
25887 /* mova ${Dsp-16-u16}[$Dst16An],r2 */
25888   {
25889     M32C_INSN_MOVA16_SRC_R2_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-16-An-relative-Mova-HI", "mova", 32,
25890     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25891   },
25892 /* mova ${Dsp-16-u8}[sb],r2 */
25893   {
25894     M32C_INSN_MOVA16_SRC_R2_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-8-SB-relative-Mova-HI", "mova", 24,
25895     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25896   },
25897 /* mova ${Dsp-16-u16}[sb],r2 */
25898   {
25899     M32C_INSN_MOVA16_SRC_R2_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-16-SB-relative-Mova-HI", "mova", 32,
25900     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25901   },
25902 /* mova ${Dsp-16-s8}[fb],r2 */
25903   {
25904     M32C_INSN_MOVA16_SRC_R2_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-8-FB-relative-Mova-HI", "mova", 24,
25905     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25906   },
25907 /* mova ${Dsp-16-u16},r2 */
25908   {
25909     M32C_INSN_MOVA16_SRC_R2_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-r2-dst16-16-16-absolute-Mova-HI", "mova", 32,
25910     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25911   },
25912 /* mova [$Dst16An],r1 */
25913   {
25914     M32C_INSN_MOVA16_SRC_R1_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-r1-dst16-An-indirect-Mova-HI", "mova", 16,
25915     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25916   },
25917 /* mova ${Dsp-16-u8}[$Dst16An],r1 */
25918   {
25919     M32C_INSN_MOVA16_SRC_R1_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-8-An-relative-Mova-HI", "mova", 24,
25920     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25921   },
25922 /* mova ${Dsp-16-u16}[$Dst16An],r1 */
25923   {
25924     M32C_INSN_MOVA16_SRC_R1_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-16-An-relative-Mova-HI", "mova", 32,
25925     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25926   },
25927 /* mova ${Dsp-16-u8}[sb],r1 */
25928   {
25929     M32C_INSN_MOVA16_SRC_R1_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-8-SB-relative-Mova-HI", "mova", 24,
25930     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25931   },
25932 /* mova ${Dsp-16-u16}[sb],r1 */
25933   {
25934     M32C_INSN_MOVA16_SRC_R1_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-16-SB-relative-Mova-HI", "mova", 32,
25935     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25936   },
25937 /* mova ${Dsp-16-s8}[fb],r1 */
25938   {
25939     M32C_INSN_MOVA16_SRC_R1_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-8-FB-relative-Mova-HI", "mova", 24,
25940     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25941   },
25942 /* mova ${Dsp-16-u16},r1 */
25943   {
25944     M32C_INSN_MOVA16_SRC_R1_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-r1-dst16-16-16-absolute-Mova-HI", "mova", 32,
25945     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25946   },
25947 /* mova [$Dst16An],r0 */
25948   {
25949     M32C_INSN_MOVA16_SRC_R0_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-r0-dst16-An-indirect-Mova-HI", "mova", 16,
25950     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25951   },
25952 /* mova ${Dsp-16-u8}[$Dst16An],r0 */
25953   {
25954     M32C_INSN_MOVA16_SRC_R0_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-8-An-relative-Mova-HI", "mova", 24,
25955     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25956   },
25957 /* mova ${Dsp-16-u16}[$Dst16An],r0 */
25958   {
25959     M32C_INSN_MOVA16_SRC_R0_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-16-An-relative-Mova-HI", "mova", 32,
25960     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25961   },
25962 /* mova ${Dsp-16-u8}[sb],r0 */
25963   {
25964     M32C_INSN_MOVA16_SRC_R0_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-8-SB-relative-Mova-HI", "mova", 24,
25965     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25966   },
25967 /* mova ${Dsp-16-u16}[sb],r0 */
25968   {
25969     M32C_INSN_MOVA16_SRC_R0_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-16-SB-relative-Mova-HI", "mova", 32,
25970     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25971   },
25972 /* mova ${Dsp-16-s8}[fb],r0 */
25973   {
25974     M32C_INSN_MOVA16_SRC_R0_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-8-FB-relative-Mova-HI", "mova", 24,
25975     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25976   },
25977 /* mova ${Dsp-16-u16},r0 */
25978   {
25979     M32C_INSN_MOVA16_SRC_R0_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-r0-dst16-16-16-absolute-Mova-HI", "mova", 32,
25980     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25981   },
25982 /* mov.w ${Dsp-16-u8}[$Dst32AnUnprefixed],${Dsp-24-u8}[sp] */
25983   {
25984     M32C_INSN_MOV32_W_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 32,
25985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25986   },
25987 /* mov.w ${Dsp-16-u8}[sb],${Dsp-24-u8}[sp] */
25988   {
25989     M32C_INSN_MOV32_W_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 32,
25990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25991   },
25992 /* mov.w ${Dsp-16-s8}[fb],${Dsp-24-u8}[sp] */
25993   {
25994     M32C_INSN_MOV32_W_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 32,
25995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25996   },
25997 /* mov.w ${Dsp-16-u16}[$Dst32AnUnprefixed],${Dsp-32-u8}[sp] */
25998   {
25999     M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 40,
26000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26001   },
26002 /* mov.w ${Dsp-16-u16}[sb],${Dsp-32-u8}[sp] */
26003   {
26004     M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 40,
26005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26006   },
26007 /* mov.w ${Dsp-16-s16}[fb],${Dsp-32-u8}[sp] */
26008   {
26009     M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 40,
26010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26011   },
26012 /* mov.w ${Dsp-16-u16},${Dsp-32-u8}[sp] */
26013   {
26014     M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 40,
26015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26016   },
26017 /* mov.w ${Dsp-16-u24}[$Dst32AnUnprefixed],${Dsp-40-u8}[sp] */
26018   {
26019     M32C_INSN_MOV32_W_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 48,
26020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26021   },
26022 /* mov.w ${Dsp-16-u24},${Dsp-40-u8}[sp] */
26023   {
26024     M32C_INSN_MOV32_W_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 48,
26025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26026   },
26027 /* mov.w $Dst32RnUnprefixedHI,${Dsp-16-u8}[sp] */
26028   {
26029     M32C_INSN_MOV32_W_DST_DSPSP_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-dst-dspsp-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24,
26030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26031   },
26032 /* mov.w $Dst32AnUnprefixedHI,${Dsp-16-u8}[sp] */
26033   {
26034     M32C_INSN_MOV32_W_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-dst-dspsp-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mov.w", 24,
26035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26036   },
26037 /* mov.w [$Dst32AnUnprefixed],${Dsp-16-u8}[sp] */
26038   {
26039     M32C_INSN_MOV32_W_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-dst-dspsp-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mov.w", 24,
26040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26041   },
26042 /* mov.b ${Dsp-16-u8}[$Dst32AnUnprefixed],${Dsp-24-u8}[sp] */
26043   {
26044     M32C_INSN_MOV32_B_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 32,
26045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26046   },
26047 /* mov.b ${Dsp-16-u8}[sb],${Dsp-24-u8}[sp] */
26048   {
26049     M32C_INSN_MOV32_B_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 32,
26050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26051   },
26052 /* mov.b ${Dsp-16-s8}[fb],${Dsp-24-u8}[sp] */
26053   {
26054     M32C_INSN_MOV32_B_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 32,
26055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26056   },
26057 /* mov.b ${Dsp-16-u16}[$Dst32AnUnprefixed],${Dsp-32-u8}[sp] */
26058   {
26059     M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 40,
26060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26061   },
26062 /* mov.b ${Dsp-16-u16}[sb],${Dsp-32-u8}[sp] */
26063   {
26064     M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 40,
26065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26066   },
26067 /* mov.b ${Dsp-16-s16}[fb],${Dsp-32-u8}[sp] */
26068   {
26069     M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 40,
26070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26071   },
26072 /* mov.b ${Dsp-16-u16},${Dsp-32-u8}[sp] */
26073   {
26074     M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 40,
26075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26076   },
26077 /* mov.b ${Dsp-16-u24}[$Dst32AnUnprefixed],${Dsp-40-u8}[sp] */
26078   {
26079     M32C_INSN_MOV32_B_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 48,
26080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26081   },
26082 /* mov.b ${Dsp-16-u24},${Dsp-40-u8}[sp] */
26083   {
26084     M32C_INSN_MOV32_B_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 48,
26085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26086   },
26087 /* mov.b $Dst32RnUnprefixedQI,${Dsp-16-u8}[sp] */
26088   {
26089     M32C_INSN_MOV32_B_DST_DSPSP_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-dst-dspsp-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24,
26090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26091   },
26092 /* mov.b $Dst32AnUnprefixedQI,${Dsp-16-u8}[sp] */
26093   {
26094     M32C_INSN_MOV32_B_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-dst-dspsp-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mov.b", 24,
26095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26096   },
26097 /* mov.b [$Dst32AnUnprefixed],${Dsp-16-u8}[sp] */
26098   {
26099     M32C_INSN_MOV32_B_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-dst-dspsp-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mov.b", 24,
26100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26101   },
26102 /* mov.w ${Dsp-16-u8}[$Dst16An],${Dsp-24-u8}[sp] */
26103   {
26104     M32C_INSN_MOV16_W_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_HI, "mov16.w-dst-dspsp-16-8-dst16-16-8-An-relative-HI", "mov.w", 32,
26105     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26106   },
26107 /* mov.w ${Dsp-16-u8}[sb],${Dsp-24-u8}[sp] */
26108   {
26109     M32C_INSN_MOV16_W_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_HI, "mov16.w-dst-dspsp-16-8-dst16-16-8-SB-relative-HI", "mov.w", 32,
26110     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26111   },
26112 /* mov.w ${Dsp-16-s8}[fb],${Dsp-24-u8}[sp] */
26113   {
26114     M32C_INSN_MOV16_W_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_HI, "mov16.w-dst-dspsp-16-8-dst16-16-8-FB-relative-HI", "mov.w", 32,
26115     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26116   },
26117 /* mov.w ${Dsp-16-u16}[$Dst16An],${Dsp-32-u8}[sp] */
26118   {
26119     M32C_INSN_MOV16_W_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_HI, "mov16.w-dst-dspsp-16-16-dst16-16-16-An-relative-HI", "mov.w", 40,
26120     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26121   },
26122 /* mov.w ${Dsp-16-u16}[sb],${Dsp-32-u8}[sp] */
26123   {
26124     M32C_INSN_MOV16_W_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_HI, "mov16.w-dst-dspsp-16-16-dst16-16-16-SB-relative-HI", "mov.w", 40,
26125     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26126   },
26127 /* mov.w ${Dsp-16-u16},${Dsp-32-u8}[sp] */
26128   {
26129     M32C_INSN_MOV16_W_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_HI, "mov16.w-dst-dspsp-16-16-dst16-16-16-absolute-HI", "mov.w", 40,
26130     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26131   },
26132 /* mov.w $Dst16RnHI,${Dsp-16-u8}[sp] */
26133   {
26134     M32C_INSN_MOV16_W_DST_DSPSP_BASIC_DST16_RN_DIRECT_HI, "mov16.w-dst-dspsp-basic-dst16-Rn-direct-HI", "mov.w", 24,
26135     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26136   },
26137 /* mov.w $Dst16AnHI,${Dsp-16-u8}[sp] */
26138   {
26139     M32C_INSN_MOV16_W_DST_DSPSP_BASIC_DST16_AN_DIRECT_HI, "mov16.w-dst-dspsp-basic-dst16-An-direct-HI", "mov.w", 24,
26140     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26141   },
26142 /* mov.w [$Dst16An],${Dsp-16-u8}[sp] */
26143   {
26144     M32C_INSN_MOV16_W_DST_DSPSP_BASIC_DST16_AN_INDIRECT_HI, "mov16.w-dst-dspsp-basic-dst16-An-indirect-HI", "mov.w", 24,
26145     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26146   },
26147 /* mov.b ${Dsp-16-u8}[$Dst16An],${Dsp-24-u8}[sp] */
26148   {
26149     M32C_INSN_MOV16_B_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_QI, "mov16.b-dst-dspsp-16-8-dst16-16-8-An-relative-QI", "mov.b", 32,
26150     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26151   },
26152 /* mov.b ${Dsp-16-u8}[sb],${Dsp-24-u8}[sp] */
26153   {
26154     M32C_INSN_MOV16_B_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_QI, "mov16.b-dst-dspsp-16-8-dst16-16-8-SB-relative-QI", "mov.b", 32,
26155     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26156   },
26157 /* mov.b ${Dsp-16-s8}[fb],${Dsp-24-u8}[sp] */
26158   {
26159     M32C_INSN_MOV16_B_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_QI, "mov16.b-dst-dspsp-16-8-dst16-16-8-FB-relative-QI", "mov.b", 32,
26160     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26161   },
26162 /* mov.b ${Dsp-16-u16}[$Dst16An],${Dsp-32-u8}[sp] */
26163   {
26164     M32C_INSN_MOV16_B_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_QI, "mov16.b-dst-dspsp-16-16-dst16-16-16-An-relative-QI", "mov.b", 40,
26165     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26166   },
26167 /* mov.b ${Dsp-16-u16}[sb],${Dsp-32-u8}[sp] */
26168   {
26169     M32C_INSN_MOV16_B_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_QI, "mov16.b-dst-dspsp-16-16-dst16-16-16-SB-relative-QI", "mov.b", 40,
26170     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26171   },
26172 /* mov.b ${Dsp-16-u16},${Dsp-32-u8}[sp] */
26173   {
26174     M32C_INSN_MOV16_B_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_QI, "mov16.b-dst-dspsp-16-16-dst16-16-16-absolute-QI", "mov.b", 40,
26175     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26176   },
26177 /* mov.b $Dst16RnQI,${Dsp-16-u8}[sp] */
26178   {
26179     M32C_INSN_MOV16_B_DST_DSPSP_BASIC_DST16_RN_DIRECT_QI, "mov16.b-dst-dspsp-basic-dst16-Rn-direct-QI", "mov.b", 24,
26180     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26181   },
26182 /* mov.b $Dst16AnQI,${Dsp-16-u8}[sp] */
26183   {
26184     M32C_INSN_MOV16_B_DST_DSPSP_BASIC_DST16_AN_DIRECT_QI, "mov16.b-dst-dspsp-basic-dst16-An-direct-QI", "mov.b", 24,
26185     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26186   },
26187 /* mov.b [$Dst16An],${Dsp-16-u8}[sp] */
26188   {
26189     M32C_INSN_MOV16_B_DST_DSPSP_BASIC_DST16_AN_INDIRECT_QI, "mov16.b-dst-dspsp-basic-dst16-An-indirect-QI", "mov.b", 24,
26190     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26191   },
26192 /* mov.w ${Dsp-24-u8}[sp],${Dsp-16-u8}[$Dst32AnUnprefixed] */
26193   {
26194     M32C_INSN_MOV32_W_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 32,
26195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26196   },
26197 /* mov.w ${Dsp-24-u8}[sp],${Dsp-16-u8}[sb] */
26198   {
26199     M32C_INSN_MOV32_W_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 32,
26200     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26201   },
26202 /* mov.w ${Dsp-24-u8}[sp],${Dsp-16-s8}[fb] */
26203   {
26204     M32C_INSN_MOV32_W_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 32,
26205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26206   },
26207 /* mov.w ${Dsp-32-u8}[sp],${Dsp-16-u16}[$Dst32AnUnprefixed] */
26208   {
26209     M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 40,
26210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26211   },
26212 /* mov.w ${Dsp-32-u8}[sp],${Dsp-16-u16}[sb] */
26213   {
26214     M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 40,
26215     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26216   },
26217 /* mov.w ${Dsp-32-u8}[sp],${Dsp-16-s16}[fb] */
26218   {
26219     M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 40,
26220     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26221   },
26222 /* mov.w ${Dsp-32-u8}[sp],${Dsp-16-u16} */
26223   {
26224     M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 40,
26225     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26226   },
26227 /* mov.w ${Dsp-40-u8}[sp],${Dsp-16-u24}[$Dst32AnUnprefixed] */
26228   {
26229     M32C_INSN_MOV32_W_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 48,
26230     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26231   },
26232 /* mov.w ${Dsp-40-u8}[sp],${Dsp-16-u24} */
26233   {
26234     M32C_INSN_MOV32_W_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 48,
26235     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26236   },
26237 /* mov.w ${Dsp-16-u8}[sp],$Dst32RnUnprefixedHI */
26238   {
26239     M32C_INSN_MOV32_W_DSPSP_DST_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-dspsp-dst-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24,
26240     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26241   },
26242 /* mov.w ${Dsp-16-u8}[sp],$Dst32AnUnprefixedHI */
26243   {
26244     M32C_INSN_MOV32_W_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-dspsp-dst-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mov.w", 24,
26245     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26246   },
26247 /* mov.w ${Dsp-16-u8}[sp],[$Dst32AnUnprefixed] */
26248   {
26249     M32C_INSN_MOV32_W_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-dspsp-dst-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mov.w", 24,
26250     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26251   },
26252 /* mov.b ${Dsp-24-u8}[sp],${Dsp-16-u8}[$Dst32AnUnprefixed] */
26253   {
26254     M32C_INSN_MOV32_B_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 32,
26255     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26256   },
26257 /* mov.b ${Dsp-24-u8}[sp],${Dsp-16-u8}[sb] */
26258   {
26259     M32C_INSN_MOV32_B_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 32,
26260     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26261   },
26262 /* mov.b ${Dsp-24-u8}[sp],${Dsp-16-s8}[fb] */
26263   {
26264     M32C_INSN_MOV32_B_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 32,
26265     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26266   },
26267 /* mov.b ${Dsp-32-u8}[sp],${Dsp-16-u16}[$Dst32AnUnprefixed] */
26268   {
26269     M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 40,
26270     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26271   },
26272 /* mov.b ${Dsp-32-u8}[sp],${Dsp-16-u16}[sb] */
26273   {
26274     M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 40,
26275     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26276   },
26277 /* mov.b ${Dsp-32-u8}[sp],${Dsp-16-s16}[fb] */
26278   {
26279     M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 40,
26280     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26281   },
26282 /* mov.b ${Dsp-32-u8}[sp],${Dsp-16-u16} */
26283   {
26284     M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 40,
26285     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26286   },
26287 /* mov.b ${Dsp-40-u8}[sp],${Dsp-16-u24}[$Dst32AnUnprefixed] */
26288   {
26289     M32C_INSN_MOV32_B_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 48,
26290     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26291   },
26292 /* mov.b ${Dsp-40-u8}[sp],${Dsp-16-u24} */
26293   {
26294     M32C_INSN_MOV32_B_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 48,
26295     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26296   },
26297 /* mov.b ${Dsp-16-u8}[sp],$Dst32RnUnprefixedQI */
26298   {
26299     M32C_INSN_MOV32_B_DSPSP_DST_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-dspsp-dst-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24,
26300     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26301   },
26302 /* mov.b ${Dsp-16-u8}[sp],$Dst32AnUnprefixedQI */
26303   {
26304     M32C_INSN_MOV32_B_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-dspsp-dst-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mov.b", 24,
26305     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26306   },
26307 /* mov.b ${Dsp-16-u8}[sp],[$Dst32AnUnprefixed] */
26308   {
26309     M32C_INSN_MOV32_B_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-dspsp-dst-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mov.b", 24,
26310     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26311   },
26312 /* mov.w ${Dsp-24-u8}[sp],${Dsp-16-u8}[$Dst16An] */
26313   {
26314     M32C_INSN_MOV16_W_DSPSP_DST_16_8_DST16_16_8_AN_RELATIVE_HI, "mov16.w-dspsp-dst-16-8-dst16-16-8-An-relative-HI", "mov.w", 32,
26315     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26316   },
26317 /* mov.w ${Dsp-24-u8}[sp],${Dsp-16-u8}[sb] */
26318   {
26319     M32C_INSN_MOV16_W_DSPSP_DST_16_8_DST16_16_8_SB_RELATIVE_HI, "mov16.w-dspsp-dst-16-8-dst16-16-8-SB-relative-HI", "mov.w", 32,
26320     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26321   },
26322 /* mov.w ${Dsp-24-u8}[sp],${Dsp-16-s8}[fb] */
26323   {
26324     M32C_INSN_MOV16_W_DSPSP_DST_16_8_DST16_16_8_FB_RELATIVE_HI, "mov16.w-dspsp-dst-16-8-dst16-16-8-FB-relative-HI", "mov.w", 32,
26325     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26326   },
26327 /* mov.w ${Dsp-32-u8}[sp],${Dsp-16-u16}[$Dst16An] */
26328   {
26329     M32C_INSN_MOV16_W_DSPSP_DST_16_16_DST16_16_16_AN_RELATIVE_HI, "mov16.w-dspsp-dst-16-16-dst16-16-16-An-relative-HI", "mov.w", 40,
26330     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26331   },
26332 /* mov.w ${Dsp-32-u8}[sp],${Dsp-16-u16}[sb] */
26333   {
26334     M32C_INSN_MOV16_W_DSPSP_DST_16_16_DST16_16_16_SB_RELATIVE_HI, "mov16.w-dspsp-dst-16-16-dst16-16-16-SB-relative-HI", "mov.w", 40,
26335     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26336   },
26337 /* mov.w ${Dsp-32-u8}[sp],${Dsp-16-u16} */
26338   {
26339     M32C_INSN_MOV16_W_DSPSP_DST_16_16_DST16_16_16_ABSOLUTE_HI, "mov16.w-dspsp-dst-16-16-dst16-16-16-absolute-HI", "mov.w", 40,
26340     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26341   },
26342 /* mov.w ${Dsp-16-u8}[sp],$Dst16RnHI */
26343   {
26344     M32C_INSN_MOV16_W_DSPSP_DST_BASIC_DST16_RN_DIRECT_HI, "mov16.w-dspsp-dst-basic-dst16-Rn-direct-HI", "mov.w", 24,
26345     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26346   },
26347 /* mov.w ${Dsp-16-u8}[sp],$Dst16AnHI */
26348   {
26349     M32C_INSN_MOV16_W_DSPSP_DST_BASIC_DST16_AN_DIRECT_HI, "mov16.w-dspsp-dst-basic-dst16-An-direct-HI", "mov.w", 24,
26350     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26351   },
26352 /* mov.w ${Dsp-16-u8}[sp],[$Dst16An] */
26353   {
26354     M32C_INSN_MOV16_W_DSPSP_DST_BASIC_DST16_AN_INDIRECT_HI, "mov16.w-dspsp-dst-basic-dst16-An-indirect-HI", "mov.w", 24,
26355     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26356   },
26357 /* mov.b ${Dsp-24-u8}[sp],${Dsp-16-u8}[$Dst16An] */
26358   {
26359     M32C_INSN_MOV16_B_DSPSP_DST_16_8_DST16_16_8_AN_RELATIVE_QI, "mov16.b-dspsp-dst-16-8-dst16-16-8-An-relative-QI", "mov.b", 32,
26360     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26361   },
26362 /* mov.b ${Dsp-24-u8}[sp],${Dsp-16-u8}[sb] */
26363   {
26364     M32C_INSN_MOV16_B_DSPSP_DST_16_8_DST16_16_8_SB_RELATIVE_QI, "mov16.b-dspsp-dst-16-8-dst16-16-8-SB-relative-QI", "mov.b", 32,
26365     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26366   },
26367 /* mov.b ${Dsp-24-u8}[sp],${Dsp-16-s8}[fb] */
26368   {
26369     M32C_INSN_MOV16_B_DSPSP_DST_16_8_DST16_16_8_FB_RELATIVE_QI, "mov16.b-dspsp-dst-16-8-dst16-16-8-FB-relative-QI", "mov.b", 32,
26370     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26371   },
26372 /* mov.b ${Dsp-32-u8}[sp],${Dsp-16-u16}[$Dst16An] */
26373   {
26374     M32C_INSN_MOV16_B_DSPSP_DST_16_16_DST16_16_16_AN_RELATIVE_QI, "mov16.b-dspsp-dst-16-16-dst16-16-16-An-relative-QI", "mov.b", 40,
26375     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26376   },
26377 /* mov.b ${Dsp-32-u8}[sp],${Dsp-16-u16}[sb] */
26378   {
26379     M32C_INSN_MOV16_B_DSPSP_DST_16_16_DST16_16_16_SB_RELATIVE_QI, "mov16.b-dspsp-dst-16-16-dst16-16-16-SB-relative-QI", "mov.b", 40,
26380     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26381   },
26382 /* mov.b ${Dsp-32-u8}[sp],${Dsp-16-u16} */
26383   {
26384     M32C_INSN_MOV16_B_DSPSP_DST_16_16_DST16_16_16_ABSOLUTE_QI, "mov16.b-dspsp-dst-16-16-dst16-16-16-absolute-QI", "mov.b", 40,
26385     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26386   },
26387 /* mov.b ${Dsp-16-u8}[sp],$Dst16RnQI */
26388   {
26389     M32C_INSN_MOV16_B_DSPSP_DST_BASIC_DST16_RN_DIRECT_QI, "mov16.b-dspsp-dst-basic-dst16-Rn-direct-QI", "mov.b", 24,
26390     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26391   },
26392 /* mov.b ${Dsp-16-u8}[sp],$Dst16AnQI */
26393   {
26394     M32C_INSN_MOV16_B_DSPSP_DST_BASIC_DST16_AN_DIRECT_QI, "mov16.b-dspsp-dst-basic-dst16-An-direct-QI", "mov.b", 24,
26395     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26396   },
26397 /* mov.b ${Dsp-16-u8}[sp],[$Dst16An] */
26398   {
26399     M32C_INSN_MOV16_B_DSPSP_DST_BASIC_DST16_AN_INDIRECT_QI, "mov16.b-dspsp-dst-basic-dst16-An-indirect-QI", "mov.b", 24,
26400     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26401   },
26402 /* mov.l${S} ${Dsp-8-u8}[sb],a1 */
26403   {
26404     M32C_INSN_MOV32_SZ_DST32_2_S_8_A1_DST32_2_S_8_SB_RELATIVE_SI, "mov32.sz-dst32-2-S-8-a1-dst32-2-S-8-SB-relative-SI", "mov.l", 16,
26405     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26406   },
26407 /* mov.l${S} ${Dsp-8-s8}[fb],a1 */
26408   {
26409     M32C_INSN_MOV32_SZ_DST32_2_S_8_A1_DST32_2_S_8_FB_RELATIVE_SI, "mov32.sz-dst32-2-S-8-a1-dst32-2-S-8-FB-relative-SI", "mov.l", 16,
26410     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26411   },
26412 /* mov.l${S} ${Dsp-8-u8}[sb],a0 */
26413   {
26414     M32C_INSN_MOV32_SZ_DST32_2_S_8_A0_DST32_2_S_8_SB_RELATIVE_SI, "mov32.sz-dst32-2-S-8-a0-dst32-2-S-8-SB-relative-SI", "mov.l", 16,
26415     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26416   },
26417 /* mov.l${S} ${Dsp-8-s8}[fb],a0 */
26418   {
26419     M32C_INSN_MOV32_SZ_DST32_2_S_8_A0_DST32_2_S_8_FB_RELATIVE_SI, "mov32.sz-dst32-2-S-8-a0-dst32-2-S-8-FB-relative-SI", "mov.l", 16,
26420     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26421   },
26422 /* mov.l${S} ${Dsp-8-u16},a1 */
26423   {
26424     M32C_INSN_MOV32_SZ_DST32_2_S_16_A1_DST32_2_S_16_ABSOLUTE_SI, "mov32.sz-dst32-2-S-16-a1-dst32-2-S-16-absolute-SI", "mov.l", 24,
26425     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26426   },
26427 /* mov.l${S} ${Dsp-8-u16},a0 */
26428   {
26429     M32C_INSN_MOV32_SZ_DST32_2_S_16_A0_DST32_2_S_16_ABSOLUTE_SI, "mov32.sz-dst32-2-S-16-a0-dst32-2-S-16-absolute-SI", "mov.l", 24,
26430     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26431   },
26432 /* mov.w${S} r0,${Dsp-8-u8}[sb] */
26433   {
26434     M32C_INSN_MOV32_W_R0_DST32_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-r0-dst32-2-S-8-dst32-2-S-8-SB-relative-HI", "mov.w", 16,
26435     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26436   },
26437 /* mov.w${S} r0,${Dsp-8-s8}[fb] */
26438   {
26439     M32C_INSN_MOV32_W_R0_DST32_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-r0-dst32-2-S-8-dst32-2-S-8-FB-relative-HI", "mov.w", 16,
26440     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26441   },
26442 /* mov.b${S} r0l,${Dsp-8-u8}[sb] */
26443   {
26444     M32C_INSN_MOV32_B_R0L_DST32_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-r0l-dst32-2-S-8-dst32-2-S-8-SB-relative-QI", "mov.b", 16,
26445     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26446   },
26447 /* mov.b${S} r0l,${Dsp-8-s8}[fb] */
26448   {
26449     M32C_INSN_MOV32_B_R0L_DST32_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-r0l-dst32-2-S-8-dst32-2-S-8-FB-relative-QI", "mov.b", 16,
26450     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26451   },
26452 /* mov.w${S} r0,${Dsp-8-u16} */
26453   {
26454     M32C_INSN_MOV32_W_R0_DST32_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-r0-dst32-2-S-16-dst32-2-S-16-absolute-HI", "mov.w", 24,
26455     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26456   },
26457 /* mov.b${S} r0l,${Dsp-8-u16} */
26458   {
26459     M32C_INSN_MOV32_B_R0L_DST32_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-r0l-dst32-2-S-16-dst32-2-S-16-absolute-QI", "mov.b", 24,
26460     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26461   },
26462 /* mov.w${S} ${Dsp-8-u8}[sb],r1 */
26463   {
26464     M32C_INSN_MOV32_W_DST32_2_S_8_R1_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-dst32-2-S-8-r1-dst32-2-S-8-SB-relative-HI", "mov.w", 16,
26465     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26466   },
26467 /* mov.w${S} ${Dsp-8-s8}[fb],r1 */
26468   {
26469     M32C_INSN_MOV32_W_DST32_2_S_8_R1_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-dst32-2-S-8-r1-dst32-2-S-8-FB-relative-HI", "mov.w", 16,
26470     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26471   },
26472 /* mov.b${S} ${Dsp-8-u8}[sb],r1l */
26473   {
26474     M32C_INSN_MOV32_B_DST32_2_S_8_R1L_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-dst32-2-S-8-r1l-dst32-2-S-8-SB-relative-QI", "mov.b", 16,
26475     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26476   },
26477 /* mov.b${S} ${Dsp-8-s8}[fb],r1l */
26478   {
26479     M32C_INSN_MOV32_B_DST32_2_S_8_R1L_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-dst32-2-S-8-r1l-dst32-2-S-8-FB-relative-QI", "mov.b", 16,
26480     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26481   },
26482 /* mov.w${S} ${Dsp-8-u16},r1 */
26483   {
26484     M32C_INSN_MOV32_W_DST32_2_S_16_R1_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-dst32-2-S-16-r1-dst32-2-S-16-absolute-HI", "mov.w", 24,
26485     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26486   },
26487 /* mov.b${S} ${Dsp-8-u16},r1l */
26488   {
26489     M32C_INSN_MOV32_B_DST32_2_S_16_R1L_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-dst32-2-S-16-r1l-dst32-2-S-16-absolute-QI", "mov.b", 24,
26490     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26491   },
26492 /* mov.w${S} r0,r1l */
26493   {
26494     M32C_INSN_MOV32_W_DST32_2_S_BASIC_R1L_DST32_2_S_R0_DIRECT_HI, "mov32.w-dst32-2-S-basic-r1l-dst32-2-S-R0-direct-HI", "mov.w", 8,
26495     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26496   },
26497 /* mov.b${S} r0l,r1l */
26498   {
26499     M32C_INSN_MOV32_B_DST32_2_S_BASIC_R1L_DST32_2_S_R0L_DIRECT_QI, "mov32.b-dst32-2-S-basic-r1l-dst32-2-S-R0l-direct-QI", "mov.b", 8,
26500     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26501   },
26502 /* mov.w${S} ${Dsp-8-u8}[sb],r0 */
26503   {
26504     M32C_INSN_MOV32_W_DST32_2_S_8_R0_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-dst32-2-S-8-r0-dst32-2-S-8-SB-relative-HI", "mov.w", 16,
26505     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26506   },
26507 /* mov.w${S} ${Dsp-8-s8}[fb],r0 */
26508   {
26509     M32C_INSN_MOV32_W_DST32_2_S_8_R0_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-dst32-2-S-8-r0-dst32-2-S-8-FB-relative-HI", "mov.w", 16,
26510     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26511   },
26512 /* mov.b${S} ${Dsp-8-u8}[sb],r0l */
26513   {
26514     M32C_INSN_MOV32_B_DST32_2_S_8_R0L_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-dst32-2-S-8-r0l-dst32-2-S-8-SB-relative-QI", "mov.b", 16,
26515     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26516   },
26517 /* mov.b${S} ${Dsp-8-s8}[fb],r0l */
26518   {
26519     M32C_INSN_MOV32_B_DST32_2_S_8_R0L_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-dst32-2-S-8-r0l-dst32-2-S-8-FB-relative-QI", "mov.b", 16,
26520     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26521   },
26522 /* mov.w${S} ${Dsp-8-u16},r0 */
26523   {
26524     M32C_INSN_MOV32_W_DST32_2_S_16_R0_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-dst32-2-S-16-r0-dst32-2-S-16-absolute-HI", "mov.w", 24,
26525     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26526   },
26527 /* mov.b${S} ${Dsp-8-u16},r0l */
26528   {
26529     M32C_INSN_MOV32_B_DST32_2_S_16_R0L_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-dst32-2-S-16-r0l-dst32-2-S-16-absolute-QI", "mov.b", 24,
26530     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26531   },
26532 /* mov.b${S} ${SrcDst16-r0l-r0h-S-normal} */
26533   {
26534     M32C_INSN_MOV16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, "mov16.b.S-r0l-r0h-srcdst16-r0l-r0h-S-derived", "mov.b", 8,
26535     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26536   },
26537 /* mov.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
26538   {
26539     M32C_INSN_MOV16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, "mov16.b.S-src2-src16-2-S-8-SB-relative-QI", "mov.b", 16,
26540     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26541   },
26542 /* mov.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
26543   {
26544     M32C_INSN_MOV16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, "mov16.b.S-src2-src16-2-S-8-FB-relative-QI", "mov.b", 16,
26545     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26546   },
26547 /* mov.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
26548   {
26549     M32C_INSN_MOV16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, "mov16.b.S-src2-src16-2-S-16-absolute-QI", "mov.b", 24,
26550     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26551   },
26552 /* mov.b${S} ${Dst16RnQI-S},${Dsp-8-u8}[sb] */
26553   {
26554     M32C_INSN_MOV16_B_S_RN_AN_SRC16_2_S_8_SB_RELATIVE_QI, "mov16.b.S-Rn-An-src16-2-S-8-SB-relative-QI", "mov.b", 16,
26555     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26556   },
26557 /* mov.b${S} ${Dst16RnQI-S},${Dsp-8-s8}[fb] */
26558   {
26559     M32C_INSN_MOV16_B_S_RN_AN_SRC16_2_S_8_FB_RELATIVE_QI, "mov16.b.S-Rn-An-src16-2-S-8-FB-relative-QI", "mov.b", 16,
26560     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26561   },
26562 /* mov.b${S} ${Dst16RnQI-S},${Dsp-8-u16} */
26563   {
26564     M32C_INSN_MOV16_B_S_RN_AN_SRC16_2_S_16_ABSOLUTE_QI, "mov16.b.S-Rn-An-src16-2-S-16-absolute-QI", "mov.b", 24,
26565     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26566   },
26567 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
26568   {
26569     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 24,
26570     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26571   },
26572 /* mov.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
26573   {
26574     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 24,
26575     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26576   },
26577 /* mov.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
26578   {
26579     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 24,
26580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26581   },
26582 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
26583   {
26584     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 24,
26585     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26586   },
26587 /* mov.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
26588   {
26589     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 24,
26590     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26591   },
26592 /* mov.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
26593   {
26594     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 24,
26595     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26596   },
26597 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
26598   {
26599     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 24,
26600     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26601   },
26602 /* mov.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
26603   {
26604     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 24,
26605     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26606   },
26607 /* mov.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
26608   {
26609     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 24,
26610     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26611   },
26612 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
26613   {
26614     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "mov.l", 32,
26615     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26616   },
26617 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
26618   {
26619     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "mov.l", 32,
26620     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26621   },
26622 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
26623   {
26624     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "mov.l", 32,
26625     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26626   },
26627 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
26628   {
26629     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "mov.l", 40,
26630     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26631   },
26632 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
26633   {
26634     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "mov.l", 40,
26635     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26636   },
26637 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
26638   {
26639     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "mov.l", 40,
26640     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26641   },
26642 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
26643   {
26644     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "mov.l", 48,
26645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26646   },
26647 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
26648   {
26649     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "mov.l", 48,
26650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26651   },
26652 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
26653   {
26654     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "mov.l", 48,
26655     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26656   },
26657 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
26658   {
26659     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "mov.l", 32,
26660     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26661   },
26662 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
26663   {
26664     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "mov.l", 32,
26665     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26666   },
26667 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
26668   {
26669     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "mov.l", 32,
26670     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26671   },
26672 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
26673   {
26674     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "mov.l", 40,
26675     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26676   },
26677 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
26678   {
26679     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "mov.l", 40,
26680     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26681   },
26682 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
26683   {
26684     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "mov.l", 40,
26685     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26686   },
26687 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
26688   {
26689     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "mov.l", 32,
26690     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26691   },
26692 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
26693   {
26694     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "mov.l", 32,
26695     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26696   },
26697 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
26698   {
26699     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "mov.l", 32,
26700     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26701   },
26702 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
26703   {
26704     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "mov.l", 40,
26705     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26706   },
26707 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
26708   {
26709     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "mov.l", 40,
26710     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26711   },
26712 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
26713   {
26714     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "mov.l", 40,
26715     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26716   },
26717 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
26718   {
26719     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "mov.l", 40,
26720     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26721   },
26722 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
26723   {
26724     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "mov.l", 40,
26725     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26726   },
26727 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
26728   {
26729     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "mov.l", 40,
26730     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26731   },
26732 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
26733   {
26734     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "mov.l", 48,
26735     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26736   },
26737 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
26738   {
26739     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "mov.l", 48,
26740     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26741   },
26742 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
26743   {
26744     M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "mov.l", 48,
26745     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26746   },
26747 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
26748   {
26749     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 32,
26750     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26751   },
26752 /* mov.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
26753   {
26754     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 32,
26755     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26756   },
26757 /* mov.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
26758   {
26759     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 32,
26760     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26761   },
26762 /* mov.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
26763   {
26764     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 32,
26765     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26766   },
26767 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
26768   {
26769     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 32,
26770     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26771   },
26772 /* mov.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
26773   {
26774     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 32,
26775     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26776   },
26777 /* mov.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
26778   {
26779     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 32,
26780     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26781   },
26782 /* mov.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
26783   {
26784     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 32,
26785     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26786   },
26787 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
26788   {
26789     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 32,
26790     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26791   },
26792 /* mov.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
26793   {
26794     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 32,
26795     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26796   },
26797 /* mov.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
26798   {
26799     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 32,
26800     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26801   },
26802 /* mov.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
26803   {
26804     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 32,
26805     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26806   },
26807 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
26808   {
26809     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "mov.l", 40,
26810     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26811   },
26812 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
26813   {
26814     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "mov.l", 40,
26815     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26816   },
26817 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
26818   {
26819     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "mov.l", 40,
26820     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26821   },
26822 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
26823   {
26824     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "mov.l", 40,
26825     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26826   },
26827 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
26828   {
26829     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "mov.l", 48,
26830     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26831   },
26832 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
26833   {
26834     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "mov.l", 48,
26835     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26836   },
26837 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
26838   {
26839     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "mov.l", 48,
26840     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26841   },
26842 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
26843   {
26844     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "mov.l", 48,
26845     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26846   },
26847 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
26848   {
26849     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "mov.l", 56,
26850     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26851   },
26852 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
26853   {
26854     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "mov.l", 56,
26855     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26856   },
26857 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
26858   {
26859     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "mov.l", 56,
26860     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26861   },
26862 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
26863   {
26864     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "mov.l", 56,
26865     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26866   },
26867 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
26868   {
26869     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "mov.l", 40,
26870     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26871   },
26872 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
26873   {
26874     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "mov.l", 40,
26875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26876   },
26877 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
26878   {
26879     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "mov.l", 40,
26880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26881   },
26882 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
26883   {
26884     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "mov.l", 40,
26885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26886   },
26887 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
26888   {
26889     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "mov.l", 48,
26890     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26891   },
26892 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
26893   {
26894     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "mov.l", 48,
26895     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26896   },
26897 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
26898   {
26899     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "mov.l", 48,
26900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26901   },
26902 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
26903   {
26904     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "mov.l", 48,
26905     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26906   },
26907 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
26908   {
26909     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "mov.l", 40,
26910     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26911   },
26912 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
26913   {
26914     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "mov.l", 40,
26915     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26916   },
26917 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
26918   {
26919     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "mov.l", 40,
26920     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26921   },
26922 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
26923   {
26924     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "mov.l", 40,
26925     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26926   },
26927 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
26928   {
26929     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "mov.l", 48,
26930     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26931   },
26932 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
26933   {
26934     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "mov.l", 48,
26935     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26936   },
26937 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
26938   {
26939     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "mov.l", 48,
26940     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26941   },
26942 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
26943   {
26944     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "mov.l", 48,
26945     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26946   },
26947 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
26948   {
26949     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "mov.l", 48,
26950     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26951   },
26952 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
26953   {
26954     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "mov.l", 48,
26955     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26956   },
26957 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
26958   {
26959     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "mov.l", 48,
26960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26961   },
26962 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u16} */
26963   {
26964     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "mov.l", 48,
26965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26966   },
26967 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
26968   {
26969     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "mov.l", 56,
26970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26971   },
26972 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
26973   {
26974     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "mov.l", 56,
26975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26976   },
26977 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
26978   {
26979     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "mov.l", 56,
26980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26981   },
26982 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u24} */
26983   {
26984     M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "mov.l", 56,
26985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26986   },
26987 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
26988   {
26989     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 40,
26990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26991   },
26992 /* mov.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
26993   {
26994     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 40,
26995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26996   },
26997 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
26998   {
26999     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 40,
27000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27001   },
27002 /* mov.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
27003   {
27004     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 40,
27005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27006   },
27007 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
27008   {
27009     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 40,
27010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27011   },
27012 /* mov.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
27013   {
27014     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 40,
27015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27016   },
27017 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
27018   {
27019     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "mov.l", 48,
27020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27021   },
27022 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
27023   {
27024     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "mov.l", 48,
27025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27026   },
27027 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
27028   {
27029     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "mov.l", 56,
27030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27031   },
27032 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
27033   {
27034     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "mov.l", 56,
27035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27036   },
27037 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
27038   {
27039     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "mov.l", 64,
27040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27041   },
27042 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
27043   {
27044     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "mov.l", 64,
27045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27046   },
27047 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
27048   {
27049     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "mov.l", 48,
27050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27051   },
27052 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
27053   {
27054     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "mov.l", 48,
27055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27056   },
27057 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
27058   {
27059     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "mov.l", 56,
27060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27061   },
27062 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
27063   {
27064     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "mov.l", 56,
27065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27066   },
27067 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
27068   {
27069     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "mov.l", 48,
27070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27071   },
27072 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
27073   {
27074     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "mov.l", 48,
27075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27076   },
27077 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
27078   {
27079     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "mov.l", 56,
27080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27081   },
27082 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
27083   {
27084     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "mov.l", 56,
27085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27086   },
27087 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
27088   {
27089     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "mov.l", 56,
27090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27091   },
27092 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u16} */
27093   {
27094     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "mov.l", 56,
27095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27096   },
27097 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
27098   {
27099     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "mov.l", 64,
27100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27101   },
27102 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u24} */
27103   {
27104     M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "mov.l", 64,
27105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27106   },
27107 /* mov.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */
27108   {
27109     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 16,
27110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27111   },
27112 /* mov.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */
27113   {
27114     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 16,
27115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27116   },
27117 /* mov.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
27118   {
27119     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 16,
27120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27121   },
27122 /* mov.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */
27123   {
27124     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 16,
27125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27126   },
27127 /* mov.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */
27128   {
27129     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 16,
27130     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27131   },
27132 /* mov.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
27133   {
27134     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 16,
27135     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27136   },
27137 /* mov.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */
27138   {
27139     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 16,
27140     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27141   },
27142 /* mov.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */
27143   {
27144     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 16,
27145     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27146   },
27147 /* mov.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
27148   {
27149     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 16,
27150     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27151   },
27152 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
27153   {
27154     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "mov.l", 24,
27155     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27156   },
27157 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
27158   {
27159     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "mov.l", 24,
27160     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27161   },
27162 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
27163   {
27164     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "mov.l", 24,
27165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27166   },
27167 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
27168   {
27169     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "mov.l", 32,
27170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27171   },
27172 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
27173   {
27174     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "mov.l", 32,
27175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27176   },
27177 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
27178   {
27179     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "mov.l", 32,
27180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27181   },
27182 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
27183   {
27184     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "mov.l", 40,
27185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27186   },
27187 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
27188   {
27189     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "mov.l", 40,
27190     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27191   },
27192 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
27193   {
27194     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "mov.l", 40,
27195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27196   },
27197 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */
27198   {
27199     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "mov.l", 24,
27200     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27201   },
27202 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */
27203   {
27204     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "mov.l", 24,
27205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27206   },
27207 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
27208   {
27209     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "mov.l", 24,
27210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27211   },
27212 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */
27213   {
27214     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "mov.l", 32,
27215     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27216   },
27217 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */
27218   {
27219     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "mov.l", 32,
27220     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27221   },
27222 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
27223   {
27224     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "mov.l", 32,
27225     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27226   },
27227 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */
27228   {
27229     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "mov.l", 24,
27230     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27231   },
27232 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */
27233   {
27234     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "mov.l", 24,
27235     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27236   },
27237 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
27238   {
27239     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "mov.l", 24,
27240     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27241   },
27242 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */
27243   {
27244     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "mov.l", 32,
27245     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27246   },
27247 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */
27248   {
27249     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "mov.l", 32,
27250     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27251   },
27252 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
27253   {
27254     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "mov.l", 32,
27255     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27256   },
27257 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */
27258   {
27259     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "mov.l", 32,
27260     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27261   },
27262 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */
27263   {
27264     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "mov.l", 32,
27265     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27266   },
27267 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
27268   {
27269     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "mov.l", 32,
27270     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27271   },
27272 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */
27273   {
27274     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "mov.l", 40,
27275     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27276   },
27277 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */
27278   {
27279     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "mov.l", 40,
27280     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27281   },
27282 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
27283   {
27284     M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "mov.l", 40,
27285     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27286   },
27287 /* mov.b${S} ${Dsp-8-u8}[sb],${Dst16AnQI-S} */
27288   {
27289     M32C_INSN_MOV16_B_S_AN_SRC16_2_S_8_SB_RELATIVE_QI, "mov16.b.S-An-src16-2-S-8-SB-relative-QI", "mov.b", 16,
27290     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
27291   },
27292 /* mov.b${S} ${Dsp-8-s8}[fb],${Dst16AnQI-S} */
27293   {
27294     M32C_INSN_MOV16_B_S_AN_SRC16_2_S_8_FB_RELATIVE_QI, "mov16.b.S-An-src16-2-S-8-FB-relative-QI", "mov.b", 16,
27295     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
27296   },
27297 /* mov.b${S} ${Dsp-8-u16},${Dst16AnQI-S} */
27298   {
27299     M32C_INSN_MOV16_B_S_AN_SRC16_2_S_16_ABSOLUTE_QI, "mov16.b.S-An-src16-2-S-16-absolute-QI", "mov.b", 24,
27300     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
27301   },
27302 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
27303   {
27304     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24,
27305     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27306   },
27307 /* mov.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
27308   {
27309     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24,
27310     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27311   },
27312 /* mov.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
27313   {
27314     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24,
27315     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27316   },
27317 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
27318   {
27319     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 24,
27320     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27321   },
27322 /* mov.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
27323   {
27324     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 24,
27325     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27326   },
27327 /* mov.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
27328   {
27329     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 24,
27330     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27331   },
27332 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
27333   {
27334     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 24,
27335     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27336   },
27337 /* mov.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
27338   {
27339     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 24,
27340     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27341   },
27342 /* mov.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
27343   {
27344     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 24,
27345     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27346   },
27347 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
27348   {
27349     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mov.w", 32,
27350     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27351   },
27352 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
27353   {
27354     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mov.w", 32,
27355     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27356   },
27357 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
27358   {
27359     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mov.w", 32,
27360     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27361   },
27362 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
27363   {
27364     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mov.w", 40,
27365     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27366   },
27367 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
27368   {
27369     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mov.w", 40,
27370     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27371   },
27372 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
27373   {
27374     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mov.w", 40,
27375     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27376   },
27377 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
27378   {
27379     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mov.w", 48,
27380     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27381   },
27382 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
27383   {
27384     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mov.w", 48,
27385     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27386   },
27387 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
27388   {
27389     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mov.w", 48,
27390     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27391   },
27392 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
27393   {
27394     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mov.w", 32,
27395     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27396   },
27397 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
27398   {
27399     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mov.w", 32,
27400     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27401   },
27402 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
27403   {
27404     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mov.w", 32,
27405     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27406   },
27407 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
27408   {
27409     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mov.w", 40,
27410     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27411   },
27412 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
27413   {
27414     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mov.w", 40,
27415     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27416   },
27417 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
27418   {
27419     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mov.w", 40,
27420     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27421   },
27422 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
27423   {
27424     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mov.w", 32,
27425     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27426   },
27427 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
27428   {
27429     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mov.w", 32,
27430     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27431   },
27432 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
27433   {
27434     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mov.w", 32,
27435     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27436   },
27437 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
27438   {
27439     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mov.w", 40,
27440     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27441   },
27442 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
27443   {
27444     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mov.w", 40,
27445     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27446   },
27447 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
27448   {
27449     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mov.w", 40,
27450     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27451   },
27452 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
27453   {
27454     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mov.w", 40,
27455     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27456   },
27457 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
27458   {
27459     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mov.w", 40,
27460     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27461   },
27462 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
27463   {
27464     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mov.w", 40,
27465     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27466   },
27467 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
27468   {
27469     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mov.w", 48,
27470     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27471   },
27472 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
27473   {
27474     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mov.w", 48,
27475     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27476   },
27477 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
27478   {
27479     M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mov.w", 48,
27480     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27481   },
27482 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
27483   {
27484     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32,
27485     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27486   },
27487 /* mov.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
27488   {
27489     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32,
27490     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27491   },
27492 /* mov.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
27493   {
27494     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32,
27495     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27496   },
27497 /* mov.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
27498   {
27499     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32,
27500     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27501   },
27502 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
27503   {
27504     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 32,
27505     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27506   },
27507 /* mov.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
27508   {
27509     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 32,
27510     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27511   },
27512 /* mov.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
27513   {
27514     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 32,
27515     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27516   },
27517 /* mov.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
27518   {
27519     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 32,
27520     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27521   },
27522 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
27523   {
27524     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 32,
27525     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27526   },
27527 /* mov.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
27528   {
27529     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 32,
27530     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27531   },
27532 /* mov.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
27533   {
27534     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 32,
27535     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27536   },
27537 /* mov.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
27538   {
27539     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 32,
27540     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27541   },
27542 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
27543   {
27544     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mov.w", 40,
27545     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27546   },
27547 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
27548   {
27549     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mov.w", 40,
27550     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27551   },
27552 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
27553   {
27554     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mov.w", 40,
27555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27556   },
27557 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
27558   {
27559     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mov.w", 40,
27560     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27561   },
27562 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
27563   {
27564     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mov.w", 48,
27565     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27566   },
27567 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
27568   {
27569     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mov.w", 48,
27570     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27571   },
27572 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
27573   {
27574     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mov.w", 48,
27575     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27576   },
27577 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
27578   {
27579     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mov.w", 48,
27580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27581   },
27582 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
27583   {
27584     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mov.w", 56,
27585     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27586   },
27587 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
27588   {
27589     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mov.w", 56,
27590     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27591   },
27592 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
27593   {
27594     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mov.w", 56,
27595     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27596   },
27597 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
27598   {
27599     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mov.w", 56,
27600     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27601   },
27602 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
27603   {
27604     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mov.w", 40,
27605     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27606   },
27607 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
27608   {
27609     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mov.w", 40,
27610     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27611   },
27612 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
27613   {
27614     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mov.w", 40,
27615     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27616   },
27617 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
27618   {
27619     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mov.w", 40,
27620     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27621   },
27622 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
27623   {
27624     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mov.w", 48,
27625     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27626   },
27627 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
27628   {
27629     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mov.w", 48,
27630     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27631   },
27632 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
27633   {
27634     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mov.w", 48,
27635     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27636   },
27637 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
27638   {
27639     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mov.w", 48,
27640     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27641   },
27642 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
27643   {
27644     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mov.w", 40,
27645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27646   },
27647 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
27648   {
27649     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mov.w", 40,
27650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27651   },
27652 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
27653   {
27654     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mov.w", 40,
27655     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27656   },
27657 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
27658   {
27659     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mov.w", 40,
27660     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27661   },
27662 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
27663   {
27664     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mov.w", 48,
27665     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27666   },
27667 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
27668   {
27669     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mov.w", 48,
27670     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27671   },
27672 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
27673   {
27674     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mov.w", 48,
27675     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27676   },
27677 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
27678   {
27679     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mov.w", 48,
27680     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27681   },
27682 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
27683   {
27684     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mov.w", 48,
27685     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27686   },
27687 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
27688   {
27689     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mov.w", 48,
27690     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27691   },
27692 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
27693   {
27694     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mov.w", 48,
27695     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27696   },
27697 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
27698   {
27699     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mov.w", 48,
27700     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27701   },
27702 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
27703   {
27704     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mov.w", 56,
27705     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27706   },
27707 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
27708   {
27709     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mov.w", 56,
27710     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27711   },
27712 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
27713   {
27714     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mov.w", 56,
27715     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27716   },
27717 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
27718   {
27719     M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mov.w", 56,
27720     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27721   },
27722 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
27723   {
27724     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 40,
27725     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27726   },
27727 /* mov.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
27728   {
27729     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 40,
27730     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27731   },
27732 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
27733   {
27734     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 40,
27735     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27736   },
27737 /* mov.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
27738   {
27739     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 40,
27740     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27741   },
27742 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
27743   {
27744     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 40,
27745     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27746   },
27747 /* mov.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
27748   {
27749     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 40,
27750     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27751   },
27752 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
27753   {
27754     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mov.w", 48,
27755     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27756   },
27757 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
27758   {
27759     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mov.w", 48,
27760     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27761   },
27762 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
27763   {
27764     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mov.w", 56,
27765     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27766   },
27767 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
27768   {
27769     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mov.w", 56,
27770     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27771   },
27772 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
27773   {
27774     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mov.w", 64,
27775     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27776   },
27777 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
27778   {
27779     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mov.w", 64,
27780     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27781   },
27782 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
27783   {
27784     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mov.w", 48,
27785     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27786   },
27787 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
27788   {
27789     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mov.w", 48,
27790     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27791   },
27792 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
27793   {
27794     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mov.w", 56,
27795     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27796   },
27797 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
27798   {
27799     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mov.w", 56,
27800     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27801   },
27802 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
27803   {
27804     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mov.w", 48,
27805     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27806   },
27807 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
27808   {
27809     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mov.w", 48,
27810     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27811   },
27812 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
27813   {
27814     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mov.w", 56,
27815     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27816   },
27817 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
27818   {
27819     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mov.w", 56,
27820     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27821   },
27822 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
27823   {
27824     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mov.w", 56,
27825     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27826   },
27827 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
27828   {
27829     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mov.w", 56,
27830     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27831   },
27832 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
27833   {
27834     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mov.w", 64,
27835     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27836   },
27837 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
27838   {
27839     M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mov.w", 64,
27840     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27841   },
27842 /* mov.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
27843   {
27844     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 16,
27845     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27846   },
27847 /* mov.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
27848   {
27849     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 16,
27850     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27851   },
27852 /* mov.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
27853   {
27854     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 16,
27855     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27856   },
27857 /* mov.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
27858   {
27859     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 16,
27860     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27861   },
27862 /* mov.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
27863   {
27864     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 16,
27865     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27866   },
27867 /* mov.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
27868   {
27869     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 16,
27870     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27871   },
27872 /* mov.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
27873   {
27874     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 16,
27875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27876   },
27877 /* mov.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
27878   {
27879     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 16,
27880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27881   },
27882 /* mov.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
27883   {
27884     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 16,
27885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27886   },
27887 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
27888   {
27889     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 24,
27890     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27891   },
27892 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
27893   {
27894     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 24,
27895     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27896   },
27897 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
27898   {
27899     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 24,
27900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27901   },
27902 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
27903   {
27904     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 32,
27905     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27906   },
27907 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
27908   {
27909     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 32,
27910     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27911   },
27912 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
27913   {
27914     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 32,
27915     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27916   },
27917 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
27918   {
27919     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 40,
27920     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27921   },
27922 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
27923   {
27924     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 40,
27925     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27926   },
27927 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
27928   {
27929     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 40,
27930     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27931   },
27932 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
27933   {
27934     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 24,
27935     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27936   },
27937 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
27938   {
27939     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 24,
27940     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27941   },
27942 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
27943   {
27944     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 24,
27945     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27946   },
27947 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
27948   {
27949     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 32,
27950     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27951   },
27952 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
27953   {
27954     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 32,
27955     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27956   },
27957 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
27958   {
27959     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 32,
27960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27961   },
27962 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
27963   {
27964     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 24,
27965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27966   },
27967 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
27968   {
27969     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 24,
27970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27971   },
27972 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
27973   {
27974     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 24,
27975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27976   },
27977 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
27978   {
27979     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 32,
27980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27981   },
27982 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
27983   {
27984     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 32,
27985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27986   },
27987 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
27988   {
27989     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 32,
27990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27991   },
27992 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
27993   {
27994     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 32,
27995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27996   },
27997 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
27998   {
27999     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 32,
28000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28001   },
28002 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
28003   {
28004     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 32,
28005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28006   },
28007 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
28008   {
28009     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 40,
28010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28011   },
28012 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
28013   {
28014     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 40,
28015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28016   },
28017 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
28018   {
28019     M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 40,
28020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28021   },
28022 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
28023   {
28024     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24,
28025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28026   },
28027 /* mov.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
28028   {
28029     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24,
28030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28031   },
28032 /* mov.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
28033   {
28034     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24,
28035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28036   },
28037 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
28038   {
28039     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 24,
28040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28041   },
28042 /* mov.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
28043   {
28044     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 24,
28045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28046   },
28047 /* mov.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
28048   {
28049     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 24,
28050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28051   },
28052 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
28053   {
28054     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 24,
28055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28056   },
28057 /* mov.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
28058   {
28059     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 24,
28060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28061   },
28062 /* mov.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
28063   {
28064     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 24,
28065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28066   },
28067 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
28068   {
28069     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mov.b", 32,
28070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28071   },
28072 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
28073   {
28074     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mov.b", 32,
28075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28076   },
28077 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
28078   {
28079     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mov.b", 32,
28080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28081   },
28082 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
28083   {
28084     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mov.b", 40,
28085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28086   },
28087 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
28088   {
28089     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mov.b", 40,
28090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28091   },
28092 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
28093   {
28094     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mov.b", 40,
28095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28096   },
28097 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
28098   {
28099     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mov.b", 48,
28100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28101   },
28102 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
28103   {
28104     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mov.b", 48,
28105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28106   },
28107 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
28108   {
28109     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mov.b", 48,
28110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28111   },
28112 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
28113   {
28114     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mov.b", 32,
28115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28116   },
28117 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
28118   {
28119     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mov.b", 32,
28120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28121   },
28122 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
28123   {
28124     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mov.b", 32,
28125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28126   },
28127 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
28128   {
28129     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mov.b", 40,
28130     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28131   },
28132 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
28133   {
28134     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mov.b", 40,
28135     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28136   },
28137 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
28138   {
28139     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mov.b", 40,
28140     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28141   },
28142 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
28143   {
28144     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mov.b", 32,
28145     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28146   },
28147 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
28148   {
28149     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mov.b", 32,
28150     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28151   },
28152 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
28153   {
28154     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mov.b", 32,
28155     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28156   },
28157 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
28158   {
28159     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mov.b", 40,
28160     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28161   },
28162 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
28163   {
28164     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mov.b", 40,
28165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28166   },
28167 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
28168   {
28169     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mov.b", 40,
28170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28171   },
28172 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
28173   {
28174     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mov.b", 40,
28175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28176   },
28177 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
28178   {
28179     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mov.b", 40,
28180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28181   },
28182 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
28183   {
28184     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mov.b", 40,
28185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28186   },
28187 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
28188   {
28189     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mov.b", 48,
28190     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28191   },
28192 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
28193   {
28194     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mov.b", 48,
28195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28196   },
28197 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
28198   {
28199     M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mov.b", 48,
28200     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28201   },
28202 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
28203   {
28204     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 32,
28205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28206   },
28207 /* mov.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
28208   {
28209     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 32,
28210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28211   },
28212 /* mov.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
28213   {
28214     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 32,
28215     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28216   },
28217 /* mov.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
28218   {
28219     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 32,
28220     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28221   },
28222 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
28223   {
28224     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 32,
28225     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28226   },
28227 /* mov.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
28228   {
28229     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 32,
28230     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28231   },
28232 /* mov.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
28233   {
28234     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 32,
28235     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28236   },
28237 /* mov.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
28238   {
28239     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 32,
28240     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28241   },
28242 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
28243   {
28244     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 32,
28245     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28246   },
28247 /* mov.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
28248   {
28249     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 32,
28250     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28251   },
28252 /* mov.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
28253   {
28254     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 32,
28255     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28256   },
28257 /* mov.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
28258   {
28259     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 32,
28260     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28261   },
28262 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
28263   {
28264     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mov.b", 40,
28265     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28266   },
28267 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
28268   {
28269     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mov.b", 40,
28270     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28271   },
28272 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
28273   {
28274     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mov.b", 40,
28275     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28276   },
28277 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
28278   {
28279     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mov.b", 40,
28280     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28281   },
28282 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
28283   {
28284     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mov.b", 48,
28285     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28286   },
28287 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
28288   {
28289     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mov.b", 48,
28290     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28291   },
28292 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
28293   {
28294     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mov.b", 48,
28295     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28296   },
28297 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
28298   {
28299     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mov.b", 48,
28300     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28301   },
28302 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
28303   {
28304     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mov.b", 56,
28305     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28306   },
28307 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
28308   {
28309     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mov.b", 56,
28310     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28311   },
28312 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
28313   {
28314     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mov.b", 56,
28315     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28316   },
28317 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
28318   {
28319     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mov.b", 56,
28320     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28321   },
28322 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
28323   {
28324     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mov.b", 40,
28325     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28326   },
28327 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
28328   {
28329     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mov.b", 40,
28330     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28331   },
28332 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
28333   {
28334     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mov.b", 40,
28335     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28336   },
28337 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
28338   {
28339     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mov.b", 40,
28340     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28341   },
28342 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
28343   {
28344     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mov.b", 48,
28345     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28346   },
28347 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
28348   {
28349     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mov.b", 48,
28350     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28351   },
28352 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
28353   {
28354     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mov.b", 48,
28355     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28356   },
28357 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
28358   {
28359     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mov.b", 48,
28360     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28361   },
28362 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
28363   {
28364     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mov.b", 40,
28365     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28366   },
28367 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
28368   {
28369     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mov.b", 40,
28370     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28371   },
28372 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
28373   {
28374     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mov.b", 40,
28375     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28376   },
28377 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
28378   {
28379     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mov.b", 40,
28380     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28381   },
28382 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
28383   {
28384     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mov.b", 48,
28385     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28386   },
28387 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
28388   {
28389     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mov.b", 48,
28390     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28391   },
28392 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
28393   {
28394     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mov.b", 48,
28395     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28396   },
28397 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
28398   {
28399     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mov.b", 48,
28400     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28401   },
28402 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
28403   {
28404     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mov.b", 48,
28405     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28406   },
28407 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
28408   {
28409     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mov.b", 48,
28410     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28411   },
28412 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
28413   {
28414     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mov.b", 48,
28415     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28416   },
28417 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
28418   {
28419     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mov.b", 48,
28420     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28421   },
28422 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
28423   {
28424     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mov.b", 56,
28425     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28426   },
28427 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
28428   {
28429     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mov.b", 56,
28430     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28431   },
28432 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
28433   {
28434     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mov.b", 56,
28435     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28436   },
28437 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
28438   {
28439     M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mov.b", 56,
28440     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28441   },
28442 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
28443   {
28444     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 40,
28445     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28446   },
28447 /* mov.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
28448   {
28449     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 40,
28450     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28451   },
28452 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
28453   {
28454     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 40,
28455     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28456   },
28457 /* mov.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
28458   {
28459     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 40,
28460     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28461   },
28462 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
28463   {
28464     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 40,
28465     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28466   },
28467 /* mov.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
28468   {
28469     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 40,
28470     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28471   },
28472 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
28473   {
28474     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mov.b", 48,
28475     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28476   },
28477 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
28478   {
28479     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mov.b", 48,
28480     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28481   },
28482 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
28483   {
28484     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mov.b", 56,
28485     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28486   },
28487 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
28488   {
28489     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mov.b", 56,
28490     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28491   },
28492 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
28493   {
28494     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mov.b", 64,
28495     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28496   },
28497 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
28498   {
28499     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mov.b", 64,
28500     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28501   },
28502 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
28503   {
28504     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mov.b", 48,
28505     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28506   },
28507 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
28508   {
28509     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mov.b", 48,
28510     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28511   },
28512 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
28513   {
28514     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mov.b", 56,
28515     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28516   },
28517 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
28518   {
28519     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mov.b", 56,
28520     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28521   },
28522 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
28523   {
28524     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mov.b", 48,
28525     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28526   },
28527 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
28528   {
28529     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mov.b", 48,
28530     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28531   },
28532 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
28533   {
28534     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mov.b", 56,
28535     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28536   },
28537 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
28538   {
28539     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mov.b", 56,
28540     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28541   },
28542 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
28543   {
28544     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mov.b", 56,
28545     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28546   },
28547 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
28548   {
28549     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mov.b", 56,
28550     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28551   },
28552 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
28553   {
28554     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mov.b", 64,
28555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28556   },
28557 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
28558   {
28559     M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mov.b", 64,
28560     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28561   },
28562 /* mov.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
28563   {
28564     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 16,
28565     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28566   },
28567 /* mov.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
28568   {
28569     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 16,
28570     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28571   },
28572 /* mov.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
28573   {
28574     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 16,
28575     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28576   },
28577 /* mov.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
28578   {
28579     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 16,
28580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28581   },
28582 /* mov.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
28583   {
28584     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 16,
28585     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28586   },
28587 /* mov.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
28588   {
28589     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 16,
28590     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28591   },
28592 /* mov.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
28593   {
28594     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 16,
28595     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28596   },
28597 /* mov.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
28598   {
28599     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 16,
28600     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28601   },
28602 /* mov.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
28603   {
28604     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 16,
28605     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28606   },
28607 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
28608   {
28609     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 24,
28610     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28611   },
28612 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
28613   {
28614     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 24,
28615     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28616   },
28617 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
28618   {
28619     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 24,
28620     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28621   },
28622 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
28623   {
28624     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 32,
28625     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28626   },
28627 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
28628   {
28629     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 32,
28630     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28631   },
28632 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
28633   {
28634     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 32,
28635     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28636   },
28637 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
28638   {
28639     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 40,
28640     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28641   },
28642 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
28643   {
28644     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 40,
28645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28646   },
28647 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
28648   {
28649     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 40,
28650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28651   },
28652 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
28653   {
28654     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 24,
28655     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28656   },
28657 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
28658   {
28659     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 24,
28660     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28661   },
28662 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
28663   {
28664     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 24,
28665     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28666   },
28667 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
28668   {
28669     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 32,
28670     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28671   },
28672 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
28673   {
28674     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 32,
28675     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28676   },
28677 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
28678   {
28679     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 32,
28680     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28681   },
28682 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
28683   {
28684     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 24,
28685     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28686   },
28687 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
28688   {
28689     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 24,
28690     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28691   },
28692 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
28693   {
28694     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 24,
28695     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28696   },
28697 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
28698   {
28699     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 32,
28700     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28701   },
28702 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
28703   {
28704     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 32,
28705     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28706   },
28707 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
28708   {
28709     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 32,
28710     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28711   },
28712 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
28713   {
28714     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 32,
28715     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28716   },
28717 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
28718   {
28719     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 32,
28720     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28721   },
28722 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
28723   {
28724     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 32,
28725     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28726   },
28727 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
28728   {
28729     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 40,
28730     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28731   },
28732 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
28733   {
28734     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 40,
28735     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28736   },
28737 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
28738   {
28739     M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 40,
28740     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28741   },
28742 /* mov.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
28743   {
28744     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "mov.w", 24,
28745     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28746   },
28747 /* mov.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
28748   {
28749     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "mov.w", 24,
28750     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28751   },
28752 /* mov.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
28753   {
28754     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "mov.w", 24,
28755     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28756   },
28757 /* mov.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
28758   {
28759     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "mov.w", 24,
28760     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28761   },
28762 /* mov.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
28763   {
28764     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "mov.w", 24,
28765     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28766   },
28767 /* mov.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
28768   {
28769     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "mov.w", 24,
28770     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28771   },
28772 /* mov.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
28773   {
28774     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "mov.w", 24,
28775     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28776   },
28777 /* mov.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
28778   {
28779     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "mov.w", 24,
28780     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28781   },
28782 /* mov.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
28783   {
28784     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "mov.w", 24,
28785     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28786   },
28787 /* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
28788   {
28789     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "mov.w", 32,
28790     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28791   },
28792 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
28793   {
28794     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "mov.w", 32,
28795     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28796   },
28797 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
28798   {
28799     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "mov.w", 32,
28800     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28801   },
28802 /* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
28803   {
28804     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "mov.w", 40,
28805     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28806   },
28807 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
28808   {
28809     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "mov.w", 40,
28810     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28811   },
28812 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
28813   {
28814     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "mov.w", 40,
28815     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28816   },
28817 /* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
28818   {
28819     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "mov.w", 32,
28820     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28821   },
28822 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
28823   {
28824     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "mov.w", 32,
28825     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28826   },
28827 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
28828   {
28829     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "mov.w", 32,
28830     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28831   },
28832 /* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
28833   {
28834     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "mov.w", 40,
28835     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28836   },
28837 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
28838   {
28839     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "mov.w", 40,
28840     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28841   },
28842 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
28843   {
28844     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "mov.w", 40,
28845     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28846   },
28847 /* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
28848   {
28849     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "mov.w", 32,
28850     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28851   },
28852 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
28853   {
28854     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "mov.w", 32,
28855     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28856   },
28857 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
28858   {
28859     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "mov.w", 32,
28860     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28861   },
28862 /* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
28863   {
28864     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "mov.w", 40,
28865     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28866   },
28867 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
28868   {
28869     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "mov.w", 40,
28870     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28871   },
28872 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
28873   {
28874     M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "mov.w", 40,
28875     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28876   },
28877 /* mov.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
28878   {
28879     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "mov.w", 32,
28880     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28881   },
28882 /* mov.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
28883   {
28884     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "mov.w", 32,
28885     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28886   },
28887 /* mov.w${G} ${Dsp-16-u16},$Dst16RnHI */
28888   {
28889     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "mov.w", 32,
28890     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28891   },
28892 /* mov.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
28893   {
28894     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "mov.w", 32,
28895     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28896   },
28897 /* mov.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
28898   {
28899     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "mov.w", 32,
28900     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28901   },
28902 /* mov.w${G} ${Dsp-16-u16},$Dst16AnHI */
28903   {
28904     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "mov.w", 32,
28905     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28906   },
28907 /* mov.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
28908   {
28909     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "mov.w", 32,
28910     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28911   },
28912 /* mov.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
28913   {
28914     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "mov.w", 32,
28915     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28916   },
28917 /* mov.w${G} ${Dsp-16-u16},[$Dst16An] */
28918   {
28919     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "mov.w", 32,
28920     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28921   },
28922 /* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
28923   {
28924     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "mov.w", 40,
28925     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28926   },
28927 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
28928   {
28929     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "mov.w", 40,
28930     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28931   },
28932 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
28933   {
28934     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "mov.w", 40,
28935     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28936   },
28937 /* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
28938   {
28939     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "mov.w", 48,
28940     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28941   },
28942 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
28943   {
28944     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "mov.w", 48,
28945     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28946   },
28947 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
28948   {
28949     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "mov.w", 48,
28950     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28951   },
28952 /* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
28953   {
28954     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "mov.w", 40,
28955     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28956   },
28957 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
28958   {
28959     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "mov.w", 40,
28960     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28961   },
28962 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
28963   {
28964     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "mov.w", 40,
28965     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28966   },
28967 /* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
28968   {
28969     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "mov.w", 48,
28970     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28971   },
28972 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
28973   {
28974     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "mov.w", 48,
28975     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28976   },
28977 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
28978   {
28979     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "mov.w", 48,
28980     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28981   },
28982 /* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
28983   {
28984     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "mov.w", 40,
28985     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28986   },
28987 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
28988   {
28989     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "mov.w", 40,
28990     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28991   },
28992 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
28993   {
28994     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "mov.w", 40,
28995     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28996   },
28997 /* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
28998   {
28999     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "mov.w", 48,
29000     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29001   },
29002 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
29003   {
29004     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "mov.w", 48,
29005     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29006   },
29007 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
29008   {
29009     M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "mov.w", 48,
29010     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29011   },
29012 /* mov.w${G} $Src16RnHI,$Dst16RnHI */
29013   {
29014     M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "mov.w", 16,
29015     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29016   },
29017 /* mov.w${G} $Src16AnHI,$Dst16RnHI */
29018   {
29019     M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "mov.w", 16,
29020     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29021   },
29022 /* mov.w${G} [$Src16An],$Dst16RnHI */
29023   {
29024     M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "mov.w", 16,
29025     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29026   },
29027 /* mov.w${G} $Src16RnHI,$Dst16AnHI */
29028   {
29029     M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "mov.w", 16,
29030     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29031   },
29032 /* mov.w${G} $Src16AnHI,$Dst16AnHI */
29033   {
29034     M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "mov.w", 16,
29035     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29036   },
29037 /* mov.w${G} [$Src16An],$Dst16AnHI */
29038   {
29039     M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "mov.w", 16,
29040     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29041   },
29042 /* mov.w${G} $Src16RnHI,[$Dst16An] */
29043   {
29044     M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "mov.w", 16,
29045     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29046   },
29047 /* mov.w${G} $Src16AnHI,[$Dst16An] */
29048   {
29049     M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "mov.w", 16,
29050     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29051   },
29052 /* mov.w${G} [$Src16An],[$Dst16An] */
29053   {
29054     M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "mov.w", 16,
29055     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29056   },
29057 /* mov.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
29058   {
29059     M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "mov.w", 24,
29060     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29061   },
29062 /* mov.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
29063   {
29064     M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "mov.w", 24,
29065     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29066   },
29067 /* mov.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
29068   {
29069     M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "mov.w", 24,
29070     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29071   },
29072 /* mov.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
29073   {
29074     M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "mov.w", 32,
29075     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29076   },
29077 /* mov.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
29078   {
29079     M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "mov.w", 32,
29080     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29081   },
29082 /* mov.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
29083   {
29084     M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "mov.w", 32,
29085     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29086   },
29087 /* mov.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
29088   {
29089     M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "mov.w", 24,
29090     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29091   },
29092 /* mov.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
29093   {
29094     M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "mov.w", 24,
29095     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29096   },
29097 /* mov.w${G} [$Src16An],${Dsp-16-u8}[sb] */
29098   {
29099     M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "mov.w", 24,
29100     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29101   },
29102 /* mov.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
29103   {
29104     M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "mov.w", 32,
29105     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29106   },
29107 /* mov.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
29108   {
29109     M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "mov.w", 32,
29110     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29111   },
29112 /* mov.w${G} [$Src16An],${Dsp-16-u16}[sb] */
29113   {
29114     M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "mov.w", 32,
29115     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29116   },
29117 /* mov.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
29118   {
29119     M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "mov.w", 24,
29120     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29121   },
29122 /* mov.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
29123   {
29124     M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "mov.w", 24,
29125     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29126   },
29127 /* mov.w${G} [$Src16An],${Dsp-16-s8}[fb] */
29128   {
29129     M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "mov.w", 24,
29130     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29131   },
29132 /* mov.w${G} $Src16RnHI,${Dsp-16-u16} */
29133   {
29134     M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "mov.w", 32,
29135     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29136   },
29137 /* mov.w${G} $Src16AnHI,${Dsp-16-u16} */
29138   {
29139     M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "mov.w", 32,
29140     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29141   },
29142 /* mov.w${G} [$Src16An],${Dsp-16-u16} */
29143   {
29144     M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "mov.w", 32,
29145     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29146   },
29147 /* mov.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
29148   {
29149     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "mov.b", 24,
29150     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29151   },
29152 /* mov.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
29153   {
29154     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "mov.b", 24,
29155     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29156   },
29157 /* mov.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
29158   {
29159     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "mov.b", 24,
29160     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29161   },
29162 /* mov.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
29163   {
29164     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "mov.b", 24,
29165     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29166   },
29167 /* mov.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
29168   {
29169     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "mov.b", 24,
29170     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29171   },
29172 /* mov.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
29173   {
29174     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "mov.b", 24,
29175     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29176   },
29177 /* mov.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
29178   {
29179     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "mov.b", 24,
29180     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29181   },
29182 /* mov.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
29183   {
29184     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "mov.b", 24,
29185     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29186   },
29187 /* mov.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
29188   {
29189     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "mov.b", 24,
29190     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29191   },
29192 /* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
29193   {
29194     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "mov.b", 32,
29195     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29196   },
29197 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
29198   {
29199     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "mov.b", 32,
29200     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29201   },
29202 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
29203   {
29204     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "mov.b", 32,
29205     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29206   },
29207 /* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
29208   {
29209     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "mov.b", 40,
29210     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29211   },
29212 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
29213   {
29214     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "mov.b", 40,
29215     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29216   },
29217 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
29218   {
29219     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "mov.b", 40,
29220     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29221   },
29222 /* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
29223   {
29224     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "mov.b", 32,
29225     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29226   },
29227 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
29228   {
29229     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "mov.b", 32,
29230     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29231   },
29232 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
29233   {
29234     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "mov.b", 32,
29235     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29236   },
29237 /* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
29238   {
29239     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "mov.b", 40,
29240     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29241   },
29242 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
29243   {
29244     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "mov.b", 40,
29245     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29246   },
29247 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
29248   {
29249     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "mov.b", 40,
29250     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29251   },
29252 /* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
29253   {
29254     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "mov.b", 32,
29255     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29256   },
29257 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
29258   {
29259     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "mov.b", 32,
29260     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29261   },
29262 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
29263   {
29264     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "mov.b", 32,
29265     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29266   },
29267 /* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
29268   {
29269     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "mov.b", 40,
29270     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29271   },
29272 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
29273   {
29274     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "mov.b", 40,
29275     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29276   },
29277 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
29278   {
29279     M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "mov.b", 40,
29280     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29281   },
29282 /* mov.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
29283   {
29284     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "mov.b", 32,
29285     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29286   },
29287 /* mov.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
29288   {
29289     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "mov.b", 32,
29290     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29291   },
29292 /* mov.b${G} ${Dsp-16-u16},$Dst16RnQI */
29293   {
29294     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "mov.b", 32,
29295     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29296   },
29297 /* mov.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
29298   {
29299     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "mov.b", 32,
29300     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29301   },
29302 /* mov.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
29303   {
29304     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "mov.b", 32,
29305     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29306   },
29307 /* mov.b${G} ${Dsp-16-u16},$Dst16AnQI */
29308   {
29309     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "mov.b", 32,
29310     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29311   },
29312 /* mov.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
29313   {
29314     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "mov.b", 32,
29315     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29316   },
29317 /* mov.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
29318   {
29319     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "mov.b", 32,
29320     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29321   },
29322 /* mov.b${G} ${Dsp-16-u16},[$Dst16An] */
29323   {
29324     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "mov.b", 32,
29325     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29326   },
29327 /* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
29328   {
29329     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "mov.b", 40,
29330     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29331   },
29332 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
29333   {
29334     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "mov.b", 40,
29335     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29336   },
29337 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
29338   {
29339     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "mov.b", 40,
29340     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29341   },
29342 /* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
29343   {
29344     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "mov.b", 48,
29345     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29346   },
29347 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
29348   {
29349     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "mov.b", 48,
29350     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29351   },
29352 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
29353   {
29354     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "mov.b", 48,
29355     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29356   },
29357 /* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
29358   {
29359     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "mov.b", 40,
29360     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29361   },
29362 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
29363   {
29364     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "mov.b", 40,
29365     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29366   },
29367 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
29368   {
29369     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "mov.b", 40,
29370     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29371   },
29372 /* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
29373   {
29374     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "mov.b", 48,
29375     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29376   },
29377 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
29378   {
29379     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "mov.b", 48,
29380     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29381   },
29382 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
29383   {
29384     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "mov.b", 48,
29385     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29386   },
29387 /* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
29388   {
29389     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "mov.b", 40,
29390     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29391   },
29392 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
29393   {
29394     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "mov.b", 40,
29395     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29396   },
29397 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
29398   {
29399     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "mov.b", 40,
29400     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29401   },
29402 /* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
29403   {
29404     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "mov.b", 48,
29405     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29406   },
29407 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
29408   {
29409     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "mov.b", 48,
29410     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29411   },
29412 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
29413   {
29414     M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "mov.b", 48,
29415     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29416   },
29417 /* mov.b${G} $Src16RnQI,$Dst16RnQI */
29418   {
29419     M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "mov.b", 16,
29420     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29421   },
29422 /* mov.b${G} $Src16AnQI,$Dst16RnQI */
29423   {
29424     M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "mov.b", 16,
29425     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29426   },
29427 /* mov.b${G} [$Src16An],$Dst16RnQI */
29428   {
29429     M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "mov.b", 16,
29430     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29431   },
29432 /* mov.b${G} $Src16RnQI,$Dst16AnQI */
29433   {
29434     M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "mov.b", 16,
29435     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29436   },
29437 /* mov.b${G} $Src16AnQI,$Dst16AnQI */
29438   {
29439     M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "mov.b", 16,
29440     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29441   },
29442 /* mov.b${G} [$Src16An],$Dst16AnQI */
29443   {
29444     M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "mov.b", 16,
29445     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29446   },
29447 /* mov.b${G} $Src16RnQI,[$Dst16An] */
29448   {
29449     M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "mov.b", 16,
29450     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29451   },
29452 /* mov.b${G} $Src16AnQI,[$Dst16An] */
29453   {
29454     M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "mov.b", 16,
29455     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29456   },
29457 /* mov.b${G} [$Src16An],[$Dst16An] */
29458   {
29459     M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "mov.b", 16,
29460     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29461   },
29462 /* mov.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
29463   {
29464     M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "mov.b", 24,
29465     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29466   },
29467 /* mov.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
29468   {
29469     M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "mov.b", 24,
29470     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29471   },
29472 /* mov.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
29473   {
29474     M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "mov.b", 24,
29475     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29476   },
29477 /* mov.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
29478   {
29479     M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "mov.b", 32,
29480     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29481   },
29482 /* mov.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
29483   {
29484     M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "mov.b", 32,
29485     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29486   },
29487 /* mov.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
29488   {
29489     M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "mov.b", 32,
29490     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29491   },
29492 /* mov.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
29493   {
29494     M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "mov.b", 24,
29495     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29496   },
29497 /* mov.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
29498   {
29499     M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "mov.b", 24,
29500     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29501   },
29502 /* mov.b${G} [$Src16An],${Dsp-16-u8}[sb] */
29503   {
29504     M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "mov.b", 24,
29505     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29506   },
29507 /* mov.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
29508   {
29509     M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "mov.b", 32,
29510     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29511   },
29512 /* mov.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
29513   {
29514     M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "mov.b", 32,
29515     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29516   },
29517 /* mov.b${G} [$Src16An],${Dsp-16-u16}[sb] */
29518   {
29519     M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "mov.b", 32,
29520     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29521   },
29522 /* mov.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
29523   {
29524     M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "mov.b", 24,
29525     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29526   },
29527 /* mov.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
29528   {
29529     M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "mov.b", 24,
29530     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29531   },
29532 /* mov.b${G} [$Src16An],${Dsp-16-s8}[fb] */
29533   {
29534     M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "mov.b", 24,
29535     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29536   },
29537 /* mov.b${G} $Src16RnQI,${Dsp-16-u16} */
29538   {
29539     M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "mov.b", 32,
29540     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29541   },
29542 /* mov.b${G} $Src16AnQI,${Dsp-16-u16} */
29543   {
29544     M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "mov.b", 32,
29545     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29546   },
29547 /* mov.b${G} [$Src16An],${Dsp-16-u16} */
29548   {
29549     M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "mov.b", 32,
29550     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29551   },
29552 /* mov.w${Z} #0,${Dsp-8-u8}[sb] */
29553   {
29554     M32C_INSN_MOV32_W_IMM_Z_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-imm-Z-2-S-8-dst32-2-S-8-SB-relative-HI", "mov.w", 16,
29555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29556   },
29557 /* mov.w${Z} #0,${Dsp-8-s8}[fb] */
29558   {
29559     M32C_INSN_MOV32_W_IMM_Z_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-imm-Z-2-S-8-dst32-2-S-8-FB-relative-HI", "mov.w", 16,
29560     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29561   },
29562 /* mov.w${Z} #0,${Dsp-8-u16} */
29563   {
29564     M32C_INSN_MOV32_W_IMM_Z_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-imm-Z-2-S-16-dst32-2-S-16-absolute-HI", "mov.w", 24,
29565     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29566   },
29567 /* mov.w${Z} #0,r0 */
29568   {
29569     M32C_INSN_MOV32_W_IMM_Z_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "mov32.w-imm-Z-2-S-basic-dst32-2-S-R0-direct-HI", "mov.w", 8,
29570     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29571   },
29572 /* mov.b${Z} #0,${Dsp-8-u8}[sb] */
29573   {
29574     M32C_INSN_MOV32_B_IMM_Z_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-imm-Z-2-S-8-dst32-2-S-8-SB-relative-QI", "mov.b", 16,
29575     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29576   },
29577 /* mov.b${Z} #0,${Dsp-8-s8}[fb] */
29578   {
29579     M32C_INSN_MOV32_B_IMM_Z_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-imm-Z-2-S-8-dst32-2-S-8-FB-relative-QI", "mov.b", 16,
29580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29581   },
29582 /* mov.b${Z} #0,${Dsp-8-u16} */
29583   {
29584     M32C_INSN_MOV32_B_IMM_Z_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-imm-Z-2-S-16-dst32-2-S-16-absolute-QI", "mov.b", 24,
29585     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29586   },
29587 /* mov.b${Z} #0,r0l */
29588   {
29589     M32C_INSN_MOV32_B_IMM_Z_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "mov32.b-imm-Z-2-S-basic-dst32-2-S-R0l-direct-QI", "mov.b", 8,
29590     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29591   },
29592 /* mov.b${Z} #0,r0l */
29593   {
29594     M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-R0l-direct-QI", "mov.b", 8,
29595     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29596   },
29597 /* mov.b${Z} #0,r0h */
29598   {
29599     M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-R0h-direct-QI", "mov.b", 8,
29600     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29601   },
29602 /* mov.b${Z} #0,${Dsp-8-u8}[sb] */
29603   {
29604     M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_8_SB_RELATIVE_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-8-8-SB-relative-QI", "mov.b", 16,
29605     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29606   },
29607 /* mov.b${Z} #0,${Dsp-8-s8}[fb] */
29608   {
29609     M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_8_FB_RELATIVE_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-8-8-FB-relative-QI", "mov.b", 16,
29610     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29611   },
29612 /* mov.b${Z} #0,${Dsp-8-u16} */
29613   {
29614     M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_16_ABSOLUTE_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-8-16-absolute-QI", "mov.b", 24,
29615     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29616   },
29617 /* mov.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */
29618   {
29619     M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mov.w", 16,
29620     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29621   },
29622 /* mov.w${Q} #${Imm-12-s4},$Dst32AnUnprefixedHI */
29623   {
29624     M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "mov.w", 16,
29625     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29626   },
29627 /* mov.w${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
29628   {
29629     M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mov.w", 16,
29630     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29631   },
29632 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
29633   {
29634     M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 24,
29635     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29636   },
29637 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
29638   {
29639     M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 32,
29640     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29641   },
29642 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
29643   {
29644     M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 40,
29645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29646   },
29647 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
29648   {
29649     M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 24,
29650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29651   },
29652 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
29653   {
29654     M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 32,
29655     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29656   },
29657 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
29658   {
29659     M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 24,
29660     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29661   },
29662 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
29663   {
29664     M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 32,
29665     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29666   },
29667 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u16} */
29668   {
29669     M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 32,
29670     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29671   },
29672 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u24} */
29673   {
29674     M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 40,
29675     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29676   },
29677 /* mov.b${Q} #${Imm-12-s4},$Dst32RnUnprefixedQI */
29678   {
29679     M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mov.b", 16,
29680     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29681   },
29682 /* mov.b${Q} #${Imm-12-s4},$Dst32AnUnprefixedQI */
29683   {
29684     M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "mov.b", 16,
29685     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29686   },
29687 /* mov.b${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
29688   {
29689     M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mov.b", 16,
29690     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29691   },
29692 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
29693   {
29694     M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 24,
29695     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29696   },
29697 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
29698   {
29699     M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 32,
29700     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29701   },
29702 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
29703   {
29704     M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 40,
29705     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29706   },
29707 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
29708   {
29709     M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 24,
29710     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29711   },
29712 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
29713   {
29714     M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 32,
29715     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29716   },
29717 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
29718   {
29719     M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 24,
29720     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29721   },
29722 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
29723   {
29724     M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 32,
29725     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29726   },
29727 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u16} */
29728   {
29729     M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 32,
29730     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29731   },
29732 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u24} */
29733   {
29734     M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 40,
29735     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29736   },
29737 /* mov.w${Q} #${Imm-8-s4},$Dst16RnQI */
29738   {
29739     M32C_INSN_MOV16_W_IMM4_Q_16_DST16_RN_DIRECT_QI, "mov16.w-imm4-Q-16-dst16-Rn-direct-QI", "mov.w", 16,
29740     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29741   },
29742 /* mov.w${Q} #${Imm-8-s4},$Dst16AnQI */
29743   {
29744     M32C_INSN_MOV16_W_IMM4_Q_16_DST16_AN_DIRECT_QI, "mov16.w-imm4-Q-16-dst16-An-direct-QI", "mov.w", 16,
29745     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29746   },
29747 /* mov.w${Q} #${Imm-8-s4},[$Dst16An] */
29748   {
29749     M32C_INSN_MOV16_W_IMM4_Q_16_DST16_AN_INDIRECT_QI, "mov16.w-imm4-Q-16-dst16-An-indirect-QI", "mov.w", 16,
29750     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29751   },
29752 /* mov.w${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
29753   {
29754     M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "mov16.w-imm4-Q-16-dst16-16-8-An-relative-QI", "mov.w", 24,
29755     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29756   },
29757 /* mov.w${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
29758   {
29759     M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "mov16.w-imm4-Q-16-dst16-16-16-An-relative-QI", "mov.w", 32,
29760     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29761   },
29762 /* mov.w${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
29763   {
29764     M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "mov16.w-imm4-Q-16-dst16-16-8-SB-relative-QI", "mov.w", 24,
29765     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29766   },
29767 /* mov.w${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
29768   {
29769     M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "mov16.w-imm4-Q-16-dst16-16-16-SB-relative-QI", "mov.w", 32,
29770     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29771   },
29772 /* mov.w${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
29773   {
29774     M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "mov16.w-imm4-Q-16-dst16-16-8-FB-relative-QI", "mov.w", 24,
29775     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29776   },
29777 /* mov.w${Q} #${Imm-8-s4},${Dsp-16-u16} */
29778   {
29779     M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "mov16.w-imm4-Q-16-dst16-16-16-absolute-QI", "mov.w", 32,
29780     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29781   },
29782 /* mov.b${Q} #${Imm-8-s4},$Dst16RnQI */
29783   {
29784     M32C_INSN_MOV16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "mov16.b-imm4-Q-16-dst16-Rn-direct-QI", "mov.b", 16,
29785     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29786   },
29787 /* mov.b${Q} #${Imm-8-s4},$Dst16AnQI */
29788   {
29789     M32C_INSN_MOV16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "mov16.b-imm4-Q-16-dst16-An-direct-QI", "mov.b", 16,
29790     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29791   },
29792 /* mov.b${Q} #${Imm-8-s4},[$Dst16An] */
29793   {
29794     M32C_INSN_MOV16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "mov16.b-imm4-Q-16-dst16-An-indirect-QI", "mov.b", 16,
29795     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29796   },
29797 /* mov.b${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
29798   {
29799     M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "mov.b", 24,
29800     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29801   },
29802 /* mov.b${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
29803   {
29804     M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "mov.b", 32,
29805     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29806   },
29807 /* mov.b${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
29808   {
29809     M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "mov.b", 24,
29810     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29811   },
29812 /* mov.b${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
29813   {
29814     M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "mov.b", 32,
29815     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29816   },
29817 /* mov.b${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
29818   {
29819     M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "mov.b", 24,
29820     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29821   },
29822 /* mov.b${Q} #${Imm-8-s4},${Dsp-16-u16} */
29823   {
29824     M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "mov16.b-imm4-Q-16-dst16-16-16-absolute-QI", "mov.b", 32,
29825     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29826   },
29827 /* mov.b${S} #${Imm-8-QI},r0l */
29828   {
29829     M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "mov16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "mov.b", 16,
29830     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29831   },
29832 /* mov.b${S} #${Imm-8-QI},r0h */
29833   {
29834     M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "mov16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "mov.b", 16,
29835     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29836   },
29837 /* mov.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
29838   {
29839     M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "mov16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "mov.b", 24,
29840     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29841   },
29842 /* mov.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
29843   {
29844     M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "mov16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "mov.b", 24,
29845     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29846   },
29847 /* mov.b${S} #${Imm-8-QI},${Dsp-16-u16} */
29848   {
29849     M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "mov16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "mov.b", 32,
29850     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29851   },
29852 /* mov.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
29853   {
29854     M32C_INSN_MOV32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "mov.w", 32,
29855     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29856   },
29857 /* mov.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
29858   {
29859     M32C_INSN_MOV32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "mov.w", 32,
29860     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29861   },
29862 /* mov.w${S} #${Imm-24-HI},${Dsp-8-u16} */
29863   {
29864     M32C_INSN_MOV32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "mov.w", 40,
29865     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29866   },
29867 /* mov.w${S} #${Imm-8-HI},r0 */
29868   {
29869     M32C_INSN_MOV32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "mov32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "mov.w", 24,
29870     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29871   },
29872 /* mov.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
29873   {
29874     M32C_INSN_MOV32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "mov.b", 24,
29875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29876   },
29877 /* mov.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
29878   {
29879     M32C_INSN_MOV32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "mov.b", 24,
29880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29881   },
29882 /* mov.b${S} #${Imm-24-QI},${Dsp-8-u16} */
29883   {
29884     M32C_INSN_MOV32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "mov.b", 32,
29885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29886   },
29887 /* mov.b${S} #${Imm-8-QI},r0l */
29888   {
29889     M32C_INSN_MOV32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "mov32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "mov.b", 16,
29890     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29891   },
29892 /* mov.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */
29893   {
29894     M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "mov.l", 48,
29895     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29896   },
29897 /* mov.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */
29898   {
29899     M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "mov.l", 48,
29900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29901   },
29902 /* mov.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */
29903   {
29904     M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "mov.l", 48,
29905     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29906   },
29907 /* mov.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
29908   {
29909     M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "mov.l", 56,
29910     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29911   },
29912 /* mov.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */
29913   {
29914     M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "mov.l", 56,
29915     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29916   },
29917 /* mov.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */
29918   {
29919     M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "mov.l", 56,
29920     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29921   },
29922 /* mov.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
29923   {
29924     M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "mov.l", 64,
29925     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29926   },
29927 /* mov.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */
29928   {
29929     M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "mov.l", 64,
29930     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29931   },
29932 /* mov.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */
29933   {
29934     M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "mov.l", 64,
29935     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29936   },
29937 /* mov.l${G} #${Imm-32-SI},${Dsp-16-u16} */
29938   {
29939     M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "mov.l", 64,
29940     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29941   },
29942 /* mov.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
29943   {
29944     M32C_INSN_MOV32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "mov.l", 72,
29945     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29946   },
29947 /* mov.l${G} #${Imm-40-SI},${Dsp-16-u24} */
29948   {
29949     M32C_INSN_MOV32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "mov.l", 72,
29950     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29951   },
29952 /* mov.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
29953   {
29954     M32C_INSN_MOV32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32,
29955     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29956   },
29957 /* mov.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
29958   {
29959     M32C_INSN_MOV32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mov.w", 32,
29960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29961   },
29962 /* mov.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
29963   {
29964     M32C_INSN_MOV32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mov.w", 32,
29965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29966   },
29967 /* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
29968   {
29969     M32C_INSN_MOV32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 40,
29970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29971   },
29972 /* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
29973   {
29974     M32C_INSN_MOV32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 40,
29975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29976   },
29977 /* mov.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
29978   {
29979     M32C_INSN_MOV32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 40,
29980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29981   },
29982 /* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
29983   {
29984     M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 48,
29985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29986   },
29987 /* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
29988   {
29989     M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 48,
29990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29991   },
29992 /* mov.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
29993   {
29994     M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 48,
29995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29996   },
29997 /* mov.w${G} #${Imm-32-HI},${Dsp-16-u16} */
29998   {
29999     M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 48,
30000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30001   },
30002 /* mov.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
30003   {
30004     M32C_INSN_MOV32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 56,
30005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30006   },
30007 /* mov.w${G} #${Imm-40-HI},${Dsp-16-u24} */
30008   {
30009     M32C_INSN_MOV32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 56,
30010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30011   },
30012 /* mov.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
30013   {
30014     M32C_INSN_MOV32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24,
30015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30016   },
30017 /* mov.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
30018   {
30019     M32C_INSN_MOV32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mov.b", 24,
30020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30021   },
30022 /* mov.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
30023   {
30024     M32C_INSN_MOV32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mov.b", 24,
30025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30026   },
30027 /* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
30028   {
30029     M32C_INSN_MOV32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 32,
30030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30031   },
30032 /* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
30033   {
30034     M32C_INSN_MOV32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 32,
30035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30036   },
30037 /* mov.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
30038   {
30039     M32C_INSN_MOV32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 32,
30040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30041   },
30042 /* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
30043   {
30044     M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 40,
30045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30046   },
30047 /* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
30048   {
30049     M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 40,
30050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30051   },
30052 /* mov.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
30053   {
30054     M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 40,
30055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30056   },
30057 /* mov.b${G} #${Imm-32-QI},${Dsp-16-u16} */
30058   {
30059     M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 40,
30060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30061   },
30062 /* mov.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
30063   {
30064     M32C_INSN_MOV32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 48,
30065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30066   },
30067 /* mov.b${G} #${Imm-40-QI},${Dsp-16-u24} */
30068   {
30069     M32C_INSN_MOV32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 48,
30070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30071   },
30072 /* mov.w${G} #${Imm-16-HI},$Dst16RnHI */
30073   {
30074     M32C_INSN_MOV16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "mov16.w-imm-G-basic-dst16-Rn-direct-HI", "mov.w", 32,
30075     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30076   },
30077 /* mov.w${G} #${Imm-16-HI},$Dst16AnHI */
30078   {
30079     M32C_INSN_MOV16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "mov16.w-imm-G-basic-dst16-An-direct-HI", "mov.w", 32,
30080     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30081   },
30082 /* mov.w${G} #${Imm-16-HI},[$Dst16An] */
30083   {
30084     M32C_INSN_MOV16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "mov16.w-imm-G-basic-dst16-An-indirect-HI", "mov.w", 32,
30085     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30086   },
30087 /* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
30088   {
30089     M32C_INSN_MOV16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "mov16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "mov.w", 40,
30090     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30091   },
30092 /* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
30093   {
30094     M32C_INSN_MOV16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "mov16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "mov.w", 40,
30095     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30096   },
30097 /* mov.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
30098   {
30099     M32C_INSN_MOV16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "mov16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "mov.w", 40,
30100     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30101   },
30102 /* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
30103   {
30104     M32C_INSN_MOV16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "mov16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "mov.w", 48,
30105     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30106   },
30107 /* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
30108   {
30109     M32C_INSN_MOV16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "mov16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "mov.w", 48,
30110     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30111   },
30112 /* mov.w${G} #${Imm-32-HI},${Dsp-16-u16} */
30113   {
30114     M32C_INSN_MOV16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "mov16.w-imm-G-16-16-dst16-16-16-absolute-HI", "mov.w", 48,
30115     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30116   },
30117 /* mov.b${G} #${Imm-16-QI},$Dst16RnQI */
30118   {
30119     M32C_INSN_MOV16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "mov16.b-imm-G-basic-dst16-Rn-direct-QI", "mov.b", 24,
30120     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30121   },
30122 /* mov.b${G} #${Imm-16-QI},$Dst16AnQI */
30123   {
30124     M32C_INSN_MOV16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "mov16.b-imm-G-basic-dst16-An-direct-QI", "mov.b", 24,
30125     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30126   },
30127 /* mov.b${G} #${Imm-16-QI},[$Dst16An] */
30128   {
30129     M32C_INSN_MOV16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "mov16.b-imm-G-basic-dst16-An-indirect-QI", "mov.b", 24,
30130     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30131   },
30132 /* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
30133   {
30134     M32C_INSN_MOV16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "mov16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "mov.b", 32,
30135     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30136   },
30137 /* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
30138   {
30139     M32C_INSN_MOV16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "mov16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "mov.b", 32,
30140     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30141   },
30142 /* mov.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
30143   {
30144     M32C_INSN_MOV16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "mov16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "mov.b", 32,
30145     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30146   },
30147 /* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
30148   {
30149     M32C_INSN_MOV16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "mov16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "mov.b", 40,
30150     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30151   },
30152 /* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
30153   {
30154     M32C_INSN_MOV16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "mov16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "mov.b", 40,
30155     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30156   },
30157 /* mov.b${G} #${Imm-32-QI},${Dsp-16-u16} */
30158   {
30159     M32C_INSN_MOV16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "mov16.b-imm-G-16-16-dst16-16-16-absolute-QI", "mov.b", 40,
30160     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30161   },
30162 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
30163   {
30164     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 32,
30165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30166   },
30167 /* min.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
30168   {
30169     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 32,
30170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30171   },
30172 /* min.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
30173   {
30174     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 32,
30175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30176   },
30177 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
30178   {
30179     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 32,
30180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30181   },
30182 /* min.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
30183   {
30184     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 32,
30185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30186   },
30187 /* min.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
30188   {
30189     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 32,
30190     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30191   },
30192 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
30193   {
30194     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 32,
30195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30196   },
30197 /* min.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
30198   {
30199     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 32,
30200     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30201   },
30202 /* min.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
30203   {
30204     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 32,
30205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30206   },
30207 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
30208   {
30209     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "min.w", 40,
30210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30211   },
30212 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
30213   {
30214     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "min.w", 40,
30215     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30216   },
30217 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
30218   {
30219     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "min.w", 40,
30220     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30221   },
30222 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
30223   {
30224     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "min.w", 48,
30225     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30226   },
30227 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
30228   {
30229     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "min.w", 48,
30230     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30231   },
30232 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
30233   {
30234     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "min.w", 48,
30235     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30236   },
30237 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
30238   {
30239     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "min.w", 56,
30240     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30241   },
30242 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
30243   {
30244     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "min.w", 56,
30245     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30246   },
30247 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
30248   {
30249     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "min.w", 56,
30250     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30251   },
30252 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
30253   {
30254     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "min.w", 40,
30255     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30256   },
30257 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
30258   {
30259     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "min.w", 40,
30260     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30261   },
30262 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
30263   {
30264     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "min.w", 40,
30265     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30266   },
30267 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
30268   {
30269     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "min.w", 48,
30270     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30271   },
30272 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
30273   {
30274     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "min.w", 48,
30275     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30276   },
30277 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
30278   {
30279     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "min.w", 48,
30280     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30281   },
30282 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
30283   {
30284     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "min.w", 40,
30285     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30286   },
30287 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
30288   {
30289     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "min.w", 40,
30290     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30291   },
30292 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
30293   {
30294     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "min.w", 40,
30295     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30296   },
30297 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
30298   {
30299     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "min.w", 48,
30300     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30301   },
30302 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
30303   {
30304     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "min.w", 48,
30305     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30306   },
30307 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
30308   {
30309     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "min.w", 48,
30310     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30311   },
30312 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
30313   {
30314     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "min.w", 48,
30315     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30316   },
30317 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
30318   {
30319     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "min.w", 48,
30320     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30321   },
30322 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
30323   {
30324     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "min.w", 48,
30325     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30326   },
30327 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
30328   {
30329     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "min.w", 56,
30330     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30331   },
30332 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
30333   {
30334     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "min.w", 56,
30335     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30336   },
30337 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
30338   {
30339     M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "min.w", 56,
30340     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30341   },
30342 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
30343   {
30344     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 40,
30345     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30346   },
30347 /* min.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
30348   {
30349     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 40,
30350     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30351   },
30352 /* min.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
30353   {
30354     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 40,
30355     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30356   },
30357 /* min.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
30358   {
30359     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 40,
30360     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30361   },
30362 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
30363   {
30364     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 40,
30365     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30366   },
30367 /* min.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
30368   {
30369     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 40,
30370     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30371   },
30372 /* min.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
30373   {
30374     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 40,
30375     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30376   },
30377 /* min.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
30378   {
30379     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 40,
30380     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30381   },
30382 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
30383   {
30384     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 40,
30385     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30386   },
30387 /* min.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
30388   {
30389     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 40,
30390     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30391   },
30392 /* min.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
30393   {
30394     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 40,
30395     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30396   },
30397 /* min.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
30398   {
30399     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 40,
30400     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30401   },
30402 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
30403   {
30404     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "min.w", 48,
30405     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30406   },
30407 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
30408   {
30409     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "min.w", 48,
30410     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30411   },
30412 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
30413   {
30414     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "min.w", 48,
30415     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30416   },
30417 /* min.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
30418   {
30419     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "min.w", 48,
30420     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30421   },
30422 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
30423   {
30424     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "min.w", 56,
30425     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30426   },
30427 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
30428   {
30429     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "min.w", 56,
30430     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30431   },
30432 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
30433   {
30434     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "min.w", 56,
30435     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30436   },
30437 /* min.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
30438   {
30439     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "min.w", 56,
30440     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30441   },
30442 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
30443   {
30444     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "min.w", 64,
30445     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30446   },
30447 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
30448   {
30449     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "min.w", 64,
30450     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30451   },
30452 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
30453   {
30454     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "min.w", 64,
30455     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30456   },
30457 /* min.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
30458   {
30459     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "min.w", 64,
30460     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30461   },
30462 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
30463   {
30464     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "min.w", 48,
30465     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30466   },
30467 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
30468   {
30469     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "min.w", 48,
30470     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30471   },
30472 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
30473   {
30474     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "min.w", 48,
30475     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30476   },
30477 /* min.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
30478   {
30479     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "min.w", 48,
30480     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30481   },
30482 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
30483   {
30484     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "min.w", 56,
30485     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30486   },
30487 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
30488   {
30489     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "min.w", 56,
30490     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30491   },
30492 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
30493   {
30494     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "min.w", 56,
30495     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30496   },
30497 /* min.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
30498   {
30499     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "min.w", 56,
30500     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30501   },
30502 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
30503   {
30504     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "min.w", 48,
30505     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30506   },
30507 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
30508   {
30509     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "min.w", 48,
30510     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30511   },
30512 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
30513   {
30514     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "min.w", 48,
30515     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30516   },
30517 /* min.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
30518   {
30519     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "min.w", 48,
30520     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30521   },
30522 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
30523   {
30524     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "min.w", 56,
30525     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30526   },
30527 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
30528   {
30529     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "min.w", 56,
30530     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30531   },
30532 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
30533   {
30534     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "min.w", 56,
30535     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30536   },
30537 /* min.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
30538   {
30539     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "min.w", 56,
30540     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30541   },
30542 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
30543   {
30544     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "min.w", 56,
30545     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30546   },
30547 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
30548   {
30549     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "min.w", 56,
30550     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30551   },
30552 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
30553   {
30554     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "min.w", 56,
30555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30556   },
30557 /* min.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
30558   {
30559     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "min.w", 56,
30560     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30561   },
30562 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
30563   {
30564     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "min.w", 64,
30565     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30566   },
30567 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
30568   {
30569     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "min.w", 64,
30570     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30571   },
30572 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
30573   {
30574     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "min.w", 64,
30575     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30576   },
30577 /* min.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
30578   {
30579     M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "min.w", 64,
30580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30581   },
30582 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
30583   {
30584     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 48,
30585     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30586   },
30587 /* min.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
30588   {
30589     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 48,
30590     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30591   },
30592 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
30593   {
30594     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 48,
30595     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30596   },
30597 /* min.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
30598   {
30599     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 48,
30600     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30601   },
30602 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
30603   {
30604     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 48,
30605     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30606   },
30607 /* min.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
30608   {
30609     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 48,
30610     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30611   },
30612 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
30613   {
30614     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "min.w", 56,
30615     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30616   },
30617 /* min.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
30618   {
30619     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "min.w", 56,
30620     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30621   },
30622 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
30623   {
30624     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "min.w", 64,
30625     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30626   },
30627 /* min.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
30628   {
30629     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "min.w", 64,
30630     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30631   },
30632 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
30633   {
30634     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "min.w", 72,
30635     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30636   },
30637 /* min.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
30638   {
30639     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "min.w", 72,
30640     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30641   },
30642 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
30643   {
30644     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "min.w", 56,
30645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30646   },
30647 /* min.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
30648   {
30649     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "min.w", 56,
30650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30651   },
30652 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
30653   {
30654     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "min.w", 64,
30655     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30656   },
30657 /* min.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
30658   {
30659     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "min.w", 64,
30660     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30661   },
30662 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
30663   {
30664     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "min.w", 56,
30665     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30666   },
30667 /* min.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
30668   {
30669     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "min.w", 56,
30670     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30671   },
30672 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
30673   {
30674     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "min.w", 64,
30675     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30676   },
30677 /* min.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
30678   {
30679     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "min.w", 64,
30680     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30681   },
30682 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
30683   {
30684     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "min.w", 64,
30685     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30686   },
30687 /* min.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
30688   {
30689     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "min.w", 64,
30690     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30691   },
30692 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
30693   {
30694     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "min.w", 72,
30695     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30696   },
30697 /* min.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
30698   {
30699     M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "min.w", 72,
30700     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30701   },
30702 /* min.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
30703   {
30704     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 24,
30705     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30706   },
30707 /* min.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
30708   {
30709     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 24,
30710     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30711   },
30712 /* min.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
30713   {
30714     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 24,
30715     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30716   },
30717 /* min.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
30718   {
30719     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 24,
30720     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30721   },
30722 /* min.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
30723   {
30724     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 24,
30725     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30726   },
30727 /* min.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
30728   {
30729     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 24,
30730     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30731   },
30732 /* min.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
30733   {
30734     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 24,
30735     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30736   },
30737 /* min.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
30738   {
30739     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 24,
30740     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30741   },
30742 /* min.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
30743   {
30744     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 24,
30745     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30746   },
30747 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
30748   {
30749     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "min.w", 32,
30750     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30751   },
30752 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
30753   {
30754     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "min.w", 32,
30755     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30756   },
30757 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
30758   {
30759     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "min.w", 32,
30760     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30761   },
30762 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
30763   {
30764     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "min.w", 40,
30765     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30766   },
30767 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
30768   {
30769     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "min.w", 40,
30770     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30771   },
30772 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
30773   {
30774     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "min.w", 40,
30775     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30776   },
30777 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
30778   {
30779     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "min.w", 48,
30780     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30781   },
30782 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
30783   {
30784     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "min.w", 48,
30785     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30786   },
30787 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
30788   {
30789     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "min.w", 48,
30790     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30791   },
30792 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
30793   {
30794     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "min.w", 32,
30795     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30796   },
30797 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
30798   {
30799     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "min.w", 32,
30800     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30801   },
30802 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
30803   {
30804     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "min.w", 32,
30805     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30806   },
30807 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
30808   {
30809     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "min.w", 40,
30810     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30811   },
30812 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
30813   {
30814     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "min.w", 40,
30815     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30816   },
30817 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
30818   {
30819     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "min.w", 40,
30820     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30821   },
30822 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
30823   {
30824     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "min.w", 32,
30825     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30826   },
30827 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
30828   {
30829     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "min.w", 32,
30830     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30831   },
30832 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
30833   {
30834     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "min.w", 32,
30835     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30836   },
30837 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
30838   {
30839     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "min.w", 40,
30840     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30841   },
30842 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
30843   {
30844     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "min.w", 40,
30845     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30846   },
30847 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
30848   {
30849     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "min.w", 40,
30850     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30851   },
30852 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
30853   {
30854     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "min.w", 40,
30855     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30856   },
30857 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
30858   {
30859     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "min.w", 40,
30860     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30861   },
30862 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
30863   {
30864     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "min.w", 40,
30865     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30866   },
30867 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
30868   {
30869     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "min.w", 48,
30870     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30871   },
30872 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
30873   {
30874     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "min.w", 48,
30875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30876   },
30877 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
30878   {
30879     M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "min.w", 48,
30880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30881   },
30882 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
30883   {
30884     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 32,
30885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30886   },
30887 /* min.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
30888   {
30889     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 32,
30890     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30891   },
30892 /* min.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
30893   {
30894     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 32,
30895     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30896   },
30897 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
30898   {
30899     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 32,
30900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30901   },
30902 /* min.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
30903   {
30904     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 32,
30905     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30906   },
30907 /* min.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
30908   {
30909     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 32,
30910     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30911   },
30912 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
30913   {
30914     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 32,
30915     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30916   },
30917 /* min.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
30918   {
30919     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 32,
30920     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30921   },
30922 /* min.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
30923   {
30924     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 32,
30925     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30926   },
30927 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
30928   {
30929     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "min.b", 40,
30930     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30931   },
30932 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
30933   {
30934     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "min.b", 40,
30935     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30936   },
30937 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
30938   {
30939     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "min.b", 40,
30940     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30941   },
30942 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
30943   {
30944     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "min.b", 48,
30945     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30946   },
30947 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
30948   {
30949     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "min.b", 48,
30950     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30951   },
30952 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
30953   {
30954     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "min.b", 48,
30955     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30956   },
30957 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
30958   {
30959     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "min.b", 56,
30960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30961   },
30962 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
30963   {
30964     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "min.b", 56,
30965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30966   },
30967 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
30968   {
30969     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "min.b", 56,
30970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30971   },
30972 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
30973   {
30974     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "min.b", 40,
30975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30976   },
30977 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
30978   {
30979     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "min.b", 40,
30980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30981   },
30982 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
30983   {
30984     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "min.b", 40,
30985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30986   },
30987 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
30988   {
30989     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "min.b", 48,
30990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30991   },
30992 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
30993   {
30994     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "min.b", 48,
30995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30996   },
30997 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
30998   {
30999     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "min.b", 48,
31000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31001   },
31002 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
31003   {
31004     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "min.b", 40,
31005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31006   },
31007 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
31008   {
31009     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "min.b", 40,
31010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31011   },
31012 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
31013   {
31014     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "min.b", 40,
31015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31016   },
31017 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
31018   {
31019     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "min.b", 48,
31020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31021   },
31022 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
31023   {
31024     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "min.b", 48,
31025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31026   },
31027 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
31028   {
31029     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "min.b", 48,
31030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31031   },
31032 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
31033   {
31034     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "min.b", 48,
31035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31036   },
31037 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
31038   {
31039     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "min.b", 48,
31040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31041   },
31042 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
31043   {
31044     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "min.b", 48,
31045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31046   },
31047 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
31048   {
31049     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "min.b", 56,
31050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31051   },
31052 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
31053   {
31054     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "min.b", 56,
31055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31056   },
31057 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
31058   {
31059     M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "min.b", 56,
31060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31061   },
31062 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
31063   {
31064     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 40,
31065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31066   },
31067 /* min.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
31068   {
31069     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 40,
31070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31071   },
31072 /* min.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
31073   {
31074     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 40,
31075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31076   },
31077 /* min.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
31078   {
31079     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 40,
31080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31081   },
31082 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
31083   {
31084     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 40,
31085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31086   },
31087 /* min.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
31088   {
31089     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 40,
31090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31091   },
31092 /* min.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
31093   {
31094     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 40,
31095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31096   },
31097 /* min.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
31098   {
31099     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 40,
31100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31101   },
31102 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
31103   {
31104     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 40,
31105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31106   },
31107 /* min.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
31108   {
31109     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 40,
31110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31111   },
31112 /* min.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
31113   {
31114     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 40,
31115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31116   },
31117 /* min.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
31118   {
31119     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 40,
31120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31121   },
31122 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
31123   {
31124     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "min.b", 48,
31125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31126   },
31127 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
31128   {
31129     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "min.b", 48,
31130     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31131   },
31132 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
31133   {
31134     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "min.b", 48,
31135     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31136   },
31137 /* min.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
31138   {
31139     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "min.b", 48,
31140     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31141   },
31142 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
31143   {
31144     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "min.b", 56,
31145     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31146   },
31147 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
31148   {
31149     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "min.b", 56,
31150     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31151   },
31152 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
31153   {
31154     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "min.b", 56,
31155     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31156   },
31157 /* min.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
31158   {
31159     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "min.b", 56,
31160     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31161   },
31162 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
31163   {
31164     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "min.b", 64,
31165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31166   },
31167 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
31168   {
31169     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "min.b", 64,
31170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31171   },
31172 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
31173   {
31174     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "min.b", 64,
31175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31176   },
31177 /* min.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
31178   {
31179     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "min.b", 64,
31180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31181   },
31182 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
31183   {
31184     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "min.b", 48,
31185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31186   },
31187 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
31188   {
31189     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "min.b", 48,
31190     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31191   },
31192 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
31193   {
31194     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "min.b", 48,
31195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31196   },
31197 /* min.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
31198   {
31199     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "min.b", 48,
31200     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31201   },
31202 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
31203   {
31204     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "min.b", 56,
31205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31206   },
31207 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
31208   {
31209     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "min.b", 56,
31210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31211   },
31212 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
31213   {
31214     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "min.b", 56,
31215     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31216   },
31217 /* min.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
31218   {
31219     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "min.b", 56,
31220     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31221   },
31222 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
31223   {
31224     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "min.b", 48,
31225     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31226   },
31227 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
31228   {
31229     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "min.b", 48,
31230     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31231   },
31232 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
31233   {
31234     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "min.b", 48,
31235     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31236   },
31237 /* min.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
31238   {
31239     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "min.b", 48,
31240     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31241   },
31242 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
31243   {
31244     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "min.b", 56,
31245     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31246   },
31247 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
31248   {
31249     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "min.b", 56,
31250     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31251   },
31252 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
31253   {
31254     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "min.b", 56,
31255     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31256   },
31257 /* min.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
31258   {
31259     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "min.b", 56,
31260     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31261   },
31262 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
31263   {
31264     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "min.b", 56,
31265     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31266   },
31267 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
31268   {
31269     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "min.b", 56,
31270     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31271   },
31272 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
31273   {
31274     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "min.b", 56,
31275     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31276   },
31277 /* min.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
31278   {
31279     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "min.b", 56,
31280     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31281   },
31282 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
31283   {
31284     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "min.b", 64,
31285     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31286   },
31287 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
31288   {
31289     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "min.b", 64,
31290     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31291   },
31292 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
31293   {
31294     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "min.b", 64,
31295     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31296   },
31297 /* min.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
31298   {
31299     M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "min.b", 64,
31300     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31301   },
31302 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
31303   {
31304     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 48,
31305     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31306   },
31307 /* min.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
31308   {
31309     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 48,
31310     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31311   },
31312 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
31313   {
31314     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 48,
31315     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31316   },
31317 /* min.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
31318   {
31319     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 48,
31320     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31321   },
31322 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
31323   {
31324     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 48,
31325     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31326   },
31327 /* min.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
31328   {
31329     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 48,
31330     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31331   },
31332 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
31333   {
31334     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "min.b", 56,
31335     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31336   },
31337 /* min.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
31338   {
31339     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "min.b", 56,
31340     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31341   },
31342 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
31343   {
31344     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "min.b", 64,
31345     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31346   },
31347 /* min.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
31348   {
31349     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "min.b", 64,
31350     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31351   },
31352 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
31353   {
31354     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "min.b", 72,
31355     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31356   },
31357 /* min.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
31358   {
31359     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "min.b", 72,
31360     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31361   },
31362 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
31363   {
31364     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "min.b", 56,
31365     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31366   },
31367 /* min.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
31368   {
31369     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "min.b", 56,
31370     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31371   },
31372 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
31373   {
31374     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "min.b", 64,
31375     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31376   },
31377 /* min.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
31378   {
31379     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "min.b", 64,
31380     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31381   },
31382 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
31383   {
31384     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "min.b", 56,
31385     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31386   },
31387 /* min.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
31388   {
31389     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "min.b", 56,
31390     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31391   },
31392 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
31393   {
31394     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "min.b", 64,
31395     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31396   },
31397 /* min.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
31398   {
31399     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "min.b", 64,
31400     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31401   },
31402 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
31403   {
31404     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "min.b", 64,
31405     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31406   },
31407 /* min.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
31408   {
31409     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "min.b", 64,
31410     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31411   },
31412 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
31413   {
31414     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "min.b", 72,
31415     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31416   },
31417 /* min.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
31418   {
31419     M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "min.b", 72,
31420     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31421   },
31422 /* min.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
31423   {
31424     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 24,
31425     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31426   },
31427 /* min.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
31428   {
31429     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 24,
31430     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31431   },
31432 /* min.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
31433   {
31434     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 24,
31435     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31436   },
31437 /* min.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
31438   {
31439     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 24,
31440     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31441   },
31442 /* min.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
31443   {
31444     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 24,
31445     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31446   },
31447 /* min.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
31448   {
31449     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 24,
31450     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31451   },
31452 /* min.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
31453   {
31454     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 24,
31455     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31456   },
31457 /* min.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
31458   {
31459     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 24,
31460     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31461   },
31462 /* min.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
31463   {
31464     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 24,
31465     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31466   },
31467 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
31468   {
31469     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "min.b", 32,
31470     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31471   },
31472 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
31473   {
31474     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "min.b", 32,
31475     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31476   },
31477 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
31478   {
31479     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "min.b", 32,
31480     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31481   },
31482 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
31483   {
31484     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "min.b", 40,
31485     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31486   },
31487 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
31488   {
31489     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "min.b", 40,
31490     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31491   },
31492 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
31493   {
31494     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "min.b", 40,
31495     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31496   },
31497 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
31498   {
31499     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "min.b", 48,
31500     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31501   },
31502 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
31503   {
31504     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "min.b", 48,
31505     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31506   },
31507 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
31508   {
31509     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "min.b", 48,
31510     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31511   },
31512 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
31513   {
31514     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "min.b", 32,
31515     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31516   },
31517 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
31518   {
31519     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "min.b", 32,
31520     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31521   },
31522 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
31523   {
31524     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "min.b", 32,
31525     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31526   },
31527 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
31528   {
31529     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "min.b", 40,
31530     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31531   },
31532 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
31533   {
31534     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "min.b", 40,
31535     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31536   },
31537 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
31538   {
31539     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "min.b", 40,
31540     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31541   },
31542 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
31543   {
31544     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "min.b", 32,
31545     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31546   },
31547 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
31548   {
31549     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "min.b", 32,
31550     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31551   },
31552 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
31553   {
31554     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "min.b", 32,
31555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31556   },
31557 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
31558   {
31559     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "min.b", 40,
31560     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31561   },
31562 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
31563   {
31564     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "min.b", 40,
31565     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31566   },
31567 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
31568   {
31569     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "min.b", 40,
31570     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31571   },
31572 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
31573   {
31574     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "min.b", 40,
31575     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31576   },
31577 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
31578   {
31579     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "min.b", 40,
31580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31581   },
31582 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
31583   {
31584     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "min.b", 40,
31585     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31586   },
31587 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
31588   {
31589     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "min.b", 48,
31590     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31591   },
31592 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
31593   {
31594     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "min.b", 48,
31595     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31596   },
31597 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
31598   {
31599     M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "min.b", 48,
31600     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31601   },
31602 /* min.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
31603   {
31604     M32C_INSN_MIN32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "min.w", 40,
31605     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31606   },
31607 /* min.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
31608   {
31609     M32C_INSN_MIN32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "min.w", 40,
31610     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31611   },
31612 /* min.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
31613   {
31614     M32C_INSN_MIN32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "min.w", 40,
31615     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31616   },
31617 /* min.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
31618   {
31619     M32C_INSN_MIN32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "min.w", 48,
31620     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31621   },
31622 /* min.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
31623   {
31624     M32C_INSN_MIN32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "min.w", 48,
31625     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31626   },
31627 /* min.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
31628   {
31629     M32C_INSN_MIN32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "min.w", 48,
31630     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31631   },
31632 /* min.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
31633   {
31634     M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "min.w", 56,
31635     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31636   },
31637 /* min.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
31638   {
31639     M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "min.w", 56,
31640     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31641   },
31642 /* min.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
31643   {
31644     M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "min.w", 56,
31645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31646   },
31647 /* min.w${X} #${Imm-40-HI},${Dsp-24-u16} */
31648   {
31649     M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "min32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "min.w", 56,
31650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31651   },
31652 /* min.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
31653   {
31654     M32C_INSN_MIN32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "min.w", 64,
31655     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31656   },
31657 /* min.w${X} #${Imm-48-HI},${Dsp-24-u24} */
31658   {
31659     M32C_INSN_MIN32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "min32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "min.w", 64,
31660     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31661   },
31662 /* min.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
31663   {
31664     M32C_INSN_MIN32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "min.b", 32,
31665     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31666   },
31667 /* min.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
31668   {
31669     M32C_INSN_MIN32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "min.b", 32,
31670     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31671   },
31672 /* min.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
31673   {
31674     M32C_INSN_MIN32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "min.b", 32,
31675     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31676   },
31677 /* min.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
31678   {
31679     M32C_INSN_MIN32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "min.b", 40,
31680     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31681   },
31682 /* min.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
31683   {
31684     M32C_INSN_MIN32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "min.b", 40,
31685     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31686   },
31687 /* min.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
31688   {
31689     M32C_INSN_MIN32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "min.b", 40,
31690     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31691   },
31692 /* min.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
31693   {
31694     M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "min.b", 48,
31695     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31696   },
31697 /* min.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
31698   {
31699     M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "min.b", 48,
31700     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31701   },
31702 /* min.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
31703   {
31704     M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "min.b", 48,
31705     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31706   },
31707 /* min.b${X} #${Imm-40-QI},${Dsp-24-u16} */
31708   {
31709     M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "min32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "min.b", 48,
31710     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31711   },
31712 /* min.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
31713   {
31714     M32C_INSN_MIN32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "min.b", 56,
31715     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31716   },
31717 /* min.b${X} #${Imm-48-QI},${Dsp-24-u24} */
31718   {
31719     M32C_INSN_MIN32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "min32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "min.b", 56,
31720     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31721   },
31722 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
31723   {
31724     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 32,
31725     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31726   },
31727 /* max.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
31728   {
31729     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 32,
31730     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31731   },
31732 /* max.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
31733   {
31734     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 32,
31735     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31736   },
31737 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
31738   {
31739     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 32,
31740     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31741   },
31742 /* max.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
31743   {
31744     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 32,
31745     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31746   },
31747 /* max.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
31748   {
31749     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 32,
31750     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31751   },
31752 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
31753   {
31754     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 32,
31755     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31756   },
31757 /* max.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
31758   {
31759     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 32,
31760     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31761   },
31762 /* max.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
31763   {
31764     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 32,
31765     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31766   },
31767 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
31768   {
31769     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "max.w", 40,
31770     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31771   },
31772 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
31773   {
31774     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "max.w", 40,
31775     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31776   },
31777 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
31778   {
31779     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "max.w", 40,
31780     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31781   },
31782 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
31783   {
31784     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "max.w", 48,
31785     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31786   },
31787 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
31788   {
31789     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "max.w", 48,
31790     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31791   },
31792 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
31793   {
31794     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "max.w", 48,
31795     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31796   },
31797 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
31798   {
31799     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "max.w", 56,
31800     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31801   },
31802 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
31803   {
31804     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "max.w", 56,
31805     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31806   },
31807 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
31808   {
31809     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "max.w", 56,
31810     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31811   },
31812 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
31813   {
31814     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "max.w", 40,
31815     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31816   },
31817 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
31818   {
31819     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "max.w", 40,
31820     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31821   },
31822 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
31823   {
31824     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "max.w", 40,
31825     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31826   },
31827 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
31828   {
31829     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "max.w", 48,
31830     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31831   },
31832 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
31833   {
31834     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "max.w", 48,
31835     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31836   },
31837 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
31838   {
31839     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "max.w", 48,
31840     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31841   },
31842 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
31843   {
31844     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "max.w", 40,
31845     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31846   },
31847 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
31848   {
31849     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "max.w", 40,
31850     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31851   },
31852 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
31853   {
31854     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "max.w", 40,
31855     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31856   },
31857 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
31858   {
31859     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "max.w", 48,
31860     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31861   },
31862 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
31863   {
31864     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "max.w", 48,
31865     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31866   },
31867 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
31868   {
31869     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "max.w", 48,
31870     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31871   },
31872 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
31873   {
31874     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "max.w", 48,
31875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31876   },
31877 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
31878   {
31879     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "max.w", 48,
31880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31881   },
31882 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
31883   {
31884     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "max.w", 48,
31885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31886   },
31887 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
31888   {
31889     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "max.w", 56,
31890     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31891   },
31892 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
31893   {
31894     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "max.w", 56,
31895     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31896   },
31897 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
31898   {
31899     M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "max.w", 56,
31900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31901   },
31902 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
31903   {
31904     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 40,
31905     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31906   },
31907 /* max.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
31908   {
31909     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 40,
31910     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31911   },
31912 /* max.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
31913   {
31914     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 40,
31915     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31916   },
31917 /* max.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
31918   {
31919     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 40,
31920     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31921   },
31922 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
31923   {
31924     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 40,
31925     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31926   },
31927 /* max.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
31928   {
31929     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 40,
31930     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31931   },
31932 /* max.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
31933   {
31934     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 40,
31935     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31936   },
31937 /* max.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
31938   {
31939     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 40,
31940     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31941   },
31942 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
31943   {
31944     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 40,
31945     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31946   },
31947 /* max.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
31948   {
31949     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 40,
31950     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31951   },
31952 /* max.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
31953   {
31954     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 40,
31955     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31956   },
31957 /* max.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
31958   {
31959     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 40,
31960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31961   },
31962 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
31963   {
31964     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "max.w", 48,
31965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31966   },
31967 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
31968   {
31969     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "max.w", 48,
31970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31971   },
31972 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
31973   {
31974     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "max.w", 48,
31975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31976   },
31977 /* max.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
31978   {
31979     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "max.w", 48,
31980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31981   },
31982 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
31983   {
31984     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "max.w", 56,
31985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31986   },
31987 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
31988   {
31989     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "max.w", 56,
31990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31991   },
31992 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
31993   {
31994     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "max.w", 56,
31995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31996   },
31997 /* max.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
31998   {
31999     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "max.w", 56,
32000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32001   },
32002 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
32003   {
32004     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "max.w", 64,
32005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32006   },
32007 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
32008   {
32009     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "max.w", 64,
32010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32011   },
32012 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
32013   {
32014     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "max.w", 64,
32015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32016   },
32017 /* max.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
32018   {
32019     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "max.w", 64,
32020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32021   },
32022 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
32023   {
32024     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "max.w", 48,
32025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32026   },
32027 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
32028   {
32029     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "max.w", 48,
32030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32031   },
32032 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
32033   {
32034     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "max.w", 48,
32035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32036   },
32037 /* max.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
32038   {
32039     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "max.w", 48,
32040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32041   },
32042 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
32043   {
32044     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "max.w", 56,
32045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32046   },
32047 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
32048   {
32049     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "max.w", 56,
32050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32051   },
32052 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
32053   {
32054     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "max.w", 56,
32055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32056   },
32057 /* max.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
32058   {
32059     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "max.w", 56,
32060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32061   },
32062 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
32063   {
32064     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "max.w", 48,
32065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32066   },
32067 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
32068   {
32069     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "max.w", 48,
32070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32071   },
32072 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
32073   {
32074     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "max.w", 48,
32075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32076   },
32077 /* max.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
32078   {
32079     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "max.w", 48,
32080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32081   },
32082 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
32083   {
32084     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "max.w", 56,
32085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32086   },
32087 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
32088   {
32089     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "max.w", 56,
32090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32091   },
32092 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
32093   {
32094     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "max.w", 56,
32095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32096   },
32097 /* max.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
32098   {
32099     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "max.w", 56,
32100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32101   },
32102 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
32103   {
32104     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "max.w", 56,
32105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32106   },
32107 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
32108   {
32109     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "max.w", 56,
32110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32111   },
32112 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
32113   {
32114     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "max.w", 56,
32115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32116   },
32117 /* max.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
32118   {
32119     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "max.w", 56,
32120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32121   },
32122 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
32123   {
32124     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "max.w", 64,
32125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32126   },
32127 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
32128   {
32129     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "max.w", 64,
32130     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32131   },
32132 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
32133   {
32134     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "max.w", 64,
32135     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32136   },
32137 /* max.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
32138   {
32139     M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "max.w", 64,
32140     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32141   },
32142 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
32143   {
32144     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 48,
32145     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32146   },
32147 /* max.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
32148   {
32149     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 48,
32150     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32151   },
32152 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
32153   {
32154     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 48,
32155     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32156   },
32157 /* max.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
32158   {
32159     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 48,
32160     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32161   },
32162 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
32163   {
32164     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 48,
32165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32166   },
32167 /* max.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
32168   {
32169     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 48,
32170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32171   },
32172 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
32173   {
32174     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "max.w", 56,
32175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32176   },
32177 /* max.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
32178   {
32179     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "max.w", 56,
32180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32181   },
32182 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
32183   {
32184     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "max.w", 64,
32185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32186   },
32187 /* max.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
32188   {
32189     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "max.w", 64,
32190     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32191   },
32192 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
32193   {
32194     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "max.w", 72,
32195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32196   },
32197 /* max.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
32198   {
32199     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "max.w", 72,
32200     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32201   },
32202 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
32203   {
32204     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "max.w", 56,
32205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32206   },
32207 /* max.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
32208   {
32209     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "max.w", 56,
32210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32211   },
32212 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
32213   {
32214     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "max.w", 64,
32215     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32216   },
32217 /* max.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
32218   {
32219     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "max.w", 64,
32220     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32221   },
32222 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
32223   {
32224     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "max.w", 56,
32225     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32226   },
32227 /* max.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
32228   {
32229     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "max.w", 56,
32230     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32231   },
32232 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
32233   {
32234     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "max.w", 64,
32235     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32236   },
32237 /* max.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
32238   {
32239     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "max.w", 64,
32240     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32241   },
32242 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
32243   {
32244     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "max.w", 64,
32245     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32246   },
32247 /* max.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
32248   {
32249     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "max.w", 64,
32250     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32251   },
32252 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
32253   {
32254     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "max.w", 72,
32255     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32256   },
32257 /* max.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
32258   {
32259     M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "max.w", 72,
32260     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32261   },
32262 /* max.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
32263   {
32264     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 24,
32265     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32266   },
32267 /* max.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
32268   {
32269     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 24,
32270     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32271   },
32272 /* max.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
32273   {
32274     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 24,
32275     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32276   },
32277 /* max.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
32278   {
32279     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 24,
32280     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32281   },
32282 /* max.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
32283   {
32284     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 24,
32285     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32286   },
32287 /* max.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
32288   {
32289     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 24,
32290     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32291   },
32292 /* max.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
32293   {
32294     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 24,
32295     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32296   },
32297 /* max.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
32298   {
32299     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 24,
32300     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32301   },
32302 /* max.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
32303   {
32304     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 24,
32305     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32306   },
32307 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
32308   {
32309     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "max.w", 32,
32310     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32311   },
32312 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
32313   {
32314     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "max.w", 32,
32315     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32316   },
32317 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
32318   {
32319     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "max.w", 32,
32320     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32321   },
32322 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
32323   {
32324     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "max.w", 40,
32325     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32326   },
32327 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
32328   {
32329     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "max.w", 40,
32330     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32331   },
32332 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
32333   {
32334     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "max.w", 40,
32335     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32336   },
32337 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
32338   {
32339     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "max.w", 48,
32340     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32341   },
32342 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
32343   {
32344     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "max.w", 48,
32345     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32346   },
32347 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
32348   {
32349     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "max.w", 48,
32350     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32351   },
32352 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
32353   {
32354     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "max.w", 32,
32355     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32356   },
32357 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
32358   {
32359     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "max.w", 32,
32360     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32361   },
32362 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
32363   {
32364     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "max.w", 32,
32365     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32366   },
32367 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
32368   {
32369     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "max.w", 40,
32370     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32371   },
32372 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
32373   {
32374     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "max.w", 40,
32375     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32376   },
32377 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
32378   {
32379     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "max.w", 40,
32380     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32381   },
32382 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
32383   {
32384     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "max.w", 32,
32385     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32386   },
32387 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
32388   {
32389     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "max.w", 32,
32390     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32391   },
32392 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
32393   {
32394     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "max.w", 32,
32395     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32396   },
32397 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
32398   {
32399     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "max.w", 40,
32400     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32401   },
32402 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
32403   {
32404     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "max.w", 40,
32405     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32406   },
32407 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
32408   {
32409     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "max.w", 40,
32410     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32411   },
32412 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
32413   {
32414     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "max.w", 40,
32415     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32416   },
32417 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
32418   {
32419     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "max.w", 40,
32420     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32421   },
32422 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
32423   {
32424     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "max.w", 40,
32425     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32426   },
32427 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
32428   {
32429     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "max.w", 48,
32430     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32431   },
32432 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
32433   {
32434     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "max.w", 48,
32435     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32436   },
32437 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
32438   {
32439     M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "max.w", 48,
32440     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32441   },
32442 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
32443   {
32444     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 32,
32445     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32446   },
32447 /* max.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
32448   {
32449     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 32,
32450     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32451   },
32452 /* max.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
32453   {
32454     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 32,
32455     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32456   },
32457 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
32458   {
32459     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 32,
32460     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32461   },
32462 /* max.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
32463   {
32464     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 32,
32465     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32466   },
32467 /* max.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
32468   {
32469     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 32,
32470     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32471   },
32472 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
32473   {
32474     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 32,
32475     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32476   },
32477 /* max.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
32478   {
32479     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 32,
32480     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32481   },
32482 /* max.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
32483   {
32484     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 32,
32485     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32486   },
32487 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
32488   {
32489     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "max.b", 40,
32490     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32491   },
32492 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
32493   {
32494     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "max.b", 40,
32495     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32496   },
32497 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
32498   {
32499     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "max.b", 40,
32500     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32501   },
32502 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
32503   {
32504     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "max.b", 48,
32505     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32506   },
32507 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
32508   {
32509     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "max.b", 48,
32510     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32511   },
32512 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
32513   {
32514     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "max.b", 48,
32515     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32516   },
32517 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
32518   {
32519     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "max.b", 56,
32520     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32521   },
32522 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
32523   {
32524     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "max.b", 56,
32525     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32526   },
32527 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
32528   {
32529     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "max.b", 56,
32530     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32531   },
32532 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
32533   {
32534     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "max.b", 40,
32535     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32536   },
32537 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
32538   {
32539     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "max.b", 40,
32540     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32541   },
32542 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
32543   {
32544     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "max.b", 40,
32545     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32546   },
32547 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
32548   {
32549     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "max.b", 48,
32550     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32551   },
32552 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
32553   {
32554     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "max.b", 48,
32555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32556   },
32557 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
32558   {
32559     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "max.b", 48,
32560     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32561   },
32562 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
32563   {
32564     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "max.b", 40,
32565     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32566   },
32567 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
32568   {
32569     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "max.b", 40,
32570     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32571   },
32572 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
32573   {
32574     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "max.b", 40,
32575     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32576   },
32577 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
32578   {
32579     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "max.b", 48,
32580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32581   },
32582 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
32583   {
32584     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "max.b", 48,
32585     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32586   },
32587 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
32588   {
32589     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "max.b", 48,
32590     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32591   },
32592 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
32593   {
32594     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "max.b", 48,
32595     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32596   },
32597 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
32598   {
32599     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "max.b", 48,
32600     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32601   },
32602 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
32603   {
32604     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "max.b", 48,
32605     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32606   },
32607 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
32608   {
32609     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "max.b", 56,
32610     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32611   },
32612 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
32613   {
32614     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "max.b", 56,
32615     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32616   },
32617 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
32618   {
32619     M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "max.b", 56,
32620     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32621   },
32622 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
32623   {
32624     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 40,
32625     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32626   },
32627 /* max.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
32628   {
32629     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 40,
32630     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32631   },
32632 /* max.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
32633   {
32634     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 40,
32635     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32636   },
32637 /* max.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
32638   {
32639     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 40,
32640     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32641   },
32642 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
32643   {
32644     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 40,
32645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32646   },
32647 /* max.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
32648   {
32649     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 40,
32650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32651   },
32652 /* max.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
32653   {
32654     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 40,
32655     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32656   },
32657 /* max.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
32658   {
32659     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 40,
32660     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32661   },
32662 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
32663   {
32664     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 40,
32665     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32666   },
32667 /* max.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
32668   {
32669     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 40,
32670     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32671   },
32672 /* max.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
32673   {
32674     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 40,
32675     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32676   },
32677 /* max.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
32678   {
32679     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 40,
32680     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32681   },
32682 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
32683   {
32684     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "max.b", 48,
32685     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32686   },
32687 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
32688   {
32689     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "max.b", 48,
32690     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32691   },
32692 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
32693   {
32694     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "max.b", 48,
32695     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32696   },
32697 /* max.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
32698   {
32699     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "max.b", 48,
32700     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32701   },
32702 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
32703   {
32704     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "max.b", 56,
32705     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32706   },
32707 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
32708   {
32709     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "max.b", 56,
32710     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32711   },
32712 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
32713   {
32714     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "max.b", 56,
32715     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32716   },
32717 /* max.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
32718   {
32719     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "max.b", 56,
32720     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32721   },
32722 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
32723   {
32724     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "max.b", 64,
32725     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32726   },
32727 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
32728   {
32729     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "max.b", 64,
32730     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32731   },
32732 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
32733   {
32734     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "max.b", 64,
32735     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32736   },
32737 /* max.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
32738   {
32739     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "max.b", 64,
32740     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32741   },
32742 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
32743   {
32744     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "max.b", 48,
32745     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32746   },
32747 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
32748   {
32749     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "max.b", 48,
32750     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32751   },
32752 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
32753   {
32754     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "max.b", 48,
32755     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32756   },
32757 /* max.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
32758   {
32759     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "max.b", 48,
32760     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32761   },
32762 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
32763   {
32764     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "max.b", 56,
32765     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32766   },
32767 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
32768   {
32769     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "max.b", 56,
32770     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32771   },
32772 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
32773   {
32774     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "max.b", 56,
32775     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32776   },
32777 /* max.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
32778   {
32779     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "max.b", 56,
32780     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32781   },
32782 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
32783   {
32784     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "max.b", 48,
32785     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32786   },
32787 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
32788   {
32789     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "max.b", 48,
32790     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32791   },
32792 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
32793   {
32794     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "max.b", 48,
32795     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32796   },
32797 /* max.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
32798   {
32799     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "max.b", 48,
32800     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32801   },
32802 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
32803   {
32804     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "max.b", 56,
32805     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32806   },
32807 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
32808   {
32809     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "max.b", 56,
32810     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32811   },
32812 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
32813   {
32814     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "max.b", 56,
32815     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32816   },
32817 /* max.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
32818   {
32819     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "max.b", 56,
32820     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32821   },
32822 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
32823   {
32824     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "max.b", 56,
32825     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32826   },
32827 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
32828   {
32829     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "max.b", 56,
32830     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32831   },
32832 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
32833   {
32834     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "max.b", 56,
32835     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32836   },
32837 /* max.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
32838   {
32839     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "max.b", 56,
32840     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32841   },
32842 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
32843   {
32844     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "max.b", 64,
32845     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32846   },
32847 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
32848   {
32849     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "max.b", 64,
32850     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32851   },
32852 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
32853   {
32854     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "max.b", 64,
32855     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32856   },
32857 /* max.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
32858   {
32859     M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "max.b", 64,
32860     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32861   },
32862 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
32863   {
32864     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 48,
32865     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32866   },
32867 /* max.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
32868   {
32869     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 48,
32870     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32871   },
32872 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
32873   {
32874     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 48,
32875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32876   },
32877 /* max.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
32878   {
32879     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 48,
32880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32881   },
32882 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
32883   {
32884     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 48,
32885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32886   },
32887 /* max.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
32888   {
32889     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 48,
32890     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32891   },
32892 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
32893   {
32894     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "max.b", 56,
32895     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32896   },
32897 /* max.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
32898   {
32899     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "max.b", 56,
32900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32901   },
32902 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
32903   {
32904     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "max.b", 64,
32905     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32906   },
32907 /* max.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
32908   {
32909     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "max.b", 64,
32910     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32911   },
32912 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
32913   {
32914     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "max.b", 72,
32915     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32916   },
32917 /* max.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
32918   {
32919     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "max.b", 72,
32920     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32921   },
32922 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
32923   {
32924     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "max.b", 56,
32925     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32926   },
32927 /* max.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
32928   {
32929     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "max.b", 56,
32930     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32931   },
32932 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
32933   {
32934     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "max.b", 64,
32935     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32936   },
32937 /* max.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
32938   {
32939     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "max.b", 64,
32940     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32941   },
32942 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
32943   {
32944     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "max.b", 56,
32945     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32946   },
32947 /* max.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
32948   {
32949     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "max.b", 56,
32950     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32951   },
32952 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
32953   {
32954     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "max.b", 64,
32955     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32956   },
32957 /* max.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
32958   {
32959     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "max.b", 64,
32960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32961   },
32962 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
32963   {
32964     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "max.b", 64,
32965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32966   },
32967 /* max.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
32968   {
32969     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "max.b", 64,
32970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32971   },
32972 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
32973   {
32974     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "max.b", 72,
32975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32976   },
32977 /* max.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
32978   {
32979     M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "max.b", 72,
32980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32981   },
32982 /* max.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
32983   {
32984     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 24,
32985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32986   },
32987 /* max.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
32988   {
32989     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 24,
32990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32991   },
32992 /* max.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
32993   {
32994     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 24,
32995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32996   },
32997 /* max.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
32998   {
32999     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 24,
33000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33001   },
33002 /* max.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
33003   {
33004     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 24,
33005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33006   },
33007 /* max.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
33008   {
33009     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 24,
33010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33011   },
33012 /* max.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
33013   {
33014     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 24,
33015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33016   },
33017 /* max.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
33018   {
33019     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 24,
33020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33021   },
33022 /* max.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
33023   {
33024     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 24,
33025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33026   },
33027 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
33028   {
33029     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "max.b", 32,
33030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33031   },
33032 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
33033   {
33034     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "max.b", 32,
33035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33036   },
33037 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
33038   {
33039     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "max.b", 32,
33040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33041   },
33042 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
33043   {
33044     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "max.b", 40,
33045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33046   },
33047 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
33048   {
33049     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "max.b", 40,
33050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33051   },
33052 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
33053   {
33054     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "max.b", 40,
33055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33056   },
33057 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
33058   {
33059     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "max.b", 48,
33060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33061   },
33062 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
33063   {
33064     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "max.b", 48,
33065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33066   },
33067 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
33068   {
33069     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "max.b", 48,
33070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33071   },
33072 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
33073   {
33074     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "max.b", 32,
33075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33076   },
33077 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
33078   {
33079     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "max.b", 32,
33080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33081   },
33082 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
33083   {
33084     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "max.b", 32,
33085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33086   },
33087 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
33088   {
33089     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "max.b", 40,
33090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33091   },
33092 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
33093   {
33094     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "max.b", 40,
33095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33096   },
33097 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
33098   {
33099     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "max.b", 40,
33100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33101   },
33102 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
33103   {
33104     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "max.b", 32,
33105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33106   },
33107 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
33108   {
33109     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "max.b", 32,
33110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33111   },
33112 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
33113   {
33114     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "max.b", 32,
33115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33116   },
33117 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
33118   {
33119     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "max.b", 40,
33120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33121   },
33122 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
33123   {
33124     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "max.b", 40,
33125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33126   },
33127 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
33128   {
33129     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "max.b", 40,
33130     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33131   },
33132 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
33133   {
33134     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "max.b", 40,
33135     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33136   },
33137 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
33138   {
33139     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "max.b", 40,
33140     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33141   },
33142 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
33143   {
33144     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "max.b", 40,
33145     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33146   },
33147 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
33148   {
33149     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "max.b", 48,
33150     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33151   },
33152 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
33153   {
33154     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "max.b", 48,
33155     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33156   },
33157 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
33158   {
33159     M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "max.b", 48,
33160     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33161   },
33162 /* max.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
33163   {
33164     M32C_INSN_MAX32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "max.w", 40,
33165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33166   },
33167 /* max.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
33168   {
33169     M32C_INSN_MAX32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "max.w", 40,
33170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33171   },
33172 /* max.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
33173   {
33174     M32C_INSN_MAX32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "max.w", 40,
33175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33176   },
33177 /* max.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
33178   {
33179     M32C_INSN_MAX32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "max.w", 48,
33180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33181   },
33182 /* max.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
33183   {
33184     M32C_INSN_MAX32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "max.w", 48,
33185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33186   },
33187 /* max.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
33188   {
33189     M32C_INSN_MAX32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "max.w", 48,
33190     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33191   },
33192 /* max.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
33193   {
33194     M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "max.w", 56,
33195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33196   },
33197 /* max.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
33198   {
33199     M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "max.w", 56,
33200     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33201   },
33202 /* max.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
33203   {
33204     M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "max.w", 56,
33205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33206   },
33207 /* max.w${X} #${Imm-40-HI},${Dsp-24-u16} */
33208   {
33209     M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "max32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "max.w", 56,
33210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33211   },
33212 /* max.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
33213   {
33214     M32C_INSN_MAX32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "max.w", 64,
33215     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33216   },
33217 /* max.w${X} #${Imm-48-HI},${Dsp-24-u24} */
33218   {
33219     M32C_INSN_MAX32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "max32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "max.w", 64,
33220     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33221   },
33222 /* max.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
33223   {
33224     M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "max.b", 32,
33225     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33226   },
33227 /* max.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
33228   {
33229     M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "max.b", 32,
33230     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33231   },
33232 /* max.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
33233   {
33234     M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "max.b", 32,
33235     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33236   },
33237 /* max.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
33238   {
33239     M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "max.b", 40,
33240     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33241   },
33242 /* max.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
33243   {
33244     M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "max.b", 40,
33245     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33246   },
33247 /* max.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
33248   {
33249     M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "max.b", 40,
33250     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33251   },
33252 /* max.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
33253   {
33254     M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "max.b", 48,
33255     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33256   },
33257 /* max.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
33258   {
33259     M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "max.b", 48,
33260     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33261   },
33262 /* max.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
33263   {
33264     M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "max.b", 48,
33265     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33266   },
33267 /* max.b${X} #${Imm-40-QI},${Dsp-24-u16} */
33268   {
33269     M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "max32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "max.b", 48,
33270     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33271   },
33272 /* max.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
33273   {
33274     M32C_INSN_MAX32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "max.b", 56,
33275     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33276   },
33277 /* max.b${X} #${Imm-48-QI},${Dsp-24-u24} */
33278   {
33279     M32C_INSN_MAX32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "max32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "max.b", 56,
33280     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33281   },
33282 /* ste.w ${Dsp-16-u16}[$Dst16An],[a1a0] */
33283   {
33284     M32C_INSN_STE_W_16_16_A1A0_DST16_16_16_AN_RELATIVE_HI, "ste.w-16-16-a1a0-dst16-16-16-An-relative-HI", "ste.w", 32,
33285     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33286   },
33287 /* ste.w ${Dsp-16-u16}[sb],[a1a0] */
33288   {
33289     M32C_INSN_STE_W_16_16_A1A0_DST16_16_16_SB_RELATIVE_HI, "ste.w-16-16-a1a0-dst16-16-16-SB-relative-HI", "ste.w", 32,
33290     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33291   },
33292 /* ste.w ${Dsp-16-u16},[a1a0] */
33293   {
33294     M32C_INSN_STE_W_16_16_A1A0_DST16_16_16_ABSOLUTE_HI, "ste.w-16-16-a1a0-dst16-16-16-absolute-HI", "ste.w", 32,
33295     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33296   },
33297 /* ste.w ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20}[a0] */
33298   {
33299     M32C_INSN_STE_W_16_16_U20A0_DST16_16_16_AN_RELATIVE_HI, "ste.w-16-16-u20a0-dst16-16-16-An-relative-HI", "ste.w", 56,
33300     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33301   },
33302 /* ste.w ${Dsp-16-u16}[sb],${Dsp-32-u20}[a0] */
33303   {
33304     M32C_INSN_STE_W_16_16_U20A0_DST16_16_16_SB_RELATIVE_HI, "ste.w-16-16-u20a0-dst16-16-16-SB-relative-HI", "ste.w", 56,
33305     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33306   },
33307 /* ste.w ${Dsp-16-u16},${Dsp-32-u20}[a0] */
33308   {
33309     M32C_INSN_STE_W_16_16_U20A0_DST16_16_16_ABSOLUTE_HI, "ste.w-16-16-u20a0-dst16-16-16-absolute-HI", "ste.w", 56,
33310     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33311   },
33312 /* ste.w ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20} */
33313   {
33314     M32C_INSN_STE_W_16_16_U20_DST16_16_16_AN_RELATIVE_HI, "ste.w-16-16-u20-dst16-16-16-An-relative-HI", "ste.w", 56,
33315     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33316   },
33317 /* ste.w ${Dsp-16-u16}[sb],${Dsp-32-u20} */
33318   {
33319     M32C_INSN_STE_W_16_16_U20_DST16_16_16_SB_RELATIVE_HI, "ste.w-16-16-u20-dst16-16-16-SB-relative-HI", "ste.w", 56,
33320     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33321   },
33322 /* ste.w ${Dsp-16-u16},${Dsp-32-u20} */
33323   {
33324     M32C_INSN_STE_W_16_16_U20_DST16_16_16_ABSOLUTE_HI, "ste.w-16-16-u20-dst16-16-16-absolute-HI", "ste.w", 56,
33325     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33326   },
33327 /* ste.w ${Dsp-16-u8}[$Dst16An],[a1a0] */
33328   {
33329     M32C_INSN_STE_W_16_8_A1A0_DST16_16_8_AN_RELATIVE_HI, "ste.w-16-8-a1a0-dst16-16-8-An-relative-HI", "ste.w", 24,
33330     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33331   },
33332 /* ste.w ${Dsp-16-u8}[sb],[a1a0] */
33333   {
33334     M32C_INSN_STE_W_16_8_A1A0_DST16_16_8_SB_RELATIVE_HI, "ste.w-16-8-a1a0-dst16-16-8-SB-relative-HI", "ste.w", 24,
33335     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33336   },
33337 /* ste.w ${Dsp-16-s8}[fb],[a1a0] */
33338   {
33339     M32C_INSN_STE_W_16_8_A1A0_DST16_16_8_FB_RELATIVE_HI, "ste.w-16-8-a1a0-dst16-16-8-FB-relative-HI", "ste.w", 24,
33340     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33341   },
33342 /* ste.w ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20}[a0] */
33343   {
33344     M32C_INSN_STE_W_16_8_U20A0_DST16_16_8_AN_RELATIVE_HI, "ste.w-16-8-u20a0-dst16-16-8-An-relative-HI", "ste.w", 48,
33345     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33346   },
33347 /* ste.w ${Dsp-16-u8}[sb],${Dsp-24-u20}[a0] */
33348   {
33349     M32C_INSN_STE_W_16_8_U20A0_DST16_16_8_SB_RELATIVE_HI, "ste.w-16-8-u20a0-dst16-16-8-SB-relative-HI", "ste.w", 48,
33350     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33351   },
33352 /* ste.w ${Dsp-16-s8}[fb],${Dsp-24-u20}[a0] */
33353   {
33354     M32C_INSN_STE_W_16_8_U20A0_DST16_16_8_FB_RELATIVE_HI, "ste.w-16-8-u20a0-dst16-16-8-FB-relative-HI", "ste.w", 48,
33355     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33356   },
33357 /* ste.w ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20} */
33358   {
33359     M32C_INSN_STE_W_16_8_U20_DST16_16_8_AN_RELATIVE_HI, "ste.w-16-8-u20-dst16-16-8-An-relative-HI", "ste.w", 48,
33360     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33361   },
33362 /* ste.w ${Dsp-16-u8}[sb],${Dsp-24-u20} */
33363   {
33364     M32C_INSN_STE_W_16_8_U20_DST16_16_8_SB_RELATIVE_HI, "ste.w-16-8-u20-dst16-16-8-SB-relative-HI", "ste.w", 48,
33365     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33366   },
33367 /* ste.w ${Dsp-16-s8}[fb],${Dsp-24-u20} */
33368   {
33369     M32C_INSN_STE_W_16_8_U20_DST16_16_8_FB_RELATIVE_HI, "ste.w-16-8-u20-dst16-16-8-FB-relative-HI", "ste.w", 48,
33370     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33371   },
33372 /* ste.w $Dst16RnHI,[a1a0] */
33373   {
33374     M32C_INSN_STE_W_BASIC_A1A0_DST16_RN_DIRECT_HI, "ste.w-basic-a1a0-dst16-Rn-direct-HI", "ste.w", 16,
33375     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33376   },
33377 /* ste.w $Dst16AnHI,[a1a0] */
33378   {
33379     M32C_INSN_STE_W_BASIC_A1A0_DST16_AN_DIRECT_HI, "ste.w-basic-a1a0-dst16-An-direct-HI", "ste.w", 16,
33380     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33381   },
33382 /* ste.w [$Dst16An],[a1a0] */
33383   {
33384     M32C_INSN_STE_W_BASIC_A1A0_DST16_AN_INDIRECT_HI, "ste.w-basic-a1a0-dst16-An-indirect-HI", "ste.w", 16,
33385     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33386   },
33387 /* ste.w $Dst16RnHI,${Dsp-16-u20}[a0] */
33388   {
33389     M32C_INSN_STE_W_BASIC_U20A0_DST16_RN_DIRECT_HI, "ste.w-basic-u20a0-dst16-Rn-direct-HI", "ste.w", 40,
33390     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33391   },
33392 /* ste.w $Dst16AnHI,${Dsp-16-u20}[a0] */
33393   {
33394     M32C_INSN_STE_W_BASIC_U20A0_DST16_AN_DIRECT_HI, "ste.w-basic-u20a0-dst16-An-direct-HI", "ste.w", 40,
33395     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33396   },
33397 /* ste.w [$Dst16An],${Dsp-16-u20}[a0] */
33398   {
33399     M32C_INSN_STE_W_BASIC_U20A0_DST16_AN_INDIRECT_HI, "ste.w-basic-u20a0-dst16-An-indirect-HI", "ste.w", 40,
33400     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33401   },
33402 /* ste.w $Dst16RnHI,${Dsp-16-u20} */
33403   {
33404     M32C_INSN_STE_W_BASIC_U20_DST16_RN_DIRECT_HI, "ste.w-basic-u20-dst16-Rn-direct-HI", "ste.w", 40,
33405     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33406   },
33407 /* ste.w $Dst16AnHI,${Dsp-16-u20} */
33408   {
33409     M32C_INSN_STE_W_BASIC_U20_DST16_AN_DIRECT_HI, "ste.w-basic-u20-dst16-An-direct-HI", "ste.w", 40,
33410     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33411   },
33412 /* ste.w [$Dst16An],${Dsp-16-u20} */
33413   {
33414     M32C_INSN_STE_W_BASIC_U20_DST16_AN_INDIRECT_HI, "ste.w-basic-u20-dst16-An-indirect-HI", "ste.w", 40,
33415     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33416   },
33417 /* ste.b ${Dsp-16-u16}[$Dst16An],[a1a0] */
33418   {
33419     M32C_INSN_STE_B_16_16_A1A0_DST16_16_16_AN_RELATIVE_QI, "ste.b-16-16-a1a0-dst16-16-16-An-relative-QI", "ste.b", 32,
33420     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33421   },
33422 /* ste.b ${Dsp-16-u16}[sb],[a1a0] */
33423   {
33424     M32C_INSN_STE_B_16_16_A1A0_DST16_16_16_SB_RELATIVE_QI, "ste.b-16-16-a1a0-dst16-16-16-SB-relative-QI", "ste.b", 32,
33425     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33426   },
33427 /* ste.b ${Dsp-16-u16},[a1a0] */
33428   {
33429     M32C_INSN_STE_B_16_16_A1A0_DST16_16_16_ABSOLUTE_QI, "ste.b-16-16-a1a0-dst16-16-16-absolute-QI", "ste.b", 32,
33430     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33431   },
33432 /* ste.b ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20}[a0] */
33433   {
33434     M32C_INSN_STE_B_16_16_U20A0_DST16_16_16_AN_RELATIVE_QI, "ste.b-16-16-u20a0-dst16-16-16-An-relative-QI", "ste.b", 56,
33435     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33436   },
33437 /* ste.b ${Dsp-16-u16}[sb],${Dsp-32-u20}[a0] */
33438   {
33439     M32C_INSN_STE_B_16_16_U20A0_DST16_16_16_SB_RELATIVE_QI, "ste.b-16-16-u20a0-dst16-16-16-SB-relative-QI", "ste.b", 56,
33440     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33441   },
33442 /* ste.b ${Dsp-16-u16},${Dsp-32-u20}[a0] */
33443   {
33444     M32C_INSN_STE_B_16_16_U20A0_DST16_16_16_ABSOLUTE_QI, "ste.b-16-16-u20a0-dst16-16-16-absolute-QI", "ste.b", 56,
33445     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33446   },
33447 /* ste.b ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20} */
33448   {
33449     M32C_INSN_STE_B_16_16_U20_DST16_16_16_AN_RELATIVE_QI, "ste.b-16-16-u20-dst16-16-16-An-relative-QI", "ste.b", 56,
33450     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33451   },
33452 /* ste.b ${Dsp-16-u16}[sb],${Dsp-32-u20} */
33453   {
33454     M32C_INSN_STE_B_16_16_U20_DST16_16_16_SB_RELATIVE_QI, "ste.b-16-16-u20-dst16-16-16-SB-relative-QI", "ste.b", 56,
33455     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33456   },
33457 /* ste.b ${Dsp-16-u16},${Dsp-32-u20} */
33458   {
33459     M32C_INSN_STE_B_16_16_U20_DST16_16_16_ABSOLUTE_QI, "ste.b-16-16-u20-dst16-16-16-absolute-QI", "ste.b", 56,
33460     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33461   },
33462 /* ste.b ${Dsp-16-u8}[$Dst16An],[a1a0] */
33463   {
33464     M32C_INSN_STE_B_16_8_A1A0_DST16_16_8_AN_RELATIVE_QI, "ste.b-16-8-a1a0-dst16-16-8-An-relative-QI", "ste.b", 24,
33465     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33466   },
33467 /* ste.b ${Dsp-16-u8}[sb],[a1a0] */
33468   {
33469     M32C_INSN_STE_B_16_8_A1A0_DST16_16_8_SB_RELATIVE_QI, "ste.b-16-8-a1a0-dst16-16-8-SB-relative-QI", "ste.b", 24,
33470     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33471   },
33472 /* ste.b ${Dsp-16-s8}[fb],[a1a0] */
33473   {
33474     M32C_INSN_STE_B_16_8_A1A0_DST16_16_8_FB_RELATIVE_QI, "ste.b-16-8-a1a0-dst16-16-8-FB-relative-QI", "ste.b", 24,
33475     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33476   },
33477 /* ste.b ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20}[a0] */
33478   {
33479     M32C_INSN_STE_B_16_8_U20A0_DST16_16_8_AN_RELATIVE_QI, "ste.b-16-8-u20a0-dst16-16-8-An-relative-QI", "ste.b", 48,
33480     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33481   },
33482 /* ste.b ${Dsp-16-u8}[sb],${Dsp-24-u20}[a0] */
33483   {
33484     M32C_INSN_STE_B_16_8_U20A0_DST16_16_8_SB_RELATIVE_QI, "ste.b-16-8-u20a0-dst16-16-8-SB-relative-QI", "ste.b", 48,
33485     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33486   },
33487 /* ste.b ${Dsp-16-s8}[fb],${Dsp-24-u20}[a0] */
33488   {
33489     M32C_INSN_STE_B_16_8_U20A0_DST16_16_8_FB_RELATIVE_QI, "ste.b-16-8-u20a0-dst16-16-8-FB-relative-QI", "ste.b", 48,
33490     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33491   },
33492 /* ste.b ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20} */
33493   {
33494     M32C_INSN_STE_B_16_8_U20_DST16_16_8_AN_RELATIVE_QI, "ste.b-16-8-u20-dst16-16-8-An-relative-QI", "ste.b", 48,
33495     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33496   },
33497 /* ste.b ${Dsp-16-u8}[sb],${Dsp-24-u20} */
33498   {
33499     M32C_INSN_STE_B_16_8_U20_DST16_16_8_SB_RELATIVE_QI, "ste.b-16-8-u20-dst16-16-8-SB-relative-QI", "ste.b", 48,
33500     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33501   },
33502 /* ste.b ${Dsp-16-s8}[fb],${Dsp-24-u20} */
33503   {
33504     M32C_INSN_STE_B_16_8_U20_DST16_16_8_FB_RELATIVE_QI, "ste.b-16-8-u20-dst16-16-8-FB-relative-QI", "ste.b", 48,
33505     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33506   },
33507 /* ste.b $Dst16RnQI,[a1a0] */
33508   {
33509     M32C_INSN_STE_B_BASIC_A1A0_DST16_RN_DIRECT_QI, "ste.b-basic-a1a0-dst16-Rn-direct-QI", "ste.b", 16,
33510     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33511   },
33512 /* ste.b $Dst16AnQI,[a1a0] */
33513   {
33514     M32C_INSN_STE_B_BASIC_A1A0_DST16_AN_DIRECT_QI, "ste.b-basic-a1a0-dst16-An-direct-QI", "ste.b", 16,
33515     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33516   },
33517 /* ste.b [$Dst16An],[a1a0] */
33518   {
33519     M32C_INSN_STE_B_BASIC_A1A0_DST16_AN_INDIRECT_QI, "ste.b-basic-a1a0-dst16-An-indirect-QI", "ste.b", 16,
33520     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33521   },
33522 /* ste.b $Dst16RnQI,${Dsp-16-u20}[a0] */
33523   {
33524     M32C_INSN_STE_B_BASIC_U20A0_DST16_RN_DIRECT_QI, "ste.b-basic-u20a0-dst16-Rn-direct-QI", "ste.b", 40,
33525     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33526   },
33527 /* ste.b $Dst16AnQI,${Dsp-16-u20}[a0] */
33528   {
33529     M32C_INSN_STE_B_BASIC_U20A0_DST16_AN_DIRECT_QI, "ste.b-basic-u20a0-dst16-An-direct-QI", "ste.b", 40,
33530     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33531   },
33532 /* ste.b [$Dst16An],${Dsp-16-u20}[a0] */
33533   {
33534     M32C_INSN_STE_B_BASIC_U20A0_DST16_AN_INDIRECT_QI, "ste.b-basic-u20a0-dst16-An-indirect-QI", "ste.b", 40,
33535     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33536   },
33537 /* ste.b $Dst16RnQI,${Dsp-16-u20} */
33538   {
33539     M32C_INSN_STE_B_BASIC_U20_DST16_RN_DIRECT_QI, "ste.b-basic-u20-dst16-Rn-direct-QI", "ste.b", 40,
33540     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33541   },
33542 /* ste.b $Dst16AnQI,${Dsp-16-u20} */
33543   {
33544     M32C_INSN_STE_B_BASIC_U20_DST16_AN_DIRECT_QI, "ste.b-basic-u20-dst16-An-direct-QI", "ste.b", 40,
33545     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33546   },
33547 /* ste.b [$Dst16An],${Dsp-16-u20} */
33548   {
33549     M32C_INSN_STE_B_BASIC_U20_DST16_AN_INDIRECT_QI, "ste.b-basic-u20-dst16-An-indirect-QI", "ste.b", 40,
33550     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33551   },
33552 /* lde.w [a1a0],${Dsp-16-u16}[$Dst16An] */
33553   {
33554     M32C_INSN_LDE_W_16_16_A1A0_DST16_16_16_AN_RELATIVE_HI, "lde.w-16-16-a1a0-dst16-16-16-An-relative-HI", "lde.w", 32,
33555     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33556   },
33557 /* lde.w [a1a0],${Dsp-16-u16}[sb] */
33558   {
33559     M32C_INSN_LDE_W_16_16_A1A0_DST16_16_16_SB_RELATIVE_HI, "lde.w-16-16-a1a0-dst16-16-16-SB-relative-HI", "lde.w", 32,
33560     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33561   },
33562 /* lde.w [a1a0],${Dsp-16-u16} */
33563   {
33564     M32C_INSN_LDE_W_16_16_A1A0_DST16_16_16_ABSOLUTE_HI, "lde.w-16-16-a1a0-dst16-16-16-absolute-HI", "lde.w", 32,
33565     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33566   },
33567 /* lde.w ${Dsp-32-u20}[a0],${Dsp-16-u16}[$Dst16An] */
33568   {
33569     M32C_INSN_LDE_W_16_16_U20A0_DST16_16_16_AN_RELATIVE_HI, "lde.w-16-16-u20a0-dst16-16-16-An-relative-HI", "lde.w", 56,
33570     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33571   },
33572 /* lde.w ${Dsp-32-u20}[a0],${Dsp-16-u16}[sb] */
33573   {
33574     M32C_INSN_LDE_W_16_16_U20A0_DST16_16_16_SB_RELATIVE_HI, "lde.w-16-16-u20a0-dst16-16-16-SB-relative-HI", "lde.w", 56,
33575     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33576   },
33577 /* lde.w ${Dsp-32-u20}[a0],${Dsp-16-u16} */
33578   {
33579     M32C_INSN_LDE_W_16_16_U20A0_DST16_16_16_ABSOLUTE_HI, "lde.w-16-16-u20a0-dst16-16-16-absolute-HI", "lde.w", 56,
33580     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33581   },
33582 /* lde.w ${Dsp-32-u20},${Dsp-16-u16}[$Dst16An] */
33583   {
33584     M32C_INSN_LDE_W_16_16_U20_DST16_16_16_AN_RELATIVE_HI, "lde.w-16-16-u20-dst16-16-16-An-relative-HI", "lde.w", 56,
33585     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33586   },
33587 /* lde.w ${Dsp-32-u20},${Dsp-16-u16}[sb] */
33588   {
33589     M32C_INSN_LDE_W_16_16_U20_DST16_16_16_SB_RELATIVE_HI, "lde.w-16-16-u20-dst16-16-16-SB-relative-HI", "lde.w", 56,
33590     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33591   },
33592 /* lde.w ${Dsp-32-u20},${Dsp-16-u16} */
33593   {
33594     M32C_INSN_LDE_W_16_16_U20_DST16_16_16_ABSOLUTE_HI, "lde.w-16-16-u20-dst16-16-16-absolute-HI", "lde.w", 56,
33595     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33596   },
33597 /* lde.w [a1a0],${Dsp-16-u8}[$Dst16An] */
33598   {
33599     M32C_INSN_LDE_W_16_8_A1A0_DST16_16_8_AN_RELATIVE_HI, "lde.w-16-8-a1a0-dst16-16-8-An-relative-HI", "lde.w", 24,
33600     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33601   },
33602 /* lde.w [a1a0],${Dsp-16-u8}[sb] */
33603   {
33604     M32C_INSN_LDE_W_16_8_A1A0_DST16_16_8_SB_RELATIVE_HI, "lde.w-16-8-a1a0-dst16-16-8-SB-relative-HI", "lde.w", 24,
33605     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33606   },
33607 /* lde.w [a1a0],${Dsp-16-s8}[fb] */
33608   {
33609     M32C_INSN_LDE_W_16_8_A1A0_DST16_16_8_FB_RELATIVE_HI, "lde.w-16-8-a1a0-dst16-16-8-FB-relative-HI", "lde.w", 24,
33610     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33611   },
33612 /* lde.w ${Dsp-24-u20}[a0],${Dsp-16-u8}[$Dst16An] */
33613   {
33614     M32C_INSN_LDE_W_16_8_U20A0_DST16_16_8_AN_RELATIVE_HI, "lde.w-16-8-u20a0-dst16-16-8-An-relative-HI", "lde.w", 48,
33615     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33616   },
33617 /* lde.w ${Dsp-24-u20}[a0],${Dsp-16-u8}[sb] */
33618   {
33619     M32C_INSN_LDE_W_16_8_U20A0_DST16_16_8_SB_RELATIVE_HI, "lde.w-16-8-u20a0-dst16-16-8-SB-relative-HI", "lde.w", 48,
33620     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33621   },
33622 /* lde.w ${Dsp-24-u20}[a0],${Dsp-16-s8}[fb] */
33623   {
33624     M32C_INSN_LDE_W_16_8_U20A0_DST16_16_8_FB_RELATIVE_HI, "lde.w-16-8-u20a0-dst16-16-8-FB-relative-HI", "lde.w", 48,
33625     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33626   },
33627 /* lde.w ${Dsp-24-u20},${Dsp-16-u8}[$Dst16An] */
33628   {
33629     M32C_INSN_LDE_W_16_8_U20_DST16_16_8_AN_RELATIVE_HI, "lde.w-16-8-u20-dst16-16-8-An-relative-HI", "lde.w", 48,
33630     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33631   },
33632 /* lde.w ${Dsp-24-u20},${Dsp-16-u8}[sb] */
33633   {
33634     M32C_INSN_LDE_W_16_8_U20_DST16_16_8_SB_RELATIVE_HI, "lde.w-16-8-u20-dst16-16-8-SB-relative-HI", "lde.w", 48,
33635     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33636   },
33637 /* lde.w ${Dsp-24-u20},${Dsp-16-s8}[fb] */
33638   {
33639     M32C_INSN_LDE_W_16_8_U20_DST16_16_8_FB_RELATIVE_HI, "lde.w-16-8-u20-dst16-16-8-FB-relative-HI", "lde.w", 48,
33640     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33641   },
33642 /* lde.w [a1a0],$Dst16RnHI */
33643   {
33644     M32C_INSN_LDE_W_BASIC_A1A0_DST16_RN_DIRECT_HI, "lde.w-basic-a1a0-dst16-Rn-direct-HI", "lde.w", 16,
33645     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33646   },
33647 /* lde.w [a1a0],$Dst16AnHI */
33648   {
33649     M32C_INSN_LDE_W_BASIC_A1A0_DST16_AN_DIRECT_HI, "lde.w-basic-a1a0-dst16-An-direct-HI", "lde.w", 16,
33650     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33651   },
33652 /* lde.w [a1a0],[$Dst16An] */
33653   {
33654     M32C_INSN_LDE_W_BASIC_A1A0_DST16_AN_INDIRECT_HI, "lde.w-basic-a1a0-dst16-An-indirect-HI", "lde.w", 16,
33655     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33656   },
33657 /* lde.w ${Dsp-16-u20}[a0],$Dst16RnHI */
33658   {
33659     M32C_INSN_LDE_W_BASIC_U20A0_DST16_RN_DIRECT_HI, "lde.w-basic-u20a0-dst16-Rn-direct-HI", "lde.w", 40,
33660     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33661   },
33662 /* lde.w ${Dsp-16-u20}[a0],$Dst16AnHI */
33663   {
33664     M32C_INSN_LDE_W_BASIC_U20A0_DST16_AN_DIRECT_HI, "lde.w-basic-u20a0-dst16-An-direct-HI", "lde.w", 40,
33665     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33666   },
33667 /* lde.w ${Dsp-16-u20}[a0],[$Dst16An] */
33668   {
33669     M32C_INSN_LDE_W_BASIC_U20A0_DST16_AN_INDIRECT_HI, "lde.w-basic-u20a0-dst16-An-indirect-HI", "lde.w", 40,
33670     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33671   },
33672 /* lde.w ${Dsp-16-u20},$Dst16RnHI */
33673   {
33674     M32C_INSN_LDE_W_BASIC_U20_DST16_RN_DIRECT_HI, "lde.w-basic-u20-dst16-Rn-direct-HI", "lde.w", 40,
33675     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33676   },
33677 /* lde.w ${Dsp-16-u20},$Dst16AnHI */
33678   {
33679     M32C_INSN_LDE_W_BASIC_U20_DST16_AN_DIRECT_HI, "lde.w-basic-u20-dst16-An-direct-HI", "lde.w", 40,
33680     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33681   },
33682 /* lde.w ${Dsp-16-u20},[$Dst16An] */
33683   {
33684     M32C_INSN_LDE_W_BASIC_U20_DST16_AN_INDIRECT_HI, "lde.w-basic-u20-dst16-An-indirect-HI", "lde.w", 40,
33685     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33686   },
33687 /* lde.b [a1a0],${Dsp-16-u16}[$Dst16An] */
33688   {
33689     M32C_INSN_LDE_B_16_16_A1A0_DST16_16_16_AN_RELATIVE_QI, "lde.b-16-16-a1a0-dst16-16-16-An-relative-QI", "lde.b", 32,
33690     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33691   },
33692 /* lde.b [a1a0],${Dsp-16-u16}[sb] */
33693   {
33694     M32C_INSN_LDE_B_16_16_A1A0_DST16_16_16_SB_RELATIVE_QI, "lde.b-16-16-a1a0-dst16-16-16-SB-relative-QI", "lde.b", 32,
33695     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33696   },
33697 /* lde.b [a1a0],${Dsp-16-u16} */
33698   {
33699     M32C_INSN_LDE_B_16_16_A1A0_DST16_16_16_ABSOLUTE_QI, "lde.b-16-16-a1a0-dst16-16-16-absolute-QI", "lde.b", 32,
33700     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33701   },
33702 /* lde.b ${Dsp-32-u20}[a0],${Dsp-16-u16}[$Dst16An] */
33703   {
33704     M32C_INSN_LDE_B_16_16_U20A0_DST16_16_16_AN_RELATIVE_QI, "lde.b-16-16-u20a0-dst16-16-16-An-relative-QI", "lde.b", 56,
33705     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33706   },
33707 /* lde.b ${Dsp-32-u20}[a0],${Dsp-16-u16}[sb] */
33708   {
33709     M32C_INSN_LDE_B_16_16_U20A0_DST16_16_16_SB_RELATIVE_QI, "lde.b-16-16-u20a0-dst16-16-16-SB-relative-QI", "lde.b", 56,
33710     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33711   },
33712 /* lde.b ${Dsp-32-u20}[a0],${Dsp-16-u16} */
33713   {
33714     M32C_INSN_LDE_B_16_16_U20A0_DST16_16_16_ABSOLUTE_QI, "lde.b-16-16-u20a0-dst16-16-16-absolute-QI", "lde.b", 56,
33715     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33716   },
33717 /* lde.b ${Dsp-32-u20},${Dsp-16-u16}[$Dst16An] */
33718   {
33719     M32C_INSN_LDE_B_16_16_U20_DST16_16_16_AN_RELATIVE_QI, "lde.b-16-16-u20-dst16-16-16-An-relative-QI", "lde.b", 56,
33720     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33721   },
33722 /* lde.b ${Dsp-32-u20},${Dsp-16-u16}[sb] */
33723   {
33724     M32C_INSN_LDE_B_16_16_U20_DST16_16_16_SB_RELATIVE_QI, "lde.b-16-16-u20-dst16-16-16-SB-relative-QI", "lde.b", 56,
33725     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33726   },
33727 /* lde.b ${Dsp-32-u20},${Dsp-16-u16} */
33728   {
33729     M32C_INSN_LDE_B_16_16_U20_DST16_16_16_ABSOLUTE_QI, "lde.b-16-16-u20-dst16-16-16-absolute-QI", "lde.b", 56,
33730     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33731   },
33732 /* lde.b [a1a0],${Dsp-16-u8}[$Dst16An] */
33733   {
33734     M32C_INSN_LDE_B_16_8_A1A0_DST16_16_8_AN_RELATIVE_QI, "lde.b-16-8-a1a0-dst16-16-8-An-relative-QI", "lde.b", 24,
33735     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33736   },
33737 /* lde.b [a1a0],${Dsp-16-u8}[sb] */
33738   {
33739     M32C_INSN_LDE_B_16_8_A1A0_DST16_16_8_SB_RELATIVE_QI, "lde.b-16-8-a1a0-dst16-16-8-SB-relative-QI", "lde.b", 24,
33740     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33741   },
33742 /* lde.b [a1a0],${Dsp-16-s8}[fb] */
33743   {
33744     M32C_INSN_LDE_B_16_8_A1A0_DST16_16_8_FB_RELATIVE_QI, "lde.b-16-8-a1a0-dst16-16-8-FB-relative-QI", "lde.b", 24,
33745     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33746   },
33747 /* lde.b ${Dsp-24-u20}[a0],${Dsp-16-u8}[$Dst16An] */
33748   {
33749     M32C_INSN_LDE_B_16_8_U20A0_DST16_16_8_AN_RELATIVE_QI, "lde.b-16-8-u20a0-dst16-16-8-An-relative-QI", "lde.b", 48,
33750     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33751   },
33752 /* lde.b ${Dsp-24-u20}[a0],${Dsp-16-u8}[sb] */
33753   {
33754     M32C_INSN_LDE_B_16_8_U20A0_DST16_16_8_SB_RELATIVE_QI, "lde.b-16-8-u20a0-dst16-16-8-SB-relative-QI", "lde.b", 48,
33755     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33756   },
33757 /* lde.b ${Dsp-24-u20}[a0],${Dsp-16-s8}[fb] */
33758   {
33759     M32C_INSN_LDE_B_16_8_U20A0_DST16_16_8_FB_RELATIVE_QI, "lde.b-16-8-u20a0-dst16-16-8-FB-relative-QI", "lde.b", 48,
33760     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33761   },
33762 /* lde.b ${Dsp-24-u20},${Dsp-16-u8}[$Dst16An] */
33763   {
33764     M32C_INSN_LDE_B_16_8_U20_DST16_16_8_AN_RELATIVE_QI, "lde.b-16-8-u20-dst16-16-8-An-relative-QI", "lde.b", 48,
33765     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33766   },
33767 /* lde.b ${Dsp-24-u20},${Dsp-16-u8}[sb] */
33768   {
33769     M32C_INSN_LDE_B_16_8_U20_DST16_16_8_SB_RELATIVE_QI, "lde.b-16-8-u20-dst16-16-8-SB-relative-QI", "lde.b", 48,
33770     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33771   },
33772 /* lde.b ${Dsp-24-u20},${Dsp-16-s8}[fb] */
33773   {
33774     M32C_INSN_LDE_B_16_8_U20_DST16_16_8_FB_RELATIVE_QI, "lde.b-16-8-u20-dst16-16-8-FB-relative-QI", "lde.b", 48,
33775     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33776   },
33777 /* lde.b [a1a0],$Dst16RnQI */
33778   {
33779     M32C_INSN_LDE_B_BASIC_A1A0_DST16_RN_DIRECT_QI, "lde.b-basic-a1a0-dst16-Rn-direct-QI", "lde.b", 16,
33780     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33781   },
33782 /* lde.b [a1a0],$Dst16AnQI */
33783   {
33784     M32C_INSN_LDE_B_BASIC_A1A0_DST16_AN_DIRECT_QI, "lde.b-basic-a1a0-dst16-An-direct-QI", "lde.b", 16,
33785     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33786   },
33787 /* lde.b [a1a0],[$Dst16An] */
33788   {
33789     M32C_INSN_LDE_B_BASIC_A1A0_DST16_AN_INDIRECT_QI, "lde.b-basic-a1a0-dst16-An-indirect-QI", "lde.b", 16,
33790     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33791   },
33792 /* lde.b ${Dsp-16-u20}[a0],$Dst16RnQI */
33793   {
33794     M32C_INSN_LDE_B_BASIC_U20A0_DST16_RN_DIRECT_QI, "lde.b-basic-u20a0-dst16-Rn-direct-QI", "lde.b", 40,
33795     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33796   },
33797 /* lde.b ${Dsp-16-u20}[a0],$Dst16AnQI */
33798   {
33799     M32C_INSN_LDE_B_BASIC_U20A0_DST16_AN_DIRECT_QI, "lde.b-basic-u20a0-dst16-An-direct-QI", "lde.b", 40,
33800     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33801   },
33802 /* lde.b ${Dsp-16-u20}[a0],[$Dst16An] */
33803   {
33804     M32C_INSN_LDE_B_BASIC_U20A0_DST16_AN_INDIRECT_QI, "lde.b-basic-u20a0-dst16-An-indirect-QI", "lde.b", 40,
33805     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33806   },
33807 /* lde.b ${Dsp-16-u20},$Dst16RnQI */
33808   {
33809     M32C_INSN_LDE_B_BASIC_U20_DST16_RN_DIRECT_QI, "lde.b-basic-u20-dst16-Rn-direct-QI", "lde.b", 40,
33810     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33811   },
33812 /* lde.b ${Dsp-16-u20},$Dst16AnQI */
33813   {
33814     M32C_INSN_LDE_B_BASIC_U20_DST16_AN_DIRECT_QI, "lde.b-basic-u20-dst16-An-direct-QI", "lde.b", 40,
33815     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33816   },
33817 /* lde.b ${Dsp-16-u20},[$Dst16An] */
33818   {
33819     M32C_INSN_LDE_B_BASIC_U20_DST16_AN_INDIRECT_QI, "lde.b-basic-u20-dst16-An-indirect-QI", "lde.b", 40,
33820     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33821   },
33822 /* stc ${cr3-Prefixed-32},$Dst32RnPrefixedSI */
33823   {
33824     M32C_INSN_STC32_SRC_CR3_DST32_RN_DIRECT_PREFIXED_SI, "stc32.src-cr3-dst32-Rn-direct-Prefixed-SI", "stc", 24,
33825     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33826   },
33827 /* stc ${cr3-Prefixed-32},$Dst32AnPrefixedSI */
33828   {
33829     M32C_INSN_STC32_SRC_CR3_DST32_AN_DIRECT_PREFIXED_SI, "stc32.src-cr3-dst32-An-direct-Prefixed-SI", "stc", 24,
33830     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33831   },
33832 /* stc ${cr3-Prefixed-32},[$Dst32AnPrefixed] */
33833   {
33834     M32C_INSN_STC32_SRC_CR3_DST32_AN_INDIRECT_PREFIXED_SI, "stc32.src-cr3-dst32-An-indirect-Prefixed-SI", "stc", 24,
33835     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33836   },
33837 /* stc ${cr3-Prefixed-32},${Dsp-24-u8}[$Dst32AnPrefixed] */
33838   {
33839     M32C_INSN_STC32_SRC_CR3_DST32_24_8_AN_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-8-An-relative-Prefixed-SI", "stc", 32,
33840     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33841   },
33842 /* stc ${cr3-Prefixed-32},${Dsp-24-u16}[$Dst32AnPrefixed] */
33843   {
33844     M32C_INSN_STC32_SRC_CR3_DST32_24_16_AN_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-16-An-relative-Prefixed-SI", "stc", 40,
33845     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33846   },
33847 /* stc ${cr3-Prefixed-32},${Dsp-24-u24}[$Dst32AnPrefixed] */
33848   {
33849     M32C_INSN_STC32_SRC_CR3_DST32_24_24_AN_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-24-An-relative-Prefixed-SI", "stc", 48,
33850     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33851   },
33852 /* stc ${cr3-Prefixed-32},${Dsp-24-u8}[sb] */
33853   {
33854     M32C_INSN_STC32_SRC_CR3_DST32_24_8_SB_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-8-SB-relative-Prefixed-SI", "stc", 32,
33855     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33856   },
33857 /* stc ${cr3-Prefixed-32},${Dsp-24-u16}[sb] */
33858   {
33859     M32C_INSN_STC32_SRC_CR3_DST32_24_16_SB_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-16-SB-relative-Prefixed-SI", "stc", 40,
33860     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33861   },
33862 /* stc ${cr3-Prefixed-32},${Dsp-24-s8}[fb] */
33863   {
33864     M32C_INSN_STC32_SRC_CR3_DST32_24_8_FB_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-8-FB-relative-Prefixed-SI", "stc", 32,
33865     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33866   },
33867 /* stc ${cr3-Prefixed-32},${Dsp-24-s16}[fb] */
33868   {
33869     M32C_INSN_STC32_SRC_CR3_DST32_24_16_FB_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-16-FB-relative-Prefixed-SI", "stc", 40,
33870     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33871   },
33872 /* stc ${cr3-Prefixed-32},${Dsp-24-u16} */
33873   {
33874     M32C_INSN_STC32_SRC_CR3_DST32_24_16_ABSOLUTE_PREFIXED_SI, "stc32.src-cr3-dst32-24-16-absolute-Prefixed-SI", "stc", 40,
33875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33876   },
33877 /* stc ${cr3-Prefixed-32},${Dsp-24-u24} */
33878   {
33879     M32C_INSN_STC32_SRC_CR3_DST32_24_24_ABSOLUTE_PREFIXED_SI, "stc32.src-cr3-dst32-24-24-absolute-Prefixed-SI", "stc", 48,
33880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33881   },
33882 /* stc ${cr2-32},$Dst32RnUnprefixedSI */
33883   {
33884     M32C_INSN_STC32_SRC_CR2_DST32_RN_DIRECT_UNPREFIXED_SI, "stc32.src-cr2-dst32-Rn-direct-Unprefixed-SI", "stc", 16,
33885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33886   },
33887 /* stc ${cr2-32},$Dst32AnUnprefixedSI */
33888   {
33889     M32C_INSN_STC32_SRC_CR2_DST32_AN_DIRECT_UNPREFIXED_SI, "stc32.src-cr2-dst32-An-direct-Unprefixed-SI", "stc", 16,
33890     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33891   },
33892 /* stc ${cr2-32},[$Dst32AnUnprefixed] */
33893   {
33894     M32C_INSN_STC32_SRC_CR2_DST32_AN_INDIRECT_UNPREFIXED_SI, "stc32.src-cr2-dst32-An-indirect-Unprefixed-SI", "stc", 16,
33895     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33896   },
33897 /* stc ${cr2-32},${Dsp-16-u8}[$Dst32AnUnprefixed] */
33898   {
33899     M32C_INSN_STC32_SRC_CR2_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-8-An-relative-Unprefixed-SI", "stc", 24,
33900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33901   },
33902 /* stc ${cr2-32},${Dsp-16-u16}[$Dst32AnUnprefixed] */
33903   {
33904     M32C_INSN_STC32_SRC_CR2_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-16-An-relative-Unprefixed-SI", "stc", 32,
33905     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33906   },
33907 /* stc ${cr2-32},${Dsp-16-u24}[$Dst32AnUnprefixed] */
33908   {
33909     M32C_INSN_STC32_SRC_CR2_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-24-An-relative-Unprefixed-SI", "stc", 40,
33910     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33911   },
33912 /* stc ${cr2-32},${Dsp-16-u8}[sb] */
33913   {
33914     M32C_INSN_STC32_SRC_CR2_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-8-SB-relative-Unprefixed-SI", "stc", 24,
33915     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33916   },
33917 /* stc ${cr2-32},${Dsp-16-u16}[sb] */
33918   {
33919     M32C_INSN_STC32_SRC_CR2_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-16-SB-relative-Unprefixed-SI", "stc", 32,
33920     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33921   },
33922 /* stc ${cr2-32},${Dsp-16-s8}[fb] */
33923   {
33924     M32C_INSN_STC32_SRC_CR2_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-8-FB-relative-Unprefixed-SI", "stc", 24,
33925     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33926   },
33927 /* stc ${cr2-32},${Dsp-16-s16}[fb] */
33928   {
33929     M32C_INSN_STC32_SRC_CR2_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-16-FB-relative-Unprefixed-SI", "stc", 32,
33930     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33931   },
33932 /* stc ${cr2-32},${Dsp-16-u16} */
33933   {
33934     M32C_INSN_STC32_SRC_CR2_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-16-absolute-Unprefixed-SI", "stc", 32,
33935     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33936   },
33937 /* stc ${cr2-32},${Dsp-16-u24} */
33938   {
33939     M32C_INSN_STC32_SRC_CR2_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-24-absolute-Unprefixed-SI", "stc", 40,
33940     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33941   },
33942 /* stc ${cr1-Prefixed-32},$Dst32RnPrefixedHI */
33943   {
33944     M32C_INSN_STC32_SRC_CR1_DST32_RN_DIRECT_PREFIXED_HI, "stc32.src-cr1-dst32-Rn-direct-Prefixed-HI", "stc", 24,
33945     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33946   },
33947 /* stc ${cr1-Prefixed-32},$Dst32AnPrefixedHI */
33948   {
33949     M32C_INSN_STC32_SRC_CR1_DST32_AN_DIRECT_PREFIXED_HI, "stc32.src-cr1-dst32-An-direct-Prefixed-HI", "stc", 24,
33950     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33951   },
33952 /* stc ${cr1-Prefixed-32},[$Dst32AnPrefixed] */
33953   {
33954     M32C_INSN_STC32_SRC_CR1_DST32_AN_INDIRECT_PREFIXED_HI, "stc32.src-cr1-dst32-An-indirect-Prefixed-HI", "stc", 24,
33955     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33956   },
33957 /* stc ${cr1-Prefixed-32},${Dsp-24-u8}[$Dst32AnPrefixed] */
33958   {
33959     M32C_INSN_STC32_SRC_CR1_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-8-An-relative-Prefixed-HI", "stc", 32,
33960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33961   },
33962 /* stc ${cr1-Prefixed-32},${Dsp-24-u16}[$Dst32AnPrefixed] */
33963   {
33964     M32C_INSN_STC32_SRC_CR1_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-16-An-relative-Prefixed-HI", "stc", 40,
33965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33966   },
33967 /* stc ${cr1-Prefixed-32},${Dsp-24-u24}[$Dst32AnPrefixed] */
33968   {
33969     M32C_INSN_STC32_SRC_CR1_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-24-An-relative-Prefixed-HI", "stc", 48,
33970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33971   },
33972 /* stc ${cr1-Prefixed-32},${Dsp-24-u8}[sb] */
33973   {
33974     M32C_INSN_STC32_SRC_CR1_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-8-SB-relative-Prefixed-HI", "stc", 32,
33975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33976   },
33977 /* stc ${cr1-Prefixed-32},${Dsp-24-u16}[sb] */
33978   {
33979     M32C_INSN_STC32_SRC_CR1_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-16-SB-relative-Prefixed-HI", "stc", 40,
33980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33981   },
33982 /* stc ${cr1-Prefixed-32},${Dsp-24-s8}[fb] */
33983   {
33984     M32C_INSN_STC32_SRC_CR1_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-8-FB-relative-Prefixed-HI", "stc", 32,
33985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33986   },
33987 /* stc ${cr1-Prefixed-32},${Dsp-24-s16}[fb] */
33988   {
33989     M32C_INSN_STC32_SRC_CR1_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-16-FB-relative-Prefixed-HI", "stc", 40,
33990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33991   },
33992 /* stc ${cr1-Prefixed-32},${Dsp-24-u16} */
33993   {
33994     M32C_INSN_STC32_SRC_CR1_DST32_24_16_ABSOLUTE_PREFIXED_HI, "stc32.src-cr1-dst32-24-16-absolute-Prefixed-HI", "stc", 40,
33995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33996   },
33997 /* stc ${cr1-Prefixed-32},${Dsp-24-u24} */
33998   {
33999     M32C_INSN_STC32_SRC_CR1_DST32_24_24_ABSOLUTE_PREFIXED_HI, "stc32.src-cr1-dst32-24-24-absolute-Prefixed-HI", "stc", 48,
34000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34001   },
34002 /* stc pc,$Dst16RnHI */
34003   {
34004     M32C_INSN_STC16_PC_DST16_RN_DIRECT_HI, "stc16.pc-dst16-Rn-direct-HI", "stc", 16,
34005     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34006   },
34007 /* stc pc,$Dst16AnHI */
34008   {
34009     M32C_INSN_STC16_PC_DST16_AN_DIRECT_HI, "stc16.pc-dst16-An-direct-HI", "stc", 16,
34010     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34011   },
34012 /* stc pc,[$Dst16An] */
34013   {
34014     M32C_INSN_STC16_PC_DST16_AN_INDIRECT_HI, "stc16.pc-dst16-An-indirect-HI", "stc", 16,
34015     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34016   },
34017 /* stc pc,${Dsp-16-u8}[$Dst16An] */
34018   {
34019     M32C_INSN_STC16_PC_DST16_16_8_AN_RELATIVE_HI, "stc16.pc-dst16-16-8-An-relative-HI", "stc", 24,
34020     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34021   },
34022 /* stc pc,${Dsp-16-u16}[$Dst16An] */
34023   {
34024     M32C_INSN_STC16_PC_DST16_16_16_AN_RELATIVE_HI, "stc16.pc-dst16-16-16-An-relative-HI", "stc", 32,
34025     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34026   },
34027 /* stc pc,${Dsp-16-u8}[sb] */
34028   {
34029     M32C_INSN_STC16_PC_DST16_16_8_SB_RELATIVE_HI, "stc16.pc-dst16-16-8-SB-relative-HI", "stc", 24,
34030     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34031   },
34032 /* stc pc,${Dsp-16-u16}[sb] */
34033   {
34034     M32C_INSN_STC16_PC_DST16_16_16_SB_RELATIVE_HI, "stc16.pc-dst16-16-16-SB-relative-HI", "stc", 32,
34035     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34036   },
34037 /* stc pc,${Dsp-16-s8}[fb] */
34038   {
34039     M32C_INSN_STC16_PC_DST16_16_8_FB_RELATIVE_HI, "stc16.pc-dst16-16-8-FB-relative-HI", "stc", 24,
34040     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34041   },
34042 /* stc pc,${Dsp-16-u16} */
34043   {
34044     M32C_INSN_STC16_PC_DST16_16_16_ABSOLUTE_HI, "stc16.pc-dst16-16-16-absolute-HI", "stc", 32,
34045     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34046   },
34047 /* stc ${cr16},$Dst16RnHI */
34048   {
34049     M32C_INSN_STC16_SRC_DST16_RN_DIRECT_HI, "stc16.src-dst16-Rn-direct-HI", "stc", 16,
34050     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34051   },
34052 /* stc ${cr16},$Dst16AnHI */
34053   {
34054     M32C_INSN_STC16_SRC_DST16_AN_DIRECT_HI, "stc16.src-dst16-An-direct-HI", "stc", 16,
34055     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34056   },
34057 /* stc ${cr16},[$Dst16An] */
34058   {
34059     M32C_INSN_STC16_SRC_DST16_AN_INDIRECT_HI, "stc16.src-dst16-An-indirect-HI", "stc", 16,
34060     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34061   },
34062 /* stc ${cr16},${Dsp-16-u8}[$Dst16An] */
34063   {
34064     M32C_INSN_STC16_SRC_DST16_16_8_AN_RELATIVE_HI, "stc16.src-dst16-16-8-An-relative-HI", "stc", 24,
34065     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34066   },
34067 /* stc ${cr16},${Dsp-16-u16}[$Dst16An] */
34068   {
34069     M32C_INSN_STC16_SRC_DST16_16_16_AN_RELATIVE_HI, "stc16.src-dst16-16-16-An-relative-HI", "stc", 32,
34070     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34071   },
34072 /* stc ${cr16},${Dsp-16-u8}[sb] */
34073   {
34074     M32C_INSN_STC16_SRC_DST16_16_8_SB_RELATIVE_HI, "stc16.src-dst16-16-8-SB-relative-HI", "stc", 24,
34075     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34076   },
34077 /* stc ${cr16},${Dsp-16-u16}[sb] */
34078   {
34079     M32C_INSN_STC16_SRC_DST16_16_16_SB_RELATIVE_HI, "stc16.src-dst16-16-16-SB-relative-HI", "stc", 32,
34080     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34081   },
34082 /* stc ${cr16},${Dsp-16-s8}[fb] */
34083   {
34084     M32C_INSN_STC16_SRC_DST16_16_8_FB_RELATIVE_HI, "stc16.src-dst16-16-8-FB-relative-HI", "stc", 24,
34085     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34086   },
34087 /* stc ${cr16},${Dsp-16-u16} */
34088   {
34089     M32C_INSN_STC16_SRC_DST16_16_16_ABSOLUTE_HI, "stc16.src-dst16-16-16-absolute-HI", "stc", 32,
34090     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34091   },
34092 /* ldc $Dst32RnPrefixedSI,${cr3-Prefixed-32} */
34093   {
34094     M32C_INSN_LDC32_SRC_CR3_DST32_RN_DIRECT_PREFIXED_SI, "ldc32.src-cr3-dst32-Rn-direct-Prefixed-SI", "ldc", 24,
34095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34096   },
34097 /* ldc $Dst32AnPrefixedSI,${cr3-Prefixed-32} */
34098   {
34099     M32C_INSN_LDC32_SRC_CR3_DST32_AN_DIRECT_PREFIXED_SI, "ldc32.src-cr3-dst32-An-direct-Prefixed-SI", "ldc", 24,
34100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34101   },
34102 /* ldc [$Dst32AnPrefixed],${cr3-Prefixed-32} */
34103   {
34104     M32C_INSN_LDC32_SRC_CR3_DST32_AN_INDIRECT_PREFIXED_SI, "ldc32.src-cr3-dst32-An-indirect-Prefixed-SI", "ldc", 24,
34105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34106   },
34107 /* ldc ${Dsp-24-u8}[$Dst32AnPrefixed],${cr3-Prefixed-32} */
34108   {
34109     M32C_INSN_LDC32_SRC_CR3_DST32_24_8_AN_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-8-An-relative-Prefixed-SI", "ldc", 32,
34110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34111   },
34112 /* ldc ${Dsp-24-u16}[$Dst32AnPrefixed],${cr3-Prefixed-32} */
34113   {
34114     M32C_INSN_LDC32_SRC_CR3_DST32_24_16_AN_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-16-An-relative-Prefixed-SI", "ldc", 40,
34115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34116   },
34117 /* ldc ${Dsp-24-u24}[$Dst32AnPrefixed],${cr3-Prefixed-32} */
34118   {
34119     M32C_INSN_LDC32_SRC_CR3_DST32_24_24_AN_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-24-An-relative-Prefixed-SI", "ldc", 48,
34120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34121   },
34122 /* ldc ${Dsp-24-u8}[sb],${cr3-Prefixed-32} */
34123   {
34124     M32C_INSN_LDC32_SRC_CR3_DST32_24_8_SB_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-8-SB-relative-Prefixed-SI", "ldc", 32,
34125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34126   },
34127 /* ldc ${Dsp-24-u16}[sb],${cr3-Prefixed-32} */
34128   {
34129     M32C_INSN_LDC32_SRC_CR3_DST32_24_16_SB_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-16-SB-relative-Prefixed-SI", "ldc", 40,
34130     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34131   },
34132 /* ldc ${Dsp-24-s8}[fb],${cr3-Prefixed-32} */
34133   {
34134     M32C_INSN_LDC32_SRC_CR3_DST32_24_8_FB_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-8-FB-relative-Prefixed-SI", "ldc", 32,
34135     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34136   },
34137 /* ldc ${Dsp-24-s16}[fb],${cr3-Prefixed-32} */
34138   {
34139     M32C_INSN_LDC32_SRC_CR3_DST32_24_16_FB_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-16-FB-relative-Prefixed-SI", "ldc", 40,
34140     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34141   },
34142 /* ldc ${Dsp-24-u16},${cr3-Prefixed-32} */
34143   {
34144     M32C_INSN_LDC32_SRC_CR3_DST32_24_16_ABSOLUTE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-16-absolute-Prefixed-SI", "ldc", 40,
34145     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34146   },
34147 /* ldc ${Dsp-24-u24},${cr3-Prefixed-32} */
34148   {
34149     M32C_INSN_LDC32_SRC_CR3_DST32_24_24_ABSOLUTE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-24-absolute-Prefixed-SI", "ldc", 48,
34150     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34151   },
34152 /* ldc $Dst32RnUnprefixedSI,${cr2-32} */
34153   {
34154     M32C_INSN_LDC32_SRC_CR2_DST32_RN_DIRECT_UNPREFIXED_SI, "ldc32.src-cr2-dst32-Rn-direct-Unprefixed-SI", "ldc", 16,
34155     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34156   },
34157 /* ldc $Dst32AnUnprefixedSI,${cr2-32} */
34158   {
34159     M32C_INSN_LDC32_SRC_CR2_DST32_AN_DIRECT_UNPREFIXED_SI, "ldc32.src-cr2-dst32-An-direct-Unprefixed-SI", "ldc", 16,
34160     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34161   },
34162 /* ldc [$Dst32AnUnprefixed],${cr2-32} */
34163   {
34164     M32C_INSN_LDC32_SRC_CR2_DST32_AN_INDIRECT_UNPREFIXED_SI, "ldc32.src-cr2-dst32-An-indirect-Unprefixed-SI", "ldc", 16,
34165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34166   },
34167 /* ldc ${Dsp-16-u8}[$Dst32AnUnprefixed],${cr2-32} */
34168   {
34169     M32C_INSN_LDC32_SRC_CR2_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-8-An-relative-Unprefixed-SI", "ldc", 24,
34170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34171   },
34172 /* ldc ${Dsp-16-u16}[$Dst32AnUnprefixed],${cr2-32} */
34173   {
34174     M32C_INSN_LDC32_SRC_CR2_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-16-An-relative-Unprefixed-SI", "ldc", 32,
34175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34176   },
34177 /* ldc ${Dsp-16-u24}[$Dst32AnUnprefixed],${cr2-32} */
34178   {
34179     M32C_INSN_LDC32_SRC_CR2_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-24-An-relative-Unprefixed-SI", "ldc", 40,
34180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34181   },
34182 /* ldc ${Dsp-16-u8}[sb],${cr2-32} */
34183   {
34184     M32C_INSN_LDC32_SRC_CR2_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-8-SB-relative-Unprefixed-SI", "ldc", 24,
34185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34186   },
34187 /* ldc ${Dsp-16-u16}[sb],${cr2-32} */
34188   {
34189     M32C_INSN_LDC32_SRC_CR2_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-16-SB-relative-Unprefixed-SI", "ldc", 32,
34190     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34191   },
34192 /* ldc ${Dsp-16-s8}[fb],${cr2-32} */
34193   {
34194     M32C_INSN_LDC32_SRC_CR2_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-8-FB-relative-Unprefixed-SI", "ldc", 24,
34195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34196   },
34197 /* ldc ${Dsp-16-s16}[fb],${cr2-32} */
34198   {
34199     M32C_INSN_LDC32_SRC_CR2_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-16-FB-relative-Unprefixed-SI", "ldc", 32,
34200     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34201   },
34202 /* ldc ${Dsp-16-u16},${cr2-32} */
34203   {
34204     M32C_INSN_LDC32_SRC_CR2_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-16-absolute-Unprefixed-SI", "ldc", 32,
34205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34206   },
34207 /* ldc ${Dsp-16-u24},${cr2-32} */
34208   {
34209     M32C_INSN_LDC32_SRC_CR2_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-24-absolute-Unprefixed-SI", "ldc", 40,
34210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34211   },
34212 /* ldc $Dst32RnPrefixedHI,${cr1-Prefixed-32} */
34213   {
34214     M32C_INSN_LDC32_SRC_CR1_DST32_RN_DIRECT_PREFIXED_HI, "ldc32.src-cr1-dst32-Rn-direct-Prefixed-HI", "ldc", 24,
34215     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34216   },
34217 /* ldc $Dst32AnPrefixedHI,${cr1-Prefixed-32} */
34218   {
34219     M32C_INSN_LDC32_SRC_CR1_DST32_AN_DIRECT_PREFIXED_HI, "ldc32.src-cr1-dst32-An-direct-Prefixed-HI", "ldc", 24,
34220     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34221   },
34222 /* ldc [$Dst32AnPrefixed],${cr1-Prefixed-32} */
34223   {
34224     M32C_INSN_LDC32_SRC_CR1_DST32_AN_INDIRECT_PREFIXED_HI, "ldc32.src-cr1-dst32-An-indirect-Prefixed-HI", "ldc", 24,
34225     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34226   },
34227 /* ldc ${Dsp-24-u8}[$Dst32AnPrefixed],${cr1-Prefixed-32} */
34228   {
34229     M32C_INSN_LDC32_SRC_CR1_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-8-An-relative-Prefixed-HI", "ldc", 32,
34230     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34231   },
34232 /* ldc ${Dsp-24-u16}[$Dst32AnPrefixed],${cr1-Prefixed-32} */
34233   {
34234     M32C_INSN_LDC32_SRC_CR1_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-16-An-relative-Prefixed-HI", "ldc", 40,
34235     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34236   },
34237 /* ldc ${Dsp-24-u24}[$Dst32AnPrefixed],${cr1-Prefixed-32} */
34238   {
34239     M32C_INSN_LDC32_SRC_CR1_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-24-An-relative-Prefixed-HI", "ldc", 48,
34240     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34241   },
34242 /* ldc ${Dsp-24-u8}[sb],${cr1-Prefixed-32} */
34243   {
34244     M32C_INSN_LDC32_SRC_CR1_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-8-SB-relative-Prefixed-HI", "ldc", 32,
34245     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34246   },
34247 /* ldc ${Dsp-24-u16}[sb],${cr1-Prefixed-32} */
34248   {
34249     M32C_INSN_LDC32_SRC_CR1_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-16-SB-relative-Prefixed-HI", "ldc", 40,
34250     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34251   },
34252 /* ldc ${Dsp-24-s8}[fb],${cr1-Prefixed-32} */
34253   {
34254     M32C_INSN_LDC32_SRC_CR1_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-8-FB-relative-Prefixed-HI", "ldc", 32,
34255     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34256   },
34257 /* ldc ${Dsp-24-s16}[fb],${cr1-Prefixed-32} */
34258   {
34259     M32C_INSN_LDC32_SRC_CR1_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-16-FB-relative-Prefixed-HI", "ldc", 40,
34260     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34261   },
34262 /* ldc ${Dsp-24-u16},${cr1-Prefixed-32} */
34263   {
34264     M32C_INSN_LDC32_SRC_CR1_DST32_24_16_ABSOLUTE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-16-absolute-Prefixed-HI", "ldc", 40,
34265     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34266   },
34267 /* ldc ${Dsp-24-u24},${cr1-Prefixed-32} */
34268   {
34269     M32C_INSN_LDC32_SRC_CR1_DST32_24_24_ABSOLUTE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-24-absolute-Prefixed-HI", "ldc", 48,
34270     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34271   },
34272 /* ldc $Dst16RnHI,${cr16} */
34273   {
34274     M32C_INSN_LDC16_DST_DST16_RN_DIRECT_HI, "ldc16.dst-dst16-Rn-direct-HI", "ldc", 16,
34275     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34276   },
34277 /* ldc $Dst16AnHI,${cr16} */
34278   {
34279     M32C_INSN_LDC16_DST_DST16_AN_DIRECT_HI, "ldc16.dst-dst16-An-direct-HI", "ldc", 16,
34280     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34281   },
34282 /* ldc [$Dst16An],${cr16} */
34283   {
34284     M32C_INSN_LDC16_DST_DST16_AN_INDIRECT_HI, "ldc16.dst-dst16-An-indirect-HI", "ldc", 16,
34285     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34286   },
34287 /* ldc ${Dsp-16-u8}[$Dst16An],${cr16} */
34288   {
34289     M32C_INSN_LDC16_DST_DST16_16_8_AN_RELATIVE_HI, "ldc16.dst-dst16-16-8-An-relative-HI", "ldc", 24,
34290     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34291   },
34292 /* ldc ${Dsp-16-u16}[$Dst16An],${cr16} */
34293   {
34294     M32C_INSN_LDC16_DST_DST16_16_16_AN_RELATIVE_HI, "ldc16.dst-dst16-16-16-An-relative-HI", "ldc", 32,
34295     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34296   },
34297 /* ldc ${Dsp-16-u8}[sb],${cr16} */
34298   {
34299     M32C_INSN_LDC16_DST_DST16_16_8_SB_RELATIVE_HI, "ldc16.dst-dst16-16-8-SB-relative-HI", "ldc", 24,
34300     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34301   },
34302 /* ldc ${Dsp-16-u16}[sb],${cr16} */
34303   {
34304     M32C_INSN_LDC16_DST_DST16_16_16_SB_RELATIVE_HI, "ldc16.dst-dst16-16-16-SB-relative-HI", "ldc", 32,
34305     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34306   },
34307 /* ldc ${Dsp-16-s8}[fb],${cr16} */
34308   {
34309     M32C_INSN_LDC16_DST_DST16_16_8_FB_RELATIVE_HI, "ldc16.dst-dst16-16-8-FB-relative-HI", "ldc", 24,
34310     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34311   },
34312 /* ldc ${Dsp-16-u16},${cr16} */
34313   {
34314     M32C_INSN_LDC16_DST_DST16_16_16_ABSOLUTE_HI, "ldc16.dst-dst16-16-16-absolute-HI", "ldc", 32,
34315     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
34316   },
34317 /* jsri.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34318   {
34319     M32C_INSN_JSRI32_A_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "jsri32.a-dst32-16-24-An-relative-Unprefixed-SI", "jsri.w", 40,
34320     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34321   },
34322 /* jsri.w ${Dsp-16-u24} */
34323   {
34324     M32C_INSN_JSRI32_A_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "jsri32.a-dst32-16-24-absolute-Unprefixed-SI", "jsri.w", 40,
34325     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34326   },
34327 /* jsri.a ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34328   {
34329     M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-16-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "jsri.a", 32,
34330     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34331   },
34332 /* jsri.a ${Dsp-16-u16}[sb] */
34333   {
34334     M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-16-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "jsri.a", 32,
34335     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34336   },
34337 /* jsri.a ${Dsp-16-s16}[fb] */
34338   {
34339     M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-16-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "jsri.a", 32,
34340     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34341   },
34342 /* jsri.a ${Dsp-16-u16} */
34343   {
34344     M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "jsri32a-dst32-16-16-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "jsri.a", 32,
34345     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34346   },
34347 /* jsri.a ${Dsp-16-u16}[$Dst16An] */
34348   {
34349     M32C_INSN_JSRI16A_DST16_16_16_SI_DST16_16_16_AN_RELATIVE_SI, "jsri16a-dst16-16-16-SI-dst16-16-16-An-relative-SI", "jsri.a", 32,
34350     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34351   },
34352 /* jsri.a ${Dsp-16-u16}[sb] */
34353   {
34354     M32C_INSN_JSRI16A_DST16_16_16_SI_DST16_16_16_SB_RELATIVE_SI, "jsri16a-dst16-16-16-SI-dst16-16-16-SB-relative-SI", "jsri.a", 32,
34355     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34356   },
34357 /* jsri.a ${Dsp-16-u16} */
34358   {
34359     M32C_INSN_JSRI16A_DST16_16_16_SI_DST16_16_16_ABSOLUTE_SI, "jsri16a-dst16-16-16-SI-dst16-16-16-absolute-SI", "jsri.a", 32,
34360     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34361   },
34362 /* jsri.a ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34363   {
34364     M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-8-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "jsri.a", 24,
34365     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34366   },
34367 /* jsri.a ${Dsp-16-u8}[sb] */
34368   {
34369     M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-8-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "jsri.a", 24,
34370     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34371   },
34372 /* jsri.a ${Dsp-16-s8}[fb] */
34373   {
34374     M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-8-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "jsri.a", 24,
34375     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34376   },
34377 /* jsri.a ${Dsp-16-u8}[$Dst16An] */
34378   {
34379     M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_AN_RELATIVE_SI, "jsri16a-dst16-16-8-SI-dst16-16-8-An-relative-SI", "jsri.a", 24,
34380     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34381   },
34382 /* jsri.a ${Dsp-16-u8}[sb] */
34383   {
34384     M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_SB_RELATIVE_SI, "jsri16a-dst16-16-8-SI-dst16-16-8-SB-relative-SI", "jsri.a", 24,
34385     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34386   },
34387 /* jsri.a ${Dsp-16-s8}[fb] */
34388   {
34389     M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_FB_RELATIVE_SI, "jsri16a-dst16-16-8-SI-dst16-16-8-FB-relative-SI", "jsri.a", 24,
34390     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34391   },
34392 /* jsri.a $Dst32RnUnprefixedSI */
34393   {
34394     M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "jsri32a-dst32-basic-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "jsri.a", 16,
34395     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34396   },
34397 /* jsri.a $Dst32AnUnprefixedSI */
34398   {
34399     M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "jsri32a-dst32-basic-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "jsri.a", 16,
34400     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34401   },
34402 /* jsri.a [$Dst32AnUnprefixed] */
34403   {
34404     M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "jsri32a-dst32-basic-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "jsri.a", 16,
34405     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34406   },
34407 /* jsri.a $Dst16RnSI */
34408   {
34409     M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_RN_DIRECT_SI, "jsri16a-dst16-basic-SI-dst16-Rn-direct-SI", "jsri.a", 16,
34410     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34411   },
34412 /* jsri.a $Dst16AnSI */
34413   {
34414     M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_AN_DIRECT_SI, "jsri16a-dst16-basic-SI-dst16-An-direct-SI", "jsri.a", 16,
34415     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34416   },
34417 /* jsri.a [$Dst16An] */
34418   {
34419     M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_AN_INDIRECT_SI, "jsri16a-dst16-basic-SI-dst16-An-indirect-SI", "jsri.a", 16,
34420     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34421   },
34422 /* jsri.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34423   {
34424     M32C_INSN_JSRI32_W_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "jsri32.w-dst32-16-24-An-relative-Unprefixed-HI", "jsri.w", 40,
34425     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34426   },
34427 /* jsri.w ${Dsp-16-u24} */
34428   {
34429     M32C_INSN_JSRI32_W_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "jsri32.w-dst32-16-24-absolute-Unprefixed-HI", "jsri.w", 40,
34430     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34431   },
34432 /* jsri.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34433   {
34434     M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-16-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "jsri.w", 32,
34435     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34436   },
34437 /* jsri.w ${Dsp-16-u16}[sb] */
34438   {
34439     M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-16-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "jsri.w", 32,
34440     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34441   },
34442 /* jsri.w ${Dsp-16-s16}[fb] */
34443   {
34444     M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-16-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "jsri.w", 32,
34445     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34446   },
34447 /* jsri.w ${Dsp-16-u16} */
34448   {
34449     M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "jsri32w-dst32-16-16-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "jsri.w", 32,
34450     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34451   },
34452 /* jsri.w ${Dsp-16-u16}[$Dst16An] */
34453   {
34454     M32C_INSN_JSRI16W_DST16_16_16_HI_DST16_16_16_AN_RELATIVE_HI, "jsri16w-dst16-16-16-HI-dst16-16-16-An-relative-HI", "jsri.w", 32,
34455     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34456   },
34457 /* jsri.w ${Dsp-16-u16}[sb] */
34458   {
34459     M32C_INSN_JSRI16W_DST16_16_16_HI_DST16_16_16_SB_RELATIVE_HI, "jsri16w-dst16-16-16-HI-dst16-16-16-SB-relative-HI", "jsri.w", 32,
34460     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34461   },
34462 /* jsri.w ${Dsp-16-u16} */
34463   {
34464     M32C_INSN_JSRI16W_DST16_16_16_HI_DST16_16_16_ABSOLUTE_HI, "jsri16w-dst16-16-16-HI-dst16-16-16-absolute-HI", "jsri.w", 32,
34465     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34466   },
34467 /* jsri.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34468   {
34469     M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-8-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "jsri.w", 24,
34470     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34471   },
34472 /* jsri.w ${Dsp-16-u8}[sb] */
34473   {
34474     M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-8-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "jsri.w", 24,
34475     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34476   },
34477 /* jsri.w ${Dsp-16-s8}[fb] */
34478   {
34479     M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-8-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "jsri.w", 24,
34480     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34481   },
34482 /* jsri.w ${Dsp-16-u8}[$Dst16An] */
34483   {
34484     M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_AN_RELATIVE_HI, "jsri16w-dst16-16-8-HI-dst16-16-8-An-relative-HI", "jsri.w", 24,
34485     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34486   },
34487 /* jsri.w ${Dsp-16-u8}[sb] */
34488   {
34489     M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_SB_RELATIVE_HI, "jsri16w-dst16-16-8-HI-dst16-16-8-SB-relative-HI", "jsri.w", 24,
34490     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34491   },
34492 /* jsri.w ${Dsp-16-s8}[fb] */
34493   {
34494     M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_FB_RELATIVE_HI, "jsri16w-dst16-16-8-HI-dst16-16-8-FB-relative-HI", "jsri.w", 24,
34495     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34496   },
34497 /* jsri.w $Dst32RnUnprefixedHI */
34498   {
34499     M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "jsri32w-dst32-basic-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "jsri.w", 16,
34500     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34501   },
34502 /* jsri.w $Dst32AnUnprefixedHI */
34503   {
34504     M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "jsri32w-dst32-basic-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "jsri.w", 16,
34505     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34506   },
34507 /* jsri.w [$Dst32AnUnprefixed] */
34508   {
34509     M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "jsri32w-dst32-basic-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "jsri.w", 16,
34510     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34511   },
34512 /* jsri.w $Dst16RnHI */
34513   {
34514     M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_RN_DIRECT_HI, "jsri16w-dst16-basic-HI-dst16-Rn-direct-HI", "jsri.w", 16,
34515     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34516   },
34517 /* jsri.w $Dst16AnHI */
34518   {
34519     M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_AN_DIRECT_HI, "jsri16w-dst16-basic-HI-dst16-An-direct-HI", "jsri.w", 16,
34520     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34521   },
34522 /* jsri.w [$Dst16An] */
34523   {
34524     M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_AN_INDIRECT_HI, "jsri16w-dst16-basic-HI-dst16-An-indirect-HI", "jsri.w", 16,
34525     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34526   },
34527 /* jmpi.a $Dst32RnUnprefixedSI */
34528   {
34529     M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "jmpi.a", 16,
34530     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34531   },
34532 /* jmpi.a $Dst32AnUnprefixedSI */
34533   {
34534     M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-An-direct-Unprefixed-SI", "jmpi.a", 16,
34535     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34536   },
34537 /* jmpi.a [$Dst32AnUnprefixed] */
34538   {
34539     M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-An-indirect-Unprefixed-SI", "jmpi.a", 16,
34540     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34541   },
34542 /* jmpi.a ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34543   {
34544     M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "jmpi.a", 24,
34545     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34546   },
34547 /* jmpi.a ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34548   {
34549     M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "jmpi.a", 32,
34550     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34551   },
34552 /* jmpi.a ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34553   {
34554     M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "jmpi.a", 40,
34555     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34556   },
34557 /* jmpi.a ${Dsp-16-u8}[sb] */
34558   {
34559     M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "jmpi.a", 24,
34560     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34561   },
34562 /* jmpi.a ${Dsp-16-u16}[sb] */
34563   {
34564     M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "jmpi.a", 32,
34565     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34566   },
34567 /* jmpi.a ${Dsp-16-s8}[fb] */
34568   {
34569     M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "jmpi.a", 24,
34570     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34571   },
34572 /* jmpi.a ${Dsp-16-s16}[fb] */
34573   {
34574     M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "jmpi.a", 32,
34575     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34576   },
34577 /* jmpi.a ${Dsp-16-u16} */
34578   {
34579     M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "jmpi.a", 32,
34580     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34581   },
34582 /* jmpi.a ${Dsp-16-u24} */
34583   {
34584     M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "jmpi.a", 40,
34585     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34586   },
34587 /* jmpi.a $Dst16RnSI */
34588   {
34589     M32C_INSN_JMPI16_A_16_DST16_RN_DIRECT_SI, "jmpi16.a-16-dst16-Rn-direct-SI", "jmpi.a", 16,
34590     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34591   },
34592 /* jmpi.a $Dst16AnSI */
34593   {
34594     M32C_INSN_JMPI16_A_16_DST16_AN_DIRECT_SI, "jmpi16.a-16-dst16-An-direct-SI", "jmpi.a", 16,
34595     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34596   },
34597 /* jmpi.a [$Dst16An] */
34598   {
34599     M32C_INSN_JMPI16_A_16_DST16_AN_INDIRECT_SI, "jmpi16.a-16-dst16-An-indirect-SI", "jmpi.a", 16,
34600     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34601   },
34602 /* jmpi.a ${Dsp-16-u8}[$Dst16An] */
34603   {
34604     M32C_INSN_JMPI16_A_16_DST16_16_8_AN_RELATIVE_SI, "jmpi16.a-16-dst16-16-8-An-relative-SI", "jmpi.a", 24,
34605     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34606   },
34607 /* jmpi.a ${Dsp-16-u16}[$Dst16An] */
34608   {
34609     M32C_INSN_JMPI16_A_16_DST16_16_16_AN_RELATIVE_SI, "jmpi16.a-16-dst16-16-16-An-relative-SI", "jmpi.a", 32,
34610     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34611   },
34612 /* jmpi.a ${Dsp-16-u8}[sb] */
34613   {
34614     M32C_INSN_JMPI16_A_16_DST16_16_8_SB_RELATIVE_SI, "jmpi16.a-16-dst16-16-8-SB-relative-SI", "jmpi.a", 24,
34615     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34616   },
34617 /* jmpi.a ${Dsp-16-u16}[sb] */
34618   {
34619     M32C_INSN_JMPI16_A_16_DST16_16_16_SB_RELATIVE_SI, "jmpi16.a-16-dst16-16-16-SB-relative-SI", "jmpi.a", 32,
34620     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34621   },
34622 /* jmpi.a ${Dsp-16-s8}[fb] */
34623   {
34624     M32C_INSN_JMPI16_A_16_DST16_16_8_FB_RELATIVE_SI, "jmpi16.a-16-dst16-16-8-FB-relative-SI", "jmpi.a", 24,
34625     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34626   },
34627 /* jmpi.a ${Dsp-16-u16} */
34628   {
34629     M32C_INSN_JMPI16_A_16_DST16_16_16_ABSOLUTE_SI, "jmpi16.a-16-dst16-16-16-absolute-SI", "jmpi.a", 32,
34630     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34631   },
34632 /* jmpi.w $Dst32RnUnprefixedHI */
34633   {
34634     M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "jmpi.w", 16,
34635     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34636   },
34637 /* jmpi.w $Dst32AnUnprefixedHI */
34638   {
34639     M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "jmpi.w", 16,
34640     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34641   },
34642 /* jmpi.w [$Dst32AnUnprefixed] */
34643   {
34644     M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "jmpi.w", 16,
34645     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34646   },
34647 /* jmpi.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34648   {
34649     M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "jmpi.w", 24,
34650     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34651   },
34652 /* jmpi.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34653   {
34654     M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "jmpi.w", 32,
34655     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34656   },
34657 /* jmpi.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34658   {
34659     M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "jmpi.w", 40,
34660     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34661   },
34662 /* jmpi.w ${Dsp-16-u8}[sb] */
34663   {
34664     M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "jmpi.w", 24,
34665     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34666   },
34667 /* jmpi.w ${Dsp-16-u16}[sb] */
34668   {
34669     M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "jmpi.w", 32,
34670     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34671   },
34672 /* jmpi.w ${Dsp-16-s8}[fb] */
34673   {
34674     M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "jmpi.w", 24,
34675     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34676   },
34677 /* jmpi.w ${Dsp-16-s16}[fb] */
34678   {
34679     M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "jmpi.w", 32,
34680     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34681   },
34682 /* jmpi.w ${Dsp-16-u16} */
34683   {
34684     M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "jmpi.w", 32,
34685     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34686   },
34687 /* jmpi.w ${Dsp-16-u24} */
34688   {
34689     M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "jmpi.w", 40,
34690     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34691   },
34692 /* jmpi.w $Dst16RnHI */
34693   {
34694     M32C_INSN_JMPI16_W_16_DST16_RN_DIRECT_HI, "jmpi16.w-16-dst16-Rn-direct-HI", "jmpi.w", 16,
34695     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34696   },
34697 /* jmpi.w $Dst16AnHI */
34698   {
34699     M32C_INSN_JMPI16_W_16_DST16_AN_DIRECT_HI, "jmpi16.w-16-dst16-An-direct-HI", "jmpi.w", 16,
34700     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34701   },
34702 /* jmpi.w [$Dst16An] */
34703   {
34704     M32C_INSN_JMPI16_W_16_DST16_AN_INDIRECT_HI, "jmpi16.w-16-dst16-An-indirect-HI", "jmpi.w", 16,
34705     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34706   },
34707 /* jmpi.w ${Dsp-16-u8}[$Dst16An] */
34708   {
34709     M32C_INSN_JMPI16_W_16_DST16_16_8_AN_RELATIVE_HI, "jmpi16.w-16-dst16-16-8-An-relative-HI", "jmpi.w", 24,
34710     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34711   },
34712 /* jmpi.w ${Dsp-16-u16}[$Dst16An] */
34713   {
34714     M32C_INSN_JMPI16_W_16_DST16_16_16_AN_RELATIVE_HI, "jmpi16.w-16-dst16-16-16-An-relative-HI", "jmpi.w", 32,
34715     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34716   },
34717 /* jmpi.w ${Dsp-16-u8}[sb] */
34718   {
34719     M32C_INSN_JMPI16_W_16_DST16_16_8_SB_RELATIVE_HI, "jmpi16.w-16-dst16-16-8-SB-relative-HI", "jmpi.w", 24,
34720     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34721   },
34722 /* jmpi.w ${Dsp-16-u16}[sb] */
34723   {
34724     M32C_INSN_JMPI16_W_16_DST16_16_16_SB_RELATIVE_HI, "jmpi16.w-16-dst16-16-16-SB-relative-HI", "jmpi.w", 32,
34725     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34726   },
34727 /* jmpi.w ${Dsp-16-s8}[fb] */
34728   {
34729     M32C_INSN_JMPI16_W_16_DST16_16_8_FB_RELATIVE_HI, "jmpi16.w-16-dst16-16-8-FB-relative-HI", "jmpi.w", 24,
34730     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34731   },
34732 /* jmpi.w ${Dsp-16-u16} */
34733   {
34734     M32C_INSN_JMPI16_W_16_DST16_16_16_ABSOLUTE_HI, "jmpi16.w-16-dst16-16-16-absolute-HI", "jmpi.w", 32,
34735     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34736   },
34737 /* indexws.w $Dst32RnUnprefixedHI */
34738   {
34739     M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexws.w", 16,
34740     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34741   },
34742 /* indexws.w $Dst32AnUnprefixedHI */
34743   {
34744     M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexws.w", 16,
34745     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34746   },
34747 /* indexws.w [$Dst32AnUnprefixed] */
34748   {
34749     M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexws.w", 16,
34750     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34751   },
34752 /* indexws.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34753   {
34754     M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexws.w", 24,
34755     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34756   },
34757 /* indexws.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34758   {
34759     M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexws.w", 32,
34760     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34761   },
34762 /* indexws.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34763   {
34764     M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexws.w", 40,
34765     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34766   },
34767 /* indexws.w ${Dsp-16-u8}[sb] */
34768   {
34769     M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexws.w", 24,
34770     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34771   },
34772 /* indexws.w ${Dsp-16-u16}[sb] */
34773   {
34774     M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexws.w", 32,
34775     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34776   },
34777 /* indexws.w ${Dsp-16-s8}[fb] */
34778   {
34779     M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexws.w", 24,
34780     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34781   },
34782 /* indexws.w ${Dsp-16-s16}[fb] */
34783   {
34784     M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexws.w", 32,
34785     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34786   },
34787 /* indexws.w ${Dsp-16-u16} */
34788   {
34789     M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexws.w", 32,
34790     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34791   },
34792 /* indexws.w ${Dsp-16-u24} */
34793   {
34794     M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexws.w", 40,
34795     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34796   },
34797 /* indexws.b $Dst32RnUnprefixedQI */
34798   {
34799     M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexws.b", 16,
34800     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34801   },
34802 /* indexws.b $Dst32AnUnprefixedQI */
34803   {
34804     M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexws.b", 16,
34805     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34806   },
34807 /* indexws.b [$Dst32AnUnprefixed] */
34808   {
34809     M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexws.b", 16,
34810     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34811   },
34812 /* indexws.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34813   {
34814     M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexws.b", 24,
34815     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34816   },
34817 /* indexws.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34818   {
34819     M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexws.b", 32,
34820     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34821   },
34822 /* indexws.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34823   {
34824     M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexws.b", 40,
34825     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34826   },
34827 /* indexws.b ${Dsp-16-u8}[sb] */
34828   {
34829     M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexws.b", 24,
34830     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34831   },
34832 /* indexws.b ${Dsp-16-u16}[sb] */
34833   {
34834     M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexws.b", 32,
34835     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34836   },
34837 /* indexws.b ${Dsp-16-s8}[fb] */
34838   {
34839     M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexws.b", 24,
34840     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34841   },
34842 /* indexws.b ${Dsp-16-s16}[fb] */
34843   {
34844     M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexws.b", 32,
34845     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34846   },
34847 /* indexws.b ${Dsp-16-u16} */
34848   {
34849     M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexws.b", 32,
34850     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34851   },
34852 /* indexws.b ${Dsp-16-u24} */
34853   {
34854     M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexws.b", 40,
34855     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34856   },
34857 /* indexwd.w $Dst32RnUnprefixedHI */
34858   {
34859     M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexwd.w", 16,
34860     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34861   },
34862 /* indexwd.w $Dst32AnUnprefixedHI */
34863   {
34864     M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexwd.w", 16,
34865     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34866   },
34867 /* indexwd.w [$Dst32AnUnprefixed] */
34868   {
34869     M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexwd.w", 16,
34870     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34871   },
34872 /* indexwd.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34873   {
34874     M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexwd.w", 24,
34875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34876   },
34877 /* indexwd.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34878   {
34879     M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexwd.w", 32,
34880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34881   },
34882 /* indexwd.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34883   {
34884     M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexwd.w", 40,
34885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34886   },
34887 /* indexwd.w ${Dsp-16-u8}[sb] */
34888   {
34889     M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexwd.w", 24,
34890     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34891   },
34892 /* indexwd.w ${Dsp-16-u16}[sb] */
34893   {
34894     M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexwd.w", 32,
34895     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34896   },
34897 /* indexwd.w ${Dsp-16-s8}[fb] */
34898   {
34899     M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexwd.w", 24,
34900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34901   },
34902 /* indexwd.w ${Dsp-16-s16}[fb] */
34903   {
34904     M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexwd.w", 32,
34905     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34906   },
34907 /* indexwd.w ${Dsp-16-u16} */
34908   {
34909     M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexwd.w", 32,
34910     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34911   },
34912 /* indexwd.w ${Dsp-16-u24} */
34913   {
34914     M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexwd.w", 40,
34915     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34916   },
34917 /* indexwd.b $Dst32RnUnprefixedQI */
34918   {
34919     M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexwd.b", 16,
34920     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34921   },
34922 /* indexwd.b $Dst32AnUnprefixedQI */
34923   {
34924     M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexwd.b", 16,
34925     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34926   },
34927 /* indexwd.b [$Dst32AnUnprefixed] */
34928   {
34929     M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexwd.b", 16,
34930     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34931   },
34932 /* indexwd.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34933   {
34934     M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexwd.b", 24,
34935     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34936   },
34937 /* indexwd.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34938   {
34939     M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexwd.b", 32,
34940     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34941   },
34942 /* indexwd.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34943   {
34944     M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexwd.b", 40,
34945     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34946   },
34947 /* indexwd.b ${Dsp-16-u8}[sb] */
34948   {
34949     M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexwd.b", 24,
34950     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34951   },
34952 /* indexwd.b ${Dsp-16-u16}[sb] */
34953   {
34954     M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexwd.b", 32,
34955     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34956   },
34957 /* indexwd.b ${Dsp-16-s8}[fb] */
34958   {
34959     M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexwd.b", 24,
34960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34961   },
34962 /* indexwd.b ${Dsp-16-s16}[fb] */
34963   {
34964     M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexwd.b", 32,
34965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34966   },
34967 /* indexwd.b ${Dsp-16-u16} */
34968   {
34969     M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexwd.b", 32,
34970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34971   },
34972 /* indexwd.b ${Dsp-16-u24} */
34973   {
34974     M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexwd.b", 40,
34975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34976   },
34977 /* indexw.w $Dst32RnUnprefixedHI */
34978   {
34979     M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexw.w", 16,
34980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34981   },
34982 /* indexw.w $Dst32AnUnprefixedHI */
34983   {
34984     M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexw.w", 16,
34985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34986   },
34987 /* indexw.w [$Dst32AnUnprefixed] */
34988   {
34989     M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexw.w", 16,
34990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34991   },
34992 /* indexw.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34993   {
34994     M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexw.w", 24,
34995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34996   },
34997 /* indexw.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34998   {
34999     M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexw.w", 32,
35000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35001   },
35002 /* indexw.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35003   {
35004     M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexw.w", 40,
35005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35006   },
35007 /* indexw.w ${Dsp-16-u8}[sb] */
35008   {
35009     M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexw.w", 24,
35010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35011   },
35012 /* indexw.w ${Dsp-16-u16}[sb] */
35013   {
35014     M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexw.w", 32,
35015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35016   },
35017 /* indexw.w ${Dsp-16-s8}[fb] */
35018   {
35019     M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexw.w", 24,
35020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35021   },
35022 /* indexw.w ${Dsp-16-s16}[fb] */
35023   {
35024     M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexw.w", 32,
35025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35026   },
35027 /* indexw.w ${Dsp-16-u16} */
35028   {
35029     M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexw.w", 32,
35030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35031   },
35032 /* indexw.w ${Dsp-16-u24} */
35033   {
35034     M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexw.w", 40,
35035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35036   },
35037 /* indexw.b $Dst32RnUnprefixedQI */
35038   {
35039     M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexw.b", 16,
35040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35041   },
35042 /* indexw.b $Dst32AnUnprefixedQI */
35043   {
35044     M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexw.b", 16,
35045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35046   },
35047 /* indexw.b [$Dst32AnUnprefixed] */
35048   {
35049     M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexw.b", 16,
35050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35051   },
35052 /* indexw.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35053   {
35054     M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexw.b", 24,
35055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35056   },
35057 /* indexw.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35058   {
35059     M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexw.b", 32,
35060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35061   },
35062 /* indexw.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35063   {
35064     M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexw.b", 40,
35065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35066   },
35067 /* indexw.b ${Dsp-16-u8}[sb] */
35068   {
35069     M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexw.b", 24,
35070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35071   },
35072 /* indexw.b ${Dsp-16-u16}[sb] */
35073   {
35074     M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexw.b", 32,
35075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35076   },
35077 /* indexw.b ${Dsp-16-s8}[fb] */
35078   {
35079     M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexw.b", 24,
35080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35081   },
35082 /* indexw.b ${Dsp-16-s16}[fb] */
35083   {
35084     M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexw.b", 32,
35085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35086   },
35087 /* indexw.b ${Dsp-16-u16} */
35088   {
35089     M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexw.b", 32,
35090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35091   },
35092 /* indexw.b ${Dsp-16-u24} */
35093   {
35094     M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexw.b", 40,
35095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35096   },
35097 /* indexls.w $Dst32RnUnprefixedHI */
35098   {
35099     M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexls.w", 16,
35100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35101   },
35102 /* indexls.w $Dst32AnUnprefixedHI */
35103   {
35104     M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexls.w", 16,
35105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35106   },
35107 /* indexls.w [$Dst32AnUnprefixed] */
35108   {
35109     M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexls.w", 16,
35110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35111   },
35112 /* indexls.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35113   {
35114     M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexls.w", 24,
35115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35116   },
35117 /* indexls.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35118   {
35119     M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexls.w", 32,
35120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35121   },
35122 /* indexls.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35123   {
35124     M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexls.w", 40,
35125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35126   },
35127 /* indexls.w ${Dsp-16-u8}[sb] */
35128   {
35129     M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexls.w", 24,
35130     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35131   },
35132 /* indexls.w ${Dsp-16-u16}[sb] */
35133   {
35134     M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexls.w", 32,
35135     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35136   },
35137 /* indexls.w ${Dsp-16-s8}[fb] */
35138   {
35139     M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexls.w", 24,
35140     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35141   },
35142 /* indexls.w ${Dsp-16-s16}[fb] */
35143   {
35144     M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexls.w", 32,
35145     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35146   },
35147 /* indexls.w ${Dsp-16-u16} */
35148   {
35149     M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexls.w", 32,
35150     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35151   },
35152 /* indexls.w ${Dsp-16-u24} */
35153   {
35154     M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexls.w", 40,
35155     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35156   },
35157 /* indexls.b $Dst32RnUnprefixedQI */
35158   {
35159     M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexls.b", 16,
35160     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35161   },
35162 /* indexls.b $Dst32AnUnprefixedQI */
35163   {
35164     M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexls.b", 16,
35165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35166   },
35167 /* indexls.b [$Dst32AnUnprefixed] */
35168   {
35169     M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexls.b", 16,
35170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35171   },
35172 /* indexls.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35173   {
35174     M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexls.b", 24,
35175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35176   },
35177 /* indexls.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35178   {
35179     M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexls.b", 32,
35180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35181   },
35182 /* indexls.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35183   {
35184     M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexls.b", 40,
35185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35186   },
35187 /* indexls.b ${Dsp-16-u8}[sb] */
35188   {
35189     M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexls.b", 24,
35190     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35191   },
35192 /* indexls.b ${Dsp-16-u16}[sb] */
35193   {
35194     M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexls.b", 32,
35195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35196   },
35197 /* indexls.b ${Dsp-16-s8}[fb] */
35198   {
35199     M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexls.b", 24,
35200     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35201   },
35202 /* indexls.b ${Dsp-16-s16}[fb] */
35203   {
35204     M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexls.b", 32,
35205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35206   },
35207 /* indexls.b ${Dsp-16-u16} */
35208   {
35209     M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexls.b", 32,
35210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35211   },
35212 /* indexls.b ${Dsp-16-u24} */
35213   {
35214     M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexls.b", 40,
35215     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35216   },
35217 /* indexld.w $Dst32RnUnprefixedHI */
35218   {
35219     M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexld.w", 16,
35220     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35221   },
35222 /* indexld.w $Dst32AnUnprefixedHI */
35223   {
35224     M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexld.w", 16,
35225     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35226   },
35227 /* indexld.w [$Dst32AnUnprefixed] */
35228   {
35229     M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexld.w", 16,
35230     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35231   },
35232 /* indexld.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35233   {
35234     M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexld.w", 24,
35235     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35236   },
35237 /* indexld.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35238   {
35239     M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexld.w", 32,
35240     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35241   },
35242 /* indexld.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35243   {
35244     M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexld.w", 40,
35245     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35246   },
35247 /* indexld.w ${Dsp-16-u8}[sb] */
35248   {
35249     M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexld.w", 24,
35250     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35251   },
35252 /* indexld.w ${Dsp-16-u16}[sb] */
35253   {
35254     M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexld.w", 32,
35255     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35256   },
35257 /* indexld.w ${Dsp-16-s8}[fb] */
35258   {
35259     M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexld.w", 24,
35260     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35261   },
35262 /* indexld.w ${Dsp-16-s16}[fb] */
35263   {
35264     M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexld.w", 32,
35265     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35266   },
35267 /* indexld.w ${Dsp-16-u16} */
35268   {
35269     M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexld.w", 32,
35270     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35271   },
35272 /* indexld.w ${Dsp-16-u24} */
35273   {
35274     M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexld.w", 40,
35275     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35276   },
35277 /* indexld.b $Dst32RnUnprefixedQI */
35278   {
35279     M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexld.b", 16,
35280     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35281   },
35282 /* indexld.b $Dst32AnUnprefixedQI */
35283   {
35284     M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexld.b", 16,
35285     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35286   },
35287 /* indexld.b [$Dst32AnUnprefixed] */
35288   {
35289     M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexld.b", 16,
35290     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35291   },
35292 /* indexld.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35293   {
35294     M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexld.b", 24,
35295     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35296   },
35297 /* indexld.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35298   {
35299     M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexld.b", 32,
35300     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35301   },
35302 /* indexld.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35303   {
35304     M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexld.b", 40,
35305     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35306   },
35307 /* indexld.b ${Dsp-16-u8}[sb] */
35308   {
35309     M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexld.b", 24,
35310     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35311   },
35312 /* indexld.b ${Dsp-16-u16}[sb] */
35313   {
35314     M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexld.b", 32,
35315     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35316   },
35317 /* indexld.b ${Dsp-16-s8}[fb] */
35318   {
35319     M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexld.b", 24,
35320     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35321   },
35322 /* indexld.b ${Dsp-16-s16}[fb] */
35323   {
35324     M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexld.b", 32,
35325     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35326   },
35327 /* indexld.b ${Dsp-16-u16} */
35328   {
35329     M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexld.b", 32,
35330     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35331   },
35332 /* indexld.b ${Dsp-16-u24} */
35333   {
35334     M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexld.b", 40,
35335     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35336   },
35337 /* indexl.w $Dst32RnUnprefixedHI */
35338   {
35339     M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexl.w", 16,
35340     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35341   },
35342 /* indexl.w $Dst32AnUnprefixedHI */
35343   {
35344     M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexl.w", 16,
35345     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35346   },
35347 /* indexl.w [$Dst32AnUnprefixed] */
35348   {
35349     M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexl.w", 16,
35350     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35351   },
35352 /* indexl.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35353   {
35354     M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexl.w", 24,
35355     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35356   },
35357 /* indexl.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35358   {
35359     M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexl.w", 32,
35360     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35361   },
35362 /* indexl.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35363   {
35364     M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexl.w", 40,
35365     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35366   },
35367 /* indexl.w ${Dsp-16-u8}[sb] */
35368   {
35369     M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexl.w", 24,
35370     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35371   },
35372 /* indexl.w ${Dsp-16-u16}[sb] */
35373   {
35374     M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexl.w", 32,
35375     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35376   },
35377 /* indexl.w ${Dsp-16-s8}[fb] */
35378   {
35379     M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexl.w", 24,
35380     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35381   },
35382 /* indexl.w ${Dsp-16-s16}[fb] */
35383   {
35384     M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexl.w", 32,
35385     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35386   },
35387 /* indexl.w ${Dsp-16-u16} */
35388   {
35389     M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexl.w", 32,
35390     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35391   },
35392 /* indexl.w ${Dsp-16-u24} */
35393   {
35394     M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexl.w", 40,
35395     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35396   },
35397 /* indexl.b $Dst32RnUnprefixedQI */
35398   {
35399     M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexl.b", 16,
35400     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35401   },
35402 /* indexl.b $Dst32AnUnprefixedQI */
35403   {
35404     M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexl.b", 16,
35405     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35406   },
35407 /* indexl.b [$Dst32AnUnprefixed] */
35408   {
35409     M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexl.b", 16,
35410     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35411   },
35412 /* indexl.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35413   {
35414     M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexl.b", 24,
35415     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35416   },
35417 /* indexl.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35418   {
35419     M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexl.b", 32,
35420     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35421   },
35422 /* indexl.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35423   {
35424     M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexl.b", 40,
35425     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35426   },
35427 /* indexl.b ${Dsp-16-u8}[sb] */
35428   {
35429     M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexl.b", 24,
35430     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35431   },
35432 /* indexl.b ${Dsp-16-u16}[sb] */
35433   {
35434     M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexl.b", 32,
35435     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35436   },
35437 /* indexl.b ${Dsp-16-s8}[fb] */
35438   {
35439     M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexl.b", 24,
35440     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35441   },
35442 /* indexl.b ${Dsp-16-s16}[fb] */
35443   {
35444     M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexl.b", 32,
35445     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35446   },
35447 /* indexl.b ${Dsp-16-u16} */
35448   {
35449     M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexl.b", 32,
35450     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35451   },
35452 /* indexl.b ${Dsp-16-u24} */
35453   {
35454     M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexl.b", 40,
35455     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35456   },
35457 /* indexbs.w $Dst32RnUnprefixedHI */
35458   {
35459     M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexbs.w", 16,
35460     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35461   },
35462 /* indexbs.w $Dst32AnUnprefixedHI */
35463   {
35464     M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexbs.w", 16,
35465     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35466   },
35467 /* indexbs.w [$Dst32AnUnprefixed] */
35468   {
35469     M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexbs.w", 16,
35470     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35471   },
35472 /* indexbs.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35473   {
35474     M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexbs.w", 24,
35475     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35476   },
35477 /* indexbs.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35478   {
35479     M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexbs.w", 32,
35480     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35481   },
35482 /* indexbs.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35483   {
35484     M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexbs.w", 40,
35485     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35486   },
35487 /* indexbs.w ${Dsp-16-u8}[sb] */
35488   {
35489     M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexbs.w", 24,
35490     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35491   },
35492 /* indexbs.w ${Dsp-16-u16}[sb] */
35493   {
35494     M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexbs.w", 32,
35495     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35496   },
35497 /* indexbs.w ${Dsp-16-s8}[fb] */
35498   {
35499     M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexbs.w", 24,
35500     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35501   },
35502 /* indexbs.w ${Dsp-16-s16}[fb] */
35503   {
35504     M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexbs.w", 32,
35505     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35506   },
35507 /* indexbs.w ${Dsp-16-u16} */
35508   {
35509     M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexbs.w", 32,
35510     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35511   },
35512 /* indexbs.w ${Dsp-16-u24} */
35513   {
35514     M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexbs.w", 40,
35515     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35516   },
35517 /* indexbs.b $Dst32RnUnprefixedQI */
35518   {
35519     M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexbs.b", 16,
35520     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35521   },
35522 /* indexbs.b $Dst32AnUnprefixedQI */
35523   {
35524     M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexbs.b", 16,
35525     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35526   },
35527 /* indexbs.b [$Dst32AnUnprefixed] */
35528   {
35529     M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexbs.b", 16,
35530     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35531   },
35532 /* indexbs.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35533   {
35534     M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexbs.b", 24,
35535     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35536   },
35537 /* indexbs.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35538   {
35539     M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexbs.b", 32,
35540     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35541   },
35542 /* indexbs.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35543   {
35544     M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexbs.b", 40,
35545     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35546   },
35547 /* indexbs.b ${Dsp-16-u8}[sb] */
35548   {
35549     M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexbs.b", 24,
35550     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35551   },
35552 /* indexbs.b ${Dsp-16-u16}[sb] */
35553   {
35554     M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexbs.b", 32,
35555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35556   },
35557 /* indexbs.b ${Dsp-16-s8}[fb] */
35558   {
35559     M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexbs.b", 24,
35560     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35561   },
35562 /* indexbs.b ${Dsp-16-s16}[fb] */
35563   {
35564     M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexbs.b", 32,
35565     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35566   },
35567 /* indexbs.b ${Dsp-16-u16} */
35568   {
35569     M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexbs.b", 32,
35570     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35571   },
35572 /* indexbs.b ${Dsp-16-u24} */
35573   {
35574     M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexbs.b", 40,
35575     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35576   },
35577 /* indexbd.w $Dst32RnUnprefixedHI */
35578   {
35579     M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexbd.w", 16,
35580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35581   },
35582 /* indexbd.w $Dst32AnUnprefixedHI */
35583   {
35584     M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexbd.w", 16,
35585     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35586   },
35587 /* indexbd.w [$Dst32AnUnprefixed] */
35588   {
35589     M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexbd.w", 16,
35590     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35591   },
35592 /* indexbd.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35593   {
35594     M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexbd.w", 24,
35595     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35596   },
35597 /* indexbd.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35598   {
35599     M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexbd.w", 32,
35600     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35601   },
35602 /* indexbd.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35603   {
35604     M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexbd.w", 40,
35605     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35606   },
35607 /* indexbd.w ${Dsp-16-u8}[sb] */
35608   {
35609     M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexbd.w", 24,
35610     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35611   },
35612 /* indexbd.w ${Dsp-16-u16}[sb] */
35613   {
35614     M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexbd.w", 32,
35615     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35616   },
35617 /* indexbd.w ${Dsp-16-s8}[fb] */
35618   {
35619     M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexbd.w", 24,
35620     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35621   },
35622 /* indexbd.w ${Dsp-16-s16}[fb] */
35623   {
35624     M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexbd.w", 32,
35625     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35626   },
35627 /* indexbd.w ${Dsp-16-u16} */
35628   {
35629     M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexbd.w", 32,
35630     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35631   },
35632 /* indexbd.w ${Dsp-16-u24} */
35633   {
35634     M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexbd.w", 40,
35635     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35636   },
35637 /* indexbd.b $Dst32RnUnprefixedQI */
35638   {
35639     M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexbd.b", 16,
35640     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35641   },
35642 /* indexbd.b $Dst32AnUnprefixedQI */
35643   {
35644     M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexbd.b", 16,
35645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35646   },
35647 /* indexbd.b [$Dst32AnUnprefixed] */
35648   {
35649     M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexbd.b", 16,
35650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35651   },
35652 /* indexbd.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35653   {
35654     M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexbd.b", 24,
35655     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35656   },
35657 /* indexbd.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35658   {
35659     M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexbd.b", 32,
35660     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35661   },
35662 /* indexbd.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35663   {
35664     M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexbd.b", 40,
35665     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35666   },
35667 /* indexbd.b ${Dsp-16-u8}[sb] */
35668   {
35669     M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexbd.b", 24,
35670     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35671   },
35672 /* indexbd.b ${Dsp-16-u16}[sb] */
35673   {
35674     M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexbd.b", 32,
35675     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35676   },
35677 /* indexbd.b ${Dsp-16-s8}[fb] */
35678   {
35679     M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexbd.b", 24,
35680     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35681   },
35682 /* indexbd.b ${Dsp-16-s16}[fb] */
35683   {
35684     M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexbd.b", 32,
35685     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35686   },
35687 /* indexbd.b ${Dsp-16-u16} */
35688   {
35689     M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexbd.b", 32,
35690     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35691   },
35692 /* indexbd.b ${Dsp-16-u24} */
35693   {
35694     M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexbd.b", 40,
35695     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35696   },
35697 /* indexb.w $Dst32RnUnprefixedHI */
35698   {
35699     M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexb.w", 16,
35700     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35701   },
35702 /* indexb.w $Dst32AnUnprefixedHI */
35703   {
35704     M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexb.w", 16,
35705     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35706   },
35707 /* indexb.w [$Dst32AnUnprefixed] */
35708   {
35709     M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexb.w", 16,
35710     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35711   },
35712 /* indexb.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35713   {
35714     M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexb.w", 24,
35715     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35716   },
35717 /* indexb.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35718   {
35719     M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexb.w", 32,
35720     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35721   },
35722 /* indexb.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35723   {
35724     M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexb.w", 40,
35725     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35726   },
35727 /* indexb.w ${Dsp-16-u8}[sb] */
35728   {
35729     M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexb.w", 24,
35730     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35731   },
35732 /* indexb.w ${Dsp-16-u16}[sb] */
35733   {
35734     M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexb.w", 32,
35735     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35736   },
35737 /* indexb.w ${Dsp-16-s8}[fb] */
35738   {
35739     M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexb.w", 24,
35740     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35741   },
35742 /* indexb.w ${Dsp-16-s16}[fb] */
35743   {
35744     M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexb.w", 32,
35745     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35746   },
35747 /* indexb.w ${Dsp-16-u16} */
35748   {
35749     M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexb.w", 32,
35750     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35751   },
35752 /* indexb.w ${Dsp-16-u24} */
35753   {
35754     M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexb.w", 40,
35755     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35756   },
35757 /* indexb.b $Dst32RnUnprefixedQI */
35758   {
35759     M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexb.b", 16,
35760     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35761   },
35762 /* indexb.b $Dst32AnUnprefixedQI */
35763   {
35764     M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexb.b", 16,
35765     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35766   },
35767 /* indexb.b [$Dst32AnUnprefixed] */
35768   {
35769     M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexb.b", 16,
35770     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35771   },
35772 /* indexb.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35773   {
35774     M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexb.b", 24,
35775     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35776   },
35777 /* indexb.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35778   {
35779     M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexb.b", 32,
35780     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35781   },
35782 /* indexb.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35783   {
35784     M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexb.b", 40,
35785     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35786   },
35787 /* indexb.b ${Dsp-16-u8}[sb] */
35788   {
35789     M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexb.b", 24,
35790     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35791   },
35792 /* indexb.b ${Dsp-16-u16}[sb] */
35793   {
35794     M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexb.b", 32,
35795     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35796   },
35797 /* indexb.b ${Dsp-16-s8}[fb] */
35798   {
35799     M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexb.b", 24,
35800     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35801   },
35802 /* indexb.b ${Dsp-16-s16}[fb] */
35803   {
35804     M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexb.b", 32,
35805     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35806   },
35807 /* indexb.b ${Dsp-16-u16} */
35808   {
35809     M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexb.b", 32,
35810     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35811   },
35812 /* indexb.b ${Dsp-16-u24} */
35813   {
35814     M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexb.b", 40,
35815     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35816   },
35817 /* inc.w $Dst32RnUnprefixedHI */
35818   {
35819     M32C_INSN_INC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "inc.w", 16,
35820     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35821   },
35822 /* inc.w $Dst32AnUnprefixedHI */
35823   {
35824     M32C_INSN_INC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "inc.w", 16,
35825     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35826   },
35827 /* inc.w [$Dst32AnUnprefixed] */
35828   {
35829     M32C_INSN_INC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "inc.w", 16,
35830     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35831   },
35832 /* inc.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35833   {
35834     M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "inc.w", 24,
35835     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35836   },
35837 /* inc.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35838   {
35839     M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "inc.w", 32,
35840     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35841   },
35842 /* inc.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35843   {
35844     M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "inc.w", 40,
35845     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35846   },
35847 /* inc.w ${Dsp-16-u8}[sb] */
35848   {
35849     M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "inc.w", 24,
35850     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35851   },
35852 /* inc.w ${Dsp-16-u16}[sb] */
35853   {
35854     M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "inc.w", 32,
35855     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35856   },
35857 /* inc.w ${Dsp-16-s8}[fb] */
35858   {
35859     M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "inc.w", 24,
35860     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35861   },
35862 /* inc.w ${Dsp-16-s16}[fb] */
35863   {
35864     M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "inc.w", 32,
35865     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35866   },
35867 /* inc.w ${Dsp-16-u16} */
35868   {
35869     M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "inc.w", 32,
35870     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35871   },
35872 /* inc.w ${Dsp-16-u24} */
35873   {
35874     M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "inc.w", 40,
35875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35876   },
35877 /* inc.b $Dst32RnUnprefixedQI */
35878   {
35879     M32C_INSN_INC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "inc.b", 16,
35880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35881   },
35882 /* inc.b $Dst32AnUnprefixedQI */
35883   {
35884     M32C_INSN_INC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "inc.b", 16,
35885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35886   },
35887 /* inc.b [$Dst32AnUnprefixed] */
35888   {
35889     M32C_INSN_INC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "inc.b", 16,
35890     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35891   },
35892 /* inc.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35893   {
35894     M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "inc.b", 24,
35895     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35896   },
35897 /* inc.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35898   {
35899     M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "inc.b", 32,
35900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35901   },
35902 /* inc.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35903   {
35904     M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "inc.b", 40,
35905     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35906   },
35907 /* inc.b ${Dsp-16-u8}[sb] */
35908   {
35909     M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "inc.b", 24,
35910     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35911   },
35912 /* inc.b ${Dsp-16-u16}[sb] */
35913   {
35914     M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "inc.b", 32,
35915     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35916   },
35917 /* inc.b ${Dsp-16-s8}[fb] */
35918   {
35919     M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "inc.b", 24,
35920     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35921   },
35922 /* inc.b ${Dsp-16-s16}[fb] */
35923   {
35924     M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "inc.b", 32,
35925     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35926   },
35927 /* inc.b ${Dsp-16-u16} */
35928   {
35929     M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "inc.b", 32,
35930     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35931   },
35932 /* inc.b ${Dsp-16-u24} */
35933   {
35934     M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "inc.b", 40,
35935     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35936   },
35937 /* inc.b r0l */
35938   {
35939     M32C_INSN_INC16_B_DST16_3_S_R0L_DIRECT_QI, "inc16.b-dst16-3-S-R0l-direct-QI", "inc.b", 8,
35940     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
35941   },
35942 /* inc.b r0h */
35943   {
35944     M32C_INSN_INC16_B_DST16_3_S_R0H_DIRECT_QI, "inc16.b-dst16-3-S-R0h-direct-QI", "inc.b", 8,
35945     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
35946   },
35947 /* inc.b ${Dsp-8-u8}[sb] */
35948   {
35949     M32C_INSN_INC16_B_DST16_3_S_8_8_SB_RELATIVE_QI, "inc16.b-dst16-3-S-8-8-SB-relative-QI", "inc.b", 16,
35950     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
35951   },
35952 /* inc.b ${Dsp-8-s8}[fb] */
35953   {
35954     M32C_INSN_INC16_B_DST16_3_S_8_8_FB_RELATIVE_QI, "inc16.b-dst16-3-S-8-8-FB-relative-QI", "inc.b", 16,
35955     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
35956   },
35957 /* inc.b ${Dsp-8-u16} */
35958   {
35959     M32C_INSN_INC16_B_DST16_3_S_8_16_ABSOLUTE_QI, "inc16.b-dst16-3-S-8-16-absolute-QI", "inc.b", 24,
35960     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
35961   },
35962 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
35963   {
35964     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 24,
35965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35966   },
35967 /* sub.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
35968   {
35969     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 24,
35970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35971   },
35972 /* sub.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
35973   {
35974     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 24,
35975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35976   },
35977 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
35978   {
35979     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 24,
35980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35981   },
35982 /* sub.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
35983   {
35984     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 24,
35985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35986   },
35987 /* sub.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
35988   {
35989     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 24,
35990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35991   },
35992 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
35993   {
35994     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 24,
35995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35996   },
35997 /* sub.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
35998   {
35999     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 24,
36000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36001   },
36002 /* sub.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
36003   {
36004     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 24,
36005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36006   },
36007 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
36008   {
36009     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "sub.l", 32,
36010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36011   },
36012 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
36013   {
36014     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "sub.l", 32,
36015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36016   },
36017 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
36018   {
36019     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "sub.l", 32,
36020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36021   },
36022 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
36023   {
36024     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "sub.l", 40,
36025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36026   },
36027 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
36028   {
36029     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "sub.l", 40,
36030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36031   },
36032 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
36033   {
36034     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "sub.l", 40,
36035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36036   },
36037 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
36038   {
36039     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "sub.l", 48,
36040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36041   },
36042 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
36043   {
36044     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "sub.l", 48,
36045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36046   },
36047 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
36048   {
36049     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "sub.l", 48,
36050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36051   },
36052 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
36053   {
36054     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "sub.l", 32,
36055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36056   },
36057 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
36058   {
36059     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "sub.l", 32,
36060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36061   },
36062 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
36063   {
36064     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "sub.l", 32,
36065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36066   },
36067 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
36068   {
36069     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "sub.l", 40,
36070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36071   },
36072 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
36073   {
36074     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "sub.l", 40,
36075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36076   },
36077 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
36078   {
36079     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "sub.l", 40,
36080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36081   },
36082 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
36083   {
36084     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "sub.l", 32,
36085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36086   },
36087 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
36088   {
36089     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "sub.l", 32,
36090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36091   },
36092 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
36093   {
36094     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "sub.l", 32,
36095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36096   },
36097 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
36098   {
36099     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "sub.l", 40,
36100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36101   },
36102 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
36103   {
36104     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "sub.l", 40,
36105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36106   },
36107 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
36108   {
36109     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "sub.l", 40,
36110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36111   },
36112 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
36113   {
36114     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "sub.l", 40,
36115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36116   },
36117 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
36118   {
36119     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "sub.l", 40,
36120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36121   },
36122 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
36123   {
36124     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "sub.l", 40,
36125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36126   },
36127 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
36128   {
36129     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "sub.l", 48,
36130     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36131   },
36132 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
36133   {
36134     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "sub.l", 48,
36135     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36136   },
36137 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
36138   {
36139     M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "sub.l", 48,
36140     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36141   },
36142 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
36143   {
36144     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 32,
36145     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36146   },
36147 /* sub.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
36148   {
36149     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 32,
36150     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36151   },
36152 /* sub.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
36153   {
36154     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 32,
36155     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36156   },
36157 /* sub.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
36158   {
36159     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 32,
36160     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36161   },
36162 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
36163   {
36164     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 32,
36165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36166   },
36167 /* sub.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
36168   {
36169     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 32,
36170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36171   },
36172 /* sub.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
36173   {
36174     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 32,
36175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36176   },
36177 /* sub.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
36178   {
36179     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 32,
36180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36181   },
36182 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
36183   {
36184     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 32,
36185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36186   },
36187 /* sub.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
36188   {
36189     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 32,
36190     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36191   },
36192 /* sub.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
36193   {
36194     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 32,
36195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36196   },
36197 /* sub.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
36198   {
36199     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 32,
36200     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36201   },
36202 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
36203   {
36204     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "sub.l", 40,
36205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36206   },
36207 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
36208   {
36209     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "sub.l", 40,
36210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36211   },
36212 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
36213   {
36214     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "sub.l", 40,
36215     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36216   },
36217 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
36218   {
36219     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "sub.l", 40,
36220     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36221   },
36222 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
36223   {
36224     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "sub.l", 48,
36225     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36226   },
36227 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
36228   {
36229     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "sub.l", 48,
36230     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36231   },
36232 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
36233   {
36234     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "sub.l", 48,
36235     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36236   },
36237 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
36238   {
36239     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "sub.l", 48,
36240     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36241   },
36242 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
36243   {
36244     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "sub.l", 56,
36245     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36246   },
36247 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
36248   {
36249     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "sub.l", 56,
36250     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36251   },
36252 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
36253   {
36254     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "sub.l", 56,
36255     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36256   },
36257 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
36258   {
36259     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "sub.l", 56,
36260     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36261   },
36262 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
36263   {
36264     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "sub.l", 40,
36265     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36266   },
36267 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
36268   {
36269     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "sub.l", 40,
36270     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36271   },
36272 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
36273   {
36274     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "sub.l", 40,
36275     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36276   },
36277 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
36278   {
36279     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "sub.l", 40,
36280     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36281   },
36282 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
36283   {
36284     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "sub.l", 48,
36285     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36286   },
36287 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
36288   {
36289     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "sub.l", 48,
36290     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36291   },
36292 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
36293   {
36294     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "sub.l", 48,
36295     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36296   },
36297 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
36298   {
36299     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "sub.l", 48,
36300     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36301   },
36302 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
36303   {
36304     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "sub.l", 40,
36305     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36306   },
36307 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
36308   {
36309     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "sub.l", 40,
36310     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36311   },
36312 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
36313   {
36314     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "sub.l", 40,
36315     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36316   },
36317 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
36318   {
36319     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "sub.l", 40,
36320     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36321   },
36322 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
36323   {
36324     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "sub.l", 48,
36325     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36326   },
36327 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
36328   {
36329     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "sub.l", 48,
36330     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36331   },
36332 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
36333   {
36334     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "sub.l", 48,
36335     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36336   },
36337 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
36338   {
36339     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "sub.l", 48,
36340     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36341   },
36342 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
36343   {
36344     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "sub.l", 48,
36345     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36346   },
36347 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
36348   {
36349     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "sub.l", 48,
36350     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36351   },
36352 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
36353   {
36354     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "sub.l", 48,
36355     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36356   },
36357 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-u16} */
36358   {
36359     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "sub.l", 48,
36360     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36361   },
36362 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
36363   {
36364     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "sub.l", 56,
36365     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36366   },
36367 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
36368   {
36369     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "sub.l", 56,
36370     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36371   },
36372 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
36373   {
36374     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "sub.l", 56,
36375     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36376   },
36377 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-u24} */
36378   {
36379     M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "sub.l", 56,
36380     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36381   },
36382 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
36383   {
36384     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 40,
36385     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36386   },
36387 /* sub.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
36388   {
36389     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 40,
36390     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36391   },
36392 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
36393   {
36394     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 40,
36395     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36396   },
36397 /* sub.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
36398   {
36399     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 40,
36400     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36401   },
36402 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
36403   {
36404     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 40,
36405     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36406   },
36407 /* sub.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
36408   {
36409     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 40,
36410     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36411   },
36412 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
36413   {
36414     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "sub.l", 48,
36415     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36416   },
36417 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
36418   {
36419     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "sub.l", 48,
36420     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36421   },
36422 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
36423   {
36424     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "sub.l", 56,
36425     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36426   },
36427 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
36428   {
36429     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "sub.l", 56,
36430     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36431   },
36432 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
36433   {
36434     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "sub.l", 64,
36435     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36436   },
36437 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
36438   {
36439     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "sub.l", 64,
36440     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36441   },
36442 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
36443   {
36444     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "sub.l", 48,
36445     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36446   },
36447 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
36448   {
36449     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "sub.l", 48,
36450     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36451   },
36452 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
36453   {
36454     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "sub.l", 56,
36455     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36456   },
36457 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
36458   {
36459     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "sub.l", 56,
36460     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36461   },
36462 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
36463   {
36464     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "sub.l", 48,
36465     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36466   },
36467 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
36468   {
36469     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "sub.l", 48,
36470     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36471   },
36472 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
36473   {
36474     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "sub.l", 56,
36475     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36476   },
36477 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
36478   {
36479     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "sub.l", 56,
36480     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36481   },
36482 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
36483   {
36484     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "sub.l", 56,
36485     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36486   },
36487 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-u16} */
36488   {
36489     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "sub.l", 56,
36490     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36491   },
36492 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
36493   {
36494     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "sub.l", 64,
36495     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36496   },
36497 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-u24} */
36498   {
36499     M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "sub.l", 64,
36500     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36501   },
36502 /* sub.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */
36503   {
36504     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 16,
36505     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36506   },
36507 /* sub.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */
36508   {
36509     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 16,
36510     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36511   },
36512 /* sub.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
36513   {
36514     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 16,
36515     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36516   },
36517 /* sub.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */
36518   {
36519     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 16,
36520     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36521   },
36522 /* sub.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */
36523   {
36524     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 16,
36525     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36526   },
36527 /* sub.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
36528   {
36529     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 16,
36530     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36531   },
36532 /* sub.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */
36533   {
36534     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 16,
36535     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36536   },
36537 /* sub.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */
36538   {
36539     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 16,
36540     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36541   },
36542 /* sub.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
36543   {
36544     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 16,
36545     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36546   },
36547 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
36548   {
36549     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "sub.l", 24,
36550     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36551   },
36552 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
36553   {
36554     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "sub.l", 24,
36555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36556   },
36557 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
36558   {
36559     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "sub.l", 24,
36560     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36561   },
36562 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
36563   {
36564     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "sub.l", 32,
36565     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36566   },
36567 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
36568   {
36569     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "sub.l", 32,
36570     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36571   },
36572 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
36573   {
36574     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "sub.l", 32,
36575     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36576   },
36577 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
36578   {
36579     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "sub.l", 40,
36580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36581   },
36582 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
36583   {
36584     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "sub.l", 40,
36585     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36586   },
36587 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
36588   {
36589     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "sub.l", 40,
36590     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36591   },
36592 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */
36593   {
36594     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "sub.l", 24,
36595     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36596   },
36597 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */
36598   {
36599     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "sub.l", 24,
36600     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36601   },
36602 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
36603   {
36604     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "sub.l", 24,
36605     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36606   },
36607 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */
36608   {
36609     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "sub.l", 32,
36610     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36611   },
36612 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */
36613   {
36614     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "sub.l", 32,
36615     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36616   },
36617 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
36618   {
36619     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "sub.l", 32,
36620     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36621   },
36622 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */
36623   {
36624     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "sub.l", 24,
36625     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36626   },
36627 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */
36628   {
36629     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "sub.l", 24,
36630     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36631   },
36632 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
36633   {
36634     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "sub.l", 24,
36635     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36636   },
36637 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */
36638   {
36639     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "sub.l", 32,
36640     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36641   },
36642 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */
36643   {
36644     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "sub.l", 32,
36645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36646   },
36647 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
36648   {
36649     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "sub.l", 32,
36650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36651   },
36652 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */
36653   {
36654     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "sub.l", 32,
36655     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36656   },
36657 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */
36658   {
36659     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "sub.l", 32,
36660     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36661   },
36662 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
36663   {
36664     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "sub.l", 32,
36665     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36666   },
36667 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */
36668   {
36669     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "sub.l", 40,
36670     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36671   },
36672 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */
36673   {
36674     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "sub.l", 40,
36675     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36676   },
36677 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
36678   {
36679     M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "sub.l", 40,
36680     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36681   },
36682 /* sub.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
36683   {
36684     M32C_INSN_SUB32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "sub32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "sub.w", 32,
36685     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36686   },
36687 /* sub.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
36688   {
36689     M32C_INSN_SUB32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "sub32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "sub.w", 32,
36690     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36691   },
36692 /* sub.w${S} #${Imm-24-HI},${Dsp-8-u16} */
36693   {
36694     M32C_INSN_SUB32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "sub32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "sub.w", 40,
36695     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36696   },
36697 /* sub.w${S} #${Imm-8-HI},r0 */
36698   {
36699     M32C_INSN_SUB32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "sub32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "sub.w", 24,
36700     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36701   },
36702 /* sub.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
36703   {
36704     M32C_INSN_SUB32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "sub32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "sub.b", 24,
36705     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36706   },
36707 /* sub.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
36708   {
36709     M32C_INSN_SUB32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "sub32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "sub.b", 24,
36710     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36711   },
36712 /* sub.b${S} #${Imm-24-QI},${Dsp-8-u16} */
36713   {
36714     M32C_INSN_SUB32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "sub32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "sub.b", 32,
36715     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36716   },
36717 /* sub.b${S} #${Imm-8-QI},r0l */
36718   {
36719     M32C_INSN_SUB32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "sub32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "sub.b", 16,
36720     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36721   },
36722 /* sub.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */
36723   {
36724     M32C_INSN_SUB32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "sub.l", 48,
36725     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36726   },
36727 /* sub.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */
36728   {
36729     M32C_INSN_SUB32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "sub.l", 48,
36730     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36731   },
36732 /* sub.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */
36733   {
36734     M32C_INSN_SUB32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "sub.l", 48,
36735     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36736   },
36737 /* sub.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
36738   {
36739     M32C_INSN_SUB32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "sub.l", 56,
36740     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36741   },
36742 /* sub.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */
36743   {
36744     M32C_INSN_SUB32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "sub.l", 56,
36745     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36746   },
36747 /* sub.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */
36748   {
36749     M32C_INSN_SUB32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "sub.l", 56,
36750     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36751   },
36752 /* sub.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
36753   {
36754     M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "sub.l", 64,
36755     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36756   },
36757 /* sub.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */
36758   {
36759     M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "sub.l", 64,
36760     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36761   },
36762 /* sub.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */
36763   {
36764     M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "sub.l", 64,
36765     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36766   },
36767 /* sub.l${G} #${Imm-32-SI},${Dsp-16-u16} */
36768   {
36769     M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "sub.l", 64,
36770     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36771   },
36772 /* sub.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
36773   {
36774     M32C_INSN_SUB32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "sub.l", 72,
36775     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36776   },
36777 /* sub.l${G} #${Imm-40-SI},${Dsp-16-u24} */
36778   {
36779     M32C_INSN_SUB32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "sub.l", 72,
36780     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36781   },
36782 /* sub.b${S} ${SrcDst16-r0l-r0h-S-normal} */
36783   {
36784     M32C_INSN_SUB16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, "sub16.b.S-r0l-r0h-srcdst16-r0l-r0h-S-derived", "sub.b", 8,
36785     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
36786   },
36787 /* sub.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
36788   {
36789     M32C_INSN_SUB16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, "sub16.b.S-src2-src16-2-S-8-SB-relative-QI", "sub.b", 16,
36790     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
36791   },
36792 /* sub.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
36793   {
36794     M32C_INSN_SUB16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, "sub16.b.S-src2-src16-2-S-8-FB-relative-QI", "sub.b", 16,
36795     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
36796   },
36797 /* sub.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
36798   {
36799     M32C_INSN_SUB16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, "sub16.b.S-src2-src16-2-S-16-absolute-QI", "sub.b", 24,
36800     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
36801   },
36802 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
36803   {
36804     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 24,
36805     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36806   },
36807 /* sub.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
36808   {
36809     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 24,
36810     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36811   },
36812 /* sub.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
36813   {
36814     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 24,
36815     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36816   },
36817 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
36818   {
36819     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 24,
36820     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36821   },
36822 /* sub.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
36823   {
36824     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 24,
36825     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36826   },
36827 /* sub.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
36828   {
36829     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 24,
36830     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36831   },
36832 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
36833   {
36834     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 24,
36835     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36836   },
36837 /* sub.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
36838   {
36839     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 24,
36840     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36841   },
36842 /* sub.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
36843   {
36844     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 24,
36845     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36846   },
36847 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
36848   {
36849     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "sub.w", 32,
36850     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36851   },
36852 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
36853   {
36854     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "sub.w", 32,
36855     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36856   },
36857 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
36858   {
36859     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "sub.w", 32,
36860     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36861   },
36862 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
36863   {
36864     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "sub.w", 40,
36865     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36866   },
36867 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
36868   {
36869     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "sub.w", 40,
36870     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36871   },
36872 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
36873   {
36874     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "sub.w", 40,
36875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36876   },
36877 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
36878   {
36879     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "sub.w", 48,
36880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36881   },
36882 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
36883   {
36884     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "sub.w", 48,
36885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36886   },
36887 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
36888   {
36889     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "sub.w", 48,
36890     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36891   },
36892 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
36893   {
36894     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "sub.w", 32,
36895     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36896   },
36897 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
36898   {
36899     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "sub.w", 32,
36900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36901   },
36902 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
36903   {
36904     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "sub.w", 32,
36905     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36906   },
36907 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
36908   {
36909     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "sub.w", 40,
36910     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36911   },
36912 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
36913   {
36914     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "sub.w", 40,
36915     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36916   },
36917 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
36918   {
36919     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "sub.w", 40,
36920     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36921   },
36922 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
36923   {
36924     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "sub.w", 32,
36925     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36926   },
36927 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
36928   {
36929     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "sub.w", 32,
36930     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36931   },
36932 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
36933   {
36934     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "sub.w", 32,
36935     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36936   },
36937 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
36938   {
36939     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "sub.w", 40,
36940     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36941   },
36942 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
36943   {
36944     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "sub.w", 40,
36945     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36946   },
36947 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
36948   {
36949     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "sub.w", 40,
36950     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36951   },
36952 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
36953   {
36954     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "sub.w", 40,
36955     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36956   },
36957 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
36958   {
36959     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "sub.w", 40,
36960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36961   },
36962 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
36963   {
36964     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "sub.w", 40,
36965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36966   },
36967 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
36968   {
36969     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "sub.w", 48,
36970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36971   },
36972 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
36973   {
36974     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "sub.w", 48,
36975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36976   },
36977 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
36978   {
36979     M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "sub.w", 48,
36980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36981   },
36982 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
36983   {
36984     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 32,
36985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36986   },
36987 /* sub.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
36988   {
36989     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 32,
36990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36991   },
36992 /* sub.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
36993   {
36994     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 32,
36995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36996   },
36997 /* sub.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
36998   {
36999     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 32,
37000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37001   },
37002 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
37003   {
37004     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 32,
37005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37006   },
37007 /* sub.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
37008   {
37009     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 32,
37010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37011   },
37012 /* sub.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
37013   {
37014     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 32,
37015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37016   },
37017 /* sub.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
37018   {
37019     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 32,
37020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37021   },
37022 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
37023   {
37024     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 32,
37025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37026   },
37027 /* sub.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
37028   {
37029     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 32,
37030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37031   },
37032 /* sub.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
37033   {
37034     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 32,
37035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37036   },
37037 /* sub.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
37038   {
37039     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 32,
37040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37041   },
37042 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
37043   {
37044     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "sub.w", 40,
37045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37046   },
37047 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
37048   {
37049     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "sub.w", 40,
37050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37051   },
37052 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
37053   {
37054     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "sub.w", 40,
37055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37056   },
37057 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
37058   {
37059     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "sub.w", 40,
37060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37061   },
37062 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
37063   {
37064     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "sub.w", 48,
37065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37066   },
37067 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
37068   {
37069     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "sub.w", 48,
37070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37071   },
37072 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
37073   {
37074     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "sub.w", 48,
37075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37076   },
37077 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
37078   {
37079     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "sub.w", 48,
37080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37081   },
37082 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
37083   {
37084     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "sub.w", 56,
37085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37086   },
37087 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
37088   {
37089     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "sub.w", 56,
37090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37091   },
37092 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
37093   {
37094     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "sub.w", 56,
37095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37096   },
37097 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
37098   {
37099     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "sub.w", 56,
37100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37101   },
37102 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
37103   {
37104     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "sub.w", 40,
37105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37106   },
37107 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
37108   {
37109     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "sub.w", 40,
37110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37111   },
37112 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
37113   {
37114     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "sub.w", 40,
37115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37116   },
37117 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
37118   {
37119     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "sub.w", 40,
37120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37121   },
37122 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
37123   {
37124     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "sub.w", 48,
37125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37126   },
37127 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
37128   {
37129     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "sub.w", 48,
37130     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37131   },
37132 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
37133   {
37134     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "sub.w", 48,
37135     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37136   },
37137 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
37138   {
37139     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "sub.w", 48,
37140     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37141   },
37142 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
37143   {
37144     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "sub.w", 40,
37145     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37146   },
37147 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
37148   {
37149     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "sub.w", 40,
37150     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37151   },
37152 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
37153   {
37154     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "sub.w", 40,
37155     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37156   },
37157 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
37158   {
37159     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "sub.w", 40,
37160     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37161   },
37162 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
37163   {
37164     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "sub.w", 48,
37165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37166   },
37167 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
37168   {
37169     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "sub.w", 48,
37170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37171   },
37172 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
37173   {
37174     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "sub.w", 48,
37175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37176   },
37177 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
37178   {
37179     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "sub.w", 48,
37180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37181   },
37182 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
37183   {
37184     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "sub.w", 48,
37185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37186   },
37187 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
37188   {
37189     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "sub.w", 48,
37190     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37191   },
37192 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
37193   {
37194     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "sub.w", 48,
37195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37196   },
37197 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
37198   {
37199     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "sub.w", 48,
37200     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37201   },
37202 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
37203   {
37204     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "sub.w", 56,
37205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37206   },
37207 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
37208   {
37209     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "sub.w", 56,
37210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37211   },
37212 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
37213   {
37214     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "sub.w", 56,
37215     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37216   },
37217 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
37218   {
37219     M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "sub.w", 56,
37220     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37221   },
37222 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
37223   {
37224     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 40,
37225     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37226   },
37227 /* sub.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
37228   {
37229     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 40,
37230     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37231   },
37232 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
37233   {
37234     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 40,
37235     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37236   },
37237 /* sub.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
37238   {
37239     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 40,
37240     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37241   },
37242 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
37243   {
37244     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 40,
37245     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37246   },
37247 /* sub.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
37248   {
37249     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 40,
37250     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37251   },
37252 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
37253   {
37254     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "sub.w", 48,
37255     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37256   },
37257 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
37258   {
37259     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "sub.w", 48,
37260     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37261   },
37262 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
37263   {
37264     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "sub.w", 56,
37265     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37266   },
37267 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
37268   {
37269     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "sub.w", 56,
37270     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37271   },
37272 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
37273   {
37274     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "sub.w", 64,
37275     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37276   },
37277 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
37278   {
37279     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "sub.w", 64,
37280     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37281   },
37282 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
37283   {
37284     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "sub.w", 48,
37285     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37286   },
37287 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
37288   {
37289     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "sub.w", 48,
37290     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37291   },
37292 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
37293   {
37294     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "sub.w", 56,
37295     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37296   },
37297 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
37298   {
37299     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "sub.w", 56,
37300     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37301   },
37302 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
37303   {
37304     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "sub.w", 48,
37305     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37306   },
37307 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
37308   {
37309     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "sub.w", 48,
37310     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37311   },
37312 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
37313   {
37314     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "sub.w", 56,
37315     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37316   },
37317 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
37318   {
37319     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "sub.w", 56,
37320     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37321   },
37322 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
37323   {
37324     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "sub.w", 56,
37325     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37326   },
37327 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
37328   {
37329     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "sub.w", 56,
37330     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37331   },
37332 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
37333   {
37334     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "sub.w", 64,
37335     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37336   },
37337 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
37338   {
37339     M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "sub.w", 64,
37340     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37341   },
37342 /* sub.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
37343   {
37344     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 16,
37345     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37346   },
37347 /* sub.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
37348   {
37349     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 16,
37350     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37351   },
37352 /* sub.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
37353   {
37354     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 16,
37355     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37356   },
37357 /* sub.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
37358   {
37359     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 16,
37360     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37361   },
37362 /* sub.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
37363   {
37364     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 16,
37365     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37366   },
37367 /* sub.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
37368   {
37369     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 16,
37370     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37371   },
37372 /* sub.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
37373   {
37374     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 16,
37375     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37376   },
37377 /* sub.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
37378   {
37379     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 16,
37380     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37381   },
37382 /* sub.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
37383   {
37384     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 16,
37385     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37386   },
37387 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
37388   {
37389     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "sub.w", 24,
37390     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37391   },
37392 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
37393   {
37394     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "sub.w", 24,
37395     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37396   },
37397 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
37398   {
37399     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "sub.w", 24,
37400     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37401   },
37402 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
37403   {
37404     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "sub.w", 32,
37405     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37406   },
37407 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
37408   {
37409     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "sub.w", 32,
37410     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37411   },
37412 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
37413   {
37414     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "sub.w", 32,
37415     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37416   },
37417 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
37418   {
37419     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "sub.w", 40,
37420     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37421   },
37422 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
37423   {
37424     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "sub.w", 40,
37425     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37426   },
37427 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
37428   {
37429     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "sub.w", 40,
37430     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37431   },
37432 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
37433   {
37434     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "sub.w", 24,
37435     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37436   },
37437 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
37438   {
37439     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "sub.w", 24,
37440     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37441   },
37442 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
37443   {
37444     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "sub.w", 24,
37445     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37446   },
37447 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
37448   {
37449     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "sub.w", 32,
37450     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37451   },
37452 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
37453   {
37454     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "sub.w", 32,
37455     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37456   },
37457 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
37458   {
37459     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "sub.w", 32,
37460     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37461   },
37462 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
37463   {
37464     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "sub.w", 24,
37465     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37466   },
37467 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
37468   {
37469     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "sub.w", 24,
37470     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37471   },
37472 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
37473   {
37474     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "sub.w", 24,
37475     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37476   },
37477 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
37478   {
37479     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "sub.w", 32,
37480     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37481   },
37482 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
37483   {
37484     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "sub.w", 32,
37485     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37486   },
37487 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
37488   {
37489     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "sub.w", 32,
37490     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37491   },
37492 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
37493   {
37494     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "sub.w", 32,
37495     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37496   },
37497 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
37498   {
37499     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "sub.w", 32,
37500     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37501   },
37502 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
37503   {
37504     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "sub.w", 32,
37505     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37506   },
37507 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
37508   {
37509     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "sub.w", 40,
37510     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37511   },
37512 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
37513   {
37514     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "sub.w", 40,
37515     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37516   },
37517 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
37518   {
37519     M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "sub.w", 40,
37520     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37521   },
37522 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
37523   {
37524     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 24,
37525     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37526   },
37527 /* sub.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
37528   {
37529     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 24,
37530     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37531   },
37532 /* sub.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
37533   {
37534     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 24,
37535     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37536   },
37537 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
37538   {
37539     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 24,
37540     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37541   },
37542 /* sub.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
37543   {
37544     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 24,
37545     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37546   },
37547 /* sub.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
37548   {
37549     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 24,
37550     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37551   },
37552 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
37553   {
37554     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 24,
37555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37556   },
37557 /* sub.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
37558   {
37559     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 24,
37560     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37561   },
37562 /* sub.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
37563   {
37564     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 24,
37565     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37566   },
37567 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
37568   {
37569     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "sub.b", 32,
37570     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37571   },
37572 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
37573   {
37574     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "sub.b", 32,
37575     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37576   },
37577 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
37578   {
37579     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "sub.b", 32,
37580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37581   },
37582 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
37583   {
37584     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "sub.b", 40,
37585     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37586   },
37587 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
37588   {
37589     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "sub.b", 40,
37590     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37591   },
37592 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
37593   {
37594     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "sub.b", 40,
37595     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37596   },
37597 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
37598   {
37599     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "sub.b", 48,
37600     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37601   },
37602 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
37603   {
37604     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "sub.b", 48,
37605     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37606   },
37607 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
37608   {
37609     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "sub.b", 48,
37610     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37611   },
37612 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
37613   {
37614     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "sub.b", 32,
37615     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37616   },
37617 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
37618   {
37619     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "sub.b", 32,
37620     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37621   },
37622 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
37623   {
37624     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "sub.b", 32,
37625     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37626   },
37627 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
37628   {
37629     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "sub.b", 40,
37630     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37631   },
37632 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
37633   {
37634     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "sub.b", 40,
37635     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37636   },
37637 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
37638   {
37639     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "sub.b", 40,
37640     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37641   },
37642 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
37643   {
37644     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "sub.b", 32,
37645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37646   },
37647 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
37648   {
37649     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "sub.b", 32,
37650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37651   },
37652 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
37653   {
37654     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "sub.b", 32,
37655     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37656   },
37657 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
37658   {
37659     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "sub.b", 40,
37660     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37661   },
37662 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
37663   {
37664     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "sub.b", 40,
37665     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37666   },
37667 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
37668   {
37669     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "sub.b", 40,
37670     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37671   },
37672 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
37673   {
37674     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "sub.b", 40,
37675     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37676   },
37677 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
37678   {
37679     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "sub.b", 40,
37680     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37681   },
37682 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
37683   {
37684     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "sub.b", 40,
37685     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37686   },
37687 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
37688   {
37689     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "sub.b", 48,
37690     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37691   },
37692 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
37693   {
37694     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "sub.b", 48,
37695     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37696   },
37697 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
37698   {
37699     M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "sub.b", 48,
37700     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37701   },
37702 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
37703   {
37704     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 32,
37705     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37706   },
37707 /* sub.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
37708   {
37709     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 32,
37710     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37711   },
37712 /* sub.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
37713   {
37714     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 32,
37715     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37716   },
37717 /* sub.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
37718   {
37719     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 32,
37720     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37721   },
37722 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
37723   {
37724     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 32,
37725     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37726   },
37727 /* sub.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
37728   {
37729     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 32,
37730     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37731   },
37732 /* sub.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
37733   {
37734     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 32,
37735     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37736   },
37737 /* sub.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
37738   {
37739     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 32,
37740     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37741   },
37742 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
37743   {
37744     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 32,
37745     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37746   },
37747 /* sub.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
37748   {
37749     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 32,
37750     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37751   },
37752 /* sub.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
37753   {
37754     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 32,
37755     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37756   },
37757 /* sub.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
37758   {
37759     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 32,
37760     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37761   },
37762 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
37763   {
37764     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "sub.b", 40,
37765     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37766   },
37767 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
37768   {
37769     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "sub.b", 40,
37770     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37771   },
37772 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
37773   {
37774     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "sub.b", 40,
37775     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37776   },
37777 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
37778   {
37779     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "sub.b", 40,
37780     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37781   },
37782 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
37783   {
37784     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "sub.b", 48,
37785     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37786   },
37787 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
37788   {
37789     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "sub.b", 48,
37790     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37791   },
37792 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
37793   {
37794     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "sub.b", 48,
37795     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37796   },
37797 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
37798   {
37799     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "sub.b", 48,
37800     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37801   },
37802 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
37803   {
37804     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "sub.b", 56,
37805     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37806   },
37807 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
37808   {
37809     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "sub.b", 56,
37810     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37811   },
37812 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
37813   {
37814     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "sub.b", 56,
37815     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37816   },
37817 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
37818   {
37819     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "sub.b", 56,
37820     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37821   },
37822 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
37823   {
37824     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "sub.b", 40,
37825     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37826   },
37827 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
37828   {
37829     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "sub.b", 40,
37830     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37831   },
37832 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
37833   {
37834     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "sub.b", 40,
37835     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37836   },
37837 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
37838   {
37839     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "sub.b", 40,
37840     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37841   },
37842 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
37843   {
37844     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "sub.b", 48,
37845     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37846   },
37847 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
37848   {
37849     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "sub.b", 48,
37850     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37851   },
37852 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
37853   {
37854     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "sub.b", 48,
37855     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37856   },
37857 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
37858   {
37859     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "sub.b", 48,
37860     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37861   },
37862 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
37863   {
37864     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "sub.b", 40,
37865     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37866   },
37867 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
37868   {
37869     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "sub.b", 40,
37870     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37871   },
37872 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
37873   {
37874     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "sub.b", 40,
37875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37876   },
37877 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
37878   {
37879     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "sub.b", 40,
37880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37881   },
37882 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
37883   {
37884     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "sub.b", 48,
37885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37886   },
37887 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
37888   {
37889     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "sub.b", 48,
37890     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37891   },
37892 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
37893   {
37894     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "sub.b", 48,
37895     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37896   },
37897 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
37898   {
37899     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "sub.b", 48,
37900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37901   },
37902 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
37903   {
37904     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "sub.b", 48,
37905     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37906   },
37907 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
37908   {
37909     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "sub.b", 48,
37910     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37911   },
37912 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
37913   {
37914     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "sub.b", 48,
37915     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37916   },
37917 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
37918   {
37919     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "sub.b", 48,
37920     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37921   },
37922 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
37923   {
37924     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "sub.b", 56,
37925     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37926   },
37927 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
37928   {
37929     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "sub.b", 56,
37930     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37931   },
37932 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
37933   {
37934     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "sub.b", 56,
37935     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37936   },
37937 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
37938   {
37939     M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "sub.b", 56,
37940     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37941   },
37942 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
37943   {
37944     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 40,
37945     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37946   },
37947 /* sub.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
37948   {
37949     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 40,
37950     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37951   },
37952 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
37953   {
37954     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 40,
37955     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37956   },
37957 /* sub.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
37958   {
37959     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 40,
37960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37961   },
37962 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
37963   {
37964     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 40,
37965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37966   },
37967 /* sub.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
37968   {
37969     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 40,
37970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37971   },
37972 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
37973   {
37974     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "sub.b", 48,
37975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37976   },
37977 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
37978   {
37979     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "sub.b", 48,
37980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37981   },
37982 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
37983   {
37984     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "sub.b", 56,
37985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37986   },
37987 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
37988   {
37989     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "sub.b", 56,
37990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37991   },
37992 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
37993   {
37994     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "sub.b", 64,
37995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37996   },
37997 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
37998   {
37999     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "sub.b", 64,
38000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38001   },
38002 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
38003   {
38004     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "sub.b", 48,
38005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38006   },
38007 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
38008   {
38009     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "sub.b", 48,
38010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38011   },
38012 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
38013   {
38014     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "sub.b", 56,
38015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38016   },
38017 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
38018   {
38019     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "sub.b", 56,
38020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38021   },
38022 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
38023   {
38024     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "sub.b", 48,
38025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38026   },
38027 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
38028   {
38029     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "sub.b", 48,
38030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38031   },
38032 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
38033   {
38034     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "sub.b", 56,
38035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38036   },
38037 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
38038   {
38039     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "sub.b", 56,
38040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38041   },
38042 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
38043   {
38044     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "sub.b", 56,
38045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38046   },
38047 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
38048   {
38049     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "sub.b", 56,
38050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38051   },
38052 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
38053   {
38054     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "sub.b", 64,
38055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38056   },
38057 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
38058   {
38059     M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "sub.b", 64,
38060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38061   },
38062 /* sub.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
38063   {
38064     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 16,
38065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38066   },
38067 /* sub.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
38068   {
38069     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 16,
38070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38071   },
38072 /* sub.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
38073   {
38074     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 16,
38075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38076   },
38077 /* sub.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
38078   {
38079     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 16,
38080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38081   },
38082 /* sub.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
38083   {
38084     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 16,
38085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38086   },
38087 /* sub.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
38088   {
38089     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 16,
38090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38091   },
38092 /* sub.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
38093   {
38094     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 16,
38095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38096   },
38097 /* sub.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
38098   {
38099     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 16,
38100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38101   },
38102 /* sub.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
38103   {
38104     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 16,
38105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38106   },
38107 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
38108   {
38109     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "sub.b", 24,
38110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38111   },
38112 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
38113   {
38114     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "sub.b", 24,
38115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38116   },
38117 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
38118   {
38119     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "sub.b", 24,
38120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38121   },
38122 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
38123   {
38124     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "sub.b", 32,
38125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38126   },
38127 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
38128   {
38129     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "sub.b", 32,
38130     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38131   },
38132 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
38133   {
38134     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "sub.b", 32,
38135     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38136   },
38137 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
38138   {
38139     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "sub.b", 40,
38140     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38141   },
38142 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
38143   {
38144     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "sub.b", 40,
38145     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38146   },
38147 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
38148   {
38149     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "sub.b", 40,
38150     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38151   },
38152 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
38153   {
38154     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "sub.b", 24,
38155     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38156   },
38157 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
38158   {
38159     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "sub.b", 24,
38160     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38161   },
38162 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
38163   {
38164     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "sub.b", 24,
38165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38166   },
38167 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
38168   {
38169     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "sub.b", 32,
38170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38171   },
38172 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
38173   {
38174     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "sub.b", 32,
38175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38176   },
38177 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
38178   {
38179     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "sub.b", 32,
38180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38181   },
38182 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
38183   {
38184     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "sub.b", 24,
38185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38186   },
38187 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
38188   {
38189     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "sub.b", 24,
38190     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38191   },
38192 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
38193   {
38194     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "sub.b", 24,
38195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38196   },
38197 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
38198   {
38199     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "sub.b", 32,
38200     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38201   },
38202 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
38203   {
38204     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "sub.b", 32,
38205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38206   },
38207 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
38208   {
38209     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "sub.b", 32,
38210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38211   },
38212 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
38213   {
38214     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "sub.b", 32,
38215     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38216   },
38217 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
38218   {
38219     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "sub.b", 32,
38220     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38221   },
38222 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
38223   {
38224     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "sub.b", 32,
38225     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38226   },
38227 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
38228   {
38229     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "sub.b", 40,
38230     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38231   },
38232 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
38233   {
38234     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "sub.b", 40,
38235     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38236   },
38237 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
38238   {
38239     M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "sub.b", 40,
38240     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38241   },
38242 /* sub.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
38243   {
38244     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "sub.w", 24,
38245     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38246   },
38247 /* sub.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
38248   {
38249     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "sub.w", 24,
38250     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38251   },
38252 /* sub.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
38253   {
38254     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "sub.w", 24,
38255     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38256   },
38257 /* sub.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
38258   {
38259     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "sub.w", 24,
38260     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38261   },
38262 /* sub.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
38263   {
38264     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "sub.w", 24,
38265     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38266   },
38267 /* sub.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
38268   {
38269     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "sub.w", 24,
38270     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38271   },
38272 /* sub.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
38273   {
38274     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "sub.w", 24,
38275     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38276   },
38277 /* sub.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
38278   {
38279     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "sub.w", 24,
38280     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38281   },
38282 /* sub.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
38283   {
38284     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "sub.w", 24,
38285     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38286   },
38287 /* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
38288   {
38289     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "sub.w", 32,
38290     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38291   },
38292 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
38293   {
38294     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "sub.w", 32,
38295     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38296   },
38297 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
38298   {
38299     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "sub.w", 32,
38300     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38301   },
38302 /* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
38303   {
38304     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "sub.w", 40,
38305     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38306   },
38307 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
38308   {
38309     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "sub.w", 40,
38310     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38311   },
38312 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
38313   {
38314     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "sub.w", 40,
38315     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38316   },
38317 /* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
38318   {
38319     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "sub.w", 32,
38320     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38321   },
38322 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
38323   {
38324     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "sub.w", 32,
38325     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38326   },
38327 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
38328   {
38329     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "sub.w", 32,
38330     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38331   },
38332 /* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
38333   {
38334     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "sub.w", 40,
38335     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38336   },
38337 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
38338   {
38339     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "sub.w", 40,
38340     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38341   },
38342 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
38343   {
38344     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "sub.w", 40,
38345     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38346   },
38347 /* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
38348   {
38349     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "sub.w", 32,
38350     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38351   },
38352 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
38353   {
38354     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "sub.w", 32,
38355     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38356   },
38357 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
38358   {
38359     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "sub.w", 32,
38360     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38361   },
38362 /* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
38363   {
38364     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "sub.w", 40,
38365     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38366   },
38367 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
38368   {
38369     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "sub.w", 40,
38370     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38371   },
38372 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
38373   {
38374     M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "sub.w", 40,
38375     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38376   },
38377 /* sub.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
38378   {
38379     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "sub.w", 32,
38380     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38381   },
38382 /* sub.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
38383   {
38384     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "sub.w", 32,
38385     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38386   },
38387 /* sub.w${G} ${Dsp-16-u16},$Dst16RnHI */
38388   {
38389     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "sub.w", 32,
38390     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38391   },
38392 /* sub.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
38393   {
38394     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "sub.w", 32,
38395     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38396   },
38397 /* sub.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
38398   {
38399     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "sub.w", 32,
38400     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38401   },
38402 /* sub.w${G} ${Dsp-16-u16},$Dst16AnHI */
38403   {
38404     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "sub.w", 32,
38405     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38406   },
38407 /* sub.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
38408   {
38409     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "sub.w", 32,
38410     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38411   },
38412 /* sub.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
38413   {
38414     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "sub.w", 32,
38415     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38416   },
38417 /* sub.w${G} ${Dsp-16-u16},[$Dst16An] */
38418   {
38419     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "sub.w", 32,
38420     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38421   },
38422 /* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
38423   {
38424     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "sub.w", 40,
38425     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38426   },
38427 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
38428   {
38429     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "sub.w", 40,
38430     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38431   },
38432 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
38433   {
38434     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "sub.w", 40,
38435     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38436   },
38437 /* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
38438   {
38439     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "sub.w", 48,
38440     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38441   },
38442 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
38443   {
38444     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "sub.w", 48,
38445     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38446   },
38447 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
38448   {
38449     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "sub.w", 48,
38450     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38451   },
38452 /* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
38453   {
38454     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "sub.w", 40,
38455     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38456   },
38457 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
38458   {
38459     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "sub.w", 40,
38460     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38461   },
38462 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
38463   {
38464     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "sub.w", 40,
38465     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38466   },
38467 /* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
38468   {
38469     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "sub.w", 48,
38470     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38471   },
38472 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
38473   {
38474     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "sub.w", 48,
38475     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38476   },
38477 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
38478   {
38479     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "sub.w", 48,
38480     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38481   },
38482 /* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
38483   {
38484     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "sub.w", 40,
38485     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38486   },
38487 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
38488   {
38489     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "sub.w", 40,
38490     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38491   },
38492 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
38493   {
38494     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "sub.w", 40,
38495     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38496   },
38497 /* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
38498   {
38499     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "sub.w", 48,
38500     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38501   },
38502 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
38503   {
38504     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "sub.w", 48,
38505     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38506   },
38507 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
38508   {
38509     M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "sub.w", 48,
38510     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38511   },
38512 /* sub.w${G} $Src16RnHI,$Dst16RnHI */
38513   {
38514     M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "sub.w", 16,
38515     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38516   },
38517 /* sub.w${G} $Src16AnHI,$Dst16RnHI */
38518   {
38519     M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "sub.w", 16,
38520     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38521   },
38522 /* sub.w${G} [$Src16An],$Dst16RnHI */
38523   {
38524     M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "sub.w", 16,
38525     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38526   },
38527 /* sub.w${G} $Src16RnHI,$Dst16AnHI */
38528   {
38529     M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "sub.w", 16,
38530     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38531   },
38532 /* sub.w${G} $Src16AnHI,$Dst16AnHI */
38533   {
38534     M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "sub.w", 16,
38535     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38536   },
38537 /* sub.w${G} [$Src16An],$Dst16AnHI */
38538   {
38539     M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "sub.w", 16,
38540     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38541   },
38542 /* sub.w${G} $Src16RnHI,[$Dst16An] */
38543   {
38544     M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "sub.w", 16,
38545     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38546   },
38547 /* sub.w${G} $Src16AnHI,[$Dst16An] */
38548   {
38549     M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "sub.w", 16,
38550     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38551   },
38552 /* sub.w${G} [$Src16An],[$Dst16An] */
38553   {
38554     M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "sub.w", 16,
38555     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38556   },
38557 /* sub.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
38558   {
38559     M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "sub.w", 24,
38560     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38561   },
38562 /* sub.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
38563   {
38564     M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "sub.w", 24,
38565     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38566   },
38567 /* sub.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
38568   {
38569     M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "sub.w", 24,
38570     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38571   },
38572 /* sub.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
38573   {
38574     M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "sub.w", 32,
38575     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38576   },
38577 /* sub.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
38578   {
38579     M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "sub.w", 32,
38580     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38581   },
38582 /* sub.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
38583   {
38584     M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "sub.w", 32,
38585     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38586   },
38587 /* sub.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
38588   {
38589     M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "sub.w", 24,
38590     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38591   },
38592 /* sub.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
38593   {
38594     M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "sub.w", 24,
38595     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38596   },
38597 /* sub.w${G} [$Src16An],${Dsp-16-u8}[sb] */
38598   {
38599     M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "sub.w", 24,
38600     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38601   },
38602 /* sub.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
38603   {
38604     M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "sub.w", 32,
38605     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38606   },
38607 /* sub.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
38608   {
38609     M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "sub.w", 32,
38610     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38611   },
38612 /* sub.w${G} [$Src16An],${Dsp-16-u16}[sb] */
38613   {
38614     M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "sub.w", 32,
38615     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38616   },
38617 /* sub.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
38618   {
38619     M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "sub.w", 24,
38620     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38621   },
38622 /* sub.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
38623   {
38624     M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "sub.w", 24,
38625     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38626   },
38627 /* sub.w${G} [$Src16An],${Dsp-16-s8}[fb] */
38628   {
38629     M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "sub.w", 24,
38630     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38631   },
38632 /* sub.w${G} $Src16RnHI,${Dsp-16-u16} */
38633   {
38634     M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "sub.w", 32,
38635     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38636   },
38637 /* sub.w${G} $Src16AnHI,${Dsp-16-u16} */
38638   {
38639     M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "sub.w", 32,
38640     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38641   },
38642 /* sub.w${G} [$Src16An],${Dsp-16-u16} */
38643   {
38644     M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "sub.w", 32,
38645     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38646   },
38647 /* sub.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
38648   {
38649     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "sub.b", 24,
38650     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38651   },
38652 /* sub.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
38653   {
38654     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "sub.b", 24,
38655     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38656   },
38657 /* sub.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
38658   {
38659     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "sub.b", 24,
38660     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38661   },
38662 /* sub.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
38663   {
38664     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "sub.b", 24,
38665     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38666   },
38667 /* sub.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
38668   {
38669     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "sub.b", 24,
38670     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38671   },
38672 /* sub.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
38673   {
38674     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "sub.b", 24,
38675     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38676   },
38677 /* sub.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
38678   {
38679     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "sub.b", 24,
38680     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38681   },
38682 /* sub.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
38683   {
38684     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "sub.b", 24,
38685     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38686   },
38687 /* sub.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
38688   {
38689     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "sub.b", 24,
38690     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38691   },
38692 /* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
38693   {
38694     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "sub.b", 32,
38695     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38696   },
38697 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
38698   {
38699     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "sub.b", 32,
38700     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38701   },
38702 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
38703   {
38704     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "sub.b", 32,
38705     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38706   },
38707 /* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
38708   {
38709     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "sub.b", 40,
38710     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38711   },
38712 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
38713   {
38714     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "sub.b", 40,
38715     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38716   },
38717 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
38718   {
38719     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "sub.b", 40,
38720     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38721   },
38722 /* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
38723   {
38724     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "sub.b", 32,
38725     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38726   },
38727 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
38728   {
38729     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "sub.b", 32,
38730     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38731   },
38732 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
38733   {
38734     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "sub.b", 32,
38735     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38736   },
38737 /* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
38738   {
38739     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "sub.b", 40,
38740     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38741   },
38742 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
38743   {
38744     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "sub.b", 40,
38745     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38746   },
38747 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
38748   {
38749     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "sub.b", 40,
38750     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38751   },
38752 /* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
38753   {
38754     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "sub.b", 32,
38755     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38756   },
38757 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
38758   {
38759     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "sub.b", 32,
38760     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38761   },
38762 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
38763   {
38764     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "sub.b", 32,
38765     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38766   },
38767 /* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
38768   {
38769     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "sub.b", 40,
38770     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38771   },
38772 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
38773   {
38774     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "sub.b", 40,
38775     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38776   },
38777 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
38778   {
38779     M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "sub.b", 40,
38780     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38781   },
38782 /* sub.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
38783   {
38784     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "sub.b", 32,
38785     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38786   },
38787 /* sub.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
38788   {
38789     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "sub.b", 32,
38790     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38791   },
38792 /* sub.b${G} ${Dsp-16-u16},$Dst16RnQI */
38793   {
38794     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "sub.b", 32,
38795     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38796   },
38797 /* sub.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
38798   {
38799     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "sub.b", 32,
38800     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38801   },
38802 /* sub.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
38803   {
38804     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "sub.b", 32,
38805     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38806   },
38807 /* sub.b${G} ${Dsp-16-u16},$Dst16AnQI */
38808   {
38809     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "sub.b", 32,
38810     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38811   },
38812 /* sub.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
38813   {
38814     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "sub.b", 32,
38815     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38816   },
38817 /* sub.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
38818   {
38819     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "sub.b", 32,
38820     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38821   },
38822 /* sub.b${G} ${Dsp-16-u16},[$Dst16An] */
38823   {
38824     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "sub.b", 32,
38825     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38826   },
38827 /* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
38828   {
38829     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "sub.b", 40,
38830     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38831   },
38832 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
38833   {
38834     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "sub.b", 40,
38835     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38836   },
38837 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
38838   {
38839     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "sub.b", 40,
38840     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38841   },
38842 /* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
38843   {
38844     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "sub.b", 48,
38845     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38846   },
38847 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
38848   {
38849     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "sub.b", 48,
38850     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38851   },
38852 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
38853   {
38854     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "sub.b", 48,
38855     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38856   },
38857 /* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
38858   {
38859     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "sub.b", 40,
38860     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38861   },
38862 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
38863   {
38864     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "sub.b", 40,
38865     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38866   },
38867 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
38868   {
38869     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "sub.b", 40,
38870     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38871   },
38872 /* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
38873   {
38874     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "sub.b", 48,
38875     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38876   },
38877 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
38878   {
38879     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "sub.b", 48,
38880     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38881   },
38882 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
38883   {
38884     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "sub.b", 48,
38885     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38886   },
38887 /* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
38888   {
38889     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "sub.b", 40,
38890     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38891   },
38892 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
38893   {
38894     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "sub.b", 40,
38895     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38896   },
38897 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
38898   {
38899     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "sub.b", 40,
38900     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38901   },
38902 /* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
38903   {
38904     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "sub.b", 48,
38905     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38906   },
38907 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
38908   {
38909     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "sub.b", 48,
38910     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38911   },
38912 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
38913   {
38914     M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "sub.b", 48,
38915     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38916   },
38917 /* sub.b${G} $Src16RnQI,$Dst16RnQI */
38918   {
38919     M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "sub.b", 16,
38920     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38921   },
38922 /* sub.b${G} $Src16AnQI,$Dst16RnQI */
38923   {
38924     M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "sub.b", 16,
38925     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38926   },
38927 /* sub.b${G} [$Src16An],$Dst16RnQI */
38928   {
38929     M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "sub.b", 16,
38930     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38931   },
38932 /* sub.b${G} $Src16RnQI,$Dst16AnQI */
38933   {
38934     M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "sub.b", 16,
38935     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38936   },
38937 /* sub.b${G} $Src16AnQI,$Dst16AnQI */
38938   {
38939     M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "sub.b", 16,
38940     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38941   },
38942 /* sub.b${G} [$Src16An],$Dst16AnQI */
38943   {
38944     M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "sub.b", 16,
38945     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38946   },
38947 /* sub.b${G} $Src16RnQI,[$Dst16An] */
38948   {
38949     M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "sub.b", 16,
38950     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38951   },
38952 /* sub.b${G} $Src16AnQI,[$Dst16An] */
38953   {
38954     M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "sub.b", 16,
38955     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38956   },
38957 /* sub.b${G} [$Src16An],[$Dst16An] */
38958   {
38959     M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "sub.b", 16,
38960     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38961   },
38962 /* sub.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
38963   {
38964     M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "sub.b", 24,
38965     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38966   },
38967 /* sub.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
38968   {
38969     M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "sub.b", 24,
38970     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38971   },
38972 /* sub.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
38973   {
38974     M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "sub.b", 24,
38975     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38976   },
38977 /* sub.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
38978   {
38979     M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "sub.b", 32,
38980     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38981   },
38982 /* sub.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
38983   {
38984     M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "sub.b", 32,
38985     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38986   },
38987 /* sub.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
38988   {
38989     M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "sub.b", 32,
38990     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38991   },
38992 /* sub.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
38993   {
38994     M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "sub.b", 24,
38995     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38996   },
38997 /* sub.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
38998   {
38999     M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "sub.b", 24,
39000     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39001   },
39002 /* sub.b${G} [$Src16An],${Dsp-16-u8}[sb] */
39003   {
39004     M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "sub.b", 24,
39005     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39006   },
39007 /* sub.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
39008   {
39009     M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "sub.b", 32,
39010     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39011   },
39012 /* sub.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
39013   {
39014     M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "sub.b", 32,
39015     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39016   },
39017 /* sub.b${G} [$Src16An],${Dsp-16-u16}[sb] */
39018   {
39019     M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "sub.b", 32,
39020     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39021   },
39022 /* sub.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
39023   {
39024     M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "sub.b", 24,
39025     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39026   },
39027 /* sub.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
39028   {
39029     M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "sub.b", 24,
39030     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39031   },
39032 /* sub.b${G} [$Src16An],${Dsp-16-s8}[fb] */
39033   {
39034     M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "sub.b", 24,
39035     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39036   },
39037 /* sub.b${G} $Src16RnQI,${Dsp-16-u16} */
39038   {
39039     M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "sub.b", 32,
39040     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39041   },
39042 /* sub.b${G} $Src16AnQI,${Dsp-16-u16} */
39043   {
39044     M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "sub.b", 32,
39045     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39046   },
39047 /* sub.b${G} [$Src16An],${Dsp-16-u16} */
39048   {
39049     M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "sub.b", 32,
39050     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39051   },
39052 /* sub.b${S} #${Imm-8-QI},r0l */
39053   {
39054     M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "sub16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "sub.b", 16,
39055     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39056   },
39057 /* sub.b${S} #${Imm-8-QI},r0h */
39058   {
39059     M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "sub16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "sub.b", 16,
39060     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39061   },
39062 /* sub.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
39063   {
39064     M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "sub16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "sub.b", 24,
39065     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39066   },
39067 /* sub.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
39068   {
39069     M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "sub16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "sub.b", 24,
39070     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39071   },
39072 /* sub.b${S} #${Imm-8-QI},${Dsp-16-u16} */
39073   {
39074     M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "sub16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "sub.b", 32,
39075     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39076   },
39077 /* sub.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
39078   {
39079     M32C_INSN_SUB32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "sub.w", 32,
39080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39081   },
39082 /* sub.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
39083   {
39084     M32C_INSN_SUB32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "sub.w", 32,
39085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39086   },
39087 /* sub.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
39088   {
39089     M32C_INSN_SUB32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "sub.w", 32,
39090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39091   },
39092 /* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
39093   {
39094     M32C_INSN_SUB32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "sub.w", 40,
39095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39096   },
39097 /* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
39098   {
39099     M32C_INSN_SUB32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "sub.w", 40,
39100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39101   },
39102 /* sub.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
39103   {
39104     M32C_INSN_SUB32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "sub.w", 40,
39105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39106   },
39107 /* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
39108   {
39109     M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "sub.w", 48,
39110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39111   },
39112 /* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
39113   {
39114     M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "sub.w", 48,
39115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39116   },
39117 /* sub.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
39118   {
39119     M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "sub.w", 48,
39120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39121   },
39122 /* sub.w${G} #${Imm-32-HI},${Dsp-16-u16} */
39123   {
39124     M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "sub.w", 48,
39125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39126   },
39127 /* sub.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
39128   {
39129     M32C_INSN_SUB32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "sub.w", 56,
39130     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39131   },
39132 /* sub.w${G} #${Imm-40-HI},${Dsp-16-u24} */
39133   {
39134     M32C_INSN_SUB32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "sub.w", 56,
39135     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39136   },
39137 /* sub.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
39138   {
39139     M32C_INSN_SUB32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "sub.b", 24,
39140     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39141   },
39142 /* sub.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
39143   {
39144     M32C_INSN_SUB32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "sub.b", 24,
39145     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39146   },
39147 /* sub.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
39148   {
39149     M32C_INSN_SUB32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "sub.b", 24,
39150     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39151   },
39152 /* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
39153   {
39154     M32C_INSN_SUB32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "sub.b", 32,
39155     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39156   },
39157 /* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
39158   {
39159     M32C_INSN_SUB32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "sub.b", 32,
39160     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39161   },
39162 /* sub.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
39163   {
39164     M32C_INSN_SUB32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "sub.b", 32,
39165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39166   },
39167 /* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
39168   {
39169     M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "sub.b", 40,
39170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39171   },
39172 /* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
39173   {
39174     M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "sub.b", 40,
39175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39176   },
39177 /* sub.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
39178   {
39179     M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "sub.b", 40,
39180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39181   },
39182 /* sub.b${G} #${Imm-32-QI},${Dsp-16-u16} */
39183   {
39184     M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "sub.b", 40,
39185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39186   },
39187 /* sub.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
39188   {
39189     M32C_INSN_SUB32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "sub.b", 48,
39190     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39191   },
39192 /* sub.b${G} #${Imm-40-QI},${Dsp-16-u24} */
39193   {
39194     M32C_INSN_SUB32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "sub.b", 48,
39195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39196   },
39197 /* sub.w${G} #${Imm-16-HI},$Dst16RnHI */
39198   {
39199     M32C_INSN_SUB16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "sub16.w-imm-G-basic-dst16-Rn-direct-HI", "sub.w", 32,
39200     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39201   },
39202 /* sub.w${G} #${Imm-16-HI},$Dst16AnHI */
39203   {
39204     M32C_INSN_SUB16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "sub16.w-imm-G-basic-dst16-An-direct-HI", "sub.w", 32,
39205     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39206   },
39207 /* sub.w${G} #${Imm-16-HI},[$Dst16An] */
39208   {
39209     M32C_INSN_SUB16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "sub16.w-imm-G-basic-dst16-An-indirect-HI", "sub.w", 32,
39210     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39211   },
39212 /* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
39213   {
39214     M32C_INSN_SUB16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "sub16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "sub.w", 40,
39215     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39216   },
39217 /* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
39218   {
39219     M32C_INSN_SUB16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "sub16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "sub.w", 40,
39220     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39221   },
39222 /* sub.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
39223   {
39224     M32C_INSN_SUB16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "sub16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "sub.w", 40,
39225     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39226   },
39227 /* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
39228   {
39229     M32C_INSN_SUB16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "sub16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "sub.w", 48,
39230     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39231   },
39232 /* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
39233   {
39234     M32C_INSN_SUB16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "sub16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "sub.w", 48,
39235     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39236   },
39237 /* sub.w${G} #${Imm-32-HI},${Dsp-16-u16} */
39238   {
39239     M32C_INSN_SUB16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "sub16.w-imm-G-16-16-dst16-16-16-absolute-HI", "sub.w", 48,
39240     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39241   },
39242 /* sub.b${G} #${Imm-16-QI},$Dst16RnQI */
39243   {
39244     M32C_INSN_SUB16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "sub16.b-imm-G-basic-dst16-Rn-direct-QI", "sub.b", 24,
39245     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39246   },
39247 /* sub.b${G} #${Imm-16-QI},$Dst16AnQI */
39248   {
39249     M32C_INSN_SUB16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "sub16.b-imm-G-basic-dst16-An-direct-QI", "sub.b", 24,
39250     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39251   },
39252 /* sub.b${G} #${Imm-16-QI},[$Dst16An] */
39253   {
39254     M32C_INSN_SUB16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "sub16.b-imm-G-basic-dst16-An-indirect-QI", "sub.b", 24,
39255     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39256   },
39257 /* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
39258   {
39259     M32C_INSN_SUB16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "sub16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "sub.b", 32,
39260     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39261   },
39262 /* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
39263   {
39264     M32C_INSN_SUB16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "sub16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "sub.b", 32,
39265     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39266   },
39267 /* sub.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
39268   {
39269     M32C_INSN_SUB16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "sub16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "sub.b", 32,
39270     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39271   },
39272 /* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
39273   {
39274     M32C_INSN_SUB16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "sub16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "sub.b", 40,
39275     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39276   },
39277 /* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
39278   {
39279     M32C_INSN_SUB16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "sub16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "sub.b", 40,
39280     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39281   },
39282 /* sub.b${G} #${Imm-32-QI},${Dsp-16-u16} */
39283   {
39284     M32C_INSN_SUB16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "sub16.b-imm-G-16-16-dst16-16-16-absolute-QI", "sub.b", 40,
39285     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
39286   },
39287 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
39288   {
39289     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 32,
39290     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39291   },
39292 /* dsub.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
39293   {
39294     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 32,
39295     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39296   },
39297 /* dsub.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
39298   {
39299     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 32,
39300     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39301   },
39302 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
39303   {
39304     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 32,
39305     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39306   },
39307 /* dsub.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
39308   {
39309     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 32,
39310     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39311   },
39312 /* dsub.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
39313   {
39314     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 32,
39315     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39316   },
39317 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
39318   {
39319     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 32,
39320     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39321   },
39322 /* dsub.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
39323   {
39324     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 32,
39325     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39326   },
39327 /* dsub.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
39328   {
39329     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 32,
39330     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39331   },
39332 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
39333   {
39334     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsub.w", 40,
39335     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39336   },
39337 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
39338   {
39339     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsub.w", 40,
39340     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39341   },
39342 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
39343   {
39344     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsub.w", 40,
39345     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39346   },
39347 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
39348   {
39349     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsub.w", 48,
39350     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39351   },
39352 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
39353   {
39354     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsub.w", 48,
39355     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39356   },
39357 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
39358   {
39359     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsub.w", 48,
39360     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39361   },
39362 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
39363   {
39364     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsub.w", 56,
39365     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39366   },
39367 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
39368   {
39369     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsub.w", 56,
39370     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39371   },
39372 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
39373   {
39374     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsub.w", 56,
39375     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39376   },
39377 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
39378   {
39379     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsub.w", 40,
39380     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39381   },
39382 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
39383   {
39384     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsub.w", 40,
39385     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39386   },
39387 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
39388   {
39389     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsub.w", 40,
39390     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39391   },
39392 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
39393   {
39394     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsub.w", 48,
39395     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39396   },
39397 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
39398   {
39399     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsub.w", 48,
39400     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39401   },
39402 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
39403   {
39404     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsub.w", 48,
39405     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39406   },
39407 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
39408   {
39409     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsub.w", 40,
39410     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39411   },
39412 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
39413   {
39414     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsub.w", 40,
39415     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39416   },
39417 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
39418   {
39419     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsub.w", 40,
39420     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39421   },
39422 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
39423   {
39424     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsub.w", 48,
39425     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39426   },
39427 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
39428   {
39429     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsub.w", 48,
39430     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39431   },
39432 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
39433   {
39434     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsub.w", 48,
39435     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39436   },
39437 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
39438   {
39439     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsub.w", 48,
39440     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39441   },
39442 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
39443   {
39444     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsub.w", 48,
39445     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39446   },
39447 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
39448   {
39449     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsub.w", 48,
39450     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39451   },
39452 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
39453   {
39454     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsub.w", 56,
39455     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39456   },
39457 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
39458   {
39459     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsub.w", 56,
39460     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39461   },
39462 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
39463   {
39464     M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsub.w", 56,
39465     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39466   },
39467 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
39468   {
39469     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 40,
39470     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39471   },
39472 /* dsub.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
39473   {
39474     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 40,
39475     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39476   },
39477 /* dsub.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
39478   {
39479     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 40,
39480     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39481   },
39482 /* dsub.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
39483   {
39484     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 40,
39485     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39486   },
39487 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
39488   {
39489     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 40,
39490     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39491   },
39492 /* dsub.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
39493   {
39494     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 40,
39495     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39496   },
39497 /* dsub.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
39498   {
39499     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 40,
39500     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39501   },
39502 /* dsub.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
39503   {
39504     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 40,
39505     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39506   },
39507 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
39508   {
39509     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 40,
39510     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39511   },
39512 /* dsub.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
39513   {
39514     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 40,
39515     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39516   },
39517 /* dsub.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
39518   {
39519     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 40,
39520     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39521   },
39522 /* dsub.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
39523   {
39524     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 40,
39525     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39526   },
39527 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
39528   {
39529     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsub.w", 48,
39530     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39531   },
39532 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
39533   {
39534     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsub.w", 48,
39535     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39536   },
39537 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
39538   {
39539     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsub.w", 48,
39540     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39541   },
39542 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
39543   {
39544     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsub.w", 48,
39545     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39546   },
39547 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
39548   {
39549     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsub.w", 56,
39550     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39551   },
39552 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
39553   {
39554     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsub.w", 56,
39555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39556   },
39557 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
39558   {
39559     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsub.w", 56,
39560     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39561   },
39562 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
39563   {
39564     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsub.w", 56,
39565     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39566   },
39567 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
39568   {
39569     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsub.w", 64,
39570     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39571   },
39572 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
39573   {
39574     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsub.w", 64,
39575     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39576   },
39577 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
39578   {
39579     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsub.w", 64,
39580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39581   },
39582 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
39583   {
39584     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsub.w", 64,
39585     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39586   },
39587 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
39588   {
39589     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsub.w", 48,
39590     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39591   },
39592 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
39593   {
39594     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsub.w", 48,
39595     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39596   },
39597 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
39598   {
39599     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsub.w", 48,
39600     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39601   },
39602 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
39603   {
39604     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsub.w", 48,
39605     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39606   },
39607 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
39608   {
39609     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsub.w", 56,
39610     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39611   },
39612 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
39613   {
39614     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsub.w", 56,
39615     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39616   },
39617 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
39618   {
39619     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsub.w", 56,
39620     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39621   },
39622 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
39623   {
39624     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsub.w", 56,
39625     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39626   },
39627 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
39628   {
39629     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsub.w", 48,
39630     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39631   },
39632 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
39633   {
39634     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsub.w", 48,
39635     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39636   },
39637 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
39638   {
39639     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsub.w", 48,
39640     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39641   },
39642 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
39643   {
39644     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsub.w", 48,
39645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39646   },
39647 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
39648   {
39649     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsub.w", 56,
39650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39651   },
39652 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
39653   {
39654     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsub.w", 56,
39655     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39656   },
39657 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
39658   {
39659     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsub.w", 56,
39660     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39661   },
39662 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
39663   {
39664     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsub.w", 56,
39665     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39666   },
39667 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
39668   {
39669     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsub.w", 56,
39670     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39671   },
39672 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
39673   {
39674     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsub.w", 56,
39675     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39676   },
39677 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
39678   {
39679     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsub.w", 56,
39680     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39681   },
39682 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
39683   {
39684     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsub.w", 56,
39685     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39686   },
39687 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
39688   {
39689     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsub.w", 64,
39690     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39691   },
39692 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
39693   {
39694     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsub.w", 64,
39695     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39696   },
39697 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
39698   {
39699     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsub.w", 64,
39700     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39701   },
39702 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
39703   {
39704     M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsub.w", 64,
39705     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39706   },
39707 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
39708   {
39709     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 48,
39710     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39711   },
39712 /* dsub.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
39713   {
39714     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 48,
39715     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39716   },
39717 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
39718   {
39719     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 48,
39720     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39721   },
39722 /* dsub.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
39723   {
39724     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 48,
39725     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39726   },
39727 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
39728   {
39729     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 48,
39730     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39731   },
39732 /* dsub.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
39733   {
39734     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 48,
39735     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39736   },
39737 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
39738   {
39739     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dsub.w", 56,
39740     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39741   },
39742 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
39743   {
39744     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dsub.w", 56,
39745     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39746   },
39747 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
39748   {
39749     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dsub.w", 64,
39750     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39751   },
39752 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
39753   {
39754     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dsub.w", 64,
39755     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39756   },
39757 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
39758   {
39759     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dsub.w", 72,
39760     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39761   },
39762 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
39763   {
39764     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dsub.w", 72,
39765     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39766   },
39767 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
39768   {
39769     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dsub.w", 56,
39770     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39771   },
39772 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
39773   {
39774     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dsub.w", 56,
39775     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39776   },
39777 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
39778   {
39779     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dsub.w", 64,
39780     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39781   },
39782 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
39783   {
39784     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dsub.w", 64,
39785     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39786   },
39787 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
39788   {
39789     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dsub.w", 56,
39790     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39791   },
39792 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
39793   {
39794     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dsub.w", 56,
39795     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39796   },
39797 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
39798   {
39799     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dsub.w", 64,
39800     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39801   },
39802 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
39803   {
39804     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dsub.w", 64,
39805     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39806   },
39807 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
39808   {
39809     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dsub.w", 64,
39810     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39811   },
39812 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
39813   {
39814     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dsub.w", 64,
39815     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39816   },
39817 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
39818   {
39819     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dsub.w", 72,
39820     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39821   },
39822 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
39823   {
39824     M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dsub.w", 72,
39825     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39826   },
39827 /* dsub.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
39828   {
39829     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 24,
39830     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39831   },
39832 /* dsub.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
39833   {
39834     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 24,
39835     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39836   },
39837 /* dsub.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
39838   {
39839     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 24,
39840     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39841   },
39842 /* dsub.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
39843   {
39844     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 24,
39845     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39846   },
39847 /* dsub.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
39848   {
39849     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 24,
39850     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39851   },
39852 /* dsub.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
39853   {
39854     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 24,
39855     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39856   },
39857 /* dsub.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
39858   {
39859     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 24,
39860     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39861   },
39862 /* dsub.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
39863   {
39864     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 24,
39865     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39866   },
39867 /* dsub.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
39868   {
39869     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 24,
39870     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39871   },
39872 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
39873   {
39874     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsub.w", 32,
39875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39876   },
39877 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
39878   {
39879     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsub.w", 32,
39880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39881   },
39882 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
39883   {
39884     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsub.w", 32,
39885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39886   },
39887 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
39888   {
39889     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsub.w", 40,
39890     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39891   },
39892 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
39893   {
39894     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsub.w", 40,
39895     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39896   },
39897 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
39898   {
39899     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsub.w", 40,
39900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39901   },
39902 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
39903   {
39904     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsub.w", 48,
39905     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39906   },
39907 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
39908   {
39909     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsub.w", 48,
39910     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39911   },
39912 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
39913   {
39914     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsub.w", 48,
39915     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39916   },
39917 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
39918   {
39919     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsub.w", 32,
39920     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39921   },
39922 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
39923   {
39924     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsub.w", 32,
39925     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39926   },
39927 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
39928   {
39929     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsub.w", 32,
39930     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39931   },
39932 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
39933   {
39934     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsub.w", 40,
39935     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39936   },
39937 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
39938   {
39939     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsub.w", 40,
39940     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39941   },
39942 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
39943   {
39944     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsub.w", 40,
39945     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39946   },
39947 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
39948   {
39949     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsub.w", 32,
39950     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39951   },
39952 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
39953   {
39954     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsub.w", 32,
39955     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39956   },
39957 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
39958   {
39959     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsub.w", 32,
39960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39961   },
39962 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
39963   {
39964     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsub.w", 40,
39965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39966   },
39967 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
39968   {
39969     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsub.w", 40,
39970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39971   },
39972 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
39973   {
39974     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsub.w", 40,
39975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39976   },
39977 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
39978   {
39979     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsub.w", 40,
39980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39981   },
39982 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
39983   {
39984     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsub.w", 40,
39985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39986   },
39987 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
39988   {
39989     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsub.w", 40,
39990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39991   },
39992 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
39993   {
39994     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsub.w", 48,
39995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39996   },
39997 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
39998   {
39999     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsub.w", 48,
40000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40001   },
40002 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
40003   {
40004     M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsub.w", 48,
40005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40006   },
40007 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
40008   {
40009     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 32,
40010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40011   },
40012 /* dsub.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
40013   {
40014     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 32,
40015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40016   },
40017 /* dsub.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
40018   {
40019     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 32,
40020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40021   },
40022 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
40023   {
40024     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 32,
40025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40026   },
40027 /* dsub.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
40028   {
40029     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 32,
40030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40031   },
40032 /* dsub.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
40033   {
40034     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 32,
40035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40036   },
40037 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
40038   {
40039     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 32,
40040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40041   },
40042 /* dsub.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
40043   {
40044     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 32,
40045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40046   },
40047 /* dsub.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
40048   {
40049     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 32,
40050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40051   },
40052 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
40053   {
40054     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsub.b", 40,
40055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40056   },
40057 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
40058   {
40059     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsub.b", 40,
40060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40061   },
40062 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
40063   {
40064     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsub.b", 40,
40065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40066   },
40067 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
40068   {
40069     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsub.b", 48,
40070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40071   },
40072 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
40073   {
40074     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsub.b", 48,
40075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40076   },
40077 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
40078   {
40079     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsub.b", 48,
40080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40081   },
40082 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
40083   {
40084     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsub.b", 56,
40085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40086   },
40087 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
40088   {
40089     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsub.b", 56,
40090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40091   },
40092 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
40093   {
40094     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsub.b", 56,
40095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40096   },
40097 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
40098   {
40099     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsub.b", 40,
40100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40101   },
40102 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
40103   {
40104     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsub.b", 40,
40105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40106   },
40107 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
40108   {
40109     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsub.b", 40,
40110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40111   },
40112 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
40113   {
40114     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsub.b", 48,
40115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40116   },
40117 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
40118   {
40119     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsub.b", 48,
40120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40121   },
40122 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
40123   {
40124     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsub.b", 48,
40125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40126   },
40127 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
40128   {
40129     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsub.b", 40,
40130     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40131   },
40132 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
40133   {
40134     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsub.b", 40,
40135     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40136   },
40137 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
40138   {
40139     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsub.b", 40,
40140     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40141   },
40142 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
40143   {
40144     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsub.b", 48,
40145     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40146   },
40147 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
40148   {
40149     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsub.b", 48,
40150     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40151   },
40152 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
40153   {
40154     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsub.b", 48,
40155     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40156   },
40157 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
40158   {
40159     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsub.b", 48,
40160     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40161   },
40162 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
40163   {
40164     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsub.b", 48,
40165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40166   },
40167 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
40168   {
40169     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsub.b", 48,
40170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40171   },
40172 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
40173   {
40174     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsub.b", 56,
40175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40176   },
40177 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
40178   {
40179     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsub.b", 56,
40180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40181   },
40182 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
40183   {
40184     M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsub.b", 56,
40185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40186   },
40187 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
40188   {
40189     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 40,
40190     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40191   },
40192 /* dsub.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
40193   {
40194     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 40,
40195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40196   },
40197 /* dsub.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
40198   {
40199     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 40,
40200     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40201   },
40202 /* dsub.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
40203   {
40204     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 40,
40205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40206   },
40207 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
40208   {
40209     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 40,
40210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40211   },
40212 /* dsub.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
40213   {
40214     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 40,
40215     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40216   },
40217 /* dsub.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
40218   {
40219     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 40,
40220     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40221   },
40222 /* dsub.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
40223   {
40224     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 40,
40225     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40226   },
40227 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
40228   {
40229     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 40,
40230     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40231   },
40232 /* dsub.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
40233   {
40234     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 40,
40235     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40236   },
40237 /* dsub.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
40238   {
40239     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 40,
40240     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40241   },
40242 /* dsub.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
40243   {
40244     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 40,
40245     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40246   },
40247 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
40248   {
40249     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsub.b", 48,
40250     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40251   },
40252 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
40253   {
40254     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsub.b", 48,
40255     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40256   },
40257 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
40258   {
40259     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsub.b", 48,
40260     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40261   },
40262 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
40263   {
40264     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsub.b", 48,
40265     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40266   },
40267 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
40268   {
40269     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsub.b", 56,
40270     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40271   },
40272 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
40273   {
40274     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsub.b", 56,
40275     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40276   },
40277 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
40278   {
40279     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsub.b", 56,
40280     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40281   },
40282 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
40283   {
40284     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsub.b", 56,
40285     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40286   },
40287 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
40288   {
40289     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsub.b", 64,
40290     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40291   },
40292 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
40293   {
40294     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsub.b", 64,
40295     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40296   },
40297 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
40298   {
40299     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsub.b", 64,
40300     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40301   },
40302 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
40303   {
40304     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsub.b", 64,
40305     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40306   },
40307 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
40308   {
40309     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsub.b", 48,
40310     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40311   },
40312 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
40313   {
40314     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsub.b", 48,
40315     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40316   },
40317 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
40318   {
40319     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsub.b", 48,
40320     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40321   },
40322 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
40323   {
40324     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsub.b", 48,
40325     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40326   },
40327 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
40328   {
40329     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsub.b", 56,
40330     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40331   },
40332 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
40333   {
40334     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsub.b", 56,
40335     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40336   },
40337 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
40338   {
40339     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsub.b", 56,
40340     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40341   },
40342 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
40343   {
40344     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsub.b", 56,
40345     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40346   },
40347 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
40348   {
40349     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsub.b", 48,
40350     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40351   },
40352 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
40353   {
40354     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsub.b", 48,
40355     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40356   },
40357 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
40358   {
40359     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsub.b", 48,
40360     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40361   },
40362 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
40363   {
40364     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsub.b", 48,
40365     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40366   },
40367 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
40368   {
40369     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsub.b", 56,
40370     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40371   },
40372 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
40373   {
40374     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsub.b", 56,
40375     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40376   },
40377 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
40378   {
40379     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsub.b", 56,
40380     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40381   },
40382 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
40383   {
40384     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsub.b", 56,
40385     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40386   },
40387 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
40388   {
40389     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsub.b", 56,
40390     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40391   },
40392 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
40393   {
40394     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsub.b", 56,
40395     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40396   },
40397 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
40398   {
40399     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsub.b", 56,
40400     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40401   },
40402 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
40403   {
40404     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsub.b", 56,
40405     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40406   },
40407 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
40408   {
40409     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsub.b", 64,
40410     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40411   },
40412 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
40413   {
40414     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsub.b", 64,
40415     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40416   },
40417 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
40418   {
40419     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsub.b", 64,
40420     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40421   },
40422 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
40423   {
40424     M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsub.b", 64,
40425     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40426   },
40427 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
40428   {
40429     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 48,
40430     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40431   },
40432 /* dsub.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
40433   {
40434     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 48,
40435     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40436   },
40437 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
40438   {
40439     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 48,
40440     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40441   },
40442 /* dsub.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
40443   {
40444     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 48,
40445     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40446   },
40447 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
40448   {
40449     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 48,
40450     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40451   },
40452 /* dsub.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
40453   {
40454     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 48,
40455     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40456   },
40457 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
40458   {
40459     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dsub.b", 56,
40460     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40461   },
40462 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
40463   {
40464     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dsub.b", 56,
40465     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40466   },
40467 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
40468   {
40469     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dsub.b", 64,
40470     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40471   },
40472 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
40473   {
40474     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dsub.b", 64,
40475     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40476   },
40477 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
40478   {
40479     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dsub.b", 72,
40480     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40481   },
40482 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
40483   {
40484     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dsub.b", 72,
40485     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40486   },
40487 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
40488   {
40489     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dsub.b", 56,
40490     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40491   },
40492 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
40493   {
40494     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dsub.b", 56,
40495     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40496   },
40497 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
40498   {
40499     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dsub.b", 64,
40500     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40501   },
40502 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
40503   {
40504     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dsub.b", 64,
40505     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40506   },
40507 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
40508   {
40509     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dsub.b", 56,
40510     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40511   },
40512 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
40513   {
40514     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dsub.b", 56,
40515     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40516   },
40517 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
40518   {
40519     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dsub.b", 64,
40520     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40521   },
40522 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
40523   {
40524     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dsub.b", 64,
40525     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40526   },
40527 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
40528   {
40529     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dsub.b", 64,
40530     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40531   },
40532 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
40533   {
40534     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dsub.b", 64,
40535     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40536   },
40537 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
40538   {
40539     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dsub.b", 72,
40540     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40541   },
40542 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
40543   {
40544     M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dsub.b", 72,
40545     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40546   },
40547 /* dsub.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
40548   {
40549     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 24,
40550     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40551   },
40552 /* dsub.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
40553   {
40554     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 24,
40555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40556   },
40557 /* dsub.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
40558   {
40559     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 24,
40560     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40561   },
40562 /* dsub.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
40563   {
40564     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 24,
40565     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40566   },
40567 /* dsub.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
40568   {
40569     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 24,
40570     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40571   },
40572 /* dsub.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
40573   {
40574     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 24,
40575     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40576   },
40577 /* dsub.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
40578   {
40579     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 24,
40580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40581   },
40582 /* dsub.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
40583   {
40584     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 24,
40585     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40586   },
40587 /* dsub.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
40588   {
40589     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 24,
40590     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40591   },
40592 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
40593   {
40594     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsub.b", 32,
40595     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40596   },
40597 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
40598   {
40599     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsub.b", 32,
40600     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40601   },
40602 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
40603   {
40604     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsub.b", 32,
40605     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40606   },
40607 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
40608   {
40609     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsub.b", 40,
40610     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40611   },
40612 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
40613   {
40614     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsub.b", 40,
40615     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40616   },
40617 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
40618   {
40619     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsub.b", 40,
40620     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40621   },
40622 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
40623   {
40624     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsub.b", 48,
40625     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40626   },
40627 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
40628   {
40629     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsub.b", 48,
40630     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40631   },
40632 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
40633   {
40634     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsub.b", 48,
40635     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40636   },
40637 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
40638   {
40639     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsub.b", 32,
40640     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40641   },
40642 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
40643   {
40644     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsub.b", 32,
40645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40646   },
40647 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
40648   {
40649     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsub.b", 32,
40650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40651   },
40652 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
40653   {
40654     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsub.b", 40,
40655     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40656   },
40657 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
40658   {
40659     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsub.b", 40,
40660     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40661   },
40662 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
40663   {
40664     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsub.b", 40,
40665     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40666   },
40667 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
40668   {
40669     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsub.b", 32,
40670     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40671   },
40672 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
40673   {
40674     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsub.b", 32,
40675     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40676   },
40677 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
40678   {
40679     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsub.b", 32,
40680     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40681   },
40682 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
40683   {
40684     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsub.b", 40,
40685     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40686   },
40687 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
40688   {
40689     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsub.b", 40,
40690     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40691   },
40692 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
40693   {
40694     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsub.b", 40,
40695     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40696   },
40697 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
40698   {
40699     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsub.b", 40,
40700     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40701   },
40702 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
40703   {
40704     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsub.b", 40,
40705     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40706   },
40707 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
40708   {
40709     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsub.b", 40,
40710     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40711   },
40712 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
40713   {
40714     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsub.b", 48,
40715     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40716   },
40717 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
40718   {
40719     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsub.b", 48,
40720     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40721   },
40722 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
40723   {
40724     M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsub.b", 48,
40725     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40726   },
40727 /* dsub.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
40728   {
40729     M32C_INSN_DSUB32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "dsub.w", 40,
40730     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40731   },
40732 /* dsub.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
40733   {
40734     M32C_INSN_DSUB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "dsub.w", 40,
40735     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40736   },
40737 /* dsub.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
40738   {
40739     M32C_INSN_DSUB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "dsub.w", 40,
40740     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40741   },
40742 /* dsub.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
40743   {
40744     M32C_INSN_DSUB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "dsub.w", 48,
40745     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40746   },
40747 /* dsub.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
40748   {
40749     M32C_INSN_DSUB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "dsub.w", 48,
40750     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40751   },
40752 /* dsub.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
40753   {
40754     M32C_INSN_DSUB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "dsub.w", 48,
40755     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40756   },
40757 /* dsub.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
40758   {
40759     M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "dsub.w", 56,
40760     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40761   },
40762 /* dsub.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
40763   {
40764     M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "dsub.w", 56,
40765     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40766   },
40767 /* dsub.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
40768   {
40769     M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "dsub.w", 56,
40770     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40771   },
40772 /* dsub.w${X} #${Imm-40-HI},${Dsp-24-u16} */
40773   {
40774     M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "dsub.w", 56,
40775     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40776   },
40777 /* dsub.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
40778   {
40779     M32C_INSN_DSUB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "dsub.w", 64,
40780     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40781   },
40782 /* dsub.w${X} #${Imm-48-HI},${Dsp-24-u24} */
40783   {
40784     M32C_INSN_DSUB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "dsub.w", 64,
40785     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40786   },
40787 /* dsub.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
40788   {
40789     M32C_INSN_DSUB32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "dsub.b", 32,
40790     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40791   },
40792 /* dsub.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
40793   {
40794     M32C_INSN_DSUB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "dsub.b", 32,
40795     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40796   },
40797 /* dsub.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
40798   {
40799     M32C_INSN_DSUB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "dsub.b", 32,
40800     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40801   },
40802 /* dsub.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
40803   {
40804     M32C_INSN_DSUB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "dsub.b", 40,
40805     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40806   },
40807 /* dsub.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
40808   {
40809     M32C_INSN_DSUB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "dsub.b", 40,
40810     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40811   },
40812 /* dsub.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
40813   {
40814     M32C_INSN_DSUB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "dsub.b", 40,
40815     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40816   },
40817 /* dsub.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
40818   {
40819     M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "dsub.b", 48,
40820     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40821   },
40822 /* dsub.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
40823   {
40824     M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "dsub.b", 48,
40825     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40826   },
40827 /* dsub.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
40828   {
40829     M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "dsub.b", 48,
40830     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40831   },
40832 /* dsub.b${X} #${Imm-40-QI},${Dsp-24-u16} */
40833   {
40834     M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "dsub.b", 48,
40835     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40836   },
40837 /* dsub.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
40838   {
40839     M32C_INSN_DSUB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "dsub.b", 56,
40840     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40841   },
40842 /* dsub.b${X} #${Imm-48-QI},${Dsp-24-u24} */
40843   {
40844     M32C_INSN_DSUB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "dsub.b", 56,
40845     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40846   },
40847 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
40848   {
40849     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 32,
40850     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40851   },
40852 /* dsbb.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
40853   {
40854     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 32,
40855     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40856   },
40857 /* dsbb.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
40858   {
40859     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 32,
40860     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40861   },
40862 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
40863   {
40864     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 32,
40865     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40866   },
40867 /* dsbb.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
40868   {
40869     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 32,
40870     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40871   },
40872 /* dsbb.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
40873   {
40874     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 32,
40875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40876   },
40877 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
40878   {
40879     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 32,
40880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40881   },
40882 /* dsbb.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
40883   {
40884     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 32,
40885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40886   },
40887 /* dsbb.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
40888   {
40889     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 32,
40890     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40891   },
40892 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
40893   {
40894     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsbb.w", 40,
40895     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40896   },
40897 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
40898   {
40899     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsbb.w", 40,
40900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40901   },
40902 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
40903   {
40904     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsbb.w", 40,
40905     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40906   },
40907 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
40908   {
40909     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsbb.w", 48,
40910     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40911   },
40912 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
40913   {
40914     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsbb.w", 48,
40915     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40916   },
40917 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
40918   {
40919     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsbb.w", 48,
40920     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40921   },
40922 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
40923   {
40924     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsbb.w", 56,
40925     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40926   },
40927 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
40928   {
40929     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsbb.w", 56,
40930     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40931   },
40932 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
40933   {
40934     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsbb.w", 56,
40935     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40936   },
40937 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
40938   {
40939     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsbb.w", 40,
40940     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40941   },
40942 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
40943   {
40944     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsbb.w", 40,
40945     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40946   },
40947 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
40948   {
40949     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsbb.w", 40,
40950     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40951   },
40952 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
40953   {
40954     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsbb.w", 48,
40955     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40956   },
40957 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
40958   {
40959     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsbb.w", 48,
40960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40961   },
40962 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
40963   {
40964     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsbb.w", 48,
40965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40966   },
40967 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
40968   {
40969     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsbb.w", 40,
40970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40971   },
40972 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
40973   {
40974     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsbb.w", 40,
40975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40976   },
40977 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
40978   {
40979     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsbb.w", 40,
40980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40981   },
40982 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
40983   {
40984     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsbb.w", 48,
40985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40986   },
40987 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
40988   {
40989     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsbb.w", 48,
40990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40991   },
40992 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
40993   {
40994     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsbb.w", 48,
40995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40996   },
40997 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
40998   {
40999     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsbb.w", 48,
41000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41001   },
41002 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
41003   {
41004     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsbb.w", 48,
41005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41006   },
41007 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
41008   {
41009     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsbb.w", 48,
41010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41011   },
41012 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
41013   {
41014     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsbb.w", 56,
41015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41016   },
41017 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
41018   {
41019     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsbb.w", 56,
41020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41021   },
41022 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
41023   {
41024     M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsbb.w", 56,
41025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41026   },
41027 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
41028   {
41029     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 40,
41030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41031   },
41032 /* dsbb.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
41033   {
41034     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 40,
41035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41036   },
41037 /* dsbb.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
41038   {
41039     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 40,
41040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41041   },
41042 /* dsbb.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
41043   {
41044     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 40,
41045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41046   },
41047 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
41048   {
41049     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 40,
41050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41051   },
41052 /* dsbb.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
41053   {
41054     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 40,
41055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41056   },
41057 /* dsbb.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
41058   {
41059     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 40,
41060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41061   },
41062 /* dsbb.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
41063   {
41064     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 40,
41065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41066   },
41067 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
41068   {
41069     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 40,
41070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41071   },
41072 /* dsbb.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
41073   {
41074     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 40,
41075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41076   },
41077 /* dsbb.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
41078   {
41079     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 40,
41080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41081   },
41082 /* dsbb.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
41083   {
41084     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 40,
41085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41086   },
41087 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
41088   {
41089     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsbb.w", 48,
41090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41091   },
41092 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
41093   {
41094     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsbb.w", 48,
41095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41096   },
41097 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
41098   {
41099     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsbb.w", 48,
41100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41101   },
41102 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
41103   {
41104     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsbb.w", 48,
41105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41106   },
41107 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
41108   {
41109     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsbb.w", 56,
41110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41111   },
41112 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
41113   {
41114     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsbb.w", 56,
41115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41116   },
41117 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
41118   {
41119     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsbb.w", 56,
41120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41121   },
41122 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
41123   {
41124     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsbb.w", 56,
41125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41126   },
41127 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
41128   {
41129     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsbb.w", 64,
41130     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41131   },
41132 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
41133   {
41134     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsbb.w", 64,
41135     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41136   },
41137 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
41138   {
41139     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsbb.w", 64,
41140     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41141   },
41142 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
41143   {
41144     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsbb.w", 64,
41145     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41146   },
41147 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
41148   {
41149     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsbb.w", 48,
41150     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41151   },
41152 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
41153   {
41154     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsbb.w", 48,
41155     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41156   },
41157 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
41158   {
41159     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsbb.w", 48,
41160     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41161   },
41162 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
41163   {
41164     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsbb.w", 48,
41165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41166   },
41167 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
41168   {
41169     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsbb.w", 56,
41170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41171   },
41172 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
41173   {
41174     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsbb.w", 56,
41175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41176   },
41177 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
41178   {
41179     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsbb.w", 56,
41180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41181   },
41182 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
41183   {
41184     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsbb.w", 56,
41185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41186   },
41187 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
41188   {
41189     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsbb.w", 48,
41190     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41191   },
41192 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
41193   {
41194     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsbb.w", 48,
41195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41196   },
41197 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
41198   {
41199     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsbb.w", 48,
41200     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41201   },
41202 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
41203   {
41204     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsbb.w", 48,
41205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41206   },
41207 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
41208   {
41209     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsbb.w", 56,
41210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41211   },
41212 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
41213   {
41214     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsbb.w", 56,
41215     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41216   },
41217 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
41218   {
41219     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsbb.w", 56,
41220     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41221   },
41222 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
41223   {
41224     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsbb.w", 56,
41225     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41226   },
41227 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
41228   {
41229     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsbb.w", 56,
41230     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41231   },
41232 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
41233   {
41234     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsbb.w", 56,
41235     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41236   },
41237 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
41238   {
41239     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsbb.w", 56,
41240     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41241   },
41242 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
41243   {
41244     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsbb.w", 56,
41245     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41246   },
41247 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
41248   {
41249     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsbb.w", 64,
41250     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41251   },
41252 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
41253   {
41254     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsbb.w", 64,
41255     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41256   },
41257 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
41258   {
41259     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsbb.w", 64,
41260     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41261   },
41262 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
41263   {
41264     M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsbb.w", 64,
41265     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41266   },
41267 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
41268   {
41269     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 48,
41270     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41271   },
41272 /* dsbb.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
41273   {
41274     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 48,
41275     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41276   },
41277 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
41278   {
41279     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 48,
41280     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41281   },
41282 /* dsbb.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
41283   {
41284     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 48,
41285     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41286   },
41287 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
41288   {
41289     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 48,
41290     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41291   },
41292 /* dsbb.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
41293   {
41294     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 48,
41295     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41296   },
41297 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
41298   {
41299     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dsbb.w", 56,
41300     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41301   },
41302 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
41303   {
41304     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dsbb.w", 56,
41305     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41306   },
41307 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
41308   {
41309     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dsbb.w", 64,
41310     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41311   },
41312 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
41313   {
41314     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dsbb.w", 64,
41315     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41316   },
41317 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
41318   {
41319     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dsbb.w", 72,
41320     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41321   },
41322 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
41323   {
41324     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dsbb.w", 72,
41325     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41326   },
41327 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
41328   {
41329     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dsbb.w", 56,
41330     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41331   },
41332 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
41333   {
41334     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dsbb.w", 56,
41335     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41336   },
41337 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
41338   {
41339     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dsbb.w", 64,
41340     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41341   },
41342 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
41343   {
41344     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dsbb.w", 64,
41345     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41346   },
41347 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
41348   {
41349     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dsbb.w", 56,
41350     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41351   },
41352 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
41353   {
41354     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dsbb.w", 56,
41355     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41356   },
41357 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
41358   {
41359     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dsbb.w", 64,
41360     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41361   },
41362 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
41363   {
41364     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dsbb.w", 64,
41365     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41366   },
41367 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
41368   {
41369     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dsbb.w", 64,
41370     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41371   },
41372 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
41373   {
41374     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dsbb.w", 64,
41375     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41376   },
41377 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
41378   {
41379     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dsbb.w", 72,
41380     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41381   },
41382 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
41383   {
41384     M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dsbb.w", 72,
41385     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41386   },
41387 /* dsbb.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
41388   {
41389     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 24,
41390     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41391   },
41392 /* dsbb.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
41393   {
41394     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 24,
41395     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41396   },
41397 /* dsbb.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
41398   {
41399     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 24,
41400     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41401   },
41402 /* dsbb.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
41403   {
41404     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 24,
41405     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41406   },
41407 /* dsbb.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
41408   {
41409     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 24,
41410     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41411   },
41412 /* dsbb.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
41413   {
41414     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 24,
41415     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41416   },
41417 /* dsbb.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
41418   {
41419     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 24,
41420     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41421   },
41422 /* dsbb.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
41423   {
41424     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 24,
41425     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41426   },
41427 /* dsbb.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
41428   {
41429     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 24,
41430     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41431   },
41432 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
41433   {
41434     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsbb.w", 32,
41435     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41436   },
41437 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
41438   {
41439     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsbb.w", 32,
41440     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41441   },
41442 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
41443   {
41444     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsbb.w", 32,
41445     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41446   },
41447 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
41448   {
41449     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsbb.w", 40,
41450     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41451   },
41452 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
41453   {
41454     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsbb.w", 40,
41455     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41456   },
41457 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
41458   {
41459     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsbb.w", 40,
41460     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41461   },
41462 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
41463   {
41464     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsbb.w", 48,
41465     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41466   },
41467 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
41468   {
41469     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsbb.w", 48,
41470     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41471   },
41472 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
41473   {
41474     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsbb.w", 48,
41475     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41476   },
41477 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
41478   {
41479     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsbb.w", 32,
41480     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41481   },
41482 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
41483   {
41484     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsbb.w", 32,
41485     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41486   },
41487 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
41488   {
41489     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsbb.w", 32,
41490     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41491   },
41492 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
41493   {
41494     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsbb.w", 40,
41495     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41496   },
41497 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
41498   {
41499     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsbb.w", 40,
41500     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41501   },
41502 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
41503   {
41504     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsbb.w", 40,
41505     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41506   },
41507 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
41508   {
41509     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsbb.w", 32,
41510     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41511   },
41512 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
41513   {
41514     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsbb.w", 32,
41515     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41516   },
41517 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
41518   {
41519     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsbb.w", 32,
41520     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41521   },
41522 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
41523   {
41524     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsbb.w", 40,
41525     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41526   },
41527 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
41528   {
41529     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsbb.w", 40,
41530     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41531   },
41532 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
41533   {
41534     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsbb.w", 40,
41535     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41536   },
41537 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
41538   {
41539     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsbb.w", 40,
41540     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41541   },
41542 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
41543   {
41544     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsbb.w", 40,
41545     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41546   },
41547 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
41548   {
41549     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsbb.w", 40,
41550     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41551   },
41552 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
41553   {
41554     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsbb.w", 48,
41555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41556   },
41557 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
41558   {
41559     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsbb.w", 48,
41560     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41561   },
41562 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
41563   {
41564     M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsbb.w", 48,
41565     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41566   },
41567 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
41568   {
41569     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 32,
41570     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41571   },
41572 /* dsbb.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
41573   {
41574     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 32,
41575     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41576   },
41577 /* dsbb.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
41578   {
41579     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 32,
41580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41581   },
41582 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
41583   {
41584     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 32,
41585     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41586   },
41587 /* dsbb.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
41588   {
41589     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 32,
41590     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41591   },
41592 /* dsbb.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
41593   {
41594     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 32,
41595     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41596   },
41597 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
41598   {
41599     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 32,
41600     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41601   },
41602 /* dsbb.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
41603   {
41604     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 32,
41605     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41606   },
41607 /* dsbb.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
41608   {
41609     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 32,
41610     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41611   },
41612 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
41613   {
41614     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsbb.b", 40,
41615     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41616   },
41617 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
41618   {
41619     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsbb.b", 40,
41620     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41621   },
41622 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
41623   {
41624     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsbb.b", 40,
41625     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41626   },
41627 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
41628   {
41629     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsbb.b", 48,
41630     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41631   },
41632 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
41633   {
41634     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsbb.b", 48,
41635     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41636   },
41637 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
41638   {
41639     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsbb.b", 48,
41640     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41641   },
41642 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
41643   {
41644     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsbb.b", 56,
41645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41646   },
41647 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
41648   {
41649     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsbb.b", 56,
41650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41651   },
41652 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
41653   {
41654     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsbb.b", 56,
41655     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41656   },
41657 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
41658   {
41659     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsbb.b", 40,
41660     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41661   },
41662 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
41663   {
41664     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsbb.b", 40,
41665     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41666   },
41667 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
41668   {
41669     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsbb.b", 40,
41670     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41671   },
41672 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
41673   {
41674     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsbb.b", 48,
41675     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41676   },
41677 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
41678   {
41679     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsbb.b", 48,
41680     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41681   },
41682 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
41683   {
41684     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsbb.b", 48,
41685     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41686   },
41687 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
41688   {
41689     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsbb.b", 40,
41690     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41691   },
41692 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
41693   {
41694     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsbb.b", 40,
41695     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41696   },
41697 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
41698   {
41699     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsbb.b", 40,
41700     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41701   },
41702 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
41703   {
41704     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsbb.b", 48,
41705     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41706   },
41707 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
41708   {
41709     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsbb.b", 48,
41710     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41711   },
41712 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
41713   {
41714     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsbb.b", 48,
41715     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41716   },
41717 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
41718   {
41719     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsbb.b", 48,
41720     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41721   },
41722 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
41723   {
41724     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsbb.b", 48,
41725     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41726   },
41727 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
41728   {
41729     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsbb.b", 48,
41730     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41731   },
41732 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
41733   {
41734     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsbb.b", 56,
41735     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41736   },
41737 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
41738   {
41739     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsbb.b", 56,
41740     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41741   },
41742 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
41743   {
41744     M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsbb.b", 56,
41745     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41746   },
41747 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
41748   {
41749     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 40,
41750     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41751   },
41752 /* dsbb.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
41753   {
41754     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 40,
41755     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41756   },
41757 /* dsbb.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
41758   {
41759     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 40,
41760     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41761   },
41762 /* dsbb.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
41763   {
41764     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 40,
41765     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41766   },
41767 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
41768   {
41769     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 40,
41770     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41771   },
41772 /* dsbb.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
41773   {
41774     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 40,
41775     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41776   },
41777 /* dsbb.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
41778   {
41779     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 40,
41780     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41781   },
41782 /* dsbb.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
41783   {
41784     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 40,
41785     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41786   },
41787 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
41788   {
41789     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 40,
41790     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41791   },
41792 /* dsbb.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
41793   {
41794     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 40,
41795     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41796   },
41797 /* dsbb.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
41798   {
41799     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 40,
41800     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41801   },
41802 /* dsbb.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
41803   {
41804     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 40,
41805     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41806   },
41807 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
41808   {
41809     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsbb.b", 48,
41810     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41811   },
41812 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
41813   {
41814     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsbb.b", 48,
41815     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41816   },
41817 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
41818   {
41819     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsbb.b", 48,
41820     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41821   },
41822 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
41823   {
41824     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsbb.b", 48,
41825     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41826   },
41827 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
41828   {
41829     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsbb.b", 56,
41830     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41831   },
41832 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
41833   {
41834     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsbb.b", 56,
41835     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41836   },
41837 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
41838   {
41839     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsbb.b", 56,
41840     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41841   },
41842 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
41843   {
41844     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsbb.b", 56,
41845     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41846   },
41847 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
41848   {
41849     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsbb.b", 64,
41850     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41851   },
41852 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
41853   {
41854     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsbb.b", 64,
41855     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41856   },
41857 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
41858   {
41859     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsbb.b", 64,
41860     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41861   },
41862 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
41863   {
41864     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsbb.b", 64,
41865     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41866   },
41867 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
41868   {
41869     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsbb.b", 48,
41870     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41871   },
41872 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
41873   {
41874     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsbb.b", 48,
41875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41876   },
41877 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
41878   {
41879     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsbb.b", 48,
41880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41881   },
41882 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
41883   {
41884     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsbb.b", 48,
41885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41886   },
41887 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
41888   {
41889     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsbb.b", 56,
41890     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41891   },
41892 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
41893   {
41894     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsbb.b", 56,
41895     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41896   },
41897 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
41898   {
41899     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsbb.b", 56,
41900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41901   },
41902 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
41903   {
41904     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsbb.b", 56,
41905     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41906   },
41907 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
41908   {
41909     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsbb.b", 48,
41910     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41911   },
41912 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
41913   {
41914     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsbb.b", 48,
41915     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41916   },
41917 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
41918   {
41919     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsbb.b", 48,
41920     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41921   },
41922 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
41923   {
41924     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsbb.b", 48,
41925     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41926   },
41927 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
41928   {
41929     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsbb.b", 56,
41930     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41931   },
41932 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
41933   {
41934     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsbb.b", 56,
41935     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41936   },
41937 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
41938   {
41939     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsbb.b", 56,
41940     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41941   },
41942 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
41943   {
41944     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsbb.b", 56,
41945     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41946   },
41947 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
41948   {
41949     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsbb.b", 56,
41950     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41951   },
41952 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
41953   {
41954     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsbb.b", 56,
41955     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41956   },
41957 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
41958   {
41959     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsbb.b", 56,
41960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41961   },
41962 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
41963   {
41964     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsbb.b", 56,
41965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41966   },
41967 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
41968   {
41969     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsbb.b", 64,
41970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41971   },
41972 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
41973   {
41974     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsbb.b", 64,
41975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41976   },
41977 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
41978   {
41979     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsbb.b", 64,
41980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41981   },
41982 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
41983   {
41984     M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsbb.b", 64,
41985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41986   },
41987 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
41988   {
41989     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 48,
41990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41991   },
41992 /* dsbb.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
41993   {
41994     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 48,
41995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41996   },
41997 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
41998   {
41999     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 48,
42000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42001   },
42002 /* dsbb.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
42003   {
42004     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 48,
42005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42006   },
42007 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
42008   {
42009     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 48,
42010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42011   },
42012 /* dsbb.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
42013   {
42014     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 48,
42015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42016   },
42017 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
42018   {
42019     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dsbb.b", 56,
42020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42021   },
42022 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
42023   {
42024     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dsbb.b", 56,
42025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42026   },
42027 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
42028   {
42029     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dsbb.b", 64,
42030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42031   },
42032 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
42033   {
42034     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dsbb.b", 64,
42035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42036   },
42037 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
42038   {
42039     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dsbb.b", 72,
42040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42041   },
42042 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
42043   {
42044     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dsbb.b", 72,
42045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42046   },
42047 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
42048   {
42049     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dsbb.b", 56,
42050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42051   },
42052 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
42053   {
42054     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dsbb.b", 56,
42055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42056   },
42057 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
42058   {
42059     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dsbb.b", 64,
42060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42061   },
42062 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
42063   {
42064     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dsbb.b", 64,
42065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42066   },
42067 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
42068   {
42069     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dsbb.b", 56,
42070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42071   },
42072 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
42073   {
42074     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dsbb.b", 56,
42075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42076   },
42077 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
42078   {
42079     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dsbb.b", 64,
42080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42081   },
42082 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
42083   {
42084     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dsbb.b", 64,
42085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42086   },
42087 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
42088   {
42089     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dsbb.b", 64,
42090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42091   },
42092 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
42093   {
42094     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dsbb.b", 64,
42095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42096   },
42097 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
42098   {
42099     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dsbb.b", 72,
42100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42101   },
42102 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
42103   {
42104     M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dsbb.b", 72,
42105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42106   },
42107 /* dsbb.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
42108   {
42109     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 24,
42110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42111   },
42112 /* dsbb.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
42113   {
42114     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 24,
42115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42116   },
42117 /* dsbb.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
42118   {
42119     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 24,
42120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42121   },
42122 /* dsbb.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
42123   {
42124     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 24,
42125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42126   },
42127 /* dsbb.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
42128   {
42129     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 24,
42130     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42131   },
42132 /* dsbb.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
42133   {
42134     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 24,
42135     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42136   },
42137 /* dsbb.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
42138   {
42139     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 24,
42140     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42141   },
42142 /* dsbb.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
42143   {
42144     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 24,
42145     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42146   },
42147 /* dsbb.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
42148   {
42149     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 24,
42150     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42151   },
42152 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
42153   {
42154     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsbb.b", 32,
42155     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42156   },
42157 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
42158   {
42159     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsbb.b", 32,
42160     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42161   },
42162 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
42163   {
42164     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsbb.b", 32,
42165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42166   },
42167 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
42168   {
42169     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsbb.b", 40,
42170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42171   },
42172 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
42173   {
42174     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsbb.b", 40,
42175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42176   },
42177 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
42178   {
42179     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsbb.b", 40,
42180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42181   },
42182 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
42183   {
42184     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsbb.b", 48,
42185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42186   },
42187 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
42188   {
42189     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsbb.b", 48,
42190     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42191   },
42192 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
42193   {
42194     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsbb.b", 48,
42195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42196   },
42197 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
42198   {
42199     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsbb.b", 32,
42200     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42201   },
42202 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
42203   {
42204     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsbb.b", 32,
42205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42206   },
42207 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
42208   {
42209     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsbb.b", 32,
42210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42211   },
42212 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
42213   {
42214     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsbb.b", 40,
42215     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42216   },
42217 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
42218   {
42219     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsbb.b", 40,
42220     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42221   },
42222 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
42223   {
42224     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsbb.b", 40,
42225     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42226   },
42227 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
42228   {
42229     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsbb.b", 32,
42230     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42231   },
42232 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
42233   {
42234     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsbb.b", 32,
42235     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42236   },
42237 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
42238   {
42239     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsbb.b", 32,
42240     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42241   },
42242 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
42243   {
42244     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsbb.b", 40,
42245     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42246   },
42247 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
42248   {
42249     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsbb.b", 40,
42250     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42251   },
42252 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
42253   {
42254     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsbb.b", 40,
42255     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42256   },
42257 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
42258   {
42259     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsbb.b", 40,
42260     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42261   },
42262 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
42263   {
42264     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsbb.b", 40,
42265     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42266   },
42267 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
42268   {
42269     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsbb.b", 40,
42270     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42271   },
42272 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
42273   {
42274     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsbb.b", 48,
42275     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42276   },
42277 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
42278   {
42279     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsbb.b", 48,
42280     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42281   },
42282 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
42283   {
42284     M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsbb.b", 48,
42285     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42286   },
42287 /* dsbb.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
42288   {
42289     M32C_INSN_DSBB32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 40,
42290     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42291   },
42292 /* dsbb.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
42293   {
42294     M32C_INSN_DSBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "dsbb.w", 40,
42295     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42296   },
42297 /* dsbb.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
42298   {
42299     M32C_INSN_DSBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "dsbb.w", 40,
42300     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42301   },
42302 /* dsbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
42303   {
42304     M32C_INSN_DSBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "dsbb.w", 48,
42305     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42306   },
42307 /* dsbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
42308   {
42309     M32C_INSN_DSBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "dsbb.w", 48,
42310     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42311   },
42312 /* dsbb.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
42313   {
42314     M32C_INSN_DSBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "dsbb.w", 48,
42315     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42316   },
42317 /* dsbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
42318   {
42319     M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "dsbb.w", 56,
42320     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42321   },
42322 /* dsbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
42323   {
42324     M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "dsbb.w", 56,
42325     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42326   },
42327 /* dsbb.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
42328   {
42329     M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "dsbb.w", 56,
42330     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42331   },
42332 /* dsbb.w${X} #${Imm-40-HI},${Dsp-24-u16} */
42333   {
42334     M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "dsbb.w", 56,
42335     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42336   },
42337 /* dsbb.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
42338   {
42339     M32C_INSN_DSBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "dsbb.w", 64,
42340     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42341   },
42342 /* dsbb.w${X} #${Imm-48-HI},${Dsp-24-u24} */
42343   {
42344     M32C_INSN_DSBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "dsbb.w", 64,
42345     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42346   },
42347 /* dsbb.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
42348   {
42349     M32C_INSN_DSBB32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 32,
42350     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42351   },
42352 /* dsbb.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
42353   {
42354     M32C_INSN_DSBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "dsbb.b", 32,
42355     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42356   },
42357 /* dsbb.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
42358   {
42359     M32C_INSN_DSBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "dsbb.b", 32,
42360     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42361   },
42362 /* dsbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
42363   {
42364     M32C_INSN_DSBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "dsbb.b", 40,
42365     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42366   },
42367 /* dsbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
42368   {
42369     M32C_INSN_DSBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "dsbb.b", 40,
42370     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42371   },
42372 /* dsbb.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
42373   {
42374     M32C_INSN_DSBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "dsbb.b", 40,
42375     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42376   },
42377 /* dsbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
42378   {
42379     M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "dsbb.b", 48,
42380     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42381   },
42382 /* dsbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
42383   {
42384     M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "dsbb.b", 48,
42385     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42386   },
42387 /* dsbb.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
42388   {
42389     M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "dsbb.b", 48,
42390     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42391   },
42392 /* dsbb.b${X} #${Imm-40-QI},${Dsp-24-u16} */
42393   {
42394     M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "dsbb.b", 48,
42395     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42396   },
42397 /* dsbb.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
42398   {
42399     M32C_INSN_DSBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "dsbb.b", 56,
42400     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42401   },
42402 /* dsbb.b${X} #${Imm-48-QI},${Dsp-24-u24} */
42403   {
42404     M32C_INSN_DSBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "dsbb.b", 56,
42405     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42406   },
42407 /* divx.l $Dst32RnPrefixedSI */
42408   {
42409     M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_RN_DIRECT_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-Rn-direct-Prefixed-SI", "divx.l", 24,
42410     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42411   },
42412 /* divx.l $Dst32AnPrefixedSI */
42413   {
42414     M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_AN_DIRECT_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-An-direct-Prefixed-SI", "divx.l", 24,
42415     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42416   },
42417 /* divx.l [$Dst32AnPrefixed] */
42418   {
42419     M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_AN_INDIRECT_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-An-indirect-Prefixed-SI", "divx.l", 24,
42420     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42421   },
42422 /* divx.l ${Dsp-24-u8}[$Dst32AnPrefixed] */
42423   {
42424     M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_8_AN_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-8-An-relative-Prefixed-SI", "divx.l", 32,
42425     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42426   },
42427 /* divx.l ${Dsp-24-u16}[$Dst32AnPrefixed] */
42428   {
42429     M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_AN_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-16-An-relative-Prefixed-SI", "divx.l", 40,
42430     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42431   },
42432 /* divx.l ${Dsp-24-u24}[$Dst32AnPrefixed] */
42433   {
42434     M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_24_AN_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-24-An-relative-Prefixed-SI", "divx.l", 48,
42435     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42436   },
42437 /* divx.l ${Dsp-24-u8}[sb] */
42438   {
42439     M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_8_SB_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-8-SB-relative-Prefixed-SI", "divx.l", 32,
42440     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42441   },
42442 /* divx.l ${Dsp-24-u16}[sb] */
42443   {
42444     M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_SB_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-16-SB-relative-Prefixed-SI", "divx.l", 40,
42445     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42446   },
42447 /* divx.l ${Dsp-24-s8}[fb] */
42448   {
42449     M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_8_FB_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-8-FB-relative-Prefixed-SI", "divx.l", 32,
42450     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42451   },
42452 /* divx.l ${Dsp-24-s16}[fb] */
42453   {
42454     M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_FB_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-16-FB-relative-Prefixed-SI", "divx.l", 40,
42455     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42456   },
42457 /* divx.l ${Dsp-24-u16} */
42458   {
42459     M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_ABSOLUTE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-16-absolute-Prefixed-SI", "divx.l", 40,
42460     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42461   },
42462 /* divx.l ${Dsp-24-u24} */
42463   {
42464     M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_24_ABSOLUTE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-24-absolute-Prefixed-SI", "divx.l", 48,
42465     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42466   },
42467 /* divu.l $Dst32RnPrefixedSI */
42468   {
42469     M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_RN_DIRECT_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-Rn-direct-Prefixed-SI", "divu.l", 24,
42470     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42471   },
42472 /* divu.l $Dst32AnPrefixedSI */
42473   {
42474     M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_AN_DIRECT_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-An-direct-Prefixed-SI", "divu.l", 24,
42475     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42476   },
42477 /* divu.l [$Dst32AnPrefixed] */
42478   {
42479     M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_AN_INDIRECT_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-An-indirect-Prefixed-SI", "divu.l", 24,
42480     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42481   },
42482 /* divu.l ${Dsp-24-u8}[$Dst32AnPrefixed] */
42483   {
42484     M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_8_AN_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-8-An-relative-Prefixed-SI", "divu.l", 32,
42485     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42486   },
42487 /* divu.l ${Dsp-24-u16}[$Dst32AnPrefixed] */
42488   {
42489     M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_AN_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-16-An-relative-Prefixed-SI", "divu.l", 40,
42490     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42491   },
42492 /* divu.l ${Dsp-24-u24}[$Dst32AnPrefixed] */
42493   {
42494     M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_24_AN_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-24-An-relative-Prefixed-SI", "divu.l", 48,
42495     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42496   },
42497 /* divu.l ${Dsp-24-u8}[sb] */
42498   {
42499     M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_8_SB_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-8-SB-relative-Prefixed-SI", "divu.l", 32,
42500     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42501   },
42502 /* divu.l ${Dsp-24-u16}[sb] */
42503   {
42504     M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_SB_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-16-SB-relative-Prefixed-SI", "divu.l", 40,
42505     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42506   },
42507 /* divu.l ${Dsp-24-s8}[fb] */
42508   {
42509     M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_8_FB_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-8-FB-relative-Prefixed-SI", "divu.l", 32,
42510     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42511   },
42512 /* divu.l ${Dsp-24-s16}[fb] */
42513   {
42514     M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_FB_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-16-FB-relative-Prefixed-SI", "divu.l", 40,
42515     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42516   },
42517 /* divu.l ${Dsp-24-u16} */
42518   {
42519     M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_ABSOLUTE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-16-absolute-Prefixed-SI", "divu.l", 40,
42520     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42521   },
42522 /* divu.l ${Dsp-24-u24} */
42523   {
42524     M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_24_ABSOLUTE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-24-absolute-Prefixed-SI", "divu.l", 48,
42525     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42526   },
42527 /* div.l $Dst32RnPrefixedSI */
42528   {
42529     M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_RN_DIRECT_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-Rn-direct-Prefixed-SI", "div.l", 24,
42530     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42531   },
42532 /* div.l $Dst32AnPrefixedSI */
42533   {
42534     M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_AN_DIRECT_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-An-direct-Prefixed-SI", "div.l", 24,
42535     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42536   },
42537 /* div.l [$Dst32AnPrefixed] */
42538   {
42539     M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_AN_INDIRECT_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-An-indirect-Prefixed-SI", "div.l", 24,
42540     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42541   },
42542 /* div.l ${Dsp-24-u8}[$Dst32AnPrefixed] */
42543   {
42544     M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_8_AN_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-8-An-relative-Prefixed-SI", "div.l", 32,
42545     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42546   },
42547 /* div.l ${Dsp-24-u16}[$Dst32AnPrefixed] */
42548   {
42549     M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_AN_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-16-An-relative-Prefixed-SI", "div.l", 40,
42550     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42551   },
42552 /* div.l ${Dsp-24-u24}[$Dst32AnPrefixed] */
42553   {
42554     M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_24_AN_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-24-An-relative-Prefixed-SI", "div.l", 48,
42555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42556   },
42557 /* div.l ${Dsp-24-u8}[sb] */
42558   {
42559     M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_8_SB_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-8-SB-relative-Prefixed-SI", "div.l", 32,
42560     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42561   },
42562 /* div.l ${Dsp-24-u16}[sb] */
42563   {
42564     M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_SB_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-16-SB-relative-Prefixed-SI", "div.l", 40,
42565     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42566   },
42567 /* div.l ${Dsp-24-s8}[fb] */
42568   {
42569     M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_8_FB_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-8-FB-relative-Prefixed-SI", "div.l", 32,
42570     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42571   },
42572 /* div.l ${Dsp-24-s16}[fb] */
42573   {
42574     M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_FB_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-16-FB-relative-Prefixed-SI", "div.l", 40,
42575     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42576   },
42577 /* div.l ${Dsp-24-u16} */
42578   {
42579     M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_ABSOLUTE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-16-absolute-Prefixed-SI", "div.l", 40,
42580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42581   },
42582 /* div.l ${Dsp-24-u24} */
42583   {
42584     M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_24_ABSOLUTE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-24-absolute-Prefixed-SI", "div.l", 48,
42585     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42586   },
42587 /* divx.w $Dst32RnUnprefixedHI */
42588   {
42589     M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "divx.w", 16,
42590     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42591   },
42592 /* divx.w $Dst32AnUnprefixedHI */
42593   {
42594     M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "divx.w", 16,
42595     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42596   },
42597 /* divx.w [$Dst32AnUnprefixed] */
42598   {
42599     M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "divx.w", 16,
42600     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42601   },
42602 /* divx.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
42603   {
42604     M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "divx.w", 24,
42605     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42606   },
42607 /* divx.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
42608   {
42609     M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "divx.w", 32,
42610     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42611   },
42612 /* divx.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
42613   {
42614     M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "divx.w", 40,
42615     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42616   },
42617 /* divx.w ${Dsp-16-u8}[sb] */
42618   {
42619     M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "divx.w", 24,
42620     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42621   },
42622 /* divx.w ${Dsp-16-u16}[sb] */
42623   {
42624     M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "divx.w", 32,
42625     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42626   },
42627 /* divx.w ${Dsp-16-s8}[fb] */
42628   {
42629     M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "divx.w", 24,
42630     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42631   },
42632 /* divx.w ${Dsp-16-s16}[fb] */
42633   {
42634     M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "divx.w", 32,
42635     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42636   },
42637 /* divx.w ${Dsp-16-u16} */
42638   {
42639     M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "divx.w", 32,
42640     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42641   },
42642 /* divx.w ${Dsp-16-u24} */
42643   {
42644     M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "divx.w", 40,
42645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42646   },
42647 /* divx.b $Dst32RnUnprefixedQI */
42648   {
42649     M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "divx.b", 16,
42650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42651   },
42652 /* divx.b $Dst32AnUnprefixedQI */
42653   {
42654     M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "divx.b", 16,
42655     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42656   },
42657 /* divx.b [$Dst32AnUnprefixed] */
42658   {
42659     M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "divx.b", 16,
42660     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42661   },
42662 /* divx.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
42663   {
42664     M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "divx.b", 24,
42665     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42666   },
42667 /* divx.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
42668   {
42669     M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "divx.b", 32,
42670     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42671   },
42672 /* divx.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
42673   {
42674     M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "divx.b", 40,
42675     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42676   },
42677 /* divx.b ${Dsp-16-u8}[sb] */
42678   {
42679     M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "divx.b", 24,
42680     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42681   },
42682 /* divx.b ${Dsp-16-u16}[sb] */
42683   {
42684     M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "divx.b", 32,
42685     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42686   },
42687 /* divx.b ${Dsp-16-s8}[fb] */
42688   {
42689     M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "divx.b", 24,
42690     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42691   },
42692 /* divx.b ${Dsp-16-s16}[fb] */
42693   {
42694     M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "divx.b", 32,
42695     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42696   },
42697 /* divx.b ${Dsp-16-u16} */
42698   {
42699     M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "divx.b", 32,
42700     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42701   },
42702 /* divx.b ${Dsp-16-u24} */
42703   {
42704     M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "divx.b", 40,
42705     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42706   },
42707 /* divx.w $Dst16RnHI */
42708   {
42709     M32C_INSN_DIVX16_W_DST16_16_HI_DST16_RN_DIRECT_HI, "divx16.w-dst16-16-HI-dst16-Rn-direct-HI", "divx.w", 16,
42710     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42711   },
42712 /* divx.w $Dst16AnHI */
42713   {
42714     M32C_INSN_DIVX16_W_DST16_16_HI_DST16_AN_DIRECT_HI, "divx16.w-dst16-16-HI-dst16-An-direct-HI", "divx.w", 16,
42715     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42716   },
42717 /* divx.w [$Dst16An] */
42718   {
42719     M32C_INSN_DIVX16_W_DST16_16_HI_DST16_AN_INDIRECT_HI, "divx16.w-dst16-16-HI-dst16-An-indirect-HI", "divx.w", 16,
42720     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42721   },
42722 /* divx.w ${Dsp-16-u8}[$Dst16An] */
42723   {
42724     M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_8_AN_RELATIVE_HI, "divx16.w-dst16-16-HI-dst16-16-8-An-relative-HI", "divx.w", 24,
42725     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42726   },
42727 /* divx.w ${Dsp-16-u16}[$Dst16An] */
42728   {
42729     M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_16_AN_RELATIVE_HI, "divx16.w-dst16-16-HI-dst16-16-16-An-relative-HI", "divx.w", 32,
42730     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42731   },
42732 /* divx.w ${Dsp-16-u8}[sb] */
42733   {
42734     M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_8_SB_RELATIVE_HI, "divx16.w-dst16-16-HI-dst16-16-8-SB-relative-HI", "divx.w", 24,
42735     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42736   },
42737 /* divx.w ${Dsp-16-u16}[sb] */
42738   {
42739     M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_16_SB_RELATIVE_HI, "divx16.w-dst16-16-HI-dst16-16-16-SB-relative-HI", "divx.w", 32,
42740     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42741   },
42742 /* divx.w ${Dsp-16-s8}[fb] */
42743   {
42744     M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_8_FB_RELATIVE_HI, "divx16.w-dst16-16-HI-dst16-16-8-FB-relative-HI", "divx.w", 24,
42745     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42746   },
42747 /* divx.w ${Dsp-16-u16} */
42748   {
42749     M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_16_ABSOLUTE_HI, "divx16.w-dst16-16-HI-dst16-16-16-absolute-HI", "divx.w", 32,
42750     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42751   },
42752 /* divx.b $Dst16RnQI */
42753   {
42754     M32C_INSN_DIVX16_B_DST16_16_QI_DST16_RN_DIRECT_QI, "divx16.b-dst16-16-QI-dst16-Rn-direct-QI", "divx.b", 16,
42755     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42756   },
42757 /* divx.b $Dst16AnQI */
42758   {
42759     M32C_INSN_DIVX16_B_DST16_16_QI_DST16_AN_DIRECT_QI, "divx16.b-dst16-16-QI-dst16-An-direct-QI", "divx.b", 16,
42760     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42761   },
42762 /* divx.b [$Dst16An] */
42763   {
42764     M32C_INSN_DIVX16_B_DST16_16_QI_DST16_AN_INDIRECT_QI, "divx16.b-dst16-16-QI-dst16-An-indirect-QI", "divx.b", 16,
42765     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42766   },
42767 /* divx.b ${Dsp-16-u8}[$Dst16An] */
42768   {
42769     M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_8_AN_RELATIVE_QI, "divx16.b-dst16-16-QI-dst16-16-8-An-relative-QI", "divx.b", 24,
42770     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42771   },
42772 /* divx.b ${Dsp-16-u16}[$Dst16An] */
42773   {
42774     M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_16_AN_RELATIVE_QI, "divx16.b-dst16-16-QI-dst16-16-16-An-relative-QI", "divx.b", 32,
42775     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42776   },
42777 /* divx.b ${Dsp-16-u8}[sb] */
42778   {
42779     M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_8_SB_RELATIVE_QI, "divx16.b-dst16-16-QI-dst16-16-8-SB-relative-QI", "divx.b", 24,
42780     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42781   },
42782 /* divx.b ${Dsp-16-u16}[sb] */
42783   {
42784     M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_16_SB_RELATIVE_QI, "divx16.b-dst16-16-QI-dst16-16-16-SB-relative-QI", "divx.b", 32,
42785     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42786   },
42787 /* divx.b ${Dsp-16-s8}[fb] */
42788   {
42789     M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_8_FB_RELATIVE_QI, "divx16.b-dst16-16-QI-dst16-16-8-FB-relative-QI", "divx.b", 24,
42790     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42791   },
42792 /* divx.b ${Dsp-16-u16} */
42793   {
42794     M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_16_ABSOLUTE_QI, "divx16.b-dst16-16-QI-dst16-16-16-absolute-QI", "divx.b", 32,
42795     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42796   },
42797 /* divu.w $Dst32RnUnprefixedHI */
42798   {
42799     M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "divu.w", 16,
42800     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42801   },
42802 /* divu.w $Dst32AnUnprefixedHI */
42803   {
42804     M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "divu.w", 16,
42805     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42806   },
42807 /* divu.w [$Dst32AnUnprefixed] */
42808   {
42809     M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "divu.w", 16,
42810     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42811   },
42812 /* divu.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
42813   {
42814     M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "divu.w", 24,
42815     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42816   },
42817 /* divu.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
42818   {
42819     M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "divu.w", 32,
42820     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42821   },
42822 /* divu.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
42823   {
42824     M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "divu.w", 40,
42825     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42826   },
42827 /* divu.w ${Dsp-16-u8}[sb] */
42828   {
42829     M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "divu.w", 24,
42830     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42831   },
42832 /* divu.w ${Dsp-16-u16}[sb] */
42833   {
42834     M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "divu.w", 32,
42835     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42836   },
42837 /* divu.w ${Dsp-16-s8}[fb] */
42838   {
42839     M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "divu.w", 24,
42840     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42841   },
42842 /* divu.w ${Dsp-16-s16}[fb] */
42843   {
42844     M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "divu.w", 32,
42845     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42846   },
42847 /* divu.w ${Dsp-16-u16} */
42848   {
42849     M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "divu.w", 32,
42850     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42851   },
42852 /* divu.w ${Dsp-16-u24} */
42853   {
42854     M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "divu.w", 40,
42855     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42856   },
42857 /* divu.b $Dst32RnUnprefixedQI */
42858   {
42859     M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "divu.b", 16,
42860     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42861   },
42862 /* divu.b $Dst32AnUnprefixedQI */
42863   {
42864     M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "divu.b", 16,
42865     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42866   },
42867 /* divu.b [$Dst32AnUnprefixed] */
42868   {
42869     M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "divu.b", 16,
42870     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42871   },
42872 /* divu.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
42873   {
42874     M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "divu.b", 24,
42875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42876   },
42877 /* divu.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
42878   {
42879     M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "divu.b", 32,
42880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42881   },
42882 /* divu.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
42883   {
42884     M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "divu.b", 40,
42885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42886   },
42887 /* divu.b ${Dsp-16-u8}[sb] */
42888   {
42889     M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "divu.b", 24,
42890     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42891   },
42892 /* divu.b ${Dsp-16-u16}[sb] */
42893   {
42894     M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "divu.b", 32,
42895     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42896   },
42897 /* divu.b ${Dsp-16-s8}[fb] */
42898   {
42899     M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "divu.b", 24,
42900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42901   },
42902 /* divu.b ${Dsp-16-s16}[fb] */
42903   {
42904     M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "divu.b", 32,
42905     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42906   },
42907 /* divu.b ${Dsp-16-u16} */
42908   {
42909     M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "divu.b", 32,
42910     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42911   },
42912 /* divu.b ${Dsp-16-u24} */
42913   {
42914     M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "divu.b", 40,
42915     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42916   },
42917 /* divu.w $Dst16RnHI */
42918   {
42919     M32C_INSN_DIVU16_W_DST16_16_HI_DST16_RN_DIRECT_HI, "divu16.w-dst16-16-HI-dst16-Rn-direct-HI", "divu.w", 16,
42920     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42921   },
42922 /* divu.w $Dst16AnHI */
42923   {
42924     M32C_INSN_DIVU16_W_DST16_16_HI_DST16_AN_DIRECT_HI, "divu16.w-dst16-16-HI-dst16-An-direct-HI", "divu.w", 16,
42925     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42926   },
42927 /* divu.w [$Dst16An] */
42928   {
42929     M32C_INSN_DIVU16_W_DST16_16_HI_DST16_AN_INDIRECT_HI, "divu16.w-dst16-16-HI-dst16-An-indirect-HI", "divu.w", 16,
42930     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42931   },
42932 /* divu.w ${Dsp-16-u8}[$Dst16An] */
42933   {
42934     M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_8_AN_RELATIVE_HI, "divu16.w-dst16-16-HI-dst16-16-8-An-relative-HI", "divu.w", 24,
42935     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42936   },
42937 /* divu.w ${Dsp-16-u16}[$Dst16An] */
42938   {
42939     M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_16_AN_RELATIVE_HI, "divu16.w-dst16-16-HI-dst16-16-16-An-relative-HI", "divu.w", 32,
42940     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42941   },
42942 /* divu.w ${Dsp-16-u8}[sb] */
42943   {
42944     M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_8_SB_RELATIVE_HI, "divu16.w-dst16-16-HI-dst16-16-8-SB-relative-HI", "divu.w", 24,
42945     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42946   },
42947 /* divu.w ${Dsp-16-u16}[sb] */
42948   {
42949     M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_16_SB_RELATIVE_HI, "divu16.w-dst16-16-HI-dst16-16-16-SB-relative-HI", "divu.w", 32,
42950     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42951   },
42952 /* divu.w ${Dsp-16-s8}[fb] */
42953   {
42954     M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_8_FB_RELATIVE_HI, "divu16.w-dst16-16-HI-dst16-16-8-FB-relative-HI", "divu.w", 24,
42955     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42956   },
42957 /* divu.w ${Dsp-16-u16} */
42958   {
42959     M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_16_ABSOLUTE_HI, "divu16.w-dst16-16-HI-dst16-16-16-absolute-HI", "divu.w", 32,
42960     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42961   },
42962 /* divu.b $Dst16RnQI */
42963   {
42964     M32C_INSN_DIVU16_B_DST16_16_QI_DST16_RN_DIRECT_QI, "divu16.b-dst16-16-QI-dst16-Rn-direct-QI", "divu.b", 16,
42965     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42966   },
42967 /* divu.b $Dst16AnQI */
42968   {
42969     M32C_INSN_DIVU16_B_DST16_16_QI_DST16_AN_DIRECT_QI, "divu16.b-dst16-16-QI-dst16-An-direct-QI", "divu.b", 16,
42970     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42971   },
42972 /* divu.b [$Dst16An] */
42973   {
42974     M32C_INSN_DIVU16_B_DST16_16_QI_DST16_AN_INDIRECT_QI, "divu16.b-dst16-16-QI-dst16-An-indirect-QI", "divu.b", 16,
42975     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42976   },
42977 /* divu.b ${Dsp-16-u8}[$Dst16An] */
42978   {
42979     M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_8_AN_RELATIVE_QI, "divu16.b-dst16-16-QI-dst16-16-8-An-relative-QI", "divu.b", 24,
42980     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42981   },
42982 /* divu.b ${Dsp-16-u16}[$Dst16An] */
42983   {
42984     M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_16_AN_RELATIVE_QI, "divu16.b-dst16-16-QI-dst16-16-16-An-relative-QI", "divu.b", 32,
42985     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42986   },
42987 /* divu.b ${Dsp-16-u8}[sb] */
42988   {
42989     M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_8_SB_RELATIVE_QI, "divu16.b-dst16-16-QI-dst16-16-8-SB-relative-QI", "divu.b", 24,
42990     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42991   },
42992 /* divu.b ${Dsp-16-u16}[sb] */
42993   {
42994     M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_16_SB_RELATIVE_QI, "divu16.b-dst16-16-QI-dst16-16-16-SB-relative-QI", "divu.b", 32,
42995     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42996   },
42997 /* divu.b ${Dsp-16-s8}[fb] */
42998   {
42999     M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_8_FB_RELATIVE_QI, "divu16.b-dst16-16-QI-dst16-16-8-FB-relative-QI", "divu.b", 24,
43000     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43001   },
43002 /* divu.b ${Dsp-16-u16} */
43003   {
43004     M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_16_ABSOLUTE_QI, "divu16.b-dst16-16-QI-dst16-16-16-absolute-QI", "divu.b", 32,
43005     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43006   },
43007 /* div.w $Dst32RnUnprefixedHI */
43008   {
43009     M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "div.w", 16,
43010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43011   },
43012 /* div.w $Dst32AnUnprefixedHI */
43013   {
43014     M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "div.w", 16,
43015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43016   },
43017 /* div.w [$Dst32AnUnprefixed] */
43018   {
43019     M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "div.w", 16,
43020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43021   },
43022 /* div.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
43023   {
43024     M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "div.w", 24,
43025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43026   },
43027 /* div.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
43028   {
43029     M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "div.w", 32,
43030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43031   },
43032 /* div.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
43033   {
43034     M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "div.w", 40,
43035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43036   },
43037 /* div.w ${Dsp-16-u8}[sb] */
43038   {
43039     M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "div.w", 24,
43040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43041   },
43042 /* div.w ${Dsp-16-u16}[sb] */
43043   {
43044     M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "div.w", 32,
43045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43046   },
43047 /* div.w ${Dsp-16-s8}[fb] */
43048   {
43049     M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "div.w", 24,
43050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43051   },
43052 /* div.w ${Dsp-16-s16}[fb] */
43053   {
43054     M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "div.w", 32,
43055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43056   },
43057 /* div.w ${Dsp-16-u16} */
43058   {
43059     M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "div.w", 32,
43060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43061   },
43062 /* div.w ${Dsp-16-u24} */
43063   {
43064     M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "div.w", 40,
43065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43066   },
43067 /* div.b $Dst32RnUnprefixedQI */
43068   {
43069     M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "div.b", 16,
43070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43071   },
43072 /* div.b $Dst32AnUnprefixedQI */
43073   {
43074     M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "div.b", 16,
43075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43076   },
43077 /* div.b [$Dst32AnUnprefixed] */
43078   {
43079     M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "div.b", 16,
43080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43081   },
43082 /* div.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
43083   {
43084     M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "div.b", 24,
43085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43086   },
43087 /* div.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
43088   {
43089     M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "div.b", 32,
43090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43091   },
43092 /* div.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
43093   {
43094     M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "div.b", 40,
43095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43096   },
43097 /* div.b ${Dsp-16-u8}[sb] */
43098   {
43099     M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "div.b", 24,
43100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43101   },
43102 /* div.b ${Dsp-16-u16}[sb] */
43103   {
43104     M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "div.b", 32,
43105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43106   },
43107 /* div.b ${Dsp-16-s8}[fb] */
43108   {
43109     M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "div.b", 24,
43110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43111   },
43112 /* div.b ${Dsp-16-s16}[fb] */
43113   {
43114     M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "div.b", 32,
43115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43116   },
43117 /* div.b ${Dsp-16-u16} */
43118   {
43119     M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "div.b", 32,
43120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43121   },
43122 /* div.b ${Dsp-16-u24} */
43123   {
43124     M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "div.b", 40,
43125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43126   },
43127 /* div.w $Dst16RnHI */
43128   {
43129     M32C_INSN_DIV16_W_DST16_16_HI_DST16_RN_DIRECT_HI, "div16.w-dst16-16-HI-dst16-Rn-direct-HI", "div.w", 16,
43130     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43131   },
43132 /* div.w $Dst16AnHI */
43133   {
43134     M32C_INSN_DIV16_W_DST16_16_HI_DST16_AN_DIRECT_HI, "div16.w-dst16-16-HI-dst16-An-direct-HI", "div.w", 16,
43135     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43136   },
43137 /* div.w [$Dst16An] */
43138   {
43139     M32C_INSN_DIV16_W_DST16_16_HI_DST16_AN_INDIRECT_HI, "div16.w-dst16-16-HI-dst16-An-indirect-HI", "div.w", 16,
43140     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43141   },
43142 /* div.w ${Dsp-16-u8}[$Dst16An] */
43143   {
43144     M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_8_AN_RELATIVE_HI, "div16.w-dst16-16-HI-dst16-16-8-An-relative-HI", "div.w", 24,
43145     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43146   },
43147 /* div.w ${Dsp-16-u16}[$Dst16An] */
43148   {
43149     M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_16_AN_RELATIVE_HI, "div16.w-dst16-16-HI-dst16-16-16-An-relative-HI", "div.w", 32,
43150     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43151   },
43152 /* div.w ${Dsp-16-u8}[sb] */
43153   {
43154     M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_8_SB_RELATIVE_HI, "div16.w-dst16-16-HI-dst16-16-8-SB-relative-HI", "div.w", 24,
43155     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43156   },
43157 /* div.w ${Dsp-16-u16}[sb] */
43158   {
43159     M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_16_SB_RELATIVE_HI, "div16.w-dst16-16-HI-dst16-16-16-SB-relative-HI", "div.w", 32,
43160     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43161   },
43162 /* div.w ${Dsp-16-s8}[fb] */
43163   {
43164     M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_8_FB_RELATIVE_HI, "div16.w-dst16-16-HI-dst16-16-8-FB-relative-HI", "div.w", 24,
43165     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43166   },
43167 /* div.w ${Dsp-16-u16} */
43168   {
43169     M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_16_ABSOLUTE_HI, "div16.w-dst16-16-HI-dst16-16-16-absolute-HI", "div.w", 32,
43170     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43171   },
43172 /* div.b $Dst16RnQI */
43173   {
43174     M32C_INSN_DIV16_B_DST16_16_QI_DST16_RN_DIRECT_QI, "div16.b-dst16-16-QI-dst16-Rn-direct-QI", "div.b", 16,
43175     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43176   },
43177 /* div.b $Dst16AnQI */
43178   {
43179     M32C_INSN_DIV16_B_DST16_16_QI_DST16_AN_DIRECT_QI, "div16.b-dst16-16-QI-dst16-An-direct-QI", "div.b", 16,
43180     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43181   },
43182 /* div.b [$Dst16An] */
43183   {
43184     M32C_INSN_DIV16_B_DST16_16_QI_DST16_AN_INDIRECT_QI, "div16.b-dst16-16-QI-dst16-An-indirect-QI", "div.b", 16,
43185     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43186   },
43187 /* div.b ${Dsp-16-u8}[$Dst16An] */
43188   {
43189     M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_8_AN_RELATIVE_QI, "div16.b-dst16-16-QI-dst16-16-8-An-relative-QI", "div.b", 24,
43190     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43191   },
43192 /* div.b ${Dsp-16-u16}[$Dst16An] */
43193   {
43194     M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_16_AN_RELATIVE_QI, "div16.b-dst16-16-QI-dst16-16-16-An-relative-QI", "div.b", 32,
43195     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43196   },
43197 /* div.b ${Dsp-16-u8}[sb] */
43198   {
43199     M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_8_SB_RELATIVE_QI, "div16.b-dst16-16-QI-dst16-16-8-SB-relative-QI", "div.b", 24,
43200     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43201   },
43202 /* div.b ${Dsp-16-u16}[sb] */
43203   {
43204     M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_16_SB_RELATIVE_QI, "div16.b-dst16-16-QI-dst16-16-16-SB-relative-QI", "div.b", 32,
43205     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43206   },
43207 /* div.b ${Dsp-16-s8}[fb] */
43208   {
43209     M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_8_FB_RELATIVE_QI, "div16.b-dst16-16-QI-dst16-16-8-FB-relative-QI", "div.b", 24,
43210     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43211   },
43212 /* div.b ${Dsp-16-u16} */
43213   {
43214     M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_16_ABSOLUTE_QI, "div16.b-dst16-16-QI-dst16-16-16-absolute-QI", "div.b", 32,
43215     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43216   },
43217 /* dec.w $Dst32RnUnprefixedHI */
43218   {
43219     M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "dec.w", 16,
43220     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43221   },
43222 /* dec.w $Dst32AnUnprefixedHI */
43223   {
43224     M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "dec.w", 16,
43225     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43226   },
43227 /* dec.w [$Dst32AnUnprefixed] */
43228   {
43229     M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "dec.w", 16,
43230     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43231   },
43232 /* dec.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
43233   {
43234     M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "dec.w", 24,
43235     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43236   },
43237 /* dec.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
43238   {
43239     M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "dec.w", 32,
43240     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43241   },
43242 /* dec.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
43243   {
43244     M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "dec.w", 40,
43245     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43246   },
43247 /* dec.w ${Dsp-16-u8}[sb] */
43248   {
43249     M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "dec.w", 24,
43250     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43251   },
43252 /* dec.w ${Dsp-16-u16}[sb] */
43253   {
43254     M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "dec.w", 32,
43255     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43256   },
43257 /* dec.w ${Dsp-16-s8}[fb] */
43258   {
43259     M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "dec.w", 24,
43260     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43261   },
43262 /* dec.w ${Dsp-16-s16}[fb] */
43263   {
43264     M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "dec.w", 32,
43265     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43266   },
43267 /* dec.w ${Dsp-16-u16} */
43268   {
43269     M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "dec.w", 32,
43270     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43271   },
43272 /* dec.w ${Dsp-16-u24} */
43273   {
43274     M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "dec.w", 40,
43275     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43276   },
43277 /* dec.b $Dst32RnUnprefixedQI */
43278   {
43279     M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "dec.b", 16,
43280     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43281   },
43282 /* dec.b $Dst32AnUnprefixedQI */
43283   {
43284     M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "dec.b", 16,
43285     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43286   },
43287 /* dec.b [$Dst32AnUnprefixed] */
43288   {
43289     M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "dec.b", 16,
43290     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43291   },
43292 /* dec.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
43293   {
43294     M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "dec.b", 24,
43295     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43296   },
43297 /* dec.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
43298   {
43299     M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "dec.b", 32,
43300     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43301   },
43302 /* dec.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
43303   {
43304     M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "dec.b", 40,
43305     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43306   },
43307 /* dec.b ${Dsp-16-u8}[sb] */
43308   {
43309     M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "dec.b", 24,
43310     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43311   },
43312 /* dec.b ${Dsp-16-u16}[sb] */
43313   {
43314     M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "dec.b", 32,
43315     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43316   },
43317 /* dec.b ${Dsp-16-s8}[fb] */
43318   {
43319     M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "dec.b", 24,
43320     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43321   },
43322 /* dec.b ${Dsp-16-s16}[fb] */
43323   {
43324     M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "dec.b", 32,
43325     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43326   },
43327 /* dec.b ${Dsp-16-u16} */
43328   {
43329     M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "dec.b", 32,
43330     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43331   },
43332 /* dec.b ${Dsp-16-u24} */
43333   {
43334     M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "dec.b", 40,
43335     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43336   },
43337 /* dec.b r0l */
43338   {
43339     M32C_INSN_DEC16_B_DST16_3_S_R0L_DIRECT_QI, "dec16.b-dst16-3-S-R0l-direct-QI", "dec.b", 8,
43340     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43341   },
43342 /* dec.b r0h */
43343   {
43344     M32C_INSN_DEC16_B_DST16_3_S_R0H_DIRECT_QI, "dec16.b-dst16-3-S-R0h-direct-QI", "dec.b", 8,
43345     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43346   },
43347 /* dec.b ${Dsp-8-u8}[sb] */
43348   {
43349     M32C_INSN_DEC16_B_DST16_3_S_8_8_SB_RELATIVE_QI, "dec16.b-dst16-3-S-8-8-SB-relative-QI", "dec.b", 16,
43350     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43351   },
43352 /* dec.b ${Dsp-8-s8}[fb] */
43353   {
43354     M32C_INSN_DEC16_B_DST16_3_S_8_8_FB_RELATIVE_QI, "dec16.b-dst16-3-S-8-8-FB-relative-QI", "dec.b", 16,
43355     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43356   },
43357 /* dec.b ${Dsp-8-u16} */
43358   {
43359     M32C_INSN_DEC16_B_DST16_3_S_8_16_ABSOLUTE_QI, "dec16.b-dst16-3-S-8-16-absolute-QI", "dec.b", 24,
43360     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43361   },
43362 /* cmpx${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
43363   {
43364     M32C_INSN_CMPX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "cmpx32-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "cmpx", 24,
43365     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43366   },
43367 /* cmpx${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
43368   {
43369     M32C_INSN_CMPX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "cmpx32-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "cmpx", 24,
43370     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43371   },
43372 /* cmpx${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
43373   {
43374     M32C_INSN_CMPX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmpx32-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "cmpx", 24,
43375     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43376   },
43377 /* cmpx${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
43378   {
43379     M32C_INSN_CMPX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "cmpx", 32,
43380     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43381   },
43382 /* cmpx${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
43383   {
43384     M32C_INSN_CMPX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "cmpx", 32,
43385     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43386   },
43387 /* cmpx${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
43388   {
43389     M32C_INSN_CMPX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "cmpx", 32,
43390     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43391   },
43392 /* cmpx${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
43393   {
43394     M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "cmpx", 40,
43395     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43396   },
43397 /* cmpx${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
43398   {
43399     M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "cmpx", 40,
43400     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43401   },
43402 /* cmpx${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
43403   {
43404     M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "cmpx", 40,
43405     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43406   },
43407 /* cmpx${X} #${Imm-32-QI},${Dsp-16-u16} */
43408   {
43409     M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "cmpx32-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "cmpx", 40,
43410     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43411   },
43412 /* cmpx${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
43413   {
43414     M32C_INSN_CMPX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "cmpx", 48,
43415     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43416   },
43417 /* cmpx${X} #${Imm-40-QI},${Dsp-16-u24} */
43418   {
43419     M32C_INSN_CMPX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "cmpx32-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "cmpx", 48,
43420     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43421   },
43422 /* cmp.w${S} ${Dsp-8-u8}[sb],${Dst32R0HI-S} */
43423   {
43424     M32C_INSN_CMP32_W_S_SRC2_R0_HI_SRC32_2_S_8_SB_RELATIVE_HI, "cmp32.w.S-src2-r0-HI-src32-2-S-8-SB-relative-HI", "cmp.w", 16,
43425     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43426   },
43427 /* cmp.w${S} ${Dsp-8-s8}[fb],${Dst32R0HI-S} */
43428   {
43429     M32C_INSN_CMP32_W_S_SRC2_R0_HI_SRC32_2_S_8_FB_RELATIVE_HI, "cmp32.w.S-src2-r0-HI-src32-2-S-8-FB-relative-HI", "cmp.w", 16,
43430     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43431   },
43432 /* cmp.w${S} ${Dsp-8-u16},${Dst32R0HI-S} */
43433   {
43434     M32C_INSN_CMP32_W_S_SRC2_R0_HI_SRC32_2_S_16_ABSOLUTE_HI, "cmp32.w.S-src2-r0-HI-src32-2-S-16-absolute-HI", "cmp.w", 24,
43435     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43436   },
43437 /* cmp.b${S} ${Dsp-8-u8}[sb],${Dst32R0QI-S} */
43438   {
43439     M32C_INSN_CMP32_B_S_SRC2_R0_QI_SRC32_2_S_8_SB_RELATIVE_QI, "cmp32.b.S-src2-r0-QI-src32-2-S-8-SB-relative-QI", "cmp.b", 16,
43440     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43441   },
43442 /* cmp.b${S} ${Dsp-8-s8}[fb],${Dst32R0QI-S} */
43443   {
43444     M32C_INSN_CMP32_B_S_SRC2_R0_QI_SRC32_2_S_8_FB_RELATIVE_QI, "cmp32.b.S-src2-r0-QI-src32-2-S-8-FB-relative-QI", "cmp.b", 16,
43445     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43446   },
43447 /* cmp.b${S} ${Dsp-8-u16},${Dst32R0QI-S} */
43448   {
43449     M32C_INSN_CMP32_B_S_SRC2_R0_QI_SRC32_2_S_16_ABSOLUTE_QI, "cmp32.b.S-src2-r0-QI-src32-2-S-16-absolute-QI", "cmp.b", 24,
43450     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43451   },
43452 /* cmp.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
43453   {
43454     M32C_INSN_CMP32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "cmp32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "cmp.w", 32,
43455     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43456   },
43457 /* cmp.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
43458   {
43459     M32C_INSN_CMP32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "cmp32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "cmp.w", 32,
43460     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43461   },
43462 /* cmp.w${S} #${Imm-24-HI},${Dsp-8-u16} */
43463   {
43464     M32C_INSN_CMP32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "cmp32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "cmp.w", 40,
43465     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43466   },
43467 /* cmp.w${S} #${Imm-8-HI},r0 */
43468   {
43469     M32C_INSN_CMP32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "cmp32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "cmp.w", 24,
43470     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43471   },
43472 /* cmp.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
43473   {
43474     M32C_INSN_CMP32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "cmp32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "cmp.b", 24,
43475     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43476   },
43477 /* cmp.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
43478   {
43479     M32C_INSN_CMP32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "cmp32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "cmp.b", 24,
43480     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43481   },
43482 /* cmp.b${S} #${Imm-24-QI},${Dsp-8-u16} */
43483   {
43484     M32C_INSN_CMP32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "cmp32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "cmp.b", 32,
43485     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43486   },
43487 /* cmp.b${S} #${Imm-8-QI},r0l */
43488   {
43489     M32C_INSN_CMP32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "cmp32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "cmp.b", 16,
43490     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43491   },
43492 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
43493   {
43494     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 24,
43495     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43496   },
43497 /* cmp.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
43498   {
43499     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 24,
43500     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43501   },
43502 /* cmp.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
43503   {
43504     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 24,
43505     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43506   },
43507 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
43508   {
43509     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 24,
43510     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43511   },
43512 /* cmp.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
43513   {
43514     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 24,
43515     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43516   },
43517 /* cmp.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
43518   {
43519     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 24,
43520     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43521   },
43522 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
43523   {
43524     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 24,
43525     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43526   },
43527 /* cmp.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
43528   {
43529     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 24,
43530     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43531   },
43532 /* cmp.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
43533   {
43534     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 24,
43535     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43536   },
43537 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
43538   {
43539     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "cmp.l", 32,
43540     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43541   },
43542 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
43543   {
43544     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "cmp.l", 32,
43545     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43546   },
43547 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
43548   {
43549     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "cmp.l", 32,
43550     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43551   },
43552 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
43553   {
43554     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "cmp.l", 40,
43555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43556   },
43557 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
43558   {
43559     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "cmp.l", 40,
43560     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43561   },
43562 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
43563   {
43564     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "cmp.l", 40,
43565     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43566   },
43567 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
43568   {
43569     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "cmp.l", 48,
43570     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43571   },
43572 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
43573   {
43574     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "cmp.l", 48,
43575     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43576   },
43577 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
43578   {
43579     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "cmp.l", 48,
43580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43581   },
43582 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
43583   {
43584     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "cmp.l", 32,
43585     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43586   },
43587 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
43588   {
43589     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "cmp.l", 32,
43590     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43591   },
43592 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
43593   {
43594     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "cmp.l", 32,
43595     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43596   },
43597 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
43598   {
43599     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "cmp.l", 40,
43600     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43601   },
43602 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
43603   {
43604     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "cmp.l", 40,
43605     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43606   },
43607 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
43608   {
43609     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "cmp.l", 40,
43610     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43611   },
43612 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
43613   {
43614     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "cmp.l", 32,
43615     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43616   },
43617 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
43618   {
43619     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "cmp.l", 32,
43620     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43621   },
43622 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
43623   {
43624     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "cmp.l", 32,
43625     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43626   },
43627 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
43628   {
43629     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "cmp.l", 40,
43630     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43631   },
43632 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
43633   {
43634     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "cmp.l", 40,
43635     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43636   },
43637 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
43638   {
43639     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "cmp.l", 40,
43640     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43641   },
43642 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
43643   {
43644     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "cmp.l", 40,
43645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43646   },
43647 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
43648   {
43649     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "cmp.l", 40,
43650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43651   },
43652 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
43653   {
43654     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "cmp.l", 40,
43655     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43656   },
43657 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
43658   {
43659     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "cmp.l", 48,
43660     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43661   },
43662 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
43663   {
43664     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "cmp.l", 48,
43665     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43666   },
43667 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
43668   {
43669     M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "cmp.l", 48,
43670     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43671   },
43672 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
43673   {
43674     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 32,
43675     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43676   },
43677 /* cmp.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
43678   {
43679     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 32,
43680     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43681   },
43682 /* cmp.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
43683   {
43684     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 32,
43685     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43686   },
43687 /* cmp.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
43688   {
43689     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 32,
43690     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43691   },
43692 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
43693   {
43694     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 32,
43695     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43696   },
43697 /* cmp.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
43698   {
43699     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 32,
43700     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43701   },
43702 /* cmp.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
43703   {
43704     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 32,
43705     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43706   },
43707 /* cmp.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
43708   {
43709     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 32,
43710     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43711   },
43712 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
43713   {
43714     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 32,
43715     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43716   },
43717 /* cmp.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
43718   {
43719     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 32,
43720     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43721   },
43722 /* cmp.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
43723   {
43724     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 32,
43725     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43726   },
43727 /* cmp.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
43728   {
43729     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 32,
43730     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43731   },
43732 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
43733   {
43734     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "cmp.l", 40,
43735     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43736   },
43737 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
43738   {
43739     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "cmp.l", 40,
43740     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43741   },
43742 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
43743   {
43744     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "cmp.l", 40,
43745     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43746   },
43747 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
43748   {
43749     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "cmp.l", 40,
43750     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43751   },
43752 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
43753   {
43754     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "cmp.l", 48,
43755     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43756   },
43757 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
43758   {
43759     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "cmp.l", 48,
43760     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43761   },
43762 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
43763   {
43764     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "cmp.l", 48,
43765     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43766   },
43767 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
43768   {
43769     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "cmp.l", 48,
43770     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43771   },
43772 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
43773   {
43774     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "cmp.l", 56,
43775     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43776   },
43777 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
43778   {
43779     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "cmp.l", 56,
43780     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43781   },
43782 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
43783   {
43784     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "cmp.l", 56,
43785     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43786   },
43787 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
43788   {
43789     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "cmp.l", 56,
43790     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43791   },
43792 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
43793   {
43794     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "cmp.l", 40,
43795     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43796   },
43797 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
43798   {
43799     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "cmp.l", 40,
43800     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43801   },
43802 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
43803   {
43804     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "cmp.l", 40,
43805     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43806   },
43807 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
43808   {
43809     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "cmp.l", 40,
43810     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43811   },
43812 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
43813   {
43814     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "cmp.l", 48,
43815     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43816   },
43817 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
43818   {
43819     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "cmp.l", 48,
43820     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43821   },
43822 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
43823   {
43824     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "cmp.l", 48,
43825     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43826   },
43827 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
43828   {
43829     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "cmp.l", 48,
43830     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43831   },
43832 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
43833   {
43834     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "cmp.l", 40,
43835     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43836   },
43837 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
43838   {
43839     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "cmp.l", 40,
43840     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43841   },
43842 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
43843   {
43844     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "cmp.l", 40,
43845     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43846   },
43847 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
43848   {
43849     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "cmp.l", 40,
43850     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43851   },
43852 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
43853   {
43854     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "cmp.l", 48,
43855     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43856   },
43857 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
43858   {
43859     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "cmp.l", 48,
43860     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43861   },
43862 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
43863   {
43864     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "cmp.l", 48,
43865     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43866   },
43867 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
43868   {
43869     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "cmp.l", 48,
43870     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43871   },
43872 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
43873   {
43874     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "cmp.l", 48,
43875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43876   },
43877 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
43878   {
43879     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "cmp.l", 48,
43880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43881   },
43882 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
43883   {
43884     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "cmp.l", 48,
43885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43886   },
43887 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u16} */
43888   {
43889     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "cmp.l", 48,
43890     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43891   },
43892 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
43893   {
43894     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "cmp.l", 56,
43895     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43896   },
43897 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
43898   {
43899     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "cmp.l", 56,
43900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43901   },
43902 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
43903   {
43904     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "cmp.l", 56,
43905     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43906   },
43907 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u24} */
43908   {
43909     M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "cmp.l", 56,
43910     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43911   },
43912 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
43913   {
43914     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 40,
43915     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43916   },
43917 /* cmp.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
43918   {
43919     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 40,
43920     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43921   },
43922 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
43923   {
43924     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 40,
43925     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43926   },
43927 /* cmp.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
43928   {
43929     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 40,
43930     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43931   },
43932 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
43933   {
43934     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 40,
43935     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43936   },
43937 /* cmp.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
43938   {
43939     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 40,
43940     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43941   },
43942 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
43943   {
43944     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "cmp.l", 48,
43945     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43946   },
43947 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
43948   {
43949     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "cmp.l", 48,
43950     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43951   },
43952 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
43953   {
43954     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "cmp.l", 56,
43955     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43956   },
43957 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
43958   {
43959     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "cmp.l", 56,
43960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43961   },
43962 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
43963   {
43964     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "cmp.l", 64,
43965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43966   },
43967 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
43968   {
43969     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "cmp.l", 64,
43970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43971   },
43972 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
43973   {
43974     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "cmp.l", 48,
43975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43976   },
43977 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
43978   {
43979     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "cmp.l", 48,
43980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43981   },
43982 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
43983   {
43984     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "cmp.l", 56,
43985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43986   },
43987 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
43988   {
43989     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "cmp.l", 56,
43990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43991   },
43992 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
43993   {
43994     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "cmp.l", 48,
43995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43996   },
43997 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
43998   {
43999     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "cmp.l", 48,
44000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44001   },
44002 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
44003   {
44004     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "cmp.l", 56,
44005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44006   },
44007 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
44008   {
44009     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "cmp.l", 56,
44010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44011   },
44012 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
44013   {
44014     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "cmp.l", 56,
44015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44016   },
44017 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u16} */
44018   {
44019     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "cmp.l", 56,
44020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44021   },
44022 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
44023   {
44024     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "cmp.l", 64,
44025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44026   },
44027 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u24} */
44028   {
44029     M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "cmp.l", 64,
44030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44031   },
44032 /* cmp.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */
44033   {
44034     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 16,
44035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44036   },
44037 /* cmp.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */
44038   {
44039     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 16,
44040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44041   },
44042 /* cmp.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
44043   {
44044     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 16,
44045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44046   },
44047 /* cmp.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */
44048   {
44049     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 16,
44050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44051   },
44052 /* cmp.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */
44053   {
44054     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 16,
44055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44056   },
44057 /* cmp.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
44058   {
44059     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 16,
44060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44061   },
44062 /* cmp.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */
44063   {
44064     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 16,
44065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44066   },
44067 /* cmp.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */
44068   {
44069     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 16,
44070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44071   },
44072 /* cmp.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
44073   {
44074     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 16,
44075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44076   },
44077 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
44078   {
44079     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "cmp.l", 24,
44080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44081   },
44082 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
44083   {
44084     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "cmp.l", 24,
44085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44086   },
44087 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
44088   {
44089     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "cmp.l", 24,
44090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44091   },
44092 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
44093   {
44094     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "cmp.l", 32,
44095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44096   },
44097 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
44098   {
44099     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "cmp.l", 32,
44100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44101   },
44102 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
44103   {
44104     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "cmp.l", 32,
44105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44106   },
44107 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
44108   {
44109     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "cmp.l", 40,
44110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44111   },
44112 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
44113   {
44114     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "cmp.l", 40,
44115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44116   },
44117 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
44118   {
44119     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "cmp.l", 40,
44120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44121   },
44122 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */
44123   {
44124     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "cmp.l", 24,
44125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44126   },
44127 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */
44128   {
44129     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "cmp.l", 24,
44130     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44131   },
44132 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
44133   {
44134     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "cmp.l", 24,
44135     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44136   },
44137 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */
44138   {
44139     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "cmp.l", 32,
44140     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44141   },
44142 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */
44143   {
44144     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "cmp.l", 32,
44145     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44146   },
44147 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
44148   {
44149     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "cmp.l", 32,
44150     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44151   },
44152 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */
44153   {
44154     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "cmp.l", 24,
44155     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44156   },
44157 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */
44158   {
44159     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "cmp.l", 24,
44160     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44161   },
44162 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
44163   {
44164     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "cmp.l", 24,
44165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44166   },
44167 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */
44168   {
44169     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "cmp.l", 32,
44170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44171   },
44172 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */
44173   {
44174     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "cmp.l", 32,
44175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44176   },
44177 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
44178   {
44179     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "cmp.l", 32,
44180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44181   },
44182 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */
44183   {
44184     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "cmp.l", 32,
44185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44186   },
44187 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */
44188   {
44189     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "cmp.l", 32,
44190     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44191   },
44192 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
44193   {
44194     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "cmp.l", 32,
44195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44196   },
44197 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */
44198   {
44199     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "cmp.l", 40,
44200     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44201   },
44202 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */
44203   {
44204     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "cmp.l", 40,
44205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44206   },
44207 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
44208   {
44209     M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "cmp.l", 40,
44210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44211   },
44212 /* cmp.b${S} ${SrcDst16-r0l-r0h-S-normal} */
44213   {
44214     M32C_INSN_CMP16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, "cmp16.b.S-r0l-r0h-srcdst16-r0l-r0h-S-derived", "cmp.b", 8,
44215     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
44216   },
44217 /* cmp.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
44218   {
44219     M32C_INSN_CMP16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, "cmp16.b.S-src2-src16-2-S-8-SB-relative-QI", "cmp.b", 16,
44220     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
44221   },
44222 /* cmp.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
44223   {
44224     M32C_INSN_CMP16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, "cmp16.b.S-src2-src16-2-S-8-FB-relative-QI", "cmp.b", 16,
44225     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
44226   },
44227 /* cmp.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
44228   {
44229     M32C_INSN_CMP16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, "cmp16.b.S-src2-src16-2-S-16-absolute-QI", "cmp.b", 24,
44230     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
44231   },
44232 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
44233   {
44234     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 24,
44235     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44236   },
44237 /* cmp.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
44238   {
44239     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 24,
44240     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44241   },
44242 /* cmp.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
44243   {
44244     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 24,
44245     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44246   },
44247 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
44248   {
44249     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 24,
44250     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44251   },
44252 /* cmp.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
44253   {
44254     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 24,
44255     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44256   },
44257 /* cmp.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
44258   {
44259     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 24,
44260     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44261   },
44262 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
44263   {
44264     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 24,
44265     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44266   },
44267 /* cmp.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
44268   {
44269     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 24,
44270     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44271   },
44272 /* cmp.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
44273   {
44274     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 24,
44275     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44276   },
44277 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
44278   {
44279     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "cmp.w", 32,
44280     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44281   },
44282 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
44283   {
44284     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "cmp.w", 32,
44285     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44286   },
44287 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
44288   {
44289     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "cmp.w", 32,
44290     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44291   },
44292 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
44293   {
44294     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "cmp.w", 40,
44295     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44296   },
44297 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
44298   {
44299     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "cmp.w", 40,
44300     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44301   },
44302 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
44303   {
44304     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "cmp.w", 40,
44305     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44306   },
44307 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
44308   {
44309     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "cmp.w", 48,
44310     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44311   },
44312 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
44313   {
44314     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "cmp.w", 48,
44315     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44316   },
44317 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
44318   {
44319     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "cmp.w", 48,
44320     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44321   },
44322 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
44323   {
44324     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "cmp.w", 32,
44325     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44326   },
44327 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
44328   {
44329     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "cmp.w", 32,
44330     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44331   },
44332 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
44333   {
44334     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "cmp.w", 32,
44335     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44336   },
44337 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
44338   {
44339     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "cmp.w", 40,
44340     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44341   },
44342 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
44343   {
44344     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "cmp.w", 40,
44345     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44346   },
44347 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
44348   {
44349     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "cmp.w", 40,
44350     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44351   },
44352 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
44353   {
44354     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "cmp.w", 32,
44355     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44356   },
44357 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
44358   {
44359     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "cmp.w", 32,
44360     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44361   },
44362 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
44363   {
44364     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "cmp.w", 32,
44365     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44366   },
44367 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
44368   {
44369     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "cmp.w", 40,
44370     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44371   },
44372 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
44373   {
44374     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "cmp.w", 40,
44375     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44376   },
44377 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
44378   {
44379     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "cmp.w", 40,
44380     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44381   },
44382 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
44383   {
44384     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "cmp.w", 40,
44385     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44386   },
44387 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
44388   {
44389     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "cmp.w", 40,
44390     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44391   },
44392 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
44393   {
44394     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "cmp.w", 40,
44395     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44396   },
44397 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
44398   {
44399     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "cmp.w", 48,
44400     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44401   },
44402 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
44403   {
44404     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "cmp.w", 48,
44405     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44406   },
44407 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
44408   {
44409     M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "cmp.w", 48,
44410     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44411   },
44412 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
44413   {
44414     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 32,
44415     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44416   },
44417 /* cmp.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
44418   {
44419     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 32,
44420     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44421   },
44422 /* cmp.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
44423   {
44424     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 32,
44425     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44426   },
44427 /* cmp.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
44428   {
44429     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 32,
44430     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44431   },
44432 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
44433   {
44434     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 32,
44435     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44436   },
44437 /* cmp.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
44438   {
44439     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 32,
44440     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44441   },
44442 /* cmp.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
44443   {
44444     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 32,
44445     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44446   },
44447 /* cmp.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
44448   {
44449     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 32,
44450     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44451   },
44452 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
44453   {
44454     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 32,
44455     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44456   },
44457 /* cmp.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
44458   {
44459     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 32,
44460     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44461   },
44462 /* cmp.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
44463   {
44464     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 32,
44465     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44466   },
44467 /* cmp.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
44468   {
44469     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 32,
44470     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44471   },
44472 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
44473   {
44474     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "cmp.w", 40,
44475     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44476   },
44477 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
44478   {
44479     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "cmp.w", 40,
44480     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44481   },
44482 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
44483   {
44484     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "cmp.w", 40,
44485     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44486   },
44487 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
44488   {
44489     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "cmp.w", 40,
44490     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44491   },
44492 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
44493   {
44494     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "cmp.w", 48,
44495     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44496   },
44497 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
44498   {
44499     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "cmp.w", 48,
44500     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44501   },
44502 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
44503   {
44504     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "cmp.w", 48,
44505     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44506   },
44507 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
44508   {
44509     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "cmp.w", 48,
44510     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44511   },
44512 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
44513   {
44514     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "cmp.w", 56,
44515     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44516   },
44517 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
44518   {
44519     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "cmp.w", 56,
44520     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44521   },
44522 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
44523   {
44524     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "cmp.w", 56,
44525     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44526   },
44527 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
44528   {
44529     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "cmp.w", 56,
44530     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44531   },
44532 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
44533   {
44534     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "cmp.w", 40,
44535     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44536   },
44537 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
44538   {
44539     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "cmp.w", 40,
44540     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44541   },
44542 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
44543   {
44544     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "cmp.w", 40,
44545     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44546   },
44547 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
44548   {
44549     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "cmp.w", 40,
44550     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44551   },
44552 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
44553   {
44554     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "cmp.w", 48,
44555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44556   },
44557 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
44558   {
44559     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "cmp.w", 48,
44560     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44561   },
44562 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
44563   {
44564     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "cmp.w", 48,
44565     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44566   },
44567 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
44568   {
44569     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "cmp.w", 48,
44570     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44571   },
44572 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
44573   {
44574     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "cmp.w", 40,
44575     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44576   },
44577 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
44578   {
44579     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "cmp.w", 40,
44580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44581   },
44582 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
44583   {
44584     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "cmp.w", 40,
44585     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44586   },
44587 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
44588   {
44589     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "cmp.w", 40,
44590     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44591   },
44592 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
44593   {
44594     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "cmp.w", 48,
44595     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44596   },
44597 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
44598   {
44599     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "cmp.w", 48,
44600     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44601   },
44602 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
44603   {
44604     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "cmp.w", 48,
44605     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44606   },
44607 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
44608   {
44609     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "cmp.w", 48,
44610     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44611   },
44612 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
44613   {
44614     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "cmp.w", 48,
44615     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44616   },
44617 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
44618   {
44619     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "cmp.w", 48,
44620     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44621   },
44622 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
44623   {
44624     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "cmp.w", 48,
44625     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44626   },
44627 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
44628   {
44629     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "cmp.w", 48,
44630     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44631   },
44632 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
44633   {
44634     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "cmp.w", 56,
44635     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44636   },
44637 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
44638   {
44639     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "cmp.w", 56,
44640     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44641   },
44642 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
44643   {
44644     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "cmp.w", 56,
44645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44646   },
44647 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
44648   {
44649     M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "cmp.w", 56,
44650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44651   },
44652 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
44653   {
44654     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 40,
44655     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44656   },
44657 /* cmp.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
44658   {
44659     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 40,
44660     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44661   },
44662 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
44663   {
44664     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 40,
44665     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44666   },
44667 /* cmp.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
44668   {
44669     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 40,
44670     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44671   },
44672 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
44673   {
44674     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 40,
44675     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44676   },
44677 /* cmp.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
44678   {
44679     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 40,
44680     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44681   },
44682 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
44683   {
44684     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "cmp.w", 48,
44685     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44686   },
44687 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
44688   {
44689     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "cmp.w", 48,
44690     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44691   },
44692 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
44693   {
44694     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "cmp.w", 56,
44695     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44696   },
44697 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
44698   {
44699     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "cmp.w", 56,
44700     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44701   },
44702 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
44703   {
44704     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "cmp.w", 64,
44705     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44706   },
44707 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
44708   {
44709     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "cmp.w", 64,
44710     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44711   },
44712 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
44713   {
44714     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "cmp.w", 48,
44715     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44716   },
44717 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
44718   {
44719     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "cmp.w", 48,
44720     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44721   },
44722 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
44723   {
44724     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "cmp.w", 56,
44725     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44726   },
44727 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
44728   {
44729     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "cmp.w", 56,
44730     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44731   },
44732 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
44733   {
44734     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "cmp.w", 48,
44735     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44736   },
44737 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
44738   {
44739     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "cmp.w", 48,
44740     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44741   },
44742 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
44743   {
44744     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "cmp.w", 56,
44745     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44746   },
44747 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
44748   {
44749     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "cmp.w", 56,
44750     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44751   },
44752 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
44753   {
44754     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "cmp.w", 56,
44755     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44756   },
44757 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
44758   {
44759     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "cmp.w", 56,
44760     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44761   },
44762 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
44763   {
44764     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "cmp.w", 64,
44765     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44766   },
44767 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
44768   {
44769     M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "cmp.w", 64,
44770     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44771   },
44772 /* cmp.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
44773   {
44774     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 16,
44775     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44776   },
44777 /* cmp.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
44778   {
44779     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 16,
44780     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44781   },
44782 /* cmp.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
44783   {
44784     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 16,
44785     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44786   },
44787 /* cmp.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
44788   {
44789     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 16,
44790     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44791   },
44792 /* cmp.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
44793   {
44794     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 16,
44795     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44796   },
44797 /* cmp.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
44798   {
44799     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 16,
44800     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44801   },
44802 /* cmp.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
44803   {
44804     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 16,
44805     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44806   },
44807 /* cmp.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
44808   {
44809     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 16,
44810     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44811   },
44812 /* cmp.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
44813   {
44814     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 16,
44815     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44816   },
44817 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
44818   {
44819     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "cmp.w", 24,
44820     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44821   },
44822 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
44823   {
44824     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "cmp.w", 24,
44825     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44826   },
44827 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
44828   {
44829     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "cmp.w", 24,
44830     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44831   },
44832 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
44833   {
44834     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "cmp.w", 32,
44835     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44836   },
44837 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
44838   {
44839     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "cmp.w", 32,
44840     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44841   },
44842 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
44843   {
44844     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "cmp.w", 32,
44845     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44846   },
44847 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
44848   {
44849     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "cmp.w", 40,
44850     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44851   },
44852 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
44853   {
44854     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "cmp.w", 40,
44855     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44856   },
44857 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
44858   {
44859     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "cmp.w", 40,
44860     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44861   },
44862 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
44863   {
44864     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "cmp.w", 24,
44865     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44866   },
44867 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
44868   {
44869     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "cmp.w", 24,
44870     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44871   },
44872 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
44873   {
44874     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "cmp.w", 24,
44875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44876   },
44877 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
44878   {
44879     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "cmp.w", 32,
44880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44881   },
44882 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
44883   {
44884     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "cmp.w", 32,
44885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44886   },
44887 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
44888   {
44889     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "cmp.w", 32,
44890     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44891   },
44892 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
44893   {
44894     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "cmp.w", 24,
44895     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44896   },
44897 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
44898   {
44899     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "cmp.w", 24,
44900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44901   },
44902 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
44903   {
44904     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "cmp.w", 24,
44905     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44906   },
44907 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
44908   {
44909     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "cmp.w", 32,
44910     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44911   },
44912 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
44913   {
44914     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "cmp.w", 32,
44915     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44916   },
44917 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
44918   {
44919     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "cmp.w", 32,
44920     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44921   },
44922 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
44923   {
44924     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "cmp.w", 32,
44925     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44926   },
44927 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
44928   {
44929     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "cmp.w", 32,
44930     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44931   },
44932 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
44933   {
44934     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "cmp.w", 32,
44935     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44936   },
44937 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
44938   {
44939     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "cmp.w", 40,
44940     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44941   },
44942 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
44943   {
44944     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "cmp.w", 40,
44945     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44946   },
44947 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
44948   {
44949     M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "cmp.w", 40,
44950     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44951   },
44952 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
44953   {
44954     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 24,
44955     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44956   },
44957 /* cmp.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
44958   {
44959     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 24,
44960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44961   },
44962 /* cmp.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
44963   {
44964     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 24,
44965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44966   },
44967 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
44968   {
44969     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 24,
44970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44971   },
44972 /* cmp.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
44973   {
44974     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 24,
44975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44976   },
44977 /* cmp.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
44978   {
44979     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 24,
44980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44981   },
44982 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
44983   {
44984     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 24,
44985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44986   },
44987 /* cmp.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
44988   {
44989     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 24,
44990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44991   },
44992 /* cmp.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
44993   {
44994     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 24,
44995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44996   },
44997 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
44998   {
44999     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "cmp.b", 32,
45000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45001   },
45002 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
45003   {
45004     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "cmp.b", 32,
45005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45006   },
45007 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
45008   {
45009     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "cmp.b", 32,
45010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45011   },
45012 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
45013   {
45014     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "cmp.b", 40,
45015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45016   },
45017 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
45018   {
45019     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "cmp.b", 40,
45020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45021   },
45022 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
45023   {
45024     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "cmp.b", 40,
45025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45026   },
45027 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
45028   {
45029     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "cmp.b", 48,
45030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45031   },
45032 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
45033   {
45034     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "cmp.b", 48,
45035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45036   },
45037 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
45038   {
45039     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "cmp.b", 48,
45040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45041   },
45042 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
45043   {
45044     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "cmp.b", 32,
45045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45046   },
45047 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
45048   {
45049     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "cmp.b", 32,
45050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45051   },
45052 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
45053   {
45054     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "cmp.b", 32,
45055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45056   },
45057 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
45058   {
45059     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "cmp.b", 40,
45060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45061   },
45062 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
45063   {
45064     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "cmp.b", 40,
45065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45066   },
45067 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
45068   {
45069     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "cmp.b", 40,
45070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45071   },
45072 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
45073   {
45074     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "cmp.b", 32,
45075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45076   },
45077 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
45078   {
45079     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "cmp.b", 32,
45080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45081   },
45082 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
45083   {
45084     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "cmp.b", 32,
45085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45086   },
45087 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
45088   {
45089     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "cmp.b", 40,
45090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45091   },
45092 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
45093   {
45094     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "cmp.b", 40,
45095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45096   },
45097 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
45098   {
45099     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "cmp.b", 40,
45100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45101   },
45102 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
45103   {
45104     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "cmp.b", 40,
45105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45106   },
45107 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
45108   {
45109     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "cmp.b", 40,
45110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45111   },
45112 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
45113   {
45114     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "cmp.b", 40,
45115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45116   },
45117 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
45118   {
45119     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "cmp.b", 48,
45120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45121   },
45122 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
45123   {
45124     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "cmp.b", 48,
45125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45126   },
45127 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
45128   {
45129     M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "cmp.b", 48,
45130     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45131   },
45132 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
45133   {
45134     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 32,
45135     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45136   },
45137 /* cmp.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
45138   {
45139     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 32,
45140     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45141   },
45142 /* cmp.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
45143   {
45144     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 32,
45145     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45146   },
45147 /* cmp.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
45148   {
45149     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 32,
45150     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45151   },
45152 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
45153   {
45154     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 32,
45155     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45156   },
45157 /* cmp.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
45158   {
45159     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 32,
45160     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45161   },
45162 /* cmp.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
45163   {
45164     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 32,
45165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45166   },
45167 /* cmp.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
45168   {
45169     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 32,
45170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45171   },
45172 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
45173   {
45174     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 32,
45175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45176   },
45177 /* cmp.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
45178   {
45179     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 32,
45180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45181   },
45182 /* cmp.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
45183   {
45184     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 32,
45185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45186   },
45187 /* cmp.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
45188   {
45189     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 32,
45190     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45191   },
45192 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
45193   {
45194     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "cmp.b", 40,
45195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45196   },
45197 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
45198   {
45199     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "cmp.b", 40,
45200     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45201   },
45202 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
45203   {
45204     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "cmp.b", 40,
45205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45206   },
45207 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
45208   {
45209     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "cmp.b", 40,
45210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45211   },
45212 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
45213   {
45214     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "cmp.b", 48,
45215     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45216   },
45217 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
45218   {
45219     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "cmp.b", 48,
45220     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45221   },
45222 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
45223   {
45224     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "cmp.b", 48,
45225     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45226   },
45227 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
45228   {
45229     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "cmp.b", 48,
45230     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45231   },
45232 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
45233   {
45234     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "cmp.b", 56,
45235     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45236   },
45237 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
45238   {
45239     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "cmp.b", 56,
45240     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45241   },
45242 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
45243   {
45244     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "cmp.b", 56,
45245     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45246   },
45247 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
45248   {
45249     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "cmp.b", 56,
45250     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45251   },
45252 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
45253   {
45254     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "cmp.b", 40,
45255     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45256   },
45257 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
45258   {
45259     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "cmp.b", 40,
45260     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45261   },
45262 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
45263   {
45264     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "cmp.b", 40,
45265     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45266   },
45267 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
45268   {
45269     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "cmp.b", 40,
45270     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45271   },
45272 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
45273   {
45274     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "cmp.b", 48,
45275     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45276   },
45277 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
45278   {
45279     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "cmp.b", 48,
45280     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45281   },
45282 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
45283   {
45284     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "cmp.b", 48,
45285     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45286   },
45287 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
45288   {
45289     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "cmp.b", 48,
45290     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45291   },
45292 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
45293   {
45294     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "cmp.b", 40,
45295     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45296   },
45297 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
45298   {
45299     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "cmp.b", 40,
45300     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45301   },
45302 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
45303   {
45304     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "cmp.b", 40,
45305     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45306   },
45307 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
45308   {
45309     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "cmp.b", 40,
45310     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45311   },
45312 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
45313   {
45314     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "cmp.b", 48,
45315     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45316   },
45317 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
45318   {
45319     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "cmp.b", 48,
45320     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45321   },
45322 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
45323   {
45324     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "cmp.b", 48,
45325     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45326   },
45327 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
45328   {
45329     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "cmp.b", 48,
45330     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45331   },
45332 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
45333   {
45334     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "cmp.b", 48,
45335     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45336   },
45337 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
45338   {
45339     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "cmp.b", 48,
45340     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45341   },
45342 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
45343   {
45344     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "cmp.b", 48,
45345     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45346   },
45347 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
45348   {
45349     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "cmp.b", 48,
45350     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45351   },
45352 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
45353   {
45354     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "cmp.b", 56,
45355     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45356   },
45357 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
45358   {
45359     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "cmp.b", 56,
45360     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45361   },
45362 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
45363   {
45364     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "cmp.b", 56,
45365     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45366   },
45367 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
45368   {
45369     M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "cmp.b", 56,
45370     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45371   },
45372 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
45373   {
45374     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 40,
45375     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45376   },
45377 /* cmp.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
45378   {
45379     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 40,
45380     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45381   },
45382 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
45383   {
45384     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 40,
45385     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45386   },
45387 /* cmp.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
45388   {
45389     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 40,
45390     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45391   },
45392 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
45393   {
45394     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 40,
45395     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45396   },
45397 /* cmp.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
45398   {
45399     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 40,
45400     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45401   },
45402 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
45403   {
45404     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "cmp.b", 48,
45405     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45406   },
45407 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
45408   {
45409     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "cmp.b", 48,
45410     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45411   },
45412 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
45413   {
45414     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "cmp.b", 56,
45415     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45416   },
45417 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
45418   {
45419     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "cmp.b", 56,
45420     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45421   },
45422 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
45423   {
45424     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "cmp.b", 64,
45425     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45426   },
45427 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
45428   {
45429     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "cmp.b", 64,
45430     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45431   },
45432 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
45433   {
45434     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "cmp.b", 48,
45435     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45436   },
45437 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
45438   {
45439     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "cmp.b", 48,
45440     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45441   },
45442 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
45443   {
45444     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "cmp.b", 56,
45445     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45446   },
45447 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
45448   {
45449     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "cmp.b", 56,
45450     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45451   },
45452 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
45453   {
45454     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "cmp.b", 48,
45455     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45456   },
45457 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
45458   {
45459     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "cmp.b", 48,
45460     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45461   },
45462 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
45463   {
45464     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "cmp.b", 56,
45465     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45466   },
45467 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
45468   {
45469     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "cmp.b", 56,
45470     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45471   },
45472 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
45473   {
45474     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "cmp.b", 56,
45475     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45476   },
45477 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
45478   {
45479     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "cmp.b", 56,
45480     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45481   },
45482 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
45483   {
45484     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "cmp.b", 64,
45485     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45486   },
45487 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
45488   {
45489     M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "cmp.b", 64,
45490     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45491   },
45492 /* cmp.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
45493   {
45494     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 16,
45495     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45496   },
45497 /* cmp.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
45498   {
45499     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 16,
45500     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45501   },
45502 /* cmp.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
45503   {
45504     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 16,
45505     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45506   },
45507 /* cmp.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
45508   {
45509     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 16,
45510     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45511   },
45512 /* cmp.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
45513   {
45514     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 16,
45515     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45516   },
45517 /* cmp.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
45518   {
45519     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 16,
45520     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45521   },
45522 /* cmp.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
45523   {
45524     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 16,
45525     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45526   },
45527 /* cmp.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
45528   {
45529     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 16,
45530     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45531   },
45532 /* cmp.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
45533   {
45534     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 16,
45535     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45536   },
45537 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
45538   {
45539     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "cmp.b", 24,
45540     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45541   },
45542 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
45543   {
45544     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "cmp.b", 24,
45545     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45546   },
45547 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
45548   {
45549     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "cmp.b", 24,
45550     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45551   },
45552 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
45553   {
45554     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "cmp.b", 32,
45555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45556   },
45557 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
45558   {
45559     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "cmp.b", 32,
45560     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45561   },
45562 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
45563   {
45564     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "cmp.b", 32,
45565     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45566   },
45567 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
45568   {
45569     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "cmp.b", 40,
45570     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45571   },
45572 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
45573   {
45574     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "cmp.b", 40,
45575     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45576   },
45577 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
45578   {
45579     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "cmp.b", 40,
45580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45581   },
45582 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
45583   {
45584     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "cmp.b", 24,
45585     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45586   },
45587 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
45588   {
45589     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "cmp.b", 24,
45590     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45591   },
45592 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
45593   {
45594     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "cmp.b", 24,
45595     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45596   },
45597 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
45598   {
45599     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "cmp.b", 32,
45600     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45601   },
45602 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
45603   {
45604     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "cmp.b", 32,
45605     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45606   },
45607 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
45608   {
45609     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "cmp.b", 32,
45610     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45611   },
45612 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
45613   {
45614     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "cmp.b", 24,
45615     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45616   },
45617 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
45618   {
45619     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "cmp.b", 24,
45620     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45621   },
45622 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
45623   {
45624     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "cmp.b", 24,
45625     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45626   },
45627 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
45628   {
45629     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "cmp.b", 32,
45630     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45631   },
45632 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
45633   {
45634     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "cmp.b", 32,
45635     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45636   },
45637 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
45638   {
45639     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "cmp.b", 32,
45640     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45641   },
45642 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
45643   {
45644     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "cmp.b", 32,
45645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45646   },
45647 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
45648   {
45649     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "cmp.b", 32,
45650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45651   },
45652 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
45653   {
45654     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "cmp.b", 32,
45655     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45656   },
45657 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
45658   {
45659     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "cmp.b", 40,
45660     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45661   },
45662 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
45663   {
45664     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "cmp.b", 40,
45665     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45666   },
45667 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
45668   {
45669     M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "cmp.b", 40,
45670     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45671   },
45672 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
45673   {
45674     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "cmp.w", 24,
45675     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45676   },
45677 /* cmp.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
45678   {
45679     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "cmp.w", 24,
45680     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45681   },
45682 /* cmp.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
45683   {
45684     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "cmp.w", 24,
45685     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45686   },
45687 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
45688   {
45689     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "cmp.w", 24,
45690     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45691   },
45692 /* cmp.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
45693   {
45694     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "cmp.w", 24,
45695     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45696   },
45697 /* cmp.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
45698   {
45699     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "cmp.w", 24,
45700     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45701   },
45702 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
45703   {
45704     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "cmp.w", 24,
45705     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45706   },
45707 /* cmp.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
45708   {
45709     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "cmp.w", 24,
45710     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45711   },
45712 /* cmp.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
45713   {
45714     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "cmp.w", 24,
45715     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45716   },
45717 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
45718   {
45719     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "cmp.w", 32,
45720     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45721   },
45722 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
45723   {
45724     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "cmp.w", 32,
45725     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45726   },
45727 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
45728   {
45729     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "cmp.w", 32,
45730     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45731   },
45732 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
45733   {
45734     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "cmp.w", 40,
45735     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45736   },
45737 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
45738   {
45739     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "cmp.w", 40,
45740     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45741   },
45742 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
45743   {
45744     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "cmp.w", 40,
45745     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45746   },
45747 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
45748   {
45749     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "cmp.w", 32,
45750     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45751   },
45752 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
45753   {
45754     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "cmp.w", 32,
45755     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45756   },
45757 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
45758   {
45759     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "cmp.w", 32,
45760     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45761   },
45762 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
45763   {
45764     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "cmp.w", 40,
45765     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45766   },
45767 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
45768   {
45769     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "cmp.w", 40,
45770     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45771   },
45772 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
45773   {
45774     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "cmp.w", 40,
45775     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45776   },
45777 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
45778   {
45779     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "cmp.w", 32,
45780     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45781   },
45782 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
45783   {
45784     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "cmp.w", 32,
45785     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45786   },
45787 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
45788   {
45789     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "cmp.w", 32,
45790     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45791   },
45792 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
45793   {
45794     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "cmp.w", 40,
45795     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45796   },
45797 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
45798   {
45799     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "cmp.w", 40,
45800     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45801   },
45802 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
45803   {
45804     M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "cmp.w", 40,
45805     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45806   },
45807 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
45808   {
45809     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "cmp.w", 32,
45810     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45811   },
45812 /* cmp.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
45813   {
45814     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "cmp.w", 32,
45815     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45816   },
45817 /* cmp.w${G} ${Dsp-16-u16},$Dst16RnHI */
45818   {
45819     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "cmp.w", 32,
45820     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45821   },
45822 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
45823   {
45824     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "cmp.w", 32,
45825     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45826   },
45827 /* cmp.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
45828   {
45829     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "cmp.w", 32,
45830     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45831   },
45832 /* cmp.w${G} ${Dsp-16-u16},$Dst16AnHI */
45833   {
45834     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "cmp.w", 32,
45835     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45836   },
45837 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
45838   {
45839     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "cmp.w", 32,
45840     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45841   },
45842 /* cmp.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
45843   {
45844     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "cmp.w", 32,
45845     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45846   },
45847 /* cmp.w${G} ${Dsp-16-u16},[$Dst16An] */
45848   {
45849     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "cmp.w", 32,
45850     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45851   },
45852 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
45853   {
45854     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "cmp.w", 40,
45855     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45856   },
45857 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
45858   {
45859     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "cmp.w", 40,
45860     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45861   },
45862 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
45863   {
45864     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "cmp.w", 40,
45865     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45866   },
45867 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
45868   {
45869     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "cmp.w", 48,
45870     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45871   },
45872 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
45873   {
45874     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "cmp.w", 48,
45875     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45876   },
45877 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
45878   {
45879     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "cmp.w", 48,
45880     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45881   },
45882 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
45883   {
45884     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "cmp.w", 40,
45885     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45886   },
45887 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
45888   {
45889     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "cmp.w", 40,
45890     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45891   },
45892 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
45893   {
45894     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "cmp.w", 40,
45895     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45896   },
45897 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
45898   {
45899     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "cmp.w", 48,
45900     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45901   },
45902 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
45903   {
45904     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "cmp.w", 48,
45905     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45906   },
45907 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
45908   {
45909     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "cmp.w", 48,
45910     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45911   },
45912 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
45913   {
45914     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "cmp.w", 40,
45915     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45916   },
45917 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
45918   {
45919     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "cmp.w", 40,
45920     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45921   },
45922 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
45923   {
45924     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "cmp.w", 40,
45925     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45926   },
45927 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
45928   {
45929     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "cmp.w", 48,
45930     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45931   },
45932 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
45933   {
45934     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "cmp.w", 48,
45935     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45936   },
45937 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
45938   {
45939     M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "cmp.w", 48,
45940     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45941   },
45942 /* cmp.w${G} $Src16RnHI,$Dst16RnHI */
45943   {
45944     M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "cmp.w", 16,
45945     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45946   },
45947 /* cmp.w${G} $Src16AnHI,$Dst16RnHI */
45948   {
45949     M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "cmp.w", 16,
45950     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45951   },
45952 /* cmp.w${G} [$Src16An],$Dst16RnHI */
45953   {
45954     M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "cmp.w", 16,
45955     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45956   },
45957 /* cmp.w${G} $Src16RnHI,$Dst16AnHI */
45958   {
45959     M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "cmp.w", 16,
45960     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45961   },
45962 /* cmp.w${G} $Src16AnHI,$Dst16AnHI */
45963   {
45964     M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "cmp.w", 16,
45965     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45966   },
45967 /* cmp.w${G} [$Src16An],$Dst16AnHI */
45968   {
45969     M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "cmp.w", 16,
45970     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45971   },
45972 /* cmp.w${G} $Src16RnHI,[$Dst16An] */
45973   {
45974     M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "cmp.w", 16,
45975     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45976   },
45977 /* cmp.w${G} $Src16AnHI,[$Dst16An] */
45978   {
45979     M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "cmp.w", 16,
45980     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45981   },
45982 /* cmp.w${G} [$Src16An],[$Dst16An] */
45983   {
45984     M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "cmp.w", 16,
45985     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45986   },
45987 /* cmp.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
45988   {
45989     M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "cmp.w", 24,
45990     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45991   },
45992 /* cmp.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
45993   {
45994     M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "cmp.w", 24,
45995     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45996   },
45997 /* cmp.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
45998   {
45999     M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "cmp.w", 24,
46000     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46001   },
46002 /* cmp.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
46003   {
46004     M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "cmp.w", 32,
46005     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46006   },
46007 /* cmp.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
46008   {
46009     M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "cmp.w", 32,
46010     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46011   },
46012 /* cmp.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
46013   {
46014     M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "cmp.w", 32,
46015     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46016   },
46017 /* cmp.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
46018   {
46019     M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "cmp.w", 24,
46020     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46021   },
46022 /* cmp.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
46023   {
46024     M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "cmp.w", 24,
46025     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46026   },
46027 /* cmp.w${G} [$Src16An],${Dsp-16-u8}[sb] */
46028   {
46029     M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "cmp.w", 24,
46030     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46031   },
46032 /* cmp.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
46033   {
46034     M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "cmp.w", 32,
46035     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46036   },
46037 /* cmp.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
46038   {
46039     M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "cmp.w", 32,
46040     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46041   },
46042 /* cmp.w${G} [$Src16An],${Dsp-16-u16}[sb] */
46043   {
46044     M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "cmp.w", 32,
46045     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46046   },
46047 /* cmp.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
46048   {
46049     M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "cmp.w", 24,
46050     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46051   },
46052 /* cmp.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
46053   {
46054     M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "cmp.w", 24,
46055     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46056   },
46057 /* cmp.w${G} [$Src16An],${Dsp-16-s8}[fb] */
46058   {
46059     M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "cmp.w", 24,
46060     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46061   },
46062 /* cmp.w${G} $Src16RnHI,${Dsp-16-u16} */
46063   {
46064     M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "cmp.w", 32,
46065     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46066   },
46067 /* cmp.w${G} $Src16AnHI,${Dsp-16-u16} */
46068   {
46069     M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "cmp.w", 32,
46070     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46071   },
46072 /* cmp.w${G} [$Src16An],${Dsp-16-u16} */
46073   {
46074     M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "cmp.w", 32,
46075     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46076   },
46077 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
46078   {
46079     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "cmp.b", 24,
46080     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46081   },
46082 /* cmp.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
46083   {
46084     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "cmp.b", 24,
46085     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46086   },
46087 /* cmp.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
46088   {
46089     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "cmp.b", 24,
46090     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46091   },
46092 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
46093   {
46094     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "cmp.b", 24,
46095     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46096   },
46097 /* cmp.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
46098   {
46099     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "cmp.b", 24,
46100     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46101   },
46102 /* cmp.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
46103   {
46104     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "cmp.b", 24,
46105     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46106   },
46107 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
46108   {
46109     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "cmp.b", 24,
46110     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46111   },
46112 /* cmp.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
46113   {
46114     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "cmp.b", 24,
46115     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46116   },
46117 /* cmp.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
46118   {
46119     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "cmp.b", 24,
46120     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46121   },
46122 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
46123   {
46124     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "cmp.b", 32,
46125     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46126   },
46127 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
46128   {
46129     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "cmp.b", 32,
46130     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46131   },
46132 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
46133   {
46134     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "cmp.b", 32,
46135     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46136   },
46137 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
46138   {
46139     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "cmp.b", 40,
46140     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46141   },
46142 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
46143   {
46144     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "cmp.b", 40,
46145     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46146   },
46147 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
46148   {
46149     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "cmp.b", 40,
46150     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46151   },
46152 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
46153   {
46154     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "cmp.b", 32,
46155     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46156   },
46157 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
46158   {
46159     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "cmp.b", 32,
46160     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46161   },
46162 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
46163   {
46164     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "cmp.b", 32,
46165     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46166   },
46167 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
46168   {
46169     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "cmp.b", 40,
46170     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46171   },
46172 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
46173   {
46174     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "cmp.b", 40,
46175     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46176   },
46177 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
46178   {
46179     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "cmp.b", 40,
46180     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46181   },
46182 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
46183   {
46184     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "cmp.b", 32,
46185     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46186   },
46187 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
46188   {
46189     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "cmp.b", 32,
46190     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46191   },
46192 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
46193   {
46194     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "cmp.b", 32,
46195     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46196   },
46197 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
46198   {
46199     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "cmp.b", 40,
46200     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46201   },
46202 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
46203   {
46204     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "cmp.b", 40,
46205     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46206   },
46207 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
46208   {
46209     M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "cmp.b", 40,
46210     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46211   },
46212 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
46213   {
46214     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "cmp.b", 32,
46215     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46216   },
46217 /* cmp.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
46218   {
46219     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "cmp.b", 32,
46220     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46221   },
46222 /* cmp.b${G} ${Dsp-16-u16},$Dst16RnQI */
46223   {
46224     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "cmp.b", 32,
46225     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46226   },
46227 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
46228   {
46229     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "cmp.b", 32,
46230     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46231   },
46232 /* cmp.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
46233   {
46234     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "cmp.b", 32,
46235     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46236   },
46237 /* cmp.b${G} ${Dsp-16-u16},$Dst16AnQI */
46238   {
46239     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "cmp.b", 32,
46240     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46241   },
46242 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
46243   {
46244     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "cmp.b", 32,
46245     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46246   },
46247 /* cmp.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
46248   {
46249     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "cmp.b", 32,
46250     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46251   },
46252 /* cmp.b${G} ${Dsp-16-u16},[$Dst16An] */
46253   {
46254     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "cmp.b", 32,
46255     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46256   },
46257 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
46258   {
46259     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "cmp.b", 40,
46260     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46261   },
46262 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
46263   {
46264     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "cmp.b", 40,
46265     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46266   },
46267 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
46268   {
46269     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "cmp.b", 40,
46270     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46271   },
46272 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
46273   {
46274     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "cmp.b", 48,
46275     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46276   },
46277 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
46278   {
46279     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "cmp.b", 48,
46280     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46281   },
46282 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
46283   {
46284     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "cmp.b", 48,
46285     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46286   },
46287 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
46288   {
46289     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "cmp.b", 40,
46290     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46291   },
46292 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
46293   {
46294     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "cmp.b", 40,
46295     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46296   },
46297 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
46298   {
46299     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "cmp.b", 40,
46300     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46301   },
46302 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
46303   {
46304     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "cmp.b", 48,
46305     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46306   },
46307 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
46308   {
46309     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "cmp.b", 48,
46310     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46311   },
46312 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
46313   {
46314     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "cmp.b", 48,
46315     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46316   },
46317 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
46318   {
46319     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "cmp.b", 40,
46320     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46321   },
46322 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
46323   {
46324     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "cmp.b", 40,
46325     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46326   },
46327 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
46328   {
46329     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "cmp.b", 40,
46330     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46331   },
46332 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
46333   {
46334     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "cmp.b", 48,
46335     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46336   },
46337 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
46338   {
46339     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "cmp.b", 48,
46340     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46341   },
46342 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
46343   {
46344     M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "cmp.b", 48,
46345     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46346   },
46347 /* cmp.b${G} $Src16RnQI,$Dst16RnQI */
46348   {
46349     M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "cmp.b", 16,
46350     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46351   },
46352 /* cmp.b${G} $Src16AnQI,$Dst16RnQI */
46353   {
46354     M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "cmp.b", 16,
46355     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46356   },
46357 /* cmp.b${G} [$Src16An],$Dst16RnQI */
46358   {
46359     M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "cmp.b", 16,
46360     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46361   },
46362 /* cmp.b${G} $Src16RnQI,$Dst16AnQI */
46363   {
46364     M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "cmp.b", 16,
46365     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46366   },
46367 /* cmp.b${G} $Src16AnQI,$Dst16AnQI */
46368   {
46369     M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "cmp.b", 16,
46370     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46371   },
46372 /* cmp.b${G} [$Src16An],$Dst16AnQI */
46373   {
46374     M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "cmp.b", 16,
46375     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46376   },
46377 /* cmp.b${G} $Src16RnQI,[$Dst16An] */
46378   {
46379     M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "cmp.b", 16,
46380     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46381   },
46382 /* cmp.b${G} $Src16AnQI,[$Dst16An] */
46383   {
46384     M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "cmp.b", 16,
46385     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46386   },
46387 /* cmp.b${G} [$Src16An],[$Dst16An] */
46388   {
46389     M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "cmp.b", 16,
46390     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46391   },
46392 /* cmp.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
46393   {
46394     M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "cmp.b", 24,
46395     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46396   },
46397 /* cmp.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
46398   {
46399     M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "cmp.b", 24,
46400     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46401   },
46402 /* cmp.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
46403   {
46404     M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "cmp.b", 24,
46405     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46406   },
46407 /* cmp.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
46408   {
46409     M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "cmp.b", 32,
46410     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46411   },
46412 /* cmp.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
46413   {
46414     M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "cmp.b", 32,
46415     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46416   },
46417 /* cmp.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
46418   {
46419     M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "cmp.b", 32,
46420     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46421   },
46422 /* cmp.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
46423   {
46424     M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "cmp.b", 24,
46425     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46426   },
46427 /* cmp.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
46428   {
46429     M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "cmp.b", 24,
46430     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46431   },
46432 /* cmp.b${G} [$Src16An],${Dsp-16-u8}[sb] */
46433   {
46434     M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "cmp.b", 24,
46435     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46436   },
46437 /* cmp.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
46438   {
46439     M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "cmp.b", 32,
46440     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46441   },
46442 /* cmp.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
46443   {
46444     M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "cmp.b", 32,
46445     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46446   },
46447 /* cmp.b${G} [$Src16An],${Dsp-16-u16}[sb] */
46448   {
46449     M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "cmp.b", 32,
46450     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46451   },
46452 /* cmp.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
46453   {
46454     M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "cmp.b", 24,
46455     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46456   },
46457 /* cmp.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
46458   {
46459     M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "cmp.b", 24,
46460     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46461   },
46462 /* cmp.b${G} [$Src16An],${Dsp-16-s8}[fb] */
46463   {
46464     M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "cmp.b", 24,
46465     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46466   },
46467 /* cmp.b${G} $Src16RnQI,${Dsp-16-u16} */
46468   {
46469     M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "cmp.b", 32,
46470     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46471   },
46472 /* cmp.b${G} $Src16AnQI,${Dsp-16-u16} */
46473   {
46474     M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "cmp.b", 32,
46475     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46476   },
46477 /* cmp.b${G} [$Src16An],${Dsp-16-u16} */
46478   {
46479     M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "cmp.b", 32,
46480     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46481   },
46482 /* cmp.b${S} #${Imm-8-QI},r0l */
46483   {
46484     M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "cmp16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "cmp.b", 16,
46485     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46486   },
46487 /* cmp.b${S} #${Imm-8-QI},r0h */
46488   {
46489     M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "cmp16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "cmp.b", 16,
46490     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46491   },
46492 /* cmp.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
46493   {
46494     M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "cmp16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "cmp.b", 24,
46495     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46496   },
46497 /* cmp.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
46498   {
46499     M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "cmp16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "cmp.b", 24,
46500     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46501   },
46502 /* cmp.b${S} #${Imm-8-QI},${Dsp-16-u16} */
46503   {
46504     M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "cmp16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "cmp.b", 32,
46505     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46506   },
46507 /* cmp.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */
46508   {
46509     M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 16,
46510     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46511   },
46512 /* cmp.w${Q} #${Imm-12-s4},$Dst32AnUnprefixedHI */
46513   {
46514     M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "cmp.w", 16,
46515     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46516   },
46517 /* cmp.w${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
46518   {
46519     M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "cmp.w", 16,
46520     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46521   },
46522 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
46523   {
46524     M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "cmp.w", 24,
46525     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46526   },
46527 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
46528   {
46529     M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "cmp.w", 32,
46530     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46531   },
46532 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
46533   {
46534     M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "cmp.w", 40,
46535     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46536   },
46537 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
46538   {
46539     M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "cmp.w", 24,
46540     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46541   },
46542 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
46543   {
46544     M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "cmp.w", 32,
46545     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46546   },
46547 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
46548   {
46549     M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "cmp.w", 24,
46550     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46551   },
46552 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
46553   {
46554     M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "cmp.w", 32,
46555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46556   },
46557 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u16} */
46558   {
46559     M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "cmp.w", 32,
46560     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46561   },
46562 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u24} */
46563   {
46564     M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "cmp.w", 40,
46565     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46566   },
46567 /* cmp.b${Q} #${Imm-12-s4},$Dst32RnUnprefixedQI */
46568   {
46569     M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 16,
46570     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46571   },
46572 /* cmp.b${Q} #${Imm-12-s4},$Dst32AnUnprefixedQI */
46573   {
46574     M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "cmp.b", 16,
46575     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46576   },
46577 /* cmp.b${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
46578   {
46579     M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "cmp.b", 16,
46580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46581   },
46582 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
46583   {
46584     M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "cmp.b", 24,
46585     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46586   },
46587 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
46588   {
46589     M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "cmp.b", 32,
46590     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46591   },
46592 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
46593   {
46594     M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "cmp.b", 40,
46595     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46596   },
46597 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
46598   {
46599     M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "cmp.b", 24,
46600     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46601   },
46602 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
46603   {
46604     M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "cmp.b", 32,
46605     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46606   },
46607 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
46608   {
46609     M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "cmp.b", 24,
46610     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46611   },
46612 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
46613   {
46614     M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "cmp.b", 32,
46615     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46616   },
46617 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u16} */
46618   {
46619     M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "cmp.b", 32,
46620     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46621   },
46622 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u24} */
46623   {
46624     M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "cmp.b", 40,
46625     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46626   },
46627 /* cmp.w${Q} #${Imm-8-s4},$Dst16RnHI */
46628   {
46629     M32C_INSN_CMP16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "cmp16.w-imm4-Q-16-dst16-Rn-direct-HI", "cmp.w", 16,
46630     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46631   },
46632 /* cmp.w${Q} #${Imm-8-s4},$Dst16AnHI */
46633   {
46634     M32C_INSN_CMP16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "cmp16.w-imm4-Q-16-dst16-An-direct-HI", "cmp.w", 16,
46635     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46636   },
46637 /* cmp.w${Q} #${Imm-8-s4},[$Dst16An] */
46638   {
46639     M32C_INSN_CMP16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "cmp16.w-imm4-Q-16-dst16-An-indirect-HI", "cmp.w", 16,
46640     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46641   },
46642 /* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
46643   {
46644     M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "cmp16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "cmp.w", 24,
46645     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46646   },
46647 /* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
46648   {
46649     M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "cmp16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "cmp.w", 32,
46650     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46651   },
46652 /* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
46653   {
46654     M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "cmp16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "cmp.w", 24,
46655     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46656   },
46657 /* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
46658   {
46659     M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "cmp16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "cmp.w", 32,
46660     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46661   },
46662 /* cmp.w${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
46663   {
46664     M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "cmp16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "cmp.w", 24,
46665     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46666   },
46667 /* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u16} */
46668   {
46669     M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "cmp16.w-imm4-Q-16-dst16-16-16-absolute-HI", "cmp.w", 32,
46670     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46671   },
46672 /* cmp.b${Q} #${Imm-8-s4},$Dst16RnQI */
46673   {
46674     M32C_INSN_CMP16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "cmp16.b-imm4-Q-16-dst16-Rn-direct-QI", "cmp.b", 16,
46675     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46676   },
46677 /* cmp.b${Q} #${Imm-8-s4},$Dst16AnQI */
46678   {
46679     M32C_INSN_CMP16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "cmp16.b-imm4-Q-16-dst16-An-direct-QI", "cmp.b", 16,
46680     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46681   },
46682 /* cmp.b${Q} #${Imm-8-s4},[$Dst16An] */
46683   {
46684     M32C_INSN_CMP16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "cmp16.b-imm4-Q-16-dst16-An-indirect-QI", "cmp.b", 16,
46685     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46686   },
46687 /* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
46688   {
46689     M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "cmp16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "cmp.b", 24,
46690     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46691   },
46692 /* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
46693   {
46694     M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "cmp16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "cmp.b", 32,
46695     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46696   },
46697 /* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
46698   {
46699     M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "cmp16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "cmp.b", 24,
46700     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46701   },
46702 /* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
46703   {
46704     M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "cmp16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "cmp.b", 32,
46705     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46706   },
46707 /* cmp.b${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
46708   {
46709     M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "cmp16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "cmp.b", 24,
46710     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46711   },
46712 /* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u16} */
46713   {
46714     M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "cmp16.b-imm4-Q-16-dst16-16-16-absolute-QI", "cmp.b", 32,
46715     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46716   },
46717 /* cmp.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
46718   {
46719     M32C_INSN_CMP32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 32,
46720     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46721   },
46722 /* cmp.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
46723   {
46724     M32C_INSN_CMP32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "cmp.w", 32,
46725     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46726   },
46727 /* cmp.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
46728   {
46729     M32C_INSN_CMP32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "cmp.w", 32,
46730     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46731   },
46732 /* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
46733   {
46734     M32C_INSN_CMP32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "cmp.w", 40,
46735     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46736   },
46737 /* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
46738   {
46739     M32C_INSN_CMP32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "cmp.w", 40,
46740     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46741   },
46742 /* cmp.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
46743   {
46744     M32C_INSN_CMP32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "cmp.w", 40,
46745     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46746   },
46747 /* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
46748   {
46749     M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "cmp.w", 48,
46750     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46751   },
46752 /* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
46753   {
46754     M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "cmp.w", 48,
46755     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46756   },
46757 /* cmp.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
46758   {
46759     M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "cmp.w", 48,
46760     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46761   },
46762 /* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16} */
46763   {
46764     M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "cmp.w", 48,
46765     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46766   },
46767 /* cmp.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
46768   {
46769     M32C_INSN_CMP32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "cmp.w", 56,
46770     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46771   },
46772 /* cmp.w${G} #${Imm-40-HI},${Dsp-16-u24} */
46773   {
46774     M32C_INSN_CMP32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "cmp.w", 56,
46775     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46776   },
46777 /* cmp.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
46778   {
46779     M32C_INSN_CMP32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 24,
46780     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46781   },
46782 /* cmp.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
46783   {
46784     M32C_INSN_CMP32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "cmp.b", 24,
46785     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46786   },
46787 /* cmp.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
46788   {
46789     M32C_INSN_CMP32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "cmp.b", 24,
46790     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46791   },
46792 /* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
46793   {
46794     M32C_INSN_CMP32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "cmp.b", 32,
46795     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46796   },
46797 /* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
46798   {
46799     M32C_INSN_CMP32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "cmp.b", 32,
46800     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46801   },
46802 /* cmp.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
46803   {
46804     M32C_INSN_CMP32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "cmp.b", 32,
46805     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46806   },
46807 /* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
46808   {
46809     M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "cmp.b", 40,
46810     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46811   },
46812 /* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
46813   {
46814     M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "cmp.b", 40,
46815     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46816   },
46817 /* cmp.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
46818   {
46819     M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "cmp.b", 40,
46820     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46821   },
46822 /* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16} */
46823   {
46824     M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "cmp.b", 40,
46825     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46826   },
46827 /* cmp.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
46828   {
46829     M32C_INSN_CMP32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "cmp.b", 48,
46830     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46831   },
46832 /* cmp.b${G} #${Imm-40-QI},${Dsp-16-u24} */
46833   {
46834     M32C_INSN_CMP32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "cmp.b", 48,
46835     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46836   },
46837 /* cmp.w${G} #${Imm-16-HI},$Dst16RnHI */
46838   {
46839     M32C_INSN_CMP16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "cmp16.w-imm-G-basic-dst16-Rn-direct-HI", "cmp.w", 32,
46840     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46841   },
46842 /* cmp.w${G} #${Imm-16-HI},$Dst16AnHI */
46843   {
46844     M32C_INSN_CMP16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "cmp16.w-imm-G-basic-dst16-An-direct-HI", "cmp.w", 32,
46845     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46846   },
46847 /* cmp.w${G} #${Imm-16-HI},[$Dst16An] */
46848   {
46849     M32C_INSN_CMP16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "cmp16.w-imm-G-basic-dst16-An-indirect-HI", "cmp.w", 32,
46850     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46851   },
46852 /* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
46853   {
46854     M32C_INSN_CMP16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "cmp16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "cmp.w", 40,
46855     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46856   },
46857 /* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
46858   {
46859     M32C_INSN_CMP16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "cmp16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "cmp.w", 40,
46860     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46861   },
46862 /* cmp.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
46863   {
46864     M32C_INSN_CMP16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "cmp16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "cmp.w", 40,
46865     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46866   },
46867 /* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
46868   {
46869     M32C_INSN_CMP16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "cmp16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "cmp.w", 48,
46870     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46871   },
46872 /* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
46873   {
46874     M32C_INSN_CMP16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "cmp16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "cmp.w", 48,
46875     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46876   },
46877 /* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16} */
46878   {
46879     M32C_INSN_CMP16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "cmp16.w-imm-G-16-16-dst16-16-16-absolute-HI", "cmp.w", 48,
46880     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46881   },
46882 /* cmp.b${G} #${Imm-16-QI},$Dst16RnQI */
46883   {
46884     M32C_INSN_CMP16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "cmp16.b-imm-G-basic-dst16-Rn-direct-QI", "cmp.b", 24,
46885     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46886   },
46887 /* cmp.b${G} #${Imm-16-QI},$Dst16AnQI */
46888   {
46889     M32C_INSN_CMP16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "cmp16.b-imm-G-basic-dst16-An-direct-QI", "cmp.b", 24,
46890     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46891   },
46892 /* cmp.b${G} #${Imm-16-QI},[$Dst16An] */
46893   {
46894     M32C_INSN_CMP16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "cmp16.b-imm-G-basic-dst16-An-indirect-QI", "cmp.b", 24,
46895     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46896   },
46897 /* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
46898   {
46899     M32C_INSN_CMP16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "cmp16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "cmp.b", 32,
46900     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46901   },
46902 /* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
46903   {
46904     M32C_INSN_CMP16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "cmp16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "cmp.b", 32,
46905     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46906   },
46907 /* cmp.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
46908   {
46909     M32C_INSN_CMP16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "cmp16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "cmp.b", 32,
46910     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46911   },
46912 /* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
46913   {
46914     M32C_INSN_CMP16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "cmp16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "cmp.b", 40,
46915     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46916   },
46917 /* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
46918   {
46919     M32C_INSN_CMP16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "cmp16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "cmp.b", 40,
46920     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46921   },
46922 /* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16} */
46923   {
46924     M32C_INSN_CMP16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "cmp16.b-imm-G-16-16-dst16-16-16-absolute-QI", "cmp.b", 40,
46925     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46926   },
46927 /* cmp.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */
46928   {
46929     M32C_INSN_CMP32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 48,
46930     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46931   },
46932 /* cmp.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */
46933   {
46934     M32C_INSN_CMP32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "cmp.l", 48,
46935     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46936   },
46937 /* cmp.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */
46938   {
46939     M32C_INSN_CMP32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "cmp.l", 48,
46940     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46941   },
46942 /* cmp.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
46943   {
46944     M32C_INSN_CMP32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "cmp.l", 56,
46945     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46946   },
46947 /* cmp.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */
46948   {
46949     M32C_INSN_CMP32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "cmp.l", 56,
46950     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46951   },
46952 /* cmp.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */
46953   {
46954     M32C_INSN_CMP32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "cmp.l", 56,
46955     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46956   },
46957 /* cmp.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
46958   {
46959     M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "cmp.l", 64,
46960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46961   },
46962 /* cmp.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */
46963   {
46964     M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "cmp.l", 64,
46965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46966   },
46967 /* cmp.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */
46968   {
46969     M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "cmp.l", 64,
46970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46971   },
46972 /* cmp.l${G} #${Imm-32-SI},${Dsp-16-u16} */
46973   {
46974     M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "cmp.l", 64,
46975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46976   },
46977 /* cmp.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
46978   {
46979     M32C_INSN_CMP32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "cmp.l", 72,
46980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46981   },
46982 /* cmp.l${G} #${Imm-40-SI},${Dsp-16-u24} */
46983   {
46984     M32C_INSN_CMP32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "cmp.l", 72,
46985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46986   },
46987 /* clip.w #${Imm-24-HI},#${Imm-40-HI},$Dst32RnPrefixedHI */
46988   {
46989     M32C_INSN_CLIP32_W_IMM_24_HI_IMM_40_HI_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "clip32.w-Imm-24-HI-Imm-40-HI-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "clip.w", 56,
46990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46991   },
46992 /* clip.w #${Imm-24-HI},#${Imm-40-HI},$Dst32AnPrefixedHI */
46993   {
46994     M32C_INSN_CLIP32_W_IMM_24_HI_IMM_40_HI_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "clip32.w-Imm-24-HI-Imm-40-HI-basic-Prefixed-dst32-An-direct-Prefixed-HI", "clip.w", 56,
46995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46996   },
46997 /* clip.w #${Imm-24-HI},#${Imm-40-HI},[$Dst32AnPrefixed] */
46998   {
46999     M32C_INSN_CLIP32_W_IMM_24_HI_IMM_40_HI_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "clip32.w-Imm-24-HI-Imm-40-HI-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "clip.w", 56,
47000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47001   },
47002 /* clip.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
47003   {
47004     M32C_INSN_CLIP32_W_IMM_32_HI_IMM_48_HI_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "clip32.w-Imm-32-HI-Imm-48-HI-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "clip.w", 64,
47005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47006   },
47007 /* clip.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-24-u8}[sb] */
47008   {
47009     M32C_INSN_CLIP32_W_IMM_32_HI_IMM_48_HI_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "clip32.w-Imm-32-HI-Imm-48-HI-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "clip.w", 64,
47010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47011   },
47012 /* clip.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-24-s8}[fb] */
47013   {
47014     M32C_INSN_CLIP32_W_IMM_32_HI_IMM_48_HI_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "clip32.w-Imm-32-HI-Imm-48-HI-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "clip.w", 64,
47015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47016   },
47017 /* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
47018   {
47019     M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "clip32.w-Imm-40-HI-Imm-56-HI-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "clip.w", 72,
47020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47021   },
47022 /* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-u16}[sb] */
47023   {
47024     M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "clip32.w-Imm-40-HI-Imm-56-HI-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "clip.w", 72,
47025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47026   },
47027 /* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-s16}[fb] */
47028   {
47029     M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "clip32.w-Imm-40-HI-Imm-56-HI-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "clip.w", 72,
47030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47031   },
47032 /* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-u16} */
47033   {
47034     M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "clip32.w-Imm-40-HI-Imm-56-HI-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "clip.w", 72,
47035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47036   },
47037 /* clip.w #${Imm-48-HI},#${Imm-64-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
47038   {
47039     M32C_INSN_CLIP32_W_IMM_48_HI_IMM_64_HI_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "clip32.w-Imm-48-HI-Imm-64-HI-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "clip.w", 80,
47040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47041   },
47042 /* clip.w #${Imm-48-HI},#${Imm-64-HI},${Dsp-24-u24} */
47043   {
47044     M32C_INSN_CLIP32_W_IMM_48_HI_IMM_64_HI_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "clip32.w-Imm-48-HI-Imm-64-HI-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "clip.w", 80,
47045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47046   },
47047 /* clip.b #${Imm-24-QI},#${Imm-32-QI},$Dst32RnPrefixedQI */
47048   {
47049     M32C_INSN_CLIP32_B_IMM_24_QI_IMM_32_QI_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "clip32.b-Imm-24-QI-Imm-32-QI-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "clip.b", 40,
47050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47051   },
47052 /* clip.b #${Imm-24-QI},#${Imm-32-QI},$Dst32AnPrefixedQI */
47053   {
47054     M32C_INSN_CLIP32_B_IMM_24_QI_IMM_32_QI_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "clip32.b-Imm-24-QI-Imm-32-QI-basic-Prefixed-dst32-An-direct-Prefixed-QI", "clip.b", 40,
47055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47056   },
47057 /* clip.b #${Imm-24-QI},#${Imm-32-QI},[$Dst32AnPrefixed] */
47058   {
47059     M32C_INSN_CLIP32_B_IMM_24_QI_IMM_32_QI_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "clip32.b-Imm-24-QI-Imm-32-QI-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "clip.b", 40,
47060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47061   },
47062 /* clip.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
47063   {
47064     M32C_INSN_CLIP32_B_IMM_32_QI_IMM_40_QI_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "clip32.b-Imm-32-QI-Imm-40-QI-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "clip.b", 48,
47065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47066   },
47067 /* clip.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-24-u8}[sb] */
47068   {
47069     M32C_INSN_CLIP32_B_IMM_32_QI_IMM_40_QI_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "clip32.b-Imm-32-QI-Imm-40-QI-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "clip.b", 48,
47070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47071   },
47072 /* clip.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-24-s8}[fb] */
47073   {
47074     M32C_INSN_CLIP32_B_IMM_32_QI_IMM_40_QI_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "clip32.b-Imm-32-QI-Imm-40-QI-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "clip.b", 48,
47075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47076   },
47077 /* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
47078   {
47079     M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "clip32.b-Imm-40-QI-Imm-48-QI-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "clip.b", 56,
47080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47081   },
47082 /* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-u16}[sb] */
47083   {
47084     M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "clip32.b-Imm-40-QI-Imm-48-QI-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "clip.b", 56,
47085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47086   },
47087 /* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-s16}[fb] */
47088   {
47089     M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "clip32.b-Imm-40-QI-Imm-48-QI-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "clip.b", 56,
47090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47091   },
47092 /* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-u16} */
47093   {
47094     M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "clip32.b-Imm-40-QI-Imm-48-QI-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "clip.b", 56,
47095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47096   },
47097 /* clip.b #${Imm-48-QI},#${Imm-56-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
47098   {
47099     M32C_INSN_CLIP32_B_IMM_48_QI_IMM_56_QI_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "clip32.b-Imm-48-QI-Imm-56-QI-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "clip.b", 64,
47100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47101   },
47102 /* clip.b #${Imm-48-QI},#${Imm-56-QI},${Dsp-24-u24} */
47103   {
47104     M32C_INSN_CLIP32_B_IMM_48_QI_IMM_56_QI_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "clip32.b-Imm-48-QI-Imm-56-QI-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "clip.b", 64,
47105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47106   },
47107 /* bxor${X} $Bitno32Prefixed,$Bit32RnPrefixed */
47108   {
47109     M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bxor", 24,
47110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47111   },
47112 /* bxor${X} $Bitno32Prefixed,$Bit32AnPrefixed */
47113   {
47114     M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bxor", 24,
47115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47116   },
47117 /* bxor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
47118   {
47119     M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bxor", 24,
47120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47121   },
47122 /* bxor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
47123   {
47124     M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bxor", 32,
47125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47126   },
47127 /* bxor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
47128   {
47129     M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bxor", 40,
47130     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47131   },
47132 /* bxor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
47133   {
47134     M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bxor", 48,
47135     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47136   },
47137 /* bxor${X} ${BitBase32-24-u11-Prefixed}[sb] */
47138   {
47139     M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bxor", 32,
47140     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47141   },
47142 /* bxor${X} ${BitBase32-24-u19-Prefixed}[sb] */
47143   {
47144     M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bxor", 40,
47145     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47146   },
47147 /* bxor${X} ${BitBase32-24-s11-Prefixed}[fb] */
47148   {
47149     M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bxor", 32,
47150     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47151   },
47152 /* bxor${X} ${BitBase32-24-s19-Prefixed}[fb] */
47153   {
47154     M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bxor", 40,
47155     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47156   },
47157 /* bxor${X} ${BitBase32-24-u19-Prefixed} */
47158   {
47159     M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bxor", 40,
47160     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47161   },
47162 /* bxor${X} ${BitBase32-24-u27-Prefixed} */
47163   {
47164     M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bxor", 48,
47165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47166   },
47167 /* bxor${X} $Bitno16R,$Bit16Rn */
47168   {
47169     M32C_INSN_BXOR16_X_BIT16_16_BIT16_RN_DIRECT, "bxor16-X-bit16-16-bit16-Rn-direct", "bxor", 24,
47170     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47171   },
47172 /* bxor${X} $Bitno16R,$Bit16An */
47173   {
47174     M32C_INSN_BXOR16_X_BIT16_16_BIT16_AN_DIRECT, "bxor16-X-bit16-16-bit16-An-direct", "bxor", 24,
47175     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47176   },
47177 /* bxor${X} [$Bit16An] */
47178   {
47179     M32C_INSN_BXOR16_X_BIT16_16_BIT16_AN_INDIRECT, "bxor16-X-bit16-16-bit16-An-indirect", "bxor", 16,
47180     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47181   },
47182 /* bxor${X} ${Dsp-16-u8}[$Bit16An] */
47183   {
47184     M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bxor16-X-bit16-16-bit16-16-8-An-relative", "bxor", 24,
47185     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47186   },
47187 /* bxor${X} ${Dsp-16-u16}[$Bit16An] */
47188   {
47189     M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bxor16-X-bit16-16-bit16-16-16-An-relative", "bxor", 32,
47190     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47191   },
47192 /* bxor${X} ${BitBase16-16-u8}[sb] */
47193   {
47194     M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bxor16-X-bit16-16-bit16-16-8-SB-relative", "bxor", 24,
47195     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47196   },
47197 /* bxor${X} ${BitBase16-16-u16}[sb] */
47198   {
47199     M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bxor16-X-bit16-16-bit16-16-16-SB-relative", "bxor", 32,
47200     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47201   },
47202 /* bxor${X} ${BitBase16-16-s8}[fb] */
47203   {
47204     M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bxor16-X-bit16-16-bit16-16-8-FB-relative", "bxor", 24,
47205     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47206   },
47207 /* bxor${X} ${BitBase16-16-u16} */
47208   {
47209     M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bxor16-X-bit16-16-bit16-16-16-absolute", "bxor", 32,
47210     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47211   },
47212 /* btsts${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
47213   {
47214     M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "btsts", 16,
47215     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47216   },
47217 /* btsts${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
47218   {
47219     M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "btsts", 16,
47220     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47221   },
47222 /* btsts${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
47223   {
47224     M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "btsts", 16,
47225     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47226   },
47227 /* btsts${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
47228   {
47229     M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "btsts", 24,
47230     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47231   },
47232 /* btsts${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
47233   {
47234     M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "btsts", 32,
47235     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47236   },
47237 /* btsts${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
47238   {
47239     M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "btsts", 40,
47240     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47241   },
47242 /* btsts${X} ${BitBase32-16-u11-Unprefixed}[sb] */
47243   {
47244     M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "btsts", 24,
47245     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47246   },
47247 /* btsts${X} ${BitBase32-16-u19-Unprefixed}[sb] */
47248   {
47249     M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "btsts", 32,
47250     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47251   },
47252 /* btsts${X} ${BitBase32-16-s11-Unprefixed}[fb] */
47253   {
47254     M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "btsts", 24,
47255     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47256   },
47257 /* btsts${X} ${BitBase32-16-s19-Unprefixed}[fb] */
47258   {
47259     M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "btsts", 32,
47260     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47261   },
47262 /* btsts${X} ${BitBase32-16-u19-Unprefixed} */
47263   {
47264     M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "btsts", 32,
47265     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47266   },
47267 /* btsts${X} ${BitBase32-16-u27-Unprefixed} */
47268   {
47269     M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "btsts", 40,
47270     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47271   },
47272 /* btsts${X} $Bitno16R,$Bit16Rn */
47273   {
47274     M32C_INSN_BTSTS16_X_BIT16_16_BIT16_RN_DIRECT, "btsts16-X-bit16-16-bit16-Rn-direct", "btsts", 24,
47275     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47276   },
47277 /* btsts${X} $Bitno16R,$Bit16An */
47278   {
47279     M32C_INSN_BTSTS16_X_BIT16_16_BIT16_AN_DIRECT, "btsts16-X-bit16-16-bit16-An-direct", "btsts", 24,
47280     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47281   },
47282 /* btsts${X} [$Bit16An] */
47283   {
47284     M32C_INSN_BTSTS16_X_BIT16_16_BIT16_AN_INDIRECT, "btsts16-X-bit16-16-bit16-An-indirect", "btsts", 16,
47285     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47286   },
47287 /* btsts${X} ${Dsp-16-u8}[$Bit16An] */
47288   {
47289     M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "btsts16-X-bit16-16-bit16-16-8-An-relative", "btsts", 24,
47290     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47291   },
47292 /* btsts${X} ${Dsp-16-u16}[$Bit16An] */
47293   {
47294     M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "btsts16-X-bit16-16-bit16-16-16-An-relative", "btsts", 32,
47295     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47296   },
47297 /* btsts${X} ${BitBase16-16-u8}[sb] */
47298   {
47299     M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "btsts16-X-bit16-16-bit16-16-8-SB-relative", "btsts", 24,
47300     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47301   },
47302 /* btsts${X} ${BitBase16-16-u16}[sb] */
47303   {
47304     M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "btsts16-X-bit16-16-bit16-16-16-SB-relative", "btsts", 32,
47305     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47306   },
47307 /* btsts${X} ${BitBase16-16-s8}[fb] */
47308   {
47309     M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "btsts16-X-bit16-16-bit16-16-8-FB-relative", "btsts", 24,
47310     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47311   },
47312 /* btsts${X} ${BitBase16-16-u16} */
47313   {
47314     M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "btsts16-X-bit16-16-bit16-16-16-absolute", "btsts", 32,
47315     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47316   },
47317 /* btstc${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
47318   {
47319     M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "btstc", 16,
47320     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47321   },
47322 /* btstc${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
47323   {
47324     M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "btstc", 16,
47325     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47326   },
47327 /* btstc${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
47328   {
47329     M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "btstc", 16,
47330     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47331   },
47332 /* btstc${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
47333   {
47334     M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "btstc", 24,
47335     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47336   },
47337 /* btstc${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
47338   {
47339     M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "btstc", 32,
47340     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47341   },
47342 /* btstc${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
47343   {
47344     M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "btstc", 40,
47345     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47346   },
47347 /* btstc${X} ${BitBase32-16-u11-Unprefixed}[sb] */
47348   {
47349     M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "btstc", 24,
47350     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47351   },
47352 /* btstc${X} ${BitBase32-16-u19-Unprefixed}[sb] */
47353   {
47354     M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "btstc", 32,
47355     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47356   },
47357 /* btstc${X} ${BitBase32-16-s11-Unprefixed}[fb] */
47358   {
47359     M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "btstc", 24,
47360     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47361   },
47362 /* btstc${X} ${BitBase32-16-s19-Unprefixed}[fb] */
47363   {
47364     M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "btstc", 32,
47365     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47366   },
47367 /* btstc${X} ${BitBase32-16-u19-Unprefixed} */
47368   {
47369     M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "btstc", 32,
47370     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47371   },
47372 /* btstc${X} ${BitBase32-16-u27-Unprefixed} */
47373   {
47374     M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "btstc", 40,
47375     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47376   },
47377 /* btstc${X} $Bitno16R,$Bit16Rn */
47378   {
47379     M32C_INSN_BTSTC16_X_BIT16_16_BIT16_RN_DIRECT, "btstc16-X-bit16-16-bit16-Rn-direct", "btstc", 24,
47380     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47381   },
47382 /* btstc${X} $Bitno16R,$Bit16An */
47383   {
47384     M32C_INSN_BTSTC16_X_BIT16_16_BIT16_AN_DIRECT, "btstc16-X-bit16-16-bit16-An-direct", "btstc", 24,
47385     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47386   },
47387 /* btstc${X} [$Bit16An] */
47388   {
47389     M32C_INSN_BTSTC16_X_BIT16_16_BIT16_AN_INDIRECT, "btstc16-X-bit16-16-bit16-An-indirect", "btstc", 16,
47390     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47391   },
47392 /* btstc${X} ${Dsp-16-u8}[$Bit16An] */
47393   {
47394     M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "btstc16-X-bit16-16-bit16-16-8-An-relative", "btstc", 24,
47395     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47396   },
47397 /* btstc${X} ${Dsp-16-u16}[$Bit16An] */
47398   {
47399     M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "btstc16-X-bit16-16-bit16-16-16-An-relative", "btstc", 32,
47400     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47401   },
47402 /* btstc${X} ${BitBase16-16-u8}[sb] */
47403   {
47404     M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "btstc16-X-bit16-16-bit16-16-8-SB-relative", "btstc", 24,
47405     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47406   },
47407 /* btstc${X} ${BitBase16-16-u16}[sb] */
47408   {
47409     M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "btstc16-X-bit16-16-bit16-16-16-SB-relative", "btstc", 32,
47410     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47411   },
47412 /* btstc${X} ${BitBase16-16-s8}[fb] */
47413   {
47414     M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "btstc16-X-bit16-16-bit16-16-8-FB-relative", "btstc", 24,
47415     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47416   },
47417 /* btstc${X} ${BitBase16-16-u16} */
47418   {
47419     M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "btstc16-X-bit16-16-bit16-16-16-absolute", "btstc", 32,
47420     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47421   },
47422 /* btst${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
47423   {
47424     M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "btst", 16,
47425     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47426   },
47427 /* btst${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
47428   {
47429     M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "btst", 16,
47430     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47431   },
47432 /* btst${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
47433   {
47434     M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "btst", 16,
47435     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47436   },
47437 /* btst${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
47438   {
47439     M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "btst", 24,
47440     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47441   },
47442 /* btst${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
47443   {
47444     M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "btst", 32,
47445     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47446   },
47447 /* btst${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
47448   {
47449     M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "btst", 40,
47450     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47451   },
47452 /* btst${X} ${BitBase32-16-u11-Unprefixed}[sb] */
47453   {
47454     M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "btst", 24,
47455     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47456   },
47457 /* btst${X} ${BitBase32-16-u19-Unprefixed}[sb] */
47458   {
47459     M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "btst", 32,
47460     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47461   },
47462 /* btst${X} ${BitBase32-16-s11-Unprefixed}[fb] */
47463   {
47464     M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "btst", 24,
47465     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47466   },
47467 /* btst${X} ${BitBase32-16-s19-Unprefixed}[fb] */
47468   {
47469     M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "btst", 32,
47470     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47471   },
47472 /* btst${X} ${BitBase32-16-u19-Unprefixed} */
47473   {
47474     M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "btst", 32,
47475     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47476   },
47477 /* btst${X} ${BitBase32-16-u27-Unprefixed} */
47478   {
47479     M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "btst", 40,
47480     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47481   },
47482 /* btst${G} $Bitno16R,$Bit16Rn */
47483   {
47484     M32C_INSN_BTST16_G_BIT16_16_8_BIT16_RN_DIRECT, "btst16-G-bit16-16-8-bit16-Rn-direct", "btst", 24,
47485     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47486   },
47487 /* btst${G} $Bitno16R,$Bit16An */
47488   {
47489     M32C_INSN_BTST16_G_BIT16_16_8_BIT16_AN_DIRECT, "btst16-G-bit16-16-8-bit16-An-direct", "btst", 24,
47490     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47491   },
47492 /* btst${G} ${Dsp-16-u8}[$Bit16An] */
47493   {
47494     M32C_INSN_BTST16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE, "btst16-G-bit16-16-8-bit16-16-8-An-relative", "btst", 24,
47495     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47496   },
47497 /* btst${G} ${BitBase16-16-u8}[sb] */
47498   {
47499     M32C_INSN_BTST16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE, "btst16-G-bit16-16-8-bit16-16-8-SB-relative", "btst", 24,
47500     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47501   },
47502 /* btst${G} ${BitBase16-16-s8}[fb] */
47503   {
47504     M32C_INSN_BTST16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, "btst16-G-bit16-16-8-bit16-16-8-FB-relative", "btst", 24,
47505     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47506   },
47507 /* btst${S} ${BitBase16-8-u11-S}[sb] */
47508   {
47509     M32C_INSN_BTST16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S, "btst16-S-bit16-11-S-bit16-11-SB-relative-S", "btst", 16,
47510     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47511   },
47512 /* btst${G} ${Dsp-16-u16}[$Bit16An] */
47513   {
47514     M32C_INSN_BTST16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE, "btst16-G-bit16-16-16-bit16-16-16-An-relative", "btst", 32,
47515     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47516   },
47517 /* btst${G} ${BitBase16-16-u16}[sb] */
47518   {
47519     M32C_INSN_BTST16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE, "btst16-G-bit16-16-16-bit16-16-16-SB-relative", "btst", 32,
47520     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47521   },
47522 /* btst${G} ${BitBase16-16-u16} */
47523   {
47524     M32C_INSN_BTST16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, "btst16-G-bit16-16-16-bit16-16-16-absolute", "btst", 32,
47525     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47526   },
47527 /* btst${G} [$Bit16An] */
47528   {
47529     M32C_INSN_BTST16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT, "btst16-G-bit16-16-basic-bit16-An-indirect", "btst", 16,
47530     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47531   },
47532 /* bset${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
47533   {
47534     M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "bset", 16,
47535     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47536   },
47537 /* bset${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
47538   {
47539     M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "bset", 16,
47540     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47541   },
47542 /* bset${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
47543   {
47544     M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "bset", 16,
47545     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47546   },
47547 /* bset${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
47548   {
47549     M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "bset", 24,
47550     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47551   },
47552 /* bset${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
47553   {
47554     M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "bset", 32,
47555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47556   },
47557 /* bset${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
47558   {
47559     M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "bset", 40,
47560     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47561   },
47562 /* bset${X} ${BitBase32-16-u11-Unprefixed}[sb] */
47563   {
47564     M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "bset", 24,
47565     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47566   },
47567 /* bset${X} ${BitBase32-16-u19-Unprefixed}[sb] */
47568   {
47569     M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "bset", 32,
47570     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47571   },
47572 /* bset${X} ${BitBase32-16-s11-Unprefixed}[fb] */
47573   {
47574     M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "bset", 24,
47575     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47576   },
47577 /* bset${X} ${BitBase32-16-s19-Unprefixed}[fb] */
47578   {
47579     M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "bset", 32,
47580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47581   },
47582 /* bset${X} ${BitBase32-16-u19-Unprefixed} */
47583   {
47584     M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "bset", 32,
47585     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47586   },
47587 /* bset${X} ${BitBase32-16-u27-Unprefixed} */
47588   {
47589     M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "bset", 40,
47590     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47591   },
47592 /* bset${G} $Bitno16R,$Bit16Rn */
47593   {
47594     M32C_INSN_BSET16_G_BIT16_16_8_BIT16_RN_DIRECT, "bset16-G-bit16-16-8-bit16-Rn-direct", "bset", 24,
47595     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47596   },
47597 /* bset${G} $Bitno16R,$Bit16An */
47598   {
47599     M32C_INSN_BSET16_G_BIT16_16_8_BIT16_AN_DIRECT, "bset16-G-bit16-16-8-bit16-An-direct", "bset", 24,
47600     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47601   },
47602 /* bset${G} ${Dsp-16-u8}[$Bit16An] */
47603   {
47604     M32C_INSN_BSET16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE, "bset16-G-bit16-16-8-bit16-16-8-An-relative", "bset", 24,
47605     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47606   },
47607 /* bset${G} ${BitBase16-16-u8}[sb] */
47608   {
47609     M32C_INSN_BSET16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE, "bset16-G-bit16-16-8-bit16-16-8-SB-relative", "bset", 24,
47610     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47611   },
47612 /* bset${G} ${BitBase16-16-s8}[fb] */
47613   {
47614     M32C_INSN_BSET16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, "bset16-G-bit16-16-8-bit16-16-8-FB-relative", "bset", 24,
47615     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47616   },
47617 /* bset${S} ${BitBase16-8-u11-S}[sb] */
47618   {
47619     M32C_INSN_BSET16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S, "bset16-S-bit16-11-S-bit16-11-SB-relative-S", "bset", 16,
47620     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47621   },
47622 /* bset${G} ${Dsp-16-u16}[$Bit16An] */
47623   {
47624     M32C_INSN_BSET16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE, "bset16-G-bit16-16-16-bit16-16-16-An-relative", "bset", 32,
47625     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47626   },
47627 /* bset${G} ${BitBase16-16-u16}[sb] */
47628   {
47629     M32C_INSN_BSET16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE, "bset16-G-bit16-16-16-bit16-16-16-SB-relative", "bset", 32,
47630     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47631   },
47632 /* bset${G} ${BitBase16-16-u16} */
47633   {
47634     M32C_INSN_BSET16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, "bset16-G-bit16-16-16-bit16-16-16-absolute", "bset", 32,
47635     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47636   },
47637 /* bset${G} [$Bit16An] */
47638   {
47639     M32C_INSN_BSET16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT, "bset16-G-bit16-16-basic-bit16-An-indirect", "bset", 16,
47640     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47641   },
47642 /* bor${X} $Bitno32Prefixed,$Bit32RnPrefixed */
47643   {
47644     M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bor", 24,
47645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47646   },
47647 /* bor${X} $Bitno32Prefixed,$Bit32AnPrefixed */
47648   {
47649     M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bor", 24,
47650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47651   },
47652 /* bor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
47653   {
47654     M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bor", 24,
47655     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47656   },
47657 /* bor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
47658   {
47659     M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bor", 32,
47660     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47661   },
47662 /* bor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
47663   {
47664     M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bor", 40,
47665     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47666   },
47667 /* bor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
47668   {
47669     M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bor", 48,
47670     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47671   },
47672 /* bor${X} ${BitBase32-24-u11-Prefixed}[sb] */
47673   {
47674     M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bor", 32,
47675     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47676   },
47677 /* bor${X} ${BitBase32-24-u19-Prefixed}[sb] */
47678   {
47679     M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bor", 40,
47680     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47681   },
47682 /* bor${X} ${BitBase32-24-s11-Prefixed}[fb] */
47683   {
47684     M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bor", 32,
47685     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47686   },
47687 /* bor${X} ${BitBase32-24-s19-Prefixed}[fb] */
47688   {
47689     M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bor", 40,
47690     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47691   },
47692 /* bor${X} ${BitBase32-24-u19-Prefixed} */
47693   {
47694     M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bor", 40,
47695     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47696   },
47697 /* bor${X} ${BitBase32-24-u27-Prefixed} */
47698   {
47699     M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bor", 48,
47700     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47701   },
47702 /* bor${X} $Bitno16R,$Bit16Rn */
47703   {
47704     M32C_INSN_BOR16_X_BIT16_16_BIT16_RN_DIRECT, "bor16-X-bit16-16-bit16-Rn-direct", "bor", 24,
47705     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47706   },
47707 /* bor${X} $Bitno16R,$Bit16An */
47708   {
47709     M32C_INSN_BOR16_X_BIT16_16_BIT16_AN_DIRECT, "bor16-X-bit16-16-bit16-An-direct", "bor", 24,
47710     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47711   },
47712 /* bor${X} [$Bit16An] */
47713   {
47714     M32C_INSN_BOR16_X_BIT16_16_BIT16_AN_INDIRECT, "bor16-X-bit16-16-bit16-An-indirect", "bor", 16,
47715     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47716   },
47717 /* bor${X} ${Dsp-16-u8}[$Bit16An] */
47718   {
47719     M32C_INSN_BOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bor16-X-bit16-16-bit16-16-8-An-relative", "bor", 24,
47720     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47721   },
47722 /* bor${X} ${Dsp-16-u16}[$Bit16An] */
47723   {
47724     M32C_INSN_BOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bor16-X-bit16-16-bit16-16-16-An-relative", "bor", 32,
47725     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47726   },
47727 /* bor${X} ${BitBase16-16-u8}[sb] */
47728   {
47729     M32C_INSN_BOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bor16-X-bit16-16-bit16-16-8-SB-relative", "bor", 24,
47730     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47731   },
47732 /* bor${X} ${BitBase16-16-u16}[sb] */
47733   {
47734     M32C_INSN_BOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bor16-X-bit16-16-bit16-16-16-SB-relative", "bor", 32,
47735     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47736   },
47737 /* bor${X} ${BitBase16-16-s8}[fb] */
47738   {
47739     M32C_INSN_BOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bor16-X-bit16-16-bit16-16-8-FB-relative", "bor", 24,
47740     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47741   },
47742 /* bor${X} ${BitBase16-16-u16} */
47743   {
47744     M32C_INSN_BOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bor16-X-bit16-16-bit16-16-16-absolute", "bor", 32,
47745     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47746   },
47747 /* bnxor${X} $Bitno32Prefixed,$Bit32RnPrefixed */
47748   {
47749     M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bnxor", 24,
47750     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47751   },
47752 /* bnxor${X} $Bitno32Prefixed,$Bit32AnPrefixed */
47753   {
47754     M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bnxor", 24,
47755     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47756   },
47757 /* bnxor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
47758   {
47759     M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bnxor", 24,
47760     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47761   },
47762 /* bnxor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
47763   {
47764     M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bnxor", 32,
47765     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47766   },
47767 /* bnxor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
47768   {
47769     M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bnxor", 40,
47770     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47771   },
47772 /* bnxor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
47773   {
47774     M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bnxor", 48,
47775     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47776   },
47777 /* bnxor${X} ${BitBase32-24-u11-Prefixed}[sb] */
47778   {
47779     M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bnxor", 32,
47780     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47781   },
47782 /* bnxor${X} ${BitBase32-24-u19-Prefixed}[sb] */
47783   {
47784     M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bnxor", 40,
47785     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47786   },
47787 /* bnxor${X} ${BitBase32-24-s11-Prefixed}[fb] */
47788   {
47789     M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bnxor", 32,
47790     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47791   },
47792 /* bnxor${X} ${BitBase32-24-s19-Prefixed}[fb] */
47793   {
47794     M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bnxor", 40,
47795     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47796   },
47797 /* bnxor${X} ${BitBase32-24-u19-Prefixed} */
47798   {
47799     M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bnxor", 40,
47800     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47801   },
47802 /* bnxor${X} ${BitBase32-24-u27-Prefixed} */
47803   {
47804     M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bnxor", 48,
47805     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47806   },
47807 /* bnxor${X} $Bitno16R,$Bit16Rn */
47808   {
47809     M32C_INSN_BNXOR16_X_BIT16_16_BIT16_RN_DIRECT, "bnxor16-X-bit16-16-bit16-Rn-direct", "bnxor", 24,
47810     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47811   },
47812 /* bnxor${X} $Bitno16R,$Bit16An */
47813   {
47814     M32C_INSN_BNXOR16_X_BIT16_16_BIT16_AN_DIRECT, "bnxor16-X-bit16-16-bit16-An-direct", "bnxor", 24,
47815     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47816   },
47817 /* bnxor${X} [$Bit16An] */
47818   {
47819     M32C_INSN_BNXOR16_X_BIT16_16_BIT16_AN_INDIRECT, "bnxor16-X-bit16-16-bit16-An-indirect", "bnxor", 16,
47820     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47821   },
47822 /* bnxor${X} ${Dsp-16-u8}[$Bit16An] */
47823   {
47824     M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bnxor16-X-bit16-16-bit16-16-8-An-relative", "bnxor", 24,
47825     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47826   },
47827 /* bnxor${X} ${Dsp-16-u16}[$Bit16An] */
47828   {
47829     M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bnxor16-X-bit16-16-bit16-16-16-An-relative", "bnxor", 32,
47830     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47831   },
47832 /* bnxor${X} ${BitBase16-16-u8}[sb] */
47833   {
47834     M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bnxor16-X-bit16-16-bit16-16-8-SB-relative", "bnxor", 24,
47835     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47836   },
47837 /* bnxor${X} ${BitBase16-16-u16}[sb] */
47838   {
47839     M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bnxor16-X-bit16-16-bit16-16-16-SB-relative", "bnxor", 32,
47840     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47841   },
47842 /* bnxor${X} ${BitBase16-16-s8}[fb] */
47843   {
47844     M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bnxor16-X-bit16-16-bit16-16-8-FB-relative", "bnxor", 24,
47845     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47846   },
47847 /* bnxor${X} ${BitBase16-16-u16} */
47848   {
47849     M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bnxor16-X-bit16-16-bit16-16-16-absolute", "bnxor", 32,
47850     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47851   },
47852 /* bntst${X} $Bitno32Prefixed,$Bit32RnPrefixed */
47853   {
47854     M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bntst", 24,
47855     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47856   },
47857 /* bntst${X} $Bitno32Prefixed,$Bit32AnPrefixed */
47858   {
47859     M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bntst", 24,
47860     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47861   },
47862 /* bntst${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
47863   {
47864     M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bntst", 24,
47865     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47866   },
47867 /* bntst${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
47868   {
47869     M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bntst", 32,
47870     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47871   },
47872 /* bntst${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
47873   {
47874     M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bntst", 40,
47875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47876   },
47877 /* bntst${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
47878   {
47879     M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bntst", 48,
47880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47881   },
47882 /* bntst${X} ${BitBase32-24-u11-Prefixed}[sb] */
47883   {
47884     M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bntst", 32,
47885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47886   },
47887 /* bntst${X} ${BitBase32-24-u19-Prefixed}[sb] */
47888   {
47889     M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bntst", 40,
47890     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47891   },
47892 /* bntst${X} ${BitBase32-24-s11-Prefixed}[fb] */
47893   {
47894     M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bntst", 32,
47895     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47896   },
47897 /* bntst${X} ${BitBase32-24-s19-Prefixed}[fb] */
47898   {
47899     M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bntst", 40,
47900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47901   },
47902 /* bntst${X} ${BitBase32-24-u19-Prefixed} */
47903   {
47904     M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bntst", 40,
47905     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47906   },
47907 /* bntst${X} ${BitBase32-24-u27-Prefixed} */
47908   {
47909     M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bntst", 48,
47910     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47911   },
47912 /* bntst${X} $Bitno16R,$Bit16Rn */
47913   {
47914     M32C_INSN_BNTST16_X_BIT16_16_BIT16_RN_DIRECT, "bntst16-X-bit16-16-bit16-Rn-direct", "bntst", 24,
47915     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47916   },
47917 /* bntst${X} $Bitno16R,$Bit16An */
47918   {
47919     M32C_INSN_BNTST16_X_BIT16_16_BIT16_AN_DIRECT, "bntst16-X-bit16-16-bit16-An-direct", "bntst", 24,
47920     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47921   },
47922 /* bntst${X} [$Bit16An] */
47923   {
47924     M32C_INSN_BNTST16_X_BIT16_16_BIT16_AN_INDIRECT, "bntst16-X-bit16-16-bit16-An-indirect", "bntst", 16,
47925     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47926   },
47927 /* bntst${X} ${Dsp-16-u8}[$Bit16An] */
47928   {
47929     M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bntst16-X-bit16-16-bit16-16-8-An-relative", "bntst", 24,
47930     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47931   },
47932 /* bntst${X} ${Dsp-16-u16}[$Bit16An] */
47933   {
47934     M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bntst16-X-bit16-16-bit16-16-16-An-relative", "bntst", 32,
47935     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47936   },
47937 /* bntst${X} ${BitBase16-16-u8}[sb] */
47938   {
47939     M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bntst16-X-bit16-16-bit16-16-8-SB-relative", "bntst", 24,
47940     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47941   },
47942 /* bntst${X} ${BitBase16-16-u16}[sb] */
47943   {
47944     M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bntst16-X-bit16-16-bit16-16-16-SB-relative", "bntst", 32,
47945     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47946   },
47947 /* bntst${X} ${BitBase16-16-s8}[fb] */
47948   {
47949     M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bntst16-X-bit16-16-bit16-16-8-FB-relative", "bntst", 24,
47950     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47951   },
47952 /* bntst${X} ${BitBase16-16-u16} */
47953   {
47954     M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bntst16-X-bit16-16-bit16-16-16-absolute", "bntst", 32,
47955     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47956   },
47957 /* bnot${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
47958   {
47959     M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "bnot", 16,
47960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47961   },
47962 /* bnot${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
47963   {
47964     M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "bnot", 16,
47965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47966   },
47967 /* bnot${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
47968   {
47969     M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "bnot", 16,
47970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47971   },
47972 /* bnot${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
47973   {
47974     M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "bnot", 24,
47975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47976   },
47977 /* bnot${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
47978   {
47979     M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "bnot", 32,
47980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47981   },
47982 /* bnot${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
47983   {
47984     M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "bnot", 40,
47985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47986   },
47987 /* bnot${X} ${BitBase32-16-u11-Unprefixed}[sb] */
47988   {
47989     M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "bnot", 24,
47990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47991   },
47992 /* bnot${X} ${BitBase32-16-u19-Unprefixed}[sb] */
47993   {
47994     M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "bnot", 32,
47995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47996   },
47997 /* bnot${X} ${BitBase32-16-s11-Unprefixed}[fb] */
47998   {
47999     M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "bnot", 24,
48000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48001   },
48002 /* bnot${X} ${BitBase32-16-s19-Unprefixed}[fb] */
48003   {
48004     M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "bnot", 32,
48005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48006   },
48007 /* bnot${X} ${BitBase32-16-u19-Unprefixed} */
48008   {
48009     M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "bnot", 32,
48010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48011   },
48012 /* bnot${X} ${BitBase32-16-u27-Unprefixed} */
48013   {
48014     M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "bnot", 40,
48015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48016   },
48017 /* bnot${G} $Bitno16R,$Bit16Rn */
48018   {
48019     M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_RN_DIRECT, "bnot16-G-bit16-16-8-bit16-Rn-direct", "bnot", 24,
48020     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48021   },
48022 /* bnot${G} $Bitno16R,$Bit16An */
48023   {
48024     M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_AN_DIRECT, "bnot16-G-bit16-16-8-bit16-An-direct", "bnot", 24,
48025     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48026   },
48027 /* bnot${G} ${Dsp-16-u8}[$Bit16An] */
48028   {
48029     M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE, "bnot16-G-bit16-16-8-bit16-16-8-An-relative", "bnot", 24,
48030     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48031   },
48032 /* bnot${G} ${BitBase16-16-u8}[sb] */
48033   {
48034     M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE, "bnot16-G-bit16-16-8-bit16-16-8-SB-relative", "bnot", 24,
48035     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48036   },
48037 /* bnot${G} ${BitBase16-16-s8}[fb] */
48038   {
48039     M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, "bnot16-G-bit16-16-8-bit16-16-8-FB-relative", "bnot", 24,
48040     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48041   },
48042 /* bnot${S} ${BitBase16-8-u11-S}[sb] */
48043   {
48044     M32C_INSN_BNOT16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S, "bnot16-S-bit16-11-S-bit16-11-SB-relative-S", "bnot", 16,
48045     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48046   },
48047 /* bnot${G} ${Dsp-16-u16}[$Bit16An] */
48048   {
48049     M32C_INSN_BNOT16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE, "bnot16-G-bit16-16-16-bit16-16-16-An-relative", "bnot", 32,
48050     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48051   },
48052 /* bnot${G} ${BitBase16-16-u16}[sb] */
48053   {
48054     M32C_INSN_BNOT16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE, "bnot16-G-bit16-16-16-bit16-16-16-SB-relative", "bnot", 32,
48055     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48056   },
48057 /* bnot${G} ${BitBase16-16-u16} */
48058   {
48059     M32C_INSN_BNOT16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, "bnot16-G-bit16-16-16-bit16-16-16-absolute", "bnot", 32,
48060     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48061   },
48062 /* bnot${G} [$Bit16An] */
48063   {
48064     M32C_INSN_BNOT16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT, "bnot16-G-bit16-16-basic-bit16-An-indirect", "bnot", 16,
48065     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48066   },
48067 /* bnor${X} $Bitno32Prefixed,$Bit32RnPrefixed */
48068   {
48069     M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bnor", 24,
48070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48071   },
48072 /* bnor${X} $Bitno32Prefixed,$Bit32AnPrefixed */
48073   {
48074     M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bnor", 24,
48075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48076   },
48077 /* bnor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
48078   {
48079     M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bnor", 24,
48080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48081   },
48082 /* bnor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
48083   {
48084     M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bnor", 32,
48085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48086   },
48087 /* bnor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
48088   {
48089     M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bnor", 40,
48090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48091   },
48092 /* bnor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
48093   {
48094     M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bnor", 48,
48095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48096   },
48097 /* bnor${X} ${BitBase32-24-u11-Prefixed}[sb] */
48098   {
48099     M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bnor", 32,
48100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48101   },
48102 /* bnor${X} ${BitBase32-24-u19-Prefixed}[sb] */
48103   {
48104     M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bnor", 40,
48105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48106   },
48107 /* bnor${X} ${BitBase32-24-s11-Prefixed}[fb] */
48108   {
48109     M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bnor", 32,
48110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48111   },
48112 /* bnor${X} ${BitBase32-24-s19-Prefixed}[fb] */
48113   {
48114     M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bnor", 40,
48115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48116   },
48117 /* bnor${X} ${BitBase32-24-u19-Prefixed} */
48118   {
48119     M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bnor", 40,
48120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48121   },
48122 /* bnor${X} ${BitBase32-24-u27-Prefixed} */
48123   {
48124     M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bnor", 48,
48125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48126   },
48127 /* bnor${X} $Bitno16R,$Bit16Rn */
48128   {
48129     M32C_INSN_BNOR16_X_BIT16_16_BIT16_RN_DIRECT, "bnor16-X-bit16-16-bit16-Rn-direct", "bnor", 24,
48130     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48131   },
48132 /* bnor${X} $Bitno16R,$Bit16An */
48133   {
48134     M32C_INSN_BNOR16_X_BIT16_16_BIT16_AN_DIRECT, "bnor16-X-bit16-16-bit16-An-direct", "bnor", 24,
48135     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48136   },
48137 /* bnor${X} [$Bit16An] */
48138   {
48139     M32C_INSN_BNOR16_X_BIT16_16_BIT16_AN_INDIRECT, "bnor16-X-bit16-16-bit16-An-indirect", "bnor", 16,
48140     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48141   },
48142 /* bnor${X} ${Dsp-16-u8}[$Bit16An] */
48143   {
48144     M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bnor16-X-bit16-16-bit16-16-8-An-relative", "bnor", 24,
48145     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48146   },
48147 /* bnor${X} ${Dsp-16-u16}[$Bit16An] */
48148   {
48149     M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bnor16-X-bit16-16-bit16-16-16-An-relative", "bnor", 32,
48150     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48151   },
48152 /* bnor${X} ${BitBase16-16-u8}[sb] */
48153   {
48154     M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bnor16-X-bit16-16-bit16-16-8-SB-relative", "bnor", 24,
48155     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48156   },
48157 /* bnor${X} ${BitBase16-16-u16}[sb] */
48158   {
48159     M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bnor16-X-bit16-16-bit16-16-16-SB-relative", "bnor", 32,
48160     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48161   },
48162 /* bnor${X} ${BitBase16-16-s8}[fb] */
48163   {
48164     M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bnor16-X-bit16-16-bit16-16-8-FB-relative", "bnor", 24,
48165     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48166   },
48167 /* bnor${X} ${BitBase16-16-u16} */
48168   {
48169     M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bnor16-X-bit16-16-bit16-16-16-absolute", "bnor", 32,
48170     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48171   },
48172 /* bnand${X} $Bitno32Prefixed,$Bit32RnPrefixed */
48173   {
48174     M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bnand", 24,
48175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48176   },
48177 /* bnand${X} $Bitno32Prefixed,$Bit32AnPrefixed */
48178   {
48179     M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bnand", 24,
48180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48181   },
48182 /* bnand${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
48183   {
48184     M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bnand", 24,
48185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48186   },
48187 /* bnand${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
48188   {
48189     M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bnand", 32,
48190     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48191   },
48192 /* bnand${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
48193   {
48194     M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bnand", 40,
48195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48196   },
48197 /* bnand${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
48198   {
48199     M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bnand", 48,
48200     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48201   },
48202 /* bnand${X} ${BitBase32-24-u11-Prefixed}[sb] */
48203   {
48204     M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bnand", 32,
48205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48206   },
48207 /* bnand${X} ${BitBase32-24-u19-Prefixed}[sb] */
48208   {
48209     M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bnand", 40,
48210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48211   },
48212 /* bnand${X} ${BitBase32-24-s11-Prefixed}[fb] */
48213   {
48214     M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bnand", 32,
48215     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48216   },
48217 /* bnand${X} ${BitBase32-24-s19-Prefixed}[fb] */
48218   {
48219     M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bnand", 40,
48220     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48221   },
48222 /* bnand${X} ${BitBase32-24-u19-Prefixed} */
48223   {
48224     M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bnand", 40,
48225     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48226   },
48227 /* bnand${X} ${BitBase32-24-u27-Prefixed} */
48228   {
48229     M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bnand", 48,
48230     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48231   },
48232 /* bnand${X} $Bitno16R,$Bit16Rn */
48233   {
48234     M32C_INSN_BNAND16_X_BIT16_16_BIT16_RN_DIRECT, "bnand16-X-bit16-16-bit16-Rn-direct", "bnand", 24,
48235     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48236   },
48237 /* bnand${X} $Bitno16R,$Bit16An */
48238   {
48239     M32C_INSN_BNAND16_X_BIT16_16_BIT16_AN_DIRECT, "bnand16-X-bit16-16-bit16-An-direct", "bnand", 24,
48240     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48241   },
48242 /* bnand${X} [$Bit16An] */
48243   {
48244     M32C_INSN_BNAND16_X_BIT16_16_BIT16_AN_INDIRECT, "bnand16-X-bit16-16-bit16-An-indirect", "bnand", 16,
48245     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48246   },
48247 /* bnand${X} ${Dsp-16-u8}[$Bit16An] */
48248   {
48249     M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bnand16-X-bit16-16-bit16-16-8-An-relative", "bnand", 24,
48250     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48251   },
48252 /* bnand${X} ${Dsp-16-u16}[$Bit16An] */
48253   {
48254     M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bnand16-X-bit16-16-bit16-16-16-An-relative", "bnand", 32,
48255     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48256   },
48257 /* bnand${X} ${BitBase16-16-u8}[sb] */
48258   {
48259     M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bnand16-X-bit16-16-bit16-16-8-SB-relative", "bnand", 24,
48260     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48261   },
48262 /* bnand${X} ${BitBase16-16-u16}[sb] */
48263   {
48264     M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bnand16-X-bit16-16-bit16-16-16-SB-relative", "bnand", 32,
48265     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48266   },
48267 /* bnand${X} ${BitBase16-16-s8}[fb] */
48268   {
48269     M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bnand16-X-bit16-16-bit16-16-8-FB-relative", "bnand", 24,
48270     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48271   },
48272 /* bnand${X} ${BitBase16-16-u16} */
48273   {
48274     M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bnand16-X-bit16-16-bit16-16-16-absolute", "bnand", 32,
48275     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48276   },
48277 /* bm${cond32-16} $Bitno32Unprefixed,$Bit32RnUnprefixed */
48278   {
48279     M32C_INSN_BM32_BIT32_BASIC_UNPREFIXED_COND32_16_BIT32_RN_DIRECT_UNPREFIXED, "bm32-bit32-basic-Unprefixed-cond32-16-bit32-Rn-direct-Unprefixed", "bm", 24,
48280     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48281   },
48282 /* bm${cond32-16} $Bitno32Unprefixed,$Bit32AnUnprefixed */
48283   {
48284     M32C_INSN_BM32_BIT32_BASIC_UNPREFIXED_COND32_16_BIT32_AN_DIRECT_UNPREFIXED, "bm32-bit32-basic-Unprefixed-cond32-16-bit32-An-direct-Unprefixed", "bm", 24,
48285     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48286   },
48287 /* bm${cond32-16} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
48288   {
48289     M32C_INSN_BM32_BIT32_BASIC_UNPREFIXED_COND32_16_BIT32_AN_INDIRECT_UNPREFIXED, "bm32-bit32-basic-Unprefixed-cond32-16-bit32-An-indirect-Unprefixed", "bm", 24,
48290     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48291   },
48292 /* bm${cond32-24} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
48293   {
48294     M32C_INSN_BM32_BIT32_16_8_UNPREFIXED_COND32_24_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "bm32-bit32-16-8-Unprefixed-cond32-24-bit32-16-11-An-relative-Unprefixed", "bm", 32,
48295     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48296   },
48297 /* bm${cond32-24} ${BitBase32-16-u11-Unprefixed}[sb] */
48298   {
48299     M32C_INSN_BM32_BIT32_16_8_UNPREFIXED_COND32_24_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "bm32-bit32-16-8-Unprefixed-cond32-24-bit32-16-11-SB-relative-Unprefixed", "bm", 32,
48300     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48301   },
48302 /* bm${cond32-24} ${BitBase32-16-s11-Unprefixed}[fb] */
48303   {
48304     M32C_INSN_BM32_BIT32_16_8_UNPREFIXED_COND32_24_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "bm32-bit32-16-8-Unprefixed-cond32-24-bit32-16-11-FB-relative-Unprefixed", "bm", 32,
48305     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48306   },
48307 /* bm${cond32-32} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
48308   {
48309     M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "bm32-bit32-16-16-Unprefixed-cond32-32-bit32-16-19-An-relative-Unprefixed", "bm", 40,
48310     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48311   },
48312 /* bm${cond32-32} ${BitBase32-16-u19-Unprefixed}[sb] */
48313   {
48314     M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "bm32-bit32-16-16-Unprefixed-cond32-32-bit32-16-19-SB-relative-Unprefixed", "bm", 40,
48315     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48316   },
48317 /* bm${cond32-32} ${BitBase32-16-s19-Unprefixed}[fb] */
48318   {
48319     M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "bm32-bit32-16-16-Unprefixed-cond32-32-bit32-16-19-FB-relative-Unprefixed", "bm", 40,
48320     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48321   },
48322 /* bm${cond32-32} ${BitBase32-16-u19-Unprefixed} */
48323   {
48324     M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_ABSOLUTE_UNPREFIXED, "bm32-bit32-16-16-Unprefixed-cond32-32-bit32-16-19-absolute-Unprefixed", "bm", 40,
48325     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48326   },
48327 /* bm${cond32-40} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
48328   {
48329     M32C_INSN_BM32_BIT32_16_24_UNPREFIXED_COND32_40_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "bm32-bit32-16-24-Unprefixed-cond32-40-bit32-16-27-An-relative-Unprefixed", "bm", 48,
48330     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48331   },
48332 /* bm${cond32-40} ${BitBase32-16-u27-Unprefixed} */
48333   {
48334     M32C_INSN_BM32_BIT32_16_24_UNPREFIXED_COND32_40_BIT32_16_27_ABSOLUTE_UNPREFIXED, "bm32-bit32-16-24-Unprefixed-cond32-40-bit32-16-27-absolute-Unprefixed", "bm", 48,
48335     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48336   },
48337 /* bm${cond16-24} $Bitno16R,$Bit16Rn */
48338   {
48339     M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_RN_DIRECT, "bm16-bit16-16-8-cond16-24-bit16-Rn-direct", "bm", 32,
48340     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48341   },
48342 /* bm${cond16-24} $Bitno16R,$Bit16An */
48343   {
48344     M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_AN_DIRECT, "bm16-bit16-16-8-cond16-24-bit16-An-direct", "bm", 32,
48345     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48346   },
48347 /* bm${cond16-24} ${Dsp-16-u8}[$Bit16An] */
48348   {
48349     M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_16_8_AN_RELATIVE, "bm16-bit16-16-8-cond16-24-bit16-16-8-An-relative", "bm", 32,
48350     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48351   },
48352 /* bm${cond16-24} ${BitBase16-16-u8}[sb] */
48353   {
48354     M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_16_8_SB_RELATIVE, "bm16-bit16-16-8-cond16-24-bit16-16-8-SB-relative", "bm", 32,
48355     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48356   },
48357 /* bm${cond16-24} ${BitBase16-16-s8}[fb] */
48358   {
48359     M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_16_8_FB_RELATIVE, "bm16-bit16-16-8-cond16-24-bit16-16-8-FB-relative", "bm", 32,
48360     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48361   },
48362 /* bm${cond16-32} ${Dsp-16-u16}[$Bit16An] */
48363   {
48364     M32C_INSN_BM16_BIT16_16_16_COND16_32_BIT16_16_16_AN_RELATIVE, "bm16-bit16-16-16-cond16-32-bit16-16-16-An-relative", "bm", 40,
48365     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48366   },
48367 /* bm${cond16-32} ${BitBase16-16-u16}[sb] */
48368   {
48369     M32C_INSN_BM16_BIT16_16_16_COND16_32_BIT16_16_16_SB_RELATIVE, "bm16-bit16-16-16-cond16-32-bit16-16-16-SB-relative", "bm", 40,
48370     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48371   },
48372 /* bm${cond16-32} ${BitBase16-16-u16} */
48373   {
48374     M32C_INSN_BM16_BIT16_16_16_COND16_32_BIT16_16_16_ABSOLUTE, "bm16-bit16-16-16-cond16-32-bit16-16-16-absolute", "bm", 40,
48375     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48376   },
48377 /* bm${cond16-16} [$Bit16An] */
48378   {
48379     M32C_INSN_BM16_BIT16_16_BASIC_COND16_16_BIT16_AN_INDIRECT, "bm16-bit16-16-basic-cond16-16-bit16-An-indirect", "bm", 24,
48380     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48381   },
48382 /* bitindex.w $Dst32RnUnprefixedHI */
48383   {
48384     M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "bitindex.w", 16,
48385     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48386   },
48387 /* bitindex.w $Dst32AnUnprefixedHI */
48388   {
48389     M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "bitindex.w", 16,
48390     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48391   },
48392 /* bitindex.w [$Dst32AnUnprefixed] */
48393   {
48394     M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "bitindex.w", 16,
48395     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48396   },
48397 /* bitindex.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
48398   {
48399     M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "bitindex.w", 24,
48400     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48401   },
48402 /* bitindex.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
48403   {
48404     M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "bitindex.w", 32,
48405     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48406   },
48407 /* bitindex.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
48408   {
48409     M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "bitindex.w", 40,
48410     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48411   },
48412 /* bitindex.w ${Dsp-16-u8}[sb] */
48413   {
48414     M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "bitindex.w", 24,
48415     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48416   },
48417 /* bitindex.w ${Dsp-16-u16}[sb] */
48418   {
48419     M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "bitindex.w", 32,
48420     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48421   },
48422 /* bitindex.w ${Dsp-16-s8}[fb] */
48423   {
48424     M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "bitindex.w", 24,
48425     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48426   },
48427 /* bitindex.w ${Dsp-16-s16}[fb] */
48428   {
48429     M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "bitindex.w", 32,
48430     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48431   },
48432 /* bitindex.w ${Dsp-16-u16} */
48433   {
48434     M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "bitindex.w", 32,
48435     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48436   },
48437 /* bitindex.w ${Dsp-16-u24} */
48438   {
48439     M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "bitindex.w", 40,
48440     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48441   },
48442 /* bitindex.b $Dst32RnUnprefixedQI */
48443   {
48444     M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "bitindex.b", 16,
48445     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48446   },
48447 /* bitindex.b $Dst32AnUnprefixedQI */
48448   {
48449     M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "bitindex.b", 16,
48450     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48451   },
48452 /* bitindex.b [$Dst32AnUnprefixed] */
48453   {
48454     M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "bitindex.b", 16,
48455     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48456   },
48457 /* bitindex.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
48458   {
48459     M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "bitindex.b", 24,
48460     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48461   },
48462 /* bitindex.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
48463   {
48464     M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "bitindex.b", 32,
48465     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48466   },
48467 /* bitindex.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
48468   {
48469     M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "bitindex.b", 40,
48470     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48471   },
48472 /* bitindex.b ${Dsp-16-u8}[sb] */
48473   {
48474     M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "bitindex.b", 24,
48475     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48476   },
48477 /* bitindex.b ${Dsp-16-u16}[sb] */
48478   {
48479     M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "bitindex.b", 32,
48480     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48481   },
48482 /* bitindex.b ${Dsp-16-s8}[fb] */
48483   {
48484     M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "bitindex.b", 24,
48485     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48486   },
48487 /* bitindex.b ${Dsp-16-s16}[fb] */
48488   {
48489     M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "bitindex.b", 32,
48490     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48491   },
48492 /* bitindex.b ${Dsp-16-u16} */
48493   {
48494     M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "bitindex.b", 32,
48495     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48496   },
48497 /* bitindex.b ${Dsp-16-u24} */
48498   {
48499     M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "bitindex.b", 40,
48500     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48501   },
48502 /* bclr${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
48503   {
48504     M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "bclr", 16,
48505     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48506   },
48507 /* bclr${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
48508   {
48509     M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "bclr", 16,
48510     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48511   },
48512 /* bclr${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
48513   {
48514     M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "bclr", 16,
48515     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48516   },
48517 /* bclr${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
48518   {
48519     M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "bclr", 24,
48520     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48521   },
48522 /* bclr${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
48523   {
48524     M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "bclr", 32,
48525     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48526   },
48527 /* bclr${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
48528   {
48529     M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "bclr", 40,
48530     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48531   },
48532 /* bclr${X} ${BitBase32-16-u11-Unprefixed}[sb] */
48533   {
48534     M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "bclr", 24,
48535     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48536   },
48537 /* bclr${X} ${BitBase32-16-u19-Unprefixed}[sb] */
48538   {
48539     M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "bclr", 32,
48540     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48541   },
48542 /* bclr${X} ${BitBase32-16-s11-Unprefixed}[fb] */
48543   {
48544     M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "bclr", 24,
48545     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48546   },
48547 /* bclr${X} ${BitBase32-16-s19-Unprefixed}[fb] */
48548   {
48549     M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "bclr", 32,
48550     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48551   },
48552 /* bclr${X} ${BitBase32-16-u19-Unprefixed} */
48553   {
48554     M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "bclr", 32,
48555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48556   },
48557 /* bclr${X} ${BitBase32-16-u27-Unprefixed} */
48558   {
48559     M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "bclr", 40,
48560     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48561   },
48562 /* bclr${G} $Bitno16R,$Bit16Rn */
48563   {
48564     M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_RN_DIRECT, "bclr16-G-bit16-16-8-bit16-Rn-direct", "bclr", 24,
48565     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48566   },
48567 /* bclr${G} $Bitno16R,$Bit16An */
48568   {
48569     M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_AN_DIRECT, "bclr16-G-bit16-16-8-bit16-An-direct", "bclr", 24,
48570     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48571   },
48572 /* bclr${G} ${Dsp-16-u8}[$Bit16An] */
48573   {
48574     M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE, "bclr16-G-bit16-16-8-bit16-16-8-An-relative", "bclr", 24,
48575     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48576   },
48577 /* bclr${G} ${BitBase16-16-u8}[sb] */
48578   {
48579     M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE, "bclr16-G-bit16-16-8-bit16-16-8-SB-relative", "bclr", 24,
48580     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48581   },
48582 /* bclr${G} ${BitBase16-16-s8}[fb] */
48583   {
48584     M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, "bclr16-G-bit16-16-8-bit16-16-8-FB-relative", "bclr", 24,
48585     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48586   },
48587 /* bclr${S} ${BitBase16-8-u11-S}[sb] */
48588   {
48589     M32C_INSN_BCLR16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S, "bclr16-S-bit16-11-S-bit16-11-SB-relative-S", "bclr", 16,
48590     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48591   },
48592 /* bclr${G} ${Dsp-16-u16}[$Bit16An] */
48593   {
48594     M32C_INSN_BCLR16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE, "bclr16-G-bit16-16-16-bit16-16-16-An-relative", "bclr", 32,
48595     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48596   },
48597 /* bclr${G} ${BitBase16-16-u16}[sb] */
48598   {
48599     M32C_INSN_BCLR16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE, "bclr16-G-bit16-16-16-bit16-16-16-SB-relative", "bclr", 32,
48600     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48601   },
48602 /* bclr${G} ${BitBase16-16-u16} */
48603   {
48604     M32C_INSN_BCLR16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, "bclr16-G-bit16-16-16-bit16-16-16-absolute", "bclr", 32,
48605     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48606   },
48607 /* bclr${G} [$Bit16An] */
48608   {
48609     M32C_INSN_BCLR16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT, "bclr16-G-bit16-16-basic-bit16-An-indirect", "bclr", 16,
48610     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48611   },
48612 /* band${X} $Bitno32Prefixed,$Bit32RnPrefixed */
48613   {
48614     M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "band", 24,
48615     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48616   },
48617 /* band${X} $Bitno32Prefixed,$Bit32AnPrefixed */
48618   {
48619     M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "band", 24,
48620     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48621   },
48622 /* band${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
48623   {
48624     M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "band", 24,
48625     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48626   },
48627 /* band${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
48628   {
48629     M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "band", 32,
48630     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48631   },
48632 /* band${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
48633   {
48634     M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "band", 40,
48635     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48636   },
48637 /* band${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
48638   {
48639     M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "band", 48,
48640     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48641   },
48642 /* band${X} ${BitBase32-24-u11-Prefixed}[sb] */
48643   {
48644     M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "band", 32,
48645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48646   },
48647 /* band${X} ${BitBase32-24-u19-Prefixed}[sb] */
48648   {
48649     M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "band", 40,
48650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48651   },
48652 /* band${X} ${BitBase32-24-s11-Prefixed}[fb] */
48653   {
48654     M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "band", 32,
48655     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48656   },
48657 /* band${X} ${BitBase32-24-s19-Prefixed}[fb] */
48658   {
48659     M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "band", 40,
48660     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48661   },
48662 /* band${X} ${BitBase32-24-u19-Prefixed} */
48663   {
48664     M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "band", 40,
48665     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48666   },
48667 /* band${X} ${BitBase32-24-u27-Prefixed} */
48668   {
48669     M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "band", 48,
48670     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48671   },
48672 /* band${X} $Bitno16R,$Bit16Rn */
48673   {
48674     M32C_INSN_BAND16_X_BIT16_16_BIT16_RN_DIRECT, "band16-X-bit16-16-bit16-Rn-direct", "band", 24,
48675     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48676   },
48677 /* band${X} $Bitno16R,$Bit16An */
48678   {
48679     M32C_INSN_BAND16_X_BIT16_16_BIT16_AN_DIRECT, "band16-X-bit16-16-bit16-An-direct", "band", 24,
48680     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48681   },
48682 /* band${X} [$Bit16An] */
48683   {
48684     M32C_INSN_BAND16_X_BIT16_16_BIT16_AN_INDIRECT, "band16-X-bit16-16-bit16-An-indirect", "band", 16,
48685     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48686   },
48687 /* band${X} ${Dsp-16-u8}[$Bit16An] */
48688   {
48689     M32C_INSN_BAND16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "band16-X-bit16-16-bit16-16-8-An-relative", "band", 24,
48690     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48691   },
48692 /* band${X} ${Dsp-16-u16}[$Bit16An] */
48693   {
48694     M32C_INSN_BAND16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "band16-X-bit16-16-bit16-16-16-An-relative", "band", 32,
48695     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48696   },
48697 /* band${X} ${BitBase16-16-u8}[sb] */
48698   {
48699     M32C_INSN_BAND16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "band16-X-bit16-16-bit16-16-8-SB-relative", "band", 24,
48700     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48701   },
48702 /* band${X} ${BitBase16-16-u16}[sb] */
48703   {
48704     M32C_INSN_BAND16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "band16-X-bit16-16-bit16-16-16-SB-relative", "band", 32,
48705     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48706   },
48707 /* band${X} ${BitBase16-16-s8}[fb] */
48708   {
48709     M32C_INSN_BAND16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "band16-X-bit16-16-bit16-16-8-FB-relative", "band", 24,
48710     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48711   },
48712 /* band${X} ${BitBase16-16-u16} */
48713   {
48714     M32C_INSN_BAND16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "band16-X-bit16-16-bit16-16-16-absolute", "band", 32,
48715     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48716   },
48717 /* and.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
48718   {
48719     M32C_INSN_AND32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "and32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "and.w", 32,
48720     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48721   },
48722 /* and.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
48723   {
48724     M32C_INSN_AND32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "and32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "and.w", 32,
48725     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48726   },
48727 /* and.w${S} #${Imm-24-HI},${Dsp-8-u16} */
48728   {
48729     M32C_INSN_AND32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "and32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "and.w", 40,
48730     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48731   },
48732 /* and.w${S} #${Imm-8-HI},r0 */
48733   {
48734     M32C_INSN_AND32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "and32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "and.w", 24,
48735     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48736   },
48737 /* and.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
48738   {
48739     M32C_INSN_AND32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "and32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "and.b", 24,
48740     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48741   },
48742 /* and.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
48743   {
48744     M32C_INSN_AND32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "and32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "and.b", 24,
48745     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48746   },
48747 /* and.b${S} #${Imm-24-QI},${Dsp-8-u16} */
48748   {
48749     M32C_INSN_AND32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "and32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "and.b", 32,
48750     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48751   },
48752 /* and.b${S} #${Imm-8-QI},r0l */
48753   {
48754     M32C_INSN_AND32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "and32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "and.b", 16,
48755     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48756   },
48757 /* and.b${S} ${SrcDst16-r0l-r0h-S-normal} */
48758   {
48759     M32C_INSN_AND16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, "and16.b.S-r0l-r0h-srcdst16-r0l-r0h-S-derived", "and.b", 8,
48760     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48761   },
48762 /* and.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
48763   {
48764     M32C_INSN_AND16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, "and16.b.S-src2-src16-2-S-8-SB-relative-QI", "and.b", 16,
48765     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48766   },
48767 /* and.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
48768   {
48769     M32C_INSN_AND16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, "and16.b.S-src2-src16-2-S-8-FB-relative-QI", "and.b", 16,
48770     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48771   },
48772 /* and.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
48773   {
48774     M32C_INSN_AND16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, "and16.b.S-src2-src16-2-S-16-absolute-QI", "and.b", 24,
48775     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48776   },
48777 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
48778   {
48779     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 24,
48780     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48781   },
48782 /* and.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
48783   {
48784     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 24,
48785     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48786   },
48787 /* and.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
48788   {
48789     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 24,
48790     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48791   },
48792 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
48793   {
48794     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 24,
48795     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48796   },
48797 /* and.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
48798   {
48799     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 24,
48800     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48801   },
48802 /* and.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
48803   {
48804     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 24,
48805     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48806   },
48807 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
48808   {
48809     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 24,
48810     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48811   },
48812 /* and.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
48813   {
48814     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 24,
48815     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48816   },
48817 /* and.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
48818   {
48819     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 24,
48820     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48821   },
48822 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
48823   {
48824     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "and.w", 32,
48825     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48826   },
48827 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
48828   {
48829     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "and.w", 32,
48830     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48831   },
48832 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
48833   {
48834     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "and.w", 32,
48835     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48836   },
48837 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
48838   {
48839     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "and.w", 40,
48840     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48841   },
48842 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
48843   {
48844     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "and.w", 40,
48845     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48846   },
48847 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
48848   {
48849     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "and.w", 40,
48850     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48851   },
48852 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
48853   {
48854     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "and.w", 48,
48855     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48856   },
48857 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
48858   {
48859     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "and.w", 48,
48860     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48861   },
48862 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
48863   {
48864     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "and.w", 48,
48865     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48866   },
48867 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
48868   {
48869     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "and.w", 32,
48870     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48871   },
48872 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
48873   {
48874     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "and.w", 32,
48875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48876   },
48877 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
48878   {
48879     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "and.w", 32,
48880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48881   },
48882 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
48883   {
48884     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "and.w", 40,
48885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48886   },
48887 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
48888   {
48889     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "and.w", 40,
48890     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48891   },
48892 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
48893   {
48894     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "and.w", 40,
48895     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48896   },
48897 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
48898   {
48899     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "and.w", 32,
48900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48901   },
48902 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
48903   {
48904     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "and.w", 32,
48905     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48906   },
48907 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
48908   {
48909     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "and.w", 32,
48910     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48911   },
48912 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
48913   {
48914     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "and.w", 40,
48915     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48916   },
48917 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
48918   {
48919     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "and.w", 40,
48920     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48921   },
48922 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
48923   {
48924     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "and.w", 40,
48925     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48926   },
48927 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
48928   {
48929     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "and.w", 40,
48930     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48931   },
48932 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
48933   {
48934     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "and.w", 40,
48935     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48936   },
48937 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
48938   {
48939     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "and.w", 40,
48940     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48941   },
48942 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
48943   {
48944     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "and.w", 48,
48945     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48946   },
48947 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
48948   {
48949     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "and.w", 48,
48950     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48951   },
48952 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
48953   {
48954     M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "and.w", 48,
48955     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48956   },
48957 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
48958   {
48959     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 32,
48960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48961   },
48962 /* and.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
48963   {
48964     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 32,
48965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48966   },
48967 /* and.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
48968   {
48969     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 32,
48970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48971   },
48972 /* and.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
48973   {
48974     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 32,
48975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48976   },
48977 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
48978   {
48979     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 32,
48980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48981   },
48982 /* and.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
48983   {
48984     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 32,
48985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48986   },
48987 /* and.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
48988   {
48989     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 32,
48990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48991   },
48992 /* and.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
48993   {
48994     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 32,
48995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48996   },
48997 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
48998   {
48999     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 32,
49000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49001   },
49002 /* and.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
49003   {
49004     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 32,
49005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49006   },
49007 /* and.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
49008   {
49009     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 32,
49010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49011   },
49012 /* and.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
49013   {
49014     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 32,
49015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49016   },
49017 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
49018   {
49019     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "and.w", 40,
49020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49021   },
49022 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
49023   {
49024     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "and.w", 40,
49025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49026   },
49027 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
49028   {
49029     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "and.w", 40,
49030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49031   },
49032 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
49033   {
49034     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "and.w", 40,
49035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49036   },
49037 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
49038   {
49039     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "and.w", 48,
49040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49041   },
49042 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
49043   {
49044     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "and.w", 48,
49045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49046   },
49047 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
49048   {
49049     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "and.w", 48,
49050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49051   },
49052 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
49053   {
49054     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "and.w", 48,
49055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49056   },
49057 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
49058   {
49059     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "and.w", 56,
49060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49061   },
49062 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
49063   {
49064     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "and.w", 56,
49065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49066   },
49067 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
49068   {
49069     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "and.w", 56,
49070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49071   },
49072 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
49073   {
49074     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "and.w", 56,
49075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49076   },
49077 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
49078   {
49079     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "and.w", 40,
49080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49081   },
49082 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
49083   {
49084     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "and.w", 40,
49085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49086   },
49087 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
49088   {
49089     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "and.w", 40,
49090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49091   },
49092 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
49093   {
49094     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "and.w", 40,
49095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49096   },
49097 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
49098   {
49099     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "and.w", 48,
49100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49101   },
49102 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
49103   {
49104     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "and.w", 48,
49105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49106   },
49107 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
49108   {
49109     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "and.w", 48,
49110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49111   },
49112 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
49113   {
49114     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "and.w", 48,
49115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49116   },
49117 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
49118   {
49119     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "and.w", 40,
49120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49121   },
49122 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
49123   {
49124     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "and.w", 40,
49125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49126   },
49127 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
49128   {
49129     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "and.w", 40,
49130     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49131   },
49132 /* and.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
49133   {
49134     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "and.w", 40,
49135     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49136   },
49137 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
49138   {
49139     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "and.w", 48,
49140     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49141   },
49142 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
49143   {
49144     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "and.w", 48,
49145     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49146   },
49147 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
49148   {
49149     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "and.w", 48,
49150     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49151   },
49152 /* and.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
49153   {
49154     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "and.w", 48,
49155     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49156   },
49157 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
49158   {
49159     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "and.w", 48,
49160     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49161   },
49162 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
49163   {
49164     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "and.w", 48,
49165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49166   },
49167 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
49168   {
49169     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "and.w", 48,
49170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49171   },
49172 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
49173   {
49174     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "and.w", 48,
49175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49176   },
49177 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
49178   {
49179     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "and.w", 56,
49180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49181   },
49182 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
49183   {
49184     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "and.w", 56,
49185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49186   },
49187 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
49188   {
49189     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "and.w", 56,
49190     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49191   },
49192 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
49193   {
49194     M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "and.w", 56,
49195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49196   },
49197 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
49198   {
49199     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 40,
49200     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49201   },
49202 /* and.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
49203   {
49204     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 40,
49205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49206   },
49207 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
49208   {
49209     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 40,
49210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49211   },
49212 /* and.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
49213   {
49214     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 40,
49215     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49216   },
49217 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
49218   {
49219     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 40,
49220     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49221   },
49222 /* and.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
49223   {
49224     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 40,
49225     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49226   },
49227 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
49228   {
49229     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "and.w", 48,
49230     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49231   },
49232 /* and.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
49233   {
49234     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "and.w", 48,
49235     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49236   },
49237 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
49238   {
49239     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "and.w", 56,
49240     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49241   },
49242 /* and.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
49243   {
49244     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "and.w", 56,
49245     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49246   },
49247 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
49248   {
49249     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "and.w", 64,
49250     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49251   },
49252 /* and.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
49253   {
49254     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "and.w", 64,
49255     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49256   },
49257 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
49258   {
49259     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "and.w", 48,
49260     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49261   },
49262 /* and.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
49263   {
49264     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "and.w", 48,
49265     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49266   },
49267 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
49268   {
49269     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "and.w", 56,
49270     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49271   },
49272 /* and.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
49273   {
49274     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "and.w", 56,
49275     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49276   },
49277 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
49278   {
49279     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "and.w", 48,
49280     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49281   },
49282 /* and.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
49283   {
49284     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "and.w", 48,
49285     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49286   },
49287 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
49288   {
49289     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "and.w", 56,
49290     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49291   },
49292 /* and.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
49293   {
49294     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "and.w", 56,
49295     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49296   },
49297 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
49298   {
49299     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "and.w", 56,
49300     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49301   },
49302 /* and.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
49303   {
49304     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "and.w", 56,
49305     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49306   },
49307 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
49308   {
49309     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "and.w", 64,
49310     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49311   },
49312 /* and.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
49313   {
49314     M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "and.w", 64,
49315     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49316   },
49317 /* and.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
49318   {
49319     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 16,
49320     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49321   },
49322 /* and.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
49323   {
49324     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 16,
49325     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49326   },
49327 /* and.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
49328   {
49329     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 16,
49330     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49331   },
49332 /* and.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
49333   {
49334     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 16,
49335     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49336   },
49337 /* and.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
49338   {
49339     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 16,
49340     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49341   },
49342 /* and.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
49343   {
49344     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 16,
49345     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49346   },
49347 /* and.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
49348   {
49349     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 16,
49350     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49351   },
49352 /* and.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
49353   {
49354     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 16,
49355     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49356   },
49357 /* and.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
49358   {
49359     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 16,
49360     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49361   },
49362 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
49363   {
49364     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "and.w", 24,
49365     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49366   },
49367 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
49368   {
49369     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "and.w", 24,
49370     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49371   },
49372 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
49373   {
49374     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "and.w", 24,
49375     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49376   },
49377 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
49378   {
49379     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "and.w", 32,
49380     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49381   },
49382 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
49383   {
49384     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "and.w", 32,
49385     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49386   },
49387 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
49388   {
49389     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "and.w", 32,
49390     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49391   },
49392 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
49393   {
49394     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "and.w", 40,
49395     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49396   },
49397 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
49398   {
49399     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "and.w", 40,
49400     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49401   },
49402 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
49403   {
49404     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "and.w", 40,
49405     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49406   },
49407 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
49408   {
49409     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "and.w", 24,
49410     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49411   },
49412 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
49413   {
49414     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "and.w", 24,
49415     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49416   },
49417 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
49418   {
49419     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "and.w", 24,
49420     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49421   },
49422 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
49423   {
49424     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "and.w", 32,
49425     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49426   },
49427 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
49428   {
49429     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "and.w", 32,
49430     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49431   },
49432 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
49433   {
49434     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "and.w", 32,
49435     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49436   },
49437 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
49438   {
49439     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "and.w", 24,
49440     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49441   },
49442 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
49443   {
49444     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "and.w", 24,
49445     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49446   },
49447 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
49448   {
49449     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "and.w", 24,
49450     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49451   },
49452 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
49453   {
49454     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "and.w", 32,
49455     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49456   },
49457 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
49458   {
49459     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "and.w", 32,
49460     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49461   },
49462 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
49463   {
49464     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "and.w", 32,
49465     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49466   },
49467 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
49468   {
49469     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "and.w", 32,
49470     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49471   },
49472 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
49473   {
49474     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "and.w", 32,
49475     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49476   },
49477 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
49478   {
49479     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "and.w", 32,
49480     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49481   },
49482 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
49483   {
49484     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "and.w", 40,
49485     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49486   },
49487 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
49488   {
49489     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "and.w", 40,
49490     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49491   },
49492 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
49493   {
49494     M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "and.w", 40,
49495     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49496   },
49497 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
49498   {
49499     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 24,
49500     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49501   },
49502 /* and.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
49503   {
49504     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 24,
49505     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49506   },
49507 /* and.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
49508   {
49509     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 24,
49510     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49511   },
49512 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
49513   {
49514     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 24,
49515     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49516   },
49517 /* and.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
49518   {
49519     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 24,
49520     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49521   },
49522 /* and.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
49523   {
49524     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 24,
49525     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49526   },
49527 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
49528   {
49529     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 24,
49530     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49531   },
49532 /* and.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
49533   {
49534     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 24,
49535     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49536   },
49537 /* and.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
49538   {
49539     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 24,
49540     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49541   },
49542 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
49543   {
49544     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "and.b", 32,
49545     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49546   },
49547 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
49548   {
49549     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "and.b", 32,
49550     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49551   },
49552 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
49553   {
49554     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "and.b", 32,
49555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49556   },
49557 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
49558   {
49559     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "and.b", 40,
49560     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49561   },
49562 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
49563   {
49564     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "and.b", 40,
49565     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49566   },
49567 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
49568   {
49569     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "and.b", 40,
49570     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49571   },
49572 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
49573   {
49574     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "and.b", 48,
49575     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49576   },
49577 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
49578   {
49579     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "and.b", 48,
49580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49581   },
49582 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
49583   {
49584     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "and.b", 48,
49585     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49586   },
49587 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
49588   {
49589     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "and.b", 32,
49590     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49591   },
49592 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
49593   {
49594     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "and.b", 32,
49595     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49596   },
49597 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
49598   {
49599     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "and.b", 32,
49600     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49601   },
49602 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
49603   {
49604     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "and.b", 40,
49605     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49606   },
49607 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
49608   {
49609     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "and.b", 40,
49610     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49611   },
49612 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
49613   {
49614     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "and.b", 40,
49615     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49616   },
49617 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
49618   {
49619     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "and.b", 32,
49620     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49621   },
49622 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
49623   {
49624     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "and.b", 32,
49625     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49626   },
49627 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
49628   {
49629     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "and.b", 32,
49630     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49631   },
49632 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
49633   {
49634     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "and.b", 40,
49635     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49636   },
49637 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
49638   {
49639     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "and.b", 40,
49640     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49641   },
49642 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
49643   {
49644     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "and.b", 40,
49645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49646   },
49647 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
49648   {
49649     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "and.b", 40,
49650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49651   },
49652 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
49653   {
49654     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "and.b", 40,
49655     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49656   },
49657 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
49658   {
49659     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "and.b", 40,
49660     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49661   },
49662 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
49663   {
49664     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "and.b", 48,
49665     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49666   },
49667 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
49668   {
49669     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "and.b", 48,
49670     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49671   },
49672 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
49673   {
49674     M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "and.b", 48,
49675     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49676   },
49677 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
49678   {
49679     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 32,
49680     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49681   },
49682 /* and.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
49683   {
49684     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 32,
49685     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49686   },
49687 /* and.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
49688   {
49689     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 32,
49690     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49691   },
49692 /* and.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
49693   {
49694     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 32,
49695     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49696   },
49697 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
49698   {
49699     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 32,
49700     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49701   },
49702 /* and.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
49703   {
49704     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 32,
49705     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49706   },
49707 /* and.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
49708   {
49709     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 32,
49710     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49711   },
49712 /* and.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
49713   {
49714     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 32,
49715     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49716   },
49717 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
49718   {
49719     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 32,
49720     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49721   },
49722 /* and.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
49723   {
49724     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 32,
49725     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49726   },
49727 /* and.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
49728   {
49729     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 32,
49730     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49731   },
49732 /* and.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
49733   {
49734     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 32,
49735     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49736   },
49737 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
49738   {
49739     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "and.b", 40,
49740     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49741   },
49742 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
49743   {
49744     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "and.b", 40,
49745     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49746   },
49747 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
49748   {
49749     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "and.b", 40,
49750     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49751   },
49752 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
49753   {
49754     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "and.b", 40,
49755     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49756   },
49757 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
49758   {
49759     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "and.b", 48,
49760     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49761   },
49762 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
49763   {
49764     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "and.b", 48,
49765     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49766   },
49767 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
49768   {
49769     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "and.b", 48,
49770     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49771   },
49772 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
49773   {
49774     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "and.b", 48,
49775     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49776   },
49777 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
49778   {
49779     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "and.b", 56,
49780     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49781   },
49782 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
49783   {
49784     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "and.b", 56,
49785     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49786   },
49787 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
49788   {
49789     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "and.b", 56,
49790     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49791   },
49792 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
49793   {
49794     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "and.b", 56,
49795     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49796   },
49797 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
49798   {
49799     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "and.b", 40,
49800     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49801   },
49802 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
49803   {
49804     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "and.b", 40,
49805     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49806   },
49807 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
49808   {
49809     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "and.b", 40,
49810     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49811   },
49812 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
49813   {
49814     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "and.b", 40,
49815     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49816   },
49817 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
49818   {
49819     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "and.b", 48,
49820     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49821   },
49822 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
49823   {
49824     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "and.b", 48,
49825     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49826   },
49827 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
49828   {
49829     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "and.b", 48,
49830     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49831   },
49832 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
49833   {
49834     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "and.b", 48,
49835     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49836   },
49837 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
49838   {
49839     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "and.b", 40,
49840     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49841   },
49842 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
49843   {
49844     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "and.b", 40,
49845     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49846   },
49847 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
49848   {
49849     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "and.b", 40,
49850     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49851   },
49852 /* and.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
49853   {
49854     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "and.b", 40,
49855     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49856   },
49857 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
49858   {
49859     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "and.b", 48,
49860     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49861   },
49862 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
49863   {
49864     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "and.b", 48,
49865     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49866   },
49867 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
49868   {
49869     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "and.b", 48,
49870     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49871   },
49872 /* and.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
49873   {
49874     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "and.b", 48,
49875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49876   },
49877 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
49878   {
49879     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "and.b", 48,
49880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49881   },
49882 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
49883   {
49884     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "and.b", 48,
49885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49886   },
49887 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
49888   {
49889     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "and.b", 48,
49890     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49891   },
49892 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
49893   {
49894     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "and.b", 48,
49895     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49896   },
49897 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
49898   {
49899     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "and.b", 56,
49900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49901   },
49902 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
49903   {
49904     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "and.b", 56,
49905     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49906   },
49907 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
49908   {
49909     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "and.b", 56,
49910     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49911   },
49912 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
49913   {
49914     M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "and.b", 56,
49915     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49916   },
49917 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
49918   {
49919     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 40,
49920     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49921   },
49922 /* and.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
49923   {
49924     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 40,
49925     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49926   },
49927 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
49928   {
49929     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 40,
49930     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49931   },
49932 /* and.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
49933   {
49934     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 40,
49935     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49936   },
49937 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
49938   {
49939     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 40,
49940     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49941   },
49942 /* and.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
49943   {
49944     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 40,
49945     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49946   },
49947 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
49948   {
49949     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "and.b", 48,
49950     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49951   },
49952 /* and.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
49953   {
49954     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "and.b", 48,
49955     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49956   },
49957 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
49958   {
49959     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "and.b", 56,
49960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49961   },
49962 /* and.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
49963   {
49964     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "and.b", 56,
49965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49966   },
49967 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
49968   {
49969     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "and.b", 64,
49970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49971   },
49972 /* and.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
49973   {
49974     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "and.b", 64,
49975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49976   },
49977 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
49978   {
49979     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "and.b", 48,
49980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49981   },
49982 /* and.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
49983   {
49984     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "and.b", 48,
49985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49986   },
49987 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
49988   {
49989     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "and.b", 56,
49990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49991   },
49992 /* and.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
49993   {
49994     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "and.b", 56,
49995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49996   },
49997 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
49998   {
49999     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "and.b", 48,
50000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50001   },
50002 /* and.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
50003   {
50004     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "and.b", 48,
50005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50006   },
50007 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
50008   {
50009     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "and.b", 56,
50010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50011   },
50012 /* and.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
50013   {
50014     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "and.b", 56,
50015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50016   },
50017 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
50018   {
50019     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "and.b", 56,
50020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50021   },
50022 /* and.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
50023   {
50024     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "and.b", 56,
50025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50026   },
50027 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
50028   {
50029     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "and.b", 64,
50030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50031   },
50032 /* and.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
50033   {
50034     M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "and.b", 64,
50035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50036   },
50037 /* and.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
50038   {
50039     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 16,
50040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50041   },
50042 /* and.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
50043   {
50044     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 16,
50045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50046   },
50047 /* and.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
50048   {
50049     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 16,
50050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50051   },
50052 /* and.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
50053   {
50054     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 16,
50055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50056   },
50057 /* and.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
50058   {
50059     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 16,
50060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50061   },
50062 /* and.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
50063   {
50064     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 16,
50065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50066   },
50067 /* and.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
50068   {
50069     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 16,
50070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50071   },
50072 /* and.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
50073   {
50074     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 16,
50075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50076   },
50077 /* and.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
50078   {
50079     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 16,
50080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50081   },
50082 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
50083   {
50084     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "and.b", 24,
50085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50086   },
50087 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
50088   {
50089     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "and.b", 24,
50090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50091   },
50092 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
50093   {
50094     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "and.b", 24,
50095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50096   },
50097 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
50098   {
50099     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "and.b", 32,
50100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50101   },
50102 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
50103   {
50104     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "and.b", 32,
50105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50106   },
50107 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
50108   {
50109     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "and.b", 32,
50110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50111   },
50112 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
50113   {
50114     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "and.b", 40,
50115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50116   },
50117 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
50118   {
50119     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "and.b", 40,
50120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50121   },
50122 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
50123   {
50124     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "and.b", 40,
50125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50126   },
50127 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
50128   {
50129     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "and.b", 24,
50130     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50131   },
50132 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
50133   {
50134     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "and.b", 24,
50135     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50136   },
50137 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
50138   {
50139     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "and.b", 24,
50140     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50141   },
50142 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
50143   {
50144     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "and.b", 32,
50145     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50146   },
50147 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
50148   {
50149     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "and.b", 32,
50150     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50151   },
50152 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
50153   {
50154     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "and.b", 32,
50155     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50156   },
50157 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
50158   {
50159     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "and.b", 24,
50160     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50161   },
50162 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
50163   {
50164     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "and.b", 24,
50165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50166   },
50167 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
50168   {
50169     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "and.b", 24,
50170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50171   },
50172 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
50173   {
50174     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "and.b", 32,
50175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50176   },
50177 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
50178   {
50179     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "and.b", 32,
50180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50181   },
50182 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
50183   {
50184     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "and.b", 32,
50185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50186   },
50187 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
50188   {
50189     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "and.b", 32,
50190     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50191   },
50192 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
50193   {
50194     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "and.b", 32,
50195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50196   },
50197 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
50198   {
50199     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "and.b", 32,
50200     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50201   },
50202 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
50203   {
50204     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "and.b", 40,
50205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50206   },
50207 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
50208   {
50209     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "and.b", 40,
50210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50211   },
50212 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
50213   {
50214     M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "and.b", 40,
50215     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50216   },
50217 /* and.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
50218   {
50219     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "and.w", 24,
50220     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50221   },
50222 /* and.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
50223   {
50224     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "and.w", 24,
50225     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50226   },
50227 /* and.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
50228   {
50229     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "and.w", 24,
50230     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50231   },
50232 /* and.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
50233   {
50234     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "and.w", 24,
50235     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50236   },
50237 /* and.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
50238   {
50239     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "and.w", 24,
50240     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50241   },
50242 /* and.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
50243   {
50244     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "and.w", 24,
50245     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50246   },
50247 /* and.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
50248   {
50249     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "and.w", 24,
50250     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50251   },
50252 /* and.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
50253   {
50254     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "and.w", 24,
50255     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50256   },
50257 /* and.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
50258   {
50259     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "and.w", 24,
50260     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50261   },
50262 /* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
50263   {
50264     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "and.w", 32,
50265     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50266   },
50267 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
50268   {
50269     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "and.w", 32,
50270     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50271   },
50272 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
50273   {
50274     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "and.w", 32,
50275     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50276   },
50277 /* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
50278   {
50279     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "and.w", 40,
50280     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50281   },
50282 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
50283   {
50284     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "and.w", 40,
50285     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50286   },
50287 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
50288   {
50289     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "and.w", 40,
50290     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50291   },
50292 /* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
50293   {
50294     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "and.w", 32,
50295     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50296   },
50297 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
50298   {
50299     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "and.w", 32,
50300     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50301   },
50302 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
50303   {
50304     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "and.w", 32,
50305     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50306   },
50307 /* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
50308   {
50309     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "and.w", 40,
50310     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50311   },
50312 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
50313   {
50314     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "and.w", 40,
50315     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50316   },
50317 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
50318   {
50319     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "and.w", 40,
50320     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50321   },
50322 /* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
50323   {
50324     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "and.w", 32,
50325     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50326   },
50327 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
50328   {
50329     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "and.w", 32,
50330     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50331   },
50332 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
50333   {
50334     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "and.w", 32,
50335     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50336   },
50337 /* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
50338   {
50339     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "and.w", 40,
50340     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50341   },
50342 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
50343   {
50344     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "and.w", 40,
50345     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50346   },
50347 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
50348   {
50349     M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "and.w", 40,
50350     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50351   },
50352 /* and.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
50353   {
50354     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "and.w", 32,
50355     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50356   },
50357 /* and.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
50358   {
50359     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "and.w", 32,
50360     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50361   },
50362 /* and.w${G} ${Dsp-16-u16},$Dst16RnHI */
50363   {
50364     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "and.w", 32,
50365     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50366   },
50367 /* and.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
50368   {
50369     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "and.w", 32,
50370     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50371   },
50372 /* and.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
50373   {
50374     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "and.w", 32,
50375     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50376   },
50377 /* and.w${G} ${Dsp-16-u16},$Dst16AnHI */
50378   {
50379     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "and.w", 32,
50380     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50381   },
50382 /* and.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
50383   {
50384     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "and.w", 32,
50385     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50386   },
50387 /* and.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
50388   {
50389     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "and.w", 32,
50390     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50391   },
50392 /* and.w${G} ${Dsp-16-u16},[$Dst16An] */
50393   {
50394     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "and.w", 32,
50395     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50396   },
50397 /* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
50398   {
50399     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "and.w", 40,
50400     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50401   },
50402 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
50403   {
50404     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "and.w", 40,
50405     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50406   },
50407 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
50408   {
50409     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "and.w", 40,
50410     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50411   },
50412 /* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
50413   {
50414     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "and.w", 48,
50415     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50416   },
50417 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
50418   {
50419     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "and.w", 48,
50420     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50421   },
50422 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
50423   {
50424     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "and.w", 48,
50425     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50426   },
50427 /* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
50428   {
50429     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "and.w", 40,
50430     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50431   },
50432 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
50433   {
50434     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "and.w", 40,
50435     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50436   },
50437 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
50438   {
50439     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "and.w", 40,
50440     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50441   },
50442 /* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
50443   {
50444     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "and.w", 48,
50445     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50446   },
50447 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
50448   {
50449     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "and.w", 48,
50450     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50451   },
50452 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
50453   {
50454     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "and.w", 48,
50455     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50456   },
50457 /* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
50458   {
50459     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "and.w", 40,
50460     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50461   },
50462 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
50463   {
50464     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "and.w", 40,
50465     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50466   },
50467 /* and.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
50468   {
50469     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "and.w", 40,
50470     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50471   },
50472 /* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
50473   {
50474     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "and.w", 48,
50475     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50476   },
50477 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
50478   {
50479     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "and.w", 48,
50480     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50481   },
50482 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
50483   {
50484     M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "and.w", 48,
50485     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50486   },
50487 /* and.w${G} $Src16RnHI,$Dst16RnHI */
50488   {
50489     M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "and.w", 16,
50490     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50491   },
50492 /* and.w${G} $Src16AnHI,$Dst16RnHI */
50493   {
50494     M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "and.w", 16,
50495     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50496   },
50497 /* and.w${G} [$Src16An],$Dst16RnHI */
50498   {
50499     M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "and.w", 16,
50500     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50501   },
50502 /* and.w${G} $Src16RnHI,$Dst16AnHI */
50503   {
50504     M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "and.w", 16,
50505     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50506   },
50507 /* and.w${G} $Src16AnHI,$Dst16AnHI */
50508   {
50509     M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "and.w", 16,
50510     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50511   },
50512 /* and.w${G} [$Src16An],$Dst16AnHI */
50513   {
50514     M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "and.w", 16,
50515     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50516   },
50517 /* and.w${G} $Src16RnHI,[$Dst16An] */
50518   {
50519     M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "and.w", 16,
50520     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50521   },
50522 /* and.w${G} $Src16AnHI,[$Dst16An] */
50523   {
50524     M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "and.w", 16,
50525     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50526   },
50527 /* and.w${G} [$Src16An],[$Dst16An] */
50528   {
50529     M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "and.w", 16,
50530     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50531   },
50532 /* and.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
50533   {
50534     M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "and.w", 24,
50535     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50536   },
50537 /* and.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
50538   {
50539     M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "and.w", 24,
50540     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50541   },
50542 /* and.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
50543   {
50544     M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "and.w", 24,
50545     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50546   },
50547 /* and.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
50548   {
50549     M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "and.w", 32,
50550     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50551   },
50552 /* and.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
50553   {
50554     M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "and.w", 32,
50555     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50556   },
50557 /* and.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
50558   {
50559     M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "and.w", 32,
50560     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50561   },
50562 /* and.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
50563   {
50564     M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "and.w", 24,
50565     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50566   },
50567 /* and.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
50568   {
50569     M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "and.w", 24,
50570     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50571   },
50572 /* and.w${G} [$Src16An],${Dsp-16-u8}[sb] */
50573   {
50574     M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "and.w", 24,
50575     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50576   },
50577 /* and.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
50578   {
50579     M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "and.w", 32,
50580     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50581   },
50582 /* and.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
50583   {
50584     M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "and.w", 32,
50585     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50586   },
50587 /* and.w${G} [$Src16An],${Dsp-16-u16}[sb] */
50588   {
50589     M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "and.w", 32,
50590     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50591   },
50592 /* and.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
50593   {
50594     M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "and.w", 24,
50595     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50596   },
50597 /* and.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
50598   {
50599     M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "and.w", 24,
50600     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50601   },
50602 /* and.w${G} [$Src16An],${Dsp-16-s8}[fb] */
50603   {
50604     M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "and.w", 24,
50605     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50606   },
50607 /* and.w${G} $Src16RnHI,${Dsp-16-u16} */
50608   {
50609     M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "and.w", 32,
50610     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50611   },
50612 /* and.w${G} $Src16AnHI,${Dsp-16-u16} */
50613   {
50614     M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "and.w", 32,
50615     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50616   },
50617 /* and.w${G} [$Src16An],${Dsp-16-u16} */
50618   {
50619     M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "and.w", 32,
50620     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50621   },
50622 /* and.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
50623   {
50624     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "and.b", 24,
50625     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50626   },
50627 /* and.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
50628   {
50629     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "and.b", 24,
50630     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50631   },
50632 /* and.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
50633   {
50634     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "and.b", 24,
50635     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50636   },
50637 /* and.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
50638   {
50639     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "and.b", 24,
50640     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50641   },
50642 /* and.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
50643   {
50644     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "and.b", 24,
50645     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50646   },
50647 /* and.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
50648   {
50649     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "and.b", 24,
50650     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50651   },
50652 /* and.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
50653   {
50654     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "and.b", 24,
50655     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50656   },
50657 /* and.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
50658   {
50659     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "and.b", 24,
50660     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50661   },
50662 /* and.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
50663   {
50664     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "and.b", 24,
50665     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50666   },
50667 /* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
50668   {
50669     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "and.b", 32,
50670     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50671   },
50672 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
50673   {
50674     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "and.b", 32,
50675     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50676   },
50677 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
50678   {
50679     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "and.b", 32,
50680     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50681   },
50682 /* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
50683   {
50684     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "and.b", 40,
50685     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50686   },
50687 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
50688   {
50689     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "and.b", 40,
50690     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50691   },
50692 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
50693   {
50694     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "and.b", 40,
50695     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50696   },
50697 /* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
50698   {
50699     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "and.b", 32,
50700     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50701   },
50702 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
50703   {
50704     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "and.b", 32,
50705     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50706   },
50707 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
50708   {
50709     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "and.b", 32,
50710     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50711   },
50712 /* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
50713   {
50714     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "and.b", 40,
50715     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50716   },
50717 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
50718   {
50719     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "and.b", 40,
50720     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50721   },
50722 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
50723   {
50724     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "and.b", 40,
50725     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50726   },
50727 /* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
50728   {
50729     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "and.b", 32,
50730     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50731   },
50732 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
50733   {
50734     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "and.b", 32,
50735     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50736   },
50737 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
50738   {
50739     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "and.b", 32,
50740     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50741   },
50742 /* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
50743   {
50744     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "and.b", 40,
50745     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50746   },
50747 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
50748   {
50749     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "and.b", 40,
50750     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50751   },
50752 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
50753   {
50754     M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "and.b", 40,
50755     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50756   },
50757 /* and.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
50758   {
50759     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "and.b", 32,
50760     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50761   },
50762 /* and.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
50763   {
50764     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "and.b", 32,
50765     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50766   },
50767 /* and.b${G} ${Dsp-16-u16},$Dst16RnQI */
50768   {
50769     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "and.b", 32,
50770     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50771   },
50772 /* and.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
50773   {
50774     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "and.b", 32,
50775     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50776   },
50777 /* and.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
50778   {
50779     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "and.b", 32,
50780     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50781   },
50782 /* and.b${G} ${Dsp-16-u16},$Dst16AnQI */
50783   {
50784     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "and.b", 32,
50785     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50786   },
50787 /* and.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
50788   {
50789     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "and.b", 32,
50790     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50791   },
50792 /* and.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
50793   {
50794     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "and.b", 32,
50795     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50796   },
50797 /* and.b${G} ${Dsp-16-u16},[$Dst16An] */
50798   {
50799     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "and.b", 32,
50800     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50801   },
50802 /* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
50803   {
50804     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "and.b", 40,
50805     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50806   },
50807 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
50808   {
50809     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "and.b", 40,
50810     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50811   },
50812 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
50813   {
50814     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "and.b", 40,
50815     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50816   },
50817 /* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
50818   {
50819     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "and.b", 48,
50820     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50821   },
50822 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
50823   {
50824     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "and.b", 48,
50825     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50826   },
50827 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
50828   {
50829     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "and.b", 48,
50830     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50831   },
50832 /* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
50833   {
50834     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "and.b", 40,
50835     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50836   },
50837 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
50838   {
50839     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "and.b", 40,
50840     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50841   },
50842 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
50843   {
50844     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "and.b", 40,
50845     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50846   },
50847 /* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
50848   {
50849     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "and.b", 48,
50850     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50851   },
50852 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
50853   {
50854     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "and.b", 48,
50855     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50856   },
50857 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
50858   {
50859     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "and.b", 48,
50860     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50861   },
50862 /* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
50863   {
50864     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "and.b", 40,
50865     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50866   },
50867 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
50868   {
50869     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "and.b", 40,
50870     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50871   },
50872 /* and.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
50873   {
50874     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "and.b", 40,
50875     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50876   },
50877 /* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
50878   {
50879     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "and.b", 48,
50880     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50881   },
50882 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
50883   {
50884     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "and.b", 48,
50885     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50886   },
50887 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
50888   {
50889     M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "and.b", 48,
50890     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50891   },
50892 /* and.b${G} $Src16RnQI,$Dst16RnQI */
50893   {
50894     M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "and.b", 16,
50895     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50896   },
50897 /* and.b${G} $Src16AnQI,$Dst16RnQI */
50898   {
50899     M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "and.b", 16,
50900     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50901   },
50902 /* and.b${G} [$Src16An],$Dst16RnQI */
50903   {
50904     M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "and.b", 16,
50905     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50906   },
50907 /* and.b${G} $Src16RnQI,$Dst16AnQI */
50908   {
50909     M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "and.b", 16,
50910     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50911   },
50912 /* and.b${G} $Src16AnQI,$Dst16AnQI */
50913   {
50914     M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "and.b", 16,
50915     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50916   },
50917 /* and.b${G} [$Src16An],$Dst16AnQI */
50918   {
50919     M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "and.b", 16,
50920     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50921   },
50922 /* and.b${G} $Src16RnQI,[$Dst16An] */
50923   {
50924     M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "and.b", 16,
50925     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50926   },
50927 /* and.b${G} $Src16AnQI,[$Dst16An] */
50928   {
50929     M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "and.b", 16,
50930     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50931   },
50932 /* and.b${G} [$Src16An],[$Dst16An] */
50933   {
50934     M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "and.b", 16,
50935     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50936   },
50937 /* and.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
50938   {
50939     M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "and.b", 24,
50940     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50941   },
50942 /* and.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
50943   {
50944     M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "and.b", 24,
50945     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50946   },
50947 /* and.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
50948   {
50949     M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "and.b", 24,
50950     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50951   },
50952 /* and.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
50953   {
50954     M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "and.b", 32,
50955     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50956   },
50957 /* and.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
50958   {
50959     M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "and.b", 32,
50960     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50961   },
50962 /* and.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
50963   {
50964     M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "and.b", 32,
50965     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50966   },
50967 /* and.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
50968   {
50969     M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "and.b", 24,
50970     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50971   },
50972 /* and.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
50973   {
50974     M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "and.b", 24,
50975     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50976   },
50977 /* and.b${G} [$Src16An],${Dsp-16-u8}[sb] */
50978   {
50979     M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "and.b", 24,
50980     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50981   },
50982 /* and.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
50983   {
50984     M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "and.b", 32,
50985     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50986   },
50987 /* and.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
50988   {
50989     M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "and.b", 32,
50990     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50991   },
50992 /* and.b${G} [$Src16An],${Dsp-16-u16}[sb] */
50993   {
50994     M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "and.b", 32,
50995     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50996   },
50997 /* and.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
50998   {
50999     M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "and.b", 24,
51000     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51001   },
51002 /* and.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
51003   {
51004     M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "and.b", 24,
51005     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51006   },
51007 /* and.b${G} [$Src16An],${Dsp-16-s8}[fb] */
51008   {
51009     M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "and.b", 24,
51010     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51011   },
51012 /* and.b${G} $Src16RnQI,${Dsp-16-u16} */
51013   {
51014     M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "and.b", 32,
51015     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51016   },
51017 /* and.b${G} $Src16AnQI,${Dsp-16-u16} */
51018   {
51019     M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "and.b", 32,
51020     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51021   },
51022 /* and.b${G} [$Src16An],${Dsp-16-u16} */
51023   {
51024     M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "and.b", 32,
51025     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51026   },
51027 /* and.b${S} #${Imm-8-QI},r0l */
51028   {
51029     M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "and16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "and.b", 16,
51030     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51031   },
51032 /* and.b${S} #${Imm-8-QI},r0h */
51033   {
51034     M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "and16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "and.b", 16,
51035     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51036   },
51037 /* and.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
51038   {
51039     M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "and16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "and.b", 24,
51040     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51041   },
51042 /* and.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
51043   {
51044     M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "and16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "and.b", 24,
51045     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51046   },
51047 /* and.b${S} #${Imm-8-QI},${Dsp-16-u16} */
51048   {
51049     M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "and16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "and.b", 32,
51050     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51051   },
51052 /* and.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
51053   {
51054     M32C_INSN_AND32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "and.w", 32,
51055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51056   },
51057 /* and.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
51058   {
51059     M32C_INSN_AND32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "and.w", 32,
51060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51061   },
51062 /* and.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
51063   {
51064     M32C_INSN_AND32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "and.w", 32,
51065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51066   },
51067 /* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
51068   {
51069     M32C_INSN_AND32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "and.w", 40,
51070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51071   },
51072 /* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
51073   {
51074     M32C_INSN_AND32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "and.w", 40,
51075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51076   },
51077 /* and.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
51078   {
51079     M32C_INSN_AND32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "and.w", 40,
51080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51081   },
51082 /* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
51083   {
51084     M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "and.w", 48,
51085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51086   },
51087 /* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
51088   {
51089     M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "and.w", 48,
51090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51091   },
51092 /* and.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
51093   {
51094     M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "and.w", 48,
51095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51096   },
51097 /* and.w${G} #${Imm-32-HI},${Dsp-16-u16} */
51098   {
51099     M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "and.w", 48,
51100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51101   },
51102 /* and.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
51103   {
51104     M32C_INSN_AND32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "and.w", 56,
51105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51106   },
51107 /* and.w${G} #${Imm-40-HI},${Dsp-16-u24} */
51108   {
51109     M32C_INSN_AND32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "and.w", 56,
51110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51111   },
51112 /* and.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
51113   {
51114     M32C_INSN_AND32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "and.b", 24,
51115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51116   },
51117 /* and.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
51118   {
51119     M32C_INSN_AND32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "and.b", 24,
51120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51121   },
51122 /* and.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
51123   {
51124     M32C_INSN_AND32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "and.b", 24,
51125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51126   },
51127 /* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
51128   {
51129     M32C_INSN_AND32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "and.b", 32,
51130     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51131   },
51132 /* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
51133   {
51134     M32C_INSN_AND32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "and.b", 32,
51135     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51136   },
51137 /* and.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
51138   {
51139     M32C_INSN_AND32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "and.b", 32,
51140     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51141   },
51142 /* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
51143   {
51144     M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "and.b", 40,
51145     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51146   },
51147 /* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
51148   {
51149     M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "and.b", 40,
51150     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51151   },
51152 /* and.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
51153   {
51154     M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "and.b", 40,
51155     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51156   },
51157 /* and.b${G} #${Imm-32-QI},${Dsp-16-u16} */
51158   {
51159     M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "and.b", 40,
51160     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51161   },
51162 /* and.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
51163   {
51164     M32C_INSN_AND32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "and.b", 48,
51165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51166   },
51167 /* and.b${G} #${Imm-40-QI},${Dsp-16-u24} */
51168   {
51169     M32C_INSN_AND32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "and.b", 48,
51170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51171   },
51172 /* and.w${G} #${Imm-16-HI},$Dst16RnHI */
51173   {
51174     M32C_INSN_AND16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "and16.w-imm-G-basic-dst16-Rn-direct-HI", "and.w", 32,
51175     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51176   },
51177 /* and.w${G} #${Imm-16-HI},$Dst16AnHI */
51178   {
51179     M32C_INSN_AND16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "and16.w-imm-G-basic-dst16-An-direct-HI", "and.w", 32,
51180     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51181   },
51182 /* and.w${G} #${Imm-16-HI},[$Dst16An] */
51183   {
51184     M32C_INSN_AND16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "and16.w-imm-G-basic-dst16-An-indirect-HI", "and.w", 32,
51185     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51186   },
51187 /* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
51188   {
51189     M32C_INSN_AND16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "and16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "and.w", 40,
51190     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51191   },
51192 /* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
51193   {
51194     M32C_INSN_AND16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "and16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "and.w", 40,
51195     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51196   },
51197 /* and.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
51198   {
51199     M32C_INSN_AND16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "and16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "and.w", 40,
51200     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51201   },
51202 /* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
51203   {
51204     M32C_INSN_AND16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "and16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "and.w", 48,
51205     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51206   },
51207 /* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
51208   {
51209     M32C_INSN_AND16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "and16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "and.w", 48,
51210     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51211   },
51212 /* and.w${G} #${Imm-32-HI},${Dsp-16-u16} */
51213   {
51214     M32C_INSN_AND16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "and16.w-imm-G-16-16-dst16-16-16-absolute-HI", "and.w", 48,
51215     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51216   },
51217 /* and.b${G} #${Imm-16-QI},$Dst16RnQI */
51218   {
51219     M32C_INSN_AND16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "and16.b-imm-G-basic-dst16-Rn-direct-QI", "and.b", 24,
51220     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51221   },
51222 /* and.b${G} #${Imm-16-QI},$Dst16AnQI */
51223   {
51224     M32C_INSN_AND16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "and16.b-imm-G-basic-dst16-An-direct-QI", "and.b", 24,
51225     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51226   },
51227 /* and.b${G} #${Imm-16-QI},[$Dst16An] */
51228   {
51229     M32C_INSN_AND16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "and16.b-imm-G-basic-dst16-An-indirect-QI", "and.b", 24,
51230     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51231   },
51232 /* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
51233   {
51234     M32C_INSN_AND16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "and16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "and.b", 32,
51235     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51236   },
51237 /* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
51238   {
51239     M32C_INSN_AND16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "and16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "and.b", 32,
51240     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51241   },
51242 /* and.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
51243   {
51244     M32C_INSN_AND16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "and16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "and.b", 32,
51245     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51246   },
51247 /* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
51248   {
51249     M32C_INSN_AND16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "and16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "and.b", 40,
51250     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51251   },
51252 /* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
51253   {
51254     M32C_INSN_AND16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "and16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "and.b", 40,
51255     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51256   },
51257 /* and.b${G} #${Imm-32-QI},${Dsp-16-u16} */
51258   {
51259     M32C_INSN_AND16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "and16.b-imm-G-16-16-dst16-16-16-absolute-QI", "and.b", 40,
51260     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
51261   },
51262 /* adjnz.w #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
51263   {
51264     M32C_INSN_ADJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "adjnz.w", 32,
51265     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51266   },
51267 /* adjnz.w #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
51268   {
51269     M32C_INSN_ADJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "adjnz.w", 32,
51270     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51271   },
51272 /* adjnz.w #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
51273   {
51274     M32C_INSN_ADJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "adjnz.w", 32,
51275     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51276   },
51277 /* adjnz.w #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
51278   {
51279     M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "adjnz.w", 40,
51280     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51281   },
51282 /* adjnz.w #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
51283   {
51284     M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "adjnz.w", 40,
51285     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51286   },
51287 /* adjnz.w #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */
51288   {
51289     M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "adjnz.w", 40,
51290     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51291   },
51292 /* adjnz.w #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */
51293   {
51294     M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "adjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "adjnz.w", 40,
51295     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51296   },
51297 /* adjnz.w #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
51298   {
51299     M32C_INSN_ADJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "adjnz.w", 48,
51300     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51301   },
51302 /* adjnz.w #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */
51303   {
51304     M32C_INSN_ADJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "adjnz32.w-imm4-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "adjnz.w", 48,
51305     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51306   },
51307 /* adjnz.w #${Imm-12-s4},$Dst32RnUnprefixedHI,${Lab-16-8} */
51308   {
51309     M32C_INSN_ADJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "adjnz32.w-imm4-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "adjnz.w", 24,
51310     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51311   },
51312 /* adjnz.w #${Imm-12-s4},$Dst32AnUnprefixedHI,${Lab-16-8} */
51313   {
51314     M32C_INSN_ADJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "adjnz32.w-imm4-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "adjnz.w", 24,
51315     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51316   },
51317 /* adjnz.w #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */
51318   {
51319     M32C_INSN_ADJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "adjnz32.w-imm4-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "adjnz.w", 24,
51320     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51321   },
51322 /* adjnz.b #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
51323   {
51324     M32C_INSN_ADJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "adjnz.b", 32,
51325     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51326   },
51327 /* adjnz.b #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
51328   {
51329     M32C_INSN_ADJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "adjnz.b", 32,
51330     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51331   },
51332 /* adjnz.b #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
51333   {
51334     M32C_INSN_ADJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "adjnz.b", 32,
51335     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51336   },
51337 /* adjnz.b #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
51338   {
51339     M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "adjnz.b", 40,
51340     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51341   },
51342 /* adjnz.b #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
51343   {
51344     M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "adjnz.b", 40,
51345     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51346   },
51347 /* adjnz.b #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */
51348   {
51349     M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "adjnz.b", 40,
51350     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51351   },
51352 /* adjnz.b #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */
51353   {
51354     M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "adjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "adjnz.b", 40,
51355     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51356   },
51357 /* adjnz.b #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
51358   {
51359     M32C_INSN_ADJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "adjnz.b", 48,
51360     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51361   },
51362 /* adjnz.b #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */
51363   {
51364     M32C_INSN_ADJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "adjnz32.b-imm4-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "adjnz.b", 48,
51365     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51366   },
51367 /* adjnz.b #${Imm-12-s4},$Dst32RnUnprefixedQI,${Lab-16-8} */
51368   {
51369     M32C_INSN_ADJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "adjnz32.b-imm4-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "adjnz.b", 24,
51370     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51371   },
51372 /* adjnz.b #${Imm-12-s4},$Dst32AnUnprefixedQI,${Lab-16-8} */
51373   {
51374     M32C_INSN_ADJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "adjnz32.b-imm4-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "adjnz.b", 24,
51375     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51376   },
51377 /* adjnz.b #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */
51378   {
51379     M32C_INSN_ADJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "adjnz32.b-imm4-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "adjnz.b", 24,
51380     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
51381   },
51382 /* adjnz.w #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
51383   {
51384     M32C_INSN_ADJNZ16_W_IMM4_16_8_DST16_16_8_AN_RELATIVE_HI, "adjnz16.w-imm4-16-8-dst16-16-8-An-relative-HI", "adjnz.w", 32,
51385     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51386   },
51387 /* adjnz.w #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
51388   {
51389     M32C_INSN_ADJNZ16_W_IMM4_16_8_DST16_16_8_SB_RELATIVE_HI, "adjnz16.w-imm4-16-8-dst16-16-8-SB-relative-HI", "adjnz.w", 32,
51390     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51391   },
51392 /* adjnz.w #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
51393   {
51394     M32C_INSN_ADJNZ16_W_IMM4_16_8_DST16_16_8_FB_RELATIVE_HI, "adjnz16.w-imm4-16-8-dst16-16-8-FB-relative-HI", "adjnz.w", 32,
51395     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51396   },
51397 /* adjnz.w #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
51398   {
51399     M32C_INSN_ADJNZ16_W_IMM4_16_16_DST16_16_16_AN_RELATIVE_HI, "adjnz16.w-imm4-16-16-dst16-16-16-An-relative-HI", "adjnz.w", 40,
51400     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51401   },
51402 /* adjnz.w #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
51403   {
51404     M32C_INSN_ADJNZ16_W_IMM4_16_16_DST16_16_16_SB_RELATIVE_HI, "adjnz16.w-imm4-16-16-dst16-16-16-SB-relative-HI", "adjnz.w", 40,
51405     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51406   },
51407 /* adjnz.w #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */
51408   {
51409     M32C_INSN_ADJNZ16_W_IMM4_16_16_DST16_16_16_ABSOLUTE_HI, "adjnz16.w-imm4-16-16-dst16-16-16-absolute-HI", "adjnz.w", 40,
51410     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51411   },
51412 /* adjnz.w #${Imm-8-s4},$Dst16RnHI,${Lab-16-8} */
51413   {
51414     M32C_INSN_ADJNZ16_W_IMM4_BASIC_DST16_RN_DIRECT_HI, "adjnz16.w-imm4-basic-dst16-Rn-direct-HI", "adjnz.w", 24,
51415     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51416   },
51417 /* adjnz.w #${Imm-8-s4},$Dst16AnHI,${Lab-16-8} */
51418   {
51419     M32C_INSN_ADJNZ16_W_IMM4_BASIC_DST16_AN_DIRECT_HI, "adjnz16.w-imm4-basic-dst16-An-direct-HI", "adjnz.w", 24,
51420     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51421   },
51422 /* adjnz.w #${Imm-8-s4},[$Dst16An],${Lab-16-8} */
51423   {
51424     M32C_INSN_ADJNZ16_W_IMM4_BASIC_DST16_AN_INDIRECT_HI, "adjnz16.w-imm4-basic-dst16-An-indirect-HI", "adjnz.w", 24,
51425     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51426   },
51427 /* adjnz.b #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
51428   {
51429     M32C_INSN_ADJNZ16_B_IMM4_16_8_DST16_16_8_AN_RELATIVE_QI, "adjnz16.b-imm4-16-8-dst16-16-8-An-relative-QI", "adjnz.b", 32,
51430     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51431   },
51432 /* adjnz.b #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
51433   {
51434     M32C_INSN_ADJNZ16_B_IMM4_16_8_DST16_16_8_SB_RELATIVE_QI, "adjnz16.b-imm4-16-8-dst16-16-8-SB-relative-QI", "adjnz.b", 32,
51435     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51436   },
51437 /* adjnz.b #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
51438   {
51439     M32C_INSN_ADJNZ16_B_IMM4_16_8_DST16_16_8_FB_RELATIVE_QI, "adjnz16.b-imm4-16-8-dst16-16-8-FB-relative-QI", "adjnz.b", 32,
51440     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51441   },
51442 /* adjnz.b #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
51443   {
51444     M32C_INSN_ADJNZ16_B_IMM4_16_16_DST16_16_16_AN_RELATIVE_QI, "adjnz16.b-imm4-16-16-dst16-16-16-An-relative-QI", "adjnz.b", 40,
51445     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51446   },
51447 /* adjnz.b #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
51448   {
51449     M32C_INSN_ADJNZ16_B_IMM4_16_16_DST16_16_16_SB_RELATIVE_QI, "adjnz16.b-imm4-16-16-dst16-16-16-SB-relative-QI", "adjnz.b", 40,
51450     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51451   },
51452 /* adjnz.b #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */
51453   {
51454     M32C_INSN_ADJNZ16_B_IMM4_16_16_DST16_16_16_ABSOLUTE_QI, "adjnz16.b-imm4-16-16-dst16-16-16-absolute-QI", "adjnz.b", 40,
51455     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51456   },
51457 /* adjnz.b #${Imm-8-s4},$Dst16RnQI,${Lab-16-8} */
51458   {
51459     M32C_INSN_ADJNZ16_B_IMM4_BASIC_DST16_RN_DIRECT_QI, "adjnz16.b-imm4-basic-dst16-Rn-direct-QI", "adjnz.b", 24,
51460     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51461   },
51462 /* adjnz.b #${Imm-8-s4},$Dst16AnQI,${Lab-16-8} */
51463   {
51464     M32C_INSN_ADJNZ16_B_IMM4_BASIC_DST16_AN_DIRECT_QI, "adjnz16.b-imm4-basic-dst16-An-direct-QI", "adjnz.b", 24,
51465     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51466   },
51467 /* adjnz.b #${Imm-8-s4},[$Dst16An],${Lab-16-8} */
51468   {
51469     M32C_INSN_ADJNZ16_B_IMM4_BASIC_DST16_AN_INDIRECT_QI, "adjnz16.b-imm4-basic-dst16-An-indirect-QI", "adjnz.b", 24,
51470     { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51471   },
51472 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
51473   {
51474     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 24,
51475     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51476   },
51477 /* addx${X} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
51478   {
51479     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 24,
51480     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51481   },
51482 /* addx${X} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
51483   {
51484     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 24,
51485     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51486   },
51487 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
51488   {
51489     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 24,
51490     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51491   },
51492 /* addx${X} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
51493   {
51494     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 24,
51495     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51496   },
51497 /* addx${X} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
51498   {
51499     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 24,
51500     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51501   },
51502 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
51503   {
51504     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 24,
51505     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51506   },
51507 /* addx${X} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
51508   {
51509     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 24,
51510     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51511   },
51512 /* addx${X} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
51513   {
51514     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 24,
51515     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51516   },
51517 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
51518   {
51519     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "addx", 32,
51520     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51521   },
51522 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
51523   {
51524     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "addx", 32,
51525     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51526   },
51527 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
51528   {
51529     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "addx", 32,
51530     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51531   },
51532 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
51533   {
51534     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "addx", 40,
51535     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51536   },
51537 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
51538   {
51539     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "addx", 40,
51540     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51541   },
51542 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
51543   {
51544     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "addx", 40,
51545     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51546   },
51547 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
51548   {
51549     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "addx", 48,
51550     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51551   },
51552 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
51553   {
51554     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "addx", 48,
51555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51556   },
51557 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
51558   {
51559     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "addx", 48,
51560     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51561   },
51562 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
51563   {
51564     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "addx", 32,
51565     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51566   },
51567 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
51568   {
51569     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "addx", 32,
51570     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51571   },
51572 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
51573   {
51574     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "addx", 32,
51575     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51576   },
51577 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
51578   {
51579     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "addx", 40,
51580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51581   },
51582 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
51583   {
51584     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "addx", 40,
51585     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51586   },
51587 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
51588   {
51589     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "addx", 40,
51590     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51591   },
51592 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
51593   {
51594     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "addx", 32,
51595     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51596   },
51597 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
51598   {
51599     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "addx", 32,
51600     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51601   },
51602 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
51603   {
51604     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "addx", 32,
51605     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51606   },
51607 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
51608   {
51609     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "addx", 40,
51610     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51611   },
51612 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
51613   {
51614     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "addx", 40,
51615     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51616   },
51617 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
51618   {
51619     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "addx", 40,
51620     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51621   },
51622 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
51623   {
51624     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "addx", 40,
51625     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51626   },
51627 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
51628   {
51629     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "addx", 40,
51630     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51631   },
51632 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
51633   {
51634     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "addx", 40,
51635     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51636   },
51637 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
51638   {
51639     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "addx", 48,
51640     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51641   },
51642 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
51643   {
51644     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "addx", 48,
51645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51646   },
51647 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
51648   {
51649     M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "addx", 48,
51650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51651   },
51652 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
51653   {
51654     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 32,
51655     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51656   },
51657 /* addx${X} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
51658   {
51659     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 32,
51660     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51661   },
51662 /* addx${X} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
51663   {
51664     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 32,
51665     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51666   },
51667 /* addx${X} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
51668   {
51669     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 32,
51670     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51671   },
51672 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
51673   {
51674     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 32,
51675     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51676   },
51677 /* addx${X} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
51678   {
51679     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 32,
51680     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51681   },
51682 /* addx${X} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
51683   {
51684     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 32,
51685     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51686   },
51687 /* addx${X} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
51688   {
51689     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 32,
51690     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51691   },
51692 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
51693   {
51694     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 32,
51695     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51696   },
51697 /* addx${X} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
51698   {
51699     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 32,
51700     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51701   },
51702 /* addx${X} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
51703   {
51704     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 32,
51705     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51706   },
51707 /* addx${X} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
51708   {
51709     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 32,
51710     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51711   },
51712 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
51713   {
51714     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "addx", 40,
51715     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51716   },
51717 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
51718   {
51719     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "addx", 40,
51720     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51721   },
51722 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
51723   {
51724     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "addx", 40,
51725     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51726   },
51727 /* addx${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
51728   {
51729     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "addx", 40,
51730     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51731   },
51732 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
51733   {
51734     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "addx", 48,
51735     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51736   },
51737 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
51738   {
51739     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "addx", 48,
51740     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51741   },
51742 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
51743   {
51744     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "addx", 48,
51745     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51746   },
51747 /* addx${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
51748   {
51749     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "addx", 48,
51750     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51751   },
51752 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
51753   {
51754     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "addx", 56,
51755     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51756   },
51757 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
51758   {
51759     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "addx", 56,
51760     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51761   },
51762 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
51763   {
51764     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "addx", 56,
51765     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51766   },
51767 /* addx${X} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
51768   {
51769     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "addx", 56,
51770     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51771   },
51772 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
51773   {
51774     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "addx", 40,
51775     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51776   },
51777 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
51778   {
51779     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "addx", 40,
51780     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51781   },
51782 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
51783   {
51784     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "addx", 40,
51785     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51786   },
51787 /* addx${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
51788   {
51789     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "addx", 40,
51790     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51791   },
51792 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
51793   {
51794     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "addx", 48,
51795     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51796   },
51797 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
51798   {
51799     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "addx", 48,
51800     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51801   },
51802 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
51803   {
51804     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "addx", 48,
51805     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51806   },
51807 /* addx${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
51808   {
51809     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "addx", 48,
51810     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51811   },
51812 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
51813   {
51814     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "addx", 40,
51815     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51816   },
51817 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
51818   {
51819     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "addx", 40,
51820     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51821   },
51822 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
51823   {
51824     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "addx", 40,
51825     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51826   },
51827 /* addx${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
51828   {
51829     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "addx", 40,
51830     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51831   },
51832 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
51833   {
51834     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "addx", 48,
51835     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51836   },
51837 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
51838   {
51839     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "addx", 48,
51840     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51841   },
51842 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
51843   {
51844     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "addx", 48,
51845     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51846   },
51847 /* addx${X} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
51848   {
51849     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "addx", 48,
51850     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51851   },
51852 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
51853   {
51854     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "addx", 48,
51855     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51856   },
51857 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
51858   {
51859     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "addx", 48,
51860     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51861   },
51862 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
51863   {
51864     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "addx", 48,
51865     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51866   },
51867 /* addx${X} ${Dsp-16-u16},${Dsp-32-u16} */
51868   {
51869     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "addx", 48,
51870     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51871   },
51872 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
51873   {
51874     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "addx", 56,
51875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51876   },
51877 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
51878   {
51879     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "addx", 56,
51880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51881   },
51882 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
51883   {
51884     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "addx", 56,
51885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51886   },
51887 /* addx${X} ${Dsp-16-u16},${Dsp-32-u24} */
51888   {
51889     M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "addx", 56,
51890     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51891   },
51892 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
51893   {
51894     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 40,
51895     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51896   },
51897 /* addx${X} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
51898   {
51899     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 40,
51900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51901   },
51902 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
51903   {
51904     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 40,
51905     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51906   },
51907 /* addx${X} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
51908   {
51909     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 40,
51910     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51911   },
51912 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
51913   {
51914     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 40,
51915     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51916   },
51917 /* addx${X} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
51918   {
51919     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 40,
51920     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51921   },
51922 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
51923   {
51924     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-SI", "addx", 48,
51925     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51926   },
51927 /* addx${X} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
51928   {
51929     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-SI", "addx", 48,
51930     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51931   },
51932 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
51933   {
51934     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-SI", "addx", 56,
51935     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51936   },
51937 /* addx${X} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
51938   {
51939     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-SI", "addx", 56,
51940     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51941   },
51942 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
51943   {
51944     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-SI", "addx", 64,
51945     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51946   },
51947 /* addx${X} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
51948   {
51949     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-SI", "addx", 64,
51950     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51951   },
51952 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
51953   {
51954     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-SI", "addx", 48,
51955     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51956   },
51957 /* addx${X} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
51958   {
51959     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-SI", "addx", 48,
51960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51961   },
51962 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
51963   {
51964     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-SI", "addx", 56,
51965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51966   },
51967 /* addx${X} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
51968   {
51969     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-SI", "addx", 56,
51970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51971   },
51972 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
51973   {
51974     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-SI", "addx", 48,
51975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51976   },
51977 /* addx${X} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
51978   {
51979     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-SI", "addx", 48,
51980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51981   },
51982 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
51983   {
51984     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-SI", "addx", 56,
51985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51986   },
51987 /* addx${X} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
51988   {
51989     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-SI", "addx", 56,
51990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51991   },
51992 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
51993   {
51994     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-SI", "addx", 56,
51995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51996   },
51997 /* addx${X} ${Dsp-16-u24},${Dsp-40-u16} */
51998   {
51999     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-SI", "addx", 56,
52000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52001   },
52002 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
52003   {
52004     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-SI", "addx", 64,
52005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52006   },
52007 /* addx${X} ${Dsp-16-u24},${Dsp-40-u24} */
52008   {
52009     M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-SI", "addx", 64,
52010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52011   },
52012 /* addx${X} $Src32RnUnprefixedQI,$Dst32RnUnprefixedSI */
52013   {
52014     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 16,
52015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52016   },
52017 /* addx${X} $Src32AnUnprefixedQI,$Dst32RnUnprefixedSI */
52018   {
52019     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 16,
52020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52021   },
52022 /* addx${X} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
52023   {
52024     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 16,
52025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52026   },
52027 /* addx${X} $Src32RnUnprefixedQI,$Dst32AnUnprefixedSI */
52028   {
52029     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 16,
52030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52031   },
52032 /* addx${X} $Src32AnUnprefixedQI,$Dst32AnUnprefixedSI */
52033   {
52034     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 16,
52035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52036   },
52037 /* addx${X} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
52038   {
52039     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 16,
52040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52041   },
52042 /* addx${X} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
52043   {
52044     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 16,
52045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52046   },
52047 /* addx${X} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
52048   {
52049     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 16,
52050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52051   },
52052 /* addx${X} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
52053   {
52054     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 16,
52055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52056   },
52057 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
52058   {
52059     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "addx", 24,
52060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52061   },
52062 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
52063   {
52064     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "addx", 24,
52065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52066   },
52067 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
52068   {
52069     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "addx", 24,
52070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52071   },
52072 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
52073   {
52074     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "addx", 32,
52075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52076   },
52077 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
52078   {
52079     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "addx", 32,
52080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52081   },
52082 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
52083   {
52084     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "addx", 32,
52085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52086   },
52087 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
52088   {
52089     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "addx", 40,
52090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52091   },
52092 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
52093   {
52094     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "addx", 40,
52095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52096   },
52097 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
52098   {
52099     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "addx", 40,
52100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52101   },
52102 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
52103   {
52104     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "addx", 24,
52105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52106   },
52107 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
52108   {
52109     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "addx", 24,
52110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52111   },
52112 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
52113   {
52114     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "addx", 24,
52115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52116   },
52117 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
52118   {
52119     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "addx", 32,
52120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52121   },
52122 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
52123   {
52124     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "addx", 32,
52125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52126   },
52127 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
52128   {
52129     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "addx", 32,
52130     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52131   },
52132 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
52133   {
52134     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "addx", 24,
52135     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52136   },
52137 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
52138   {
52139     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "addx", 24,
52140     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52141   },
52142 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
52143   {
52144     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "addx", 24,
52145     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52146   },
52147 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
52148   {
52149     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "addx", 32,
52150     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52151   },
52152 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
52153   {
52154     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "addx", 32,
52155     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52156   },
52157 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
52158   {
52159     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "addx", 32,
52160     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52161   },
52162 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u16} */
52163   {
52164     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "addx", 32,
52165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52166   },
52167 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u16} */
52168   {
52169     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "addx", 32,
52170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52171   },
52172 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-u16} */
52173   {
52174     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "addx", 32,
52175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52176   },
52177 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u24} */
52178   {
52179     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "addx", 40,
52180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52181   },
52182 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u24} */
52183   {
52184     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "addx", 40,
52185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52186   },
52187 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-u24} */
52188   {
52189     M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "addx", 40,
52190     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52191   },
52192 /* addx${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
52193   {
52194     M32C_INSN_ADDX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "addx", 24,
52195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52196   },
52197 /* addx${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
52198   {
52199     M32C_INSN_ADDX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "addx", 24,
52200     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52201   },
52202 /* addx${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
52203   {
52204     M32C_INSN_ADDX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "addx", 24,
52205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52206   },
52207 /* addx${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
52208   {
52209     M32C_INSN_ADDX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "addx", 32,
52210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52211   },
52212 /* addx${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
52213   {
52214     M32C_INSN_ADDX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "addx", 32,
52215     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52216   },
52217 /* addx${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
52218   {
52219     M32C_INSN_ADDX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "addx", 32,
52220     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52221   },
52222 /* addx${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
52223   {
52224     M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "addx", 40,
52225     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52226   },
52227 /* addx${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
52228   {
52229     M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "addx", 40,
52230     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52231   },
52232 /* addx${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
52233   {
52234     M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "addx", 40,
52235     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52236   },
52237 /* addx${X} #${Imm-32-QI},${Dsp-16-u16} */
52238   {
52239     M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "addx32-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "addx", 40,
52240     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52241   },
52242 /* addx${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
52243   {
52244     M32C_INSN_ADDX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "addx", 48,
52245     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52246   },
52247 /* addx${X} #${Imm-40-QI},${Dsp-16-u24} */
52248   {
52249     M32C_INSN_ADDX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "addx32-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "addx", 48,
52250     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52251   },
52252 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
52253   {
52254     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 32,
52255     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52256   },
52257 /* dadd.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
52258   {
52259     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 32,
52260     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52261   },
52262 /* dadd.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
52263   {
52264     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 32,
52265     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52266   },
52267 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
52268   {
52269     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 32,
52270     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52271   },
52272 /* dadd.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
52273   {
52274     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 32,
52275     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52276   },
52277 /* dadd.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
52278   {
52279     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 32,
52280     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52281   },
52282 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
52283   {
52284     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 32,
52285     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52286   },
52287 /* dadd.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
52288   {
52289     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 32,
52290     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52291   },
52292 /* dadd.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
52293   {
52294     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 32,
52295     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52296   },
52297 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
52298   {
52299     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadd.w", 40,
52300     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52301   },
52302 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
52303   {
52304     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadd.w", 40,
52305     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52306   },
52307 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
52308   {
52309     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadd.w", 40,
52310     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52311   },
52312 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
52313   {
52314     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadd.w", 48,
52315     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52316   },
52317 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
52318   {
52319     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadd.w", 48,
52320     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52321   },
52322 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
52323   {
52324     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadd.w", 48,
52325     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52326   },
52327 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
52328   {
52329     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadd.w", 56,
52330     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52331   },
52332 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
52333   {
52334     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadd.w", 56,
52335     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52336   },
52337 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
52338   {
52339     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadd.w", 56,
52340     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52341   },
52342 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
52343   {
52344     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadd.w", 40,
52345     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52346   },
52347 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
52348   {
52349     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadd.w", 40,
52350     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52351   },
52352 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
52353   {
52354     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadd.w", 40,
52355     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52356   },
52357 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
52358   {
52359     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadd.w", 48,
52360     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52361   },
52362 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
52363   {
52364     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadd.w", 48,
52365     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52366   },
52367 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
52368   {
52369     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadd.w", 48,
52370     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52371   },
52372 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
52373   {
52374     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadd.w", 40,
52375     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52376   },
52377 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
52378   {
52379     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadd.w", 40,
52380     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52381   },
52382 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
52383   {
52384     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadd.w", 40,
52385     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52386   },
52387 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
52388   {
52389     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadd.w", 48,
52390     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52391   },
52392 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
52393   {
52394     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadd.w", 48,
52395     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52396   },
52397 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
52398   {
52399     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadd.w", 48,
52400     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52401   },
52402 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
52403   {
52404     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadd.w", 48,
52405     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52406   },
52407 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
52408   {
52409     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadd.w", 48,
52410     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52411   },
52412 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
52413   {
52414     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadd.w", 48,
52415     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52416   },
52417 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
52418   {
52419     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadd.w", 56,
52420     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52421   },
52422 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
52423   {
52424     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadd.w", 56,
52425     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52426   },
52427 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
52428   {
52429     M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadd.w", 56,
52430     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52431   },
52432 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
52433   {
52434     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 40,
52435     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52436   },
52437 /* dadd.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
52438   {
52439     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 40,
52440     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52441   },
52442 /* dadd.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
52443   {
52444     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 40,
52445     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52446   },
52447 /* dadd.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
52448   {
52449     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 40,
52450     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52451   },
52452 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
52453   {
52454     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 40,
52455     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52456   },
52457 /* dadd.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
52458   {
52459     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 40,
52460     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52461   },
52462 /* dadd.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
52463   {
52464     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 40,
52465     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52466   },
52467 /* dadd.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
52468   {
52469     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 40,
52470     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52471   },
52472 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
52473   {
52474     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 40,
52475     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52476   },
52477 /* dadd.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
52478   {
52479     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 40,
52480     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52481   },
52482 /* dadd.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
52483   {
52484     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 40,
52485     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52486   },
52487 /* dadd.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
52488   {
52489     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 40,
52490     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52491   },
52492 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
52493   {
52494     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadd.w", 48,
52495     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52496   },
52497 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
52498   {
52499     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadd.w", 48,
52500     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52501   },
52502 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
52503   {
52504     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadd.w", 48,
52505     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52506   },
52507 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
52508   {
52509     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadd.w", 48,
52510     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52511   },
52512 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
52513   {
52514     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadd.w", 56,
52515     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52516   },
52517 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
52518   {
52519     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadd.w", 56,
52520     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52521   },
52522 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
52523   {
52524     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadd.w", 56,
52525     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52526   },
52527 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
52528   {
52529     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadd.w", 56,
52530     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52531   },
52532 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
52533   {
52534     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadd.w", 64,
52535     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52536   },
52537 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
52538   {
52539     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadd.w", 64,
52540     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52541   },
52542 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
52543   {
52544     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadd.w", 64,
52545     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52546   },
52547 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
52548   {
52549     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadd.w", 64,
52550     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52551   },
52552 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
52553   {
52554     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadd.w", 48,
52555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52556   },
52557 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
52558   {
52559     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadd.w", 48,
52560     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52561   },
52562 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
52563   {
52564     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadd.w", 48,
52565     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52566   },
52567 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
52568   {
52569     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadd.w", 48,
52570     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52571   },
52572 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
52573   {
52574     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadd.w", 56,
52575     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52576   },
52577 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
52578   {
52579     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadd.w", 56,
52580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52581   },
52582 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
52583   {
52584     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadd.w", 56,
52585     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52586   },
52587 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
52588   {
52589     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadd.w", 56,
52590     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52591   },
52592 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
52593   {
52594     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadd.w", 48,
52595     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52596   },
52597 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
52598   {
52599     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadd.w", 48,
52600     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52601   },
52602 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
52603   {
52604     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadd.w", 48,
52605     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52606   },
52607 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
52608   {
52609     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadd.w", 48,
52610     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52611   },
52612 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
52613   {
52614     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadd.w", 56,
52615     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52616   },
52617 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
52618   {
52619     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadd.w", 56,
52620     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52621   },
52622 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
52623   {
52624     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadd.w", 56,
52625     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52626   },
52627 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
52628   {
52629     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadd.w", 56,
52630     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52631   },
52632 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
52633   {
52634     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadd.w", 56,
52635     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52636   },
52637 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
52638   {
52639     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadd.w", 56,
52640     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52641   },
52642 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
52643   {
52644     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadd.w", 56,
52645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52646   },
52647 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
52648   {
52649     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadd.w", 56,
52650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52651   },
52652 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
52653   {
52654     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadd.w", 64,
52655     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52656   },
52657 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
52658   {
52659     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadd.w", 64,
52660     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52661   },
52662 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
52663   {
52664     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadd.w", 64,
52665     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52666   },
52667 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
52668   {
52669     M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadd.w", 64,
52670     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52671   },
52672 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
52673   {
52674     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 48,
52675     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52676   },
52677 /* dadd.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
52678   {
52679     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 48,
52680     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52681   },
52682 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
52683   {
52684     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 48,
52685     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52686   },
52687 /* dadd.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
52688   {
52689     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 48,
52690     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52691   },
52692 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
52693   {
52694     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 48,
52695     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52696   },
52697 /* dadd.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
52698   {
52699     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 48,
52700     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52701   },
52702 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
52703   {
52704     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dadd.w", 56,
52705     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52706   },
52707 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
52708   {
52709     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dadd.w", 56,
52710     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52711   },
52712 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
52713   {
52714     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dadd.w", 64,
52715     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52716   },
52717 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
52718   {
52719     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dadd.w", 64,
52720     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52721   },
52722 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
52723   {
52724     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dadd.w", 72,
52725     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52726   },
52727 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
52728   {
52729     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dadd.w", 72,
52730     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52731   },
52732 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
52733   {
52734     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dadd.w", 56,
52735     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52736   },
52737 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
52738   {
52739     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dadd.w", 56,
52740     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52741   },
52742 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
52743   {
52744     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dadd.w", 64,
52745     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52746   },
52747 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
52748   {
52749     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dadd.w", 64,
52750     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52751   },
52752 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
52753   {
52754     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dadd.w", 56,
52755     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52756   },
52757 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
52758   {
52759     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dadd.w", 56,
52760     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52761   },
52762 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
52763   {
52764     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dadd.w", 64,
52765     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52766   },
52767 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
52768   {
52769     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dadd.w", 64,
52770     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52771   },
52772 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
52773   {
52774     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dadd.w", 64,
52775     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52776   },
52777 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
52778   {
52779     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dadd.w", 64,
52780     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52781   },
52782 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
52783   {
52784     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dadd.w", 72,
52785     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52786   },
52787 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
52788   {
52789     M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dadd.w", 72,
52790     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52791   },
52792 /* dadd.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
52793   {
52794     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 24,
52795     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52796   },
52797 /* dadd.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
52798   {
52799     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 24,
52800     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52801   },
52802 /* dadd.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
52803   {
52804     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 24,
52805     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52806   },
52807 /* dadd.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
52808   {
52809     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 24,
52810     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52811   },
52812 /* dadd.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
52813   {
52814     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 24,
52815     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52816   },
52817 /* dadd.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
52818   {
52819     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 24,
52820     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52821   },
52822 /* dadd.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
52823   {
52824     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 24,
52825     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52826   },
52827 /* dadd.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
52828   {
52829     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 24,
52830     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52831   },
52832 /* dadd.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
52833   {
52834     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 24,
52835     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52836   },
52837 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
52838   {
52839     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadd.w", 32,
52840     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52841   },
52842 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
52843   {
52844     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadd.w", 32,
52845     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52846   },
52847 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
52848   {
52849     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadd.w", 32,
52850     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52851   },
52852 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
52853   {
52854     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadd.w", 40,
52855     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52856   },
52857 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
52858   {
52859     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadd.w", 40,
52860     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52861   },
52862 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
52863   {
52864     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadd.w", 40,
52865     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52866   },
52867 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
52868   {
52869     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadd.w", 48,
52870     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52871   },
52872 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
52873   {
52874     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadd.w", 48,
52875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52876   },
52877 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
52878   {
52879     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadd.w", 48,
52880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52881   },
52882 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
52883   {
52884     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadd.w", 32,
52885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52886   },
52887 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
52888   {
52889     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadd.w", 32,
52890     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52891   },
52892 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
52893   {
52894     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadd.w", 32,
52895     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52896   },
52897 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
52898   {
52899     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadd.w", 40,
52900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52901   },
52902 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
52903   {
52904     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadd.w", 40,
52905     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52906   },
52907 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
52908   {
52909     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadd.w", 40,
52910     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52911   },
52912 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
52913   {
52914     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadd.w", 32,
52915     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52916   },
52917 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
52918   {
52919     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadd.w", 32,
52920     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52921   },
52922 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
52923   {
52924     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadd.w", 32,
52925     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52926   },
52927 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
52928   {
52929     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadd.w", 40,
52930     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52931   },
52932 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
52933   {
52934     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadd.w", 40,
52935     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52936   },
52937 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
52938   {
52939     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadd.w", 40,
52940     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52941   },
52942 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
52943   {
52944     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadd.w", 40,
52945     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52946   },
52947 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
52948   {
52949     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadd.w", 40,
52950     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52951   },
52952 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
52953   {
52954     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadd.w", 40,
52955     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52956   },
52957 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
52958   {
52959     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadd.w", 48,
52960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52961   },
52962 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
52963   {
52964     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadd.w", 48,
52965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52966   },
52967 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
52968   {
52969     M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadd.w", 48,
52970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52971   },
52972 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
52973   {
52974     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 32,
52975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52976   },
52977 /* dadd.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
52978   {
52979     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 32,
52980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52981   },
52982 /* dadd.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
52983   {
52984     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 32,
52985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52986   },
52987 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
52988   {
52989     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 32,
52990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52991   },
52992 /* dadd.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
52993   {
52994     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 32,
52995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52996   },
52997 /* dadd.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
52998   {
52999     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 32,
53000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53001   },
53002 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
53003   {
53004     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 32,
53005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53006   },
53007 /* dadd.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
53008   {
53009     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 32,
53010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53011   },
53012 /* dadd.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
53013   {
53014     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 32,
53015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53016   },
53017 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
53018   {
53019     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadd.b", 40,
53020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53021   },
53022 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
53023   {
53024     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadd.b", 40,
53025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53026   },
53027 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
53028   {
53029     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadd.b", 40,
53030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53031   },
53032 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
53033   {
53034     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadd.b", 48,
53035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53036   },
53037 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
53038   {
53039     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadd.b", 48,
53040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53041   },
53042 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
53043   {
53044     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadd.b", 48,
53045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53046   },
53047 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
53048   {
53049     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadd.b", 56,
53050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53051   },
53052 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
53053   {
53054     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadd.b", 56,
53055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53056   },
53057 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
53058   {
53059     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadd.b", 56,
53060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53061   },
53062 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
53063   {
53064     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadd.b", 40,
53065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53066   },
53067 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
53068   {
53069     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadd.b", 40,
53070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53071   },
53072 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
53073   {
53074     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadd.b", 40,
53075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53076   },
53077 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
53078   {
53079     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadd.b", 48,
53080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53081   },
53082 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
53083   {
53084     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadd.b", 48,
53085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53086   },
53087 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
53088   {
53089     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadd.b", 48,
53090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53091   },
53092 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
53093   {
53094     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadd.b", 40,
53095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53096   },
53097 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
53098   {
53099     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadd.b", 40,
53100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53101   },
53102 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
53103   {
53104     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadd.b", 40,
53105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53106   },
53107 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
53108   {
53109     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadd.b", 48,
53110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53111   },
53112 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
53113   {
53114     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadd.b", 48,
53115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53116   },
53117 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
53118   {
53119     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadd.b", 48,
53120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53121   },
53122 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
53123   {
53124     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadd.b", 48,
53125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53126   },
53127 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
53128   {
53129     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadd.b", 48,
53130     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53131   },
53132 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
53133   {
53134     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadd.b", 48,
53135     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53136   },
53137 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
53138   {
53139     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadd.b", 56,
53140     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53141   },
53142 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
53143   {
53144     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadd.b", 56,
53145     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53146   },
53147 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
53148   {
53149     M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadd.b", 56,
53150     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53151   },
53152 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
53153   {
53154     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 40,
53155     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53156   },
53157 /* dadd.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
53158   {
53159     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 40,
53160     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53161   },
53162 /* dadd.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
53163   {
53164     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 40,
53165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53166   },
53167 /* dadd.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
53168   {
53169     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 40,
53170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53171   },
53172 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
53173   {
53174     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 40,
53175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53176   },
53177 /* dadd.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
53178   {
53179     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 40,
53180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53181   },
53182 /* dadd.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
53183   {
53184     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 40,
53185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53186   },
53187 /* dadd.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
53188   {
53189     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 40,
53190     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53191   },
53192 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
53193   {
53194     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 40,
53195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53196   },
53197 /* dadd.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
53198   {
53199     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 40,
53200     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53201   },
53202 /* dadd.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
53203   {
53204     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 40,
53205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53206   },
53207 /* dadd.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
53208   {
53209     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 40,
53210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53211   },
53212 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
53213   {
53214     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadd.b", 48,
53215     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53216   },
53217 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
53218   {
53219     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadd.b", 48,
53220     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53221   },
53222 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
53223   {
53224     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadd.b", 48,
53225     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53226   },
53227 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
53228   {
53229     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadd.b", 48,
53230     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53231   },
53232 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
53233   {
53234     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadd.b", 56,
53235     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53236   },
53237 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
53238   {
53239     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadd.b", 56,
53240     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53241   },
53242 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
53243   {
53244     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadd.b", 56,
53245     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53246   },
53247 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
53248   {
53249     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadd.b", 56,
53250     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53251   },
53252 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
53253   {
53254     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadd.b", 64,
53255     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53256   },
53257 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
53258   {
53259     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadd.b", 64,
53260     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53261   },
53262 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
53263   {
53264     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadd.b", 64,
53265     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53266   },
53267 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
53268   {
53269     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadd.b", 64,
53270     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53271   },
53272 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
53273   {
53274     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadd.b", 48,
53275     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53276   },
53277 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
53278   {
53279     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadd.b", 48,
53280     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53281   },
53282 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
53283   {
53284     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadd.b", 48,
53285     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53286   },
53287 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
53288   {
53289     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadd.b", 48,
53290     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53291   },
53292 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
53293   {
53294     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadd.b", 56,
53295     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53296   },
53297 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
53298   {
53299     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadd.b", 56,
53300     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53301   },
53302 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
53303   {
53304     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadd.b", 56,
53305     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53306   },
53307 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
53308   {
53309     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadd.b", 56,
53310     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53311   },
53312 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
53313   {
53314     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadd.b", 48,
53315     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53316   },
53317 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
53318   {
53319     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadd.b", 48,
53320     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53321   },
53322 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
53323   {
53324     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadd.b", 48,
53325     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53326   },
53327 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
53328   {
53329     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadd.b", 48,
53330     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53331   },
53332 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
53333   {
53334     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadd.b", 56,
53335     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53336   },
53337 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
53338   {
53339     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadd.b", 56,
53340     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53341   },
53342 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
53343   {
53344     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadd.b", 56,
53345     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53346   },
53347 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
53348   {
53349     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadd.b", 56,
53350     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53351   },
53352 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
53353   {
53354     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadd.b", 56,
53355     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53356   },
53357 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
53358   {
53359     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadd.b", 56,
53360     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53361   },
53362 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
53363   {
53364     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadd.b", 56,
53365     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53366   },
53367 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
53368   {
53369     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadd.b", 56,
53370     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53371   },
53372 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
53373   {
53374     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadd.b", 64,
53375     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53376   },
53377 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
53378   {
53379     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadd.b", 64,
53380     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53381   },
53382 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
53383   {
53384     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadd.b", 64,
53385     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53386   },
53387 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
53388   {
53389     M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadd.b", 64,
53390     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53391   },
53392 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
53393   {
53394     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 48,
53395     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53396   },
53397 /* dadd.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
53398   {
53399     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 48,
53400     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53401   },
53402 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
53403   {
53404     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 48,
53405     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53406   },
53407 /* dadd.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
53408   {
53409     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 48,
53410     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53411   },
53412 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
53413   {
53414     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 48,
53415     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53416   },
53417 /* dadd.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
53418   {
53419     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 48,
53420     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53421   },
53422 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
53423   {
53424     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dadd.b", 56,
53425     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53426   },
53427 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
53428   {
53429     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dadd.b", 56,
53430     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53431   },
53432 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
53433   {
53434     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dadd.b", 64,
53435     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53436   },
53437 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
53438   {
53439     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dadd.b", 64,
53440     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53441   },
53442 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
53443   {
53444     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dadd.b", 72,
53445     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53446   },
53447 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
53448   {
53449     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dadd.b", 72,
53450     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53451   },
53452 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
53453   {
53454     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dadd.b", 56,
53455     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53456   },
53457 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
53458   {
53459     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dadd.b", 56,
53460     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53461   },
53462 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
53463   {
53464     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dadd.b", 64,
53465     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53466   },
53467 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
53468   {
53469     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dadd.b", 64,
53470     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53471   },
53472 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
53473   {
53474     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dadd.b", 56,
53475     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53476   },
53477 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
53478   {
53479     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dadd.b", 56,
53480     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53481   },
53482 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
53483   {
53484     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dadd.b", 64,
53485     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53486   },
53487 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
53488   {
53489     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dadd.b", 64,
53490     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53491   },
53492 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
53493   {
53494     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dadd.b", 64,
53495     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53496   },
53497 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
53498   {
53499     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dadd.b", 64,
53500     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53501   },
53502 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
53503   {
53504     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dadd.b", 72,
53505     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53506   },
53507 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
53508   {
53509     M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dadd.b", 72,
53510     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53511   },
53512 /* dadd.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
53513   {
53514     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 24,
53515     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53516   },
53517 /* dadd.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
53518   {
53519     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 24,
53520     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53521   },
53522 /* dadd.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
53523   {
53524     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 24,
53525     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53526   },
53527 /* dadd.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
53528   {
53529     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 24,
53530     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53531   },
53532 /* dadd.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
53533   {
53534     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 24,
53535     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53536   },
53537 /* dadd.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
53538   {
53539     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 24,
53540     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53541   },
53542 /* dadd.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
53543   {
53544     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 24,
53545     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53546   },
53547 /* dadd.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
53548   {
53549     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 24,
53550     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53551   },
53552 /* dadd.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
53553   {
53554     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 24,
53555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53556   },
53557 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
53558   {
53559     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadd.b", 32,
53560     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53561   },
53562 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
53563   {
53564     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadd.b", 32,
53565     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53566   },
53567 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
53568   {
53569     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadd.b", 32,
53570     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53571   },
53572 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
53573   {
53574     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadd.b", 40,
53575     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53576   },
53577 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
53578   {
53579     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadd.b", 40,
53580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53581   },
53582 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
53583   {
53584     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadd.b", 40,
53585     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53586   },
53587 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
53588   {
53589     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadd.b", 48,
53590     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53591   },
53592 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
53593   {
53594     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadd.b", 48,
53595     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53596   },
53597 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
53598   {
53599     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadd.b", 48,
53600     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53601   },
53602 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
53603   {
53604     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadd.b", 32,
53605     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53606   },
53607 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
53608   {
53609     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadd.b", 32,
53610     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53611   },
53612 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
53613   {
53614     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadd.b", 32,
53615     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53616   },
53617 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
53618   {
53619     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadd.b", 40,
53620     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53621   },
53622 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
53623   {
53624     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadd.b", 40,
53625     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53626   },
53627 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
53628   {
53629     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadd.b", 40,
53630     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53631   },
53632 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
53633   {
53634     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadd.b", 32,
53635     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53636   },
53637 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
53638   {
53639     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadd.b", 32,
53640     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53641   },
53642 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
53643   {
53644     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadd.b", 32,
53645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53646   },
53647 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
53648   {
53649     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadd.b", 40,
53650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53651   },
53652 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
53653   {
53654     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadd.b", 40,
53655     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53656   },
53657 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
53658   {
53659     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadd.b", 40,
53660     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53661   },
53662 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
53663   {
53664     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadd.b", 40,
53665     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53666   },
53667 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
53668   {
53669     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadd.b", 40,
53670     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53671   },
53672 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
53673   {
53674     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadd.b", 40,
53675     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53676   },
53677 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
53678   {
53679     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadd.b", 48,
53680     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53681   },
53682 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
53683   {
53684     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadd.b", 48,
53685     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53686   },
53687 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
53688   {
53689     M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadd.b", 48,
53690     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53691   },
53692 /* dadd.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
53693   {
53694     M32C_INSN_DADD32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "dadd.w", 40,
53695     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53696   },
53697 /* dadd.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
53698   {
53699     M32C_INSN_DADD32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "dadd.w", 40,
53700     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53701   },
53702 /* dadd.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
53703   {
53704     M32C_INSN_DADD32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "dadd.w", 40,
53705     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53706   },
53707 /* dadd.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
53708   {
53709     M32C_INSN_DADD32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "dadd.w", 48,
53710     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53711   },
53712 /* dadd.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
53713   {
53714     M32C_INSN_DADD32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "dadd.w", 48,
53715     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53716   },
53717 /* dadd.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
53718   {
53719     M32C_INSN_DADD32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "dadd.w", 48,
53720     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53721   },
53722 /* dadd.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
53723   {
53724     M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "dadd.w", 56,
53725     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53726   },
53727 /* dadd.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
53728   {
53729     M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "dadd.w", 56,
53730     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53731   },
53732 /* dadd.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
53733   {
53734     M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "dadd.w", 56,
53735     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53736   },
53737 /* dadd.w${X} #${Imm-40-HI},${Dsp-24-u16} */
53738   {
53739     M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "dadd.w", 56,
53740     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53741   },
53742 /* dadd.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
53743   {
53744     M32C_INSN_DADD32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "dadd.w", 64,
53745     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53746   },
53747 /* dadd.w${X} #${Imm-48-HI},${Dsp-24-u24} */
53748   {
53749     M32C_INSN_DADD32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "dadd.w", 64,
53750     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53751   },
53752 /* dadd.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
53753   {
53754     M32C_INSN_DADD32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "dadd.b", 32,
53755     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53756   },
53757 /* dadd.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
53758   {
53759     M32C_INSN_DADD32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "dadd.b", 32,
53760     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53761   },
53762 /* dadd.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
53763   {
53764     M32C_INSN_DADD32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "dadd.b", 32,
53765     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53766   },
53767 /* dadd.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
53768   {
53769     M32C_INSN_DADD32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "dadd.b", 40,
53770     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53771   },
53772 /* dadd.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
53773   {
53774     M32C_INSN_DADD32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "dadd.b", 40,
53775     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53776   },
53777 /* dadd.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
53778   {
53779     M32C_INSN_DADD32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "dadd.b", 40,
53780     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53781   },
53782 /* dadd.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
53783   {
53784     M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "dadd.b", 48,
53785     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53786   },
53787 /* dadd.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
53788   {
53789     M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "dadd.b", 48,
53790     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53791   },
53792 /* dadd.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
53793   {
53794     M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "dadd.b", 48,
53795     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53796   },
53797 /* dadd.b${X} #${Imm-40-QI},${Dsp-24-u16} */
53798   {
53799     M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "dadd.b", 48,
53800     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53801   },
53802 /* dadd.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
53803   {
53804     M32C_INSN_DADD32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "dadd.b", 56,
53805     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53806   },
53807 /* dadd.b${X} #${Imm-48-QI},${Dsp-24-u24} */
53808   {
53809     M32C_INSN_DADD32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "dadd.b", 56,
53810     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53811   },
53812 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
53813   {
53814     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 32,
53815     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53816   },
53817 /* dadc.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
53818   {
53819     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 32,
53820     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53821   },
53822 /* dadc.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
53823   {
53824     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 32,
53825     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53826   },
53827 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
53828   {
53829     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 32,
53830     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53831   },
53832 /* dadc.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
53833   {
53834     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 32,
53835     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53836   },
53837 /* dadc.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
53838   {
53839     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 32,
53840     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53841   },
53842 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
53843   {
53844     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 32,
53845     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53846   },
53847 /* dadc.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
53848   {
53849     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 32,
53850     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53851   },
53852 /* dadc.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
53853   {
53854     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 32,
53855     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53856   },
53857 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
53858   {
53859     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadc.w", 40,
53860     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53861   },
53862 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
53863   {
53864     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadc.w", 40,
53865     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53866   },
53867 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
53868   {
53869     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadc.w", 40,
53870     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53871   },
53872 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
53873   {
53874     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadc.w", 48,
53875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53876   },
53877 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
53878   {
53879     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadc.w", 48,
53880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53881   },
53882 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
53883   {
53884     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadc.w", 48,
53885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53886   },
53887 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
53888   {
53889     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadc.w", 56,
53890     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53891   },
53892 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
53893   {
53894     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadc.w", 56,
53895     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53896   },
53897 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
53898   {
53899     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadc.w", 56,
53900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53901   },
53902 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
53903   {
53904     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadc.w", 40,
53905     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53906   },
53907 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
53908   {
53909     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadc.w", 40,
53910     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53911   },
53912 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
53913   {
53914     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadc.w", 40,
53915     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53916   },
53917 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
53918   {
53919     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadc.w", 48,
53920     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53921   },
53922 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
53923   {
53924     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadc.w", 48,
53925     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53926   },
53927 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
53928   {
53929     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadc.w", 48,
53930     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53931   },
53932 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
53933   {
53934     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadc.w", 40,
53935     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53936   },
53937 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
53938   {
53939     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadc.w", 40,
53940     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53941   },
53942 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
53943   {
53944     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadc.w", 40,
53945     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53946   },
53947 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
53948   {
53949     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadc.w", 48,
53950     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53951   },
53952 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
53953   {
53954     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadc.w", 48,
53955     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53956   },
53957 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
53958   {
53959     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadc.w", 48,
53960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53961   },
53962 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
53963   {
53964     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadc.w", 48,
53965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53966   },
53967 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
53968   {
53969     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadc.w", 48,
53970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53971   },
53972 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
53973   {
53974     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadc.w", 48,
53975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53976   },
53977 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
53978   {
53979     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadc.w", 56,
53980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53981   },
53982 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
53983   {
53984     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadc.w", 56,
53985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53986   },
53987 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
53988   {
53989     M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadc.w", 56,
53990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53991   },
53992 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
53993   {
53994     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 40,
53995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53996   },
53997 /* dadc.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
53998   {
53999     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 40,
54000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54001   },
54002 /* dadc.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
54003   {
54004     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 40,
54005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54006   },
54007 /* dadc.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
54008   {
54009     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 40,
54010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54011   },
54012 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
54013   {
54014     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 40,
54015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54016   },
54017 /* dadc.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
54018   {
54019     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 40,
54020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54021   },
54022 /* dadc.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
54023   {
54024     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 40,
54025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54026   },
54027 /* dadc.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
54028   {
54029     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 40,
54030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54031   },
54032 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
54033   {
54034     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 40,
54035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54036   },
54037 /* dadc.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
54038   {
54039     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 40,
54040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54041   },
54042 /* dadc.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
54043   {
54044     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 40,
54045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54046   },
54047 /* dadc.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
54048   {
54049     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 40,
54050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54051   },
54052 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
54053   {
54054     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadc.w", 48,
54055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54056   },
54057 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
54058   {
54059     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadc.w", 48,
54060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54061   },
54062 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
54063   {
54064     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadc.w", 48,
54065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54066   },
54067 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
54068   {
54069     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadc.w", 48,
54070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54071   },
54072 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
54073   {
54074     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadc.w", 56,
54075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54076   },
54077 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
54078   {
54079     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadc.w", 56,
54080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54081   },
54082 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
54083   {
54084     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadc.w", 56,
54085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54086   },
54087 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
54088   {
54089     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadc.w", 56,
54090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54091   },
54092 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
54093   {
54094     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadc.w", 64,
54095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54096   },
54097 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
54098   {
54099     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadc.w", 64,
54100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54101   },
54102 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
54103   {
54104     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadc.w", 64,
54105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54106   },
54107 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
54108   {
54109     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadc.w", 64,
54110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54111   },
54112 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
54113   {
54114     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadc.w", 48,
54115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54116   },
54117 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
54118   {
54119     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadc.w", 48,
54120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54121   },
54122 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
54123   {
54124     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadc.w", 48,
54125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54126   },
54127 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
54128   {
54129     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadc.w", 48,
54130     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54131   },
54132 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
54133   {
54134     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadc.w", 56,
54135     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54136   },
54137 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
54138   {
54139     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadc.w", 56,
54140     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54141   },
54142 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
54143   {
54144     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadc.w", 56,
54145     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54146   },
54147 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
54148   {
54149     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadc.w", 56,
54150     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54151   },
54152 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
54153   {
54154     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadc.w", 48,
54155     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54156   },
54157 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
54158   {
54159     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadc.w", 48,
54160     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54161   },
54162 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
54163   {
54164     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadc.w", 48,
54165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54166   },
54167 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
54168   {
54169     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadc.w", 48,
54170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54171   },
54172 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
54173   {
54174     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadc.w", 56,
54175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54176   },
54177 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
54178   {
54179     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadc.w", 56,
54180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54181   },
54182 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
54183   {
54184     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadc.w", 56,
54185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54186   },
54187 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
54188   {
54189     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadc.w", 56,
54190     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54191   },
54192 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
54193   {
54194     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadc.w", 56,
54195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54196   },
54197 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
54198   {
54199     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadc.w", 56,
54200     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54201   },
54202 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
54203   {
54204     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadc.w", 56,
54205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54206   },
54207 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
54208   {
54209     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadc.w", 56,
54210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54211   },
54212 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
54213   {
54214     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadc.w", 64,
54215     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54216   },
54217 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
54218   {
54219     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadc.w", 64,
54220     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54221   },
54222 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
54223   {
54224     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadc.w", 64,
54225     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54226   },
54227 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
54228   {
54229     M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadc.w", 64,
54230     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54231   },
54232 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
54233   {
54234     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 48,
54235     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54236   },
54237 /* dadc.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
54238   {
54239     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 48,
54240     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54241   },
54242 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
54243   {
54244     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 48,
54245     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54246   },
54247 /* dadc.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
54248   {
54249     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 48,
54250     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54251   },
54252 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
54253   {
54254     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 48,
54255     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54256   },
54257 /* dadc.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
54258   {
54259     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 48,
54260     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54261   },
54262 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
54263   {
54264     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dadc.w", 56,
54265     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54266   },
54267 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
54268   {
54269     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dadc.w", 56,
54270     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54271   },
54272 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
54273   {
54274     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dadc.w", 64,
54275     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54276   },
54277 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
54278   {
54279     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dadc.w", 64,
54280     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54281   },
54282 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
54283   {
54284     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dadc.w", 72,
54285     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54286   },
54287 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
54288   {
54289     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dadc.w", 72,
54290     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54291   },
54292 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
54293   {
54294     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dadc.w", 56,
54295     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54296   },
54297 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
54298   {
54299     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dadc.w", 56,
54300     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54301   },
54302 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
54303   {
54304     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dadc.w", 64,
54305     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54306   },
54307 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
54308   {
54309     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dadc.w", 64,
54310     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54311   },
54312 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
54313   {
54314     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dadc.w", 56,
54315     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54316   },
54317 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
54318   {
54319     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dadc.w", 56,
54320     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54321   },
54322 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
54323   {
54324     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dadc.w", 64,
54325     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54326   },
54327 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
54328   {
54329     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dadc.w", 64,
54330     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54331   },
54332 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
54333   {
54334     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dadc.w", 64,
54335     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54336   },
54337 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
54338   {
54339     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dadc.w", 64,
54340     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54341   },
54342 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
54343   {
54344     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dadc.w", 72,
54345     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54346   },
54347 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
54348   {
54349     M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dadc.w", 72,
54350     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54351   },
54352 /* dadc.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
54353   {
54354     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 24,
54355     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54356   },
54357 /* dadc.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
54358   {
54359     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 24,
54360     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54361   },
54362 /* dadc.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
54363   {
54364     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 24,
54365     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54366   },
54367 /* dadc.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
54368   {
54369     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 24,
54370     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54371   },
54372 /* dadc.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
54373   {
54374     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 24,
54375     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54376   },
54377 /* dadc.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
54378   {
54379     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 24,
54380     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54381   },
54382 /* dadc.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
54383   {
54384     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 24,
54385     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54386   },
54387 /* dadc.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
54388   {
54389     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 24,
54390     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54391   },
54392 /* dadc.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
54393   {
54394     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 24,
54395     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54396   },
54397 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
54398   {
54399     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadc.w", 32,
54400     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54401   },
54402 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
54403   {
54404     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadc.w", 32,
54405     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54406   },
54407 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
54408   {
54409     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadc.w", 32,
54410     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54411   },
54412 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
54413   {
54414     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadc.w", 40,
54415     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54416   },
54417 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
54418   {
54419     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadc.w", 40,
54420     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54421   },
54422 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
54423   {
54424     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadc.w", 40,
54425     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54426   },
54427 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
54428   {
54429     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadc.w", 48,
54430     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54431   },
54432 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
54433   {
54434     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadc.w", 48,
54435     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54436   },
54437 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
54438   {
54439     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadc.w", 48,
54440     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54441   },
54442 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
54443   {
54444     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadc.w", 32,
54445     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54446   },
54447 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
54448   {
54449     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadc.w", 32,
54450     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54451   },
54452 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
54453   {
54454     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadc.w", 32,
54455     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54456   },
54457 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
54458   {
54459     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadc.w", 40,
54460     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54461   },
54462 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
54463   {
54464     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadc.w", 40,
54465     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54466   },
54467 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
54468   {
54469     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadc.w", 40,
54470     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54471   },
54472 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
54473   {
54474     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadc.w", 32,
54475     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54476   },
54477 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
54478   {
54479     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadc.w", 32,
54480     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54481   },
54482 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
54483   {
54484     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadc.w", 32,
54485     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54486   },
54487 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
54488   {
54489     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadc.w", 40,
54490     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54491   },
54492 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
54493   {
54494     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadc.w", 40,
54495     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54496   },
54497 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
54498   {
54499     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadc.w", 40,
54500     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54501   },
54502 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
54503   {
54504     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadc.w", 40,
54505     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54506   },
54507 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
54508   {
54509     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadc.w", 40,
54510     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54511   },
54512 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
54513   {
54514     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadc.w", 40,
54515     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54516   },
54517 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
54518   {
54519     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadc.w", 48,
54520     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54521   },
54522 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
54523   {
54524     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadc.w", 48,
54525     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54526   },
54527 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
54528   {
54529     M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadc.w", 48,
54530     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54531   },
54532 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
54533   {
54534     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 32,
54535     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54536   },
54537 /* dadc.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
54538   {
54539     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 32,
54540     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54541   },
54542 /* dadc.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
54543   {
54544     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 32,
54545     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54546   },
54547 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
54548   {
54549     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 32,
54550     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54551   },
54552 /* dadc.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
54553   {
54554     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 32,
54555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54556   },
54557 /* dadc.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
54558   {
54559     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 32,
54560     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54561   },
54562 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
54563   {
54564     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 32,
54565     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54566   },
54567 /* dadc.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
54568   {
54569     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 32,
54570     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54571   },
54572 /* dadc.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
54573   {
54574     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 32,
54575     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54576   },
54577 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
54578   {
54579     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadc.b", 40,
54580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54581   },
54582 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
54583   {
54584     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadc.b", 40,
54585     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54586   },
54587 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
54588   {
54589     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadc.b", 40,
54590     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54591   },
54592 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
54593   {
54594     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadc.b", 48,
54595     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54596   },
54597 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
54598   {
54599     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadc.b", 48,
54600     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54601   },
54602 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
54603   {
54604     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadc.b", 48,
54605     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54606   },
54607 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
54608   {
54609     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadc.b", 56,
54610     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54611   },
54612 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
54613   {
54614     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadc.b", 56,
54615     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54616   },
54617 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
54618   {
54619     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadc.b", 56,
54620     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54621   },
54622 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
54623   {
54624     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadc.b", 40,
54625     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54626   },
54627 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
54628   {
54629     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadc.b", 40,
54630     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54631   },
54632 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
54633   {
54634     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadc.b", 40,
54635     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54636   },
54637 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
54638   {
54639     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadc.b", 48,
54640     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54641   },
54642 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
54643   {
54644     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadc.b", 48,
54645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54646   },
54647 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
54648   {
54649     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadc.b", 48,
54650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54651   },
54652 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
54653   {
54654     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadc.b", 40,
54655     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54656   },
54657 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
54658   {
54659     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadc.b", 40,
54660     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54661   },
54662 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
54663   {
54664     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadc.b", 40,
54665     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54666   },
54667 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
54668   {
54669     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadc.b", 48,
54670     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54671   },
54672 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
54673   {
54674     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadc.b", 48,
54675     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54676   },
54677 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
54678   {
54679     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadc.b", 48,
54680     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54681   },
54682 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
54683   {
54684     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadc.b", 48,
54685     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54686   },
54687 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
54688   {
54689     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadc.b", 48,
54690     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54691   },
54692 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
54693   {
54694     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadc.b", 48,
54695     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54696   },
54697 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
54698   {
54699     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadc.b", 56,
54700     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54701   },
54702 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
54703   {
54704     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadc.b", 56,
54705     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54706   },
54707 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
54708   {
54709     M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadc.b", 56,
54710     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54711   },
54712 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
54713   {
54714     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 40,
54715     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54716   },
54717 /* dadc.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
54718   {
54719     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 40,
54720     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54721   },
54722 /* dadc.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
54723   {
54724     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 40,
54725     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54726   },
54727 /* dadc.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
54728   {
54729     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 40,
54730     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54731   },
54732 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
54733   {
54734     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 40,
54735     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54736   },
54737 /* dadc.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
54738   {
54739     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 40,
54740     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54741   },
54742 /* dadc.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
54743   {
54744     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 40,
54745     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54746   },
54747 /* dadc.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
54748   {
54749     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 40,
54750     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54751   },
54752 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
54753   {
54754     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 40,
54755     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54756   },
54757 /* dadc.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
54758   {
54759     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 40,
54760     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54761   },
54762 /* dadc.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
54763   {
54764     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 40,
54765     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54766   },
54767 /* dadc.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
54768   {
54769     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 40,
54770     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54771   },
54772 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
54773   {
54774     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadc.b", 48,
54775     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54776   },
54777 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
54778   {
54779     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadc.b", 48,
54780     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54781   },
54782 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
54783   {
54784     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadc.b", 48,
54785     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54786   },
54787 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
54788   {
54789     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadc.b", 48,
54790     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54791   },
54792 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
54793   {
54794     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadc.b", 56,
54795     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54796   },
54797 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
54798   {
54799     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadc.b", 56,
54800     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54801   },
54802 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
54803   {
54804     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadc.b", 56,
54805     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54806   },
54807 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
54808   {
54809     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadc.b", 56,
54810     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54811   },
54812 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
54813   {
54814     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadc.b", 64,
54815     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54816   },
54817 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
54818   {
54819     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadc.b", 64,
54820     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54821   },
54822 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
54823   {
54824     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadc.b", 64,
54825     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54826   },
54827 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
54828   {
54829     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadc.b", 64,
54830     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54831   },
54832 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
54833   {
54834     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadc.b", 48,
54835     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54836   },
54837 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
54838   {
54839     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadc.b", 48,
54840     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54841   },
54842 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
54843   {
54844     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadc.b", 48,
54845     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54846   },
54847 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
54848   {
54849     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadc.b", 48,
54850     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54851   },
54852 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
54853   {
54854     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadc.b", 56,
54855     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54856   },
54857 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
54858   {
54859     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadc.b", 56,
54860     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54861   },
54862 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
54863   {
54864     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadc.b", 56,
54865     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54866   },
54867 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
54868   {
54869     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadc.b", 56,
54870     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54871   },
54872 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
54873   {
54874     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadc.b", 48,
54875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54876   },
54877 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
54878   {
54879     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadc.b", 48,
54880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54881   },
54882 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
54883   {
54884     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadc.b", 48,
54885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54886   },
54887 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
54888   {
54889     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadc.b", 48,
54890     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54891   },
54892 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
54893   {
54894     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadc.b", 56,
54895     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54896   },
54897 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
54898   {
54899     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadc.b", 56,
54900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54901   },
54902 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
54903   {
54904     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadc.b", 56,
54905     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54906   },
54907 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
54908   {
54909     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadc.b", 56,
54910     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54911   },
54912 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
54913   {
54914     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadc.b", 56,
54915     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54916   },
54917 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
54918   {
54919     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadc.b", 56,
54920     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54921   },
54922 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
54923   {
54924     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadc.b", 56,
54925     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54926   },
54927 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
54928   {
54929     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadc.b", 56,
54930     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54931   },
54932 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
54933   {
54934     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadc.b", 64,
54935     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54936   },
54937 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
54938   {
54939     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadc.b", 64,
54940     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54941   },
54942 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
54943   {
54944     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadc.b", 64,
54945     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54946   },
54947 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
54948   {
54949     M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadc.b", 64,
54950     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54951   },
54952 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
54953   {
54954     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 48,
54955     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54956   },
54957 /* dadc.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
54958   {
54959     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 48,
54960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54961   },
54962 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
54963   {
54964     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 48,
54965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54966   },
54967 /* dadc.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
54968   {
54969     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 48,
54970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54971   },
54972 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
54973   {
54974     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 48,
54975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54976   },
54977 /* dadc.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
54978   {
54979     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 48,
54980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54981   },
54982 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
54983   {
54984     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dadc.b", 56,
54985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54986   },
54987 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
54988   {
54989     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dadc.b", 56,
54990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54991   },
54992 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
54993   {
54994     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dadc.b", 64,
54995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54996   },
54997 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
54998   {
54999     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dadc.b", 64,
55000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55001   },
55002 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
55003   {
55004     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dadc.b", 72,
55005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55006   },
55007 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
55008   {
55009     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dadc.b", 72,
55010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55011   },
55012 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
55013   {
55014     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dadc.b", 56,
55015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55016   },
55017 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
55018   {
55019     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dadc.b", 56,
55020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55021   },
55022 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
55023   {
55024     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dadc.b", 64,
55025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55026   },
55027 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
55028   {
55029     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dadc.b", 64,
55030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55031   },
55032 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
55033   {
55034     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dadc.b", 56,
55035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55036   },
55037 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
55038   {
55039     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dadc.b", 56,
55040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55041   },
55042 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
55043   {
55044     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dadc.b", 64,
55045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55046   },
55047 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
55048   {
55049     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dadc.b", 64,
55050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55051   },
55052 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
55053   {
55054     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dadc.b", 64,
55055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55056   },
55057 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
55058   {
55059     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dadc.b", 64,
55060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55061   },
55062 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
55063   {
55064     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dadc.b", 72,
55065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55066   },
55067 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
55068   {
55069     M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dadc.b", 72,
55070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55071   },
55072 /* dadc.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
55073   {
55074     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 24,
55075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55076   },
55077 /* dadc.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
55078   {
55079     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 24,
55080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55081   },
55082 /* dadc.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
55083   {
55084     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 24,
55085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55086   },
55087 /* dadc.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
55088   {
55089     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 24,
55090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55091   },
55092 /* dadc.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
55093   {
55094     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 24,
55095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55096   },
55097 /* dadc.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
55098   {
55099     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 24,
55100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55101   },
55102 /* dadc.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
55103   {
55104     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 24,
55105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55106   },
55107 /* dadc.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
55108   {
55109     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 24,
55110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55111   },
55112 /* dadc.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
55113   {
55114     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 24,
55115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55116   },
55117 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
55118   {
55119     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadc.b", 32,
55120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55121   },
55122 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
55123   {
55124     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadc.b", 32,
55125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55126   },
55127 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
55128   {
55129     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadc.b", 32,
55130     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55131   },
55132 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
55133   {
55134     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadc.b", 40,
55135     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55136   },
55137 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
55138   {
55139     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadc.b", 40,
55140     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55141   },
55142 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
55143   {
55144     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadc.b", 40,
55145     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55146   },
55147 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
55148   {
55149     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadc.b", 48,
55150     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55151   },
55152 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
55153   {
55154     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadc.b", 48,
55155     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55156   },
55157 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
55158   {
55159     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadc.b", 48,
55160     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55161   },
55162 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
55163   {
55164     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadc.b", 32,
55165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55166   },
55167 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
55168   {
55169     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadc.b", 32,
55170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55171   },
55172 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
55173   {
55174     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadc.b", 32,
55175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55176   },
55177 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
55178   {
55179     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadc.b", 40,
55180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55181   },
55182 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
55183   {
55184     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadc.b", 40,
55185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55186   },
55187 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
55188   {
55189     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadc.b", 40,
55190     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55191   },
55192 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
55193   {
55194     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadc.b", 32,
55195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55196   },
55197 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
55198   {
55199     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadc.b", 32,
55200     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55201   },
55202 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
55203   {
55204     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadc.b", 32,
55205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55206   },
55207 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
55208   {
55209     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadc.b", 40,
55210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55211   },
55212 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
55213   {
55214     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadc.b", 40,
55215     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55216   },
55217 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
55218   {
55219     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadc.b", 40,
55220     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55221   },
55222 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
55223   {
55224     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadc.b", 40,
55225     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55226   },
55227 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
55228   {
55229     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadc.b", 40,
55230     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55231   },
55232 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
55233   {
55234     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadc.b", 40,
55235     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55236   },
55237 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
55238   {
55239     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadc.b", 48,
55240     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55241   },
55242 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
55243   {
55244     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadc.b", 48,
55245     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55246   },
55247 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
55248   {
55249     M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadc.b", 48,
55250     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55251   },
55252 /* dadc.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
55253   {
55254     M32C_INSN_DADC32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "dadc.w", 40,
55255     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55256   },
55257 /* dadc.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
55258   {
55259     M32C_INSN_DADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "dadc.w", 40,
55260     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55261   },
55262 /* dadc.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
55263   {
55264     M32C_INSN_DADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "dadc.w", 40,
55265     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55266   },
55267 /* dadc.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
55268   {
55269     M32C_INSN_DADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "dadc.w", 48,
55270     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55271   },
55272 /* dadc.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
55273   {
55274     M32C_INSN_DADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "dadc.w", 48,
55275     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55276   },
55277 /* dadc.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
55278   {
55279     M32C_INSN_DADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "dadc.w", 48,
55280     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55281   },
55282 /* dadc.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
55283   {
55284     M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "dadc.w", 56,
55285     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55286   },
55287 /* dadc.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
55288   {
55289     M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "dadc.w", 56,
55290     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55291   },
55292 /* dadc.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
55293   {
55294     M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "dadc.w", 56,
55295     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55296   },
55297 /* dadc.w${X} #${Imm-40-HI},${Dsp-24-u16} */
55298   {
55299     M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "dadc.w", 56,
55300     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55301   },
55302 /* dadc.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
55303   {
55304     M32C_INSN_DADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "dadc.w", 64,
55305     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55306   },
55307 /* dadc.w${X} #${Imm-48-HI},${Dsp-24-u24} */
55308   {
55309     M32C_INSN_DADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "dadc.w", 64,
55310     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55311   },
55312 /* dadc.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
55313   {
55314     M32C_INSN_DADC32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "dadc.b", 32,
55315     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55316   },
55317 /* dadc.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
55318   {
55319     M32C_INSN_DADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "dadc.b", 32,
55320     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55321   },
55322 /* dadc.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
55323   {
55324     M32C_INSN_DADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "dadc.b", 32,
55325     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55326   },
55327 /* dadc.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
55328   {
55329     M32C_INSN_DADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "dadc.b", 40,
55330     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55331   },
55332 /* dadc.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
55333   {
55334     M32C_INSN_DADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "dadc.b", 40,
55335     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55336   },
55337 /* dadc.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
55338   {
55339     M32C_INSN_DADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "dadc.b", 40,
55340     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55341   },
55342 /* dadc.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
55343   {
55344     M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "dadc.b", 48,
55345     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55346   },
55347 /* dadc.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
55348   {
55349     M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "dadc.b", 48,
55350     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55351   },
55352 /* dadc.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
55353   {
55354     M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "dadc.b", 48,
55355     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55356   },
55357 /* dadc.b${X} #${Imm-40-QI},${Dsp-24-u16} */
55358   {
55359     M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "dadc.b", 48,
55360     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55361   },
55362 /* dadc.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
55363   {
55364     M32C_INSN_DADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "dadc.b", 56,
55365     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55366   },
55367 /* dadc.b${X} #${Imm-48-QI},${Dsp-24-u24} */
55368   {
55369     M32C_INSN_DADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "dadc.b", 56,
55370     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55371   },
55372 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
55373   {
55374     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 32,
55375     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55376   },
55377 /* adc.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
55378   {
55379     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 32,
55380     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55381   },
55382 /* adc.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
55383   {
55384     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 32,
55385     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55386   },
55387 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
55388   {
55389     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 32,
55390     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55391   },
55392 /* adc.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
55393   {
55394     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 32,
55395     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55396   },
55397 /* adc.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
55398   {
55399     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 32,
55400     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55401   },
55402 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
55403   {
55404     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 32,
55405     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55406   },
55407 /* adc.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
55408   {
55409     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 32,
55410     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55411   },
55412 /* adc.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
55413   {
55414     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 32,
55415     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55416   },
55417 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
55418   {
55419     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "adc.w", 40,
55420     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55421   },
55422 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
55423   {
55424     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "adc.w", 40,
55425     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55426   },
55427 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
55428   {
55429     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "adc.w", 40,
55430     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55431   },
55432 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
55433   {
55434     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "adc.w", 48,
55435     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55436   },
55437 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
55438   {
55439     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "adc.w", 48,
55440     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55441   },
55442 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
55443   {
55444     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "adc.w", 48,
55445     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55446   },
55447 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
55448   {
55449     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "adc.w", 56,
55450     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55451   },
55452 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
55453   {
55454     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "adc.w", 56,
55455     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55456   },
55457 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
55458   {
55459     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "adc.w", 56,
55460     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55461   },
55462 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
55463   {
55464     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "adc.w", 40,
55465     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55466   },
55467 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
55468   {
55469     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "adc.w", 40,
55470     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55471   },
55472 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
55473   {
55474     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "adc.w", 40,
55475     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55476   },
55477 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
55478   {
55479     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "adc.w", 48,
55480     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55481   },
55482 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
55483   {
55484     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "adc.w", 48,
55485     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55486   },
55487 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
55488   {
55489     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "adc.w", 48,
55490     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55491   },
55492 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
55493   {
55494     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "adc.w", 40,
55495     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55496   },
55497 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
55498   {
55499     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "adc.w", 40,
55500     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55501   },
55502 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
55503   {
55504     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "adc.w", 40,
55505     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55506   },
55507 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
55508   {
55509     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "adc.w", 48,
55510     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55511   },
55512 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
55513   {
55514     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "adc.w", 48,
55515     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55516   },
55517 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
55518   {
55519     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "adc.w", 48,
55520     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55521   },
55522 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
55523   {
55524     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "adc.w", 48,
55525     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55526   },
55527 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
55528   {
55529     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "adc.w", 48,
55530     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55531   },
55532 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
55533   {
55534     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "adc.w", 48,
55535     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55536   },
55537 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
55538   {
55539     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "adc.w", 56,
55540     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55541   },
55542 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
55543   {
55544     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "adc.w", 56,
55545     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55546   },
55547 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
55548   {
55549     M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "adc.w", 56,
55550     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55551   },
55552 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
55553   {
55554     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 40,
55555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55556   },
55557 /* adc.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
55558   {
55559     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 40,
55560     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55561   },
55562 /* adc.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
55563   {
55564     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 40,
55565     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55566   },
55567 /* adc.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
55568   {
55569     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 40,
55570     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55571   },
55572 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
55573   {
55574     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 40,
55575     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55576   },
55577 /* adc.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
55578   {
55579     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 40,
55580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55581   },
55582 /* adc.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
55583   {
55584     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 40,
55585     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55586   },
55587 /* adc.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
55588   {
55589     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 40,
55590     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55591   },
55592 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
55593   {
55594     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 40,
55595     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55596   },
55597 /* adc.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
55598   {
55599     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 40,
55600     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55601   },
55602 /* adc.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
55603   {
55604     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 40,
55605     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55606   },
55607 /* adc.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
55608   {
55609     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 40,
55610     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55611   },
55612 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
55613   {
55614     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "adc.w", 48,
55615     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55616   },
55617 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
55618   {
55619     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "adc.w", 48,
55620     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55621   },
55622 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
55623   {
55624     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "adc.w", 48,
55625     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55626   },
55627 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
55628   {
55629     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "adc.w", 48,
55630     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55631   },
55632 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
55633   {
55634     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "adc.w", 56,
55635     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55636   },
55637 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
55638   {
55639     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "adc.w", 56,
55640     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55641   },
55642 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
55643   {
55644     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "adc.w", 56,
55645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55646   },
55647 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
55648   {
55649     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "adc.w", 56,
55650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55651   },
55652 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
55653   {
55654     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "adc.w", 64,
55655     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55656   },
55657 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
55658   {
55659     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "adc.w", 64,
55660     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55661   },
55662 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
55663   {
55664     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "adc.w", 64,
55665     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55666   },
55667 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
55668   {
55669     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "adc.w", 64,
55670     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55671   },
55672 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
55673   {
55674     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "adc.w", 48,
55675     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55676   },
55677 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
55678   {
55679     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "adc.w", 48,
55680     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55681   },
55682 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
55683   {
55684     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "adc.w", 48,
55685     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55686   },
55687 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
55688   {
55689     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "adc.w", 48,
55690     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55691   },
55692 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
55693   {
55694     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "adc.w", 56,
55695     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55696   },
55697 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
55698   {
55699     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "adc.w", 56,
55700     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55701   },
55702 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
55703   {
55704     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "adc.w", 56,
55705     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55706   },
55707 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
55708   {
55709     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "adc.w", 56,
55710     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55711   },
55712 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
55713   {
55714     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "adc.w", 48,
55715     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55716   },
55717 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
55718   {
55719     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "adc.w", 48,
55720     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55721   },
55722 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
55723   {
55724     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "adc.w", 48,
55725     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55726   },
55727 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
55728   {
55729     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "adc.w", 48,
55730     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55731   },
55732 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
55733   {
55734     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "adc.w", 56,
55735     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55736   },
55737 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
55738   {
55739     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "adc.w", 56,
55740     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55741   },
55742 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
55743   {
55744     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "adc.w", 56,
55745     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55746   },
55747 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
55748   {
55749     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "adc.w", 56,
55750     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55751   },
55752 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
55753   {
55754     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "adc.w", 56,
55755     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55756   },
55757 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
55758   {
55759     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "adc.w", 56,
55760     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55761   },
55762 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
55763   {
55764     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "adc.w", 56,
55765     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55766   },
55767 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
55768   {
55769     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "adc.w", 56,
55770     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55771   },
55772 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
55773   {
55774     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "adc.w", 64,
55775     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55776   },
55777 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
55778   {
55779     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "adc.w", 64,
55780     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55781   },
55782 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
55783   {
55784     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "adc.w", 64,
55785     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55786   },
55787 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
55788   {
55789     M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "adc.w", 64,
55790     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55791   },
55792 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
55793   {
55794     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 48,
55795     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55796   },
55797 /* adc.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
55798   {
55799     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 48,
55800     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55801   },
55802 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
55803   {
55804     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 48,
55805     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55806   },
55807 /* adc.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
55808   {
55809     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 48,
55810     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55811   },
55812 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
55813   {
55814     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 48,
55815     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55816   },
55817 /* adc.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
55818   {
55819     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 48,
55820     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55821   },
55822 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
55823   {
55824     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "adc.w", 56,
55825     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55826   },
55827 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
55828   {
55829     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "adc.w", 56,
55830     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55831   },
55832 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
55833   {
55834     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "adc.w", 64,
55835     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55836   },
55837 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
55838   {
55839     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "adc.w", 64,
55840     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55841   },
55842 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
55843   {
55844     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "adc.w", 72,
55845     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55846   },
55847 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
55848   {
55849     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "adc.w", 72,
55850     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55851   },
55852 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
55853   {
55854     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "adc.w", 56,
55855     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55856   },
55857 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
55858   {
55859     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "adc.w", 56,
55860     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55861   },
55862 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
55863   {
55864     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "adc.w", 64,
55865     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55866   },
55867 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
55868   {
55869     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "adc.w", 64,
55870     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55871   },
55872 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
55873   {
55874     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "adc.w", 56,
55875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55876   },
55877 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
55878   {
55879     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "adc.w", 56,
55880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55881   },
55882 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
55883   {
55884     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "adc.w", 64,
55885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55886   },
55887 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
55888   {
55889     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "adc.w", 64,
55890     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55891   },
55892 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
55893   {
55894     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "adc.w", 64,
55895     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55896   },
55897 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
55898   {
55899     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "adc.w", 64,
55900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55901   },
55902 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
55903   {
55904     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "adc.w", 72,
55905     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55906   },
55907 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
55908   {
55909     M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "adc.w", 72,
55910     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55911   },
55912 /* adc.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
55913   {
55914     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 24,
55915     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55916   },
55917 /* adc.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
55918   {
55919     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 24,
55920     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55921   },
55922 /* adc.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
55923   {
55924     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 24,
55925     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55926   },
55927 /* adc.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
55928   {
55929     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 24,
55930     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55931   },
55932 /* adc.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
55933   {
55934     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 24,
55935     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55936   },
55937 /* adc.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
55938   {
55939     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 24,
55940     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55941   },
55942 /* adc.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
55943   {
55944     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 24,
55945     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55946   },
55947 /* adc.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
55948   {
55949     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 24,
55950     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55951   },
55952 /* adc.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
55953   {
55954     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 24,
55955     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55956   },
55957 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
55958   {
55959     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "adc.w", 32,
55960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55961   },
55962 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
55963   {
55964     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "adc.w", 32,
55965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55966   },
55967 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
55968   {
55969     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "adc.w", 32,
55970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55971   },
55972 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
55973   {
55974     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "adc.w", 40,
55975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55976   },
55977 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
55978   {
55979     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "adc.w", 40,
55980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55981   },
55982 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
55983   {
55984     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "adc.w", 40,
55985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55986   },
55987 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
55988   {
55989     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "adc.w", 48,
55990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55991   },
55992 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
55993   {
55994     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "adc.w", 48,
55995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55996   },
55997 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
55998   {
55999     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "adc.w", 48,
56000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56001   },
56002 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
56003   {
56004     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "adc.w", 32,
56005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56006   },
56007 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
56008   {
56009     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "adc.w", 32,
56010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56011   },
56012 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
56013   {
56014     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "adc.w", 32,
56015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56016   },
56017 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
56018   {
56019     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "adc.w", 40,
56020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56021   },
56022 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
56023   {
56024     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "adc.w", 40,
56025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56026   },
56027 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
56028   {
56029     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "adc.w", 40,
56030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56031   },
56032 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
56033   {
56034     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "adc.w", 32,
56035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56036   },
56037 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
56038   {
56039     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "adc.w", 32,
56040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56041   },
56042 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
56043   {
56044     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "adc.w", 32,
56045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56046   },
56047 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
56048   {
56049     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "adc.w", 40,
56050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56051   },
56052 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
56053   {
56054     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "adc.w", 40,
56055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56056   },
56057 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
56058   {
56059     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "adc.w", 40,
56060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56061   },
56062 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
56063   {
56064     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "adc.w", 40,
56065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56066   },
56067 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
56068   {
56069     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "adc.w", 40,
56070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56071   },
56072 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
56073   {
56074     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "adc.w", 40,
56075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56076   },
56077 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
56078   {
56079     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "adc.w", 48,
56080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56081   },
56082 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
56083   {
56084     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "adc.w", 48,
56085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56086   },
56087 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
56088   {
56089     M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "adc.w", 48,
56090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56091   },
56092 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
56093   {
56094     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 32,
56095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56096   },
56097 /* adc.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
56098   {
56099     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 32,
56100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56101   },
56102 /* adc.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
56103   {
56104     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 32,
56105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56106   },
56107 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
56108   {
56109     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 32,
56110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56111   },
56112 /* adc.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
56113   {
56114     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 32,
56115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56116   },
56117 /* adc.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
56118   {
56119     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 32,
56120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56121   },
56122 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
56123   {
56124     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 32,
56125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56126   },
56127 /* adc.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
56128   {
56129     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 32,
56130     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56131   },
56132 /* adc.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
56133   {
56134     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 32,
56135     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56136   },
56137 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
56138   {
56139     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "adc.b", 40,
56140     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56141   },
56142 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
56143   {
56144     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "adc.b", 40,
56145     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56146   },
56147 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
56148   {
56149     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "adc.b", 40,
56150     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56151   },
56152 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
56153   {
56154     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "adc.b", 48,
56155     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56156   },
56157 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
56158   {
56159     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "adc.b", 48,
56160     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56161   },
56162 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
56163   {
56164     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "adc.b", 48,
56165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56166   },
56167 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
56168   {
56169     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "adc.b", 56,
56170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56171   },
56172 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
56173   {
56174     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "adc.b", 56,
56175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56176   },
56177 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
56178   {
56179     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "adc.b", 56,
56180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56181   },
56182 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
56183   {
56184     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "adc.b", 40,
56185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56186   },
56187 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
56188   {
56189     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "adc.b", 40,
56190     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56191   },
56192 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
56193   {
56194     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "adc.b", 40,
56195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56196   },
56197 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
56198   {
56199     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "adc.b", 48,
56200     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56201   },
56202 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
56203   {
56204     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "adc.b", 48,
56205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56206   },
56207 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
56208   {
56209     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "adc.b", 48,
56210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56211   },
56212 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
56213   {
56214     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "adc.b", 40,
56215     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56216   },
56217 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
56218   {
56219     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "adc.b", 40,
56220     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56221   },
56222 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
56223   {
56224     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "adc.b", 40,
56225     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56226   },
56227 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
56228   {
56229     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "adc.b", 48,
56230     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56231   },
56232 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
56233   {
56234     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "adc.b", 48,
56235     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56236   },
56237 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
56238   {
56239     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "adc.b", 48,
56240     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56241   },
56242 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
56243   {
56244     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "adc.b", 48,
56245     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56246   },
56247 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
56248   {
56249     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "adc.b", 48,
56250     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56251   },
56252 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
56253   {
56254     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "adc.b", 48,
56255     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56256   },
56257 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
56258   {
56259     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "adc.b", 56,
56260     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56261   },
56262 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
56263   {
56264     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "adc.b", 56,
56265     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56266   },
56267 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
56268   {
56269     M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "adc.b", 56,
56270     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56271   },
56272 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
56273   {
56274     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 40,
56275     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56276   },
56277 /* adc.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
56278   {
56279     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 40,
56280     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56281   },
56282 /* adc.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
56283   {
56284     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 40,
56285     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56286   },
56287 /* adc.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
56288   {
56289     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 40,
56290     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56291   },
56292 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
56293   {
56294     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 40,
56295     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56296   },
56297 /* adc.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
56298   {
56299     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 40,
56300     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56301   },
56302 /* adc.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
56303   {
56304     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 40,
56305     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56306   },
56307 /* adc.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
56308   {
56309     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 40,
56310     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56311   },
56312 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
56313   {
56314     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 40,
56315     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56316   },
56317 /* adc.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
56318   {
56319     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 40,
56320     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56321   },
56322 /* adc.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
56323   {
56324     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 40,
56325     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56326   },
56327 /* adc.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
56328   {
56329     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 40,
56330     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56331   },
56332 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
56333   {
56334     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "adc.b", 48,
56335     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56336   },
56337 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
56338   {
56339     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "adc.b", 48,
56340     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56341   },
56342 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
56343   {
56344     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "adc.b", 48,
56345     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56346   },
56347 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
56348   {
56349     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "adc.b", 48,
56350     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56351   },
56352 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
56353   {
56354     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "adc.b", 56,
56355     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56356   },
56357 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
56358   {
56359     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "adc.b", 56,
56360     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56361   },
56362 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
56363   {
56364     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "adc.b", 56,
56365     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56366   },
56367 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
56368   {
56369     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "adc.b", 56,
56370     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56371   },
56372 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
56373   {
56374     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "adc.b", 64,
56375     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56376   },
56377 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
56378   {
56379     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "adc.b", 64,
56380     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56381   },
56382 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
56383   {
56384     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "adc.b", 64,
56385     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56386   },
56387 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
56388   {
56389     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "adc.b", 64,
56390     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56391   },
56392 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
56393   {
56394     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "adc.b", 48,
56395     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56396   },
56397 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
56398   {
56399     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "adc.b", 48,
56400     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56401   },
56402 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
56403   {
56404     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "adc.b", 48,
56405     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56406   },
56407 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
56408   {
56409     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "adc.b", 48,
56410     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56411   },
56412 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
56413   {
56414     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "adc.b", 56,
56415     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56416   },
56417 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
56418   {
56419     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "adc.b", 56,
56420     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56421   },
56422 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
56423   {
56424     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "adc.b", 56,
56425     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56426   },
56427 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
56428   {
56429     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "adc.b", 56,
56430     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56431   },
56432 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
56433   {
56434     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "adc.b", 48,
56435     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56436   },
56437 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
56438   {
56439     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "adc.b", 48,
56440     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56441   },
56442 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
56443   {
56444     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "adc.b", 48,
56445     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56446   },
56447 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
56448   {
56449     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "adc.b", 48,
56450     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56451   },
56452 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
56453   {
56454     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "adc.b", 56,
56455     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56456   },
56457 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
56458   {
56459     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "adc.b", 56,
56460     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56461   },
56462 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
56463   {
56464     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "adc.b", 56,
56465     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56466   },
56467 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
56468   {
56469     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "adc.b", 56,
56470     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56471   },
56472 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
56473   {
56474     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "adc.b", 56,
56475     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56476   },
56477 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
56478   {
56479     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "adc.b", 56,
56480     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56481   },
56482 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
56483   {
56484     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "adc.b", 56,
56485     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56486   },
56487 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
56488   {
56489     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "adc.b", 56,
56490     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56491   },
56492 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
56493   {
56494     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "adc.b", 64,
56495     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56496   },
56497 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
56498   {
56499     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "adc.b", 64,
56500     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56501   },
56502 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
56503   {
56504     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "adc.b", 64,
56505     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56506   },
56507 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
56508   {
56509     M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "adc.b", 64,
56510     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56511   },
56512 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
56513   {
56514     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 48,
56515     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56516   },
56517 /* adc.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
56518   {
56519     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 48,
56520     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56521   },
56522 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
56523   {
56524     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 48,
56525     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56526   },
56527 /* adc.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
56528   {
56529     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 48,
56530     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56531   },
56532 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
56533   {
56534     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 48,
56535     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56536   },
56537 /* adc.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
56538   {
56539     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 48,
56540     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56541   },
56542 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
56543   {
56544     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "adc.b", 56,
56545     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56546   },
56547 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
56548   {
56549     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "adc.b", 56,
56550     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56551   },
56552 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
56553   {
56554     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "adc.b", 64,
56555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56556   },
56557 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
56558   {
56559     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "adc.b", 64,
56560     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56561   },
56562 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
56563   {
56564     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "adc.b", 72,
56565     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56566   },
56567 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
56568   {
56569     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "adc.b", 72,
56570     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56571   },
56572 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
56573   {
56574     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "adc.b", 56,
56575     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56576   },
56577 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
56578   {
56579     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "adc.b", 56,
56580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56581   },
56582 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
56583   {
56584     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "adc.b", 64,
56585     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56586   },
56587 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
56588   {
56589     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "adc.b", 64,
56590     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56591   },
56592 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
56593   {
56594     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "adc.b", 56,
56595     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56596   },
56597 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
56598   {
56599     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "adc.b", 56,
56600     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56601   },
56602 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
56603   {
56604     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "adc.b", 64,
56605     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56606   },
56607 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
56608   {
56609     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "adc.b", 64,
56610     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56611   },
56612 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
56613   {
56614     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "adc.b", 64,
56615     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56616   },
56617 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
56618   {
56619     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "adc.b", 64,
56620     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56621   },
56622 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
56623   {
56624     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "adc.b", 72,
56625     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56626   },
56627 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
56628   {
56629     M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "adc.b", 72,
56630     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56631   },
56632 /* adc.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
56633   {
56634     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 24,
56635     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56636   },
56637 /* adc.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
56638   {
56639     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 24,
56640     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56641   },
56642 /* adc.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
56643   {
56644     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 24,
56645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56646   },
56647 /* adc.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
56648   {
56649     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 24,
56650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56651   },
56652 /* adc.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
56653   {
56654     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 24,
56655     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56656   },
56657 /* adc.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
56658   {
56659     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 24,
56660     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56661   },
56662 /* adc.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
56663   {
56664     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 24,
56665     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56666   },
56667 /* adc.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
56668   {
56669     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 24,
56670     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56671   },
56672 /* adc.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
56673   {
56674     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 24,
56675     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56676   },
56677 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
56678   {
56679     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "adc.b", 32,
56680     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56681   },
56682 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
56683   {
56684     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "adc.b", 32,
56685     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56686   },
56687 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
56688   {
56689     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "adc.b", 32,
56690     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56691   },
56692 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
56693   {
56694     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "adc.b", 40,
56695     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56696   },
56697 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
56698   {
56699     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "adc.b", 40,
56700     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56701   },
56702 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
56703   {
56704     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "adc.b", 40,
56705     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56706   },
56707 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
56708   {
56709     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "adc.b", 48,
56710     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56711   },
56712 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
56713   {
56714     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "adc.b", 48,
56715     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56716   },
56717 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
56718   {
56719     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "adc.b", 48,
56720     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56721   },
56722 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
56723   {
56724     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "adc.b", 32,
56725     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56726   },
56727 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
56728   {
56729     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "adc.b", 32,
56730     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56731   },
56732 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
56733   {
56734     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "adc.b", 32,
56735     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56736   },
56737 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
56738   {
56739     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "adc.b", 40,
56740     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56741   },
56742 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
56743   {
56744     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "adc.b", 40,
56745     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56746   },
56747 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
56748   {
56749     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "adc.b", 40,
56750     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56751   },
56752 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
56753   {
56754     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "adc.b", 32,
56755     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56756   },
56757 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
56758   {
56759     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "adc.b", 32,
56760     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56761   },
56762 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
56763   {
56764     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "adc.b", 32,
56765     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56766   },
56767 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
56768   {
56769     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "adc.b", 40,
56770     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56771   },
56772 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
56773   {
56774     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "adc.b", 40,
56775     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56776   },
56777 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
56778   {
56779     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "adc.b", 40,
56780     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56781   },
56782 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
56783   {
56784     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "adc.b", 40,
56785     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56786   },
56787 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
56788   {
56789     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "adc.b", 40,
56790     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56791   },
56792 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
56793   {
56794     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "adc.b", 40,
56795     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56796   },
56797 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
56798   {
56799     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "adc.b", 48,
56800     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56801   },
56802 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
56803   {
56804     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "adc.b", 48,
56805     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56806   },
56807 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
56808   {
56809     M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "adc.b", 48,
56810     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56811   },
56812 /* adc.w${X} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
56813   {
56814     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "adc.w", 24,
56815     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56816   },
56817 /* adc.w${X} ${Dsp-16-u8}[sb],$Dst16RnHI */
56818   {
56819     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "adc.w", 24,
56820     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56821   },
56822 /* adc.w${X} ${Dsp-16-s8}[fb],$Dst16RnHI */
56823   {
56824     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "adc.w", 24,
56825     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56826   },
56827 /* adc.w${X} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
56828   {
56829     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "adc.w", 24,
56830     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56831   },
56832 /* adc.w${X} ${Dsp-16-u8}[sb],$Dst16AnHI */
56833   {
56834     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "adc.w", 24,
56835     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56836   },
56837 /* adc.w${X} ${Dsp-16-s8}[fb],$Dst16AnHI */
56838   {
56839     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "adc.w", 24,
56840     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56841   },
56842 /* adc.w${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
56843   {
56844     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "adc.w", 24,
56845     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56846   },
56847 /* adc.w${X} ${Dsp-16-u8}[sb],[$Dst16An] */
56848   {
56849     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "adc.w", 24,
56850     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56851   },
56852 /* adc.w${X} ${Dsp-16-s8}[fb],[$Dst16An] */
56853   {
56854     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "adc.w", 24,
56855     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56856   },
56857 /* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
56858   {
56859     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "adc.w", 32,
56860     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56861   },
56862 /* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
56863   {
56864     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "adc.w", 32,
56865     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56866   },
56867 /* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
56868   {
56869     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "adc.w", 32,
56870     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56871   },
56872 /* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
56873   {
56874     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "adc.w", 40,
56875     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56876   },
56877 /* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
56878   {
56879     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "adc.w", 40,
56880     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56881   },
56882 /* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
56883   {
56884     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "adc.w", 40,
56885     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56886   },
56887 /* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
56888   {
56889     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "adc.w", 32,
56890     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56891   },
56892 /* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
56893   {
56894     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "adc.w", 32,
56895     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56896   },
56897 /* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
56898   {
56899     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "adc.w", 32,
56900     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56901   },
56902 /* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
56903   {
56904     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "adc.w", 40,
56905     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56906   },
56907 /* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
56908   {
56909     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "adc.w", 40,
56910     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56911   },
56912 /* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
56913   {
56914     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "adc.w", 40,
56915     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56916   },
56917 /* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
56918   {
56919     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "adc.w", 32,
56920     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56921   },
56922 /* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
56923   {
56924     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "adc.w", 32,
56925     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56926   },
56927 /* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
56928   {
56929     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "adc.w", 32,
56930     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56931   },
56932 /* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
56933   {
56934     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "adc.w", 40,
56935     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56936   },
56937 /* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
56938   {
56939     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "adc.w", 40,
56940     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56941   },
56942 /* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
56943   {
56944     M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "adc.w", 40,
56945     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56946   },
56947 /* adc.w${X} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
56948   {
56949     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "adc.w", 32,
56950     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56951   },
56952 /* adc.w${X} ${Dsp-16-u16}[sb],$Dst16RnHI */
56953   {
56954     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "adc.w", 32,
56955     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56956   },
56957 /* adc.w${X} ${Dsp-16-u16},$Dst16RnHI */
56958   {
56959     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "adc.w", 32,
56960     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56961   },
56962 /* adc.w${X} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
56963   {
56964     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "adc.w", 32,
56965     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56966   },
56967 /* adc.w${X} ${Dsp-16-u16}[sb],$Dst16AnHI */
56968   {
56969     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "adc.w", 32,
56970     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56971   },
56972 /* adc.w${X} ${Dsp-16-u16},$Dst16AnHI */
56973   {
56974     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "adc.w", 32,
56975     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56976   },
56977 /* adc.w${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
56978   {
56979     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "adc.w", 32,
56980     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56981   },
56982 /* adc.w${X} ${Dsp-16-u16}[sb],[$Dst16An] */
56983   {
56984     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "adc.w", 32,
56985     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56986   },
56987 /* adc.w${X} ${Dsp-16-u16},[$Dst16An] */
56988   {
56989     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "adc.w", 32,
56990     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56991   },
56992 /* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
56993   {
56994     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "adc.w", 40,
56995     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56996   },
56997 /* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
56998   {
56999     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "adc.w", 40,
57000     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57001   },
57002 /* adc.w${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
57003   {
57004     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "adc.w", 40,
57005     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57006   },
57007 /* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
57008   {
57009     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "adc.w", 48,
57010     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57011   },
57012 /* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
57013   {
57014     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "adc.w", 48,
57015     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57016   },
57017 /* adc.w${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
57018   {
57019     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "adc.w", 48,
57020     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57021   },
57022 /* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
57023   {
57024     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "adc.w", 40,
57025     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57026   },
57027 /* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
57028   {
57029     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "adc.w", 40,
57030     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57031   },
57032 /* adc.w${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
57033   {
57034     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "adc.w", 40,
57035     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57036   },
57037 /* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
57038   {
57039     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "adc.w", 48,
57040     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57041   },
57042 /* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
57043   {
57044     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "adc.w", 48,
57045     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57046   },
57047 /* adc.w${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
57048   {
57049     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "adc.w", 48,
57050     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57051   },
57052 /* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
57053   {
57054     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "adc.w", 40,
57055     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57056   },
57057 /* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
57058   {
57059     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "adc.w", 40,
57060     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57061   },
57062 /* adc.w${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
57063   {
57064     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "adc.w", 40,
57065     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57066   },
57067 /* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
57068   {
57069     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "adc.w", 48,
57070     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57071   },
57072 /* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
57073   {
57074     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "adc.w", 48,
57075     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57076   },
57077 /* adc.w${X} ${Dsp-16-u16},${Dsp-32-u16} */
57078   {
57079     M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "adc.w", 48,
57080     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57081   },
57082 /* adc.w${X} $Src16RnHI,$Dst16RnHI */
57083   {
57084     M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "adc.w", 16,
57085     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57086   },
57087 /* adc.w${X} $Src16AnHI,$Dst16RnHI */
57088   {
57089     M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "adc.w", 16,
57090     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57091   },
57092 /* adc.w${X} [$Src16An],$Dst16RnHI */
57093   {
57094     M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "adc.w", 16,
57095     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57096   },
57097 /* adc.w${X} $Src16RnHI,$Dst16AnHI */
57098   {
57099     M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "adc.w", 16,
57100     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57101   },
57102 /* adc.w${X} $Src16AnHI,$Dst16AnHI */
57103   {
57104     M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "adc.w", 16,
57105     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57106   },
57107 /* adc.w${X} [$Src16An],$Dst16AnHI */
57108   {
57109     M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "adc.w", 16,
57110     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57111   },
57112 /* adc.w${X} $Src16RnHI,[$Dst16An] */
57113   {
57114     M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "adc.w", 16,
57115     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57116   },
57117 /* adc.w${X} $Src16AnHI,[$Dst16An] */
57118   {
57119     M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "adc.w", 16,
57120     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57121   },
57122 /* adc.w${X} [$Src16An],[$Dst16An] */
57123   {
57124     M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "adc.w", 16,
57125     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57126   },
57127 /* adc.w${X} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
57128   {
57129     M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "adc.w", 24,
57130     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57131   },
57132 /* adc.w${X} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
57133   {
57134     M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "adc.w", 24,
57135     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57136   },
57137 /* adc.w${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
57138   {
57139     M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "adc.w", 24,
57140     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57141   },
57142 /* adc.w${X} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
57143   {
57144     M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "adc.w", 32,
57145     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57146   },
57147 /* adc.w${X} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
57148   {
57149     M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "adc.w", 32,
57150     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57151   },
57152 /* adc.w${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
57153   {
57154     M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "adc.w", 32,
57155     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57156   },
57157 /* adc.w${X} $Src16RnHI,${Dsp-16-u8}[sb] */
57158   {
57159     M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "adc.w", 24,
57160     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57161   },
57162 /* adc.w${X} $Src16AnHI,${Dsp-16-u8}[sb] */
57163   {
57164     M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "adc.w", 24,
57165     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57166   },
57167 /* adc.w${X} [$Src16An],${Dsp-16-u8}[sb] */
57168   {
57169     M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "adc.w", 24,
57170     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57171   },
57172 /* adc.w${X} $Src16RnHI,${Dsp-16-u16}[sb] */
57173   {
57174     M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "adc.w", 32,
57175     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57176   },
57177 /* adc.w${X} $Src16AnHI,${Dsp-16-u16}[sb] */
57178   {
57179     M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "adc.w", 32,
57180     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57181   },
57182 /* adc.w${X} [$Src16An],${Dsp-16-u16}[sb] */
57183   {
57184     M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "adc.w", 32,
57185     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57186   },
57187 /* adc.w${X} $Src16RnHI,${Dsp-16-s8}[fb] */
57188   {
57189     M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "adc.w", 24,
57190     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57191   },
57192 /* adc.w${X} $Src16AnHI,${Dsp-16-s8}[fb] */
57193   {
57194     M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "adc.w", 24,
57195     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57196   },
57197 /* adc.w${X} [$Src16An],${Dsp-16-s8}[fb] */
57198   {
57199     M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "adc.w", 24,
57200     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57201   },
57202 /* adc.w${X} $Src16RnHI,${Dsp-16-u16} */
57203   {
57204     M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "adc.w", 32,
57205     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57206   },
57207 /* adc.w${X} $Src16AnHI,${Dsp-16-u16} */
57208   {
57209     M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "adc.w", 32,
57210     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57211   },
57212 /* adc.w${X} [$Src16An],${Dsp-16-u16} */
57213   {
57214     M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "adc.w", 32,
57215     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57216   },
57217 /* adc.b${X} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
57218   {
57219     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "adc.b", 24,
57220     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57221   },
57222 /* adc.b${X} ${Dsp-16-u8}[sb],$Dst16RnQI */
57223   {
57224     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "adc.b", 24,
57225     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57226   },
57227 /* adc.b${X} ${Dsp-16-s8}[fb],$Dst16RnQI */
57228   {
57229     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "adc.b", 24,
57230     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57231   },
57232 /* adc.b${X} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
57233   {
57234     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "adc.b", 24,
57235     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57236   },
57237 /* adc.b${X} ${Dsp-16-u8}[sb],$Dst16AnQI */
57238   {
57239     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "adc.b", 24,
57240     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57241   },
57242 /* adc.b${X} ${Dsp-16-s8}[fb],$Dst16AnQI */
57243   {
57244     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "adc.b", 24,
57245     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57246   },
57247 /* adc.b${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
57248   {
57249     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "adc.b", 24,
57250     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57251   },
57252 /* adc.b${X} ${Dsp-16-u8}[sb],[$Dst16An] */
57253   {
57254     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "adc.b", 24,
57255     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57256   },
57257 /* adc.b${X} ${Dsp-16-s8}[fb],[$Dst16An] */
57258   {
57259     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "adc.b", 24,
57260     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57261   },
57262 /* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
57263   {
57264     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "adc.b", 32,
57265     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57266   },
57267 /* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
57268   {
57269     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "adc.b", 32,
57270     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57271   },
57272 /* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
57273   {
57274     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "adc.b", 32,
57275     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57276   },
57277 /* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
57278   {
57279     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "adc.b", 40,
57280     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57281   },
57282 /* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
57283   {
57284     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "adc.b", 40,
57285     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57286   },
57287 /* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
57288   {
57289     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "adc.b", 40,
57290     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57291   },
57292 /* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
57293   {
57294     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "adc.b", 32,
57295     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57296   },
57297 /* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
57298   {
57299     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "adc.b", 32,
57300     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57301   },
57302 /* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
57303   {
57304     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "adc.b", 32,
57305     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57306   },
57307 /* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
57308   {
57309     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "adc.b", 40,
57310     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57311   },
57312 /* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
57313   {
57314     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "adc.b", 40,
57315     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57316   },
57317 /* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
57318   {
57319     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "adc.b", 40,
57320     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57321   },
57322 /* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
57323   {
57324     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "adc.b", 32,
57325     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57326   },
57327 /* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
57328   {
57329     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "adc.b", 32,
57330     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57331   },
57332 /* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
57333   {
57334     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "adc.b", 32,
57335     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57336   },
57337 /* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
57338   {
57339     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "adc.b", 40,
57340     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57341   },
57342 /* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
57343   {
57344     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "adc.b", 40,
57345     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57346   },
57347 /* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
57348   {
57349     M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "adc.b", 40,
57350     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57351   },
57352 /* adc.b${X} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
57353   {
57354     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "adc.b", 32,
57355     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57356   },
57357 /* adc.b${X} ${Dsp-16-u16}[sb],$Dst16RnQI */
57358   {
57359     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "adc.b", 32,
57360     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57361   },
57362 /* adc.b${X} ${Dsp-16-u16},$Dst16RnQI */
57363   {
57364     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "adc.b", 32,
57365     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57366   },
57367 /* adc.b${X} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
57368   {
57369     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "adc.b", 32,
57370     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57371   },
57372 /* adc.b${X} ${Dsp-16-u16}[sb],$Dst16AnQI */
57373   {
57374     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "adc.b", 32,
57375     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57376   },
57377 /* adc.b${X} ${Dsp-16-u16},$Dst16AnQI */
57378   {
57379     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "adc.b", 32,
57380     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57381   },
57382 /* adc.b${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
57383   {
57384     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "adc.b", 32,
57385     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57386   },
57387 /* adc.b${X} ${Dsp-16-u16}[sb],[$Dst16An] */
57388   {
57389     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "adc.b", 32,
57390     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57391   },
57392 /* adc.b${X} ${Dsp-16-u16},[$Dst16An] */
57393   {
57394     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "adc.b", 32,
57395     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57396   },
57397 /* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
57398   {
57399     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "adc.b", 40,
57400     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57401   },
57402 /* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
57403   {
57404     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "adc.b", 40,
57405     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57406   },
57407 /* adc.b${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
57408   {
57409     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "adc.b", 40,
57410     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57411   },
57412 /* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
57413   {
57414     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "adc.b", 48,
57415     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57416   },
57417 /* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
57418   {
57419     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "adc.b", 48,
57420     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57421   },
57422 /* adc.b${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
57423   {
57424     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "adc.b", 48,
57425     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57426   },
57427 /* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
57428   {
57429     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "adc.b", 40,
57430     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57431   },
57432 /* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
57433   {
57434     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "adc.b", 40,
57435     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57436   },
57437 /* adc.b${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
57438   {
57439     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "adc.b", 40,
57440     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57441   },
57442 /* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
57443   {
57444     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "adc.b", 48,
57445     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57446   },
57447 /* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
57448   {
57449     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "adc.b", 48,
57450     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57451   },
57452 /* adc.b${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
57453   {
57454     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "adc.b", 48,
57455     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57456   },
57457 /* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
57458   {
57459     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "adc.b", 40,
57460     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57461   },
57462 /* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
57463   {
57464     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "adc.b", 40,
57465     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57466   },
57467 /* adc.b${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
57468   {
57469     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "adc.b", 40,
57470     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57471   },
57472 /* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
57473   {
57474     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "adc.b", 48,
57475     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57476   },
57477 /* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
57478   {
57479     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "adc.b", 48,
57480     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57481   },
57482 /* adc.b${X} ${Dsp-16-u16},${Dsp-32-u16} */
57483   {
57484     M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "adc.b", 48,
57485     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57486   },
57487 /* adc.b${X} $Src16RnQI,$Dst16RnQI */
57488   {
57489     M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "adc.b", 16,
57490     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57491   },
57492 /* adc.b${X} $Src16AnQI,$Dst16RnQI */
57493   {
57494     M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "adc.b", 16,
57495     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57496   },
57497 /* adc.b${X} [$Src16An],$Dst16RnQI */
57498   {
57499     M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "adc.b", 16,
57500     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57501   },
57502 /* adc.b${X} $Src16RnQI,$Dst16AnQI */
57503   {
57504     M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "adc.b", 16,
57505     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57506   },
57507 /* adc.b${X} $Src16AnQI,$Dst16AnQI */
57508   {
57509     M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "adc.b", 16,
57510     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57511   },
57512 /* adc.b${X} [$Src16An],$Dst16AnQI */
57513   {
57514     M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "adc.b", 16,
57515     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57516   },
57517 /* adc.b${X} $Src16RnQI,[$Dst16An] */
57518   {
57519     M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "adc.b", 16,
57520     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57521   },
57522 /* adc.b${X} $Src16AnQI,[$Dst16An] */
57523   {
57524     M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "adc.b", 16,
57525     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57526   },
57527 /* adc.b${X} [$Src16An],[$Dst16An] */
57528   {
57529     M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "adc.b", 16,
57530     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57531   },
57532 /* adc.b${X} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
57533   {
57534     M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "adc.b", 24,
57535     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57536   },
57537 /* adc.b${X} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
57538   {
57539     M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "adc.b", 24,
57540     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57541   },
57542 /* adc.b${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
57543   {
57544     M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "adc.b", 24,
57545     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57546   },
57547 /* adc.b${X} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
57548   {
57549     M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "adc.b", 32,
57550     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57551   },
57552 /* adc.b${X} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
57553   {
57554     M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "adc.b", 32,
57555     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57556   },
57557 /* adc.b${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
57558   {
57559     M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "adc.b", 32,
57560     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57561   },
57562 /* adc.b${X} $Src16RnQI,${Dsp-16-u8}[sb] */
57563   {
57564     M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "adc.b", 24,
57565     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57566   },
57567 /* adc.b${X} $Src16AnQI,${Dsp-16-u8}[sb] */
57568   {
57569     M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "adc.b", 24,
57570     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57571   },
57572 /* adc.b${X} [$Src16An],${Dsp-16-u8}[sb] */
57573   {
57574     M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "adc.b", 24,
57575     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57576   },
57577 /* adc.b${X} $Src16RnQI,${Dsp-16-u16}[sb] */
57578   {
57579     M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "adc.b", 32,
57580     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57581   },
57582 /* adc.b${X} $Src16AnQI,${Dsp-16-u16}[sb] */
57583   {
57584     M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "adc.b", 32,
57585     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57586   },
57587 /* adc.b${X} [$Src16An],${Dsp-16-u16}[sb] */
57588   {
57589     M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "adc.b", 32,
57590     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57591   },
57592 /* adc.b${X} $Src16RnQI,${Dsp-16-s8}[fb] */
57593   {
57594     M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "adc.b", 24,
57595     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57596   },
57597 /* adc.b${X} $Src16AnQI,${Dsp-16-s8}[fb] */
57598   {
57599     M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "adc.b", 24,
57600     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57601   },
57602 /* adc.b${X} [$Src16An],${Dsp-16-s8}[fb] */
57603   {
57604     M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "adc.b", 24,
57605     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57606   },
57607 /* adc.b${X} $Src16RnQI,${Dsp-16-u16} */
57608   {
57609     M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "adc.b", 32,
57610     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57611   },
57612 /* adc.b${X} $Src16AnQI,${Dsp-16-u16} */
57613   {
57614     M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "adc.b", 32,
57615     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57616   },
57617 /* adc.b${X} [$Src16An],${Dsp-16-u16} */
57618   {
57619     M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "adc.b", 32,
57620     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57621   },
57622 /* adc.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
57623   {
57624     M32C_INSN_ADC32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "adc.w", 40,
57625     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57626   },
57627 /* adc.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
57628   {
57629     M32C_INSN_ADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "adc.w", 40,
57630     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57631   },
57632 /* adc.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
57633   {
57634     M32C_INSN_ADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "adc.w", 40,
57635     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57636   },
57637 /* adc.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
57638   {
57639     M32C_INSN_ADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "adc.w", 48,
57640     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57641   },
57642 /* adc.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
57643   {
57644     M32C_INSN_ADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "adc.w", 48,
57645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57646   },
57647 /* adc.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
57648   {
57649     M32C_INSN_ADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "adc.w", 48,
57650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57651   },
57652 /* adc.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
57653   {
57654     M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "adc.w", 56,
57655     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57656   },
57657 /* adc.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
57658   {
57659     M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "adc.w", 56,
57660     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57661   },
57662 /* adc.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
57663   {
57664     M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "adc.w", 56,
57665     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57666   },
57667 /* adc.w${X} #${Imm-40-HI},${Dsp-24-u16} */
57668   {
57669     M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "adc32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "adc.w", 56,
57670     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57671   },
57672 /* adc.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
57673   {
57674     M32C_INSN_ADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "adc.w", 64,
57675     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57676   },
57677 /* adc.w${X} #${Imm-48-HI},${Dsp-24-u24} */
57678   {
57679     M32C_INSN_ADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "adc32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "adc.w", 64,
57680     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57681   },
57682 /* adc.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
57683   {
57684     M32C_INSN_ADC32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "adc.b", 32,
57685     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57686   },
57687 /* adc.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
57688   {
57689     M32C_INSN_ADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "adc.b", 32,
57690     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57691   },
57692 /* adc.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
57693   {
57694     M32C_INSN_ADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "adc.b", 32,
57695     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57696   },
57697 /* adc.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
57698   {
57699     M32C_INSN_ADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "adc.b", 40,
57700     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57701   },
57702 /* adc.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
57703   {
57704     M32C_INSN_ADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "adc.b", 40,
57705     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57706   },
57707 /* adc.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
57708   {
57709     M32C_INSN_ADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "adc.b", 40,
57710     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57711   },
57712 /* adc.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
57713   {
57714     M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "adc.b", 48,
57715     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57716   },
57717 /* adc.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
57718   {
57719     M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "adc.b", 48,
57720     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57721   },
57722 /* adc.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
57723   {
57724     M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "adc.b", 48,
57725     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57726   },
57727 /* adc.b${X} #${Imm-40-QI},${Dsp-24-u16} */
57728   {
57729     M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "adc32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "adc.b", 48,
57730     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57731   },
57732 /* adc.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
57733   {
57734     M32C_INSN_ADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "adc.b", 56,
57735     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57736   },
57737 /* adc.b${X} #${Imm-48-QI},${Dsp-24-u24} */
57738   {
57739     M32C_INSN_ADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "adc32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "adc.b", 56,
57740     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57741   },
57742 /* adc.w${X} #${Imm-16-HI},$Dst16RnHI */
57743   {
57744     M32C_INSN_ADC16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "adc16.w-imm-G-basic-dst16-Rn-direct-HI", "adc.w", 32,
57745     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57746   },
57747 /* adc.w${X} #${Imm-16-HI},$Dst16AnHI */
57748   {
57749     M32C_INSN_ADC16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "adc16.w-imm-G-basic-dst16-An-direct-HI", "adc.w", 32,
57750     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57751   },
57752 /* adc.w${X} #${Imm-16-HI},[$Dst16An] */
57753   {
57754     M32C_INSN_ADC16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "adc16.w-imm-G-basic-dst16-An-indirect-HI", "adc.w", 32,
57755     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57756   },
57757 /* adc.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
57758   {
57759     M32C_INSN_ADC16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "adc16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "adc.w", 40,
57760     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57761   },
57762 /* adc.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
57763   {
57764     M32C_INSN_ADC16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "adc16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "adc.w", 40,
57765     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57766   },
57767 /* adc.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
57768   {
57769     M32C_INSN_ADC16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "adc16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "adc.w", 40,
57770     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57771   },
57772 /* adc.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
57773   {
57774     M32C_INSN_ADC16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "adc16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "adc.w", 48,
57775     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57776   },
57777 /* adc.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
57778   {
57779     M32C_INSN_ADC16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "adc16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "adc.w", 48,
57780     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57781   },
57782 /* adc.w${X} #${Imm-32-HI},${Dsp-16-u16} */
57783   {
57784     M32C_INSN_ADC16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "adc16.w-imm-G-16-16-dst16-16-16-absolute-HI", "adc.w", 48,
57785     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57786   },
57787 /* adc.b${X} #${Imm-16-QI},$Dst16RnQI */
57788   {
57789     M32C_INSN_ADC16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "adc16.b-imm-G-basic-dst16-Rn-direct-QI", "adc.b", 24,
57790     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57791   },
57792 /* adc.b${X} #${Imm-16-QI},$Dst16AnQI */
57793   {
57794     M32C_INSN_ADC16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "adc16.b-imm-G-basic-dst16-An-direct-QI", "adc.b", 24,
57795     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57796   },
57797 /* adc.b${X} #${Imm-16-QI},[$Dst16An] */
57798   {
57799     M32C_INSN_ADC16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "adc16.b-imm-G-basic-dst16-An-indirect-QI", "adc.b", 24,
57800     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57801   },
57802 /* adc.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
57803   {
57804     M32C_INSN_ADC16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "adc16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "adc.b", 32,
57805     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57806   },
57807 /* adc.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
57808   {
57809     M32C_INSN_ADC16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "adc16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "adc.b", 32,
57810     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57811   },
57812 /* adc.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
57813   {
57814     M32C_INSN_ADC16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "adc16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "adc.b", 32,
57815     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57816   },
57817 /* adc.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
57818   {
57819     M32C_INSN_ADC16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "adc16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "adc.b", 40,
57820     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57821   },
57822 /* adc.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
57823   {
57824     M32C_INSN_ADC16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "adc16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "adc.b", 40,
57825     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57826   },
57827 /* adc.b${X} #${Imm-32-QI},${Dsp-16-u16} */
57828   {
57829     M32C_INSN_ADC16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "adc16.b-imm-G-16-16-dst16-16-16-absolute-QI", "adc.b", 40,
57830     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57831   },
57832 /* add.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
57833   {
57834     M32C_INSN_ADD32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "add32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "add.w", 32,
57835     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57836   },
57837 /* add.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
57838   {
57839     M32C_INSN_ADD32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "add32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "add.w", 32,
57840     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57841   },
57842 /* add.w${S} #${Imm-24-HI},${Dsp-8-u16} */
57843   {
57844     M32C_INSN_ADD32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "add32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "add.w", 40,
57845     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57846   },
57847 /* add.w${S} #${Imm-8-HI},r0 */
57848   {
57849     M32C_INSN_ADD32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "add32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "add.w", 24,
57850     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57851   },
57852 /* add.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
57853   {
57854     M32C_INSN_ADD32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "add32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "add.b", 24,
57855     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57856   },
57857 /* add.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
57858   {
57859     M32C_INSN_ADD32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "add32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "add.b", 24,
57860     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57861   },
57862 /* add.b${S} #${Imm-24-QI},${Dsp-8-u16} */
57863   {
57864     M32C_INSN_ADD32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "add32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "add.b", 32,
57865     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57866   },
57867 /* add.b${S} #${Imm-8-QI},r0l */
57868   {
57869     M32C_INSN_ADD32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "add32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "add.b", 16,
57870     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57871   },
57872 /* add.l${S} #${Imm1-S},a0 */
57873   {
57874     M32C_INSN_ADD32_L_S_IMM1_S_AN_DST32_1_S_A0_DIRECT_HI, "add32.l-s-imm1-S-an-dst32-1-S-A0-direct-HI", "add.l", 8,
57875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57876   },
57877 /* add.l${S} #${Imm1-S},a1 */
57878   {
57879     M32C_INSN_ADD32_L_S_IMM1_S_AN_DST32_1_S_A1_DIRECT_HI, "add32.l-s-imm1-S-an-dst32-1-S-A1-direct-HI", "add.l", 8,
57880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57881   },
57882 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
57883   {
57884     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 24,
57885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57886   },
57887 /* add.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
57888   {
57889     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 24,
57890     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57891   },
57892 /* add.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
57893   {
57894     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 24,
57895     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57896   },
57897 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
57898   {
57899     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 24,
57900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57901   },
57902 /* add.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
57903   {
57904     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 24,
57905     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57906   },
57907 /* add.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
57908   {
57909     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 24,
57910     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57911   },
57912 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
57913   {
57914     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 24,
57915     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57916   },
57917 /* add.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
57918   {
57919     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 24,
57920     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57921   },
57922 /* add.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
57923   {
57924     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 24,
57925     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57926   },
57927 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
57928   {
57929     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "add.l", 32,
57930     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57931   },
57932 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
57933   {
57934     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "add.l", 32,
57935     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57936   },
57937 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
57938   {
57939     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "add.l", 32,
57940     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57941   },
57942 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
57943   {
57944     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "add.l", 40,
57945     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57946   },
57947 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
57948   {
57949     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "add.l", 40,
57950     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57951   },
57952 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
57953   {
57954     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "add.l", 40,
57955     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57956   },
57957 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
57958   {
57959     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "add.l", 48,
57960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57961   },
57962 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
57963   {
57964     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "add.l", 48,
57965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57966   },
57967 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
57968   {
57969     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "add.l", 48,
57970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57971   },
57972 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
57973   {
57974     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "add.l", 32,
57975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57976   },
57977 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
57978   {
57979     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "add.l", 32,
57980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57981   },
57982 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
57983   {
57984     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "add.l", 32,
57985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57986   },
57987 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
57988   {
57989     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "add.l", 40,
57990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57991   },
57992 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
57993   {
57994     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "add.l", 40,
57995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57996   },
57997 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
57998   {
57999     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "add.l", 40,
58000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58001   },
58002 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
58003   {
58004     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "add.l", 32,
58005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58006   },
58007 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
58008   {
58009     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "add.l", 32,
58010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58011   },
58012 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
58013   {
58014     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "add.l", 32,
58015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58016   },
58017 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
58018   {
58019     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "add.l", 40,
58020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58021   },
58022 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
58023   {
58024     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "add.l", 40,
58025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58026   },
58027 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
58028   {
58029     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "add.l", 40,
58030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58031   },
58032 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
58033   {
58034     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "add.l", 40,
58035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58036   },
58037 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
58038   {
58039     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "add.l", 40,
58040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58041   },
58042 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
58043   {
58044     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "add.l", 40,
58045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58046   },
58047 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
58048   {
58049     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "add.l", 48,
58050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58051   },
58052 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
58053   {
58054     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "add.l", 48,
58055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58056   },
58057 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
58058   {
58059     M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "add.l", 48,
58060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58061   },
58062 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
58063   {
58064     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 32,
58065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58066   },
58067 /* add.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
58068   {
58069     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 32,
58070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58071   },
58072 /* add.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
58073   {
58074     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 32,
58075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58076   },
58077 /* add.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
58078   {
58079     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 32,
58080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58081   },
58082 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
58083   {
58084     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 32,
58085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58086   },
58087 /* add.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
58088   {
58089     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 32,
58090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58091   },
58092 /* add.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
58093   {
58094     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 32,
58095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58096   },
58097 /* add.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
58098   {
58099     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 32,
58100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58101   },
58102 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
58103   {
58104     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 32,
58105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58106   },
58107 /* add.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
58108   {
58109     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 32,
58110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58111   },
58112 /* add.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
58113   {
58114     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 32,
58115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58116   },
58117 /* add.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
58118   {
58119     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 32,
58120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58121   },
58122 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
58123   {
58124     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "add.l", 40,
58125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58126   },
58127 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
58128   {
58129     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "add.l", 40,
58130     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58131   },
58132 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
58133   {
58134     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "add.l", 40,
58135     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58136   },
58137 /* add.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
58138   {
58139     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "add.l", 40,
58140     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58141   },
58142 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
58143   {
58144     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "add.l", 48,
58145     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58146   },
58147 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
58148   {
58149     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "add.l", 48,
58150     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58151   },
58152 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
58153   {
58154     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "add.l", 48,
58155     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58156   },
58157 /* add.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
58158   {
58159     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "add.l", 48,
58160     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58161   },
58162 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
58163   {
58164     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "add.l", 56,
58165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58166   },
58167 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
58168   {
58169     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "add.l", 56,
58170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58171   },
58172 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
58173   {
58174     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "add.l", 56,
58175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58176   },
58177 /* add.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
58178   {
58179     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "add.l", 56,
58180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58181   },
58182 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
58183   {
58184     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "add.l", 40,
58185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58186   },
58187 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
58188   {
58189     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "add.l", 40,
58190     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58191   },
58192 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
58193   {
58194     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "add.l", 40,
58195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58196   },
58197 /* add.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
58198   {
58199     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "add.l", 40,
58200     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58201   },
58202 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
58203   {
58204     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "add.l", 48,
58205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58206   },
58207 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
58208   {
58209     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "add.l", 48,
58210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58211   },
58212 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
58213   {
58214     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "add.l", 48,
58215     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58216   },
58217 /* add.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
58218   {
58219     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "add.l", 48,
58220     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58221   },
58222 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
58223   {
58224     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "add.l", 40,
58225     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58226   },
58227 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
58228   {
58229     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "add.l", 40,
58230     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58231   },
58232 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
58233   {
58234     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "add.l", 40,
58235     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58236   },
58237 /* add.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
58238   {
58239     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "add.l", 40,
58240     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58241   },
58242 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
58243   {
58244     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "add.l", 48,
58245     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58246   },
58247 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
58248   {
58249     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "add.l", 48,
58250     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58251   },
58252 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
58253   {
58254     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "add.l", 48,
58255     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58256   },
58257 /* add.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
58258   {
58259     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "add.l", 48,
58260     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58261   },
58262 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
58263   {
58264     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "add.l", 48,
58265     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58266   },
58267 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
58268   {
58269     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "add.l", 48,
58270     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58271   },
58272 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
58273   {
58274     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "add.l", 48,
58275     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58276   },
58277 /* add.l${G} ${Dsp-16-u16},${Dsp-32-u16} */
58278   {
58279     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "add.l", 48,
58280     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58281   },
58282 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
58283   {
58284     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "add.l", 56,
58285     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58286   },
58287 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
58288   {
58289     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "add.l", 56,
58290     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58291   },
58292 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
58293   {
58294     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "add.l", 56,
58295     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58296   },
58297 /* add.l${G} ${Dsp-16-u16},${Dsp-32-u24} */
58298   {
58299     M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "add.l", 56,
58300     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58301   },
58302 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
58303   {
58304     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 40,
58305     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58306   },
58307 /* add.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
58308   {
58309     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 40,
58310     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58311   },
58312 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
58313   {
58314     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 40,
58315     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58316   },
58317 /* add.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
58318   {
58319     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 40,
58320     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58321   },
58322 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
58323   {
58324     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 40,
58325     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58326   },
58327 /* add.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
58328   {
58329     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 40,
58330     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58331   },
58332 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
58333   {
58334     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "add.l", 48,
58335     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58336   },
58337 /* add.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
58338   {
58339     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "add.l", 48,
58340     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58341   },
58342 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
58343   {
58344     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "add.l", 56,
58345     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58346   },
58347 /* add.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
58348   {
58349     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "add.l", 56,
58350     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58351   },
58352 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
58353   {
58354     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "add.l", 64,
58355     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58356   },
58357 /* add.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
58358   {
58359     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "add.l", 64,
58360     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58361   },
58362 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
58363   {
58364     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "add.l", 48,
58365     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58366   },
58367 /* add.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
58368   {
58369     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "add.l", 48,
58370     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58371   },
58372 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
58373   {
58374     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "add.l", 56,
58375     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58376   },
58377 /* add.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
58378   {
58379     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "add.l", 56,
58380     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58381   },
58382 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
58383   {
58384     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "add.l", 48,
58385     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58386   },
58387 /* add.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
58388   {
58389     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "add.l", 48,
58390     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58391   },
58392 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
58393   {
58394     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "add.l", 56,
58395     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58396   },
58397 /* add.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
58398   {
58399     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "add.l", 56,
58400     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58401   },
58402 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
58403   {
58404     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "add.l", 56,
58405     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58406   },
58407 /* add.l${G} ${Dsp-16-u24},${Dsp-40-u16} */
58408   {
58409     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "add.l", 56,
58410     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58411   },
58412 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
58413   {
58414     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "add.l", 64,
58415     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58416   },
58417 /* add.l${G} ${Dsp-16-u24},${Dsp-40-u24} */
58418   {
58419     M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "add.l", 64,
58420     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58421   },
58422 /* add.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */
58423   {
58424     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 16,
58425     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58426   },
58427 /* add.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */
58428   {
58429     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 16,
58430     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58431   },
58432 /* add.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
58433   {
58434     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 16,
58435     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58436   },
58437 /* add.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */
58438   {
58439     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 16,
58440     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58441   },
58442 /* add.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */
58443   {
58444     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 16,
58445     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58446   },
58447 /* add.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
58448   {
58449     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 16,
58450     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58451   },
58452 /* add.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */
58453   {
58454     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 16,
58455     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58456   },
58457 /* add.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */
58458   {
58459     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 16,
58460     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58461   },
58462 /* add.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
58463   {
58464     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 16,
58465     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58466   },
58467 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
58468   {
58469     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "add.l", 24,
58470     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58471   },
58472 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
58473   {
58474     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "add.l", 24,
58475     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58476   },
58477 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
58478   {
58479     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "add.l", 24,
58480     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58481   },
58482 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
58483   {
58484     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "add.l", 32,
58485     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58486   },
58487 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
58488   {
58489     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "add.l", 32,
58490     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58491   },
58492 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
58493   {
58494     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "add.l", 32,
58495     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58496   },
58497 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
58498   {
58499     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "add.l", 40,
58500     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58501   },
58502 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
58503   {
58504     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "add.l", 40,
58505     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58506   },
58507 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
58508   {
58509     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "add.l", 40,
58510     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58511   },
58512 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */
58513   {
58514     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "add.l", 24,
58515     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58516   },
58517 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */
58518   {
58519     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "add.l", 24,
58520     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58521   },
58522 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
58523   {
58524     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "add.l", 24,
58525     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58526   },
58527 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */
58528   {
58529     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "add.l", 32,
58530     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58531   },
58532 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */
58533   {
58534     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "add.l", 32,
58535     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58536   },
58537 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
58538   {
58539     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "add.l", 32,
58540     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58541   },
58542 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */
58543   {
58544     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "add.l", 24,
58545     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58546   },
58547 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */
58548   {
58549     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "add.l", 24,
58550     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58551   },
58552 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
58553   {
58554     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "add.l", 24,
58555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58556   },
58557 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */
58558   {
58559     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "add.l", 32,
58560     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58561   },
58562 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */
58563   {
58564     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "add.l", 32,
58565     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58566   },
58567 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
58568   {
58569     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "add.l", 32,
58570     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58571   },
58572 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */
58573   {
58574     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "add.l", 32,
58575     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58576   },
58577 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */
58578   {
58579     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "add.l", 32,
58580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58581   },
58582 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
58583   {
58584     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "add.l", 32,
58585     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58586   },
58587 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */
58588   {
58589     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "add.l", 40,
58590     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58591   },
58592 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */
58593   {
58594     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "add.l", 40,
58595     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58596   },
58597 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
58598   {
58599     M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "add.l", 40,
58600     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58601   },
58602 /* add.b${S} ${SrcDst16-r0l-r0h-S-normal} */
58603   {
58604     M32C_INSN_ADD16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, "add16.b.S-r0l-r0h-srcdst16-r0l-r0h-S-derived", "add.b", 8,
58605     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
58606   },
58607 /* add.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
58608   {
58609     M32C_INSN_ADD16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, "add16.b.S-src2-src16-2-S-8-SB-relative-QI", "add.b", 16,
58610     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
58611   },
58612 /* add.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
58613   {
58614     M32C_INSN_ADD16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, "add16.b.S-src2-src16-2-S-8-FB-relative-QI", "add.b", 16,
58615     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
58616   },
58617 /* add.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
58618   {
58619     M32C_INSN_ADD16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, "add16.b.S-src2-src16-2-S-16-absolute-QI", "add.b", 24,
58620     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
58621   },
58622 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
58623   {
58624     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 24,
58625     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58626   },
58627 /* add.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
58628   {
58629     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 24,
58630     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58631   },
58632 /* add.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
58633   {
58634     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 24,
58635     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58636   },
58637 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
58638   {
58639     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 24,
58640     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58641   },
58642 /* add.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
58643   {
58644     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 24,
58645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58646   },
58647 /* add.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
58648   {
58649     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 24,
58650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58651   },
58652 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
58653   {
58654     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 24,
58655     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58656   },
58657 /* add.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
58658   {
58659     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 24,
58660     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58661   },
58662 /* add.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
58663   {
58664     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 24,
58665     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58666   },
58667 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
58668   {
58669     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "add.w", 32,
58670     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58671   },
58672 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
58673   {
58674     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "add.w", 32,
58675     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58676   },
58677 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
58678   {
58679     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "add.w", 32,
58680     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58681   },
58682 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
58683   {
58684     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "add.w", 40,
58685     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58686   },
58687 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
58688   {
58689     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "add.w", 40,
58690     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58691   },
58692 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
58693   {
58694     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "add.w", 40,
58695     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58696   },
58697 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
58698   {
58699     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "add.w", 48,
58700     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58701   },
58702 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
58703   {
58704     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "add.w", 48,
58705     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58706   },
58707 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
58708   {
58709     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "add.w", 48,
58710     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58711   },
58712 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
58713   {
58714     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "add.w", 32,
58715     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58716   },
58717 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
58718   {
58719     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "add.w", 32,
58720     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58721   },
58722 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
58723   {
58724     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "add.w", 32,
58725     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58726   },
58727 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
58728   {
58729     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "add.w", 40,
58730     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58731   },
58732 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
58733   {
58734     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "add.w", 40,
58735     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58736   },
58737 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
58738   {
58739     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "add.w", 40,
58740     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58741   },
58742 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
58743   {
58744     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "add.w", 32,
58745     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58746   },
58747 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
58748   {
58749     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "add.w", 32,
58750     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58751   },
58752 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
58753   {
58754     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "add.w", 32,
58755     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58756   },
58757 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
58758   {
58759     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "add.w", 40,
58760     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58761   },
58762 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
58763   {
58764     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "add.w", 40,
58765     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58766   },
58767 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
58768   {
58769     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "add.w", 40,
58770     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58771   },
58772 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
58773   {
58774     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "add.w", 40,
58775     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58776   },
58777 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
58778   {
58779     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "add.w", 40,
58780     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58781   },
58782 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
58783   {
58784     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "add.w", 40,
58785     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58786   },
58787 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
58788   {
58789     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "add.w", 48,
58790     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58791   },
58792 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
58793   {
58794     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "add.w", 48,
58795     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58796   },
58797 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
58798   {
58799     M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "add.w", 48,
58800     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58801   },
58802 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
58803   {
58804     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 32,
58805     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58806   },
58807 /* add.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
58808   {
58809     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 32,
58810     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58811   },
58812 /* add.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
58813   {
58814     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 32,
58815     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58816   },
58817 /* add.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
58818   {
58819     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 32,
58820     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58821   },
58822 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
58823   {
58824     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 32,
58825     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58826   },
58827 /* add.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
58828   {
58829     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 32,
58830     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58831   },
58832 /* add.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
58833   {
58834     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 32,
58835     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58836   },
58837 /* add.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
58838   {
58839     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 32,
58840     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58841   },
58842 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
58843   {
58844     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 32,
58845     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58846   },
58847 /* add.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
58848   {
58849     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 32,
58850     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58851   },
58852 /* add.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
58853   {
58854     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 32,
58855     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58856   },
58857 /* add.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
58858   {
58859     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 32,
58860     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58861   },
58862 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
58863   {
58864     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "add.w", 40,
58865     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58866   },
58867 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
58868   {
58869     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "add.w", 40,
58870     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58871   },
58872 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
58873   {
58874     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "add.w", 40,
58875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58876   },
58877 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
58878   {
58879     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "add.w", 40,
58880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58881   },
58882 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
58883   {
58884     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "add.w", 48,
58885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58886   },
58887 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
58888   {
58889     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "add.w", 48,
58890     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58891   },
58892 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
58893   {
58894     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "add.w", 48,
58895     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58896   },
58897 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
58898   {
58899     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "add.w", 48,
58900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58901   },
58902 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
58903   {
58904     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "add.w", 56,
58905     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58906   },
58907 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
58908   {
58909     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "add.w", 56,
58910     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58911   },
58912 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
58913   {
58914     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "add.w", 56,
58915     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58916   },
58917 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
58918   {
58919     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "add.w", 56,
58920     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58921   },
58922 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
58923   {
58924     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "add.w", 40,
58925     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58926   },
58927 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
58928   {
58929     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "add.w", 40,
58930     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58931   },
58932 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
58933   {
58934     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "add.w", 40,
58935     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58936   },
58937 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
58938   {
58939     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "add.w", 40,
58940     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58941   },
58942 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
58943   {
58944     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "add.w", 48,
58945     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58946   },
58947 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
58948   {
58949     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "add.w", 48,
58950     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58951   },
58952 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
58953   {
58954     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "add.w", 48,
58955     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58956   },
58957 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
58958   {
58959     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "add.w", 48,
58960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58961   },
58962 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
58963   {
58964     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "add.w", 40,
58965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58966   },
58967 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
58968   {
58969     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "add.w", 40,
58970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58971   },
58972 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
58973   {
58974     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "add.w", 40,
58975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58976   },
58977 /* add.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
58978   {
58979     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "add.w", 40,
58980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58981   },
58982 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
58983   {
58984     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "add.w", 48,
58985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58986   },
58987 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
58988   {
58989     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "add.w", 48,
58990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58991   },
58992 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
58993   {
58994     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "add.w", 48,
58995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58996   },
58997 /* add.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
58998   {
58999     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "add.w", 48,
59000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59001   },
59002 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
59003   {
59004     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "add.w", 48,
59005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59006   },
59007 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
59008   {
59009     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "add.w", 48,
59010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59011   },
59012 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
59013   {
59014     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "add.w", 48,
59015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59016   },
59017 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
59018   {
59019     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "add.w", 48,
59020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59021   },
59022 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
59023   {
59024     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "add.w", 56,
59025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59026   },
59027 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
59028   {
59029     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "add.w", 56,
59030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59031   },
59032 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
59033   {
59034     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "add.w", 56,
59035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59036   },
59037 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
59038   {
59039     M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "add.w", 56,
59040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59041   },
59042 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
59043   {
59044     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 40,
59045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59046   },
59047 /* add.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
59048   {
59049     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 40,
59050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59051   },
59052 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
59053   {
59054     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 40,
59055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59056   },
59057 /* add.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
59058   {
59059     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 40,
59060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59061   },
59062 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
59063   {
59064     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 40,
59065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59066   },
59067 /* add.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
59068   {
59069     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 40,
59070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59071   },
59072 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
59073   {
59074     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "add.w", 48,
59075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59076   },
59077 /* add.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
59078   {
59079     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "add.w", 48,
59080     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59081   },
59082 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
59083   {
59084     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "add.w", 56,
59085     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59086   },
59087 /* add.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
59088   {
59089     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "add.w", 56,
59090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59091   },
59092 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
59093   {
59094     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "add.w", 64,
59095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59096   },
59097 /* add.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
59098   {
59099     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "add.w", 64,
59100     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59101   },
59102 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
59103   {
59104     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "add.w", 48,
59105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59106   },
59107 /* add.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
59108   {
59109     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "add.w", 48,
59110     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59111   },
59112 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
59113   {
59114     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "add.w", 56,
59115     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59116   },
59117 /* add.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
59118   {
59119     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "add.w", 56,
59120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59121   },
59122 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
59123   {
59124     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "add.w", 48,
59125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59126   },
59127 /* add.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
59128   {
59129     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "add.w", 48,
59130     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59131   },
59132 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
59133   {
59134     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "add.w", 56,
59135     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59136   },
59137 /* add.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
59138   {
59139     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "add.w", 56,
59140     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59141   },
59142 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
59143   {
59144     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "add.w", 56,
59145     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59146   },
59147 /* add.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
59148   {
59149     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "add.w", 56,
59150     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59151   },
59152 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
59153   {
59154     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "add.w", 64,
59155     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59156   },
59157 /* add.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
59158   {
59159     M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "add.w", 64,
59160     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59161   },
59162 /* add.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
59163   {
59164     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 16,
59165     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59166   },
59167 /* add.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
59168   {
59169     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 16,
59170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59171   },
59172 /* add.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
59173   {
59174     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 16,
59175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59176   },
59177 /* add.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
59178   {
59179     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 16,
59180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59181   },
59182 /* add.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
59183   {
59184     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 16,
59185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59186   },
59187 /* add.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
59188   {
59189     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 16,
59190     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59191   },
59192 /* add.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
59193   {
59194     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 16,
59195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59196   },
59197 /* add.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
59198   {
59199     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 16,
59200     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59201   },
59202 /* add.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
59203   {
59204     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 16,
59205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59206   },
59207 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
59208   {
59209     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "add.w", 24,
59210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59211   },
59212 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
59213   {
59214     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "add.w", 24,
59215     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59216   },
59217 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
59218   {
59219     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "add.w", 24,
59220     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59221   },
59222 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
59223   {
59224     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "add.w", 32,
59225     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59226   },
59227 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
59228   {
59229     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "add.w", 32,
59230     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59231   },
59232 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
59233   {
59234     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "add.w", 32,
59235     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59236   },
59237 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
59238   {
59239     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "add.w", 40,
59240     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59241   },
59242 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
59243   {
59244     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "add.w", 40,
59245     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59246   },
59247 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
59248   {
59249     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "add.w", 40,
59250     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59251   },
59252 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
59253   {
59254     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "add.w", 24,
59255     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59256   },
59257 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
59258   {
59259     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "add.w", 24,
59260     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59261   },
59262 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
59263   {
59264     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "add.w", 24,
59265     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59266   },
59267 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
59268   {
59269     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "add.w", 32,
59270     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59271   },
59272 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
59273   {
59274     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "add.w", 32,
59275     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59276   },
59277 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
59278   {
59279     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "add.w", 32,
59280     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59281   },
59282 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
59283   {
59284     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "add.w", 24,
59285     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59286   },
59287 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
59288   {
59289     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "add.w", 24,
59290     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59291   },
59292 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
59293   {
59294     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "add.w", 24,
59295     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59296   },
59297 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
59298   {
59299     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "add.w", 32,
59300     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59301   },
59302 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
59303   {
59304     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "add.w", 32,
59305     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59306   },
59307 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
59308   {
59309     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "add.w", 32,
59310     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59311   },
59312 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
59313   {
59314     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "add.w", 32,
59315     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59316   },
59317 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
59318   {
59319     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "add.w", 32,
59320     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59321   },
59322 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
59323   {
59324     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "add.w", 32,
59325     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59326   },
59327 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
59328   {
59329     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "add.w", 40,
59330     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59331   },
59332 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
59333   {
59334     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "add.w", 40,
59335     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59336   },
59337 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
59338   {
59339     M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "add.w", 40,
59340     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59341   },
59342 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
59343   {
59344     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 24,
59345     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59346   },
59347 /* add.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
59348   {
59349     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 24,
59350     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59351   },
59352 /* add.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
59353   {
59354     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 24,
59355     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59356   },
59357 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
59358   {
59359     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 24,
59360     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59361   },
59362 /* add.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
59363   {
59364     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 24,
59365     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59366   },
59367 /* add.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
59368   {
59369     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 24,
59370     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59371   },
59372 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
59373   {
59374     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 24,
59375     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59376   },
59377 /* add.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
59378   {
59379     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 24,
59380     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59381   },
59382 /* add.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
59383   {
59384     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 24,
59385     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59386   },
59387 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
59388   {
59389     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "add.b", 32,
59390     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59391   },
59392 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
59393   {
59394     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "add.b", 32,
59395     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59396   },
59397 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
59398   {
59399     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "add.b", 32,
59400     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59401   },
59402 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
59403   {
59404     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "add.b", 40,
59405     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59406   },
59407 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
59408   {
59409     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "add.b", 40,
59410     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59411   },
59412 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
59413   {
59414     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "add.b", 40,
59415     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59416   },
59417 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
59418   {
59419     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "add.b", 48,
59420     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59421   },
59422 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
59423   {
59424     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "add.b", 48,
59425     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59426   },
59427 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
59428   {
59429     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "add.b", 48,
59430     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59431   },
59432 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
59433   {
59434     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "add.b", 32,
59435     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59436   },
59437 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
59438   {
59439     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "add.b", 32,
59440     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59441   },
59442 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
59443   {
59444     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "add.b", 32,
59445     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59446   },
59447 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
59448   {
59449     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "add.b", 40,
59450     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59451   },
59452 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
59453   {
59454     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "add.b", 40,
59455     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59456   },
59457 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
59458   {
59459     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "add.b", 40,
59460     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59461   },
59462 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
59463   {
59464     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "add.b", 32,
59465     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59466   },
59467 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
59468   {
59469     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "add.b", 32,
59470     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59471   },
59472 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
59473   {
59474     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "add.b", 32,
59475     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59476   },
59477 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
59478   {
59479     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "add.b", 40,
59480     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59481   },
59482 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
59483   {
59484     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "add.b", 40,
59485     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59486   },
59487 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
59488   {
59489     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "add.b", 40,
59490     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59491   },
59492 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
59493   {
59494     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "add.b", 40,
59495     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59496   },
59497 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
59498   {
59499     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "add.b", 40,
59500     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59501   },
59502 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
59503   {
59504     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "add.b", 40,
59505     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59506   },
59507 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
59508   {
59509     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "add.b", 48,
59510     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59511   },
59512 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
59513   {
59514     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "add.b", 48,
59515     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59516   },
59517 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
59518   {
59519     M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "add.b", 48,
59520     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59521   },
59522 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
59523   {
59524     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 32,
59525     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59526   },
59527 /* add.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
59528   {
59529     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 32,
59530     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59531   },
59532 /* add.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
59533   {
59534     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 32,
59535     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59536   },
59537 /* add.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
59538   {
59539     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 32,
59540     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59541   },
59542 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
59543   {
59544     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 32,
59545     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59546   },
59547 /* add.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
59548   {
59549     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 32,
59550     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59551   },
59552 /* add.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
59553   {
59554     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 32,
59555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59556   },
59557 /* add.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
59558   {
59559     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 32,
59560     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59561   },
59562 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
59563   {
59564     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 32,
59565     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59566   },
59567 /* add.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
59568   {
59569     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 32,
59570     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59571   },
59572 /* add.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
59573   {
59574     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 32,
59575     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59576   },
59577 /* add.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
59578   {
59579     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 32,
59580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59581   },
59582 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
59583   {
59584     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "add.b", 40,
59585     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59586   },
59587 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
59588   {
59589     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "add.b", 40,
59590     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59591   },
59592 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
59593   {
59594     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "add.b", 40,
59595     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59596   },
59597 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
59598   {
59599     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "add.b", 40,
59600     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59601   },
59602 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
59603   {
59604     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "add.b", 48,
59605     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59606   },
59607 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
59608   {
59609     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "add.b", 48,
59610     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59611   },
59612 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
59613   {
59614     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "add.b", 48,
59615     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59616   },
59617 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
59618   {
59619     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "add.b", 48,
59620     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59621   },
59622 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
59623   {
59624     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "add.b", 56,
59625     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59626   },
59627 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
59628   {
59629     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "add.b", 56,
59630     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59631   },
59632 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
59633   {
59634     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "add.b", 56,
59635     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59636   },
59637 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
59638   {
59639     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "add.b", 56,
59640     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59641   },
59642 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
59643   {
59644     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "add.b", 40,
59645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59646   },
59647 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
59648   {
59649     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "add.b", 40,
59650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59651   },
59652 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
59653   {
59654     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "add.b", 40,
59655     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59656   },
59657 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
59658   {
59659     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "add.b", 40,
59660     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59661   },
59662 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
59663   {
59664     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "add.b", 48,
59665     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59666   },
59667 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
59668   {
59669     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "add.b", 48,
59670     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59671   },
59672 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
59673   {
59674     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "add.b", 48,
59675     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59676   },
59677 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
59678   {
59679     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "add.b", 48,
59680     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59681   },
59682 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
59683   {
59684     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "add.b", 40,
59685     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59686   },
59687 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
59688   {
59689     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "add.b", 40,
59690     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59691   },
59692 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
59693   {
59694     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "add.b", 40,
59695     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59696   },
59697 /* add.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
59698   {
59699     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "add.b", 40,
59700     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59701   },
59702 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
59703   {
59704     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "add.b", 48,
59705     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59706   },
59707 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
59708   {
59709     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "add.b", 48,
59710     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59711   },
59712 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
59713   {
59714     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "add.b", 48,
59715     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59716   },
59717 /* add.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
59718   {
59719     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "add.b", 48,
59720     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59721   },
59722 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
59723   {
59724     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "add.b", 48,
59725     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59726   },
59727 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
59728   {
59729     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "add.b", 48,
59730     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59731   },
59732 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
59733   {
59734     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "add.b", 48,
59735     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59736   },
59737 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
59738   {
59739     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "add.b", 48,
59740     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59741   },
59742 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
59743   {
59744     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "add.b", 56,
59745     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59746   },
59747 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
59748   {
59749     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "add.b", 56,
59750     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59751   },
59752 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
59753   {
59754     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "add.b", 56,
59755     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59756   },
59757 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
59758   {
59759     M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "add.b", 56,
59760     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59761   },
59762 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
59763   {
59764     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 40,
59765     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59766   },
59767 /* add.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
59768   {
59769     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 40,
59770     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59771   },
59772 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
59773   {
59774     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 40,
59775     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59776   },
59777 /* add.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
59778   {
59779     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 40,
59780     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59781   },
59782 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
59783   {
59784     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 40,
59785     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59786   },
59787 /* add.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
59788   {
59789     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 40,
59790     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59791   },
59792 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
59793   {
59794     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "add.b", 48,
59795     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59796   },
59797 /* add.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
59798   {
59799     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "add.b", 48,
59800     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59801   },
59802 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
59803   {
59804     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "add.b", 56,
59805     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59806   },
59807 /* add.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
59808   {
59809     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "add.b", 56,
59810     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59811   },
59812 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
59813   {
59814     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "add.b", 64,
59815     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59816   },
59817 /* add.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
59818   {
59819     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "add.b", 64,
59820     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59821   },
59822 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
59823   {
59824     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "add.b", 48,
59825     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59826   },
59827 /* add.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
59828   {
59829     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "add.b", 48,
59830     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59831   },
59832 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
59833   {
59834     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "add.b", 56,
59835     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59836   },
59837 /* add.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
59838   {
59839     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "add.b", 56,
59840     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59841   },
59842 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
59843   {
59844     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "add.b", 48,
59845     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59846   },
59847 /* add.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
59848   {
59849     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "add.b", 48,
59850     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59851   },
59852 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
59853   {
59854     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "add.b", 56,
59855     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59856   },
59857 /* add.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
59858   {
59859     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "add.b", 56,
59860     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59861   },
59862 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
59863   {
59864     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "add.b", 56,
59865     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59866   },
59867 /* add.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
59868   {
59869     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "add.b", 56,
59870     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59871   },
59872 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
59873   {
59874     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "add.b", 64,
59875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59876   },
59877 /* add.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
59878   {
59879     M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "add.b", 64,
59880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59881   },
59882 /* add.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
59883   {
59884     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 16,
59885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59886   },
59887 /* add.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
59888   {
59889     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 16,
59890     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59891   },
59892 /* add.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
59893   {
59894     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 16,
59895     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59896   },
59897 /* add.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
59898   {
59899     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 16,
59900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59901   },
59902 /* add.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
59903   {
59904     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 16,
59905     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59906   },
59907 /* add.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
59908   {
59909     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 16,
59910     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59911   },
59912 /* add.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
59913   {
59914     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 16,
59915     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59916   },
59917 /* add.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
59918   {
59919     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 16,
59920     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59921   },
59922 /* add.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
59923   {
59924     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 16,
59925     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59926   },
59927 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
59928   {
59929     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "add.b", 24,
59930     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59931   },
59932 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
59933   {
59934     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "add.b", 24,
59935     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59936   },
59937 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
59938   {
59939     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "add.b", 24,
59940     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59941   },
59942 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
59943   {
59944     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "add.b", 32,
59945     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59946   },
59947 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
59948   {
59949     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "add.b", 32,
59950     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59951   },
59952 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
59953   {
59954     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "add.b", 32,
59955     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59956   },
59957 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
59958   {
59959     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "add.b", 40,
59960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59961   },
59962 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
59963   {
59964     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "add.b", 40,
59965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59966   },
59967 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
59968   {
59969     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "add.b", 40,
59970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59971   },
59972 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
59973   {
59974     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "add.b", 24,
59975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59976   },
59977 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
59978   {
59979     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "add.b", 24,
59980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59981   },
59982 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
59983   {
59984     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "add.b", 24,
59985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59986   },
59987 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
59988   {
59989     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "add.b", 32,
59990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59991   },
59992 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
59993   {
59994     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "add.b", 32,
59995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59996   },
59997 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
59998   {
59999     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "add.b", 32,
60000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60001   },
60002 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
60003   {
60004     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "add.b", 24,
60005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60006   },
60007 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
60008   {
60009     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "add.b", 24,
60010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60011   },
60012 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
60013   {
60014     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "add.b", 24,
60015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60016   },
60017 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
60018   {
60019     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "add.b", 32,
60020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60021   },
60022 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
60023   {
60024     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "add.b", 32,
60025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60026   },
60027 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
60028   {
60029     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "add.b", 32,
60030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60031   },
60032 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
60033   {
60034     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "add.b", 32,
60035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60036   },
60037 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
60038   {
60039     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "add.b", 32,
60040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60041   },
60042 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
60043   {
60044     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "add.b", 32,
60045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60046   },
60047 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
60048   {
60049     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "add.b", 40,
60050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60051   },
60052 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
60053   {
60054     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "add.b", 40,
60055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60056   },
60057 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
60058   {
60059     M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "add.b", 40,
60060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60061   },
60062 /* add.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
60063   {
60064     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "add.w", 24,
60065     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60066   },
60067 /* add.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
60068   {
60069     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "add.w", 24,
60070     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60071   },
60072 /* add.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
60073   {
60074     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "add.w", 24,
60075     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60076   },
60077 /* add.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
60078   {
60079     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "add.w", 24,
60080     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60081   },
60082 /* add.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
60083   {
60084     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "add.w", 24,
60085     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60086   },
60087 /* add.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
60088   {
60089     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "add.w", 24,
60090     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60091   },
60092 /* add.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
60093   {
60094     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "add.w", 24,
60095     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60096   },
60097 /* add.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
60098   {
60099     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "add.w", 24,
60100     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60101   },
60102 /* add.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
60103   {
60104     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "add.w", 24,
60105     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60106   },
60107 /* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
60108   {
60109     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "add.w", 32,
60110     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60111   },
60112 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
60113   {
60114     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "add.w", 32,
60115     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60116   },
60117 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
60118   {
60119     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "add.w", 32,
60120     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60121   },
60122 /* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
60123   {
60124     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "add.w", 40,
60125     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60126   },
60127 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
60128   {
60129     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "add.w", 40,
60130     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60131   },
60132 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
60133   {
60134     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "add.w", 40,
60135     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60136   },
60137 /* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
60138   {
60139     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "add.w", 32,
60140     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60141   },
60142 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
60143   {
60144     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "add.w", 32,
60145     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60146   },
60147 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
60148   {
60149     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "add.w", 32,
60150     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60151   },
60152 /* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
60153   {
60154     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "add.w", 40,
60155     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60156   },
60157 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
60158   {
60159     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "add.w", 40,
60160     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60161   },
60162 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
60163   {
60164     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "add.w", 40,
60165     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60166   },
60167 /* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
60168   {
60169     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "add.w", 32,
60170     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60171   },
60172 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
60173   {
60174     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "add.w", 32,
60175     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60176   },
60177 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
60178   {
60179     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "add.w", 32,
60180     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60181   },
60182 /* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
60183   {
60184     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "add.w", 40,
60185     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60186   },
60187 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
60188   {
60189     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "add.w", 40,
60190     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60191   },
60192 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
60193   {
60194     M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "add.w", 40,
60195     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60196   },
60197 /* add.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
60198   {
60199     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "add.w", 32,
60200     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60201   },
60202 /* add.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
60203   {
60204     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "add.w", 32,
60205     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60206   },
60207 /* add.w${G} ${Dsp-16-u16},$Dst16RnHI */
60208   {
60209     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "add.w", 32,
60210     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60211   },
60212 /* add.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
60213   {
60214     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "add.w", 32,
60215     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60216   },
60217 /* add.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
60218   {
60219     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "add.w", 32,
60220     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60221   },
60222 /* add.w${G} ${Dsp-16-u16},$Dst16AnHI */
60223   {
60224     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "add.w", 32,
60225     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60226   },
60227 /* add.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
60228   {
60229     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "add.w", 32,
60230     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60231   },
60232 /* add.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
60233   {
60234     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "add.w", 32,
60235     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60236   },
60237 /* add.w${G} ${Dsp-16-u16},[$Dst16An] */
60238   {
60239     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "add.w", 32,
60240     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60241   },
60242 /* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
60243   {
60244     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "add.w", 40,
60245     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60246   },
60247 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
60248   {
60249     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "add.w", 40,
60250     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60251   },
60252 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
60253   {
60254     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "add.w", 40,
60255     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60256   },
60257 /* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
60258   {
60259     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "add.w", 48,
60260     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60261   },
60262 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
60263   {
60264     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "add.w", 48,
60265     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60266   },
60267 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
60268   {
60269     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "add.w", 48,
60270     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60271   },
60272 /* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
60273   {
60274     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "add.w", 40,
60275     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60276   },
60277 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
60278   {
60279     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "add.w", 40,
60280     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60281   },
60282 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
60283   {
60284     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "add.w", 40,
60285     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60286   },
60287 /* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
60288   {
60289     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "add.w", 48,
60290     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60291   },
60292 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
60293   {
60294     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "add.w", 48,
60295     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60296   },
60297 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
60298   {
60299     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "add.w", 48,
60300     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60301   },
60302 /* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
60303   {
60304     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "add.w", 40,
60305     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60306   },
60307 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
60308   {
60309     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "add.w", 40,
60310     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60311   },
60312 /* add.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
60313   {
60314     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "add.w", 40,
60315     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60316   },
60317 /* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
60318   {
60319     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "add.w", 48,
60320     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60321   },
60322 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
60323   {
60324     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "add.w", 48,
60325     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60326   },
60327 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
60328   {
60329     M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "add.w", 48,
60330     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60331   },
60332 /* add.w${G} $Src16RnHI,$Dst16RnHI */
60333   {
60334     M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "add.w", 16,
60335     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60336   },
60337 /* add.w${G} $Src16AnHI,$Dst16RnHI */
60338   {
60339     M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "add.w", 16,
60340     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60341   },
60342 /* add.w${G} [$Src16An],$Dst16RnHI */
60343   {
60344     M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "add.w", 16,
60345     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60346   },
60347 /* add.w${G} $Src16RnHI,$Dst16AnHI */
60348   {
60349     M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "add.w", 16,
60350     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60351   },
60352 /* add.w${G} $Src16AnHI,$Dst16AnHI */
60353   {
60354     M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "add.w", 16,
60355     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60356   },
60357 /* add.w${G} [$Src16An],$Dst16AnHI */
60358   {
60359     M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "add.w", 16,
60360     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60361   },
60362 /* add.w${G} $Src16RnHI,[$Dst16An] */
60363   {
60364     M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "add.w", 16,
60365     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60366   },
60367 /* add.w${G} $Src16AnHI,[$Dst16An] */
60368   {
60369     M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "add.w", 16,
60370     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60371   },
60372 /* add.w${G} [$Src16An],[$Dst16An] */
60373   {
60374     M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "add.w", 16,
60375     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60376   },
60377 /* add.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
60378   {
60379     M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "add.w", 24,
60380     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60381   },
60382 /* add.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
60383   {
60384     M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "add.w", 24,
60385     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60386   },
60387 /* add.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
60388   {
60389     M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "add.w", 24,
60390     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60391   },
60392 /* add.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
60393   {
60394     M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "add.w", 32,
60395     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60396   },
60397 /* add.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
60398   {
60399     M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "add.w", 32,
60400     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60401   },
60402 /* add.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
60403   {
60404     M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "add.w", 32,
60405     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60406   },
60407 /* add.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
60408   {
60409     M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "add.w", 24,
60410     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60411   },
60412 /* add.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
60413   {
60414     M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "add.w", 24,
60415     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60416   },
60417 /* add.w${G} [$Src16An],${Dsp-16-u8}[sb] */
60418   {
60419     M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "add.w", 24,
60420     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60421   },
60422 /* add.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
60423   {
60424     M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "add.w", 32,
60425     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60426   },
60427 /* add.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
60428   {
60429     M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "add.w", 32,
60430     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60431   },
60432 /* add.w${G} [$Src16An],${Dsp-16-u16}[sb] */
60433   {
60434     M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "add.w", 32,
60435     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60436   },
60437 /* add.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
60438   {
60439     M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "add.w", 24,
60440     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60441   },
60442 /* add.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
60443   {
60444     M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "add.w", 24,
60445     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60446   },
60447 /* add.w${G} [$Src16An],${Dsp-16-s8}[fb] */
60448   {
60449     M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "add.w", 24,
60450     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60451   },
60452 /* add.w${G} $Src16RnHI,${Dsp-16-u16} */
60453   {
60454     M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "add.w", 32,
60455     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60456   },
60457 /* add.w${G} $Src16AnHI,${Dsp-16-u16} */
60458   {
60459     M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "add.w", 32,
60460     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60461   },
60462 /* add.w${G} [$Src16An],${Dsp-16-u16} */
60463   {
60464     M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "add.w", 32,
60465     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60466   },
60467 /* add.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
60468   {
60469     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "add.b", 24,
60470     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60471   },
60472 /* add.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
60473   {
60474     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "add.b", 24,
60475     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60476   },
60477 /* add.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
60478   {
60479     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "add.b", 24,
60480     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60481   },
60482 /* add.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
60483   {
60484     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "add.b", 24,
60485     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60486   },
60487 /* add.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
60488   {
60489     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "add.b", 24,
60490     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60491   },
60492 /* add.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
60493   {
60494     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "add.b", 24,
60495     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60496   },
60497 /* add.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
60498   {
60499     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "add.b", 24,
60500     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60501   },
60502 /* add.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
60503   {
60504     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "add.b", 24,
60505     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60506   },
60507 /* add.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
60508   {
60509     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "add.b", 24,
60510     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60511   },
60512 /* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
60513   {
60514     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "add.b", 32,
60515     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60516   },
60517 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
60518   {
60519     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "add.b", 32,
60520     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60521   },
60522 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
60523   {
60524     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "add.b", 32,
60525     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60526   },
60527 /* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
60528   {
60529     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "add.b", 40,
60530     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60531   },
60532 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
60533   {
60534     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "add.b", 40,
60535     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60536   },
60537 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
60538   {
60539     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "add.b", 40,
60540     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60541   },
60542 /* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
60543   {
60544     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "add.b", 32,
60545     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60546   },
60547 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
60548   {
60549     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "add.b", 32,
60550     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60551   },
60552 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
60553   {
60554     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "add.b", 32,
60555     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60556   },
60557 /* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
60558   {
60559     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "add.b", 40,
60560     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60561   },
60562 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
60563   {
60564     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "add.b", 40,
60565     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60566   },
60567 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
60568   {
60569     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "add.b", 40,
60570     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60571   },
60572 /* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
60573   {
60574     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "add.b", 32,
60575     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60576   },
60577 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
60578   {
60579     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "add.b", 32,
60580     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60581   },
60582 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
60583   {
60584     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "add.b", 32,
60585     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60586   },
60587 /* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
60588   {
60589     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "add.b", 40,
60590     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60591   },
60592 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
60593   {
60594     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "add.b", 40,
60595     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60596   },
60597 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
60598   {
60599     M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "add.b", 40,
60600     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60601   },
60602 /* add.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
60603   {
60604     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "add.b", 32,
60605     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60606   },
60607 /* add.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
60608   {
60609     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "add.b", 32,
60610     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60611   },
60612 /* add.b${G} ${Dsp-16-u16},$Dst16RnQI */
60613   {
60614     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "add.b", 32,
60615     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60616   },
60617 /* add.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
60618   {
60619     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "add.b", 32,
60620     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60621   },
60622 /* add.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
60623   {
60624     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "add.b", 32,
60625     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60626   },
60627 /* add.b${G} ${Dsp-16-u16},$Dst16AnQI */
60628   {
60629     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "add.b", 32,
60630     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60631   },
60632 /* add.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
60633   {
60634     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "add.b", 32,
60635     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60636   },
60637 /* add.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
60638   {
60639     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "add.b", 32,
60640     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60641   },
60642 /* add.b${G} ${Dsp-16-u16},[$Dst16An] */
60643   {
60644     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "add.b", 32,
60645     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60646   },
60647 /* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
60648   {
60649     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "add.b", 40,
60650     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60651   },
60652 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
60653   {
60654     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "add.b", 40,
60655     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60656   },
60657 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
60658   {
60659     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "add.b", 40,
60660     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60661   },
60662 /* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
60663   {
60664     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "add.b", 48,
60665     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60666   },
60667 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
60668   {
60669     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "add.b", 48,
60670     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60671   },
60672 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
60673   {
60674     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "add.b", 48,
60675     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60676   },
60677 /* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
60678   {
60679     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "add.b", 40,
60680     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60681   },
60682 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
60683   {
60684     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "add.b", 40,
60685     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60686   },
60687 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
60688   {
60689     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "add.b", 40,
60690     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60691   },
60692 /* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
60693   {
60694     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "add.b", 48,
60695     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60696   },
60697 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
60698   {
60699     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "add.b", 48,
60700     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60701   },
60702 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
60703   {
60704     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "add.b", 48,
60705     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60706   },
60707 /* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
60708   {
60709     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "add.b", 40,
60710     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60711   },
60712 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
60713   {
60714     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "add.b", 40,
60715     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60716   },
60717 /* add.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
60718   {
60719     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "add.b", 40,
60720     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60721   },
60722 /* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
60723   {
60724     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "add.b", 48,
60725     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60726   },
60727 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
60728   {
60729     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "add.b", 48,
60730     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60731   },
60732 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
60733   {
60734     M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "add.b", 48,
60735     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60736   },
60737 /* add.b${G} $Src16RnQI,$Dst16RnQI */
60738   {
60739     M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "add.b", 16,
60740     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60741   },
60742 /* add.b${G} $Src16AnQI,$Dst16RnQI */
60743   {
60744     M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "add.b", 16,
60745     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60746   },
60747 /* add.b${G} [$Src16An],$Dst16RnQI */
60748   {
60749     M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "add.b", 16,
60750     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60751   },
60752 /* add.b${G} $Src16RnQI,$Dst16AnQI */
60753   {
60754     M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "add.b", 16,
60755     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60756   },
60757 /* add.b${G} $Src16AnQI,$Dst16AnQI */
60758   {
60759     M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "add.b", 16,
60760     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60761   },
60762 /* add.b${G} [$Src16An],$Dst16AnQI */
60763   {
60764     M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "add.b", 16,
60765     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60766   },
60767 /* add.b${G} $Src16RnQI,[$Dst16An] */
60768   {
60769     M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "add.b", 16,
60770     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60771   },
60772 /* add.b${G} $Src16AnQI,[$Dst16An] */
60773   {
60774     M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "add.b", 16,
60775     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60776   },
60777 /* add.b${G} [$Src16An],[$Dst16An] */
60778   {
60779     M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "add.b", 16,
60780     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60781   },
60782 /* add.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
60783   {
60784     M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "add.b", 24,
60785     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60786   },
60787 /* add.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
60788   {
60789     M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "add.b", 24,
60790     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60791   },
60792 /* add.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
60793   {
60794     M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "add.b", 24,
60795     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60796   },
60797 /* add.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
60798   {
60799     M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "add.b", 32,
60800     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60801   },
60802 /* add.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
60803   {
60804     M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "add.b", 32,
60805     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60806   },
60807 /* add.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
60808   {
60809     M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "add.b", 32,
60810     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60811   },
60812 /* add.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
60813   {
60814     M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "add.b", 24,
60815     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60816   },
60817 /* add.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
60818   {
60819     M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "add.b", 24,
60820     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60821   },
60822 /* add.b${G} [$Src16An],${Dsp-16-u8}[sb] */
60823   {
60824     M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "add.b", 24,
60825     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60826   },
60827 /* add.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
60828   {
60829     M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "add.b", 32,
60830     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60831   },
60832 /* add.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
60833   {
60834     M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "add.b", 32,
60835     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60836   },
60837 /* add.b${G} [$Src16An],${Dsp-16-u16}[sb] */
60838   {
60839     M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "add.b", 32,
60840     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60841   },
60842 /* add.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
60843   {
60844     M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "add.b", 24,
60845     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60846   },
60847 /* add.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
60848   {
60849     M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "add.b", 24,
60850     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60851   },
60852 /* add.b${G} [$Src16An],${Dsp-16-s8}[fb] */
60853   {
60854     M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "add.b", 24,
60855     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60856   },
60857 /* add.b${G} $Src16RnQI,${Dsp-16-u16} */
60858   {
60859     M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "add.b", 32,
60860     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60861   },
60862 /* add.b${G} $Src16AnQI,${Dsp-16-u16} */
60863   {
60864     M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "add.b", 32,
60865     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60866   },
60867 /* add.b${G} [$Src16An],${Dsp-16-u16} */
60868   {
60869     M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "add.b", 32,
60870     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60871   },
60872 /* add.b${S} #${Imm-8-QI},r0l */
60873   {
60874     M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "add16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "add.b", 16,
60875     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60876   },
60877 /* add.b${S} #${Imm-8-QI},r0h */
60878   {
60879     M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "add16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "add.b", 16,
60880     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60881   },
60882 /* add.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
60883   {
60884     M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "add16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "add.b", 24,
60885     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60886   },
60887 /* add.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
60888   {
60889     M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "add16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "add.b", 24,
60890     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60891   },
60892 /* add.b${S} #${Imm-8-QI},${Dsp-16-u16} */
60893   {
60894     M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "add16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "add.b", 32,
60895     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60896   },
60897 /* add.l${Q} #${Imm-12-s4},$Dst32RnUnprefixedSI */
60898   {
60899     M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "add.l", 16,
60900     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60901   },
60902 /* add.l${Q} #${Imm-12-s4},$Dst32AnUnprefixedSI */
60903   {
60904     M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-SI", "add.l", 16,
60905     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60906   },
60907 /* add.l${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
60908   {
60909     M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-SI", "add.l", 16,
60910     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60911   },
60912 /* add.l${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
60913   {
60914     M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "add.l", 24,
60915     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60916   },
60917 /* add.l${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
60918   {
60919     M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "add.l", 32,
60920     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60921   },
60922 /* add.l${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
60923   {
60924     M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "add.l", 40,
60925     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60926   },
60927 /* add.l${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
60928   {
60929     M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "add.l", 24,
60930     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60931   },
60932 /* add.l${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
60933   {
60934     M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "add.l", 32,
60935     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60936   },
60937 /* add.l${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
60938   {
60939     M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "add.l", 24,
60940     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60941   },
60942 /* add.l${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
60943   {
60944     M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "add.l", 32,
60945     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60946   },
60947 /* add.l${Q} #${Imm-12-s4},${Dsp-16-u16} */
60948   {
60949     M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "add.l", 32,
60950     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60951   },
60952 /* add.l${Q} #${Imm-12-s4},${Dsp-16-u24} */
60953   {
60954     M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "add.l", 40,
60955     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60956   },
60957 /* add.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */
60958   {
60959     M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "add.w", 16,
60960     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60961   },
60962 /* add.w${Q} #${Imm-12-s4},$Dst32AnUnprefixedHI */
60963   {
60964     M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "add.w", 16,
60965     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60966   },
60967 /* add.w${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
60968   {
60969     M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "add.w", 16,
60970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60971   },
60972 /* add.w${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
60973   {
60974     M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "add.w", 24,
60975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60976   },
60977 /* add.w${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
60978   {
60979     M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "add.w", 32,
60980     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60981   },
60982 /* add.w${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
60983   {
60984     M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "add.w", 40,
60985     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60986   },
60987 /* add.w${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
60988   {
60989     M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "add.w", 24,
60990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60991   },
60992 /* add.w${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
60993   {
60994     M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "add.w", 32,
60995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60996   },
60997 /* add.w${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
60998   {
60999     M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "add.w", 24,
61000     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61001   },
61002 /* add.w${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
61003   {
61004     M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "add.w", 32,
61005     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61006   },
61007 /* add.w${Q} #${Imm-12-s4},${Dsp-16-u16} */
61008   {
61009     M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "add.w", 32,
61010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61011   },
61012 /* add.w${Q} #${Imm-12-s4},${Dsp-16-u24} */
61013   {
61014     M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "add.w", 40,
61015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61016   },
61017 /* add.b${Q} #${Imm-12-s4},$Dst32RnUnprefixedQI */
61018   {
61019     M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "add.b", 16,
61020     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61021   },
61022 /* add.b${Q} #${Imm-12-s4},$Dst32AnUnprefixedQI */
61023   {
61024     M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "add.b", 16,
61025     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61026   },
61027 /* add.b${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
61028   {
61029     M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "add.b", 16,
61030     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61031   },
61032 /* add.b${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
61033   {
61034     M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "add.b", 24,
61035     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61036   },
61037 /* add.b${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
61038   {
61039     M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "add.b", 32,
61040     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61041   },
61042 /* add.b${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
61043   {
61044     M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "add.b", 40,
61045     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61046   },
61047 /* add.b${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
61048   {
61049     M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "add.b", 24,
61050     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61051   },
61052 /* add.b${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
61053   {
61054     M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "add.b", 32,
61055     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61056   },
61057 /* add.b${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
61058   {
61059     M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "add.b", 24,
61060     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61061   },
61062 /* add.b${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
61063   {
61064     M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "add.b", 32,
61065     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61066   },
61067 /* add.b${Q} #${Imm-12-s4},${Dsp-16-u16} */
61068   {
61069     M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "add.b", 32,
61070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61071   },
61072 /* add.b${Q} #${Imm-12-s4},${Dsp-16-u24} */
61073   {
61074     M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "add.b", 40,
61075     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61076   },
61077 /* add.w${Q} #${Imm-8-s4},$Dst16RnHI */
61078   {
61079     M32C_INSN_ADD16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "add16.w-imm4-Q-16-dst16-Rn-direct-HI", "add.w", 16,
61080     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61081   },
61082 /* add.w${Q} #${Imm-8-s4},$Dst16AnHI */
61083   {
61084     M32C_INSN_ADD16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "add16.w-imm4-Q-16-dst16-An-direct-HI", "add.w", 16,
61085     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61086   },
61087 /* add.w${Q} #${Imm-8-s4},[$Dst16An] */
61088   {
61089     M32C_INSN_ADD16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "add16.w-imm4-Q-16-dst16-An-indirect-HI", "add.w", 16,
61090     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61091   },
61092 /* add.w${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
61093   {
61094     M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "add16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "add.w", 24,
61095     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61096   },
61097 /* add.w${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
61098   {
61099     M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "add16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "add.w", 32,
61100     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61101   },
61102 /* add.w${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
61103   {
61104     M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "add16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "add.w", 24,
61105     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61106   },
61107 /* add.w${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
61108   {
61109     M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "add16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "add.w", 32,
61110     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61111   },
61112 /* add.w${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
61113   {
61114     M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "add16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "add.w", 24,
61115     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61116   },
61117 /* add.w${Q} #${Imm-8-s4},${Dsp-16-u16} */
61118   {
61119     M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "add16.w-imm4-Q-16-dst16-16-16-absolute-HI", "add.w", 32,
61120     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61121   },
61122 /* add.b${Q} #${Imm-8-s4},$Dst16RnQI */
61123   {
61124     M32C_INSN_ADD16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "add16.b-imm4-Q-16-dst16-Rn-direct-QI", "add.b", 16,
61125     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61126   },
61127 /* add.b${Q} #${Imm-8-s4},$Dst16AnQI */
61128   {
61129     M32C_INSN_ADD16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "add16.b-imm4-Q-16-dst16-An-direct-QI", "add.b", 16,
61130     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61131   },
61132 /* add.b${Q} #${Imm-8-s4},[$Dst16An] */
61133   {
61134     M32C_INSN_ADD16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "add16.b-imm4-Q-16-dst16-An-indirect-QI", "add.b", 16,
61135     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61136   },
61137 /* add.b${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
61138   {
61139     M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "add16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "add.b", 24,
61140     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61141   },
61142 /* add.b${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
61143   {
61144     M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "add16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "add.b", 32,
61145     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61146   },
61147 /* add.b${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
61148   {
61149     M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "add16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "add.b", 24,
61150     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61151   },
61152 /* add.b${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
61153   {
61154     M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "add16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "add.b", 32,
61155     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61156   },
61157 /* add.b${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
61158   {
61159     M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "add16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "add.b", 24,
61160     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61161   },
61162 /* add.b${Q} #${Imm-8-s4},${Dsp-16-u16} */
61163   {
61164     M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "add16.b-imm4-Q-16-dst16-16-16-absolute-QI", "add.b", 32,
61165     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61166   },
61167 /* add.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
61168   {
61169     M32C_INSN_ADD32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "add.w", 32,
61170     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61171   },
61172 /* add.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
61173   {
61174     M32C_INSN_ADD32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "add.w", 32,
61175     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61176   },
61177 /* add.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
61178   {
61179     M32C_INSN_ADD32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "add.w", 32,
61180     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61181   },
61182 /* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
61183   {
61184     M32C_INSN_ADD32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "add.w", 40,
61185     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61186   },
61187 /* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
61188   {
61189     M32C_INSN_ADD32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "add.w", 40,
61190     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61191   },
61192 /* add.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
61193   {
61194     M32C_INSN_ADD32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "add.w", 40,
61195     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61196   },
61197 /* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
61198   {
61199     M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "add.w", 48,
61200     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61201   },
61202 /* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
61203   {
61204     M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "add.w", 48,
61205     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61206   },
61207 /* add.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
61208   {
61209     M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "add.w", 48,
61210     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61211   },
61212 /* add.w${G} #${Imm-32-HI},${Dsp-16-u16} */
61213   {
61214     M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "add.w", 48,
61215     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61216   },
61217 /* add.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
61218   {
61219     M32C_INSN_ADD32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "add.w", 56,
61220     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61221   },
61222 /* add.w${G} #${Imm-40-HI},${Dsp-16-u24} */
61223   {
61224     M32C_INSN_ADD32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "add.w", 56,
61225     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61226   },
61227 /* add.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
61228   {
61229     M32C_INSN_ADD32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "add.b", 24,
61230     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61231   },
61232 /* add.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
61233   {
61234     M32C_INSN_ADD32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "add.b", 24,
61235     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61236   },
61237 /* add.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
61238   {
61239     M32C_INSN_ADD32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "add.b", 24,
61240     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61241   },
61242 /* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
61243   {
61244     M32C_INSN_ADD32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "add.b", 32,
61245     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61246   },
61247 /* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
61248   {
61249     M32C_INSN_ADD32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "add.b", 32,
61250     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61251   },
61252 /* add.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
61253   {
61254     M32C_INSN_ADD32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "add.b", 32,
61255     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61256   },
61257 /* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
61258   {
61259     M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "add.b", 40,
61260     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61261   },
61262 /* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
61263   {
61264     M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "add.b", 40,
61265     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61266   },
61267 /* add.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
61268   {
61269     M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "add.b", 40,
61270     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61271   },
61272 /* add.b${G} #${Imm-32-QI},${Dsp-16-u16} */
61273   {
61274     M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "add.b", 40,
61275     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61276   },
61277 /* add.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
61278   {
61279     M32C_INSN_ADD32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "add.b", 48,
61280     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61281   },
61282 /* add.b${G} #${Imm-40-QI},${Dsp-16-u24} */
61283   {
61284     M32C_INSN_ADD32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "add.b", 48,
61285     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61286   },
61287 /* add.w${G} #${Imm-16-HI},$Dst16RnHI */
61288   {
61289     M32C_INSN_ADD16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "add16.w-imm-G-basic-dst16-Rn-direct-HI", "add.w", 32,
61290     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61291   },
61292 /* add.w${G} #${Imm-16-HI},$Dst16AnHI */
61293   {
61294     M32C_INSN_ADD16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "add16.w-imm-G-basic-dst16-An-direct-HI", "add.w", 32,
61295     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61296   },
61297 /* add.w${G} #${Imm-16-HI},[$Dst16An] */
61298   {
61299     M32C_INSN_ADD16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "add16.w-imm-G-basic-dst16-An-indirect-HI", "add.w", 32,
61300     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61301   },
61302 /* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
61303   {
61304     M32C_INSN_ADD16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "add16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "add.w", 40,
61305     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61306   },
61307 /* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
61308   {
61309     M32C_INSN_ADD16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "add16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "add.w", 40,
61310     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61311   },
61312 /* add.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
61313   {
61314     M32C_INSN_ADD16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "add16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "add.w", 40,
61315     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61316   },
61317 /* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
61318   {
61319     M32C_INSN_ADD16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "add16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "add.w", 48,
61320     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61321   },
61322 /* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
61323   {
61324     M32C_INSN_ADD16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "add16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "add.w", 48,
61325     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61326   },
61327 /* add.w${G} #${Imm-32-HI},${Dsp-16-u16} */
61328   {
61329     M32C_INSN_ADD16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "add16.w-imm-G-16-16-dst16-16-16-absolute-HI", "add.w", 48,
61330     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61331   },
61332 /* add.b${G} #${Imm-16-QI},$Dst16RnQI */
61333   {
61334     M32C_INSN_ADD16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "add16.b-imm-G-basic-dst16-Rn-direct-QI", "add.b", 24,
61335     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61336   },
61337 /* add.b${G} #${Imm-16-QI},$Dst16AnQI */
61338   {
61339     M32C_INSN_ADD16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "add16.b-imm-G-basic-dst16-An-direct-QI", "add.b", 24,
61340     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61341   },
61342 /* add.b${G} #${Imm-16-QI},[$Dst16An] */
61343   {
61344     M32C_INSN_ADD16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "add16.b-imm-G-basic-dst16-An-indirect-QI", "add.b", 24,
61345     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61346   },
61347 /* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
61348   {
61349     M32C_INSN_ADD16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "add16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "add.b", 32,
61350     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61351   },
61352 /* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
61353   {
61354     M32C_INSN_ADD16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "add16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "add.b", 32,
61355     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61356   },
61357 /* add.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
61358   {
61359     M32C_INSN_ADD16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "add16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "add.b", 32,
61360     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61361   },
61362 /* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
61363   {
61364     M32C_INSN_ADD16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "add16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "add.b", 40,
61365     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61366   },
61367 /* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
61368   {
61369     M32C_INSN_ADD16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "add16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "add.b", 40,
61370     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61371   },
61372 /* add.b${G} #${Imm-32-QI},${Dsp-16-u16} */
61373   {
61374     M32C_INSN_ADD16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "add16.b-imm-G-16-16-dst16-16-16-absolute-QI", "add.b", 40,
61375     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61376   },
61377 /* add.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */
61378   {
61379     M32C_INSN_ADD32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "add.l", 48,
61380     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61381   },
61382 /* add.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */
61383   {
61384     M32C_INSN_ADD32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "add.l", 48,
61385     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61386   },
61387 /* add.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */
61388   {
61389     M32C_INSN_ADD32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "add.l", 48,
61390     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61391   },
61392 /* add.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
61393   {
61394     M32C_INSN_ADD32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "add.l", 56,
61395     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61396   },
61397 /* add.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */
61398   {
61399     M32C_INSN_ADD32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "add.l", 56,
61400     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61401   },
61402 /* add.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */
61403   {
61404     M32C_INSN_ADD32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "add.l", 56,
61405     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61406   },
61407 /* add.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
61408   {
61409     M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "add.l", 64,
61410     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61411   },
61412 /* add.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */
61413   {
61414     M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "add.l", 64,
61415     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61416   },
61417 /* add.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */
61418   {
61419     M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "add.l", 64,
61420     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61421   },
61422 /* add.l${G} #${Imm-32-SI},${Dsp-16-u16} */
61423   {
61424     M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "add.l", 64,
61425     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61426   },
61427 /* add.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
61428   {
61429     M32C_INSN_ADD32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "add.l", 72,
61430     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61431   },
61432 /* add.l${G} #${Imm-40-SI},${Dsp-16-u24} */
61433   {
61434     M32C_INSN_ADD32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "add.l", 72,
61435     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61436   },
61437 /* adcf.w $Dst32RnUnprefixedHI */
61438   {
61439     M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "adcf.w", 16,
61440     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61441   },
61442 /* adcf.w $Dst32AnUnprefixedHI */
61443   {
61444     M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "adcf.w", 16,
61445     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61446   },
61447 /* adcf.w [$Dst32AnUnprefixed] */
61448   {
61449     M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "adcf.w", 16,
61450     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61451   },
61452 /* adcf.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
61453   {
61454     M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "adcf.w", 24,
61455     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61456   },
61457 /* adcf.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
61458   {
61459     M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "adcf.w", 32,
61460     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61461   },
61462 /* adcf.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
61463   {
61464     M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "adcf.w", 40,
61465     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61466   },
61467 /* adcf.w ${Dsp-16-u8}[sb] */
61468   {
61469     M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "adcf.w", 24,
61470     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61471   },
61472 /* adcf.w ${Dsp-16-u16}[sb] */
61473   {
61474     M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "adcf.w", 32,
61475     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61476   },
61477 /* adcf.w ${Dsp-16-s8}[fb] */
61478   {
61479     M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "adcf.w", 24,
61480     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61481   },
61482 /* adcf.w ${Dsp-16-s16}[fb] */
61483   {
61484     M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "adcf.w", 32,
61485     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61486   },
61487 /* adcf.w ${Dsp-16-u16} */
61488   {
61489     M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "adcf.w", 32,
61490     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61491   },
61492 /* adcf.w ${Dsp-16-u24} */
61493   {
61494     M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "adcf.w", 40,
61495     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61496   },
61497 /* adcf.b $Dst32RnUnprefixedQI */
61498   {
61499     M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "adcf.b", 16,
61500     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61501   },
61502 /* adcf.b $Dst32AnUnprefixedQI */
61503   {
61504     M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "adcf.b", 16,
61505     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61506   },
61507 /* adcf.b [$Dst32AnUnprefixed] */
61508   {
61509     M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "adcf.b", 16,
61510     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61511   },
61512 /* adcf.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
61513   {
61514     M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "adcf.b", 24,
61515     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61516   },
61517 /* adcf.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
61518   {
61519     M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "adcf.b", 32,
61520     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61521   },
61522 /* adcf.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
61523   {
61524     M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "adcf.b", 40,
61525     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61526   },
61527 /* adcf.b ${Dsp-16-u8}[sb] */
61528   {
61529     M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "adcf.b", 24,
61530     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61531   },
61532 /* adcf.b ${Dsp-16-u16}[sb] */
61533   {
61534     M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "adcf.b", 32,
61535     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61536   },
61537 /* adcf.b ${Dsp-16-s8}[fb] */
61538   {
61539     M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "adcf.b", 24,
61540     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61541   },
61542 /* adcf.b ${Dsp-16-s16}[fb] */
61543   {
61544     M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "adcf.b", 32,
61545     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61546   },
61547 /* adcf.b ${Dsp-16-u16} */
61548   {
61549     M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "adcf.b", 32,
61550     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61551   },
61552 /* adcf.b ${Dsp-16-u24} */
61553   {
61554     M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "adcf.b", 40,
61555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61556   },
61557 /* adcf.w $Dst16RnHI */
61558   {
61559     M32C_INSN_ADCF16_W_16_DST16_RN_DIRECT_HI, "adcf16.w-16-dst16-Rn-direct-HI", "adcf.w", 16,
61560     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61561   },
61562 /* adcf.w $Dst16AnHI */
61563   {
61564     M32C_INSN_ADCF16_W_16_DST16_AN_DIRECT_HI, "adcf16.w-16-dst16-An-direct-HI", "adcf.w", 16,
61565     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61566   },
61567 /* adcf.w [$Dst16An] */
61568   {
61569     M32C_INSN_ADCF16_W_16_DST16_AN_INDIRECT_HI, "adcf16.w-16-dst16-An-indirect-HI", "adcf.w", 16,
61570     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61571   },
61572 /* adcf.w ${Dsp-16-u8}[$Dst16An] */
61573   {
61574     M32C_INSN_ADCF16_W_16_DST16_16_8_AN_RELATIVE_HI, "adcf16.w-16-dst16-16-8-An-relative-HI", "adcf.w", 24,
61575     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61576   },
61577 /* adcf.w ${Dsp-16-u16}[$Dst16An] */
61578   {
61579     M32C_INSN_ADCF16_W_16_DST16_16_16_AN_RELATIVE_HI, "adcf16.w-16-dst16-16-16-An-relative-HI", "adcf.w", 32,
61580     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61581   },
61582 /* adcf.w ${Dsp-16-u8}[sb] */
61583   {
61584     M32C_INSN_ADCF16_W_16_DST16_16_8_SB_RELATIVE_HI, "adcf16.w-16-dst16-16-8-SB-relative-HI", "adcf.w", 24,
61585     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61586   },
61587 /* adcf.w ${Dsp-16-u16}[sb] */
61588   {
61589     M32C_INSN_ADCF16_W_16_DST16_16_16_SB_RELATIVE_HI, "adcf16.w-16-dst16-16-16-SB-relative-HI", "adcf.w", 32,
61590     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61591   },
61592 /* adcf.w ${Dsp-16-s8}[fb] */
61593   {
61594     M32C_INSN_ADCF16_W_16_DST16_16_8_FB_RELATIVE_HI, "adcf16.w-16-dst16-16-8-FB-relative-HI", "adcf.w", 24,
61595     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61596   },
61597 /* adcf.w ${Dsp-16-u16} */
61598   {
61599     M32C_INSN_ADCF16_W_16_DST16_16_16_ABSOLUTE_HI, "adcf16.w-16-dst16-16-16-absolute-HI", "adcf.w", 32,
61600     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61601   },
61602 /* adcf.b $Dst16RnQI */
61603   {
61604     M32C_INSN_ADCF16_B_16_DST16_RN_DIRECT_QI, "adcf16.b-16-dst16-Rn-direct-QI", "adcf.b", 16,
61605     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61606   },
61607 /* adcf.b $Dst16AnQI */
61608   {
61609     M32C_INSN_ADCF16_B_16_DST16_AN_DIRECT_QI, "adcf16.b-16-dst16-An-direct-QI", "adcf.b", 16,
61610     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61611   },
61612 /* adcf.b [$Dst16An] */
61613   {
61614     M32C_INSN_ADCF16_B_16_DST16_AN_INDIRECT_QI, "adcf16.b-16-dst16-An-indirect-QI", "adcf.b", 16,
61615     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61616   },
61617 /* adcf.b ${Dsp-16-u8}[$Dst16An] */
61618   {
61619     M32C_INSN_ADCF16_B_16_DST16_16_8_AN_RELATIVE_QI, "adcf16.b-16-dst16-16-8-An-relative-QI", "adcf.b", 24,
61620     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61621   },
61622 /* adcf.b ${Dsp-16-u16}[$Dst16An] */
61623   {
61624     M32C_INSN_ADCF16_B_16_DST16_16_16_AN_RELATIVE_QI, "adcf16.b-16-dst16-16-16-An-relative-QI", "adcf.b", 32,
61625     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61626   },
61627 /* adcf.b ${Dsp-16-u8}[sb] */
61628   {
61629     M32C_INSN_ADCF16_B_16_DST16_16_8_SB_RELATIVE_QI, "adcf16.b-16-dst16-16-8-SB-relative-QI", "adcf.b", 24,
61630     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61631   },
61632 /* adcf.b ${Dsp-16-u16}[sb] */
61633   {
61634     M32C_INSN_ADCF16_B_16_DST16_16_16_SB_RELATIVE_QI, "adcf16.b-16-dst16-16-16-SB-relative-QI", "adcf.b", 32,
61635     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61636   },
61637 /* adcf.b ${Dsp-16-s8}[fb] */
61638   {
61639     M32C_INSN_ADCF16_B_16_DST16_16_8_FB_RELATIVE_QI, "adcf16.b-16-dst16-16-8-FB-relative-QI", "adcf.b", 24,
61640     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61641   },
61642 /* adcf.b ${Dsp-16-u16} */
61643   {
61644     M32C_INSN_ADCF16_B_16_DST16_16_16_ABSOLUTE_QI, "adcf16.b-16-dst16-16-16-absolute-QI", "adcf.b", 32,
61645     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61646   },
61647 /* abs.w $Dst32RnUnprefixedHI */
61648   {
61649     M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "abs.w", 16,
61650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61651   },
61652 /* abs.w $Dst32AnUnprefixedHI */
61653   {
61654     M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "abs.w", 16,
61655     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61656   },
61657 /* abs.w [$Dst32AnUnprefixed] */
61658   {
61659     M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "abs.w", 16,
61660     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61661   },
61662 /* abs.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
61663   {
61664     M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "abs.w", 24,
61665     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61666   },
61667 /* abs.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
61668   {
61669     M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "abs.w", 32,
61670     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61671   },
61672 /* abs.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
61673   {
61674     M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "abs.w", 40,
61675     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61676   },
61677 /* abs.w ${Dsp-16-u8}[sb] */
61678   {
61679     M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "abs.w", 24,
61680     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61681   },
61682 /* abs.w ${Dsp-16-u16}[sb] */
61683   {
61684     M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "abs.w", 32,
61685     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61686   },
61687 /* abs.w ${Dsp-16-s8}[fb] */
61688   {
61689     M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "abs.w", 24,
61690     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61691   },
61692 /* abs.w ${Dsp-16-s16}[fb] */
61693   {
61694     M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "abs.w", 32,
61695     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61696   },
61697 /* abs.w ${Dsp-16-u16} */
61698   {
61699     M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "abs.w", 32,
61700     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61701   },
61702 /* abs.w ${Dsp-16-u24} */
61703   {
61704     M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "abs.w", 40,
61705     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61706   },
61707 /* abs.b $Dst32RnUnprefixedQI */
61708   {
61709     M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "abs.b", 16,
61710     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61711   },
61712 /* abs.b $Dst32AnUnprefixedQI */
61713   {
61714     M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "abs.b", 16,
61715     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61716   },
61717 /* abs.b [$Dst32AnUnprefixed] */
61718   {
61719     M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "abs.b", 16,
61720     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61721   },
61722 /* abs.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
61723   {
61724     M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "abs.b", 24,
61725     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61726   },
61727 /* abs.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
61728   {
61729     M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "abs.b", 32,
61730     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61731   },
61732 /* abs.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
61733   {
61734     M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "abs.b", 40,
61735     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61736   },
61737 /* abs.b ${Dsp-16-u8}[sb] */
61738   {
61739     M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "abs.b", 24,
61740     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61741   },
61742 /* abs.b ${Dsp-16-u16}[sb] */
61743   {
61744     M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "abs.b", 32,
61745     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61746   },
61747 /* abs.b ${Dsp-16-s8}[fb] */
61748   {
61749     M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "abs.b", 24,
61750     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61751   },
61752 /* abs.b ${Dsp-16-s16}[fb] */
61753   {
61754     M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "abs.b", 32,
61755     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61756   },
61757 /* abs.b ${Dsp-16-u16} */
61758   {
61759     M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "abs.b", 32,
61760     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61761   },
61762 /* abs.b ${Dsp-16-u24} */
61763   {
61764     M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "abs.b", 40,
61765     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61766   },
61767 /* abs.w $Dst16RnHI */
61768   {
61769     M32C_INSN_ABS16_W_16_DST16_RN_DIRECT_HI, "abs16.w-16-dst16-Rn-direct-HI", "abs.w", 16,
61770     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61771   },
61772 /* abs.w $Dst16AnHI */
61773   {
61774     M32C_INSN_ABS16_W_16_DST16_AN_DIRECT_HI, "abs16.w-16-dst16-An-direct-HI", "abs.w", 16,
61775     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61776   },
61777 /* abs.w [$Dst16An] */
61778   {
61779     M32C_INSN_ABS16_W_16_DST16_AN_INDIRECT_HI, "abs16.w-16-dst16-An-indirect-HI", "abs.w", 16,
61780     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61781   },
61782 /* abs.w ${Dsp-16-u8}[$Dst16An] */
61783   {
61784     M32C_INSN_ABS16_W_16_DST16_16_8_AN_RELATIVE_HI, "abs16.w-16-dst16-16-8-An-relative-HI", "abs.w", 24,
61785     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61786   },
61787 /* abs.w ${Dsp-16-u16}[$Dst16An] */
61788   {
61789     M32C_INSN_ABS16_W_16_DST16_16_16_AN_RELATIVE_HI, "abs16.w-16-dst16-16-16-An-relative-HI", "abs.w", 32,
61790     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61791   },
61792 /* abs.w ${Dsp-16-u8}[sb] */
61793   {
61794     M32C_INSN_ABS16_W_16_DST16_16_8_SB_RELATIVE_HI, "abs16.w-16-dst16-16-8-SB-relative-HI", "abs.w", 24,
61795     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61796   },
61797 /* abs.w ${Dsp-16-u16}[sb] */
61798   {
61799     M32C_INSN_ABS16_W_16_DST16_16_16_SB_RELATIVE_HI, "abs16.w-16-dst16-16-16-SB-relative-HI", "abs.w", 32,
61800     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61801   },
61802 /* abs.w ${Dsp-16-s8}[fb] */
61803   {
61804     M32C_INSN_ABS16_W_16_DST16_16_8_FB_RELATIVE_HI, "abs16.w-16-dst16-16-8-FB-relative-HI", "abs.w", 24,
61805     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61806   },
61807 /* abs.w ${Dsp-16-u16} */
61808   {
61809     M32C_INSN_ABS16_W_16_DST16_16_16_ABSOLUTE_HI, "abs16.w-16-dst16-16-16-absolute-HI", "abs.w", 32,
61810     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61811   },
61812 /* abs.b $Dst16RnQI */
61813   {
61814     M32C_INSN_ABS16_B_16_DST16_RN_DIRECT_QI, "abs16.b-16-dst16-Rn-direct-QI", "abs.b", 16,
61815     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61816   },
61817 /* abs.b $Dst16AnQI */
61818   {
61819     M32C_INSN_ABS16_B_16_DST16_AN_DIRECT_QI, "abs16.b-16-dst16-An-direct-QI", "abs.b", 16,
61820     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61821   },
61822 /* abs.b [$Dst16An] */
61823   {
61824     M32C_INSN_ABS16_B_16_DST16_AN_INDIRECT_QI, "abs16.b-16-dst16-An-indirect-QI", "abs.b", 16,
61825     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61826   },
61827 /* abs.b ${Dsp-16-u8}[$Dst16An] */
61828   {
61829     M32C_INSN_ABS16_B_16_DST16_16_8_AN_RELATIVE_QI, "abs16.b-16-dst16-16-8-An-relative-QI", "abs.b", 24,
61830     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61831   },
61832 /* abs.b ${Dsp-16-u16}[$Dst16An] */
61833   {
61834     M32C_INSN_ABS16_B_16_DST16_16_16_AN_RELATIVE_QI, "abs16.b-16-dst16-16-16-An-relative-QI", "abs.b", 32,
61835     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61836   },
61837 /* abs.b ${Dsp-16-u8}[sb] */
61838   {
61839     M32C_INSN_ABS16_B_16_DST16_16_8_SB_RELATIVE_QI, "abs16.b-16-dst16-16-8-SB-relative-QI", "abs.b", 24,
61840     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61841   },
61842 /* abs.b ${Dsp-16-u16}[sb] */
61843   {
61844     M32C_INSN_ABS16_B_16_DST16_16_16_SB_RELATIVE_QI, "abs16.b-16-dst16-16-16-SB-relative-QI", "abs.b", 32,
61845     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61846   },
61847 /* abs.b ${Dsp-16-s8}[fb] */
61848   {
61849     M32C_INSN_ABS16_B_16_DST16_16_8_FB_RELATIVE_QI, "abs16.b-16-dst16-16-8-FB-relative-QI", "abs.b", 24,
61850     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61851   },
61852 /* abs.b ${Dsp-16-u16} */
61853   {
61854     M32C_INSN_ABS16_B_16_DST16_16_16_ABSOLUTE_QI, "abs16.b-16-dst16-16-16-absolute-QI", "abs.b", 32,
61855     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61856   },
61857 /* add${size}$Q #${Imm-12-s4},sp */
61858   {
61859     M32C_INSN_ADD16_Q_SP, "add16-Q-sp", "add", 16,
61860     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61861   },
61862 /* add.b$G #${Imm-16-QI},sp */
61863   {
61864     M32C_INSN_ADD16_B_G_SP, "add16.b-G-sp", "add.b", 24,
61865     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61866   },
61867 /* add.w$G #${Imm-16-HI},sp */
61868   {
61869     M32C_INSN_ADD16_W_G_SP, "add16.w-G-sp", "add.w", 32,
61870     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61871   },
61872 /* add.l$Q #${Imm3-S},sp */
61873   {
61874     M32C_INSN_ADD32_L_IMM3_Q, "add32.l-imm3-Q", "add.l", 8,
61875     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61876   },
61877 /* add.l$S #${Imm-16-QI},sp */
61878   {
61879     M32C_INSN_ADD32_L_IMM8_S, "add32.l-imm8-S", "add.l", 24,
61880     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61881   },
61882 /* add.l$G #${Imm-16-HI},sp */
61883   {
61884     M32C_INSN_ADD32_L_IMM16_G, "add32.l-imm16-G", "add.l", 32,
61885     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61886   },
61887 /* dadc.b #${Imm-16-QI} */
61888   {
61889     M32C_INSN_DADC16_B_IMM8, "dadc16.b-imm8", "dadc.b", 24,
61890     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61891   },
61892 /* dadc.w #${Imm-16-HI} */
61893   {
61894     M32C_INSN_DADC16_W_IMM16, "dadc16.w-imm16", "dadc.w", 32,
61895     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61896   },
61897 /* dadc.b r0h,r0l */
61898   {
61899     M32C_INSN_DADC16_B_R0H_R0L, "dadc16.b-r0h-r0l", "dadc.b", 16,
61900     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61901   },
61902 /* dadc.w r1,r0 */
61903   {
61904     M32C_INSN_DADC16_W_R1_R0, "dadc16.w-r1-r0", "dadc.w", 16,
61905     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61906   },
61907 /* dadd.b #${Imm-16-QI} */
61908   {
61909     M32C_INSN_DADD16_B_IMM8, "dadd16.b-imm8", "dadd.b", 24,
61910     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61911   },
61912 /* dadd.w #${Imm-16-HI} */
61913   {
61914     M32C_INSN_DADD16_W_IMM16, "dadd16.w-imm16", "dadd.w", 32,
61915     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61916   },
61917 /* dadd.b r0h,r0l */
61918   {
61919     M32C_INSN_DADD16_B_R0H_R0L, "dadd16.b-r0h-r0l", "dadd.b", 16,
61920     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61921   },
61922 /* dadd.w r1,r0 */
61923   {
61924     M32C_INSN_DADD16_W_R1_R0, "dadd16.w-r1-r0", "dadd.w", 16,
61925     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61926   },
61927 /* bm$cond16c c */
61928   {
61929     M32C_INSN_BM16_C, "bm16-c", "bm", 16,
61930     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61931   },
61932 /* bm$cond32 c */
61933   {
61934     M32C_INSN_BM32_C, "bm32-c", "bm", 16,
61935     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61936   },
61937 /* brk */
61938   {
61939     M32C_INSN_BRK16, "brk16", "brk", 8,
61940     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61941   },
61942 /* brk */
61943   {
61944     M32C_INSN_BRK32, "brk32", "brk", 8,
61945     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61946   },
61947 /* brk2 */
61948   {
61949     M32C_INSN_BRK232, "brk232", "brk2", 8,
61950     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61951   },
61952 /* dec.w ${Dst16An-S} */
61953   {
61954     M32C_INSN_DEC16_W, "dec16.w", "dec.w", 8,
61955     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61956   },
61957 /* div.b #${Imm-16-QI} */
61958   {
61959     M32C_INSN_DIV16_B_IMM_16_QI, "div16.b-Imm-16-QI", "div.b", 24,
61960     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61961   },
61962 /* div.w #${Imm-16-HI} */
61963   {
61964     M32C_INSN_DIV16_W_IMM_16_HI, "div16.w-Imm-16-HI", "div.w", 32,
61965     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61966   },
61967 /* div.b #${Imm-16-QI} */
61968   {
61969     M32C_INSN_DIV32_B_IMM_16_QI, "div32.b-Imm-16-QI", "div.b", 24,
61970     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61971   },
61972 /* div.w #${Imm-16-HI} */
61973   {
61974     M32C_INSN_DIV32_W_IMM_16_HI, "div32.w-Imm-16-HI", "div.w", 32,
61975     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61976   },
61977 /* divu.b #${Imm-16-QI} */
61978   {
61979     M32C_INSN_DIVU16_B_IMM_16_QI, "divu16.b-Imm-16-QI", "divu.b", 24,
61980     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61981   },
61982 /* divu.w #${Imm-16-HI} */
61983   {
61984     M32C_INSN_DIVU16_W_IMM_16_HI, "divu16.w-Imm-16-HI", "divu.w", 32,
61985     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61986   },
61987 /* divu.b #${Imm-16-QI} */
61988   {
61989     M32C_INSN_DIVU32_B_IMM_16_QI, "divu32.b-Imm-16-QI", "divu.b", 24,
61990     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61991   },
61992 /* divu.w #${Imm-16-HI} */
61993   {
61994     M32C_INSN_DIVU32_W_IMM_16_HI, "divu32.w-Imm-16-HI", "divu.w", 32,
61995     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61996   },
61997 /* divx.b #${Imm-16-QI} */
61998   {
61999     M32C_INSN_DIVX16_B_IMM_16_QI, "divx16.b-Imm-16-QI", "divx.b", 24,
62000     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62001   },
62002 /* divx.w #${Imm-16-HI} */
62003   {
62004     M32C_INSN_DIVX16_W_IMM_16_HI, "divx16.w-Imm-16-HI", "divx.w", 32,
62005     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62006   },
62007 /* divx.b #${Imm-16-QI} */
62008   {
62009     M32C_INSN_DIVX32_B_IMM_16_QI, "divx32.b-Imm-16-QI", "divx.b", 24,
62010     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62011   },
62012 /* divx.w #${Imm-16-HI} */
62013   {
62014     M32C_INSN_DIVX32_W_IMM_16_HI, "divx32.w-Imm-16-HI", "divx.w", 32,
62015     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62016   },
62017 /* dsbb.b #${Imm-16-QI} */
62018   {
62019     M32C_INSN_DSBB16_B_IMM8, "dsbb16.b-imm8", "dsbb.b", 24,
62020     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62021   },
62022 /* dsbb.w #${Imm-16-HI} */
62023   {
62024     M32C_INSN_DSBB16_W_IMM16, "dsbb16.w-imm16", "dsbb.w", 32,
62025     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62026   },
62027 /* dsbb.b r0h,r0l */
62028   {
62029     M32C_INSN_DSBB16_B_R0H_R0L, "dsbb16.b-r0h-r0l", "dsbb.b", 16,
62030     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62031   },
62032 /* dsbb.w r1,r0 */
62033   {
62034     M32C_INSN_DSBB16_W_R1_R0, "dsbb16.w-r1-r0", "dsbb.w", 16,
62035     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62036   },
62037 /* dsub.b #${Imm-16-QI} */
62038   {
62039     M32C_INSN_DSUB16_B_IMM8, "dsub16.b-imm8", "dsub.b", 24,
62040     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62041   },
62042 /* dsub.w #${Imm-16-HI} */
62043   {
62044     M32C_INSN_DSUB16_W_IMM16, "dsub16.w-imm16", "dsub.w", 32,
62045     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62046   },
62047 /* dsub.b r0h,r0l */
62048   {
62049     M32C_INSN_DSUB16_B_R0H_R0L, "dsub16.b-r0h-r0l", "dsub.b", 16,
62050     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62051   },
62052 /* dsub.w r1,r0 */
62053   {
62054     M32C_INSN_DSUB16_W_R1_R0, "dsub16.w-r1-r0", "dsub.w", 16,
62055     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62056   },
62057 /* enter #${Dsp-16-u8} */
62058   {
62059     M32C_INSN_ENTER16, "enter16", "enter", 24,
62060     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62061   },
62062 /* exitd */
62063   {
62064     M32C_INSN_EXITD16, "exitd16", "exitd", 16,
62065     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
62066   },
62067 /* enter #${Dsp-8-u8} */
62068   {
62069     M32C_INSN_ENTER32, "enter32", "enter", 16,
62070     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62071   },
62072 /* exitd */
62073   {
62074     M32C_INSN_EXITD32, "exitd32", "exitd", 8,
62075     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
62076   },
62077 /* fclr ${flags16} */
62078   {
62079     M32C_INSN_FCLR16, "fclr16", "fclr", 16,
62080     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62081   },
62082 /* fset ${flags16} */
62083   {
62084     M32C_INSN_FSET16, "fset16", "fset", 16,
62085     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62086   },
62087 /* fclr ${flags32} */
62088   {
62089     M32C_INSN_FCLR, "fclr", "fclr", 16,
62090     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62091   },
62092 /* fset ${flags32} */
62093   {
62094     M32C_INSN_FSET, "fset", "fset", 16,
62095     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62096   },
62097 /* inc.w ${Dst16An-S} */
62098   {
62099     M32C_INSN_INC16_W, "inc16.w", "inc.w", 8,
62100     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62101   },
62102 /* freit */
62103   {
62104     M32C_INSN_FREIT32, "freit32", "freit", 8,
62105     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62106   },
62107 /* int #${Dsp-10-u6} */
62108   {
62109     M32C_INSN_INT16, "int16", "int", 16,
62110     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62111   },
62112 /* into */
62113   {
62114     M32C_INSN_INTO16, "into16", "into", 8,
62115     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62116   },
62117 /* int #${Dsp-8-u6} */
62118   {
62119     M32C_INSN_INT32, "int32", "int", 16,
62120     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62121   },
62122 /* into */
62123   {
62124     M32C_INSN_INTO32, "into32", "into", 8,
62125     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62126   },
62127 /* j$cond16j5 ${Lab-8-8} */
62128   {
62129     M32C_INSN_JCND16_5, "jcnd16-5", "j", 16,
62130     { 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
62131   },
62132 /* j$cond16j ${Lab-16-8} */
62133   {
62134     M32C_INSN_JCND16, "jcnd16", "j", 24,
62135     { 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
62136   },
62137 /* j$cond32j ${Lab-8-8} */
62138   {
62139     M32C_INSN_JCND32, "jcnd32", "j", 16,
62140     { 0|A(RELAXABLE)|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
62141   },
62142 /* jmp.s ${Lab-5-3} */
62143   {
62144     M32C_INSN_JMP16_S, "jmp16.s", "jmp.s", 8,
62145     { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
62146   },
62147 /* jmp.b ${Lab-8-8} */
62148   {
62149     M32C_INSN_JMP16_B, "jmp16.b", "jmp.b", 16,
62150     { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
62151   },
62152 /* jmp.w ${Lab-8-16} */
62153   {
62154     M32C_INSN_JMP16_W, "jmp16.w", "jmp.w", 24,
62155     { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
62156   },
62157 /* jmp.a ${Lab-8-24} */
62158   {
62159     M32C_INSN_JMP16_A, "jmp16.a", "jmp.a", 32,
62160     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
62161   },
62162 /* jmps #${Imm-8-QI} */
62163   {
62164     M32C_INSN_JMPS16, "jmps16", "jmps", 16,
62165     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
62166   },
62167 /* jmp.s ${Lab32-jmp-s} */
62168   {
62169     M32C_INSN_JMP32_S, "jmp32.s", "jmp.s", 8,
62170     { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
62171   },
62172 /* jmp.b ${Lab-8-8} */
62173   {
62174     M32C_INSN_JMP32_B, "jmp32.b", "jmp.b", 16,
62175     { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
62176   },
62177 /* jmp.w ${Lab-8-16} */
62178   {
62179     M32C_INSN_JMP32_W, "jmp32.w", "jmp.w", 24,
62180     { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
62181   },
62182 /* jmp.a ${Lab-8-24} */
62183   {
62184     M32C_INSN_JMP32_A, "jmp32.a", "jmp.a", 32,
62185     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
62186   },
62187 /* jmps #${Imm-8-QI} */
62188   {
62189     M32C_INSN_JMPS32, "jmps32", "jmps", 16,
62190     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
62191   },
62192 /* jsr.w ${Lab-8-16} */
62193   {
62194     M32C_INSN_JSR16_W, "jsr16.w", "jsr.w", 24,
62195     { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
62196   },
62197 /* jsr.a ${Lab-8-24} */
62198   {
62199     M32C_INSN_JSR16_A, "jsr16.a", "jsr.a", 32,
62200     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
62201   },
62202 /* jsr.w ${Lab-8-16} */
62203   {
62204     M32C_INSN_JSR32_W, "jsr32.w", "jsr.w", 24,
62205     { 0|A(RELAXABLE)|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
62206   },
62207 /* jsr.a ${Lab-8-24} */
62208   {
62209     M32C_INSN_JSR32_A, "jsr32.a", "jsr.a", 32,
62210     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
62211   },
62212 /* jsrs #${Imm-8-QI} */
62213   {
62214     M32C_INSN_JSRS16, "jsrs16", "jsrs", 16,
62215     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
62216   },
62217 /* jsrs #${Imm-8-QI} */
62218   {
62219     M32C_INSN_JSRS, "jsrs", "jsrs", 16,
62220     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
62221   },
62222 /* ldc #${Imm-16-HI},${cr16} */
62223   {
62224     M32C_INSN_LDC16_IMM16, "ldc16.imm16", "ldc", 32,
62225     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62226   },
62227 /* ldc #${Imm-16-HI},${cr1-Unprefixed-32} */
62228   {
62229     M32C_INSN_LDC32_IMM16_CR1, "ldc32.imm16-cr1", "ldc", 32,
62230     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62231   },
62232 /* ldc #${Dsp-16-u24},${cr2-32} */
62233   {
62234     M32C_INSN_LDC32_IMM16_CR2, "ldc32.imm16-cr2", "ldc", 40,
62235     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62236   },
62237 /* ldc #${Dsp-16-u24},${cr3-Unprefixed-32} */
62238   {
62239     M32C_INSN_LDC32_IMM16_CR3, "ldc32.imm16-cr3", "ldc", 40,
62240     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62241   },
62242 /* ldctx ${Dsp-16-u16},${Dsp-32-u24} */
62243   {
62244     M32C_INSN_LDCTX16, "ldctx16", "ldctx", 56,
62245     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62246   },
62247 /* ldctx ${Dsp-16-u16},${Dsp-32-u24} */
62248   {
62249     M32C_INSN_LDCTX32, "ldctx32", "ldctx", 56,
62250     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62251   },
62252 /* stctx ${Dsp-16-u16},${Dsp-32-u24} */
62253   {
62254     M32C_INSN_STCTX16, "stctx16", "stctx", 56,
62255     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62256   },
62257 /* stctx ${Dsp-16-u16},${Dsp-32-u24} */
62258   {
62259     M32C_INSN_STCTX32, "stctx32", "stctx", 56,
62260     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62261   },
62262 /* ldipl #${Imm-13-u3} */
62263   {
62264     M32C_INSN_LDIPL16_IMM, "ldipl16.imm", "ldipl", 16,
62265     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62266   },
62267 /* ldipl #${Imm-13-u3} */
62268   {
62269     M32C_INSN_LDIPL32_IMM, "ldipl32.imm", "ldipl", 16,
62270     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62271   },
62272 /* mov.b$S #${Imm-8-QI},a0 */
62273   {
62274     M32C_INSN_MOV16_B_S_IMM_A0, "mov16.b.S-imm-a0", "mov.b", 16,
62275     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62276   },
62277 /* mov.b$S #${Imm-8-QI},a1 */
62278   {
62279     M32C_INSN_MOV16_B_S_IMM_A1, "mov16.b.S-imm-a1", "mov.b", 16,
62280     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62281   },
62282 /* mov.w$S #${Imm-8-HI},a0 */
62283   {
62284     M32C_INSN_MOV16_W_S_IMM_A0, "mov16.w.S-imm-a0", "mov.w", 24,
62285     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62286   },
62287 /* mov.w$S #${Imm-8-HI},a1 */
62288   {
62289     M32C_INSN_MOV16_W_S_IMM_A1, "mov16.w.S-imm-a1", "mov.w", 24,
62290     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62291   },
62292 /* mov.w$S #${Imm-8-HI},a0 */
62293   {
62294     M32C_INSN_MOV32_W_A0, "mov32-w-a0", "mov.w", 24,
62295     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62296   },
62297 /* mov.w$S #${Imm-8-HI},a1 */
62298   {
62299     M32C_INSN_MOV32_W_A1, "mov32-w-a1", "mov.w", 24,
62300     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62301   },
62302 /* mov.l$S #${Dsp-8-u24},a0 */
62303   {
62304     M32C_INSN_MOV32_L_A0, "mov32-l-a0", "mov.l", 32,
62305     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62306   },
62307 /* mov.l$S #${Dsp-8-u24},a1 */
62308   {
62309     M32C_INSN_MOV32_L_A1, "mov32-l-a1", "mov.l", 32,
62310     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62311   },
62312 /* mov.b$S r0l,a1 */
62313   {
62314     M32C_INSN_MOV16_B_S_R0L_A1, "mov16.b.S-r0l-a1", "mov.b", 8,
62315     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62316   },
62317 /* mov.b$S r0h,a0 */
62318   {
62319     M32C_INSN_MOV16_B_S_R0H_A0, "mov16.b.S-r0h-a0", "mov.b", 8,
62320     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62321   },
62322 /* nop */
62323   {
62324     M32C_INSN_NOP16, "nop16", "nop", 8,
62325     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62326   },
62327 /* nop */
62328   {
62329     M32C_INSN_NOP32, "nop32", "nop", 8,
62330     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62331   },
62332 /* popc ${cr16} */
62333   {
62334     M32C_INSN_POPC16_IMM16, "popc16.imm16", "popc", 16,
62335     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62336   },
62337 /* popc ${cr1-Unprefixed-32} */
62338   {
62339     M32C_INSN_POPC32_IMM16_CR1, "popc32.imm16-cr1", "popc", 16,
62340     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62341   },
62342 /* popc ${cr2-32} */
62343   {
62344     M32C_INSN_POPC32_IMM16_CR2, "popc32.imm16-cr2", "popc", 16,
62345     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62346   },
62347 /* pushc ${cr16} */
62348   {
62349     M32C_INSN_PUSHC16_IMM16, "pushc16.imm16", "pushc", 16,
62350     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62351   },
62352 /* pushc ${cr1-Unprefixed-32} */
62353   {
62354     M32C_INSN_PUSHC32_IMM16_CR1, "pushc32.imm16-cr1", "pushc", 16,
62355     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62356   },
62357 /* pushc ${cr2-32} */
62358   {
62359     M32C_INSN_PUSHC32_IMM16_CR2, "pushc32.imm16-cr2", "pushc", 16,
62360     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62361   },
62362 /* popm ${Regsetpop} */
62363   {
62364     M32C_INSN_POPM16, "popm16", "popm", 16,
62365     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62366   },
62367 /* pushm ${Regsetpush} */
62368   {
62369     M32C_INSN_PUSHM16, "pushm16", "pushm", 16,
62370     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62371   },
62372 /* popm ${Regsetpop} */
62373   {
62374     M32C_INSN_POPM, "popm", "popm", 16,
62375     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62376   },
62377 /* pushm ${Regsetpush} */
62378   {
62379     M32C_INSN_PUSHM, "pushm", "pushm", 16,
62380     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62381   },
62382 /* push.b$G #${Imm-16-QI} */
62383   {
62384     M32C_INSN_PUSH16_B_G_IMM, "push16.b.G-imm", "push.b", 24,
62385     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62386   },
62387 /* push.w$G #${Imm-16-HI} */
62388   {
62389     M32C_INSN_PUSH16_W_G_IMM, "push16.w.G-imm", "push.w", 32,
62390     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62391   },
62392 /* push.b #Imm-8-QI */
62393   {
62394     M32C_INSN_PUSH32_B_IMM, "push32.b.imm", "push.b", 16,
62395     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62396   },
62397 /* push.w #${Imm-8-HI} */
62398   {
62399     M32C_INSN_PUSH32_W_IMM, "push32.w.imm", "push.w", 24,
62400     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62401   },
62402 /* push.l #${Imm-16-SI} */
62403   {
62404     M32C_INSN_PUSH32_L_IMM, "push32.l.imm", "push.l", 48,
62405     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62406   },
62407 /* reit */
62408   {
62409     M32C_INSN_REIT16, "reit16", "reit", 8,
62410     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62411   },
62412 /* reit */
62413   {
62414     M32C_INSN_REIT32, "reit32", "reit", 8,
62415     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62416   },
62417 /* rmpa.b */
62418   {
62419     M32C_INSN_RMPA16_B, "rmpa16.b", "rmpa.b", 16,
62420     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62421   },
62422 /* rmpa.w */
62423   {
62424     M32C_INSN_RMPA16_W, "rmpa16.w", "rmpa.w", 16,
62425     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62426   },
62427 /* rmpa.b */
62428   {
62429     M32C_INSN_RMPA32_B, "rmpa32.b", "rmpa.b", 16,
62430     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62431   },
62432 /* rmpa.w */
62433   {
62434     M32C_INSN_RMPA32_W, "rmpa32.w", "rmpa.w", 16,
62435     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62436   },
62437 /* rts */
62438   {
62439     M32C_INSN_RTS16, "rts16", "rts", 8,
62440     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
62441   },
62442 /* rts */
62443   {
62444     M32C_INSN_RTS32, "rts32", "rts", 8,
62445     { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
62446   },
62447 /* scmpu.b */
62448   {
62449     M32C_INSN_SCMPU_B, "scmpu.b", "scmpu.b", 16,
62450     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62451   },
62452 /* scmpu.w */
62453   {
62454     M32C_INSN_SCMPU_W, "scmpu.w", "scmpu.w", 16,
62455     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62456   },
62457 /* sha.l #${Imm-sh-12-s4},r2r0 */
62458   {
62459     M32C_INSN_SHA16_L_IMM_R2R0, "sha16-L-imm-r2r0", "sha.l", 16,
62460     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62461   },
62462 /* sha.l #${Imm-sh-12-s4},r3r1 */
62463   {
62464     M32C_INSN_SHA16_L_IMM_R3R1, "sha16-L-imm-r3r1", "sha.l", 16,
62465     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62466   },
62467 /* sha.l r1h,r2r0 */
62468   {
62469     M32C_INSN_SHA16_L_R1H_R2R0, "sha16-L-r1h-r2r0", "sha.l", 16,
62470     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62471   },
62472 /* sha.l r1h,r3r1 */
62473   {
62474     M32C_INSN_SHA16_L_R1H_R3R1, "sha16-L-r1h-r3r1", "sha.l", 16,
62475     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62476   },
62477 /* shl.l #${Imm-sh-12-s4},r2r0 */
62478   {
62479     M32C_INSN_SHL16_L_IMM_R2R0, "shl16-L-imm-r2r0", "shl.l", 16,
62480     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62481   },
62482 /* shl.l #${Imm-sh-12-s4},r3r1 */
62483   {
62484     M32C_INSN_SHL16_L_IMM_R3R1, "shl16-L-imm-r3r1", "shl.l", 16,
62485     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62486   },
62487 /* shl.l r1h,r2r0 */
62488   {
62489     M32C_INSN_SHL16_L_R1H_R2R0, "shl16-L-r1h-r2r0", "shl.l", 16,
62490     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62491   },
62492 /* shl.l r1h,r3r1 */
62493   {
62494     M32C_INSN_SHL16_L_R1H_R3R1, "shl16-L-r1h-r3r1", "shl.l", 16,
62495     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62496   },
62497 /* sin.b */
62498   {
62499     M32C_INSN_SIN32_B, "sin32.b", "sin.b", 16,
62500     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62501   },
62502 /* sin.w */
62503   {
62504     M32C_INSN_SIN32_W, "sin32.w", "sin.w", 16,
62505     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62506   },
62507 /* smovb.b */
62508   {
62509     M32C_INSN_SMOVB16_B, "smovb16.b", "smovb.b", 16,
62510     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62511   },
62512 /* smovb.w */
62513   {
62514     M32C_INSN_SMOVB16_W, "smovb16.w", "smovb.w", 16,
62515     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62516   },
62517 /* smovb.b */
62518   {
62519     M32C_INSN_SMOVB32_B, "smovb32.b", "smovb.b", 16,
62520     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62521   },
62522 /* smovb.w */
62523   {
62524     M32C_INSN_SMOVB32_W, "smovb32.w", "smovb.w", 16,
62525     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62526   },
62527 /* smovf.b */
62528   {
62529     M32C_INSN_SMOVF16_B, "smovf16.b", "smovf.b", 16,
62530     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62531   },
62532 /* smovf.w */
62533   {
62534     M32C_INSN_SMOVF16_W, "smovf16.w", "smovf.w", 16,
62535     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62536   },
62537 /* smovf.b */
62538   {
62539     M32C_INSN_SMOVF32_B, "smovf32.b", "smovf.b", 16,
62540     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62541   },
62542 /* smovf.w */
62543   {
62544     M32C_INSN_SMOVF32_W, "smovf32.w", "smovf.w", 16,
62545     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62546   },
62547 /* smovu.b */
62548   {
62549     M32C_INSN_SMOVU_B, "smovu.b", "smovu.b", 16,
62550     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62551   },
62552 /* smovu.w */
62553   {
62554     M32C_INSN_SMOVU_W, "smovu.w", "smovu.w", 16,
62555     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62556   },
62557 /* sout.b */
62558   {
62559     M32C_INSN_SOUT_B, "sout.b", "sout.b", 16,
62560     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62561   },
62562 /* sout.w */
62563   {
62564     M32C_INSN_SOUT_W, "sout.w", "sout.w", 16,
62565     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62566   },
62567 /* sstr.b */
62568   {
62569     M32C_INSN_SSTR16_B, "sstr16.b", "sstr.b", 16,
62570     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62571   },
62572 /* sstr.w */
62573   {
62574     M32C_INSN_SSTR16_W, "sstr16.w", "sstr.w", 16,
62575     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62576   },
62577 /* sstr.b */
62578   {
62579     M32C_INSN_SSTR_B, "sstr.b", "sstr.b", 16,
62580     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62581   },
62582 /* sstr.w */
62583   {
62584     M32C_INSN_SSTR_W, "sstr.w", "sstr.w", 16,
62585     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62586   },
62587 /* stzx #${Imm-8-QI},#${Imm-16-QI},r0h */
62588   {
62589     M32C_INSN_STZX16_IMM8_IMM8_R0H, "stzx16-imm8-imm8-r0h", "stzx", 24,
62590     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62591   },
62592 /* stzx #${Imm-8-QI},#${Imm-16-QI},r0l */
62593   {
62594     M32C_INSN_STZX16_IMM8_IMM8_R0L, "stzx16-imm8-imm8-r0l", "stzx", 24,
62595     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62596   },
62597 /* stzx #${Imm-8-QI},#${Imm-16-QI},Dsp-24-u8[sb] */
62598   {
62599     M32C_INSN_STZX16_IMM8_IMM8_DSP8SB, "stzx16-imm8-imm8-dsp8sb", "stzx", 32,
62600     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62601   },
62602 /* stzx #${Imm-8-QI},#${Imm-16-QI},Dsp-24-u8[fb] */
62603   {
62604     M32C_INSN_STZX16_IMM8_IMM8_DSP8FB, "stzx16-imm8-imm8-dsp8fb", "stzx", 32,
62605     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62606   },
62607 /* stzx #${Imm-8-QI},#${Imm-16-QI},Dsp-24-u16 */
62608   {
62609     M32C_INSN_STZX16_IMM8_IMM8_ABS16, "stzx16-imm8-imm8-abs16", "stzx", 40,
62610     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62611   },
62612 /* und */
62613   {
62614     M32C_INSN_UND16, "und16", "und", 8,
62615     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62616   },
62617 /* und */
62618   {
62619     M32C_INSN_UND32, "und32", "und", 8,
62620     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62621   },
62622 /* wait */
62623   {
62624     M32C_INSN_WAIT16, "wait16", "wait", 16,
62625     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62626   },
62627 /* wait */
62628   {
62629     M32C_INSN_WAIT, "wait", "wait", 16,
62630     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62631   },
62632 /* exts.w r0 */
62633   {
62634     M32C_INSN_EXTS16_W_R0, "exts16.w-r0", "exts.w", 16,
62635     { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62636   },
62637 /* src-indirect */
62638   {
62639     M32C_INSN_SRCIND, "srcind", "src-indirect", 8,
62640     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62641   },
62642 /* dest-indirect */
62643   {
62644     M32C_INSN_DESTIND, "destind", "dest-indirect", 8,
62645     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62646   },
62647 /* src-dest-indirect */
62648   {
62649     M32C_INSN_SRCDESTIND, "srcdestind", "src-dest-indirect", 8,
62650     { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62651   },
62652 };
62653
62654 #undef OP
62655 #undef A
62656
62657 /* Initialize anything needed to be done once, before any cpu_open call.  */
62658
62659 static void
62660 init_tables (void)
62661 {
62662 }
62663
62664 static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
62665 static void build_hw_table      (CGEN_CPU_TABLE *);
62666 static void build_ifield_table  (CGEN_CPU_TABLE *);
62667 static void build_operand_table (CGEN_CPU_TABLE *);
62668 static void build_insn_table    (CGEN_CPU_TABLE *);
62669 static void m32c_cgen_rebuild_tables (CGEN_CPU_TABLE *);
62670
62671 /* Subroutine of m32c_cgen_cpu_open to look up a mach via its bfd name.  */
62672
62673 static const CGEN_MACH *
62674 lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
62675 {
62676   while (table->name)
62677     {
62678       if (strcmp (name, table->bfd_name) == 0)
62679         return table;
62680       ++table;
62681     }
62682   abort ();
62683 }
62684
62685 /* Subroutine of m32c_cgen_cpu_open to build the hardware table.  */
62686
62687 static void
62688 build_hw_table (CGEN_CPU_TABLE *cd)
62689 {
62690   int i;
62691   int machs = cd->machs;
62692   const CGEN_HW_ENTRY *init = & m32c_cgen_hw_table[0];
62693   /* MAX_HW is only an upper bound on the number of selected entries.
62694      However each entry is indexed by it's enum so there can be holes in
62695      the table.  */
62696   const CGEN_HW_ENTRY **selected =
62697     (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
62698
62699   cd->hw_table.init_entries = init;
62700   cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
62701   memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
62702   /* ??? For now we just use machs to determine which ones we want.  */
62703   for (i = 0; init[i].name != NULL; ++i)
62704     if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
62705         & machs)
62706       selected[init[i].type] = &init[i];
62707   cd->hw_table.entries = selected;
62708   cd->hw_table.num_entries = MAX_HW;
62709 }
62710
62711 /* Subroutine of m32c_cgen_cpu_open to build the hardware table.  */
62712
62713 static void
62714 build_ifield_table (CGEN_CPU_TABLE *cd)
62715 {
62716   cd->ifld_table = & m32c_cgen_ifld_table[0];
62717 }
62718
62719 /* Subroutine of m32c_cgen_cpu_open to build the hardware table.  */
62720
62721 static void
62722 build_operand_table (CGEN_CPU_TABLE *cd)
62723 {
62724   int i;
62725   int machs = cd->machs;
62726   const CGEN_OPERAND *init = & m32c_cgen_operand_table[0];
62727   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
62728      However each entry is indexed by it's enum so there can be holes in
62729      the table.  */
62730   const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
62731
62732   cd->operand_table.init_entries = init;
62733   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
62734   memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
62735   /* ??? For now we just use mach to determine which ones we want.  */
62736   for (i = 0; init[i].name != NULL; ++i)
62737     if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
62738         & machs)
62739       selected[init[i].type] = &init[i];
62740   cd->operand_table.entries = selected;
62741   cd->operand_table.num_entries = MAX_OPERANDS;
62742 }
62743
62744 /* Subroutine of m32c_cgen_cpu_open to build the hardware table.
62745    ??? This could leave out insns not supported by the specified mach/isa,
62746    but that would cause errors like "foo only supported by bar" to become
62747    "unknown insn", so for now we include all insns and require the app to
62748    do the checking later.
62749    ??? On the other hand, parsing of such insns may require their hardware or
62750    operand elements to be in the table [which they mightn't be].  */
62751
62752 static void
62753 build_insn_table (CGEN_CPU_TABLE *cd)
62754 {
62755   int i;
62756   const CGEN_IBASE *ib = & m32c_cgen_insn_table[0];
62757   CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
62758
62759   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
62760   for (i = 0; i < MAX_INSNS; ++i)
62761     insns[i].base = &ib[i];
62762   cd->insn_table.init_entries = insns;
62763   cd->insn_table.entry_size = sizeof (CGEN_IBASE);
62764   cd->insn_table.num_init_entries = MAX_INSNS;
62765 }
62766
62767 /* Subroutine of m32c_cgen_cpu_open to rebuild the tables.  */
62768
62769 static void
62770 m32c_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
62771 {
62772   int i;
62773   unsigned int isas = cd->isas;
62774   unsigned int machs = cd->machs;
62775
62776   cd->int_insn_p = CGEN_INT_INSN_P;
62777
62778   /* Data derived from the isa spec.  */
62779 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
62780   cd->default_insn_bitsize = UNSET;
62781   cd->base_insn_bitsize = UNSET;
62782   cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
62783   cd->max_insn_bitsize = 0;
62784   for (i = 0; i < MAX_ISAS; ++i)
62785     if (((1 << i) & isas) != 0)
62786       {
62787         const CGEN_ISA *isa = & m32c_cgen_isa_table[i];
62788
62789         /* Default insn sizes of all selected isas must be
62790            equal or we set the result to 0, meaning "unknown".  */
62791         if (cd->default_insn_bitsize == UNSET)
62792           cd->default_insn_bitsize = isa->default_insn_bitsize;
62793         else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
62794           ; /* This is ok.  */
62795         else
62796           cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
62797
62798         /* Base insn sizes of all selected isas must be equal
62799            or we set the result to 0, meaning "unknown".  */
62800         if (cd->base_insn_bitsize == UNSET)
62801           cd->base_insn_bitsize = isa->base_insn_bitsize;
62802         else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
62803           ; /* This is ok.  */
62804         else
62805           cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
62806
62807         /* Set min,max insn sizes.  */
62808         if (isa->min_insn_bitsize < cd->min_insn_bitsize)
62809           cd->min_insn_bitsize = isa->min_insn_bitsize;
62810         if (isa->max_insn_bitsize > cd->max_insn_bitsize)
62811           cd->max_insn_bitsize = isa->max_insn_bitsize;
62812       }
62813
62814   /* Data derived from the mach spec.  */
62815   for (i = 0; i < MAX_MACHS; ++i)
62816     if (((1 << i) & machs) != 0)
62817       {
62818         const CGEN_MACH *mach = & m32c_cgen_mach_table[i];
62819
62820         if (mach->insn_chunk_bitsize != 0)
62821         {
62822           if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
62823             {
62824               fprintf (stderr, "m32c_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
62825                        cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
62826               abort ();
62827             }
62828
62829           cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
62830         }
62831       }
62832
62833   /* Determine which hw elements are used by MACH.  */
62834   build_hw_table (cd);
62835
62836   /* Build the ifield table.  */
62837   build_ifield_table (cd);
62838
62839   /* Determine which operands are used by MACH/ISA.  */
62840   build_operand_table (cd);
62841
62842   /* Build the instruction table.  */
62843   build_insn_table (cd);
62844 }
62845
62846 /* Initialize a cpu table and return a descriptor.
62847    It's much like opening a file, and must be the first function called.
62848    The arguments are a set of (type/value) pairs, terminated with
62849    CGEN_CPU_OPEN_END.
62850
62851    Currently supported values:
62852    CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
62853    CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
62854    CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
62855    CGEN_CPU_OPEN_ENDIAN:  specify endian choice
62856    CGEN_CPU_OPEN_END:     terminates arguments
62857
62858    ??? Simultaneous multiple isas might not make sense, but it's not (yet)
62859    precluded.
62860
62861    ??? We only support ISO C stdargs here, not K&R.
62862    Laziness, plus experiment to see if anything requires K&R - eventually
62863    K&R will no longer be supported - e.g. GDB is currently trying this.  */
62864
62865 CGEN_CPU_DESC
62866 m32c_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
62867 {
62868   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
62869   static int init_p;
62870   unsigned int isas = 0;  /* 0 = "unspecified" */
62871   unsigned int machs = 0; /* 0 = "unspecified" */
62872   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
62873   va_list ap;
62874
62875   if (! init_p)
62876     {
62877       init_tables ();
62878       init_p = 1;
62879     }
62880
62881   memset (cd, 0, sizeof (*cd));
62882
62883   va_start (ap, arg_type);
62884   while (arg_type != CGEN_CPU_OPEN_END)
62885     {
62886       switch (arg_type)
62887         {
62888         case CGEN_CPU_OPEN_ISAS :
62889           isas = va_arg (ap, unsigned int);
62890           break;
62891         case CGEN_CPU_OPEN_MACHS :
62892           machs = va_arg (ap, unsigned int);
62893           break;
62894         case CGEN_CPU_OPEN_BFDMACH :
62895           {
62896             const char *name = va_arg (ap, const char *);
62897             const CGEN_MACH *mach =
62898               lookup_mach_via_bfd_name (m32c_cgen_mach_table, name);
62899
62900             machs |= 1 << mach->num;
62901             break;
62902           }
62903         case CGEN_CPU_OPEN_ENDIAN :
62904           endian = va_arg (ap, enum cgen_endian);
62905           break;
62906         default :
62907           fprintf (stderr, "m32c_cgen_cpu_open: unsupported argument `%d'\n",
62908                    arg_type);
62909           abort (); /* ??? return NULL? */
62910         }
62911       arg_type = va_arg (ap, enum cgen_cpu_open_arg);
62912     }
62913   va_end (ap);
62914
62915   /* Mach unspecified means "all".  */
62916   if (machs == 0)
62917     machs = (1 << MAX_MACHS) - 1;
62918   /* Base mach is always selected.  */
62919   machs |= 1;
62920   /* ISA unspecified means "all".  */
62921   if (isas == 0)
62922     isas = (1 << MAX_ISAS) - 1;
62923   if (endian == CGEN_ENDIAN_UNKNOWN)
62924     {
62925       /* ??? If target has only one, could have a default.  */
62926       fprintf (stderr, "m32c_cgen_cpu_open: no endianness specified\n");
62927       abort ();
62928     }
62929
62930   cd->isas = isas;
62931   cd->machs = machs;
62932   cd->endian = endian;
62933   /* FIXME: for the sparc case we can determine insn-endianness statically.
62934      The worry here is where both data and insn endian can be independently
62935      chosen, in which case this function will need another argument.
62936      Actually, will want to allow for more arguments in the future anyway.  */
62937   cd->insn_endian = endian;
62938
62939   /* Table (re)builder.  */
62940   cd->rebuild_tables = m32c_cgen_rebuild_tables;
62941   m32c_cgen_rebuild_tables (cd);
62942
62943   /* Default to not allowing signed overflow.  */
62944   cd->signed_overflow_ok_p = 0;
62945
62946   return (CGEN_CPU_DESC) cd;
62947 }
62948
62949 /* Cover fn to m32c_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
62950    MACH_NAME is the bfd name of the mach.  */
62951
62952 CGEN_CPU_DESC
62953 m32c_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
62954 {
62955   return m32c_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
62956                                CGEN_CPU_OPEN_ENDIAN, endian,
62957                                CGEN_CPU_OPEN_END);
62958 }
62959
62960 /* Close a cpu table.
62961    ??? This can live in a machine independent file, but there's currently
62962    no place to put this file (there's no libcgen).  libopcodes is the wrong
62963    place as some simulator ports use this but they don't use libopcodes.  */
62964
62965 void
62966 m32c_cgen_cpu_close (CGEN_CPU_DESC cd)
62967 {
62968   unsigned int i;
62969   const CGEN_INSN *insns;
62970
62971   if (cd->macro_insn_table.init_entries)
62972     {
62973       insns = cd->macro_insn_table.init_entries;
62974       for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
62975         if (CGEN_INSN_RX ((insns)))
62976           regfree (CGEN_INSN_RX (insns));
62977     }
62978
62979   if (cd->insn_table.init_entries)
62980     {
62981       insns = cd->insn_table.init_entries;
62982       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
62983         if (CGEN_INSN_RX (insns))
62984           regfree (CGEN_INSN_RX (insns));
62985     }
62986
62987   if (cd->macro_insn_table.init_entries)
62988     free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
62989
62990   if (cd->insn_table.init_entries)
62991     free ((CGEN_INSN *) cd->insn_table.init_entries);
62992
62993   if (cd->hw_table.entries)
62994     free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
62995
62996   if (cd->operand_table.entries)
62997     free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
62998
62999   free (cd);
63000 }
63001