3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright 1996-2005 Free Software Foundation, Inc.
7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
31 #include "m32c-desc.h"
34 #include "libiberty.h"
39 static const CGEN_ATTR_ENTRY bool_attr[] =
46 static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
48 { "base", MACH_BASE },
49 { "m16c", MACH_M16C },
50 { "m32c", MACH_M32C },
55 static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
63 const CGEN_ATTR_TABLE m32c_cgen_ifield_attr_table[] =
65 { "MACH", & MACH_attr[0], & MACH_attr[0] },
66 { "ISA", & ISA_attr[0], & ISA_attr[0] },
67 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
68 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
69 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
70 { "RESERVED", &bool_attr[0], &bool_attr[0] },
71 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
72 { "SIGNED", &bool_attr[0], &bool_attr[0] },
76 const CGEN_ATTR_TABLE m32c_cgen_hardware_attr_table[] =
78 { "MACH", & MACH_attr[0], & MACH_attr[0] },
79 { "ISA", & ISA_attr[0], & ISA_attr[0] },
80 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
81 { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
82 { "PC", &bool_attr[0], &bool_attr[0] },
83 { "PROFILE", &bool_attr[0], &bool_attr[0] },
87 const CGEN_ATTR_TABLE m32c_cgen_operand_attr_table[] =
89 { "MACH", & MACH_attr[0], & MACH_attr[0] },
90 { "ISA", & ISA_attr[0], & ISA_attr[0] },
91 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
92 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
93 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
94 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
95 { "SIGNED", &bool_attr[0], &bool_attr[0] },
96 { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
97 { "RELAX", &bool_attr[0], &bool_attr[0] },
98 { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
102 const CGEN_ATTR_TABLE m32c_cgen_insn_attr_table[] =
104 { "MACH", & MACH_attr[0], & MACH_attr[0] },
105 { "ISA", & ISA_attr[0], & ISA_attr[0] },
106 { "ALIAS", &bool_attr[0], &bool_attr[0] },
107 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
108 { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
109 { "COND-CTI", &bool_attr[0], &bool_attr[0] },
110 { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
111 { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
112 { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
113 { "RELAXED", &bool_attr[0], &bool_attr[0] },
114 { "NO-DIS", &bool_attr[0], &bool_attr[0] },
115 { "PBB", &bool_attr[0], &bool_attr[0] },
119 /* Instruction set variants. */
121 static const CGEN_ISA m32c_cgen_isa_table[] = {
122 { "m16c", 32, 32, 8, 56 },
123 { "m32c", 32, 32, 8, 80 },
127 /* Machine variants. */
129 static const CGEN_MACH m32c_cgen_mach_table[] = {
130 { "m16c", "m16c", MACH_M16C, 0 },
131 { "m32c", "m32c", MACH_M32C, 0 },
135 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_entries[] =
137 { "r0", 0, {0, {0}}, 0, 0 },
138 { "r1", 1, {0, {0}}, 0, 0 },
139 { "r2", 2, {0, {0}}, 0, 0 },
140 { "r3", 3, {0, {0}}, 0, 0 }
143 CGEN_KEYWORD m32c_cgen_opval_h_gr =
145 & m32c_cgen_opval_h_gr_entries[0],
150 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_QI_entries[] =
152 { "r0l", 0, {0, {0}}, 0, 0 },
153 { "r0h", 1, {0, {0}}, 0, 0 },
154 { "r1l", 2, {0, {0}}, 0, 0 },
155 { "r1h", 3, {0, {0}}, 0, 0 }
158 CGEN_KEYWORD m32c_cgen_opval_h_gr_QI =
160 & m32c_cgen_opval_h_gr_QI_entries[0],
165 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_HI_entries[] =
167 { "r0", 0, {0, {0}}, 0, 0 },
168 { "r1", 1, {0, {0}}, 0, 0 },
169 { "r2", 2, {0, {0}}, 0, 0 },
170 { "r3", 3, {0, {0}}, 0, 0 }
173 CGEN_KEYWORD m32c_cgen_opval_h_gr_HI =
175 & m32c_cgen_opval_h_gr_HI_entries[0],
180 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_SI_entries[] =
182 { "r2r0", 0, {0, {0}}, 0, 0 },
183 { "r3r1", 1, {0, {0}}, 0, 0 }
186 CGEN_KEYWORD m32c_cgen_opval_h_gr_SI =
188 & m32c_cgen_opval_h_gr_SI_entries[0],
193 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_ext_QI_entries[] =
195 { "r0l", 0, {0, {0}}, 0, 0 },
196 { "r1l", 1, {0, {0}}, 0, 0 }
199 CGEN_KEYWORD m32c_cgen_opval_h_gr_ext_QI =
201 & m32c_cgen_opval_h_gr_ext_QI_entries[0],
206 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_gr_ext_HI_entries[] =
208 { "r0", 0, {0, {0}}, 0, 0 },
209 { "r1", 1, {0, {0}}, 0, 0 }
212 CGEN_KEYWORD m32c_cgen_opval_h_gr_ext_HI =
214 & m32c_cgen_opval_h_gr_ext_HI_entries[0],
219 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0l_entries[] =
221 { "r0l", 0, {0, {0}}, 0, 0 }
224 CGEN_KEYWORD m32c_cgen_opval_h_r0l =
226 & m32c_cgen_opval_h_r0l_entries[0],
231 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0h_entries[] =
233 { "r0h", 0, {0, {0}}, 0, 0 }
236 CGEN_KEYWORD m32c_cgen_opval_h_r0h =
238 & m32c_cgen_opval_h_r0h_entries[0],
243 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1l_entries[] =
245 { "r1l", 0, {0, {0}}, 0, 0 }
248 CGEN_KEYWORD m32c_cgen_opval_h_r1l =
250 & m32c_cgen_opval_h_r1l_entries[0],
255 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1h_entries[] =
257 { "r1h", 0, {0, {0}}, 0, 0 }
260 CGEN_KEYWORD m32c_cgen_opval_h_r1h =
262 & m32c_cgen_opval_h_r1h_entries[0],
267 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0_entries[] =
269 { "r0", 0, {0, {0}}, 0, 0 }
272 CGEN_KEYWORD m32c_cgen_opval_h_r0 =
274 & m32c_cgen_opval_h_r0_entries[0],
279 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1_entries[] =
281 { "r1", 0, {0, {0}}, 0, 0 }
284 CGEN_KEYWORD m32c_cgen_opval_h_r1 =
286 & m32c_cgen_opval_h_r1_entries[0],
291 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r2_entries[] =
293 { "r2", 0, {0, {0}}, 0, 0 }
296 CGEN_KEYWORD m32c_cgen_opval_h_r2 =
298 & m32c_cgen_opval_h_r2_entries[0],
303 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r3_entries[] =
305 { "r3", 0, {0, {0}}, 0, 0 }
308 CGEN_KEYWORD m32c_cgen_opval_h_r3 =
310 & m32c_cgen_opval_h_r3_entries[0],
315 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r0l_r0h_entries[] =
317 { "r0l", 0, {0, {0}}, 0, 0 },
318 { "r0h", 1, {0, {0}}, 0, 0 }
321 CGEN_KEYWORD m32c_cgen_opval_h_r0l_r0h =
323 & m32c_cgen_opval_h_r0l_r0h_entries[0],
328 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r2r0_entries[] =
330 { "r2r0", 0, {0, {0}}, 0, 0 }
333 CGEN_KEYWORD m32c_cgen_opval_h_r2r0 =
335 & m32c_cgen_opval_h_r2r0_entries[0],
340 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r3r1_entries[] =
342 { "r3r1", 0, {0, {0}}, 0, 0 }
345 CGEN_KEYWORD m32c_cgen_opval_h_r3r1 =
347 & m32c_cgen_opval_h_r3r1_entries[0],
352 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_r1r2r0_entries[] =
354 { "r1r2r0", 0, {0, {0}}, 0, 0 }
357 CGEN_KEYWORD m32c_cgen_opval_h_r1r2r0 =
359 & m32c_cgen_opval_h_r1r2r0_entries[0],
364 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_entries[] =
366 { "a0", 0, {0, {0}}, 0, 0 },
367 { "a1", 1, {0, {0}}, 0, 0 }
370 CGEN_KEYWORD m32c_cgen_opval_h_ar =
372 & m32c_cgen_opval_h_ar_entries[0],
377 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_QI_entries[] =
379 { "a0", 0, {0, {0}}, 0, 0 },
380 { "a1", 1, {0, {0}}, 0, 0 }
383 CGEN_KEYWORD m32c_cgen_opval_h_ar_QI =
385 & m32c_cgen_opval_h_ar_QI_entries[0],
390 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_HI_entries[] =
392 { "a0", 0, {0, {0}}, 0, 0 },
393 { "a1", 1, {0, {0}}, 0, 0 }
396 CGEN_KEYWORD m32c_cgen_opval_h_ar_HI =
398 & m32c_cgen_opval_h_ar_HI_entries[0],
403 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_ar_SI_entries[] =
405 { "a1a0", 0, {0, {0}}, 0, 0 }
408 CGEN_KEYWORD m32c_cgen_opval_h_ar_SI =
410 & m32c_cgen_opval_h_ar_SI_entries[0],
415 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_a0_entries[] =
417 { "a0", 0, {0, {0}}, 0, 0 }
420 CGEN_KEYWORD m32c_cgen_opval_h_a0 =
422 & m32c_cgen_opval_h_a0_entries[0],
427 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_a1_entries[] =
429 { "a1", 1, {0, {0}}, 0, 0 }
432 CGEN_KEYWORD m32c_cgen_opval_h_a1 =
434 & m32c_cgen_opval_h_a1_entries[0],
439 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16_entries[] =
441 { "geu", 0, {0, {0}}, 0, 0 },
442 { "c", 0, {0, {0}}, 0, 0 },
443 { "gtu", 1, {0, {0}}, 0, 0 },
444 { "eq", 2, {0, {0}}, 0, 0 },
445 { "z", 2, {0, {0}}, 0, 0 },
446 { "n", 3, {0, {0}}, 0, 0 },
447 { "le", 4, {0, {0}}, 0, 0 },
448 { "o", 5, {0, {0}}, 0, 0 },
449 { "ge", 6, {0, {0}}, 0, 0 },
450 { "ltu", 248, {0, {0}}, 0, 0 },
451 { "nc", 248, {0, {0}}, 0, 0 },
452 { "leu", 249, {0, {0}}, 0, 0 },
453 { "ne", 250, {0, {0}}, 0, 0 },
454 { "nz", 250, {0, {0}}, 0, 0 },
455 { "pz", 251, {0, {0}}, 0, 0 },
456 { "gt", 252, {0, {0}}, 0, 0 },
457 { "no", 253, {0, {0}}, 0, 0 },
458 { "lt", 254, {0, {0}}, 0, 0 }
461 CGEN_KEYWORD m32c_cgen_opval_h_cond16 =
463 & m32c_cgen_opval_h_cond16_entries[0],
468 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16c_entries[] =
470 { "geu", 0, {0, {0}}, 0, 0 },
471 { "c", 0, {0, {0}}, 0, 0 },
472 { "gtu", 1, {0, {0}}, 0, 0 },
473 { "eq", 2, {0, {0}}, 0, 0 },
474 { "z", 2, {0, {0}}, 0, 0 },
475 { "n", 3, {0, {0}}, 0, 0 },
476 { "ltu", 4, {0, {0}}, 0, 0 },
477 { "nc", 4, {0, {0}}, 0, 0 },
478 { "leu", 5, {0, {0}}, 0, 0 },
479 { "ne", 6, {0, {0}}, 0, 0 },
480 { "nz", 6, {0, {0}}, 0, 0 },
481 { "pz", 7, {0, {0}}, 0, 0 },
482 { "le", 8, {0, {0}}, 0, 0 },
483 { "o", 9, {0, {0}}, 0, 0 },
484 { "ge", 10, {0, {0}}, 0, 0 },
485 { "gt", 12, {0, {0}}, 0, 0 },
486 { "no", 13, {0, {0}}, 0, 0 },
487 { "lt", 14, {0, {0}}, 0, 0 }
490 CGEN_KEYWORD m32c_cgen_opval_h_cond16c =
492 & m32c_cgen_opval_h_cond16c_entries[0],
497 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16j_entries[] =
499 { "le", 8, {0, {0}}, 0, 0 },
500 { "o", 9, {0, {0}}, 0, 0 },
501 { "ge", 10, {0, {0}}, 0, 0 },
502 { "gt", 12, {0, {0}}, 0, 0 },
503 { "no", 13, {0, {0}}, 0, 0 },
504 { "lt", 14, {0, {0}}, 0, 0 }
507 CGEN_KEYWORD m32c_cgen_opval_h_cond16j =
509 & m32c_cgen_opval_h_cond16j_entries[0],
514 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond16j_5_entries[] =
516 { "geu", 0, {0, {0}}, 0, 0 },
517 { "c", 0, {0, {0}}, 0, 0 },
518 { "gtu", 1, {0, {0}}, 0, 0 },
519 { "eq", 2, {0, {0}}, 0, 0 },
520 { "z", 2, {0, {0}}, 0, 0 },
521 { "n", 3, {0, {0}}, 0, 0 },
522 { "ltu", 4, {0, {0}}, 0, 0 },
523 { "nc", 4, {0, {0}}, 0, 0 },
524 { "leu", 5, {0, {0}}, 0, 0 },
525 { "ne", 6, {0, {0}}, 0, 0 },
526 { "nz", 6, {0, {0}}, 0, 0 },
527 { "pz", 7, {0, {0}}, 0, 0 }
530 CGEN_KEYWORD m32c_cgen_opval_h_cond16j_5 =
532 & m32c_cgen_opval_h_cond16j_5_entries[0],
537 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cond32_entries[] =
539 { "ltu", 0, {0, {0}}, 0, 0 },
540 { "nc", 0, {0, {0}}, 0, 0 },
541 { "leu", 1, {0, {0}}, 0, 0 },
542 { "ne", 2, {0, {0}}, 0, 0 },
543 { "nz", 2, {0, {0}}, 0, 0 },
544 { "pz", 3, {0, {0}}, 0, 0 },
545 { "no", 4, {0, {0}}, 0, 0 },
546 { "gt", 5, {0, {0}}, 0, 0 },
547 { "ge", 6, {0, {0}}, 0, 0 },
548 { "geu", 8, {0, {0}}, 0, 0 },
549 { "c", 8, {0, {0}}, 0, 0 },
550 { "gtu", 9, {0, {0}}, 0, 0 },
551 { "eq", 10, {0, {0}}, 0, 0 },
552 { "z", 10, {0, {0}}, 0, 0 },
553 { "n", 11, {0, {0}}, 0, 0 },
554 { "o", 12, {0, {0}}, 0, 0 },
555 { "le", 13, {0, {0}}, 0, 0 },
556 { "lt", 14, {0, {0}}, 0, 0 }
559 CGEN_KEYWORD m32c_cgen_opval_h_cond32 =
561 & m32c_cgen_opval_h_cond32_entries[0],
566 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr1_32_entries[] =
568 { "dct0", 0, {0, {0}}, 0, 0 },
569 { "dct1", 1, {0, {0}}, 0, 0 },
570 { "flg", 2, {0, {0}}, 0, 0 },
571 { "svf", 3, {0, {0}}, 0, 0 },
572 { "drc0", 4, {0, {0}}, 0, 0 },
573 { "drc1", 5, {0, {0}}, 0, 0 },
574 { "dmd0", 6, {0, {0}}, 0, 0 },
575 { "dmd1", 7, {0, {0}}, 0, 0 }
578 CGEN_KEYWORD m32c_cgen_opval_h_cr1_32 =
580 & m32c_cgen_opval_h_cr1_32_entries[0],
585 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr2_32_entries[] =
587 { "intb", 0, {0, {0}}, 0, 0 },
588 { "sp", 1, {0, {0}}, 0, 0 },
589 { "sb", 2, {0, {0}}, 0, 0 },
590 { "fb", 3, {0, {0}}, 0, 0 },
591 { "svp", 4, {0, {0}}, 0, 0 },
592 { "vct", 5, {0, {0}}, 0, 0 },
593 { "isp", 7, {0, {0}}, 0, 0 }
596 CGEN_KEYWORD m32c_cgen_opval_h_cr2_32 =
598 & m32c_cgen_opval_h_cr2_32_entries[0],
603 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr3_32_entries[] =
605 { "dma0", 2, {0, {0}}, 0, 0 },
606 { "dma1", 3, {0, {0}}, 0, 0 },
607 { "dra0", 4, {0, {0}}, 0, 0 },
608 { "dra1", 5, {0, {0}}, 0, 0 },
609 { "dsa0", 6, {0, {0}}, 0, 0 },
610 { "dsa1", 7, {0, {0}}, 0, 0 }
613 CGEN_KEYWORD m32c_cgen_opval_h_cr3_32 =
615 & m32c_cgen_opval_h_cr3_32_entries[0],
620 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_cr_16_entries[] =
622 { "intbl", 1, {0, {0}}, 0, 0 },
623 { "intbh", 2, {0, {0}}, 0, 0 },
624 { "flg", 3, {0, {0}}, 0, 0 },
625 { "isp", 4, {0, {0}}, 0, 0 },
626 { "sp", 5, {0, {0}}, 0, 0 },
627 { "sb", 6, {0, {0}}, 0, 0 },
628 { "fb", 7, {0, {0}}, 0, 0 }
631 CGEN_KEYWORD m32c_cgen_opval_h_cr_16 =
633 & m32c_cgen_opval_h_cr_16_entries[0],
638 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_flags_entries[] =
640 { "c", 0, {0, {0}}, 0, 0 },
641 { "d", 1, {0, {0}}, 0, 0 },
642 { "z", 2, {0, {0}}, 0, 0 },
643 { "s", 3, {0, {0}}, 0, 0 },
644 { "b", 4, {0, {0}}, 0, 0 },
645 { "o", 5, {0, {0}}, 0, 0 },
646 { "i", 6, {0, {0}}, 0, 0 },
647 { "u", 7, {0, {0}}, 0, 0 }
650 CGEN_KEYWORD m32c_cgen_opval_h_flags =
652 & m32c_cgen_opval_h_flags_entries[0],
657 static CGEN_KEYWORD_ENTRY m32c_cgen_opval_h_shimm_entries[] =
659 { "1", 0, {0, {0}}, 0, 0 },
660 { "2", 1, {0, {0}}, 0, 0 },
661 { "3", 2, {0, {0}}, 0, 0 },
662 { "4", 3, {0, {0}}, 0, 0 },
663 { "5", 4, {0, {0}}, 0, 0 },
664 { "6", 5, {0, {0}}, 0, 0 },
665 { "7", 6, {0, {0}}, 0, 0 },
666 { "8", 7, {0, {0}}, 0, 0 },
667 { "-1", -8, {0, {0}}, 0, 0 },
668 { "-2", -7, {0, {0}}, 0, 0 },
669 { "-3", -6, {0, {0}}, 0, 0 },
670 { "-4", -5, {0, {0}}, 0, 0 },
671 { "-5", -4, {0, {0}}, 0, 0 },
672 { "-6", -3, {0, {0}}, 0, 0 },
673 { "-7", -2, {0, {0}}, 0, 0 },
674 { "-8", -1, {0, {0}}, 0, 0 }
677 CGEN_KEYWORD m32c_cgen_opval_h_shimm =
679 & m32c_cgen_opval_h_shimm_entries[0],
685 /* The hardware table. */
687 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
688 #define A(a) (1 << CGEN_HW_##a)
690 #define A(a) (1 << CGEN_HW_/**/a)
693 const CGEN_HW_ENTRY m32c_cgen_hw_table[] =
695 { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
696 { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
697 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
698 { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
699 { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
700 { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
701 { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr, { 0|A(CACHE_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
702 { "h-gr-QI", HW_H_GR_QI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_QI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
703 { "h-gr-HI", HW_H_GR_HI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_HI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
704 { "h-gr-SI", HW_H_GR_SI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_SI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
705 { "h-gr-ext-QI", HW_H_GR_EXT_QI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_ext_QI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
706 { "h-gr-ext-HI", HW_H_GR_EXT_HI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_gr_ext_HI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
707 { "h-r0l", HW_H_R0L, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r0l, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
708 { "h-r0h", HW_H_R0H, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r0h, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
709 { "h-r1l", HW_H_R1L, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r1l, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
710 { "h-r1h", HW_H_R1H, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r1h, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
711 { "h-r0", HW_H_R0, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r0, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
712 { "h-r1", HW_H_R1, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r1, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
713 { "h-r2", HW_H_R2, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r2, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
714 { "h-r3", HW_H_R3, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r3, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
715 { "h-r0l-r0h", HW_H_R0L_R0H, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r0l_r0h, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
716 { "h-r2r0", HW_H_R2R0, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r2r0, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
717 { "h-r3r1", HW_H_R3R1, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r3r1, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
718 { "h-r1r2r0", HW_H_R1R2R0, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_r1r2r0, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
719 { "h-ar", HW_H_AR, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_ar, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
720 { "h-ar-QI", HW_H_AR_QI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_ar_QI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
721 { "h-ar-HI", HW_H_AR_HI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_ar_HI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
722 { "h-ar-SI", HW_H_AR_SI, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_ar_SI, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
723 { "h-a0", HW_H_A0, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_a0, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
724 { "h-a1", HW_H_A1, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_a1, { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
725 { "h-sb", HW_H_SB, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
726 { "h-fb", HW_H_FB, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
727 { "h-sp", HW_H_SP, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
728 { "h-sbit", HW_H_SBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
729 { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
730 { "h-obit", HW_H_OBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
731 { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
732 { "h-ubit", HW_H_UBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
733 { "h-ibit", HW_H_IBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
734 { "h-bbit", HW_H_BBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
735 { "h-dbit", HW_H_DBIT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
736 { "h-dct0", HW_H_DCT0, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
737 { "h-dct1", HW_H_DCT1, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
738 { "h-svf", HW_H_SVF, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
739 { "h-drc0", HW_H_DRC0, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
740 { "h-drc1", HW_H_DRC1, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
741 { "h-dmd0", HW_H_DMD0, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
742 { "h-dmd1", HW_H_DMD1, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
743 { "h-intb", HW_H_INTB, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
744 { "h-svp", HW_H_SVP, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
745 { "h-vct", HW_H_VCT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
746 { "h-isp", HW_H_ISP, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
747 { "h-dma0", HW_H_DMA0, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
748 { "h-dma1", HW_H_DMA1, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
749 { "h-dra0", HW_H_DRA0, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
750 { "h-dra1", HW_H_DRA1, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
751 { "h-dsa0", HW_H_DSA0, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
752 { "h-dsa1", HW_H_DSA1, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
753 { "h-cond16", HW_H_COND16, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond16, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
754 { "h-cond16c", HW_H_COND16C, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond16c, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
755 { "h-cond16j", HW_H_COND16J, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond16j, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
756 { "h-cond16j-5", HW_H_COND16J_5, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond16j_5, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
757 { "h-cond32", HW_H_COND32, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cond32, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
758 { "h-cr1-32", HW_H_CR1_32, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cr1_32, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
759 { "h-cr2-32", HW_H_CR2_32, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cr2_32, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
760 { "h-cr3-32", HW_H_CR3_32, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cr3_32, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
761 { "h-cr-16", HW_H_CR_16, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_cr_16, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
762 { "h-flags", HW_H_FLAGS, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_flags, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
763 { "h-shimm", HW_H_SHIMM, CGEN_ASM_KEYWORD, (PTR) & m32c_cgen_opval_h_shimm, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
764 { "h-bit-index", HW_H_BIT_INDEX, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
765 { "h-src-index", HW_H_SRC_INDEX, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
766 { "h-dst-index", HW_H_DST_INDEX, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
767 { "h-src-indirect", HW_H_SRC_INDIRECT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
768 { "h-dst-indirect", HW_H_DST_INDIRECT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
769 { "h-none", HW_H_NONE, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
770 { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
776 /* The instruction field table. */
778 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
779 #define A(a) (1 << CGEN_IFLD_##a)
781 #define A(a) (1 << CGEN_IFLD_/**/a)
784 const CGEN_IFLD m32c_cgen_ifld_table[] =
786 { M32C_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } },
787 { M32C_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } },
788 { M32C_F_0_1, "f-0-1", 0, 32, 0, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
789 { M32C_F_0_2, "f-0-2", 0, 32, 0, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
790 { M32C_F_0_3, "f-0-3", 0, 32, 0, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
791 { M32C_F_0_4, "f-0-4", 0, 32, 0, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
792 { M32C_F_1_3, "f-1-3", 0, 32, 1, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
793 { M32C_F_2_2, "f-2-2", 0, 32, 2, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
794 { M32C_F_3_4, "f-3-4", 0, 32, 3, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
795 { M32C_F_3_1, "f-3-1", 0, 32, 3, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
796 { M32C_F_4_1, "f-4-1", 0, 32, 4, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
797 { M32C_F_4_3, "f-4-3", 0, 32, 4, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
798 { M32C_F_4_4, "f-4-4", 0, 32, 4, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
799 { M32C_F_4_6, "f-4-6", 0, 32, 4, 6, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
800 { M32C_F_5_1, "f-5-1", 0, 32, 5, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
801 { M32C_F_5_3, "f-5-3", 0, 32, 5, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
802 { M32C_F_6_2, "f-6-2", 0, 32, 6, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
803 { M32C_F_7_1, "f-7-1", 0, 32, 7, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
804 { M32C_F_8_1, "f-8-1", 0, 32, 8, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
805 { M32C_F_8_2, "f-8-2", 0, 32, 8, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
806 { M32C_F_8_3, "f-8-3", 0, 32, 8, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
807 { M32C_F_8_4, "f-8-4", 0, 32, 8, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
808 { M32C_F_8_8, "f-8-8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
809 { M32C_F_9_3, "f-9-3", 0, 32, 9, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
810 { M32C_F_9_1, "f-9-1", 0, 32, 9, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
811 { M32C_F_10_1, "f-10-1", 0, 32, 10, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
812 { M32C_F_10_2, "f-10-2", 0, 32, 10, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
813 { M32C_F_10_3, "f-10-3", 0, 32, 10, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
814 { M32C_F_11_1, "f-11-1", 0, 32, 11, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
815 { M32C_F_12_1, "f-12-1", 0, 32, 12, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
816 { M32C_F_12_2, "f-12-2", 0, 32, 12, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
817 { M32C_F_12_3, "f-12-3", 0, 32, 12, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
818 { M32C_F_12_4, "f-12-4", 0, 32, 12, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
819 { M32C_F_12_6, "f-12-6", 0, 32, 12, 6, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
820 { M32C_F_13_3, "f-13-3", 0, 32, 13, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
821 { M32C_F_14_1, "f-14-1", 0, 32, 14, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
822 { M32C_F_14_2, "f-14-2", 0, 32, 14, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
823 { M32C_F_15_1, "f-15-1", 0, 32, 15, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
824 { M32C_F_16_1, "f-16-1", 0, 32, 16, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
825 { M32C_F_16_2, "f-16-2", 0, 32, 16, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
826 { M32C_F_16_4, "f-16-4", 0, 32, 16, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
827 { M32C_F_18_1, "f-18-1", 0, 32, 18, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
828 { M32C_F_18_2, "f-18-2", 0, 32, 18, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
829 { M32C_F_18_3, "f-18-3", 0, 32, 18, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
830 { M32C_F_20_1, "f-20-1", 0, 32, 20, 1, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
831 { M32C_F_20_3, "f-20-3", 0, 32, 20, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
832 { M32C_F_20_2, "f-20-2", 0, 32, 20, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
833 { M32C_F_20_4, "f-20-4", 0, 32, 20, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
834 { M32C_F_21_3, "f-21-3", 0, 32, 21, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
835 { M32C_F_24_2, "f-24-2", 0, 32, 24, 2, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
836 { M32C_F_SRC16_RN, "f-src16-rn", 0, 32, 10, 2, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
837 { M32C_F_SRC16_AN, "f-src16-an", 0, 32, 11, 1, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
838 { M32C_F_SRC32_AN_UNPREFIXED, "f-src32-an-unprefixed", 0, 32, 11, 1, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
839 { M32C_F_SRC32_AN_PREFIXED, "f-src32-an-prefixed", 0, 32, 19, 1, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
840 { M32C_F_SRC32_RN_UNPREFIXED_QI, "f-src32-rn-unprefixed-QI", 0, 32, 10, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
841 { M32C_F_SRC32_RN_PREFIXED_QI, "f-src32-rn-prefixed-QI", 0, 32, 18, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
842 { M32C_F_SRC32_RN_UNPREFIXED_HI, "f-src32-rn-unprefixed-HI", 0, 32, 10, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
843 { M32C_F_SRC32_RN_PREFIXED_HI, "f-src32-rn-prefixed-HI", 0, 32, 18, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
844 { M32C_F_SRC32_RN_UNPREFIXED_SI, "f-src32-rn-unprefixed-SI", 0, 32, 10, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
845 { M32C_F_SRC32_RN_PREFIXED_SI, "f-src32-rn-prefixed-SI", 0, 32, 18, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
846 { M32C_F_DST32_RN_EXT_UNPREFIXED, "f-dst32-rn-ext-unprefixed", 0, 32, 9, 1, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
847 { M32C_F_DST16_RN, "f-dst16-rn", 0, 32, 14, 2, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
848 { M32C_F_DST16_RN_EXT, "f-dst16-rn-ext", 0, 32, 14, 1, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
849 { M32C_F_DST16_RN_QI_S, "f-dst16-rn-QI-s", 0, 32, 5, 1, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
850 { M32C_F_DST16_AN, "f-dst16-an", 0, 32, 15, 1, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
851 { M32C_F_DST16_AN_S, "f-dst16-an-s", 0, 32, 4, 1, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
852 { M32C_F_DST32_AN_UNPREFIXED, "f-dst32-an-unprefixed", 0, 32, 9, 1, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
853 { M32C_F_DST32_AN_PREFIXED, "f-dst32-an-prefixed", 0, 32, 17, 1, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
854 { M32C_F_DST32_RN_UNPREFIXED_QI, "f-dst32-rn-unprefixed-QI", 0, 32, 8, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
855 { M32C_F_DST32_RN_PREFIXED_QI, "f-dst32-rn-prefixed-QI", 0, 32, 16, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
856 { M32C_F_DST32_RN_UNPREFIXED_HI, "f-dst32-rn-unprefixed-HI", 0, 32, 8, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
857 { M32C_F_DST32_RN_PREFIXED_HI, "f-dst32-rn-prefixed-HI", 0, 32, 16, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
858 { M32C_F_DST32_RN_UNPREFIXED_SI, "f-dst32-rn-unprefixed-SI", 0, 32, 8, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
859 { M32C_F_DST32_RN_PREFIXED_SI, "f-dst32-rn-prefixed-SI", 0, 32, 16, 2, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
860 { M32C_F_DST16_1_S, "f-dst16-1-S", 0, 32, 5, 1, { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
861 { M32C_F_IMM_8_S4, "f-imm-8-s4", 0, 32, 8, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
862 { M32C_F_IMM_12_S4, "f-imm-12-s4", 0, 32, 12, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
863 { M32C_F_IMM_13_U3, "f-imm-13-u3", 0, 32, 13, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
864 { M32C_F_IMM_20_S4, "f-imm-20-s4", 0, 32, 20, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
865 { M32C_F_IMM1_S, "f-imm1-S", 0, 32, 2, 1, { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
866 { M32C_F_IMM3_S, "f-imm3-S", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
867 { M32C_F_DSP_8_U6, "f-dsp-8-u6", 0, 32, 8, 6, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
868 { M32C_F_DSP_8_U8, "f-dsp-8-u8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
869 { M32C_F_DSP_8_S8, "f-dsp-8-s8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
870 { M32C_F_DSP_10_U6, "f-dsp-10-u6", 0, 32, 10, 6, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
871 { M32C_F_DSP_16_U8, "f-dsp-16-u8", 0, 32, 16, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
872 { M32C_F_DSP_16_S8, "f-dsp-16-s8", 0, 32, 16, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
873 { M32C_F_DSP_24_U8, "f-dsp-24-u8", 0, 32, 24, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
874 { M32C_F_DSP_24_S8, "f-dsp-24-s8", 0, 32, 24, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
875 { M32C_F_DSP_32_U8, "f-dsp-32-u8", 32, 32, 0, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
876 { M32C_F_DSP_32_S8, "f-dsp-32-s8", 32, 32, 0, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
877 { M32C_F_DSP_40_U8, "f-dsp-40-u8", 32, 32, 8, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
878 { M32C_F_DSP_40_S8, "f-dsp-40-s8", 32, 32, 8, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
879 { M32C_F_DSP_48_U8, "f-dsp-48-u8", 32, 32, 16, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
880 { M32C_F_DSP_48_S8, "f-dsp-48-s8", 32, 32, 16, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
881 { M32C_F_DSP_56_U8, "f-dsp-56-u8", 32, 32, 24, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
882 { M32C_F_DSP_56_S8, "f-dsp-56-s8", 32, 32, 24, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
883 { M32C_F_DSP_64_U8, "f-dsp-64-u8", 64, 32, 0, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
884 { M32C_F_DSP_64_S8, "f-dsp-64-s8", 64, 32, 0, 8, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
885 { M32C_F_DSP_8_U16, "f-dsp-8-u16", 0, 32, 8, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
886 { M32C_F_DSP_8_S16, "f-dsp-8-s16", 0, 32, 8, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
887 { M32C_F_DSP_16_U16, "f-dsp-16-u16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
888 { M32C_F_DSP_16_S16, "f-dsp-16-s16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
889 { M32C_F_DSP_24_U16, "f-dsp-24-u16", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
890 { M32C_F_DSP_24_S16, "f-dsp-24-s16", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
891 { M32C_F_DSP_32_U16, "f-dsp-32-u16", 32, 32, 0, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
892 { M32C_F_DSP_32_S16, "f-dsp-32-s16", 32, 32, 0, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
893 { M32C_F_DSP_40_U16, "f-dsp-40-u16", 32, 32, 8, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
894 { M32C_F_DSP_40_S16, "f-dsp-40-s16", 32, 32, 8, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
895 { M32C_F_DSP_48_U16, "f-dsp-48-u16", 32, 32, 16, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
896 { M32C_F_DSP_48_S16, "f-dsp-48-s16", 32, 32, 16, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
897 { M32C_F_DSP_64_U16, "f-dsp-64-u16", 64, 32, 0, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
898 { M32C_F_DSP_16_U24, "f-dsp-16-u24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
899 { M32C_F_DSP_24_U24, "f-dsp-24-u24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
900 { M32C_F_DSP_32_U24, "f-dsp-32-u24", 32, 32, 0, 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
901 { M32C_F_DSP_40_U24, "f-dsp-40-u24", 32, 32, 8, 24, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
902 { M32C_F_DSP_40_S32, "f-dsp-40-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
903 { M32C_F_DSP_48_U24, "f-dsp-48-u24", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
904 { M32C_F_DSP_16_S32, "f-dsp-16-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
905 { M32C_F_DSP_24_S32, "f-dsp-24-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
906 { M32C_F_DSP_32_S32, "f-dsp-32-s32", 32, 32, 0, 32, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
907 { M32C_F_DSP_48_U32, "f-dsp-48-u32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
908 { M32C_F_DSP_48_S32, "f-dsp-48-s32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
909 { M32C_F_DSP_56_S16, "f-dsp-56-s16", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
910 { M32C_F_DSP_64_S16, "f-dsp-64-s16", 64, 32, 0, 16, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
911 { M32C_F_BITNO16_S, "f-bitno16-S", 0, 32, 5, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
912 { M32C_F_BITNO32_PREFIXED, "f-bitno32-prefixed", 0, 32, 21, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
913 { M32C_F_BITNO32_UNPREFIXED, "f-bitno32-unprefixed", 0, 32, 13, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
914 { M32C_F_BITBASE16_U11_S, "f-bitbase16-u11-S", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
915 { M32C_F_BITBASE32_16_U11_UNPREFIXED, "f-bitbase32-16-u11-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
916 { M32C_F_BITBASE32_16_S11_UNPREFIXED, "f-bitbase32-16-s11-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
917 { M32C_F_BITBASE32_16_U19_UNPREFIXED, "f-bitbase32-16-u19-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
918 { M32C_F_BITBASE32_16_S19_UNPREFIXED, "f-bitbase32-16-s19-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
919 { M32C_F_BITBASE32_16_U27_UNPREFIXED, "f-bitbase32-16-u27-unprefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
920 { M32C_F_BITBASE32_24_U11_PREFIXED, "f-bitbase32-24-u11-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
921 { M32C_F_BITBASE32_24_S11_PREFIXED, "f-bitbase32-24-s11-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
922 { M32C_F_BITBASE32_24_U19_PREFIXED, "f-bitbase32-24-u19-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
923 { M32C_F_BITBASE32_24_S19_PREFIXED, "f-bitbase32-24-s19-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
924 { M32C_F_BITBASE32_24_U27_PREFIXED, "f-bitbase32-24-u27-prefixed", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
925 { M32C_F_LAB_5_3, "f-lab-5-3", 0, 32, 5, 3, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
926 { M32C_F_LAB32_JMP_S, "f-lab32-jmp-s", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
927 { M32C_F_LAB_8_8, "f-lab-8-8", 0, 32, 8, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
928 { M32C_F_LAB_8_16, "f-lab-8-16", 0, 32, 8, 16, { 0|A(SIGN_OPT)|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
929 { M32C_F_LAB_8_24, "f-lab-8-24", 0, 32, 8, 24, { 0|A(ABS_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
930 { M32C_F_LAB_16_8, "f-lab-16-8", 0, 32, 16, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
931 { M32C_F_LAB_24_8, "f-lab-24-8", 0, 32, 24, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
932 { M32C_F_LAB_32_8, "f-lab-32-8", 32, 32, 0, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
933 { M32C_F_LAB_40_8, "f-lab-40-8", 32, 32, 8, 8, { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
934 { M32C_F_COND16, "f-cond16", 0, 32, 12, 4, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
935 { M32C_F_COND16J_5, "f-cond16j-5", 0, 32, 5, 3, { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
936 { M32C_F_COND32, "f-cond32", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
937 { M32C_F_COND32J, "f-cond32j", 0, 0, 0, 0,{ 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
938 { 0, 0, 0, 0, 0, 0, {0, {0}} }
945 /* multi ifield declarations */
947 const CGEN_MAYBE_MULTI_IFLD M32C_F_IMM3_S_MULTI_IFIELD [];
948 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_U16_MULTI_IFIELD [];
949 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_S16_MULTI_IFIELD [];
950 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_16_U24_MULTI_IFIELD [];
951 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_U24_MULTI_IFIELD [];
952 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_40_S32_MULTI_IFIELD [];
953 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_U24_MULTI_IFIELD [];
954 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_16_S32_MULTI_IFIELD [];
955 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_S32_MULTI_IFIELD [];
956 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_U32_MULTI_IFIELD [];
957 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_S32_MULTI_IFIELD [];
958 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_56_S16_MULTI_IFIELD [];
959 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE16_U11_S_MULTI_IFIELD [];
960 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U11_UNPREFIXED_MULTI_IFIELD [];
961 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_S11_UNPREFIXED_MULTI_IFIELD [];
962 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U19_UNPREFIXED_MULTI_IFIELD [];
963 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_S19_UNPREFIXED_MULTI_IFIELD [];
964 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U27_UNPREFIXED_MULTI_IFIELD [];
965 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U11_PREFIXED_MULTI_IFIELD [];
966 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_S11_PREFIXED_MULTI_IFIELD [];
967 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U19_PREFIXED_MULTI_IFIELD [];
968 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_S19_PREFIXED_MULTI_IFIELD [];
969 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U27_PREFIXED_MULTI_IFIELD [];
970 const CGEN_MAYBE_MULTI_IFLD M32C_F_LAB32_JMP_S_MULTI_IFIELD [];
971 const CGEN_MAYBE_MULTI_IFLD M32C_F_COND32_MULTI_IFIELD [];
972 const CGEN_MAYBE_MULTI_IFLD M32C_F_COND32J_MULTI_IFIELD [];
975 /* multi ifield definitions */
977 const CGEN_MAYBE_MULTI_IFLD M32C_F_IMM3_S_MULTI_IFIELD [] =
979 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_2_2] } },
980 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_7_1] } },
981 { 0, { (const PTR) 0 } }
983 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_U16_MULTI_IFIELD [] =
985 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
986 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
987 { 0, { (const PTR) 0 } }
989 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_S16_MULTI_IFIELD [] =
991 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
992 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
993 { 0, { (const PTR) 0 } }
995 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_16_U24_MULTI_IFIELD [] =
997 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
998 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
999 { 0, { (const PTR) 0 } }
1001 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_U24_MULTI_IFIELD [] =
1003 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
1004 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U16] } },
1005 { 0, { (const PTR) 0 } }
1007 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_40_S32_MULTI_IFIELD [] =
1009 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U24] } },
1010 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_U8] } },
1011 { 0, { (const PTR) 0 } }
1013 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_U24_MULTI_IFIELD [] =
1015 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U16] } },
1016 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_U8] } },
1017 { 0, { (const PTR) 0 } }
1019 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_16_S32_MULTI_IFIELD [] =
1021 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
1022 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U16] } },
1023 { 0, { (const PTR) 0 } }
1025 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_24_S32_MULTI_IFIELD [] =
1027 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
1028 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U24] } },
1029 { 0, { (const PTR) 0 } }
1031 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_U32_MULTI_IFIELD [] =
1033 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U16] } },
1034 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_U16] } },
1035 { 0, { (const PTR) 0 } }
1037 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_48_S32_MULTI_IFIELD [] =
1039 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U16] } },
1040 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_U16] } },
1041 { 0, { (const PTR) 0 } }
1043 const CGEN_MAYBE_MULTI_IFLD M32C_F_DSP_56_S16_MULTI_IFIELD [] =
1045 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_56_U8] } },
1046 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_U8] } },
1047 { 0, { (const PTR) 0 } }
1049 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE16_U11_S_MULTI_IFIELD [] =
1051 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO16_S] } },
1052 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U8] } },
1053 { 0, { (const PTR) 0 } }
1055 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U11_UNPREFIXED_MULTI_IFIELD [] =
1057 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } },
1058 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
1059 { 0, { (const PTR) 0 } }
1061 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_S11_UNPREFIXED_MULTI_IFIELD [] =
1063 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } },
1064 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S8] } },
1065 { 0, { (const PTR) 0 } }
1067 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U19_UNPREFIXED_MULTI_IFIELD [] =
1069 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } },
1070 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
1071 { 0, { (const PTR) 0 } }
1073 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_S19_UNPREFIXED_MULTI_IFIELD [] =
1075 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } },
1076 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S16] } },
1077 { 0, { (const PTR) 0 } }
1079 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_16_U27_UNPREFIXED_MULTI_IFIELD [] =
1081 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } },
1082 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
1083 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
1084 { 0, { (const PTR) 0 } }
1086 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U11_PREFIXED_MULTI_IFIELD [] =
1088 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } },
1089 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
1090 { 0, { (const PTR) 0 } }
1092 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_S11_PREFIXED_MULTI_IFIELD [] =
1094 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } },
1095 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_S8] } },
1096 { 0, { (const PTR) 0 } }
1098 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U19_PREFIXED_MULTI_IFIELD [] =
1100 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } },
1101 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
1102 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
1103 { 0, { (const PTR) 0 } }
1105 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_S19_PREFIXED_MULTI_IFIELD [] =
1107 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } },
1108 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
1109 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S8] } },
1110 { 0, { (const PTR) 0 } }
1112 const CGEN_MAYBE_MULTI_IFLD M32C_F_BITBASE32_24_U27_PREFIXED_MULTI_IFIELD [] =
1114 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } },
1115 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
1116 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U16] } },
1117 { 0, { (const PTR) 0 } }
1119 const CGEN_MAYBE_MULTI_IFLD M32C_F_LAB32_JMP_S_MULTI_IFIELD [] =
1121 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_2_2] } },
1122 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_7_1] } },
1123 { 0, { (const PTR) 0 } }
1125 const CGEN_MAYBE_MULTI_IFLD M32C_F_COND32_MULTI_IFIELD [] =
1127 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_9_1] } },
1128 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } },
1129 { 0, { (const PTR) 0 } }
1131 const CGEN_MAYBE_MULTI_IFLD M32C_F_COND32J_MULTI_IFIELD [] =
1133 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_1_3] } },
1134 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_7_1] } },
1135 { 0, { (const PTR) 0 } }
1138 /* The operand table. */
1140 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1141 #define A(a) (1 << CGEN_OPERAND_##a)
1143 #define A(a) (1 << CGEN_OPERAND_/**/a)
1145 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
1146 #define OPERAND(op) M32C_OPERAND_##op
1148 #define OPERAND(op) M32C_OPERAND_/**/op
1151 const CGEN_OPERAND m32c_cgen_operand_table[] =
1153 /* pc: program counter */
1154 { "pc", M32C_OPERAND_PC, HW_H_PC, 0, 0,
1155 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_NIL] } },
1156 { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C) } } },
1157 /* Src16RnQI: general register QI view */
1158 { "Src16RnQI", M32C_OPERAND_SRC16RNQI, HW_H_GR_QI, 10, 2,
1159 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_RN] } },
1160 { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
1161 /* Src16RnHI: general register QH view */
1162 { "Src16RnHI", M32C_OPERAND_SRC16RNHI, HW_H_GR_HI, 10, 2,
1163 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_RN] } },
1164 { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
1165 /* Src32RnUnprefixedQI: general register QI view */
1166 { "Src32RnUnprefixedQI", M32C_OPERAND_SRC32RNUNPREFIXEDQI, HW_H_GR_QI, 10, 2,
1167 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_UNPREFIXED_QI] } },
1168 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1169 /* Src32RnUnprefixedHI: general register HI view */
1170 { "Src32RnUnprefixedHI", M32C_OPERAND_SRC32RNUNPREFIXEDHI, HW_H_GR_HI, 10, 2,
1171 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_UNPREFIXED_HI] } },
1172 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1173 /* Src32RnUnprefixedSI: general register SI view */
1174 { "Src32RnUnprefixedSI", M32C_OPERAND_SRC32RNUNPREFIXEDSI, HW_H_GR_SI, 10, 2,
1175 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_UNPREFIXED_SI] } },
1176 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1177 /* Src32RnPrefixedQI: general register QI view */
1178 { "Src32RnPrefixedQI", M32C_OPERAND_SRC32RNPREFIXEDQI, HW_H_GR_QI, 18, 2,
1179 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_PREFIXED_QI] } },
1180 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1181 /* Src32RnPrefixedHI: general register HI view */
1182 { "Src32RnPrefixedHI", M32C_OPERAND_SRC32RNPREFIXEDHI, HW_H_GR_HI, 18, 2,
1183 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_PREFIXED_HI] } },
1184 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1185 /* Src32RnPrefixedSI: general register SI view */
1186 { "Src32RnPrefixedSI", M32C_OPERAND_SRC32RNPREFIXEDSI, HW_H_GR_SI, 18, 2,
1187 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_RN_PREFIXED_SI] } },
1188 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1189 /* Src16An: address register */
1190 { "Src16An", M32C_OPERAND_SRC16AN, HW_H_AR, 11, 1,
1191 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_AN] } },
1192 { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
1193 /* Src16AnQI: address register QI view */
1194 { "Src16AnQI", M32C_OPERAND_SRC16ANQI, HW_H_AR_QI, 11, 1,
1195 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_AN] } },
1196 { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
1197 /* Src16AnHI: address register HI view */
1198 { "Src16AnHI", M32C_OPERAND_SRC16ANHI, HW_H_AR_HI, 11, 1,
1199 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC16_AN] } },
1200 { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
1201 /* Src32AnUnprefixed: address register */
1202 { "Src32AnUnprefixed", M32C_OPERAND_SRC32ANUNPREFIXED, HW_H_AR, 11, 1,
1203 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_UNPREFIXED] } },
1204 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1205 /* Src32AnUnprefixedQI: address register QI view */
1206 { "Src32AnUnprefixedQI", M32C_OPERAND_SRC32ANUNPREFIXEDQI, HW_H_AR_QI, 11, 1,
1207 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_UNPREFIXED] } },
1208 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1209 /* Src32AnUnprefixedHI: address register HI view */
1210 { "Src32AnUnprefixedHI", M32C_OPERAND_SRC32ANUNPREFIXEDHI, HW_H_AR_HI, 11, 1,
1211 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_UNPREFIXED] } },
1212 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1213 /* Src32AnUnprefixedSI: address register SI view */
1214 { "Src32AnUnprefixedSI", M32C_OPERAND_SRC32ANUNPREFIXEDSI, HW_H_AR, 11, 1,
1215 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_UNPREFIXED] } },
1216 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1217 /* Src32AnPrefixed: address register */
1218 { "Src32AnPrefixed", M32C_OPERAND_SRC32ANPREFIXED, HW_H_AR, 19, 1,
1219 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_PREFIXED] } },
1220 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1221 /* Src32AnPrefixedQI: address register QI view */
1222 { "Src32AnPrefixedQI", M32C_OPERAND_SRC32ANPREFIXEDQI, HW_H_AR_QI, 19, 1,
1223 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_PREFIXED] } },
1224 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1225 /* Src32AnPrefixedHI: address register HI view */
1226 { "Src32AnPrefixedHI", M32C_OPERAND_SRC32ANPREFIXEDHI, HW_H_AR_HI, 19, 1,
1227 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_PREFIXED] } },
1228 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1229 /* Src32AnPrefixedSI: address register SI view */
1230 { "Src32AnPrefixedSI", M32C_OPERAND_SRC32ANPREFIXEDSI, HW_H_AR, 19, 1,
1231 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_SRC32_AN_PREFIXED] } },
1232 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1233 /* Dst16RnQI: general register QI view */
1234 { "Dst16RnQI", M32C_OPERAND_DST16RNQI, HW_H_GR_QI, 14, 2,
1235 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN] } },
1236 { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
1237 /* Dst16RnHI: general register HI view */
1238 { "Dst16RnHI", M32C_OPERAND_DST16RNHI, HW_H_GR_HI, 14, 2,
1239 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN] } },
1240 { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
1241 /* Dst16RnSI: general register SI view */
1242 { "Dst16RnSI", M32C_OPERAND_DST16RNSI, HW_H_GR_SI, 14, 2,
1243 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN] } },
1244 { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
1245 /* Dst16RnExtQI: general register QI/HI view for 'ext' insns */
1246 { "Dst16RnExtQI", M32C_OPERAND_DST16RNEXTQI, HW_H_GR_EXT_QI, 14, 1,
1247 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN_EXT] } },
1248 { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
1249 /* Dst32R0QI-S: general register QI view */
1250 { "Dst32R0QI-S", M32C_OPERAND_DST32R0QI_S, HW_H_R0L, 0, 0,
1251 { 0, { (const PTR) 0 } },
1252 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1253 /* Dst32R0HI-S: general register HI view */
1254 { "Dst32R0HI-S", M32C_OPERAND_DST32R0HI_S, HW_H_R0, 0, 0,
1255 { 0, { (const PTR) 0 } },
1256 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1257 /* Dst32RnUnprefixedQI: general register QI view */
1258 { "Dst32RnUnprefixedQI", M32C_OPERAND_DST32RNUNPREFIXEDQI, HW_H_GR_QI, 8, 2,
1259 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_UNPREFIXED_QI] } },
1260 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1261 /* Dst32RnUnprefixedHI: general register HI view */
1262 { "Dst32RnUnprefixedHI", M32C_OPERAND_DST32RNUNPREFIXEDHI, HW_H_GR_HI, 8, 2,
1263 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_UNPREFIXED_HI] } },
1264 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1265 /* Dst32RnUnprefixedSI: general register SI view */
1266 { "Dst32RnUnprefixedSI", M32C_OPERAND_DST32RNUNPREFIXEDSI, HW_H_GR_SI, 8, 2,
1267 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_UNPREFIXED_SI] } },
1268 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1269 /* Dst32RnExtUnprefixedQI: general register QI view */
1270 { "Dst32RnExtUnprefixedQI", M32C_OPERAND_DST32RNEXTUNPREFIXEDQI, HW_H_GR_EXT_QI, 9, 1,
1271 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_EXT_UNPREFIXED] } },
1272 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1273 /* Dst32RnExtUnprefixedHI: general register HI view */
1274 { "Dst32RnExtUnprefixedHI", M32C_OPERAND_DST32RNEXTUNPREFIXEDHI, HW_H_GR_EXT_HI, 9, 1,
1275 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_EXT_UNPREFIXED] } },
1276 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1277 /* Dst32RnPrefixedQI: general register QI view */
1278 { "Dst32RnPrefixedQI", M32C_OPERAND_DST32RNPREFIXEDQI, HW_H_GR_QI, 16, 2,
1279 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_PREFIXED_QI] } },
1280 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1281 /* Dst32RnPrefixedHI: general register HI view */
1282 { "Dst32RnPrefixedHI", M32C_OPERAND_DST32RNPREFIXEDHI, HW_H_GR_HI, 16, 2,
1283 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_PREFIXED_HI] } },
1284 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1285 /* Dst32RnPrefixedSI: general register SI view */
1286 { "Dst32RnPrefixedSI", M32C_OPERAND_DST32RNPREFIXEDSI, HW_H_GR_SI, 16, 2,
1287 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_PREFIXED_SI] } },
1288 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1289 /* Dst16RnQI-S: general register QI view */
1290 { "Dst16RnQI-S", M32C_OPERAND_DST16RNQI_S, HW_H_R0L_R0H, 5, 1,
1291 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN_QI_S] } },
1292 { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
1293 /* Dst16AnQI-S: address register QI view */
1294 { "Dst16AnQI-S", M32C_OPERAND_DST16ANQI_S, HW_H_AR_QI, 5, 1,
1295 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN_QI_S] } },
1296 { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
1297 /* Bit16Rn: general register bit view */
1298 { "Bit16Rn", M32C_OPERAND_BIT16RN, HW_H_GR_HI, 14, 2,
1299 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_RN] } },
1300 { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
1301 /* Bit32RnPrefixed: general register bit view */
1302 { "Bit32RnPrefixed", M32C_OPERAND_BIT32RNPREFIXED, HW_H_GR_QI, 16, 2,
1303 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_PREFIXED_QI] } },
1304 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1305 /* Bit32RnUnprefixed: general register bit view */
1306 { "Bit32RnUnprefixed", M32C_OPERAND_BIT32RNUNPREFIXED, HW_H_GR_QI, 8, 2,
1307 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_RN_UNPREFIXED_QI] } },
1308 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1310 { "R0", M32C_OPERAND_R0, HW_H_R0, 0, 0,
1311 { 0, { (const PTR) 0 } },
1312 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1314 { "R1", M32C_OPERAND_R1, HW_H_R1, 0, 0,
1315 { 0, { (const PTR) 0 } },
1316 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1318 { "R2", M32C_OPERAND_R2, HW_H_R2, 0, 0,
1319 { 0, { (const PTR) 0 } },
1320 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1322 { "R3", M32C_OPERAND_R3, HW_H_R3, 0, 0,
1323 { 0, { (const PTR) 0 } },
1324 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1326 { "R0l", M32C_OPERAND_R0L, HW_H_R0L, 0, 0,
1327 { 0, { (const PTR) 0 } },
1328 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1330 { "R0h", M32C_OPERAND_R0H, HW_H_R0H, 0, 0,
1331 { 0, { (const PTR) 0 } },
1332 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1334 { "R2R0", M32C_OPERAND_R2R0, HW_H_R2R0, 0, 0,
1335 { 0, { (const PTR) 0 } },
1336 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1338 { "R3R1", M32C_OPERAND_R3R1, HW_H_R3R1, 0, 0,
1339 { 0, { (const PTR) 0 } },
1340 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1341 /* R1R2R0: r1r2r0 */
1342 { "R1R2R0", M32C_OPERAND_R1R2R0, HW_H_R1R2R0, 0, 0,
1343 { 0, { (const PTR) 0 } },
1344 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1345 /* Dst16An: address register */
1346 { "Dst16An", M32C_OPERAND_DST16AN, HW_H_AR, 15, 1,
1347 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } },
1348 { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
1349 /* Dst16AnQI: address register QI view */
1350 { "Dst16AnQI", M32C_OPERAND_DST16ANQI, HW_H_AR_QI, 15, 1,
1351 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } },
1352 { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
1353 /* Dst16AnHI: address register HI view */
1354 { "Dst16AnHI", M32C_OPERAND_DST16ANHI, HW_H_AR_HI, 15, 1,
1355 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } },
1356 { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
1357 /* Dst16AnSI: address register SI view */
1358 { "Dst16AnSI", M32C_OPERAND_DST16ANSI, HW_H_AR_SI, 15, 1,
1359 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } },
1360 { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
1361 /* Dst16An-S: address register HI view */
1362 { "Dst16An-S", M32C_OPERAND_DST16AN_S, HW_H_AR_HI, 4, 1,
1363 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN_S] } },
1364 { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
1365 /* Dst32AnUnprefixed: address register */
1366 { "Dst32AnUnprefixed", M32C_OPERAND_DST32ANUNPREFIXED, HW_H_AR, 9, 1,
1367 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
1368 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1369 /* Dst32AnUnprefixedQI: address register QI view */
1370 { "Dst32AnUnprefixedQI", M32C_OPERAND_DST32ANUNPREFIXEDQI, HW_H_AR_QI, 9, 1,
1371 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
1372 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1373 /* Dst32AnUnprefixedHI: address register HI view */
1374 { "Dst32AnUnprefixedHI", M32C_OPERAND_DST32ANUNPREFIXEDHI, HW_H_AR_HI, 9, 1,
1375 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
1376 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1377 /* Dst32AnUnprefixedSI: address register SI view */
1378 { "Dst32AnUnprefixedSI", M32C_OPERAND_DST32ANUNPREFIXEDSI, HW_H_AR, 9, 1,
1379 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
1380 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1381 /* Dst32AnExtUnprefixed: address register */
1382 { "Dst32AnExtUnprefixed", M32C_OPERAND_DST32ANEXTUNPREFIXED, HW_H_AR, 9, 1,
1383 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
1384 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1385 /* Dst32AnPrefixed: address register */
1386 { "Dst32AnPrefixed", M32C_OPERAND_DST32ANPREFIXED, HW_H_AR, 17, 1,
1387 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } },
1388 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1389 /* Dst32AnPrefixedQI: address register QI view */
1390 { "Dst32AnPrefixedQI", M32C_OPERAND_DST32ANPREFIXEDQI, HW_H_AR_QI, 17, 1,
1391 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } },
1392 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1393 /* Dst32AnPrefixedHI: address register HI view */
1394 { "Dst32AnPrefixedHI", M32C_OPERAND_DST32ANPREFIXEDHI, HW_H_AR_HI, 17, 1,
1395 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } },
1396 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1397 /* Dst32AnPrefixedSI: address register SI view */
1398 { "Dst32AnPrefixedSI", M32C_OPERAND_DST32ANPREFIXEDSI, HW_H_AR, 17, 1,
1399 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } },
1400 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1401 /* Bit16An: address register bit view */
1402 { "Bit16An", M32C_OPERAND_BIT16AN, HW_H_AR, 15, 1,
1403 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST16_AN] } },
1404 { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
1405 /* Bit32AnPrefixed: address register bit */
1406 { "Bit32AnPrefixed", M32C_OPERAND_BIT32ANPREFIXED, HW_H_AR, 17, 1,
1407 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_PREFIXED] } },
1408 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1409 /* Bit32AnUnprefixed: address register bit */
1410 { "Bit32AnUnprefixed", M32C_OPERAND_BIT32ANUNPREFIXED, HW_H_AR, 9, 1,
1411 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DST32_AN_UNPREFIXED] } },
1412 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1414 { "A0", M32C_OPERAND_A0, HW_H_A0, 0, 0,
1415 { 0, { (const PTR) 0 } },
1416 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1418 { "A1", M32C_OPERAND_A1, HW_H_A1, 0, 0,
1419 { 0, { (const PTR) 0 } },
1420 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1421 /* sb: SB register */
1422 { "sb", M32C_OPERAND_SB, HW_H_SB, 0, 0,
1423 { 0, { (const PTR) 0 } },
1424 { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1425 /* fb: FB register */
1426 { "fb", M32C_OPERAND_FB, HW_H_FB, 0, 0,
1427 { 0, { (const PTR) 0 } },
1428 { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1429 /* sp: SP register */
1430 { "sp", M32C_OPERAND_SP, HW_H_SP, 0, 0,
1431 { 0, { (const PTR) 0 } },
1432 { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1433 /* SrcDst16-r0l-r0h-S-normal: r0l/r0h pair */
1434 { "SrcDst16-r0l-r0h-S-normal", M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL, HW_H_SINT, 5, 1,
1435 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_5_1] } },
1436 { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
1437 /* Regsetpop: popm regset */
1438 { "Regsetpop", M32C_OPERAND_REGSETPOP, HW_H_UINT, 8, 8,
1439 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_8_8] } },
1440 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1441 /* Regsetpush: pushm regset */
1442 { "Regsetpush", M32C_OPERAND_REGSETPUSH, HW_H_UINT, 8, 8,
1443 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_8_8] } },
1444 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1445 /* Rn16-push-S: r0[lh] */
1446 { "Rn16-push-S", M32C_OPERAND_RN16_PUSH_S, HW_H_GR_QI, 4, 1,
1447 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_4_1] } },
1448 { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
1449 /* An16-push-S: a[01] */
1450 { "An16-push-S", M32C_OPERAND_AN16_PUSH_S, HW_H_AR_HI, 4, 1,
1451 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_4_1] } },
1452 { 0, { (1<<MACH_M16C), (1<<ISA_M16C) } } },
1453 /* Dsp-8-u6: unsigned 6 bit displacement at offset 8 bits */
1454 { "Dsp-8-u6", M32C_OPERAND_DSP_8_U6, HW_H_UINT, 8, 6,
1455 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U6] } },
1456 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1457 /* Dsp-8-u8: unsigned 8 bit displacement at offset 8 bits */
1458 { "Dsp-8-u8", M32C_OPERAND_DSP_8_U8, HW_H_UINT, 8, 8,
1459 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U8] } },
1460 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1461 /* Dsp-8-u16: unsigned 16 bit displacement at offset 8 bits */
1462 { "Dsp-8-u16", M32C_OPERAND_DSP_8_U16, HW_H_UINT, 8, 16,
1463 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_U16] } },
1464 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1465 /* Dsp-8-s8: signed 8 bit displacement at offset 8 bits */
1466 { "Dsp-8-s8", M32C_OPERAND_DSP_8_S8, HW_H_SINT, 8, 8,
1467 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_S8] } },
1468 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1469 /* Dsp-10-u6: unsigned 6 bit displacement at offset 10 bits */
1470 { "Dsp-10-u6", M32C_OPERAND_DSP_10_U6, HW_H_UINT, 10, 6,
1471 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_10_U6] } },
1472 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1473 /* Dsp-16-u8: unsigned 8 bit displacement at offset 16 bits */
1474 { "Dsp-16-u8", M32C_OPERAND_DSP_16_U8, HW_H_UINT, 16, 8,
1475 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
1476 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1477 /* Dsp-16-u16: unsigned 16 bit displacement at offset 16 bits */
1478 { "Dsp-16-u16", M32C_OPERAND_DSP_16_U16, HW_H_UINT, 16, 16,
1479 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
1480 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1481 /* Dsp-16-u20: unsigned 20 bit displacement at offset 16 bits */
1482 { "Dsp-16-u20", M32C_OPERAND_DSP_16_U20, HW_H_UINT, 0, 24,
1483 { 2, { (const PTR) &M32C_F_DSP_16_U24_MULTI_IFIELD[0] } },
1484 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1485 /* Dsp-16-u24: unsigned 24 bit displacement at offset 16 bits */
1486 { "Dsp-16-u24", M32C_OPERAND_DSP_16_U24, HW_H_UINT, 0, 24,
1487 { 2, { (const PTR) &M32C_F_DSP_16_U24_MULTI_IFIELD[0] } },
1488 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1489 /* Dsp-16-s8: signed 8 bit displacement at offset 16 bits */
1490 { "Dsp-16-s8", M32C_OPERAND_DSP_16_S8, HW_H_SINT, 16, 8,
1491 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S8] } },
1492 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1493 /* Dsp-16-s16: signed 16 bit displacement at offset 16 bits */
1494 { "Dsp-16-s16", M32C_OPERAND_DSP_16_S16, HW_H_SINT, 16, 16,
1495 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S16] } },
1496 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1497 /* Dsp-24-u8: unsigned 8 bit displacement at offset 24 bits */
1498 { "Dsp-24-u8", M32C_OPERAND_DSP_24_U8, HW_H_UINT, 24, 8,
1499 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
1500 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1501 /* Dsp-24-u16: unsigned 16 bit displacement at offset 24 bits */
1502 { "Dsp-24-u16", M32C_OPERAND_DSP_24_U16, HW_H_UINT, 0, 16,
1503 { 2, { (const PTR) &M32C_F_DSP_24_U16_MULTI_IFIELD[0] } },
1504 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1505 /* Dsp-24-u20: unsigned 20 bit displacement at offset 24 bits */
1506 { "Dsp-24-u20", M32C_OPERAND_DSP_24_U20, HW_H_UINT, 0, 24,
1507 { 2, { (const PTR) &M32C_F_DSP_24_U24_MULTI_IFIELD[0] } },
1508 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1509 /* Dsp-24-u24: unsigned 24 bit displacement at offset 24 bits */
1510 { "Dsp-24-u24", M32C_OPERAND_DSP_24_U24, HW_H_UINT, 0, 24,
1511 { 2, { (const PTR) &M32C_F_DSP_24_U24_MULTI_IFIELD[0] } },
1512 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1513 /* Dsp-24-s8: signed 8 bit displacement at offset 24 bits */
1514 { "Dsp-24-s8", M32C_OPERAND_DSP_24_S8, HW_H_SINT, 24, 8,
1515 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_S8] } },
1516 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1517 /* Dsp-24-s16: signed 16 bit displacement at offset 24 bits */
1518 { "Dsp-24-s16", M32C_OPERAND_DSP_24_S16, HW_H_SINT, 0, 16,
1519 { 2, { (const PTR) &M32C_F_DSP_24_S16_MULTI_IFIELD[0] } },
1520 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1521 /* Dsp-32-u8: unsigned 8 bit displacement at offset 32 bits */
1522 { "Dsp-32-u8", M32C_OPERAND_DSP_32_U8, HW_H_UINT, 0, 8,
1523 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
1524 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1525 /* Dsp-32-u16: unsigned 16 bit displacement at offset 32 bits */
1526 { "Dsp-32-u16", M32C_OPERAND_DSP_32_U16, HW_H_UINT, 0, 16,
1527 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U16] } },
1528 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1529 /* Dsp-32-u24: unsigned 24 bit displacement at offset 32 bits */
1530 { "Dsp-32-u24", M32C_OPERAND_DSP_32_U24, HW_H_UINT, 0, 24,
1531 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U24] } },
1532 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1533 /* Dsp-32-u20: unsigned 20 bit displacement at offset 32 bits */
1534 { "Dsp-32-u20", M32C_OPERAND_DSP_32_U20, HW_H_UINT, 0, 24,
1535 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U24] } },
1536 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1537 /* Dsp-32-s8: signed 8 bit displacement at offset 32 bits */
1538 { "Dsp-32-s8", M32C_OPERAND_DSP_32_S8, HW_H_SINT, 0, 8,
1539 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S8] } },
1540 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1541 /* Dsp-32-s16: signed 16 bit displacement at offset 32 bits */
1542 { "Dsp-32-s16", M32C_OPERAND_DSP_32_S16, HW_H_SINT, 0, 16,
1543 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S16] } },
1544 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1545 /* Dsp-40-u8: unsigned 8 bit displacement at offset 40 bits */
1546 { "Dsp-40-u8", M32C_OPERAND_DSP_40_U8, HW_H_UINT, 8, 8,
1547 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U8] } },
1548 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1549 /* Dsp-40-s8: signed 8 bit displacement at offset 40 bits */
1550 { "Dsp-40-s8", M32C_OPERAND_DSP_40_S8, HW_H_UINT, 8, 8,
1551 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S8] } },
1552 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1553 /* Dsp-40-u16: unsigned 16 bit displacement at offset 40 bits */
1554 { "Dsp-40-u16", M32C_OPERAND_DSP_40_U16, HW_H_UINT, 8, 16,
1555 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U16] } },
1556 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1557 /* Dsp-40-s16: signed 16 bit displacement at offset 40 bits */
1558 { "Dsp-40-s16", M32C_OPERAND_DSP_40_S16, HW_H_UINT, 8, 16,
1559 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S16] } },
1560 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1561 /* Dsp-40-u24: unsigned 24 bit displacement at offset 40 bits */
1562 { "Dsp-40-u24", M32C_OPERAND_DSP_40_U24, HW_H_UINT, 8, 24,
1563 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U24] } },
1564 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1565 /* Dsp-48-u8: unsigned 8 bit displacement at offset 48 bits */
1566 { "Dsp-48-u8", M32C_OPERAND_DSP_48_U8, HW_H_UINT, 16, 8,
1567 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U8] } },
1568 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1569 /* Dsp-48-s8: signed 8 bit displacement at offset 48 bits */
1570 { "Dsp-48-s8", M32C_OPERAND_DSP_48_S8, HW_H_UINT, 16, 8,
1571 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S8] } },
1572 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1573 /* Dsp-48-u16: unsigned 16 bit displacement at offset 48 bits */
1574 { "Dsp-48-u16", M32C_OPERAND_DSP_48_U16, HW_H_UINT, 16, 16,
1575 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_U16] } },
1576 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1577 /* Dsp-48-s16: signed 16 bit displacement at offset 48 bits */
1578 { "Dsp-48-s16", M32C_OPERAND_DSP_48_S16, HW_H_UINT, 16, 16,
1579 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S16] } },
1580 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1581 /* Dsp-48-u24: unsigned 24 bit displacement at offset 48 bits */
1582 { "Dsp-48-u24", M32C_OPERAND_DSP_48_U24, HW_H_UINT, 0, 24,
1583 { 2, { (const PTR) &M32C_F_DSP_48_U24_MULTI_IFIELD[0] } },
1584 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1585 /* Imm-8-s4: signed 4 bit immediate at offset 8 bits */
1586 { "Imm-8-s4", M32C_OPERAND_IMM_8_S4, HW_H_SINT, 8, 4,
1587 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_8_S4] } },
1588 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1589 /* Imm-sh-8-s4: signed 4 bit shift immediate at offset 8 bits */
1590 { "Imm-sh-8-s4", M32C_OPERAND_IMM_SH_8_S4, HW_H_SHIMM, 8, 4,
1591 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_8_S4] } },
1592 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1593 /* Imm-8-QI: signed 8 bit immediate at offset 8 bits */
1594 { "Imm-8-QI", M32C_OPERAND_IMM_8_QI, HW_H_SINT, 8, 8,
1595 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_S8] } },
1596 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1597 /* Imm-8-HI: signed 16 bit immediate at offset 8 bits */
1598 { "Imm-8-HI", M32C_OPERAND_IMM_8_HI, HW_H_SINT, 8, 16,
1599 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_8_S16] } },
1600 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1601 /* Imm-12-s4: signed 4 bit immediate at offset 12 bits */
1602 { "Imm-12-s4", M32C_OPERAND_IMM_12_S4, HW_H_SINT, 12, 4,
1603 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_12_S4] } },
1604 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1605 /* Imm-sh-12-s4: signed 4 bit shift immediate at offset 12 bits */
1606 { "Imm-sh-12-s4", M32C_OPERAND_IMM_SH_12_S4, HW_H_SHIMM, 12, 4,
1607 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_12_S4] } },
1608 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1609 /* Imm-13-u3: signed 3 bit immediate at offset 13 bits */
1610 { "Imm-13-u3", M32C_OPERAND_IMM_13_U3, HW_H_UINT, 13, 3,
1611 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_13_U3] } },
1612 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1613 /* Imm-20-s4: signed 4 bit immediate at offset 20 bits */
1614 { "Imm-20-s4", M32C_OPERAND_IMM_20_S4, HW_H_SINT, 20, 4,
1615 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_20_S4] } },
1616 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1617 /* Imm-sh-20-s4: signed 4 bit shift immediate at offset 12 bits */
1618 { "Imm-sh-20-s4", M32C_OPERAND_IMM_SH_20_S4, HW_H_SHIMM, 20, 4,
1619 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM_20_S4] } },
1620 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1621 /* Imm-16-QI: signed 8 bit immediate at offset 16 bits */
1622 { "Imm-16-QI", M32C_OPERAND_IMM_16_QI, HW_H_SINT, 16, 8,
1623 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S8] } },
1624 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1625 /* Imm-16-HI: signed 16 bit immediate at offset 16 bits */
1626 { "Imm-16-HI", M32C_OPERAND_IMM_16_HI, HW_H_SINT, 16, 16,
1627 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S16] } },
1628 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1629 /* Imm-16-SI: signed 32 bit immediate at offset 16 bits */
1630 { "Imm-16-SI", M32C_OPERAND_IMM_16_SI, HW_H_SINT, 0, 32,
1631 { 2, { (const PTR) &M32C_F_DSP_16_S32_MULTI_IFIELD[0] } },
1632 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1633 /* Imm-24-QI: signed 8 bit immediate at offset 24 bits */
1634 { "Imm-24-QI", M32C_OPERAND_IMM_24_QI, HW_H_SINT, 24, 8,
1635 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_S8] } },
1636 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1637 /* Imm-24-HI: signed 16 bit immediate at offset 24 bits */
1638 { "Imm-24-HI", M32C_OPERAND_IMM_24_HI, HW_H_SINT, 0, 16,
1639 { 2, { (const PTR) &M32C_F_DSP_24_S16_MULTI_IFIELD[0] } },
1640 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1641 /* Imm-24-SI: signed 32 bit immediate at offset 24 bits */
1642 { "Imm-24-SI", M32C_OPERAND_IMM_24_SI, HW_H_SINT, 0, 32,
1643 { 2, { (const PTR) &M32C_F_DSP_24_S32_MULTI_IFIELD[0] } },
1644 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1645 /* Imm-32-QI: signed 8 bit immediate at offset 32 bits */
1646 { "Imm-32-QI", M32C_OPERAND_IMM_32_QI, HW_H_SINT, 0, 8,
1647 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S8] } },
1648 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1649 /* Imm-32-SI: signed 32 bit immediate at offset 32 bits */
1650 { "Imm-32-SI", M32C_OPERAND_IMM_32_SI, HW_H_SINT, 0, 32,
1651 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S32] } },
1652 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1653 /* Imm-32-HI: signed 16 bit immediate at offset 32 bits */
1654 { "Imm-32-HI", M32C_OPERAND_IMM_32_HI, HW_H_SINT, 0, 16,
1655 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_S16] } },
1656 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1657 /* Imm-40-QI: signed 8 bit immediate at offset 40 bits */
1658 { "Imm-40-QI", M32C_OPERAND_IMM_40_QI, HW_H_SINT, 8, 8,
1659 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S8] } },
1660 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1661 /* Imm-40-HI: signed 16 bit immediate at offset 40 bits */
1662 { "Imm-40-HI", M32C_OPERAND_IMM_40_HI, HW_H_SINT, 8, 16,
1663 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_S16] } },
1664 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1665 /* Imm-40-SI: signed 32 bit immediate at offset 40 bits */
1666 { "Imm-40-SI", M32C_OPERAND_IMM_40_SI, HW_H_SINT, 0, 32,
1667 { 2, { (const PTR) &M32C_F_DSP_40_S32_MULTI_IFIELD[0] } },
1668 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1669 /* Imm-48-QI: signed 8 bit immediate at offset 48 bits */
1670 { "Imm-48-QI", M32C_OPERAND_IMM_48_QI, HW_H_SINT, 16, 8,
1671 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S8] } },
1672 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1673 /* Imm-48-HI: signed 16 bit immediate at offset 48 bits */
1674 { "Imm-48-HI", M32C_OPERAND_IMM_48_HI, HW_H_SINT, 16, 16,
1675 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_48_S16] } },
1676 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1677 /* Imm-48-SI: signed 32 bit immediate at offset 48 bits */
1678 { "Imm-48-SI", M32C_OPERAND_IMM_48_SI, HW_H_SINT, 0, 32,
1679 { 2, { (const PTR) &M32C_F_DSP_48_S32_MULTI_IFIELD[0] } },
1680 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1681 /* Imm-56-QI: signed 8 bit immediate at offset 56 bits */
1682 { "Imm-56-QI", M32C_OPERAND_IMM_56_QI, HW_H_SINT, 24, 8,
1683 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_56_S8] } },
1684 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1685 /* Imm-56-HI: signed 16 bit immediate at offset 56 bits */
1686 { "Imm-56-HI", M32C_OPERAND_IMM_56_HI, HW_H_SINT, 0, 16,
1687 { 2, { (const PTR) &M32C_F_DSP_56_S16_MULTI_IFIELD[0] } },
1688 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1689 /* Imm-64-HI: signed 16 bit immediate at offset 64 bits */
1690 { "Imm-64-HI", M32C_OPERAND_IMM_64_HI, HW_H_SINT, 0, 16,
1691 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_64_S16] } },
1692 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1693 /* Imm1-S: signed 1 bit immediate for short format binary insns */
1694 { "Imm1-S", M32C_OPERAND_IMM1_S, HW_H_SINT, 2, 1,
1695 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_IMM1_S] } },
1696 { 0, { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1697 /* Imm3-S: signed 3 bit immediate for short format binary insns */
1698 { "Imm3-S", M32C_OPERAND_IMM3_S, HW_H_SINT, 2, 3,
1699 { 2, { (const PTR) &M32C_F_IMM3_S_MULTI_IFIELD[0] } },
1700 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1701 /* Bitno16R: bit number for indexing registers */
1702 { "Bitno16R", M32C_OPERAND_BITNO16R, HW_H_UINT, 16, 8,
1703 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
1704 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } },
1705 /* Bitno32Prefixed: bit number for indexing objects */
1706 { "Bitno32Prefixed", M32C_OPERAND_BITNO32PREFIXED, HW_H_UINT, 21, 3,
1707 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_PREFIXED] } },
1708 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1709 /* Bitno32Unprefixed: bit number for indexing objects */
1710 { "Bitno32Unprefixed", M32C_OPERAND_BITNO32UNPREFIXED, HW_H_UINT, 13, 3,
1711 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_BITNO32_UNPREFIXED] } },
1712 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1713 /* BitBase16-16-u8: unsigned bit,base:8 at offset 16for m16c */
1714 { "BitBase16-16-u8", M32C_OPERAND_BITBASE16_16_U8, HW_H_UINT, 16, 8,
1715 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
1716 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } },
1717 /* BitBase16-16-s8: signed bit,base:8 at offset 16for m16c */
1718 { "BitBase16-16-s8", M32C_OPERAND_BITBASE16_16_S8, HW_H_UINT, 16, 8,
1719 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_S8] } },
1720 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } },
1721 /* BitBase16-16-u16: unsigned bit,base:16 at offset 16 for m16c */
1722 { "BitBase16-16-u16", M32C_OPERAND_BITBASE16_16_U16, HW_H_UINT, 16, 16,
1723 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U16] } },
1724 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } },
1725 /* BitBase16-8-u11-S: signed bit,base:11 at offset 16 for m16c */
1726 { "BitBase16-8-u11-S", M32C_OPERAND_BITBASE16_8_U11_S, HW_H_SINT, 5, 11,
1727 { 2, { (const PTR) &M32C_F_BITBASE16_U11_S_MULTI_IFIELD[0] } },
1728 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C) } } },
1729 /* BitBase32-16-u11-Unprefixed: unsigned bit,base:11 at offset 16 for m32c */
1730 { "BitBase32-16-u11-Unprefixed", M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED, HW_H_UINT, 13, 11,
1731 { 2, { (const PTR) &M32C_F_BITBASE32_16_U11_UNPREFIXED_MULTI_IFIELD[0] } },
1732 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1733 /* BitBase32-16-s11-Unprefixed: signed bit,base:11 at offset 16 for m32c */
1734 { "BitBase32-16-s11-Unprefixed", M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED, HW_H_SINT, 13, 11,
1735 { 2, { (const PTR) &M32C_F_BITBASE32_16_S11_UNPREFIXED_MULTI_IFIELD[0] } },
1736 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1737 /* BitBase32-16-u19-Unprefixed: unsigned bit,base:19 at offset 16 for m32c */
1738 { "BitBase32-16-u19-Unprefixed", M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED, HW_H_UINT, 13, 19,
1739 { 2, { (const PTR) &M32C_F_BITBASE32_16_U19_UNPREFIXED_MULTI_IFIELD[0] } },
1740 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1741 /* BitBase32-16-s19-Unprefixed: signed bit,base:19 at offset 16 for m32c */
1742 { "BitBase32-16-s19-Unprefixed", M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED, HW_H_SINT, 13, 19,
1743 { 2, { (const PTR) &M32C_F_BITBASE32_16_S19_UNPREFIXED_MULTI_IFIELD[0] } },
1744 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1745 /* BitBase32-16-u27-Unprefixed: unsigned bit,base:27 at offset 16 for m32c */
1746 { "BitBase32-16-u27-Unprefixed", M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED, HW_H_UINT, 0, 27,
1747 { 3, { (const PTR) &M32C_F_BITBASE32_16_U27_UNPREFIXED_MULTI_IFIELD[0] } },
1748 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1749 /* BitBase32-24-u11-Prefixed: unsigned bit,base:11 at offset 24 for m32c */
1750 { "BitBase32-24-u11-Prefixed", M32C_OPERAND_BITBASE32_24_U11_PREFIXED, HW_H_UINT, 21, 11,
1751 { 2, { (const PTR) &M32C_F_BITBASE32_24_U11_PREFIXED_MULTI_IFIELD[0] } },
1752 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1753 /* BitBase32-24-s11-Prefixed: signed bit,base:11 at offset 24 for m32c */
1754 { "BitBase32-24-s11-Prefixed", M32C_OPERAND_BITBASE32_24_S11_PREFIXED, HW_H_SINT, 21, 11,
1755 { 2, { (const PTR) &M32C_F_BITBASE32_24_S11_PREFIXED_MULTI_IFIELD[0] } },
1756 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1757 /* BitBase32-24-u19-Prefixed: unsigned bit,base:19 at offset 24 for m32c */
1758 { "BitBase32-24-u19-Prefixed", M32C_OPERAND_BITBASE32_24_U19_PREFIXED, HW_H_UINT, 0, 19,
1759 { 3, { (const PTR) &M32C_F_BITBASE32_24_U19_PREFIXED_MULTI_IFIELD[0] } },
1760 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1761 /* BitBase32-24-s19-Prefixed: signed bit,base:19 at offset 24 for m32c */
1762 { "BitBase32-24-s19-Prefixed", M32C_OPERAND_BITBASE32_24_S19_PREFIXED, HW_H_SINT, 0, 19,
1763 { 3, { (const PTR) &M32C_F_BITBASE32_24_S19_PREFIXED_MULTI_IFIELD[0] } },
1764 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1765 /* BitBase32-24-u27-Prefixed: unsigned bit,base:27 at offset 24 for m32c */
1766 { "BitBase32-24-u27-Prefixed", M32C_OPERAND_BITBASE32_24_U27_PREFIXED, HW_H_UINT, 0, 27,
1767 { 3, { (const PTR) &M32C_F_BITBASE32_24_U27_PREFIXED_MULTI_IFIELD[0] } },
1768 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1769 /* Lab-5-3: 3 bit label */
1770 { "Lab-5-3", M32C_OPERAND_LAB_5_3, HW_H_IADDR, 5, 3,
1771 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_5_3] } },
1772 { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1773 /* Lab32-jmp-s: 3 bit label */
1774 { "Lab32-jmp-s", M32C_OPERAND_LAB32_JMP_S, HW_H_IADDR, 2, 3,
1775 { 2, { (const PTR) &M32C_F_LAB32_JMP_S_MULTI_IFIELD[0] } },
1776 { 0|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1777 /* Lab-8-8: 8 bit label */
1778 { "Lab-8-8", M32C_OPERAND_LAB_8_8, HW_H_IADDR, 8, 8,
1779 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_8_8] } },
1780 { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1781 /* Lab-8-16: 16 bit label */
1782 { "Lab-8-16", M32C_OPERAND_LAB_8_16, HW_H_IADDR, 8, 16,
1783 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_8_16] } },
1784 { 0|A(SIGN_OPT)|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1785 /* Lab-8-24: 24 bit label */
1786 { "Lab-8-24", M32C_OPERAND_LAB_8_24, HW_H_IADDR, 8, 24,
1787 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_8_24] } },
1788 { 0|A(ABS_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1789 /* Lab-16-8: 8 bit label */
1790 { "Lab-16-8", M32C_OPERAND_LAB_16_8, HW_H_IADDR, 16, 8,
1791 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_16_8] } },
1792 { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1793 /* Lab-24-8: 8 bit label */
1794 { "Lab-24-8", M32C_OPERAND_LAB_24_8, HW_H_IADDR, 24, 8,
1795 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_24_8] } },
1796 { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1797 /* Lab-32-8: 8 bit label */
1798 { "Lab-32-8", M32C_OPERAND_LAB_32_8, HW_H_IADDR, 0, 8,
1799 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_32_8] } },
1800 { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1801 /* Lab-40-8: 8 bit label */
1802 { "Lab-40-8", M32C_OPERAND_LAB_40_8, HW_H_IADDR, 8, 8,
1803 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_LAB_40_8] } },
1804 { 0|A(PCREL_ADDR), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1805 /* sbit: negative bit */
1806 { "sbit", M32C_OPERAND_SBIT, HW_H_SBIT, 0, 0,
1807 { 0, { (const PTR) 0 } },
1808 { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1809 /* obit: overflow bit */
1810 { "obit", M32C_OPERAND_OBIT, HW_H_OBIT, 0, 0,
1811 { 0, { (const PTR) 0 } },
1812 { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1813 /* zbit: zero bit */
1814 { "zbit", M32C_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
1815 { 0, { (const PTR) 0 } },
1816 { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1817 /* cbit: carry bit */
1818 { "cbit", M32C_OPERAND_CBIT, HW_H_CBIT, 0, 0,
1819 { 0, { (const PTR) 0 } },
1820 { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1821 /* ubit: stack ptr select bit */
1822 { "ubit", M32C_OPERAND_UBIT, HW_H_UBIT, 0, 0,
1823 { 0, { (const PTR) 0 } },
1824 { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1825 /* ibit: interrupt enable bit */
1826 { "ibit", M32C_OPERAND_IBIT, HW_H_IBIT, 0, 0,
1827 { 0, { (const PTR) 0 } },
1828 { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1829 /* bbit: reg bank select bit */
1830 { "bbit", M32C_OPERAND_BBIT, HW_H_BBIT, 0, 0,
1831 { 0, { (const PTR) 0 } },
1832 { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1833 /* dbit: debug bit */
1834 { "dbit", M32C_OPERAND_DBIT, HW_H_DBIT, 0, 0,
1835 { 0, { (const PTR) 0 } },
1836 { 0|A(SEM_ONLY), { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1837 /* cond16-16: condition */
1838 { "cond16-16", M32C_OPERAND_COND16_16, HW_H_COND16, 16, 8,
1839 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
1840 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } },
1841 /* cond16-24: condition */
1842 { "cond16-24", M32C_OPERAND_COND16_24, HW_H_COND16, 24, 8,
1843 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
1844 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } },
1845 /* cond16-32: condition */
1846 { "cond16-32", M32C_OPERAND_COND16_32, HW_H_COND16, 0, 8,
1847 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
1848 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } },
1849 /* cond32-16: condition */
1850 { "cond32-16", M32C_OPERAND_COND32_16, HW_H_COND32, 16, 8,
1851 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_16_U8] } },
1852 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1853 /* cond32-24: condition */
1854 { "cond32-24", M32C_OPERAND_COND32_24, HW_H_COND32, 24, 8,
1855 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_24_U8] } },
1856 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1857 /* cond32-32: condition */
1858 { "cond32-32", M32C_OPERAND_COND32_32, HW_H_COND32, 0, 8,
1859 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_32_U8] } },
1860 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1861 /* cond32-40: condition */
1862 { "cond32-40", M32C_OPERAND_COND32_40, HW_H_COND32, 8, 8,
1863 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_DSP_40_U8] } },
1864 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1865 /* cond16c: condition */
1866 { "cond16c", M32C_OPERAND_COND16C, HW_H_COND16C, 12, 4,
1867 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_COND16] } },
1868 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } },
1869 /* cond16j: condition */
1870 { "cond16j", M32C_OPERAND_COND16J, HW_H_COND16J, 12, 4,
1871 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_COND16] } },
1872 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } },
1873 /* cond16j5: condition */
1874 { "cond16j5", M32C_OPERAND_COND16J5, HW_H_COND16J_5, 5, 3,
1875 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_COND16J_5] } },
1876 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } },
1877 /* cond32: condition */
1878 { "cond32", M32C_OPERAND_COND32, HW_H_COND32, 9, 4,
1879 { 2, { (const PTR) &M32C_F_COND32_MULTI_IFIELD[0] } },
1880 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1881 /* cond32j: condition */
1882 { "cond32j", M32C_OPERAND_COND32J, HW_H_COND32, 1, 4,
1883 { 2, { (const PTR) &M32C_F_COND32J_MULTI_IFIELD[0] } },
1884 { 0|A(VIRTUAL), { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1885 /* sccond32: scCND condition */
1886 { "sccond32", M32C_OPERAND_SCCOND32, HW_H_COND32, 12, 4,
1887 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_COND16] } },
1888 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1889 /* flags16: flags */
1890 { "flags16", M32C_OPERAND_FLAGS16, HW_H_FLAGS, 9, 3,
1891 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_9_3] } },
1892 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } },
1893 /* flags32: flags */
1894 { "flags32", M32C_OPERAND_FLAGS32, HW_H_FLAGS, 13, 3,
1895 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } },
1896 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1898 { "cr16", M32C_OPERAND_CR16, HW_H_CR_16, 9, 3,
1899 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_9_3] } },
1900 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } } },
1901 /* cr1-Unprefixed-32: control */
1902 { "cr1-Unprefixed-32", M32C_OPERAND_CR1_UNPREFIXED_32, HW_H_CR1_32, 13, 3,
1903 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } },
1904 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1905 /* cr1-Prefixed-32: control */
1906 { "cr1-Prefixed-32", M32C_OPERAND_CR1_PREFIXED_32, HW_H_CR1_32, 21, 3,
1907 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_21_3] } },
1908 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1909 /* cr2-32: control */
1910 { "cr2-32", M32C_OPERAND_CR2_32, HW_H_CR2_32, 13, 3,
1911 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } },
1912 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1913 /* cr3-Unprefixed-32: control */
1914 { "cr3-Unprefixed-32", M32C_OPERAND_CR3_UNPREFIXED_32, HW_H_CR3_32, 13, 3,
1915 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_13_3] } },
1916 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1917 /* cr3-Prefixed-32: control */
1918 { "cr3-Prefixed-32", M32C_OPERAND_CR3_PREFIXED_32, HW_H_CR3_32, 21, 3,
1919 { 0, { (const PTR) &m32c_cgen_ifld_table[M32C_F_21_3] } },
1920 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } } },
1921 /* Z: Suffix for zero format insns */
1922 { "Z", M32C_OPERAND_Z, HW_H_SINT, 0, 0,
1923 { 0, { (const PTR) 0 } },
1924 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1925 /* S: Suffix for short format insns */
1926 { "S", M32C_OPERAND_S, HW_H_SINT, 0, 0,
1927 { 0, { (const PTR) 0 } },
1928 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1929 /* Q: Suffix for quick format insns */
1930 { "Q", M32C_OPERAND_Q, HW_H_SINT, 0, 0,
1931 { 0, { (const PTR) 0 } },
1932 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1933 /* G: Suffix for general format insns */
1934 { "G", M32C_OPERAND_G, HW_H_SINT, 0, 0,
1935 { 0, { (const PTR) 0 } },
1936 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1937 /* X: Empty suffix */
1938 { "X", M32C_OPERAND_X, HW_H_SINT, 0, 0,
1939 { 0, { (const PTR) 0 } },
1940 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1941 /* size: any size specifier */
1942 { "size", M32C_OPERAND_SIZE, HW_H_SINT, 0, 0,
1943 { 0, { (const PTR) 0 } },
1944 { 0, { (1<<MACH_BASE), (1<<ISA_M16C)|(1<<ISA_M32C) } } },
1945 /* BitIndex: Bit Index for the next insn */
1946 { "BitIndex", M32C_OPERAND_BITINDEX, HW_H_BIT_INDEX, 0, 0,
1947 { 0, { (const PTR) 0 } },
1948 { 0|A(SEM_ONLY), { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1949 /* SrcIndex: Source Index for the next insn */
1950 { "SrcIndex", M32C_OPERAND_SRCINDEX, HW_H_SRC_INDEX, 0, 0,
1951 { 0, { (const PTR) 0 } },
1952 { 0|A(SEM_ONLY), { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1953 /* DstIndex: Destination Index for the next insn */
1954 { "DstIndex", M32C_OPERAND_DSTINDEX, HW_H_DST_INDEX, 0, 0,
1955 { 0, { (const PTR) 0 } },
1956 { 0|A(SEM_ONLY), { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1957 /* NoRemainder: Place holder for when the remainder is not kept */
1958 { "NoRemainder", M32C_OPERAND_NOREMAINDER, HW_H_NONE, 0, 0,
1959 { 0, { (const PTR) 0 } },
1960 { 0|A(SEM_ONLY), { (1<<MACH_M32C), (1<<ISA_M32C) } } },
1961 /* src16-Rn-direct-QI: m16c Rn direct source QI */
1962 /* src16-Rn-direct-HI: m16c Rn direct source HI */
1963 /* src32-Rn-direct-Unprefixed-QI: m32c Rn direct source QI */
1964 /* src32-Rn-direct-Prefixed-QI: m32c Rn direct source QI */
1965 /* src32-Rn-direct-Unprefixed-HI: m32c Rn direct source HI */
1966 /* src32-Rn-direct-Prefixed-HI: m32c Rn direct source HI */
1967 /* src32-Rn-direct-Unprefixed-SI: m32c Rn direct source SI */
1968 /* src32-Rn-direct-Prefixed-SI: m32c Rn direct source SI */
1969 /* src16-An-direct-QI: m16c An direct destination QI */
1970 /* src16-An-direct-HI: m16c An direct destination HI */
1971 /* src32-An-direct-Unprefixed-QI: m32c An direct destination QI */
1972 /* src32-An-direct-Unprefixed-HI: m32c An direct destination HI */
1973 /* src32-An-direct-Unprefixed-SI: m32c An direct destination SI */
1974 /* src32-An-direct-Prefixed-QI: m32c An direct destination QI */
1975 /* src32-An-direct-Prefixed-HI: m32c An direct destination HI */
1976 /* src32-An-direct-Prefixed-SI: m32c An direct destination SI */
1977 /* src16-An-indirect-QI: m16c An indirect destination QI */
1978 /* src16-An-indirect-HI: m16c An indirect destination HI */
1979 /* src32-An-indirect-Unprefixed-QI: m32c An indirect destination QI */
1980 /* src32-An-indirect-Unprefixed-HI: m32c An indirect destination HI */
1981 /* src32-An-indirect-Unprefixed-SI: m32c An indirect destination SI */
1982 /* src32-An-indirect-Prefixed-QI: m32c An indirect destination QI */
1983 /* src32-An-indirect-Prefixed-HI: m32c An indirect destination HI */
1984 /* src32-An-indirect-Prefixed-SI: m32c An indirect destination SI */
1985 /* src16-16-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */
1986 /* src16-16-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */
1987 /* src16-16-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */
1988 /* src16-16-8-An-relative-QI: m16c dsp:8[An] relative destination QI */
1989 /* src16-16-16-An-relative-QI: m16c dsp:16[An] relative destination QI */
1990 /* src16-16-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */
1991 /* src16-16-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */
1992 /* src16-16-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */
1993 /* src16-16-8-An-relative-HI: m16c dsp:8[An] relative destination HI */
1994 /* src16-16-16-An-relative-HI: m16c dsp:16[An] relative destination HI */
1995 /* src32-16-8-SB-relative-Unprefixed-QI: m32c dsp:8[sb] relative destination QI */
1996 /* src32-16-16-SB-relative-Unprefixed-QI: m32c dsp:16[sb] relative destination QI */
1997 /* src32-16-8-FB-relative-Unprefixed-QI: m32c dsp:8[fb] relative destination QI */
1998 /* src32-16-16-FB-relative-Unprefixed-QI: m32c dsp:16[fb] relative destination QI */
1999 /* src32-16-8-An-relative-Unprefixed-QI: m32c dsp:8[An] relative destination QI */
2000 /* src32-16-16-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2001 /* src32-16-24-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2002 /* src32-16-8-SB-relative-Unprefixed-HI: m32c dsp:8[sb] relative destination HI */
2003 /* src32-16-16-SB-relative-Unprefixed-HI: m32c dsp:16[sb] relative destination HI */
2004 /* src32-16-8-FB-relative-Unprefixed-HI: m32c dsp:8[fb] relative destination HI */
2005 /* src32-16-16-FB-relative-Unprefixed-HI: m32c dsp:16[fb] relative destination HI */
2006 /* src32-16-8-An-relative-Unprefixed-HI: m32c dsp:8[An] relative destination HI */
2007 /* src32-16-16-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2008 /* src32-16-24-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2009 /* src32-16-8-SB-relative-Unprefixed-SI: m32c dsp:8[sb] relative destination SI */
2010 /* src32-16-16-SB-relative-Unprefixed-SI: m32c dsp:16[sb] relative destination SI */
2011 /* src32-16-8-FB-relative-Unprefixed-SI: m32c dsp:8[fb] relative destination SI */
2012 /* src32-16-16-FB-relative-Unprefixed-SI: m32c dsp:16[fb] relative destination SI */
2013 /* src32-16-8-An-relative-Unprefixed-SI: m32c dsp:8[An] relative destination SI */
2014 /* src32-16-16-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2015 /* src32-16-24-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2016 /* src32-24-8-SB-relative-Prefixed-QI: m32c dsp:8[sb] relative destination QI */
2017 /* src32-24-16-SB-relative-Prefixed-QI: m32c dsp:16[sb] relative destination QI */
2018 /* src32-24-8-FB-relative-Prefixed-QI: m32c dsp:8[fb] relative destination QI */
2019 /* src32-24-16-FB-relative-Prefixed-QI: m32c dsp:16[fb] relative destination QI */
2020 /* src32-24-8-An-relative-Prefixed-QI: m32c dsp:8[An] relative destination QI */
2021 /* src32-24-16-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2022 /* src32-24-24-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2023 /* src32-24-8-SB-relative-Prefixed-HI: m32c dsp:8[sb] relative destination HI */
2024 /* src32-24-16-SB-relative-Prefixed-HI: m32c dsp:16[sb] relative destination HI */
2025 /* src32-24-8-FB-relative-Prefixed-HI: m32c dsp:8[fb] relative destination HI */
2026 /* src32-24-16-FB-relative-Prefixed-HI: m32c dsp:16[fb] relative destination HI */
2027 /* src32-24-8-An-relative-Prefixed-HI: m32c dsp:8[An] relative destination HI */
2028 /* src32-24-16-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2029 /* src32-24-24-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2030 /* src32-24-8-SB-relative-Prefixed-SI: m32c dsp:8[sb] relative destination SI */
2031 /* src32-24-16-SB-relative-Prefixed-SI: m32c dsp:16[sb] relative destination SI */
2032 /* src32-24-8-FB-relative-Prefixed-SI: m32c dsp:8[fb] relative destination SI */
2033 /* src32-24-16-FB-relative-Prefixed-SI: m32c dsp:16[fb] relative destination SI */
2034 /* src32-24-8-An-relative-Prefixed-SI: m32c dsp:8[An] relative destination SI */
2035 /* src32-24-16-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2036 /* src32-24-24-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2037 /* src16-16-16-absolute-QI: m16c absolute address QI */
2038 /* src16-16-16-absolute-HI: m16c absolute address HI */
2039 /* src32-16-16-absolute-Unprefixed-QI: m32c absolute address QI */
2040 /* src32-16-24-absolute-Unprefixed-QI: m32c absolute address QI */
2041 /* src32-16-16-absolute-Unprefixed-HI: m32c absolute address HI */
2042 /* src32-16-24-absolute-Unprefixed-HI: m32c absolute address HI */
2043 /* src32-16-16-absolute-Unprefixed-SI: m32c absolute address SI */
2044 /* src32-16-24-absolute-Unprefixed-SI: m32c absolute address SI */
2045 /* src32-24-16-absolute-Prefixed-QI: m32c absolute address QI */
2046 /* src32-24-24-absolute-Prefixed-QI: m32c absolute address QI */
2047 /* src32-24-16-absolute-Prefixed-HI: m32c absolute address HI */
2048 /* src32-24-24-absolute-Prefixed-HI: m32c absolute address HI */
2049 /* src32-24-16-absolute-Prefixed-SI: m32c absolute address SI */
2050 /* src32-24-24-absolute-Prefixed-SI: m32c absolute address SI */
2051 /* src16-2-S-8-SB-relative-QI: m16c SB relative address */
2052 /* src16-2-S-8-FB-relative-QI: m16c FB relative address */
2053 /* src16-2-S-16-absolute-QI: m16c absolute address */
2054 /* src32-2-S-8-SB-relative-QI: m32c SB relative address */
2055 /* src32-2-S-8-FB-relative-QI: m32c FB relative address */
2056 /* src32-2-S-16-absolute-QI: m32c absolute address */
2057 /* src32-2-S-8-SB-relative-HI: m32c SB relative address */
2058 /* src32-2-S-8-FB-relative-HI: m32c FB relative address */
2059 /* src32-2-S-16-absolute-HI: m32c absolute address */
2060 /* dst16-Rn-direct-QI: m16c Rn direct destination QI */
2061 /* dst16-Rn-direct-HI: m16c Rn direct destination HI */
2062 /* dst16-Rn-direct-SI: m16c Rn direct destination SI */
2063 /* dst16-Rn-direct-Ext-QI: m16c Rn direct destination QI */
2064 /* dst32-Rn-direct-Unprefixed-QI: m32c Rn direct destination QI */
2065 /* dst32-Rn-direct-Prefixed-QI: m32c Rn direct destination QI */
2066 /* dst32-Rn-direct-Unprefixed-HI: m32c Rn direct destination HI */
2067 /* dst32-Rn-direct-Prefixed-HI: m32c Rn direct destination HI */
2068 /* dst32-Rn-direct-Unprefixed-SI: m32c Rn direct destination SI */
2069 /* dst32-Rn-direct-Prefixed-SI: m32c Rn direct destination SI */
2070 /* dst32-Rn-direct-ExtUnprefixed-QI: m32c Rn direct destination QI */
2071 /* dst32-Rn-direct-ExtUnprefixed-HI: m32c Rn direct destination HI */
2072 /* dst32-R3-direct-Unprefixed-HI: m32c R3 direct HI */
2073 /* dst16-An-direct-QI: m16c An direct destination QI */
2074 /* dst16-An-direct-HI: m16c An direct destination HI */
2075 /* dst16-An-direct-SI: m16c An direct destination SI */
2076 /* dst32-An-direct-Unprefixed-QI: m32c An direct destination QI */
2077 /* dst32-An-direct-Prefixed-QI: m32c An direct destination QI */
2078 /* dst32-An-direct-Unprefixed-HI: m32c An direct destination HI */
2079 /* dst32-An-direct-Prefixed-HI: m32c An direct destination HI */
2080 /* dst32-An-direct-Unprefixed-SI: m32c An direct destination SI */
2081 /* dst32-An-direct-Prefixed-SI: m32c An direct destination SI */
2082 /* dst16-An-indirect-QI: m16c An indirect destination QI */
2083 /* dst16-An-indirect-HI: m16c An indirect destination HI */
2084 /* dst16-An-indirect-SI: m16c An indirect destination SI */
2085 /* dst16-An-indirect-Ext-QI: m16c An indirect destination QI */
2086 /* dst32-An-indirect-Unprefixed-QI: m32c An indirect destination QI */
2087 /* dst32-An-indirect-Prefixed-QI: m32c An indirect destination QI */
2088 /* dst32-An-indirect-Unprefixed-HI: m32c An indirect destination HI */
2089 /* dst32-An-indirect-Prefixed-HI: m32c An indirect destination HI */
2090 /* dst32-An-indirect-Unprefixed-SI: m32c An indirect destination SI */
2091 /* dst32-An-indirect-Prefixed-SI: m32c An indirect destination SI */
2092 /* dst32-An-indirect-ExtUnprefixed-QI: m32c An indirect destination QI */
2093 /* dst32-An-indirect-ExtUnprefixed-HI: m32c An indirect destination HI */
2094 /* dst16-16-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */
2095 /* dst16-16-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */
2096 /* dst16-16-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */
2097 /* dst16-16-8-An-relative-QI: m16c dsp:8[An] relative destination QI */
2098 /* dst16-16-16-An-relative-QI: m16c dsp:16[An] relative destination QI */
2099 /* dst16-24-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */
2100 /* dst16-24-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */
2101 /* dst16-24-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */
2102 /* dst16-24-8-An-relative-QI: m16c dsp:8[An] relative destination QI */
2103 /* dst16-24-16-An-relative-QI: m16c dsp:16[An] relative destination QI */
2104 /* dst16-32-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */
2105 /* dst16-32-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */
2106 /* dst16-32-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */
2107 /* dst16-32-8-An-relative-QI: m16c dsp:8[An] relative destination QI */
2108 /* dst16-32-16-An-relative-QI: m16c dsp:16[An] relative destination QI */
2109 /* dst16-40-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */
2110 /* dst16-40-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */
2111 /* dst16-40-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */
2112 /* dst16-40-8-An-relative-QI: m16c dsp:8[An] relative destination QI */
2113 /* dst16-40-16-An-relative-QI: m16c dsp:16[An] relative destination QI */
2114 /* dst16-48-8-SB-relative-QI: m16c dsp:8[sb] relative destination QI */
2115 /* dst16-48-16-SB-relative-QI: m16c dsp:16[sb] relative destination QI */
2116 /* dst16-48-8-FB-relative-QI: m16c dsp:8[fb] relative destination QI */
2117 /* dst16-48-8-An-relative-QI: m16c dsp:8[An] relative destination QI */
2118 /* dst16-48-16-An-relative-QI: m16c dsp:16[An] relative destination QI */
2119 /* dst16-16-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */
2120 /* dst16-16-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */
2121 /* dst16-16-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */
2122 /* dst16-16-8-An-relative-HI: m16c dsp:8[An] relative destination HI */
2123 /* dst16-16-16-An-relative-HI: m16c dsp:16[An] relative destination HI */
2124 /* dst16-24-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */
2125 /* dst16-24-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */
2126 /* dst16-24-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */
2127 /* dst16-24-8-An-relative-HI: m16c dsp:8[An] relative destination HI */
2128 /* dst16-24-16-An-relative-HI: m16c dsp:16[An] relative destination HI */
2129 /* dst16-32-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */
2130 /* dst16-32-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */
2131 /* dst16-32-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */
2132 /* dst16-32-8-An-relative-HI: m16c dsp:8[An] relative destination HI */
2133 /* dst16-32-16-An-relative-HI: m16c dsp:16[An] relative destination HI */
2134 /* dst16-40-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */
2135 /* dst16-40-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */
2136 /* dst16-40-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */
2137 /* dst16-40-8-An-relative-HI: m16c dsp:8[An] relative destination HI */
2138 /* dst16-40-16-An-relative-HI: m16c dsp:16[An] relative destination HI */
2139 /* dst16-48-8-SB-relative-HI: m16c dsp:8[sb] relative destination HI */
2140 /* dst16-48-16-SB-relative-HI: m16c dsp:16[sb] relative destination HI */
2141 /* dst16-48-8-FB-relative-HI: m16c dsp:8[fb] relative destination HI */
2142 /* dst16-48-8-An-relative-HI: m16c dsp:8[An] relative destination HI */
2143 /* dst16-48-16-An-relative-HI: m16c dsp:16[An] relative destination HI */
2144 /* dst16-16-8-SB-relative-SI: m16c dsp:8[sb] relative destination SI */
2145 /* dst16-16-16-SB-relative-SI: m16c dsp:16[sb] relative destination SI */
2146 /* dst16-16-8-FB-relative-SI: m16c dsp:8[fb] relative destination SI */
2147 /* dst16-16-8-An-relative-SI: m16c dsp:8[An] relative destination SI */
2148 /* dst16-16-16-An-relative-SI: m16c dsp:16[An] relative destination SI */
2149 /* dst16-24-8-SB-relative-SI: m16c dsp:8[sb] relative destination SI */
2150 /* dst16-24-16-SB-relative-SI: m16c dsp:16[sb] relative destination SI */
2151 /* dst16-24-8-FB-relative-SI: m16c dsp:8[fb] relative destination SI */
2152 /* dst16-24-8-An-relative-SI: m16c dsp:8[An] relative destination SI */
2153 /* dst16-24-16-An-relative-SI: m16c dsp:16[An] relative destination SI */
2154 /* dst16-32-8-SB-relative-SI: m16c dsp:8[sb] relative destination SI */
2155 /* dst16-32-16-SB-relative-SI: m16c dsp:16[sb] relative destination SI */
2156 /* dst16-32-8-FB-relative-SI: m16c dsp:8[fb] relative destination SI */
2157 /* dst16-32-8-An-relative-SI: m16c dsp:8[An] relative destination SI */
2158 /* dst16-32-16-An-relative-SI: m16c dsp:16[An] relative destination SI */
2159 /* dst16-40-8-SB-relative-SI: m16c dsp:8[sb] relative destination SI */
2160 /* dst16-40-16-SB-relative-SI: m16c dsp:16[sb] relative destination SI */
2161 /* dst16-40-8-FB-relative-SI: m16c dsp:8[fb] relative destination SI */
2162 /* dst16-40-8-An-relative-SI: m16c dsp:8[An] relative destination SI */
2163 /* dst16-40-16-An-relative-SI: m16c dsp:16[An] relative destination SI */
2164 /* dst16-48-8-SB-relative-SI: m16c dsp:8[sb] relative destination SI */
2165 /* dst16-48-16-SB-relative-SI: m16c dsp:16[sb] relative destination SI */
2166 /* dst16-48-8-FB-relative-SI: m16c dsp:8[fb] relative destination SI */
2167 /* dst16-48-8-An-relative-SI: m16c dsp:8[An] relative destination SI */
2168 /* dst16-48-16-An-relative-SI: m16c dsp:16[An] relative destination SI */
2169 /* dst16-16-8-SB-relative-Ext-QI: m16c dsp:8[sb] relative destination QI */
2170 /* dst16-16-16-SB-relative-Ext-QI: m16c dsp:16[sb] relative destination QI */
2171 /* dst16-16-8-FB-relative-Ext-QI: m16c dsp:8[fb] relative destination QI */
2172 /* dst16-16-8-An-relative-Ext-QI: m16c dsp:8[An] relative destination QI */
2173 /* dst16-16-16-An-relative-Ext-QI: m16c dsp:16[An] relative destination QI */
2174 /* dst32-16-8-SB-relative-Unprefixed-QI: m32c dsp:8[sb] relative destination QI */
2175 /* dst32-16-16-SB-relative-Unprefixed-QI: m32c dsp:16[sb] relative destination QI */
2176 /* dst32-16-8-FB-relative-Unprefixed-QI: m32c dsp:8[fb] relative destination QI */
2177 /* dst32-16-16-FB-relative-Unprefixed-QI: m32c dsp:16[fb] relative destination QI */
2178 /* dst32-16-8-An-relative-Unprefixed-QI: m32c dsp:8[An] relative destination QI */
2179 /* dst32-16-16-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2180 /* dst32-16-24-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2181 /* dst32-24-8-SB-relative-Unprefixed-QI: m32c dsp:8[sb] relative destination QI */
2182 /* dst32-24-16-SB-relative-Unprefixed-QI: m32c dsp:16[sb] relative destination QI */
2183 /* dst32-24-8-FB-relative-Unprefixed-QI: m32c dsp:8[fb] relative destination QI */
2184 /* dst32-24-16-FB-relative-Unprefixed-QI: m32c dsp:16[fb] relative destination QI */
2185 /* dst32-24-8-An-relative-Unprefixed-QI: m32c dsp:8[An] relative destination QI */
2186 /* dst32-24-16-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2187 /* dst32-24-24-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2188 /* dst32-32-8-SB-relative-Unprefixed-QI: m32c dsp:8[sb] relative destination QI */
2189 /* dst32-32-16-SB-relative-Unprefixed-QI: m32c dsp:16[sb] relative destination QI */
2190 /* dst32-32-8-FB-relative-Unprefixed-QI: m32c dsp:8[fb] relative destination QI */
2191 /* dst32-32-16-FB-relative-Unprefixed-QI: m32c dsp:16[fb] relative destination QI */
2192 /* dst32-32-8-An-relative-Unprefixed-QI: m32c dsp:8[An] relative destination QI */
2193 /* dst32-32-16-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2194 /* dst32-32-24-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2195 /* dst32-40-8-SB-relative-Unprefixed-QI: m32c dsp:8[sb] relative destination QI */
2196 /* dst32-40-16-SB-relative-Unprefixed-QI: m32c dsp:16[sb] relative destination QI */
2197 /* dst32-40-8-FB-relative-Unprefixed-QI: m32c dsp:8[fb] relative destination QI */
2198 /* dst32-40-16-FB-relative-Unprefixed-QI: m32c dsp:16[fb] relative destination QI */
2199 /* dst32-40-8-An-relative-Unprefixed-QI: m32c dsp:8[An] relative destination QI */
2200 /* dst32-40-16-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2201 /* dst32-40-24-An-relative-Unprefixed-QI: m32c dsp:16[An] relative destination QI */
2202 /* dst32-16-8-SB-relative-Unprefixed-HI: m32c dsp:8[sb] relative destination HI */
2203 /* dst32-16-16-SB-relative-Unprefixed-HI: m32c dsp:16[sb] relative destination HI */
2204 /* dst32-16-8-FB-relative-Unprefixed-HI: m32c dsp:8[fb] relative destination HI */
2205 /* dst32-16-16-FB-relative-Unprefixed-HI: m32c dsp:16[fb] relative destination HI */
2206 /* dst32-16-8-An-relative-Unprefixed-HI: m32c dsp:8[An] relative destination HI */
2207 /* dst32-16-16-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2208 /* dst32-16-24-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2209 /* dst32-24-8-SB-relative-Unprefixed-HI: m32c dsp:8[sb] relative destination HI */
2210 /* dst32-24-16-SB-relative-Unprefixed-HI: m32c dsp:16[sb] relative destination HI */
2211 /* dst32-24-8-FB-relative-Unprefixed-HI: m32c dsp:8[fb] relative destination HI */
2212 /* dst32-24-16-FB-relative-Unprefixed-HI: m32c dsp:16[fb] relative destination HI */
2213 /* dst32-24-8-An-relative-Unprefixed-HI: m32c dsp:8[An] relative destination HI */
2214 /* dst32-24-16-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2215 /* dst32-24-24-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2216 /* dst32-32-8-SB-relative-Unprefixed-HI: m32c dsp:8[sb] relative destination HI */
2217 /* dst32-32-16-SB-relative-Unprefixed-HI: m32c dsp:16[sb] relative destination HI */
2218 /* dst32-32-8-FB-relative-Unprefixed-HI: m32c dsp:8[fb] relative destination HI */
2219 /* dst32-32-16-FB-relative-Unprefixed-HI: m32c dsp:16[fb] relative destination HI */
2220 /* dst32-32-8-An-relative-Unprefixed-HI: m32c dsp:8[An] relative destination HI */
2221 /* dst32-32-16-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2222 /* dst32-32-24-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2223 /* dst32-40-8-SB-relative-Unprefixed-HI: m32c dsp:8[sb] relative destination HI */
2224 /* dst32-40-16-SB-relative-Unprefixed-HI: m32c dsp:16[sb] relative destination HI */
2225 /* dst32-40-8-FB-relative-Unprefixed-HI: m32c dsp:8[fb] relative destination HI */
2226 /* dst32-40-16-FB-relative-Unprefixed-HI: m32c dsp:16[fb] relative destination HI */
2227 /* dst32-40-8-An-relative-Unprefixed-HI: m32c dsp:8[An] relative destination HI */
2228 /* dst32-40-16-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2229 /* dst32-40-24-An-relative-Unprefixed-HI: m32c dsp:16[An] relative destination HI */
2230 /* dst32-16-8-SB-relative-Unprefixed-SI: m32c dsp:8[sb] relative destination SI */
2231 /* dst32-16-16-SB-relative-Unprefixed-SI: m32c dsp:16[sb] relative destination SI */
2232 /* dst32-16-8-FB-relative-Unprefixed-SI: m32c dsp:8[fb] relative destination SI */
2233 /* dst32-16-16-FB-relative-Unprefixed-SI: m32c dsp:16[fb] relative destination SI */
2234 /* dst32-16-8-An-relative-Unprefixed-SI: m32c dsp:8[An] relative destination SI */
2235 /* dst32-16-16-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2236 /* dst32-16-24-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2237 /* dst32-24-8-SB-relative-Unprefixed-SI: m32c dsp:8[sb] relative destination SI */
2238 /* dst32-24-16-SB-relative-Unprefixed-SI: m32c dsp:16[sb] relative destination SI */
2239 /* dst32-24-8-FB-relative-Unprefixed-SI: m32c dsp:8[fb] relative destination SI */
2240 /* dst32-24-16-FB-relative-Unprefixed-SI: m32c dsp:16[fb] relative destination SI */
2241 /* dst32-24-8-An-relative-Unprefixed-SI: m32c dsp:8[An] relative destination SI */
2242 /* dst32-24-16-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2243 /* dst32-24-24-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2244 /* dst32-32-8-SB-relative-Unprefixed-SI: m32c dsp:8[sb] relative destination SI */
2245 /* dst32-32-16-SB-relative-Unprefixed-SI: m32c dsp:16[sb] relative destination SI */
2246 /* dst32-32-8-FB-relative-Unprefixed-SI: m32c dsp:8[fb] relative destination SI */
2247 /* dst32-32-16-FB-relative-Unprefixed-SI: m32c dsp:16[fb] relative destination SI */
2248 /* dst32-32-8-An-relative-Unprefixed-SI: m32c dsp:8[An] relative destination SI */
2249 /* dst32-32-16-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2250 /* dst32-32-24-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2251 /* dst32-40-8-SB-relative-Unprefixed-SI: m32c dsp:8[sb] relative destination SI */
2252 /* dst32-40-16-SB-relative-Unprefixed-SI: m32c dsp:16[sb] relative destination SI */
2253 /* dst32-40-8-FB-relative-Unprefixed-SI: m32c dsp:8[fb] relative destination SI */
2254 /* dst32-40-16-FB-relative-Unprefixed-SI: m32c dsp:16[fb] relative destination SI */
2255 /* dst32-40-8-An-relative-Unprefixed-SI: m32c dsp:8[An] relative destination SI */
2256 /* dst32-40-16-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2257 /* dst32-40-24-An-relative-Unprefixed-SI: m32c dsp:16[An] relative destination SI */
2258 /* dst32-24-8-SB-relative-Prefixed-QI: m32c dsp:8[sb] relative destination QI */
2259 /* dst32-24-16-SB-relative-Prefixed-QI: m32c dsp:16[sb] relative destination QI */
2260 /* dst32-24-8-FB-relative-Prefixed-QI: m32c dsp:8[fb] relative destination QI */
2261 /* dst32-24-16-FB-relative-Prefixed-QI: m32c dsp:16[fb] relative destination QI */
2262 /* dst32-24-8-An-relative-Prefixed-QI: m32c dsp:8[An] relative destination QI */
2263 /* dst32-24-16-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2264 /* dst32-24-24-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2265 /* dst32-32-8-SB-relative-Prefixed-QI: m32c dsp:8[sb] relative destination QI */
2266 /* dst32-32-16-SB-relative-Prefixed-QI: m32c dsp:16[sb] relative destination QI */
2267 /* dst32-32-8-FB-relative-Prefixed-QI: m32c dsp:8[fb] relative destination QI */
2268 /* dst32-32-16-FB-relative-Prefixed-QI: m32c dsp:16[fb] relative destination QI */
2269 /* dst32-32-8-An-relative-Prefixed-QI: m32c dsp:8[An] relative destination QI */
2270 /* dst32-32-16-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2271 /* dst32-32-24-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2272 /* dst32-40-8-SB-relative-Prefixed-QI: m32c dsp:8[sb] relative destination QI */
2273 /* dst32-40-16-SB-relative-Prefixed-QI: m32c dsp:16[sb] relative destination QI */
2274 /* dst32-40-8-FB-relative-Prefixed-QI: m32c dsp:8[fb] relative destination QI */
2275 /* dst32-40-16-FB-relative-Prefixed-QI: m32c dsp:16[fb] relative destination QI */
2276 /* dst32-40-8-An-relative-Prefixed-QI: m32c dsp:8[An] relative destination QI */
2277 /* dst32-40-16-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2278 /* dst32-40-24-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2279 /* dst32-48-8-SB-relative-Prefixed-QI: m32c dsp:8[sb] relative destination QI */
2280 /* dst32-48-16-SB-relative-Prefixed-QI: m32c dsp:16[sb] relative destination QI */
2281 /* dst32-48-8-FB-relative-Prefixed-QI: m32c dsp:8[fb] relative destination QI */
2282 /* dst32-48-16-FB-relative-Prefixed-QI: m32c dsp:16[fb] relative destination QI */
2283 /* dst32-48-8-An-relative-Prefixed-QI: m32c dsp:8[An] relative destination QI */
2284 /* dst32-48-16-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2285 /* dst32-48-24-An-relative-Prefixed-QI: m32c dsp:16[An] relative destination QI */
2286 /* dst32-24-8-SB-relative-Prefixed-HI: m32c dsp:8[sb] relative destination HI */
2287 /* dst32-24-16-SB-relative-Prefixed-HI: m32c dsp:16[sb] relative destination HI */
2288 /* dst32-24-8-FB-relative-Prefixed-HI: m32c dsp:8[fb] relative destination HI */
2289 /* dst32-24-16-FB-relative-Prefixed-HI: m32c dsp:16[fb] relative destination HI */
2290 /* dst32-24-8-An-relative-Prefixed-HI: m32c dsp:8[An] relative destination HI */
2291 /* dst32-24-16-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2292 /* dst32-24-24-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2293 /* dst32-32-8-SB-relative-Prefixed-HI: m32c dsp:8[sb] relative destination HI */
2294 /* dst32-32-16-SB-relative-Prefixed-HI: m32c dsp:16[sb] relative destination HI */
2295 /* dst32-32-8-FB-relative-Prefixed-HI: m32c dsp:8[fb] relative destination HI */
2296 /* dst32-32-16-FB-relative-Prefixed-HI: m32c dsp:16[fb] relative destination HI */
2297 /* dst32-32-8-An-relative-Prefixed-HI: m32c dsp:8[An] relative destination HI */
2298 /* dst32-32-16-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2299 /* dst32-32-24-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2300 /* dst32-40-8-SB-relative-Prefixed-HI: m32c dsp:8[sb] relative destination HI */
2301 /* dst32-40-16-SB-relative-Prefixed-HI: m32c dsp:16[sb] relative destination HI */
2302 /* dst32-40-8-FB-relative-Prefixed-HI: m32c dsp:8[fb] relative destination HI */
2303 /* dst32-40-16-FB-relative-Prefixed-HI: m32c dsp:16[fb] relative destination HI */
2304 /* dst32-40-8-An-relative-Prefixed-HI: m32c dsp:8[An] relative destination HI */
2305 /* dst32-40-16-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2306 /* dst32-40-24-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2307 /* dst32-48-8-SB-relative-Prefixed-HI: m32c dsp:8[sb] relative destination HI */
2308 /* dst32-48-16-SB-relative-Prefixed-HI: m32c dsp:16[sb] relative destination HI */
2309 /* dst32-48-8-FB-relative-Prefixed-HI: m32c dsp:8[fb] relative destination HI */
2310 /* dst32-48-16-FB-relative-Prefixed-HI: m32c dsp:16[fb] relative destination HI */
2311 /* dst32-48-8-An-relative-Prefixed-HI: m32c dsp:8[An] relative destination HI */
2312 /* dst32-48-16-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2313 /* dst32-48-24-An-relative-Prefixed-HI: m32c dsp:16[An] relative destination HI */
2314 /* dst32-24-8-SB-relative-Prefixed-SI: m32c dsp:8[sb] relative destination SI */
2315 /* dst32-24-16-SB-relative-Prefixed-SI: m32c dsp:16[sb] relative destination SI */
2316 /* dst32-24-8-FB-relative-Prefixed-SI: m32c dsp:8[fb] relative destination SI */
2317 /* dst32-24-16-FB-relative-Prefixed-SI: m32c dsp:16[fb] relative destination SI */
2318 /* dst32-24-8-An-relative-Prefixed-SI: m32c dsp:8[An] relative destination SI */
2319 /* dst32-24-16-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2320 /* dst32-24-24-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2321 /* dst32-32-8-SB-relative-Prefixed-SI: m32c dsp:8[sb] relative destination SI */
2322 /* dst32-32-16-SB-relative-Prefixed-SI: m32c dsp:16[sb] relative destination SI */
2323 /* dst32-32-8-FB-relative-Prefixed-SI: m32c dsp:8[fb] relative destination SI */
2324 /* dst32-32-16-FB-relative-Prefixed-SI: m32c dsp:16[fb] relative destination SI */
2325 /* dst32-32-8-An-relative-Prefixed-SI: m32c dsp:8[An] relative destination SI */
2326 /* dst32-32-16-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2327 /* dst32-32-24-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2328 /* dst32-40-8-SB-relative-Prefixed-SI: m32c dsp:8[sb] relative destination SI */
2329 /* dst32-40-16-SB-relative-Prefixed-SI: m32c dsp:16[sb] relative destination SI */
2330 /* dst32-40-8-FB-relative-Prefixed-SI: m32c dsp:8[fb] relative destination SI */
2331 /* dst32-40-16-FB-relative-Prefixed-SI: m32c dsp:16[fb] relative destination SI */
2332 /* dst32-40-8-An-relative-Prefixed-SI: m32c dsp:8[An] relative destination SI */
2333 /* dst32-40-16-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2334 /* dst32-40-24-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2335 /* dst32-48-8-SB-relative-Prefixed-SI: m32c dsp:8[sb] relative destination SI */
2336 /* dst32-48-16-SB-relative-Prefixed-SI: m32c dsp:16[sb] relative destination SI */
2337 /* dst32-48-8-FB-relative-Prefixed-SI: m32c dsp:8[fb] relative destination SI */
2338 /* dst32-48-16-FB-relative-Prefixed-SI: m32c dsp:16[fb] relative destination SI */
2339 /* dst32-48-8-An-relative-Prefixed-SI: m32c dsp:8[An] relative destination SI */
2340 /* dst32-48-16-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2341 /* dst32-48-24-An-relative-Prefixed-SI: m32c dsp:16[An] relative destination SI */
2342 /* dst32-16-8-SB-relative-ExtUnprefixed-QI: m32c dsp:8[sb] relative destination QI */
2343 /* dst32-16-16-SB-relative-ExtUnprefixed-QI: m32c dsp:16[sb] relative destination QI */
2344 /* dst32-16-8-FB-relative-ExtUnprefixed-QI: m32c dsp:8[fb] relative destination QI */
2345 /* dst32-16-16-FB-relative-ExtUnprefixed-QI: m32c dsp:16[fb] relative destination QI */
2346 /* dst32-16-8-An-relative-ExtUnprefixed-QI: m32c dsp:8[An] relative destination QI */
2347 /* dst32-16-16-An-relative-ExtUnprefixed-QI: m32c dsp:16[An] relative destination QI */
2348 /* dst32-16-24-An-relative-ExtUnprefixed-QI: m32c dsp:16[An] relative destination QI */
2349 /* dst32-16-8-SB-relative-ExtUnprefixed-HI: m32c dsp:8[sb] relative destination HI */
2350 /* dst32-16-16-SB-relative-ExtUnprefixed-HI: m32c dsp:16[sb] relative destination HI */
2351 /* dst32-16-8-FB-relative-ExtUnprefixed-HI: m32c dsp:8[fb] relative destination HI */
2352 /* dst32-16-16-FB-relative-ExtUnprefixed-HI: m32c dsp:16[fb] relative destination HI */
2353 /* dst32-16-8-An-relative-ExtUnprefixed-HI: m32c dsp:8[An] relative destination HI */
2354 /* dst32-16-16-An-relative-ExtUnprefixed-HI: m32c dsp:16[An] relative destination HI */
2355 /* dst32-16-24-An-relative-ExtUnprefixed-HI: m32c dsp:16[An] relative destination HI */
2356 /* dst16-16-16-absolute-QI: m16c absolute address QI */
2357 /* dst16-24-16-absolute-QI: m16c absolute address QI */
2358 /* dst16-32-16-absolute-QI: m16c absolute address QI */
2359 /* dst16-40-16-absolute-QI: m16c absolute address QI */
2360 /* dst16-48-16-absolute-QI: m16c absolute address QI */
2361 /* dst16-16-16-absolute-HI: m16c absolute address HI */
2362 /* dst16-24-16-absolute-HI: m16c absolute address HI */
2363 /* dst16-32-16-absolute-HI: m16c absolute address HI */
2364 /* dst16-40-16-absolute-HI: m16c absolute address HI */
2365 /* dst16-48-16-absolute-HI: m16c absolute address HI */
2366 /* dst16-16-16-absolute-SI: m16c absolute address SI */
2367 /* dst16-24-16-absolute-SI: m16c absolute address SI */
2368 /* dst16-32-16-absolute-SI: m16c absolute address SI */
2369 /* dst16-40-16-absolute-SI: m16c absolute address SI */
2370 /* dst16-48-16-absolute-SI: m16c absolute address SI */
2371 /* dst16-16-16-absolute-Ext-QI: m16c absolute address QI */
2372 /* dst32-16-16-absolute-Unprefixed-QI: m32c absolute address QI */
2373 /* dst32-16-24-absolute-Unprefixed-QI: m32c absolute address QI */
2374 /* dst32-24-16-absolute-Unprefixed-QI: m32c absolute address QI */
2375 /* dst32-24-24-absolute-Unprefixed-QI: m32c absolute address QI */
2376 /* dst32-32-16-absolute-Unprefixed-QI: m32c absolute address QI */
2377 /* dst32-32-24-absolute-Unprefixed-QI: m32c absolute address QI */
2378 /* dst32-40-16-absolute-Unprefixed-QI: m32c absolute address QI */
2379 /* dst32-40-24-absolute-Unprefixed-QI: m32c absolute address QI */
2380 /* dst32-16-16-absolute-Unprefixed-HI: m32c absolute address HI */
2381 /* dst32-16-24-absolute-Unprefixed-HI: m32c absolute address HI */
2382 /* dst32-24-16-absolute-Unprefixed-HI: m32c absolute address HI */
2383 /* dst32-24-24-absolute-Unprefixed-HI: m32c absolute address HI */
2384 /* dst32-32-16-absolute-Unprefixed-HI: m32c absolute address HI */
2385 /* dst32-32-24-absolute-Unprefixed-HI: m32c absolute address HI */
2386 /* dst32-40-16-absolute-Unprefixed-HI: m32c absolute address HI */
2387 /* dst32-40-24-absolute-Unprefixed-HI: m32c absolute address HI */
2388 /* dst32-16-16-absolute-Unprefixed-SI: m32c absolute address SI */
2389 /* dst32-16-24-absolute-Unprefixed-SI: m32c absolute address SI */
2390 /* dst32-24-16-absolute-Unprefixed-SI: m32c absolute address SI */
2391 /* dst32-24-24-absolute-Unprefixed-SI: m32c absolute address SI */
2392 /* dst32-32-16-absolute-Unprefixed-SI: m32c absolute address SI */
2393 /* dst32-32-24-absolute-Unprefixed-SI: m32c absolute address SI */
2394 /* dst32-40-16-absolute-Unprefixed-SI: m32c absolute address SI */
2395 /* dst32-40-24-absolute-Unprefixed-SI: m32c absolute address SI */
2396 /* dst32-24-16-absolute-Prefixed-QI: m32c absolute address QI */
2397 /* dst32-24-24-absolute-Prefixed-QI: m32c absolute address QI */
2398 /* dst32-32-16-absolute-Prefixed-QI: m32c absolute address QI */
2399 /* dst32-32-24-absolute-Prefixed-QI: m32c absolute address QI */
2400 /* dst32-40-16-absolute-Prefixed-QI: m32c absolute address QI */
2401 /* dst32-40-24-absolute-Prefixed-QI: m32c absolute address QI */
2402 /* dst32-48-16-absolute-Prefixed-QI: m32c absolute address QI */
2403 /* dst32-48-24-absolute-Prefixed-QI: m32c absolute address QI */
2404 /* dst32-24-16-absolute-Prefixed-HI: m32c absolute address HI */
2405 /* dst32-24-24-absolute-Prefixed-HI: m32c absolute address HI */
2406 /* dst32-32-16-absolute-Prefixed-HI: m32c absolute address HI */
2407 /* dst32-32-24-absolute-Prefixed-HI: m32c absolute address HI */
2408 /* dst32-40-16-absolute-Prefixed-HI: m32c absolute address HI */
2409 /* dst32-40-24-absolute-Prefixed-HI: m32c absolute address HI */
2410 /* dst32-48-16-absolute-Prefixed-HI: m32c absolute address HI */
2411 /* dst32-48-24-absolute-Prefixed-HI: m32c absolute address HI */
2412 /* dst32-24-16-absolute-Prefixed-SI: m32c absolute address SI */
2413 /* dst32-24-24-absolute-Prefixed-SI: m32c absolute address SI */
2414 /* dst32-32-16-absolute-Prefixed-SI: m32c absolute address SI */
2415 /* dst32-32-24-absolute-Prefixed-SI: m32c absolute address SI */
2416 /* dst32-40-16-absolute-Prefixed-SI: m32c absolute address SI */
2417 /* dst32-40-24-absolute-Prefixed-SI: m32c absolute address SI */
2418 /* dst32-48-16-absolute-Prefixed-SI: m32c absolute address SI */
2419 /* dst32-48-24-absolute-Prefixed-SI: m32c absolute address SI */
2420 /* dst32-16-16-absolute-ExtUnprefixed-QI: m32c absolute address QI */
2421 /* dst32-16-24-absolute-ExtUnprefixed-QI: m32c absolute address QI */
2422 /* dst32-16-16-absolute-ExtUnprefixed-HI: m32c absolute address HI */
2423 /* dst32-16-24-absolute-ExtUnprefixed-HI: m32c absolute address HI */
2424 /* bit16-Rn-direct: m16c Rn direct bit */
2425 /* bit32-Rn-direct-Unprefixed: m32c Rn direct bit */
2426 /* bit32-Rn-direct-Prefixed: m32c Rn direct bit */
2427 /* bit16-An-direct: m16c An direct bit */
2428 /* bit32-An-direct-Unprefixed: m32c An direct bit */
2429 /* bit32-An-direct-Prefixed: m32c An direct bit */
2430 /* bit16-An-indirect: m16c An indirect bit */
2431 /* bit32-An-indirect-Unprefixed: m32c An indirect destination */
2432 /* bit32-An-indirect-Prefixed: m32c An indirect destination */
2433 /* bit16-16-8-SB-relative: m16c dsp:8[sb] relative bit xmode */
2434 /* bit16-16-16-SB-relative: m16c dsp:16[sb] relative bit xmode */
2435 /* bit16-16-8-FB-relative: m16c dsp:8[fb] relative bit xmode */
2436 /* bit16-16-8-An-relative: m16c dsp:8[An] relative bit xmode */
2437 /* bit16-16-16-An-relative: m16c dsp:16[An] relative bit xmode */
2438 /* bit32-16-11-SB-relative-Unprefixed: m32c bit,base:11[sb] relative bit */
2439 /* bit32-16-19-SB-relative-Unprefixed: m32c bit,base:19[sb] relative bit */
2440 /* bit32-16-11-FB-relative-Unprefixed: m32c bit,base:11[fb] relative bit */
2441 /* bit32-16-19-FB-relative-Unprefixed: m32c bit,base:19[fb] relative bit */
2442 /* bit32-16-11-An-relative-Unprefixed: m32c bit,base:11[An] relative bit */
2443 /* bit32-16-19-An-relative-Unprefixed: m32c bit,base:19[An] relative bit */
2444 /* bit32-16-27-An-relative-Unprefixed: m32c bit,base:27[An] relative bit */
2445 /* bit32-24-11-SB-relative-Prefixed: m32c bit,base:11[sb] relative bit */
2446 /* bit32-24-19-SB-relative-Prefixed: m32c bit,base:19[sb] relative bit */
2447 /* bit32-24-11-FB-relative-Prefixed: m32c bit,base:11[fb] relative bit */
2448 /* bit32-24-19-FB-relative-Prefixed: m32c bit,base:19[fb] relative bit */
2449 /* bit32-24-11-An-relative-Prefixed: m32c bit,base:11[An] relative bit */
2450 /* bit32-24-19-An-relative-Prefixed: m32c bit,base:19[An] relative bit */
2451 /* bit32-24-27-An-relative-Prefixed: m32c bit,base:27[An] relative bit */
2452 /* bit16-11-SB-relative-S: m16c bit,base:11[sb] relative bit */
2453 /* Rn16-push-S-derived: m16c r0[lh] for push,pop short version */
2454 /* An16-push-S-derived: m16c r0[lh] for push,pop short version */
2455 /* bit16-16-16-absolute: m16c absolute address */
2456 /* bit32-16-19-absolute-Unprefixed: m32c absolute address bit */
2457 /* bit32-16-27-absolute-Unprefixed: m32c absolute address bit */
2458 /* bit32-24-19-absolute-Prefixed: m32c absolute address bit */
2459 /* bit32-24-27-absolute-Prefixed: m32c absolute address bit */
2460 /* dst16-3-S-R0l-direct-QI: m16c R0l direct QI */
2461 /* dst16-3-S-R0h-direct-QI: m16c R0h direct QI */
2462 /* dst16-3-S-8-8-SB-relative-QI: m16c SB relative QI */
2463 /* dst16-3-S-8-8-FB-relative-QI: m16c FB relative QI */
2464 /* dst16-3-S-8-16-absolute-QI: m16c absolute address QI */
2465 /* dst16-3-S-16-8-SB-relative-QI: m16c SB relative QI */
2466 /* dst16-3-S-16-8-FB-relative-QI: m16c FB relative QI */
2467 /* dst16-3-S-16-16-absolute-QI: m16c absolute address QI */
2468 /* srcdst16-r0l-r0h-S-derived: m16c r0l/r0h operand for short format insns */
2469 /* dst32-2-S-R0l-direct-QI: m32c R0l direct QI */
2470 /* dst32-2-S-R0-direct-HI: m32c R0 direct HI */
2471 /* dst32-1-S-A0-direct-HI: m32c A0 direct HI */
2472 /* dst32-1-S-A1-direct-HI: m32c A1 direct HI */
2473 /* dst32-2-S-8-SB-relative-QI: m32c SB relative for short binary insns */
2474 /* dst32-2-S-8-FB-relative-QI: m32c FB relative for short binary insns */
2475 /* dst32-2-S-16-absolute-QI: m32c absolute address for short binary insns */
2476 /* dst32-2-S-8-SB-relative-HI: m32c SB relative for short binary insns */
2477 /* dst32-2-S-8-FB-relative-HI: m32c FB relative for short binary insns */
2478 /* dst32-2-S-16-absolute-HI: m32c absolute address for short binary insns */
2479 /* dst32-2-S-8-SB-relative-SI: m32c SB relative for short binary insns */
2480 /* dst32-2-S-8-FB-relative-SI: m32c FB relative for short binary insns */
2481 /* dst32-2-S-16-absolute-SI: m32c absolute address for short binary insns */
2482 /* src16-basic-QI: m16c source operand of size QI with no additional fields */
2483 /* src16-basic-HI: m16c source operand of size HI with no additional fields */
2484 /* src32-basic-Unprefixed-QI: m32c destination operand of size QI with no additional fields */
2485 /* src32-basic-Prefixed-QI: m32c destination operand of size QI with no additional fields */
2486 /* src32-basic-Unprefixed-HI: m32c destination operand of size HI with no additional fields */
2487 /* src32-basic-Prefixed-HI: m32c destination operand of size HI with no additional fields */
2488 /* src32-basic-Unprefixed-SI: m32c destination operand of size SI with no additional fields */
2489 /* src32-basic-Prefixed-SI: m32c destination operand of size SI with no additional fields */
2490 /* src32-basic-ExtPrefixed-QI: m32c source operand of size QI with no additional fields */
2491 /* src16-16-8-QI: m16c source operand of size QI with additional 8 bit fields at offset 16 */
2492 /* src16-16-16-QI: m16c source operand of size QI with additional 16 bit fields at offset 16 */
2493 /* src16-16-8-HI: m16c source operand of size HI with additional 8 bit fields at offset 16 */
2494 /* src16-16-16-HI: m16c source operand of size HI with additional 16 bit fields at offset 16 */
2495 /* src32-16-8-Unprefixed-QI: m32c source operand of size QI with additional 8 bit fields at offset 16 */
2496 /* src32-16-16-Unprefixed-QI: m32c source operand of size QI with additional 16 bit fields at offset 16 */
2497 /* src32-16-24-Unprefixed-QI: m32c source operand of size QI with additional 24 bit fields at offset 16 */
2498 /* src32-16-8-Unprefixed-HI: m32c source operand of size HI with additional 8 bit fields at offset 16 */
2499 /* src32-16-16-Unprefixed-HI: m32c source operand of size HI with additional 16 bit fields at offset 16 */
2500 /* src32-16-24-Unprefixed-HI: m32c source operand of size HI with additional 24 bit fields at offset 16 */
2501 /* src32-16-8-Unprefixed-SI: m32c source operand of size SI with additional 8 bit fields at offset 16 */
2502 /* src32-16-16-Unprefixed-SI: m32c source operand of size SI with additional 16 bit fields at offset 16 */
2503 /* src32-16-24-Unprefixed-SI: m32c source operand of size SI with additional 24 bit fields at offset 16 */
2504 /* src32-24-8-Prefixed-QI: m32c source operand of size QI with additional 8 bit fields at offset 24 */
2505 /* src32-24-16-Prefixed-QI: m32c source operand of size QI with additional 16 bit fields at offset 16 */
2506 /* src32-24-24-Prefixed-QI: m32c source operand of size QI with additional 24 bit fields at offset 16 */
2507 /* src32-24-8-Prefixed-HI: m32c source operand of size HI with additional 8 bit fields at offset 24 */
2508 /* src32-24-16-Prefixed-HI: m32c source operand of size HI with additional 16 bit fields at offset 16 */
2509 /* src32-24-24-Prefixed-HI: m32c source operand of size HI with additional 24 bit fields at offset 16 */
2510 /* src32-24-8-Prefixed-SI: m32c source operand of size SI with additional 8 bit fields at offset 24 */
2511 /* src32-24-16-Prefixed-SI: m32c source operand of size SI with additional 16 bit fields at offset 16 */
2512 /* src32-24-24-Prefixed-SI: m32c source operand of size SI with additional 24 bit fields at offset 16 */
2513 /* dst16-basic-QI: m16c destination operand of size QI with no additional fields */
2514 /* dst16-basic-HI: m16c destination operand of size HI with no additional fields */
2515 /* dst16-basic-SI: m16c destination operand of size SI with no additional fields */
2516 /* dst32-basic-Unprefixed-QI: m32c destination operand of size QI with no additional fields */
2517 /* dst32-basic-Prefixed-QI: m32c destination operand of size QI with no additional fields */
2518 /* dst32-basic-Unprefixed-HI: m32c destination operand of size HI with no additional fields */
2519 /* dst32-basic-Prefixed-HI: m32c destination operand of size HI with no additional fields */
2520 /* dst32-basic-Unprefixed-SI: m32c destination operand of size SI with no additional fields */
2521 /* dst32-basic-Prefixed-SI: m32c destination operand of size SI with no additional fields */
2522 /* dst16-16-QI: m16c destination operand of size QI with additional fields at offset 16 */
2523 /* dst16-16-8-QI: m16c destination operand of size QI with additional fields at offset 16 */
2524 /* dst16-16-16-QI: m16c destination operand of size QI with additional fields at offset 16 */
2525 /* dst16-16-HI: m16c destination operand of size HI with additional fields at offset 16 */
2526 /* dst16-16-8-HI: m16c destination operand of size HI with additional fields at offset 16 */
2527 /* dst16-16-16-HI: m16c destination operand of size HI with additional fields at offset 16 */
2528 /* dst16-16-SI: m16c destination operand of size SI with additional fields at offset 16 */
2529 /* dst16-16-8-SI: m16c destination operand of size SI with additional fields at offset 16 */
2530 /* dst16-16-16-SI: m16c destination operand of size SI with additional fields at offset 16 */
2531 /* dst16-16-Ext-QI: m16c destination operand of size QI for 'ext' insns with additional fields at offset 16 */
2532 /* dst16-An-indirect-Mova-HI: m16c addressof An indirect destination HI */
2533 /* dst16-16-8-An-relative-Mova-HI: m16c addressof dsp:8[An] relative destination HI */
2534 /* dst16-16-16-An-relative-Mova-HI: m16c addressof dsp:16[An] relative destination HI */
2535 /* dst16-16-8-SB-relative-Mova-HI: m16c addressof dsp:8[sb] relative destination HI */
2536 /* dst16-16-16-SB-relative-Mova-HI: m16c addressof dsp:16[sb] relative destination HI */
2537 /* dst16-16-8-FB-relative-Mova-HI: m16c addressof dsp:8[fb] relative destination HI */
2538 /* dst16-16-16-absolute-Mova-HI: m16c addressof absolute address HI */
2539 /* dst16-16-Mova-HI: m16c addressof destination operand of size HI with additional fields at offset 16 */
2540 /* dst32-An-indirect-Unprefixed-Mova-SI: m32c addressof An indirect destination SI */
2541 /* dst32-16-8-An-relative-Unprefixed-Mova-SI: m32c addressof dsp:8[An] relative destination SI */
2542 /* dst32-16-16-An-relative-Unprefixed-Mova-SI: m32c addressof dsp:16[An] relative destination SI */
2543 /* dst32-16-24-An-relative-Unprefixed-Mova-SI: addressof m32c dsp:16[An] relative destination SI */
2544 /* dst32-16-8-SB-relative-Unprefixed-Mova-SI: m32c addressof dsp:8[sb] relative destination SI */
2545 /* dst32-16-16-SB-relative-Unprefixed-Mova-SI: m32c addressof dsp:16[sb] relative destination SI */
2546 /* dst32-16-8-FB-relative-Unprefixed-Mova-SI: m32c addressof dsp:8[fb] relative destination SI */
2547 /* dst32-16-16-FB-relative-Unprefixed-Mova-SI: m32c addressof dsp:16[fb] relative destination SI */
2548 /* dst32-16-16-absolute-Unprefixed-Mova-SI: m32c addressof absolute address SI */
2549 /* dst32-16-24-absolute-Unprefixed-Mova-SI: m32c addressof absolute address SI */
2550 /* dst32-16-Unprefixed-Mova-SI: m32c addressof destination operand of size SI with additional fields at offset 16 */
2551 /* dst32-16-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 16 */
2552 /* dst32-16-8-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 16 */
2553 /* dst32-16-16-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 16 */
2554 /* dst32-16-24-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 16 */
2555 /* dst32-16-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 16 */
2556 /* dst32-16-8-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 16 */
2557 /* dst32-16-16-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 16 */
2558 /* dst32-16-24-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 16 */
2559 /* dst32-16-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 16 */
2560 /* dst32-16-8-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 16 */
2561 /* dst32-16-16-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 16 */
2562 /* dst32-16-24-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 16 */
2563 /* dst32-16-ExtUnprefixed-QI: m32c destination operand of size QI with additional fields at offset 16 */
2564 /* dst32-16-ExtUnprefixed-HI: m32c destination operand of size HI with additional fields at offset 16 */
2565 /* dst32-16-Unprefixed-Mulex-HI: m32c destination operand of size HI with additional fields at offset 16 */
2566 /* dst16-24-QI: m16c destination operand of size QI with additional fields at offset 24 */
2567 /* dst16-24-HI: m16c destination operand of size HI with additional fields at offset 24 */
2568 /* dst32-24-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 24 */
2569 /* dst32-24-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 24 */
2570 /* dst32-24-8-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 24 */
2571 /* dst32-24-16-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 24 */
2572 /* dst32-24-24-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 24 */
2573 /* dst32-24-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 24 */
2574 /* dst32-24-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 24 */
2575 /* dst32-24-8-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 24 */
2576 /* dst32-24-16-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 24 */
2577 /* dst32-24-24-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 24 */
2578 /* dst32-24-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 24 */
2579 /* dst32-24-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 24 */
2580 /* dst32-24-8-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 24 */
2581 /* dst32-24-16-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 24 */
2582 /* dst32-24-24-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 24 */
2583 /* dst16-32-QI: m16c destination operand of size QI with additional fields at offset 32 */
2584 /* dst16-32-HI: m16c destination operand of size HI with additional fields at offset 32 */
2585 /* dst32-32-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 32 */
2586 /* dst32-32-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 32 */
2587 /* dst32-32-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 32 */
2588 /* dst32-32-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 32 */
2589 /* dst32-32-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 32 */
2590 /* dst32-32-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 32 */
2591 /* dst32-40-Unprefixed-QI: m32c destination operand of size QI with additional fields at offset 32 */
2592 /* dst32-40-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 32 */
2593 /* dst32-40-Unprefixed-HI: m32c destination operand of size HI with additional fields at offset 32 */
2594 /* dst32-40-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 32 */
2595 /* dst32-40-Unprefixed-SI: m32c destination operand of size SI with additional fields at offset 32 */
2596 /* dst32-40-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 32 */
2597 /* dst32-48-Prefixed-QI: m32c destination operand of size QI with additional fields at offset 32 */
2598 /* dst32-48-Prefixed-HI: m32c destination operand of size HI with additional fields at offset 32 */
2599 /* dst32-48-Prefixed-SI: m32c destination operand of size SI with additional fields at offset 32 */
2600 /* bit16-16: m16c bit operand with possible additional fields at offset 24 */
2601 /* bit16-16-basic: m16c bit operand with no additional fields */
2602 /* bit16-16-8: m16c bit operand with possible additional fields at offset 24 */
2603 /* bit16-16-16: m16c bit operand with possible additional fields at offset 24 */
2604 /* bit32-16-Unprefixed: m32c bit operand with possible additional fields at offset 24 */
2605 /* bit32-24-Prefixed: m32c bit operand with possible additional fields at offset 24 */
2606 /* bit32-basic-Unprefixed: m32c bit operand with no additional fields */
2607 /* bit32-16-8-Unprefixed: m32c bit operand with 8 bit additional fields */
2608 /* bit32-16-16-Unprefixed: m32c bit operand with 16 bit additional fields */
2609 /* bit32-16-24-Unprefixed: m32c bit operand with 24 bit additional fields */
2610 /* src16-2-S: m16c source operand of size QI for short format insns */
2611 /* src32-2-S-QI: m32c source operand of size QI for short format insns */
2612 /* src32-2-S-HI: m32c source operand of size QI for short format insns */
2613 /* Dst16-3-S-8: m16c destination operand of size QI for short format insns */
2614 /* Dst16-3-S-16: m16c destination operand of size QI for short format insns */
2615 /* srcdst16-r0l-r0h-S: m16c r0l/r0h operand of size QI for short format insns */
2616 /* dst32-2-S-basic-QI: m32c r0l operand of size QI for short format binary insns */
2617 /* dst32-2-S-basic-HI: m32c r0 operand of size HI for short format binary insns */
2618 /* dst32-2-S-8-QI: m32c operand of size */
2619 /* dst32-2-S-16-QI: m32c operand of size */
2620 /* dst32-2-S-8-HI: m32c operand of size */
2621 /* dst32-2-S-16-HI: m32c operand of size */
2622 /* dst32-2-S-8-SI: m32c operand of size */
2623 /* dst32-2-S-16-SI: m32c operand of size */
2624 /* dst32-an-S: m32c An operand for short format binary insns */
2625 /* bit16-11-S: m16c bit operand for short format insns */
2626 /* Rn16-push-S-anyof: m16c bit operand for short format insns */
2627 /* An16-push-S-anyof: m16c bit operand for short format insns */
2630 { 0, { (const PTR) 0 } },
2637 /* The instruction table. */
2639 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
2640 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
2641 #define A(a) (1 << CGEN_INSN_##a)
2643 #define A(a) (1 << CGEN_INSN_/**/a)
2646 static const CGEN_IBASE m32c_cgen_insn_table[MAX_INSNS] =
2648 /* Special null first entry.
2649 A `num' value of zero is thus invalid.
2650 Also, the special `invalid' insn resides here. */
2651 { 0, 0, 0, 0, {0, {0}} },
2652 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
2654 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 32,
2655 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2657 /* extz ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
2659 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 32,
2660 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2662 /* extz ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
2664 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 32,
2665 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2667 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
2669 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 32,
2670 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2672 /* extz ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
2674 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 32,
2675 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2677 /* extz ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
2679 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 32,
2680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2682 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
2684 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 32,
2685 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2687 /* extz ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
2689 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 32,
2690 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2692 /* extz ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
2694 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 32,
2695 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2697 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
2699 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "extz", 40,
2700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2702 /* extz ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
2704 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "extz", 40,
2705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2707 /* extz ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
2709 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "extz", 40,
2710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2712 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
2714 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "extz", 48,
2715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2717 /* extz ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
2719 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "extz", 48,
2720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2722 /* extz ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
2724 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "extz", 48,
2725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2727 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
2729 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "extz", 56,
2730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2732 /* extz ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
2734 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "extz", 56,
2735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2737 /* extz ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
2739 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "extz", 56,
2740 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2742 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
2744 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "extz", 40,
2745 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2747 /* extz ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
2749 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "extz", 40,
2750 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2752 /* extz ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
2754 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "extz", 40,
2755 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2757 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
2759 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "extz", 48,
2760 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2762 /* extz ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
2764 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "extz", 48,
2765 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2767 /* extz ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
2769 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "extz", 48,
2770 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2772 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
2774 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "extz", 40,
2775 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2777 /* extz ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
2779 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "extz", 40,
2780 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2782 /* extz ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
2784 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "extz", 40,
2785 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2787 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
2789 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "extz", 48,
2790 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2792 /* extz ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
2794 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "extz", 48,
2795 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2797 /* extz ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
2799 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "extz", 48,
2800 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2802 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
2804 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "extz", 48,
2805 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2807 /* extz ${Dsp-24-u8}[sb],${Dsp-32-u16} */
2809 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "extz", 48,
2810 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2812 /* extz ${Dsp-24-s8}[fb],${Dsp-32-u16} */
2814 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "extz", 48,
2815 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2817 /* extz ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
2819 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "extz", 56,
2820 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2822 /* extz ${Dsp-24-u8}[sb],${Dsp-32-u24} */
2824 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "extz", 56,
2825 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2827 /* extz ${Dsp-24-s8}[fb],${Dsp-32-u24} */
2829 M32C_INSN_EXTZ32_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "extz32-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "extz", 56,
2830 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2832 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
2834 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 40,
2835 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2837 /* extz ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
2839 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 40,
2840 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2842 /* extz ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
2844 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 40,
2845 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2847 /* extz ${Dsp-24-u16},$Dst32RnPrefixedHI */
2849 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 40,
2850 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2852 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
2854 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 40,
2855 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2857 /* extz ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
2859 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 40,
2860 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2862 /* extz ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
2864 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 40,
2865 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2867 /* extz ${Dsp-24-u16},$Dst32AnPrefixedHI */
2869 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 40,
2870 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2872 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
2874 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 40,
2875 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2877 /* extz ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
2879 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 40,
2880 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2882 /* extz ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
2884 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 40,
2885 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2887 /* extz ${Dsp-24-u16},[$Dst32AnPrefixed] */
2889 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 40,
2890 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2892 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
2894 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "extz", 48,
2895 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2897 /* extz ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
2899 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "extz", 48,
2900 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2902 /* extz ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
2904 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "extz", 48,
2905 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2907 /* extz ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
2909 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "extz", 48,
2910 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2912 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
2914 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "extz", 56,
2915 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2917 /* extz ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
2919 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "extz", 56,
2920 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2922 /* extz ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
2924 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "extz", 56,
2925 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2927 /* extz ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
2929 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "extz", 56,
2930 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2932 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
2934 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "extz", 64,
2935 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2937 /* extz ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
2939 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "extz", 64,
2940 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2942 /* extz ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
2944 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "extz", 64,
2945 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2947 /* extz ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
2949 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "extz", 64,
2950 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2952 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
2954 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "extz", 48,
2955 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2957 /* extz ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
2959 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "extz", 48,
2960 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2962 /* extz ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
2964 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "extz", 48,
2965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2967 /* extz ${Dsp-24-u16},${Dsp-40-u8}[sb] */
2969 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "extz", 48,
2970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2972 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
2974 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "extz", 56,
2975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2977 /* extz ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
2979 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "extz", 56,
2980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2982 /* extz ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
2984 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "extz", 56,
2985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2987 /* extz ${Dsp-24-u16},${Dsp-40-u16}[sb] */
2989 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "extz", 56,
2990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2992 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
2994 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "extz", 48,
2995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
2997 /* extz ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
2999 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "extz", 48,
3000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3002 /* extz ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
3004 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "extz", 48,
3005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3007 /* extz ${Dsp-24-u16},${Dsp-40-s8}[fb] */
3009 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "extz", 48,
3010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3012 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
3014 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "extz", 56,
3015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3017 /* extz ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
3019 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "extz", 56,
3020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3022 /* extz ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
3024 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "extz", 56,
3025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3027 /* extz ${Dsp-24-u16},${Dsp-40-s16}[fb] */
3029 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "extz", 56,
3030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3032 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
3034 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "extz", 56,
3035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3037 /* extz ${Dsp-24-u16}[sb],${Dsp-40-u16} */
3039 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "extz", 56,
3040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3042 /* extz ${Dsp-24-s16}[fb],${Dsp-40-u16} */
3044 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "extz", 56,
3045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3047 /* extz ${Dsp-24-u16},${Dsp-40-u16} */
3049 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "extz", 56,
3050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3052 /* extz ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
3054 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "extz", 64,
3055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3057 /* extz ${Dsp-24-u16}[sb],${Dsp-40-u24} */
3059 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "extz", 64,
3060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3062 /* extz ${Dsp-24-s16}[fb],${Dsp-40-u24} */
3064 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "extz", 64,
3065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3067 /* extz ${Dsp-24-u16},${Dsp-40-u24} */
3069 M32C_INSN_EXTZ32_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "extz32-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "extz", 64,
3070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3072 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
3074 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 48,
3075 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3077 /* extz ${Dsp-24-u24},$Dst32RnPrefixedHI */
3079 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 48,
3080 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3082 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
3084 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 48,
3085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3087 /* extz ${Dsp-24-u24},$Dst32AnPrefixedHI */
3089 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 48,
3090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3092 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
3094 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 48,
3095 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3097 /* extz ${Dsp-24-u24},[$Dst32AnPrefixed] */
3099 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 48,
3100 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3102 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
3104 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-HI", "extz", 56,
3105 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3107 /* extz ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
3109 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-HI", "extz", 56,
3110 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3112 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
3114 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-HI", "extz", 64,
3115 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3117 /* extz ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
3119 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-HI", "extz", 64,
3120 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3122 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
3124 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-HI", "extz", 72,
3125 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3127 /* extz ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
3129 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-HI", "extz", 72,
3130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3132 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
3134 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-HI", "extz", 56,
3135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3137 /* extz ${Dsp-24-u24},${Dsp-48-u8}[sb] */
3139 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-HI", "extz", 56,
3140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3142 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
3144 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-HI", "extz", 64,
3145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3147 /* extz ${Dsp-24-u24},${Dsp-48-u16}[sb] */
3149 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-HI", "extz", 64,
3150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3152 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
3154 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-HI", "extz", 56,
3155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3157 /* extz ${Dsp-24-u24},${Dsp-48-s8}[fb] */
3159 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-HI", "extz", 56,
3160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3162 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
3164 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-HI", "extz", 64,
3165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3167 /* extz ${Dsp-24-u24},${Dsp-48-s16}[fb] */
3169 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-HI", "extz", 64,
3170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3172 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
3174 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-HI", "extz", 64,
3175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3177 /* extz ${Dsp-24-u24},${Dsp-48-u16} */
3179 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-HI", "extz", 64,
3180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3182 /* extz ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
3184 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-HI", "extz", 72,
3185 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3187 /* extz ${Dsp-24-u24},${Dsp-48-u24} */
3189 M32C_INSN_EXTZ32_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "extz32-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-HI", "extz", 72,
3190 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3192 /* extz $Src32RnPrefixedQI,$Dst32RnPrefixedHI */
3194 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 24,
3195 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3197 /* extz [$Src32AnPrefixed],$Dst32RnPrefixedHI */
3199 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "extz", 24,
3200 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3202 /* extz $Src32RnPrefixedQI,$Dst32AnPrefixedHI */
3204 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 24,
3205 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3207 /* extz [$Src32AnPrefixed],$Dst32AnPrefixedHI */
3209 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-HI", "extz", 24,
3210 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3212 /* extz $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
3214 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 24,
3215 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3217 /* extz [$Src32AnPrefixed],[$Dst32AnPrefixed] */
3219 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "extz", 24,
3220 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3222 /* extz $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
3224 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-HI", "extz", 32,
3225 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3227 /* extz [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
3229 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-HI", "extz", 32,
3230 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3232 /* extz $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
3234 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-HI", "extz", 40,
3235 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3237 /* extz [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
3239 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-HI", "extz", 40,
3240 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3242 /* extz $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
3244 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-HI", "extz", 48,
3245 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3247 /* extz [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
3249 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-HI", "extz", 48,
3250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3252 /* extz $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
3254 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-HI", "extz", 32,
3255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3257 /* extz [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
3259 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-HI", "extz", 32,
3260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3262 /* extz $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
3264 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-HI", "extz", 40,
3265 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3267 /* extz [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
3269 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-HI", "extz", 40,
3270 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3272 /* extz $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
3274 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-HI", "extz", 32,
3275 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3277 /* extz [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
3279 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-HI", "extz", 32,
3280 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3282 /* extz $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
3284 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-HI", "extz", 40,
3285 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3287 /* extz [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
3289 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-HI", "extz", 40,
3290 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3292 /* extz $Src32RnPrefixedQI,${Dsp-24-u16} */
3294 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-HI", "extz", 40,
3295 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3297 /* extz [$Src32AnPrefixed],${Dsp-24-u16} */
3299 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-HI", "extz", 40,
3300 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3302 /* extz $Src32RnPrefixedQI,${Dsp-24-u24} */
3304 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-HI", "extz", 48,
3305 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3307 /* extz [$Src32AnPrefixed],${Dsp-24-u24} */
3309 M32C_INSN_EXTZ32_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "extz32-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-HI", "extz", 48,
3310 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3312 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
3314 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 32,
3315 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3317 /* exts.b ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
3319 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 32,
3320 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3322 /* exts.b ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
3324 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 32,
3325 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3327 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
3329 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 32,
3330 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3332 /* exts.b ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
3334 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 32,
3335 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3337 /* exts.b ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
3339 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 32,
3340 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3342 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
3344 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 32,
3345 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3347 /* exts.b ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
3349 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 32,
3350 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3352 /* exts.b ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
3354 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 32,
3355 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3357 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
3359 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "exts.b", 40,
3360 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3362 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
3364 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "exts.b", 40,
3365 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3367 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
3369 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-HI", "exts.b", 40,
3370 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3372 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
3374 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "exts.b", 48,
3375 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3377 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
3379 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "exts.b", 48,
3380 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3382 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
3384 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-HI", "exts.b", 48,
3385 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3387 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
3389 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "exts.b", 56,
3390 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3392 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
3394 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "exts.b", 56,
3395 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3397 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
3399 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-HI", "exts.b", 56,
3400 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3402 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
3404 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "exts.b", 40,
3405 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3407 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
3409 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "exts.b", 40,
3410 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3412 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
3414 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-HI", "exts.b", 40,
3415 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3417 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
3419 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "exts.b", 48,
3420 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3422 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
3424 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "exts.b", 48,
3425 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3427 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
3429 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-HI", "exts.b", 48,
3430 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3432 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
3434 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "exts.b", 40,
3435 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3437 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
3439 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "exts.b", 40,
3440 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3442 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
3444 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-HI", "exts.b", 40,
3445 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3447 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
3449 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "exts.b", 48,
3450 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3452 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
3454 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "exts.b", 48,
3455 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3457 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
3459 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-HI", "exts.b", 48,
3460 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3462 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
3464 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "exts.b", 48,
3465 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3467 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u16} */
3469 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "exts.b", 48,
3470 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3472 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u16} */
3474 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-HI", "exts.b", 48,
3475 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3477 /* exts.b ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
3479 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "exts.b", 56,
3480 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3482 /* exts.b ${Dsp-24-u8}[sb],${Dsp-32-u24} */
3484 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "exts.b", 56,
3485 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3487 /* exts.b ${Dsp-24-s8}[fb],${Dsp-32-u24} */
3489 M32C_INSN_EXTS32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-HI", "exts.b", 56,
3490 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3492 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
3494 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 40,
3495 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3497 /* exts.b ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
3499 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 40,
3500 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3502 /* exts.b ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
3504 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 40,
3505 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3507 /* exts.b ${Dsp-24-u16},$Dst32RnPrefixedHI */
3509 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 40,
3510 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3512 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
3514 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 40,
3515 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3517 /* exts.b ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
3519 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 40,
3520 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3522 /* exts.b ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
3524 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 40,
3525 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3527 /* exts.b ${Dsp-24-u16},$Dst32AnPrefixedHI */
3529 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 40,
3530 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3532 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
3534 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 40,
3535 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3537 /* exts.b ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
3539 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 40,
3540 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3542 /* exts.b ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
3544 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 40,
3545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3547 /* exts.b ${Dsp-24-u16},[$Dst32AnPrefixed] */
3549 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 40,
3550 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3552 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
3554 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "exts.b", 48,
3555 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3557 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
3559 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "exts.b", 48,
3560 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3562 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
3564 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "exts.b", 48,
3565 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3567 /* exts.b ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
3569 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-HI", "exts.b", 48,
3570 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3572 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
3574 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "exts.b", 56,
3575 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3577 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
3579 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "exts.b", 56,
3580 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3582 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
3584 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "exts.b", 56,
3585 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3587 /* exts.b ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
3589 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-HI", "exts.b", 56,
3590 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3592 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
3594 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "exts.b", 64,
3595 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3597 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
3599 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "exts.b", 64,
3600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3602 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
3604 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "exts.b", 64,
3605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3607 /* exts.b ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
3609 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-HI", "exts.b", 64,
3610 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3612 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
3614 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "exts.b", 48,
3615 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3617 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
3619 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "exts.b", 48,
3620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3622 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
3624 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "exts.b", 48,
3625 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3627 /* exts.b ${Dsp-24-u16},${Dsp-40-u8}[sb] */
3629 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-HI", "exts.b", 48,
3630 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3632 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
3634 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "exts.b", 56,
3635 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3637 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
3639 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "exts.b", 56,
3640 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3642 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
3644 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "exts.b", 56,
3645 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3647 /* exts.b ${Dsp-24-u16},${Dsp-40-u16}[sb] */
3649 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-HI", "exts.b", 56,
3650 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3652 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
3654 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "exts.b", 48,
3655 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3657 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
3659 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "exts.b", 48,
3660 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3662 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
3664 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "exts.b", 48,
3665 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3667 /* exts.b ${Dsp-24-u16},${Dsp-40-s8}[fb] */
3669 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-HI", "exts.b", 48,
3670 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3672 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
3674 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "exts.b", 56,
3675 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3677 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
3679 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "exts.b", 56,
3680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3682 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
3684 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "exts.b", 56,
3685 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3687 /* exts.b ${Dsp-24-u16},${Dsp-40-s16}[fb] */
3689 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-HI", "exts.b", 56,
3690 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3692 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
3694 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "exts.b", 56,
3695 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3697 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u16} */
3699 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "exts.b", 56,
3700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3702 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u16} */
3704 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "exts.b", 56,
3705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3707 /* exts.b ${Dsp-24-u16},${Dsp-40-u16} */
3709 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-HI", "exts.b", 56,
3710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3712 /* exts.b ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
3714 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "exts.b", 64,
3715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3717 /* exts.b ${Dsp-24-u16}[sb],${Dsp-40-u24} */
3719 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "exts.b", 64,
3720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3722 /* exts.b ${Dsp-24-s16}[fb],${Dsp-40-u24} */
3724 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "exts.b", 64,
3725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3727 /* exts.b ${Dsp-24-u16},${Dsp-40-u24} */
3729 M32C_INSN_EXTS32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-HI", "exts.b", 64,
3730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3732 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
3734 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 48,
3735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3737 /* exts.b ${Dsp-24-u24},$Dst32RnPrefixedHI */
3739 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 48,
3740 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3742 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
3744 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 48,
3745 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3747 /* exts.b ${Dsp-24-u24},$Dst32AnPrefixedHI */
3749 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 48,
3750 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3752 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
3754 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 48,
3755 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3757 /* exts.b ${Dsp-24-u24},[$Dst32AnPrefixed] */
3759 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 48,
3760 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3762 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
3764 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-HI", "exts.b", 56,
3765 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3767 /* exts.b ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
3769 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-HI", "exts.b", 56,
3770 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3772 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
3774 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-HI", "exts.b", 64,
3775 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3777 /* exts.b ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
3779 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-HI", "exts.b", 64,
3780 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3782 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
3784 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-HI", "exts.b", 72,
3785 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3787 /* exts.b ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
3789 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-HI", "exts.b", 72,
3790 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3792 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
3794 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-HI", "exts.b", 56,
3795 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3797 /* exts.b ${Dsp-24-u24},${Dsp-48-u8}[sb] */
3799 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-HI", "exts.b", 56,
3800 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3802 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
3804 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-HI", "exts.b", 64,
3805 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3807 /* exts.b ${Dsp-24-u24},${Dsp-48-u16}[sb] */
3809 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-HI", "exts.b", 64,
3810 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3812 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
3814 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-HI", "exts.b", 56,
3815 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3817 /* exts.b ${Dsp-24-u24},${Dsp-48-s8}[fb] */
3819 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-HI", "exts.b", 56,
3820 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3822 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
3824 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-HI", "exts.b", 64,
3825 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3827 /* exts.b ${Dsp-24-u24},${Dsp-48-s16}[fb] */
3829 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-HI", "exts.b", 64,
3830 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3832 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
3834 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-HI", "exts.b", 64,
3835 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3837 /* exts.b ${Dsp-24-u24},${Dsp-48-u16} */
3839 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-HI", "exts.b", 64,
3840 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3842 /* exts.b ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
3844 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-HI", "exts.b", 72,
3845 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3847 /* exts.b ${Dsp-24-u24},${Dsp-48-u24} */
3849 M32C_INSN_EXTS32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "exts32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-HI", "exts.b", 72,
3850 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3852 /* exts.b $Src32RnPrefixedQI,$Dst32RnPrefixedHI */
3854 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 24,
3855 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3857 /* exts.b [$Src32AnPrefixed],$Dst32RnPrefixedHI */
3859 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-HI", "exts.b", 24,
3860 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3862 /* exts.b $Src32RnPrefixedQI,$Dst32AnPrefixedHI */
3864 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 24,
3865 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3867 /* exts.b [$Src32AnPrefixed],$Dst32AnPrefixedHI */
3869 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-HI", "exts.b", 24,
3870 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3872 /* exts.b $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
3874 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 24,
3875 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3877 /* exts.b [$Src32AnPrefixed],[$Dst32AnPrefixed] */
3879 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-HI", "exts.b", 24,
3880 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3882 /* exts.b $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
3884 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-HI", "exts.b", 32,
3885 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3887 /* exts.b [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
3889 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-HI", "exts.b", 32,
3890 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3892 /* exts.b $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
3894 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-HI", "exts.b", 40,
3895 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3897 /* exts.b [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
3899 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-HI", "exts.b", 40,
3900 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3902 /* exts.b $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
3904 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-HI", "exts.b", 48,
3905 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3907 /* exts.b [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
3909 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-HI", "exts.b", 48,
3910 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3912 /* exts.b $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
3914 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-HI", "exts.b", 32,
3915 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3917 /* exts.b [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
3919 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-HI", "exts.b", 32,
3920 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3922 /* exts.b $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
3924 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-HI", "exts.b", 40,
3925 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3927 /* exts.b [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
3929 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-HI", "exts.b", 40,
3930 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3932 /* exts.b $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
3934 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-HI", "exts.b", 32,
3935 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3937 /* exts.b [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
3939 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-HI", "exts.b", 32,
3940 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3942 /* exts.b $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
3944 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-HI", "exts.b", 40,
3945 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3947 /* exts.b [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
3949 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-HI", "exts.b", 40,
3950 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3952 /* exts.b $Src32RnPrefixedQI,${Dsp-24-u16} */
3954 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-HI", "exts.b", 40,
3955 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3957 /* exts.b [$Src32AnPrefixed],${Dsp-24-u16} */
3959 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-HI", "exts.b", 40,
3960 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3962 /* exts.b $Src32RnPrefixedQI,${Dsp-24-u24} */
3964 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-HI", "exts.b", 48,
3965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3967 /* exts.b [$Src32AnPrefixed],${Dsp-24-u24} */
3969 M32C_INSN_EXTS32_B_BASIC_EXTPREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "exts32.b-basic-ExtPrefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-HI", "exts.b", 48,
3970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3972 /* exts.w $Dst32RnExtUnprefixedHI */
3974 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_RN_DIRECT_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-Rn-direct-ExtUnprefixed-HI", "exts.w", 16,
3975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3977 /* exts.w $Dst32AnUnprefixedSI */
3979 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "exts32.w-16-ExtUnprefixed-dst32-An-direct-Unprefixed-SI", "exts.w", 16,
3980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3982 /* exts.w [$Dst32AnExtUnprefixed] */
3984 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_AN_INDIRECT_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-An-indirect-ExtUnprefixed-HI", "exts.w", 16,
3985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3987 /* exts.w ${Dsp-16-u8}[$Dst32AnExtUnprefixed] */
3989 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-8-An-relative-ExtUnprefixed-HI", "exts.w", 24,
3990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3992 /* exts.w ${Dsp-16-u16}[$Dst32AnExtUnprefixed] */
3994 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-16-An-relative-ExtUnprefixed-HI", "exts.w", 32,
3995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
3997 /* exts.w ${Dsp-16-u24}[$Dst32AnExtUnprefixed] */
3999 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-24-An-relative-ExtUnprefixed-HI", "exts.w", 40,
4000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4002 /* exts.w ${Dsp-16-u8}[sb] */
4004 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-8-SB-relative-ExtUnprefixed-HI", "exts.w", 24,
4005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4007 /* exts.w ${Dsp-16-u16}[sb] */
4009 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-16-SB-relative-ExtUnprefixed-HI", "exts.w", 32,
4010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4012 /* exts.w ${Dsp-16-s8}[fb] */
4014 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-8-FB-relative-ExtUnprefixed-HI", "exts.w", 24,
4015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4017 /* exts.w ${Dsp-16-s16}[fb] */
4019 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-16-FB-relative-ExtUnprefixed-HI", "exts.w", 32,
4020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4022 /* exts.w ${Dsp-16-u16} */
4024 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-16-absolute-ExtUnprefixed-HI", "exts.w", 32,
4025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4027 /* exts.w ${Dsp-16-u24} */
4029 M32C_INSN_EXTS32_W_16_EXTUNPREFIXED_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_HI, "exts32.w-16-ExtUnprefixed-dst32-16-24-absolute-ExtUnprefixed-HI", "exts.w", 40,
4030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4032 /* exts.b $Dst32RnExtUnprefixedQI */
4034 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_RN_DIRECT_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-Rn-direct-ExtUnprefixed-QI", "exts.b", 16,
4035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4037 /* exts.b $Dst32AnUnprefixedHI */
4039 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "exts32.b-16-ExtUnprefixed-dst32-An-direct-Unprefixed-HI", "exts.b", 16,
4040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4042 /* exts.b [$Dst32AnExtUnprefixed] */
4044 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_AN_INDIRECT_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-An-indirect-ExtUnprefixed-QI", "exts.b", 16,
4045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4047 /* exts.b ${Dsp-16-u8}[$Dst32AnExtUnprefixed] */
4049 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-8-An-relative-ExtUnprefixed-QI", "exts.b", 24,
4050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4052 /* exts.b ${Dsp-16-u16}[$Dst32AnExtUnprefixed] */
4054 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-16-An-relative-ExtUnprefixed-QI", "exts.b", 32,
4055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4057 /* exts.b ${Dsp-16-u24}[$Dst32AnExtUnprefixed] */
4059 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-24-An-relative-ExtUnprefixed-QI", "exts.b", 40,
4060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4062 /* exts.b ${Dsp-16-u8}[sb] */
4064 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-8-SB-relative-ExtUnprefixed-QI", "exts.b", 24,
4065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4067 /* exts.b ${Dsp-16-u16}[sb] */
4069 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-16-SB-relative-ExtUnprefixed-QI", "exts.b", 32,
4070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4072 /* exts.b ${Dsp-16-s8}[fb] */
4074 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-8-FB-relative-ExtUnprefixed-QI", "exts.b", 24,
4075 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4077 /* exts.b ${Dsp-16-s16}[fb] */
4079 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-16-FB-relative-ExtUnprefixed-QI", "exts.b", 32,
4080 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4082 /* exts.b ${Dsp-16-u16} */
4084 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-16-absolute-ExtUnprefixed-QI", "exts.b", 32,
4085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4087 /* exts.b ${Dsp-16-u24} */
4089 M32C_INSN_EXTS32_B_16_EXTUNPREFIXED_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_QI, "exts32.b-16-ExtUnprefixed-dst32-16-24-absolute-ExtUnprefixed-QI", "exts.b", 40,
4090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4092 /* exts.b $Dst16RnExtQI */
4094 M32C_INSN_EXTS16_B_16_EXT_DST16_RN_DIRECT_EXT_QI, "exts16.b-16-Ext-dst16-Rn-direct-Ext-QI", "exts.b", 16,
4095 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
4097 /* exts.b [$Dst16An] */
4099 M32C_INSN_EXTS16_B_16_EXT_DST16_AN_INDIRECT_EXT_QI, "exts16.b-16-Ext-dst16-An-indirect-Ext-QI", "exts.b", 16,
4100 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
4102 /* exts.b ${Dsp-16-u8}[$Dst16An] */
4104 M32C_INSN_EXTS16_B_16_EXT_DST16_16_8_AN_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-8-An-relative-Ext-QI", "exts.b", 24,
4105 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
4107 /* exts.b ${Dsp-16-u16}[$Dst16An] */
4109 M32C_INSN_EXTS16_B_16_EXT_DST16_16_16_AN_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-16-An-relative-Ext-QI", "exts.b", 32,
4110 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
4112 /* exts.b ${Dsp-16-u8}[sb] */
4114 M32C_INSN_EXTS16_B_16_EXT_DST16_16_8_SB_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-8-SB-relative-Ext-QI", "exts.b", 24,
4115 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
4117 /* exts.b ${Dsp-16-u16}[sb] */
4119 M32C_INSN_EXTS16_B_16_EXT_DST16_16_16_SB_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-16-SB-relative-Ext-QI", "exts.b", 32,
4120 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
4122 /* exts.b ${Dsp-16-s8}[fb] */
4124 M32C_INSN_EXTS16_B_16_EXT_DST16_16_8_FB_RELATIVE_EXT_QI, "exts16.b-16-Ext-dst16-16-8-FB-relative-Ext-QI", "exts.b", 24,
4125 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
4127 /* exts.b ${Dsp-16-u16} */
4129 M32C_INSN_EXTS16_B_16_EXT_DST16_16_16_ABSOLUTE_EXT_QI, "exts16.b-16-Ext-dst16-16-16-absolute-Ext-QI", "exts.b", 32,
4130 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
4132 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
4134 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 24,
4135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4137 /* xor.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
4139 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 24,
4140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4142 /* xor.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
4144 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 24,
4145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4147 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
4149 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 24,
4150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4152 /* xor.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
4154 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 24,
4155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4157 /* xor.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
4159 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 24,
4160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4162 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
4164 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 24,
4165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4167 /* xor.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
4169 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 24,
4170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4172 /* xor.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
4174 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 24,
4175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4177 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
4179 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "xor.w", 32,
4180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4182 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
4184 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "xor.w", 32,
4185 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4187 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
4189 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "xor.w", 32,
4190 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4192 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
4194 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "xor.w", 40,
4195 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4197 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
4199 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "xor.w", 40,
4200 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4202 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
4204 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "xor.w", 40,
4205 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4207 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
4209 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "xor.w", 48,
4210 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4212 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
4214 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "xor.w", 48,
4215 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4217 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
4219 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "xor.w", 48,
4220 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4222 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
4224 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "xor.w", 32,
4225 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4227 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
4229 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "xor.w", 32,
4230 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4232 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
4234 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "xor.w", 32,
4235 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4237 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
4239 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "xor.w", 40,
4240 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4242 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
4244 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "xor.w", 40,
4245 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4247 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
4249 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "xor.w", 40,
4250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4252 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
4254 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "xor.w", 32,
4255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4257 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
4259 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "xor.w", 32,
4260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4262 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
4264 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "xor.w", 32,
4265 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4267 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
4269 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "xor.w", 40,
4270 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4272 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
4274 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "xor.w", 40,
4275 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4277 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
4279 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "xor.w", 40,
4280 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4282 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
4284 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "xor.w", 40,
4285 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4287 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
4289 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "xor.w", 40,
4290 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4292 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
4294 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "xor.w", 40,
4295 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4297 /* xor.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
4299 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "xor.w", 48,
4300 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4302 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
4304 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "xor.w", 48,
4305 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4307 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
4309 M32C_INSN_XOR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "xor.w", 48,
4310 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4312 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
4314 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32,
4315 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4317 /* xor.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
4319 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32,
4320 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4322 /* xor.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
4324 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32,
4325 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4327 /* xor.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
4329 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32,
4330 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4332 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
4334 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 32,
4335 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4337 /* xor.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
4339 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 32,
4340 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4342 /* xor.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
4344 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 32,
4345 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4347 /* xor.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
4349 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 32,
4350 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4352 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
4354 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 32,
4355 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4357 /* xor.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
4359 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 32,
4360 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4362 /* xor.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
4364 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 32,
4365 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4367 /* xor.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
4369 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 32,
4370 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4372 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
4374 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "xor.w", 40,
4375 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4377 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
4379 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "xor.w", 40,
4380 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4382 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
4384 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "xor.w", 40,
4385 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4387 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
4389 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "xor.w", 40,
4390 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4392 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
4394 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "xor.w", 48,
4395 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4397 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
4399 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "xor.w", 48,
4400 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4402 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
4404 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "xor.w", 48,
4405 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4407 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
4409 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "xor.w", 48,
4410 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4412 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
4414 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "xor.w", 56,
4415 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4417 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
4419 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "xor.w", 56,
4420 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4422 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
4424 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "xor.w", 56,
4425 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4427 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
4429 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "xor.w", 56,
4430 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4432 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
4434 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "xor.w", 40,
4435 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4437 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
4439 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "xor.w", 40,
4440 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4442 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
4444 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "xor.w", 40,
4445 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4447 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
4449 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "xor.w", 40,
4450 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4452 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
4454 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "xor.w", 48,
4455 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4457 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
4459 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "xor.w", 48,
4460 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4462 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
4464 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "xor.w", 48,
4465 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4467 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
4469 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "xor.w", 48,
4470 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4472 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
4474 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "xor.w", 40,
4475 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4477 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
4479 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "xor.w", 40,
4480 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4482 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
4484 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "xor.w", 40,
4485 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4487 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
4489 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "xor.w", 40,
4490 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4492 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
4494 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "xor.w", 48,
4495 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4497 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
4499 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "xor.w", 48,
4500 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4502 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
4504 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "xor.w", 48,
4505 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4507 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
4509 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "xor.w", 48,
4510 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4512 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
4514 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "xor.w", 48,
4515 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4517 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
4519 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "xor.w", 48,
4520 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4522 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
4524 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "xor.w", 48,
4525 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4527 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
4529 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "xor.w", 48,
4530 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4532 /* xor.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
4534 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "xor.w", 56,
4535 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4537 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
4539 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "xor.w", 56,
4540 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4542 /* xor.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
4544 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "xor.w", 56,
4545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4547 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
4549 M32C_INSN_XOR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "xor.w", 56,
4550 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4552 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
4554 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 40,
4555 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4557 /* xor.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
4559 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 40,
4560 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4562 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
4564 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 40,
4565 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4567 /* xor.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
4569 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 40,
4570 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4572 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
4574 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 40,
4575 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4577 /* xor.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
4579 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 40,
4580 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4582 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
4584 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "xor.w", 48,
4585 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4587 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
4589 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "xor.w", 48,
4590 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4592 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
4594 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "xor.w", 56,
4595 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4597 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
4599 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "xor.w", 56,
4600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4602 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
4604 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "xor.w", 64,
4605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4607 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
4609 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "xor.w", 64,
4610 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4612 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
4614 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "xor.w", 48,
4615 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4617 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
4619 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "xor.w", 48,
4620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4622 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
4624 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "xor.w", 56,
4625 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4627 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
4629 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "xor.w", 56,
4630 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4632 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
4634 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "xor.w", 48,
4635 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4637 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
4639 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "xor.w", 48,
4640 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4642 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
4644 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "xor.w", 56,
4645 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4647 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
4649 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "xor.w", 56,
4650 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4652 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
4654 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "xor.w", 56,
4655 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4657 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
4659 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "xor.w", 56,
4660 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4662 /* xor.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
4664 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "xor.w", 64,
4665 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4667 /* xor.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
4669 M32C_INSN_XOR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "xor.w", 64,
4670 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4672 /* xor.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
4674 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 16,
4675 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4677 /* xor.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
4679 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 16,
4680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4682 /* xor.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
4684 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "xor.w", 16,
4685 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4687 /* xor.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
4689 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 16,
4690 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4692 /* xor.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
4694 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 16,
4695 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4697 /* xor.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
4699 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "xor.w", 16,
4700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4702 /* xor.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
4704 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 16,
4705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4707 /* xor.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
4709 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 16,
4710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4712 /* xor.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
4714 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "xor.w", 16,
4715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4717 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
4719 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "xor.w", 24,
4720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4722 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
4724 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "xor.w", 24,
4725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4727 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
4729 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "xor.w", 24,
4730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4732 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
4734 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "xor.w", 32,
4735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4737 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
4739 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "xor.w", 32,
4740 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4742 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
4744 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "xor.w", 32,
4745 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4747 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
4749 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "xor.w", 40,
4750 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4752 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
4754 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "xor.w", 40,
4755 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4757 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
4759 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "xor.w", 40,
4760 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4762 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
4764 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "xor.w", 24,
4765 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4767 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
4769 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "xor.w", 24,
4770 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4772 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
4774 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "xor.w", 24,
4775 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4777 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
4779 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "xor.w", 32,
4780 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4782 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
4784 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "xor.w", 32,
4785 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4787 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
4789 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "xor.w", 32,
4790 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4792 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
4794 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "xor.w", 24,
4795 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4797 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
4799 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "xor.w", 24,
4800 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4802 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
4804 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "xor.w", 24,
4805 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4807 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
4809 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "xor.w", 32,
4810 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4812 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
4814 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "xor.w", 32,
4815 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4817 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
4819 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "xor.w", 32,
4820 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4822 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
4824 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "xor.w", 32,
4825 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4827 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
4829 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "xor.w", 32,
4830 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4832 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
4834 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "xor.w", 32,
4835 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4837 /* xor.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
4839 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "xor.w", 40,
4840 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4842 /* xor.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
4844 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "xor.w", 40,
4845 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4847 /* xor.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
4849 M32C_INSN_XOR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "xor.w", 40,
4850 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4852 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
4854 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 24,
4855 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4857 /* xor.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
4859 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 24,
4860 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4862 /* xor.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
4864 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 24,
4865 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4867 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
4869 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 24,
4870 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4872 /* xor.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
4874 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 24,
4875 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4877 /* xor.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
4879 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 24,
4880 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4882 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
4884 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 24,
4885 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4887 /* xor.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
4889 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 24,
4890 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4892 /* xor.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
4894 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 24,
4895 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4897 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
4899 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "xor.b", 32,
4900 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4902 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
4904 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "xor.b", 32,
4905 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4907 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
4909 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "xor.b", 32,
4910 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4912 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
4914 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "xor.b", 40,
4915 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4917 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
4919 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "xor.b", 40,
4920 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4922 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
4924 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "xor.b", 40,
4925 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4927 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
4929 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "xor.b", 48,
4930 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4932 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
4934 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "xor.b", 48,
4935 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4937 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
4939 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "xor.b", 48,
4940 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4942 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
4944 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "xor.b", 32,
4945 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4947 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
4949 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "xor.b", 32,
4950 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4952 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
4954 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "xor.b", 32,
4955 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4957 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
4959 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "xor.b", 40,
4960 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4962 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
4964 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "xor.b", 40,
4965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4967 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
4969 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "xor.b", 40,
4970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4972 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
4974 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "xor.b", 32,
4975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4977 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
4979 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "xor.b", 32,
4980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4982 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
4984 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "xor.b", 32,
4985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4987 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
4989 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "xor.b", 40,
4990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4992 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
4994 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "xor.b", 40,
4995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
4997 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
4999 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "xor.b", 40,
5000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5002 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
5004 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "xor.b", 40,
5005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5007 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
5009 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "xor.b", 40,
5010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5012 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
5014 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "xor.b", 40,
5015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5017 /* xor.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
5019 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "xor.b", 48,
5020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5022 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
5024 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "xor.b", 48,
5025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5027 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
5029 M32C_INSN_XOR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "xor.b", 48,
5030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5032 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
5034 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 32,
5035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5037 /* xor.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
5039 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 32,
5040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5042 /* xor.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
5044 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 32,
5045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5047 /* xor.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
5049 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 32,
5050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5052 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
5054 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 32,
5055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5057 /* xor.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
5059 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 32,
5060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5062 /* xor.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
5064 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 32,
5065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5067 /* xor.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
5069 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 32,
5070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5072 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
5074 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 32,
5075 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5077 /* xor.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
5079 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 32,
5080 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5082 /* xor.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
5084 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 32,
5085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5087 /* xor.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
5089 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 32,
5090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5092 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
5094 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "xor.b", 40,
5095 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5097 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
5099 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "xor.b", 40,
5100 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5102 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
5104 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "xor.b", 40,
5105 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5107 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
5109 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "xor.b", 40,
5110 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5112 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
5114 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "xor.b", 48,
5115 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5117 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
5119 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "xor.b", 48,
5120 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5122 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
5124 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "xor.b", 48,
5125 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5127 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
5129 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "xor.b", 48,
5130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5132 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
5134 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "xor.b", 56,
5135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5137 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
5139 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "xor.b", 56,
5140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5142 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
5144 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "xor.b", 56,
5145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5147 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
5149 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "xor.b", 56,
5150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5152 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
5154 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "xor.b", 40,
5155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5157 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
5159 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "xor.b", 40,
5160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5162 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
5164 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "xor.b", 40,
5165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5167 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
5169 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "xor.b", 40,
5170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5172 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
5174 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "xor.b", 48,
5175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5177 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
5179 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "xor.b", 48,
5180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5182 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
5184 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "xor.b", 48,
5185 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5187 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
5189 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "xor.b", 48,
5190 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5192 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
5194 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "xor.b", 40,
5195 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5197 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
5199 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "xor.b", 40,
5200 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5202 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
5204 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "xor.b", 40,
5205 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5207 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
5209 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "xor.b", 40,
5210 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5212 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
5214 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "xor.b", 48,
5215 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5217 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
5219 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "xor.b", 48,
5220 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5222 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
5224 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "xor.b", 48,
5225 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5227 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
5229 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "xor.b", 48,
5230 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5232 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
5234 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "xor.b", 48,
5235 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5237 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
5239 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "xor.b", 48,
5240 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5242 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
5244 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "xor.b", 48,
5245 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5247 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
5249 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "xor.b", 48,
5250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5252 /* xor.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
5254 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "xor.b", 56,
5255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5257 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
5259 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "xor.b", 56,
5260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5262 /* xor.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
5264 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "xor.b", 56,
5265 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5267 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
5269 M32C_INSN_XOR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "xor.b", 56,
5270 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5272 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
5274 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 40,
5275 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5277 /* xor.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
5279 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 40,
5280 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5282 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
5284 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 40,
5285 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5287 /* xor.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
5289 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 40,
5290 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5292 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
5294 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 40,
5295 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5297 /* xor.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
5299 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 40,
5300 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5302 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
5304 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "xor.b", 48,
5305 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5307 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
5309 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "xor.b", 48,
5310 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5312 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
5314 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "xor.b", 56,
5315 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5317 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
5319 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "xor.b", 56,
5320 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5322 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
5324 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "xor.b", 64,
5325 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5327 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
5329 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "xor.b", 64,
5330 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5332 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
5334 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "xor.b", 48,
5335 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5337 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
5339 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "xor.b", 48,
5340 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5342 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
5344 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "xor.b", 56,
5345 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5347 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
5349 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "xor.b", 56,
5350 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5352 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
5354 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "xor.b", 48,
5355 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5357 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
5359 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "xor.b", 48,
5360 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5362 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
5364 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "xor.b", 56,
5365 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5367 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
5369 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "xor.b", 56,
5370 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5372 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
5374 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "xor.b", 56,
5375 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5377 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
5379 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "xor.b", 56,
5380 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5382 /* xor.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
5384 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "xor.b", 64,
5385 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5387 /* xor.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
5389 M32C_INSN_XOR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "xor.b", 64,
5390 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5392 /* xor.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
5394 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 16,
5395 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5397 /* xor.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
5399 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 16,
5400 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5402 /* xor.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
5404 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "xor.b", 16,
5405 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5407 /* xor.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
5409 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 16,
5410 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5412 /* xor.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
5414 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 16,
5415 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5417 /* xor.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
5419 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "xor.b", 16,
5420 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5422 /* xor.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
5424 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 16,
5425 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5427 /* xor.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
5429 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 16,
5430 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5432 /* xor.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
5434 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "xor.b", 16,
5435 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5437 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
5439 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "xor.b", 24,
5440 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5442 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
5444 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "xor.b", 24,
5445 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5447 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
5449 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "xor.b", 24,
5450 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5452 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
5454 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "xor.b", 32,
5455 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5457 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
5459 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "xor.b", 32,
5460 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5462 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
5464 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "xor.b", 32,
5465 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5467 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
5469 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "xor.b", 40,
5470 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5472 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
5474 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "xor.b", 40,
5475 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5477 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
5479 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "xor.b", 40,
5480 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5482 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
5484 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "xor.b", 24,
5485 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5487 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
5489 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "xor.b", 24,
5490 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5492 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
5494 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "xor.b", 24,
5495 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5497 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
5499 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "xor.b", 32,
5500 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5502 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
5504 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "xor.b", 32,
5505 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5507 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
5509 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "xor.b", 32,
5510 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5512 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
5514 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "xor.b", 24,
5515 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5517 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
5519 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "xor.b", 24,
5520 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5522 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
5524 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "xor.b", 24,
5525 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5527 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
5529 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "xor.b", 32,
5530 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5532 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
5534 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "xor.b", 32,
5535 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5537 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
5539 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "xor.b", 32,
5540 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5542 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
5544 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "xor.b", 32,
5545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5547 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
5549 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "xor.b", 32,
5550 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5552 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
5554 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "xor.b", 32,
5555 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5557 /* xor.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
5559 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "xor.b", 40,
5560 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5562 /* xor.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
5564 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "xor.b", 40,
5565 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5567 /* xor.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
5569 M32C_INSN_XOR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "xor.b", 40,
5570 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
5572 /* xor.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
5574 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "xor.w", 24,
5575 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5577 /* xor.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
5579 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "xor.w", 24,
5580 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5582 /* xor.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
5584 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "xor.w", 24,
5585 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5587 /* xor.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
5589 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "xor.w", 24,
5590 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5592 /* xor.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
5594 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "xor.w", 24,
5595 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5597 /* xor.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
5599 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "xor.w", 24,
5600 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5602 /* xor.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
5604 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "xor.w", 24,
5605 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5607 /* xor.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
5609 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "xor.w", 24,
5610 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5612 /* xor.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
5614 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "xor.w", 24,
5615 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5617 /* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
5619 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "xor.w", 32,
5620 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5622 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
5624 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "xor.w", 32,
5625 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5627 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
5629 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "xor.w", 32,
5630 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5632 /* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
5634 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "xor.w", 40,
5635 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5637 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
5639 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "xor.w", 40,
5640 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5642 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
5644 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "xor.w", 40,
5645 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5647 /* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
5649 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "xor.w", 32,
5650 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5652 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
5654 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "xor.w", 32,
5655 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5657 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
5659 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "xor.w", 32,
5660 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5662 /* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
5664 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "xor.w", 40,
5665 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5667 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
5669 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "xor.w", 40,
5670 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5672 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
5674 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "xor.w", 40,
5675 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5677 /* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
5679 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "xor.w", 32,
5680 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5682 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
5684 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "xor.w", 32,
5685 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5687 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
5689 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "xor.w", 32,
5690 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5692 /* xor.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
5694 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "xor16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "xor.w", 40,
5695 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5697 /* xor.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
5699 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "xor16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "xor.w", 40,
5700 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5702 /* xor.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
5704 M32C_INSN_XOR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "xor16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "xor.w", 40,
5705 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5707 /* xor.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
5709 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "xor.w", 32,
5710 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5712 /* xor.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
5714 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "xor.w", 32,
5715 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5717 /* xor.w${G} ${Dsp-16-u16},$Dst16RnHI */
5719 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "xor.w", 32,
5720 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5722 /* xor.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
5724 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "xor.w", 32,
5725 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5727 /* xor.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
5729 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "xor.w", 32,
5730 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5732 /* xor.w${G} ${Dsp-16-u16},$Dst16AnHI */
5734 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "xor.w", 32,
5735 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5737 /* xor.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
5739 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "xor.w", 32,
5740 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5742 /* xor.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
5744 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "xor.w", 32,
5745 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5747 /* xor.w${G} ${Dsp-16-u16},[$Dst16An] */
5749 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "xor.w", 32,
5750 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5752 /* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
5754 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "xor.w", 40,
5755 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5757 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
5759 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "xor.w", 40,
5760 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5762 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
5764 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "xor.w", 40,
5765 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5767 /* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
5769 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "xor.w", 48,
5770 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5772 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
5774 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "xor.w", 48,
5775 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5777 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
5779 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "xor.w", 48,
5780 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5782 /* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
5784 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "xor.w", 40,
5785 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5787 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
5789 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "xor.w", 40,
5790 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5792 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
5794 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "xor.w", 40,
5795 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5797 /* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
5799 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "xor.w", 48,
5800 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5802 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
5804 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "xor.w", 48,
5805 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5807 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
5809 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "xor.w", 48,
5810 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5812 /* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
5814 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "xor.w", 40,
5815 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5817 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
5819 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "xor.w", 40,
5820 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5822 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
5824 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "xor.w", 40,
5825 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5827 /* xor.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
5829 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "xor16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "xor.w", 48,
5830 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5832 /* xor.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
5834 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "xor16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "xor.w", 48,
5835 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5837 /* xor.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
5839 M32C_INSN_XOR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "xor16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "xor.w", 48,
5840 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5842 /* xor.w${G} $Src16RnHI,$Dst16RnHI */
5844 M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "xor.w", 16,
5845 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5847 /* xor.w${G} $Src16AnHI,$Dst16RnHI */
5849 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "xor.w", 16,
5850 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5852 /* xor.w${G} [$Src16An],$Dst16RnHI */
5854 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "xor.w", 16,
5855 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5857 /* xor.w${G} $Src16RnHI,$Dst16AnHI */
5859 M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "xor.w", 16,
5860 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5862 /* xor.w${G} $Src16AnHI,$Dst16AnHI */
5864 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "xor.w", 16,
5865 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5867 /* xor.w${G} [$Src16An],$Dst16AnHI */
5869 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "xor.w", 16,
5870 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5872 /* xor.w${G} $Src16RnHI,[$Dst16An] */
5874 M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "xor.w", 16,
5875 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5877 /* xor.w${G} $Src16AnHI,[$Dst16An] */
5879 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "xor.w", 16,
5880 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5882 /* xor.w${G} [$Src16An],[$Dst16An] */
5884 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "xor.w", 16,
5885 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5887 /* xor.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
5889 M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "xor.w", 24,
5890 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5892 /* xor.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
5894 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "xor.w", 24,
5895 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5897 /* xor.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
5899 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "xor.w", 24,
5900 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5902 /* xor.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
5904 M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "xor.w", 32,
5905 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5907 /* xor.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
5909 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "xor.w", 32,
5910 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5912 /* xor.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
5914 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "xor.w", 32,
5915 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5917 /* xor.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
5919 M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "xor.w", 24,
5920 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5922 /* xor.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
5924 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "xor.w", 24,
5925 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5927 /* xor.w${G} [$Src16An],${Dsp-16-u8}[sb] */
5929 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "xor.w", 24,
5930 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5932 /* xor.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
5934 M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "xor.w", 32,
5935 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5937 /* xor.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
5939 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "xor.w", 32,
5940 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5942 /* xor.w${G} [$Src16An],${Dsp-16-u16}[sb] */
5944 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "xor.w", 32,
5945 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5947 /* xor.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
5949 M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "xor.w", 24,
5950 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5952 /* xor.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
5954 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "xor.w", 24,
5955 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5957 /* xor.w${G} [$Src16An],${Dsp-16-s8}[fb] */
5959 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "xor.w", 24,
5960 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5962 /* xor.w${G} $Src16RnHI,${Dsp-16-u16} */
5964 M32C_INSN_XOR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "xor16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "xor.w", 32,
5965 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5967 /* xor.w${G} $Src16AnHI,${Dsp-16-u16} */
5969 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "xor16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "xor.w", 32,
5970 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5972 /* xor.w${G} [$Src16An],${Dsp-16-u16} */
5974 M32C_INSN_XOR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "xor16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "xor.w", 32,
5975 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5977 /* xor.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
5979 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "xor.b", 24,
5980 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5982 /* xor.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
5984 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "xor.b", 24,
5985 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5987 /* xor.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
5989 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "xor.b", 24,
5990 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5992 /* xor.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
5994 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "xor.b", 24,
5995 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
5997 /* xor.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
5999 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "xor.b", 24,
6000 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6002 /* xor.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
6004 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "xor.b", 24,
6005 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6007 /* xor.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
6009 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "xor.b", 24,
6010 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6012 /* xor.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
6014 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "xor.b", 24,
6015 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6017 /* xor.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
6019 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "xor.b", 24,
6020 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6022 /* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
6024 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "xor.b", 32,
6025 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6027 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
6029 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "xor.b", 32,
6030 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6032 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
6034 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "xor.b", 32,
6035 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6037 /* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
6039 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "xor.b", 40,
6040 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6042 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
6044 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "xor.b", 40,
6045 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6047 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
6049 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "xor.b", 40,
6050 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6052 /* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
6054 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "xor.b", 32,
6055 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6057 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
6059 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "xor.b", 32,
6060 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6062 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
6064 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "xor.b", 32,
6065 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6067 /* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
6069 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "xor.b", 40,
6070 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6072 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
6074 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "xor.b", 40,
6075 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6077 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
6079 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "xor.b", 40,
6080 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6082 /* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
6084 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "xor.b", 32,
6085 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6087 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
6089 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "xor.b", 32,
6090 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6092 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
6094 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "xor.b", 32,
6095 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6097 /* xor.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
6099 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "xor16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "xor.b", 40,
6100 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6102 /* xor.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
6104 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "xor16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "xor.b", 40,
6105 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6107 /* xor.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
6109 M32C_INSN_XOR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "xor16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "xor.b", 40,
6110 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6112 /* xor.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
6114 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "xor.b", 32,
6115 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6117 /* xor.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
6119 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "xor.b", 32,
6120 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6122 /* xor.b${G} ${Dsp-16-u16},$Dst16RnQI */
6124 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "xor.b", 32,
6125 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6127 /* xor.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
6129 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "xor.b", 32,
6130 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6132 /* xor.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
6134 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "xor.b", 32,
6135 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6137 /* xor.b${G} ${Dsp-16-u16},$Dst16AnQI */
6139 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "xor.b", 32,
6140 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6142 /* xor.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
6144 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "xor.b", 32,
6145 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6147 /* xor.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
6149 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "xor.b", 32,
6150 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6152 /* xor.b${G} ${Dsp-16-u16},[$Dst16An] */
6154 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "xor.b", 32,
6155 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6157 /* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
6159 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "xor.b", 40,
6160 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6162 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
6164 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "xor.b", 40,
6165 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6167 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
6169 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "xor.b", 40,
6170 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6172 /* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
6174 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "xor.b", 48,
6175 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6177 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
6179 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "xor.b", 48,
6180 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6182 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
6184 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "xor.b", 48,
6185 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6187 /* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
6189 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "xor.b", 40,
6190 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6192 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
6194 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "xor.b", 40,
6195 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6197 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
6199 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "xor.b", 40,
6200 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6202 /* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
6204 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "xor.b", 48,
6205 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6207 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
6209 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "xor.b", 48,
6210 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6212 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
6214 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "xor.b", 48,
6215 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6217 /* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
6219 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "xor.b", 40,
6220 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6222 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
6224 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "xor.b", 40,
6225 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6227 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
6229 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "xor.b", 40,
6230 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6232 /* xor.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
6234 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "xor16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "xor.b", 48,
6235 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6237 /* xor.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
6239 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "xor16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "xor.b", 48,
6240 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6242 /* xor.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
6244 M32C_INSN_XOR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "xor16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "xor.b", 48,
6245 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6247 /* xor.b${G} $Src16RnQI,$Dst16RnQI */
6249 M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "xor.b", 16,
6250 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6252 /* xor.b${G} $Src16AnQI,$Dst16RnQI */
6254 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "xor.b", 16,
6255 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6257 /* xor.b${G} [$Src16An],$Dst16RnQI */
6259 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "xor.b", 16,
6260 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6262 /* xor.b${G} $Src16RnQI,$Dst16AnQI */
6264 M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "xor.b", 16,
6265 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6267 /* xor.b${G} $Src16AnQI,$Dst16AnQI */
6269 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "xor.b", 16,
6270 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6272 /* xor.b${G} [$Src16An],$Dst16AnQI */
6274 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "xor.b", 16,
6275 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6277 /* xor.b${G} $Src16RnQI,[$Dst16An] */
6279 M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "xor.b", 16,
6280 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6282 /* xor.b${G} $Src16AnQI,[$Dst16An] */
6284 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "xor.b", 16,
6285 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6287 /* xor.b${G} [$Src16An],[$Dst16An] */
6289 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "xor.b", 16,
6290 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6292 /* xor.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
6294 M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "xor.b", 24,
6295 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6297 /* xor.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
6299 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "xor.b", 24,
6300 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6302 /* xor.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
6304 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "xor.b", 24,
6305 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6307 /* xor.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
6309 M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "xor.b", 32,
6310 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6312 /* xor.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
6314 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "xor.b", 32,
6315 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6317 /* xor.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
6319 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "xor.b", 32,
6320 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6322 /* xor.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
6324 M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "xor.b", 24,
6325 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6327 /* xor.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
6329 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "xor.b", 24,
6330 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6332 /* xor.b${G} [$Src16An],${Dsp-16-u8}[sb] */
6334 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "xor.b", 24,
6335 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6337 /* xor.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
6339 M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "xor.b", 32,
6340 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6342 /* xor.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
6344 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "xor.b", 32,
6345 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6347 /* xor.b${G} [$Src16An],${Dsp-16-u16}[sb] */
6349 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "xor.b", 32,
6350 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6352 /* xor.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
6354 M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "xor.b", 24,
6355 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6357 /* xor.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
6359 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "xor.b", 24,
6360 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6362 /* xor.b${G} [$Src16An],${Dsp-16-s8}[fb] */
6364 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "xor.b", 24,
6365 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6367 /* xor.b${G} $Src16RnQI,${Dsp-16-u16} */
6369 M32C_INSN_XOR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "xor16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "xor.b", 32,
6370 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6372 /* xor.b${G} $Src16AnQI,${Dsp-16-u16} */
6374 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "xor16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "xor.b", 32,
6375 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6377 /* xor.b${G} [$Src16An],${Dsp-16-u16} */
6379 M32C_INSN_XOR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "xor16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "xor.b", 32,
6380 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6382 /* xor.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
6384 M32C_INSN_XOR32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "xor32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "xor.w", 32,
6385 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6387 /* xor.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
6389 M32C_INSN_XOR32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "xor32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "xor.w", 32,
6390 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6392 /* xor.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
6394 M32C_INSN_XOR32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "xor32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "xor.w", 32,
6395 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6397 /* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
6399 M32C_INSN_XOR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "xor.w", 40,
6400 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6402 /* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
6404 M32C_INSN_XOR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "xor.w", 40,
6405 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6407 /* xor.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
6409 M32C_INSN_XOR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "xor.w", 40,
6410 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6412 /* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
6414 M32C_INSN_XOR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "xor.w", 48,
6415 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6417 /* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
6419 M32C_INSN_XOR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "xor.w", 48,
6420 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6422 /* xor.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
6424 M32C_INSN_XOR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "xor.w", 48,
6425 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6427 /* xor.w${G} #${Imm-32-HI},${Dsp-16-u16} */
6429 M32C_INSN_XOR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xor32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "xor.w", 48,
6430 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6432 /* xor.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
6434 M32C_INSN_XOR32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xor32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "xor.w", 56,
6435 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6437 /* xor.w${G} #${Imm-40-HI},${Dsp-16-u24} */
6439 M32C_INSN_XOR32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xor32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "xor.w", 56,
6440 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6442 /* xor.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
6444 M32C_INSN_XOR32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "xor32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "xor.b", 24,
6445 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6447 /* xor.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
6449 M32C_INSN_XOR32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "xor32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "xor.b", 24,
6450 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6452 /* xor.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
6454 M32C_INSN_XOR32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "xor32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "xor.b", 24,
6455 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6457 /* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
6459 M32C_INSN_XOR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "xor.b", 32,
6460 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6462 /* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
6464 M32C_INSN_XOR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "xor.b", 32,
6465 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6467 /* xor.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
6469 M32C_INSN_XOR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "xor.b", 32,
6470 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6472 /* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
6474 M32C_INSN_XOR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "xor.b", 40,
6475 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6477 /* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
6479 M32C_INSN_XOR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "xor.b", 40,
6480 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6482 /* xor.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
6484 M32C_INSN_XOR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "xor.b", 40,
6485 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6487 /* xor.b${G} #${Imm-32-QI},${Dsp-16-u16} */
6489 M32C_INSN_XOR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xor32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "xor.b", 40,
6490 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6492 /* xor.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
6494 M32C_INSN_XOR32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xor32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "xor.b", 48,
6495 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6497 /* xor.b${G} #${Imm-40-QI},${Dsp-16-u24} */
6499 M32C_INSN_XOR32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xor32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "xor.b", 48,
6500 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6502 /* xor.w${G} #${Imm-16-HI},$Dst16RnHI */
6504 M32C_INSN_XOR16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "xor16.w-imm-G-basic-dst16-Rn-direct-HI", "xor.w", 32,
6505 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6507 /* xor.w${G} #${Imm-16-HI},$Dst16AnHI */
6509 M32C_INSN_XOR16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "xor16.w-imm-G-basic-dst16-An-direct-HI", "xor.w", 32,
6510 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6512 /* xor.w${G} #${Imm-16-HI},[$Dst16An] */
6514 M32C_INSN_XOR16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "xor16.w-imm-G-basic-dst16-An-indirect-HI", "xor.w", 32,
6515 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6517 /* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
6519 M32C_INSN_XOR16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "xor16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "xor.w", 40,
6520 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6522 /* xor.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
6524 M32C_INSN_XOR16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "xor16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "xor.w", 40,
6525 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6527 /* xor.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
6529 M32C_INSN_XOR16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "xor16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "xor.w", 40,
6530 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6532 /* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
6534 M32C_INSN_XOR16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "xor16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "xor.w", 48,
6535 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6537 /* xor.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
6539 M32C_INSN_XOR16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "xor16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "xor.w", 48,
6540 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6542 /* xor.w${G} #${Imm-32-HI},${Dsp-16-u16} */
6544 M32C_INSN_XOR16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "xor16.w-imm-G-16-16-dst16-16-16-absolute-HI", "xor.w", 48,
6545 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6547 /* xor.b${G} #${Imm-16-QI},$Dst16RnQI */
6549 M32C_INSN_XOR16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "xor16.b-imm-G-basic-dst16-Rn-direct-QI", "xor.b", 24,
6550 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6552 /* xor.b${G} #${Imm-16-QI},$Dst16AnQI */
6554 M32C_INSN_XOR16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "xor16.b-imm-G-basic-dst16-An-direct-QI", "xor.b", 24,
6555 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6557 /* xor.b${G} #${Imm-16-QI},[$Dst16An] */
6559 M32C_INSN_XOR16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "xor16.b-imm-G-basic-dst16-An-indirect-QI", "xor.b", 24,
6560 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6562 /* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
6564 M32C_INSN_XOR16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "xor16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "xor.b", 32,
6565 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6567 /* xor.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
6569 M32C_INSN_XOR16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "xor16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "xor.b", 32,
6570 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6572 /* xor.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
6574 M32C_INSN_XOR16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "xor16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "xor.b", 32,
6575 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6577 /* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
6579 M32C_INSN_XOR16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "xor16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "xor.b", 40,
6580 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6582 /* xor.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
6584 M32C_INSN_XOR16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "xor16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "xor.b", 40,
6585 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6587 /* xor.b${G} #${Imm-32-QI},${Dsp-16-u16} */
6589 M32C_INSN_XOR16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "xor16.b-imm-G-16-16-dst16-16-16-absolute-QI", "xor.b", 40,
6590 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
6592 /* xchg.w r3,$Dst32RnUnprefixedHI */
6594 M32C_INSN_XCHG32W_R3_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-r3-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16,
6595 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6597 /* xchg.w r3,$Dst32AnUnprefixedHI */
6599 M32C_INSN_XCHG32W_R3_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-r3-dst32-An-direct-Unprefixed-HI", "xchg.w", 16,
6600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6602 /* xchg.w r3,[$Dst32AnUnprefixed] */
6604 M32C_INSN_XCHG32W_R3_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-r3-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16,
6605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6607 /* xchg.w r3,${Dsp-16-u8}[$Dst32AnUnprefixed] */
6609 M32C_INSN_XCHG32W_R3_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24,
6610 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6612 /* xchg.w r3,${Dsp-16-u16}[$Dst32AnUnprefixed] */
6614 M32C_INSN_XCHG32W_R3_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32,
6615 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6617 /* xchg.w r3,${Dsp-16-u24}[$Dst32AnUnprefixed] */
6619 M32C_INSN_XCHG32W_R3_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40,
6620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6622 /* xchg.w r3,${Dsp-16-u8}[sb] */
6624 M32C_INSN_XCHG32W_R3_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24,
6625 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6627 /* xchg.w r3,${Dsp-16-u16}[sb] */
6629 M32C_INSN_XCHG32W_R3_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32,
6630 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6632 /* xchg.w r3,${Dsp-16-s8}[fb] */
6634 M32C_INSN_XCHG32W_R3_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24,
6635 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6637 /* xchg.w r3,${Dsp-16-s16}[fb] */
6639 M32C_INSN_XCHG32W_R3_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32,
6640 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6642 /* xchg.w r3,${Dsp-16-u16} */
6644 M32C_INSN_XCHG32W_R3_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32,
6645 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6647 /* xchg.w r3,${Dsp-16-u24} */
6649 M32C_INSN_XCHG32W_R3_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r3-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40,
6650 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6652 /* xchg.w r2,$Dst32RnUnprefixedHI */
6654 M32C_INSN_XCHG32W_R2_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-r2-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16,
6655 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6657 /* xchg.w r2,$Dst32AnUnprefixedHI */
6659 M32C_INSN_XCHG32W_R2_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-r2-dst32-An-direct-Unprefixed-HI", "xchg.w", 16,
6660 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6662 /* xchg.w r2,[$Dst32AnUnprefixed] */
6664 M32C_INSN_XCHG32W_R2_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-r2-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16,
6665 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6667 /* xchg.w r2,${Dsp-16-u8}[$Dst32AnUnprefixed] */
6669 M32C_INSN_XCHG32W_R2_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24,
6670 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6672 /* xchg.w r2,${Dsp-16-u16}[$Dst32AnUnprefixed] */
6674 M32C_INSN_XCHG32W_R2_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32,
6675 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6677 /* xchg.w r2,${Dsp-16-u24}[$Dst32AnUnprefixed] */
6679 M32C_INSN_XCHG32W_R2_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40,
6680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6682 /* xchg.w r2,${Dsp-16-u8}[sb] */
6684 M32C_INSN_XCHG32W_R2_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24,
6685 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6687 /* xchg.w r2,${Dsp-16-u16}[sb] */
6689 M32C_INSN_XCHG32W_R2_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32,
6690 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6692 /* xchg.w r2,${Dsp-16-s8}[fb] */
6694 M32C_INSN_XCHG32W_R2_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24,
6695 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6697 /* xchg.w r2,${Dsp-16-s16}[fb] */
6699 M32C_INSN_XCHG32W_R2_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32,
6700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6702 /* xchg.w r2,${Dsp-16-u16} */
6704 M32C_INSN_XCHG32W_R2_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32,
6705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6707 /* xchg.w r2,${Dsp-16-u24} */
6709 M32C_INSN_XCHG32W_R2_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r2-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40,
6710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6712 /* xchg.w a1,$Dst32RnUnprefixedHI */
6714 M32C_INSN_XCHG32W_A1_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-a1-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16,
6715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6717 /* xchg.w a1,$Dst32AnUnprefixedHI */
6719 M32C_INSN_XCHG32W_A1_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-a1-dst32-An-direct-Unprefixed-HI", "xchg.w", 16,
6720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6722 /* xchg.w a1,[$Dst32AnUnprefixed] */
6724 M32C_INSN_XCHG32W_A1_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-a1-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16,
6725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6727 /* xchg.w a1,${Dsp-16-u8}[$Dst32AnUnprefixed] */
6729 M32C_INSN_XCHG32W_A1_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24,
6730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6732 /* xchg.w a1,${Dsp-16-u16}[$Dst32AnUnprefixed] */
6734 M32C_INSN_XCHG32W_A1_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32,
6735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6737 /* xchg.w a1,${Dsp-16-u24}[$Dst32AnUnprefixed] */
6739 M32C_INSN_XCHG32W_A1_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40,
6740 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6742 /* xchg.w a1,${Dsp-16-u8}[sb] */
6744 M32C_INSN_XCHG32W_A1_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24,
6745 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6747 /* xchg.w a1,${Dsp-16-u16}[sb] */
6749 M32C_INSN_XCHG32W_A1_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32,
6750 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6752 /* xchg.w a1,${Dsp-16-s8}[fb] */
6754 M32C_INSN_XCHG32W_A1_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24,
6755 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6757 /* xchg.w a1,${Dsp-16-s16}[fb] */
6759 M32C_INSN_XCHG32W_A1_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32,
6760 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6762 /* xchg.w a1,${Dsp-16-u16} */
6764 M32C_INSN_XCHG32W_A1_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32,
6765 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6767 /* xchg.w a1,${Dsp-16-u24} */
6769 M32C_INSN_XCHG32W_A1_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-a1-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40,
6770 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6772 /* xchg.w a0,$Dst32RnUnprefixedHI */
6774 M32C_INSN_XCHG32W_A0_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-a0-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16,
6775 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6777 /* xchg.w a0,$Dst32AnUnprefixedHI */
6779 M32C_INSN_XCHG32W_A0_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-a0-dst32-An-direct-Unprefixed-HI", "xchg.w", 16,
6780 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6782 /* xchg.w a0,[$Dst32AnUnprefixed] */
6784 M32C_INSN_XCHG32W_A0_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-a0-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16,
6785 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6787 /* xchg.w a0,${Dsp-16-u8}[$Dst32AnUnprefixed] */
6789 M32C_INSN_XCHG32W_A0_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24,
6790 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6792 /* xchg.w a0,${Dsp-16-u16}[$Dst32AnUnprefixed] */
6794 M32C_INSN_XCHG32W_A0_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32,
6795 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6797 /* xchg.w a0,${Dsp-16-u24}[$Dst32AnUnprefixed] */
6799 M32C_INSN_XCHG32W_A0_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40,
6800 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6802 /* xchg.w a0,${Dsp-16-u8}[sb] */
6804 M32C_INSN_XCHG32W_A0_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24,
6805 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6807 /* xchg.w a0,${Dsp-16-u16}[sb] */
6809 M32C_INSN_XCHG32W_A0_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32,
6810 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6812 /* xchg.w a0,${Dsp-16-s8}[fb] */
6814 M32C_INSN_XCHG32W_A0_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24,
6815 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6817 /* xchg.w a0,${Dsp-16-s16}[fb] */
6819 M32C_INSN_XCHG32W_A0_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32,
6820 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6822 /* xchg.w a0,${Dsp-16-u16} */
6824 M32C_INSN_XCHG32W_A0_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32,
6825 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6827 /* xchg.w a0,${Dsp-16-u24} */
6829 M32C_INSN_XCHG32W_A0_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-a0-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40,
6830 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6832 /* xchg.w r1,$Dst32RnUnprefixedHI */
6834 M32C_INSN_XCHG32W_R1_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-r1-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16,
6835 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6837 /* xchg.w r1,$Dst32AnUnprefixedHI */
6839 M32C_INSN_XCHG32W_R1_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-r1-dst32-An-direct-Unprefixed-HI", "xchg.w", 16,
6840 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6842 /* xchg.w r1,[$Dst32AnUnprefixed] */
6844 M32C_INSN_XCHG32W_R1_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-r1-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16,
6845 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6847 /* xchg.w r1,${Dsp-16-u8}[$Dst32AnUnprefixed] */
6849 M32C_INSN_XCHG32W_R1_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24,
6850 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6852 /* xchg.w r1,${Dsp-16-u16}[$Dst32AnUnprefixed] */
6854 M32C_INSN_XCHG32W_R1_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32,
6855 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6857 /* xchg.w r1,${Dsp-16-u24}[$Dst32AnUnprefixed] */
6859 M32C_INSN_XCHG32W_R1_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40,
6860 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6862 /* xchg.w r1,${Dsp-16-u8}[sb] */
6864 M32C_INSN_XCHG32W_R1_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24,
6865 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6867 /* xchg.w r1,${Dsp-16-u16}[sb] */
6869 M32C_INSN_XCHG32W_R1_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32,
6870 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6872 /* xchg.w r1,${Dsp-16-s8}[fb] */
6874 M32C_INSN_XCHG32W_R1_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24,
6875 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6877 /* xchg.w r1,${Dsp-16-s16}[fb] */
6879 M32C_INSN_XCHG32W_R1_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32,
6880 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6882 /* xchg.w r1,${Dsp-16-u16} */
6884 M32C_INSN_XCHG32W_R1_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32,
6885 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6887 /* xchg.w r1,${Dsp-16-u24} */
6889 M32C_INSN_XCHG32W_R1_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r1-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40,
6890 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6892 /* xchg.w r0,$Dst32RnUnprefixedHI */
6894 M32C_INSN_XCHG32W_R0_DST32_RN_DIRECT_UNPREFIXED_HI, "xchg32w-r0-dst32-Rn-direct-Unprefixed-HI", "xchg.w", 16,
6895 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6897 /* xchg.w r0,$Dst32AnUnprefixedHI */
6899 M32C_INSN_XCHG32W_R0_DST32_AN_DIRECT_UNPREFIXED_HI, "xchg32w-r0-dst32-An-direct-Unprefixed-HI", "xchg.w", 16,
6900 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6902 /* xchg.w r0,[$Dst32AnUnprefixed] */
6904 M32C_INSN_XCHG32W_R0_DST32_AN_INDIRECT_UNPREFIXED_HI, "xchg32w-r0-dst32-An-indirect-Unprefixed-HI", "xchg.w", 16,
6905 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6907 /* xchg.w r0,${Dsp-16-u8}[$Dst32AnUnprefixed] */
6909 M32C_INSN_XCHG32W_R0_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-8-An-relative-Unprefixed-HI", "xchg.w", 24,
6910 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6912 /* xchg.w r0,${Dsp-16-u16}[$Dst32AnUnprefixed] */
6914 M32C_INSN_XCHG32W_R0_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-16-An-relative-Unprefixed-HI", "xchg.w", 32,
6915 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6917 /* xchg.w r0,${Dsp-16-u24}[$Dst32AnUnprefixed] */
6919 M32C_INSN_XCHG32W_R0_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-24-An-relative-Unprefixed-HI", "xchg.w", 40,
6920 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6922 /* xchg.w r0,${Dsp-16-u8}[sb] */
6924 M32C_INSN_XCHG32W_R0_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-8-SB-relative-Unprefixed-HI", "xchg.w", 24,
6925 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6927 /* xchg.w r0,${Dsp-16-u16}[sb] */
6929 M32C_INSN_XCHG32W_R0_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-16-SB-relative-Unprefixed-HI", "xchg.w", 32,
6930 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6932 /* xchg.w r0,${Dsp-16-s8}[fb] */
6934 M32C_INSN_XCHG32W_R0_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-8-FB-relative-Unprefixed-HI", "xchg.w", 24,
6935 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6937 /* xchg.w r0,${Dsp-16-s16}[fb] */
6939 M32C_INSN_XCHG32W_R0_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-16-FB-relative-Unprefixed-HI", "xchg.w", 32,
6940 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6942 /* xchg.w r0,${Dsp-16-u16} */
6944 M32C_INSN_XCHG32W_R0_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-16-absolute-Unprefixed-HI", "xchg.w", 32,
6945 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6947 /* xchg.w r0,${Dsp-16-u24} */
6949 M32C_INSN_XCHG32W_R0_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "xchg32w-r0-dst32-16-24-absolute-Unprefixed-HI", "xchg.w", 40,
6950 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6952 /* xchg.b r1h,$Dst32RnUnprefixedQI */
6954 M32C_INSN_XCHG32B_R1H_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-r1h-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16,
6955 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6957 /* xchg.b r1h,$Dst32AnUnprefixedQI */
6959 M32C_INSN_XCHG32B_R1H_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-r1h-dst32-An-direct-Unprefixed-QI", "xchg.b", 16,
6960 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6962 /* xchg.b r1h,[$Dst32AnUnprefixed] */
6964 M32C_INSN_XCHG32B_R1H_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-r1h-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16,
6965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6967 /* xchg.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
6969 M32C_INSN_XCHG32B_R1H_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24,
6970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6972 /* xchg.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
6974 M32C_INSN_XCHG32B_R1H_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32,
6975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6977 /* xchg.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
6979 M32C_INSN_XCHG32B_R1H_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40,
6980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6982 /* xchg.b r1h,${Dsp-16-u8}[sb] */
6984 M32C_INSN_XCHG32B_R1H_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24,
6985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6987 /* xchg.b r1h,${Dsp-16-u16}[sb] */
6989 M32C_INSN_XCHG32B_R1H_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32,
6990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6992 /* xchg.b r1h,${Dsp-16-s8}[fb] */
6994 M32C_INSN_XCHG32B_R1H_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24,
6995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
6997 /* xchg.b r1h,${Dsp-16-s16}[fb] */
6999 M32C_INSN_XCHG32B_R1H_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32,
7000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7002 /* xchg.b r1h,${Dsp-16-u16} */
7004 M32C_INSN_XCHG32B_R1H_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32,
7005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7007 /* xchg.b r1h,${Dsp-16-u24} */
7009 M32C_INSN_XCHG32B_R1H_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r1h-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40,
7010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7012 /* xchg.b r0h,$Dst32RnUnprefixedQI */
7014 M32C_INSN_XCHG32B_R0H_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-r0h-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16,
7015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7017 /* xchg.b r0h,$Dst32AnUnprefixedQI */
7019 M32C_INSN_XCHG32B_R0H_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-r0h-dst32-An-direct-Unprefixed-QI", "xchg.b", 16,
7020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7022 /* xchg.b r0h,[$Dst32AnUnprefixed] */
7024 M32C_INSN_XCHG32B_R0H_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-r0h-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16,
7025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7027 /* xchg.b r0h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
7029 M32C_INSN_XCHG32B_R0H_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24,
7030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7032 /* xchg.b r0h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
7034 M32C_INSN_XCHG32B_R0H_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32,
7035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7037 /* xchg.b r0h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
7039 M32C_INSN_XCHG32B_R0H_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40,
7040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7042 /* xchg.b r0h,${Dsp-16-u8}[sb] */
7044 M32C_INSN_XCHG32B_R0H_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24,
7045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7047 /* xchg.b r0h,${Dsp-16-u16}[sb] */
7049 M32C_INSN_XCHG32B_R0H_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32,
7050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7052 /* xchg.b r0h,${Dsp-16-s8}[fb] */
7054 M32C_INSN_XCHG32B_R0H_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24,
7055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7057 /* xchg.b r0h,${Dsp-16-s16}[fb] */
7059 M32C_INSN_XCHG32B_R0H_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32,
7060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7062 /* xchg.b r0h,${Dsp-16-u16} */
7064 M32C_INSN_XCHG32B_R0H_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32,
7065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7067 /* xchg.b r0h,${Dsp-16-u24} */
7069 M32C_INSN_XCHG32B_R0H_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r0h-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40,
7070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7072 /* xchg.b a1,$Dst32RnUnprefixedQI */
7074 M32C_INSN_XCHG32B_A1_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-a1-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16,
7075 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7077 /* xchg.b a1,$Dst32AnUnprefixedQI */
7079 M32C_INSN_XCHG32B_A1_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-a1-dst32-An-direct-Unprefixed-QI", "xchg.b", 16,
7080 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7082 /* xchg.b a1,[$Dst32AnUnprefixed] */
7084 M32C_INSN_XCHG32B_A1_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-a1-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16,
7085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7087 /* xchg.b a1,${Dsp-16-u8}[$Dst32AnUnprefixed] */
7089 M32C_INSN_XCHG32B_A1_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24,
7090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7092 /* xchg.b a1,${Dsp-16-u16}[$Dst32AnUnprefixed] */
7094 M32C_INSN_XCHG32B_A1_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32,
7095 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7097 /* xchg.b a1,${Dsp-16-u24}[$Dst32AnUnprefixed] */
7099 M32C_INSN_XCHG32B_A1_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40,
7100 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7102 /* xchg.b a1,${Dsp-16-u8}[sb] */
7104 M32C_INSN_XCHG32B_A1_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24,
7105 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7107 /* xchg.b a1,${Dsp-16-u16}[sb] */
7109 M32C_INSN_XCHG32B_A1_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32,
7110 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7112 /* xchg.b a1,${Dsp-16-s8}[fb] */
7114 M32C_INSN_XCHG32B_A1_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24,
7115 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7117 /* xchg.b a1,${Dsp-16-s16}[fb] */
7119 M32C_INSN_XCHG32B_A1_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32,
7120 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7122 /* xchg.b a1,${Dsp-16-u16} */
7124 M32C_INSN_XCHG32B_A1_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32,
7125 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7127 /* xchg.b a1,${Dsp-16-u24} */
7129 M32C_INSN_XCHG32B_A1_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-a1-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40,
7130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7132 /* xchg.b a0,$Dst32RnUnprefixedQI */
7134 M32C_INSN_XCHG32B_A0_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-a0-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16,
7135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7137 /* xchg.b a0,$Dst32AnUnprefixedQI */
7139 M32C_INSN_XCHG32B_A0_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-a0-dst32-An-direct-Unprefixed-QI", "xchg.b", 16,
7140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7142 /* xchg.b a0,[$Dst32AnUnprefixed] */
7144 M32C_INSN_XCHG32B_A0_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-a0-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16,
7145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7147 /* xchg.b a0,${Dsp-16-u8}[$Dst32AnUnprefixed] */
7149 M32C_INSN_XCHG32B_A0_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24,
7150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7152 /* xchg.b a0,${Dsp-16-u16}[$Dst32AnUnprefixed] */
7154 M32C_INSN_XCHG32B_A0_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32,
7155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7157 /* xchg.b a0,${Dsp-16-u24}[$Dst32AnUnprefixed] */
7159 M32C_INSN_XCHG32B_A0_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40,
7160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7162 /* xchg.b a0,${Dsp-16-u8}[sb] */
7164 M32C_INSN_XCHG32B_A0_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24,
7165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7167 /* xchg.b a0,${Dsp-16-u16}[sb] */
7169 M32C_INSN_XCHG32B_A0_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32,
7170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7172 /* xchg.b a0,${Dsp-16-s8}[fb] */
7174 M32C_INSN_XCHG32B_A0_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24,
7175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7177 /* xchg.b a0,${Dsp-16-s16}[fb] */
7179 M32C_INSN_XCHG32B_A0_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32,
7180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7182 /* xchg.b a0,${Dsp-16-u16} */
7184 M32C_INSN_XCHG32B_A0_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32,
7185 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7187 /* xchg.b a0,${Dsp-16-u24} */
7189 M32C_INSN_XCHG32B_A0_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-a0-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40,
7190 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7192 /* xchg.b r1l,$Dst32RnUnprefixedQI */
7194 M32C_INSN_XCHG32B_R1L_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-r1l-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16,
7195 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7197 /* xchg.b r1l,$Dst32AnUnprefixedQI */
7199 M32C_INSN_XCHG32B_R1L_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-r1l-dst32-An-direct-Unprefixed-QI", "xchg.b", 16,
7200 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7202 /* xchg.b r1l,[$Dst32AnUnprefixed] */
7204 M32C_INSN_XCHG32B_R1L_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-r1l-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16,
7205 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7207 /* xchg.b r1l,${Dsp-16-u8}[$Dst32AnUnprefixed] */
7209 M32C_INSN_XCHG32B_R1L_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24,
7210 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7212 /* xchg.b r1l,${Dsp-16-u16}[$Dst32AnUnprefixed] */
7214 M32C_INSN_XCHG32B_R1L_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32,
7215 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7217 /* xchg.b r1l,${Dsp-16-u24}[$Dst32AnUnprefixed] */
7219 M32C_INSN_XCHG32B_R1L_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40,
7220 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7222 /* xchg.b r1l,${Dsp-16-u8}[sb] */
7224 M32C_INSN_XCHG32B_R1L_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24,
7225 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7227 /* xchg.b r1l,${Dsp-16-u16}[sb] */
7229 M32C_INSN_XCHG32B_R1L_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32,
7230 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7232 /* xchg.b r1l,${Dsp-16-s8}[fb] */
7234 M32C_INSN_XCHG32B_R1L_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24,
7235 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7237 /* xchg.b r1l,${Dsp-16-s16}[fb] */
7239 M32C_INSN_XCHG32B_R1L_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32,
7240 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7242 /* xchg.b r1l,${Dsp-16-u16} */
7244 M32C_INSN_XCHG32B_R1L_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32,
7245 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7247 /* xchg.b r1l,${Dsp-16-u24} */
7249 M32C_INSN_XCHG32B_R1L_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r1l-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40,
7250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7252 /* xchg.b r0l,$Dst32RnUnprefixedQI */
7254 M32C_INSN_XCHG32B_R0L_DST32_RN_DIRECT_UNPREFIXED_QI, "xchg32b-r0l-dst32-Rn-direct-Unprefixed-QI", "xchg.b", 16,
7255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7257 /* xchg.b r0l,$Dst32AnUnprefixedQI */
7259 M32C_INSN_XCHG32B_R0L_DST32_AN_DIRECT_UNPREFIXED_QI, "xchg32b-r0l-dst32-An-direct-Unprefixed-QI", "xchg.b", 16,
7260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7262 /* xchg.b r0l,[$Dst32AnUnprefixed] */
7264 M32C_INSN_XCHG32B_R0L_DST32_AN_INDIRECT_UNPREFIXED_QI, "xchg32b-r0l-dst32-An-indirect-Unprefixed-QI", "xchg.b", 16,
7265 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7267 /* xchg.b r0l,${Dsp-16-u8}[$Dst32AnUnprefixed] */
7269 M32C_INSN_XCHG32B_R0L_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-8-An-relative-Unprefixed-QI", "xchg.b", 24,
7270 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7272 /* xchg.b r0l,${Dsp-16-u16}[$Dst32AnUnprefixed] */
7274 M32C_INSN_XCHG32B_R0L_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-16-An-relative-Unprefixed-QI", "xchg.b", 32,
7275 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7277 /* xchg.b r0l,${Dsp-16-u24}[$Dst32AnUnprefixed] */
7279 M32C_INSN_XCHG32B_R0L_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-24-An-relative-Unprefixed-QI", "xchg.b", 40,
7280 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7282 /* xchg.b r0l,${Dsp-16-u8}[sb] */
7284 M32C_INSN_XCHG32B_R0L_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-8-SB-relative-Unprefixed-QI", "xchg.b", 24,
7285 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7287 /* xchg.b r0l,${Dsp-16-u16}[sb] */
7289 M32C_INSN_XCHG32B_R0L_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-16-SB-relative-Unprefixed-QI", "xchg.b", 32,
7290 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7292 /* xchg.b r0l,${Dsp-16-s8}[fb] */
7294 M32C_INSN_XCHG32B_R0L_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-8-FB-relative-Unprefixed-QI", "xchg.b", 24,
7295 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7297 /* xchg.b r0l,${Dsp-16-s16}[fb] */
7299 M32C_INSN_XCHG32B_R0L_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-16-FB-relative-Unprefixed-QI", "xchg.b", 32,
7300 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7302 /* xchg.b r0l,${Dsp-16-u16} */
7304 M32C_INSN_XCHG32B_R0L_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-16-absolute-Unprefixed-QI", "xchg.b", 32,
7305 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7307 /* xchg.b r0l,${Dsp-16-u24} */
7309 M32C_INSN_XCHG32B_R0L_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "xchg32b-r0l-dst32-16-24-absolute-Unprefixed-QI", "xchg.b", 40,
7310 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7312 /* xchg.w r3,$Dst16RnHI */
7314 M32C_INSN_XCHG16W_R3_DST16_RN_DIRECT_HI, "xchg16w-r3-dst16-Rn-direct-HI", "xchg.w", 16,
7315 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7317 /* xchg.w r3,$Dst16AnHI */
7319 M32C_INSN_XCHG16W_R3_DST16_AN_DIRECT_HI, "xchg16w-r3-dst16-An-direct-HI", "xchg.w", 16,
7320 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7322 /* xchg.w r3,[$Dst16An] */
7324 M32C_INSN_XCHG16W_R3_DST16_AN_INDIRECT_HI, "xchg16w-r3-dst16-An-indirect-HI", "xchg.w", 16,
7325 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7327 /* xchg.w r3,${Dsp-16-u8}[$Dst16An] */
7329 M32C_INSN_XCHG16W_R3_DST16_16_8_AN_RELATIVE_HI, "xchg16w-r3-dst16-16-8-An-relative-HI", "xchg.w", 24,
7330 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7332 /* xchg.w r3,${Dsp-16-u16}[$Dst16An] */
7334 M32C_INSN_XCHG16W_R3_DST16_16_16_AN_RELATIVE_HI, "xchg16w-r3-dst16-16-16-An-relative-HI", "xchg.w", 32,
7335 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7337 /* xchg.w r3,${Dsp-16-u8}[sb] */
7339 M32C_INSN_XCHG16W_R3_DST16_16_8_SB_RELATIVE_HI, "xchg16w-r3-dst16-16-8-SB-relative-HI", "xchg.w", 24,
7340 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7342 /* xchg.w r3,${Dsp-16-u16}[sb] */
7344 M32C_INSN_XCHG16W_R3_DST16_16_16_SB_RELATIVE_HI, "xchg16w-r3-dst16-16-16-SB-relative-HI", "xchg.w", 32,
7345 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7347 /* xchg.w r3,${Dsp-16-s8}[fb] */
7349 M32C_INSN_XCHG16W_R3_DST16_16_8_FB_RELATIVE_HI, "xchg16w-r3-dst16-16-8-FB-relative-HI", "xchg.w", 24,
7350 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7352 /* xchg.w r3,${Dsp-16-u16} */
7354 M32C_INSN_XCHG16W_R3_DST16_16_16_ABSOLUTE_HI, "xchg16w-r3-dst16-16-16-absolute-HI", "xchg.w", 32,
7355 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7357 /* xchg.w r2,$Dst16RnHI */
7359 M32C_INSN_XCHG16W_R2_DST16_RN_DIRECT_HI, "xchg16w-r2-dst16-Rn-direct-HI", "xchg.w", 16,
7360 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7362 /* xchg.w r2,$Dst16AnHI */
7364 M32C_INSN_XCHG16W_R2_DST16_AN_DIRECT_HI, "xchg16w-r2-dst16-An-direct-HI", "xchg.w", 16,
7365 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7367 /* xchg.w r2,[$Dst16An] */
7369 M32C_INSN_XCHG16W_R2_DST16_AN_INDIRECT_HI, "xchg16w-r2-dst16-An-indirect-HI", "xchg.w", 16,
7370 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7372 /* xchg.w r2,${Dsp-16-u8}[$Dst16An] */
7374 M32C_INSN_XCHG16W_R2_DST16_16_8_AN_RELATIVE_HI, "xchg16w-r2-dst16-16-8-An-relative-HI", "xchg.w", 24,
7375 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7377 /* xchg.w r2,${Dsp-16-u16}[$Dst16An] */
7379 M32C_INSN_XCHG16W_R2_DST16_16_16_AN_RELATIVE_HI, "xchg16w-r2-dst16-16-16-An-relative-HI", "xchg.w", 32,
7380 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7382 /* xchg.w r2,${Dsp-16-u8}[sb] */
7384 M32C_INSN_XCHG16W_R2_DST16_16_8_SB_RELATIVE_HI, "xchg16w-r2-dst16-16-8-SB-relative-HI", "xchg.w", 24,
7385 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7387 /* xchg.w r2,${Dsp-16-u16}[sb] */
7389 M32C_INSN_XCHG16W_R2_DST16_16_16_SB_RELATIVE_HI, "xchg16w-r2-dst16-16-16-SB-relative-HI", "xchg.w", 32,
7390 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7392 /* xchg.w r2,${Dsp-16-s8}[fb] */
7394 M32C_INSN_XCHG16W_R2_DST16_16_8_FB_RELATIVE_HI, "xchg16w-r2-dst16-16-8-FB-relative-HI", "xchg.w", 24,
7395 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7397 /* xchg.w r2,${Dsp-16-u16} */
7399 M32C_INSN_XCHG16W_R2_DST16_16_16_ABSOLUTE_HI, "xchg16w-r2-dst16-16-16-absolute-HI", "xchg.w", 32,
7400 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7402 /* xchg.w r1,$Dst16RnHI */
7404 M32C_INSN_XCHG16W_R1_DST16_RN_DIRECT_HI, "xchg16w-r1-dst16-Rn-direct-HI", "xchg.w", 16,
7405 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7407 /* xchg.w r1,$Dst16AnHI */
7409 M32C_INSN_XCHG16W_R1_DST16_AN_DIRECT_HI, "xchg16w-r1-dst16-An-direct-HI", "xchg.w", 16,
7410 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7412 /* xchg.w r1,[$Dst16An] */
7414 M32C_INSN_XCHG16W_R1_DST16_AN_INDIRECT_HI, "xchg16w-r1-dst16-An-indirect-HI", "xchg.w", 16,
7415 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7417 /* xchg.w r1,${Dsp-16-u8}[$Dst16An] */
7419 M32C_INSN_XCHG16W_R1_DST16_16_8_AN_RELATIVE_HI, "xchg16w-r1-dst16-16-8-An-relative-HI", "xchg.w", 24,
7420 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7422 /* xchg.w r1,${Dsp-16-u16}[$Dst16An] */
7424 M32C_INSN_XCHG16W_R1_DST16_16_16_AN_RELATIVE_HI, "xchg16w-r1-dst16-16-16-An-relative-HI", "xchg.w", 32,
7425 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7427 /* xchg.w r1,${Dsp-16-u8}[sb] */
7429 M32C_INSN_XCHG16W_R1_DST16_16_8_SB_RELATIVE_HI, "xchg16w-r1-dst16-16-8-SB-relative-HI", "xchg.w", 24,
7430 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7432 /* xchg.w r1,${Dsp-16-u16}[sb] */
7434 M32C_INSN_XCHG16W_R1_DST16_16_16_SB_RELATIVE_HI, "xchg16w-r1-dst16-16-16-SB-relative-HI", "xchg.w", 32,
7435 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7437 /* xchg.w r1,${Dsp-16-s8}[fb] */
7439 M32C_INSN_XCHG16W_R1_DST16_16_8_FB_RELATIVE_HI, "xchg16w-r1-dst16-16-8-FB-relative-HI", "xchg.w", 24,
7440 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7442 /* xchg.w r1,${Dsp-16-u16} */
7444 M32C_INSN_XCHG16W_R1_DST16_16_16_ABSOLUTE_HI, "xchg16w-r1-dst16-16-16-absolute-HI", "xchg.w", 32,
7445 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7447 /* xchg.w r0,$Dst16RnQI */
7449 M32C_INSN_XCHG16W_R0_DST16_RN_DIRECT_QI, "xchg16w-r0-dst16-Rn-direct-QI", "xchg.w", 16,
7450 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7452 /* xchg.w r0,$Dst16AnQI */
7454 M32C_INSN_XCHG16W_R0_DST16_AN_DIRECT_QI, "xchg16w-r0-dst16-An-direct-QI", "xchg.w", 16,
7455 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7457 /* xchg.w r0,[$Dst16An] */
7459 M32C_INSN_XCHG16W_R0_DST16_AN_INDIRECT_QI, "xchg16w-r0-dst16-An-indirect-QI", "xchg.w", 16,
7460 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7462 /* xchg.w r0,${Dsp-16-u8}[$Dst16An] */
7464 M32C_INSN_XCHG16W_R0_DST16_16_8_AN_RELATIVE_QI, "xchg16w-r0-dst16-16-8-An-relative-QI", "xchg.w", 24,
7465 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7467 /* xchg.w r0,${Dsp-16-u16}[$Dst16An] */
7469 M32C_INSN_XCHG16W_R0_DST16_16_16_AN_RELATIVE_QI, "xchg16w-r0-dst16-16-16-An-relative-QI", "xchg.w", 32,
7470 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7472 /* xchg.w r0,${Dsp-16-u8}[sb] */
7474 M32C_INSN_XCHG16W_R0_DST16_16_8_SB_RELATIVE_QI, "xchg16w-r0-dst16-16-8-SB-relative-QI", "xchg.w", 24,
7475 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7477 /* xchg.w r0,${Dsp-16-u16}[sb] */
7479 M32C_INSN_XCHG16W_R0_DST16_16_16_SB_RELATIVE_QI, "xchg16w-r0-dst16-16-16-SB-relative-QI", "xchg.w", 32,
7480 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7482 /* xchg.w r0,${Dsp-16-s8}[fb] */
7484 M32C_INSN_XCHG16W_R0_DST16_16_8_FB_RELATIVE_QI, "xchg16w-r0-dst16-16-8-FB-relative-QI", "xchg.w", 24,
7485 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7487 /* xchg.w r0,${Dsp-16-u16} */
7489 M32C_INSN_XCHG16W_R0_DST16_16_16_ABSOLUTE_QI, "xchg16w-r0-dst16-16-16-absolute-QI", "xchg.w", 32,
7490 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7492 /* xchg.b r1h,$Dst16RnQI */
7494 M32C_INSN_XCHG16B_R1H_DST16_RN_DIRECT_QI, "xchg16b-r1h-dst16-Rn-direct-QI", "xchg.b", 16,
7495 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7497 /* xchg.b r1h,$Dst16AnQI */
7499 M32C_INSN_XCHG16B_R1H_DST16_AN_DIRECT_QI, "xchg16b-r1h-dst16-An-direct-QI", "xchg.b", 16,
7500 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7502 /* xchg.b r1h,[$Dst16An] */
7504 M32C_INSN_XCHG16B_R1H_DST16_AN_INDIRECT_QI, "xchg16b-r1h-dst16-An-indirect-QI", "xchg.b", 16,
7505 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7507 /* xchg.b r1h,${Dsp-16-u8}[$Dst16An] */
7509 M32C_INSN_XCHG16B_R1H_DST16_16_8_AN_RELATIVE_QI, "xchg16b-r1h-dst16-16-8-An-relative-QI", "xchg.b", 24,
7510 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7512 /* xchg.b r1h,${Dsp-16-u16}[$Dst16An] */
7514 M32C_INSN_XCHG16B_R1H_DST16_16_16_AN_RELATIVE_QI, "xchg16b-r1h-dst16-16-16-An-relative-QI", "xchg.b", 32,
7515 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7517 /* xchg.b r1h,${Dsp-16-u8}[sb] */
7519 M32C_INSN_XCHG16B_R1H_DST16_16_8_SB_RELATIVE_QI, "xchg16b-r1h-dst16-16-8-SB-relative-QI", "xchg.b", 24,
7520 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7522 /* xchg.b r1h,${Dsp-16-u16}[sb] */
7524 M32C_INSN_XCHG16B_R1H_DST16_16_16_SB_RELATIVE_QI, "xchg16b-r1h-dst16-16-16-SB-relative-QI", "xchg.b", 32,
7525 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7527 /* xchg.b r1h,${Dsp-16-s8}[fb] */
7529 M32C_INSN_XCHG16B_R1H_DST16_16_8_FB_RELATIVE_QI, "xchg16b-r1h-dst16-16-8-FB-relative-QI", "xchg.b", 24,
7530 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7532 /* xchg.b r1h,${Dsp-16-u16} */
7534 M32C_INSN_XCHG16B_R1H_DST16_16_16_ABSOLUTE_QI, "xchg16b-r1h-dst16-16-16-absolute-QI", "xchg.b", 32,
7535 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7537 /* xchg.b r1l,$Dst16RnQI */
7539 M32C_INSN_XCHG16B_R1L_DST16_RN_DIRECT_QI, "xchg16b-r1l-dst16-Rn-direct-QI", "xchg.b", 16,
7540 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7542 /* xchg.b r1l,$Dst16AnQI */
7544 M32C_INSN_XCHG16B_R1L_DST16_AN_DIRECT_QI, "xchg16b-r1l-dst16-An-direct-QI", "xchg.b", 16,
7545 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7547 /* xchg.b r1l,[$Dst16An] */
7549 M32C_INSN_XCHG16B_R1L_DST16_AN_INDIRECT_QI, "xchg16b-r1l-dst16-An-indirect-QI", "xchg.b", 16,
7550 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7552 /* xchg.b r1l,${Dsp-16-u8}[$Dst16An] */
7554 M32C_INSN_XCHG16B_R1L_DST16_16_8_AN_RELATIVE_QI, "xchg16b-r1l-dst16-16-8-An-relative-QI", "xchg.b", 24,
7555 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7557 /* xchg.b r1l,${Dsp-16-u16}[$Dst16An] */
7559 M32C_INSN_XCHG16B_R1L_DST16_16_16_AN_RELATIVE_QI, "xchg16b-r1l-dst16-16-16-An-relative-QI", "xchg.b", 32,
7560 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7562 /* xchg.b r1l,${Dsp-16-u8}[sb] */
7564 M32C_INSN_XCHG16B_R1L_DST16_16_8_SB_RELATIVE_QI, "xchg16b-r1l-dst16-16-8-SB-relative-QI", "xchg.b", 24,
7565 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7567 /* xchg.b r1l,${Dsp-16-u16}[sb] */
7569 M32C_INSN_XCHG16B_R1L_DST16_16_16_SB_RELATIVE_QI, "xchg16b-r1l-dst16-16-16-SB-relative-QI", "xchg.b", 32,
7570 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7572 /* xchg.b r1l,${Dsp-16-s8}[fb] */
7574 M32C_INSN_XCHG16B_R1L_DST16_16_8_FB_RELATIVE_QI, "xchg16b-r1l-dst16-16-8-FB-relative-QI", "xchg.b", 24,
7575 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7577 /* xchg.b r1l,${Dsp-16-u16} */
7579 M32C_INSN_XCHG16B_R1L_DST16_16_16_ABSOLUTE_QI, "xchg16b-r1l-dst16-16-16-absolute-QI", "xchg.b", 32,
7580 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7582 /* xchg.b r0h,$Dst16RnQI */
7584 M32C_INSN_XCHG16B_R0H_DST16_RN_DIRECT_QI, "xchg16b-r0h-dst16-Rn-direct-QI", "xchg.b", 16,
7585 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7587 /* xchg.b r0h,$Dst16AnQI */
7589 M32C_INSN_XCHG16B_R0H_DST16_AN_DIRECT_QI, "xchg16b-r0h-dst16-An-direct-QI", "xchg.b", 16,
7590 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7592 /* xchg.b r0h,[$Dst16An] */
7594 M32C_INSN_XCHG16B_R0H_DST16_AN_INDIRECT_QI, "xchg16b-r0h-dst16-An-indirect-QI", "xchg.b", 16,
7595 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7597 /* xchg.b r0h,${Dsp-16-u8}[$Dst16An] */
7599 M32C_INSN_XCHG16B_R0H_DST16_16_8_AN_RELATIVE_QI, "xchg16b-r0h-dst16-16-8-An-relative-QI", "xchg.b", 24,
7600 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7602 /* xchg.b r0h,${Dsp-16-u16}[$Dst16An] */
7604 M32C_INSN_XCHG16B_R0H_DST16_16_16_AN_RELATIVE_QI, "xchg16b-r0h-dst16-16-16-An-relative-QI", "xchg.b", 32,
7605 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7607 /* xchg.b r0h,${Dsp-16-u8}[sb] */
7609 M32C_INSN_XCHG16B_R0H_DST16_16_8_SB_RELATIVE_QI, "xchg16b-r0h-dst16-16-8-SB-relative-QI", "xchg.b", 24,
7610 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7612 /* xchg.b r0h,${Dsp-16-u16}[sb] */
7614 M32C_INSN_XCHG16B_R0H_DST16_16_16_SB_RELATIVE_QI, "xchg16b-r0h-dst16-16-16-SB-relative-QI", "xchg.b", 32,
7615 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7617 /* xchg.b r0h,${Dsp-16-s8}[fb] */
7619 M32C_INSN_XCHG16B_R0H_DST16_16_8_FB_RELATIVE_QI, "xchg16b-r0h-dst16-16-8-FB-relative-QI", "xchg.b", 24,
7620 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7622 /* xchg.b r0h,${Dsp-16-u16} */
7624 M32C_INSN_XCHG16B_R0H_DST16_16_16_ABSOLUTE_QI, "xchg16b-r0h-dst16-16-16-absolute-QI", "xchg.b", 32,
7625 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7627 /* xchg.b r0l,$Dst16RnQI */
7629 M32C_INSN_XCHG16B_R0L_DST16_RN_DIRECT_QI, "xchg16b-r0l-dst16-Rn-direct-QI", "xchg.b", 16,
7630 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7632 /* xchg.b r0l,$Dst16AnQI */
7634 M32C_INSN_XCHG16B_R0L_DST16_AN_DIRECT_QI, "xchg16b-r0l-dst16-An-direct-QI", "xchg.b", 16,
7635 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7637 /* xchg.b r0l,[$Dst16An] */
7639 M32C_INSN_XCHG16B_R0L_DST16_AN_INDIRECT_QI, "xchg16b-r0l-dst16-An-indirect-QI", "xchg.b", 16,
7640 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7642 /* xchg.b r0l,${Dsp-16-u8}[$Dst16An] */
7644 M32C_INSN_XCHG16B_R0L_DST16_16_8_AN_RELATIVE_QI, "xchg16b-r0l-dst16-16-8-An-relative-QI", "xchg.b", 24,
7645 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7647 /* xchg.b r0l,${Dsp-16-u16}[$Dst16An] */
7649 M32C_INSN_XCHG16B_R0L_DST16_16_16_AN_RELATIVE_QI, "xchg16b-r0l-dst16-16-16-An-relative-QI", "xchg.b", 32,
7650 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7652 /* xchg.b r0l,${Dsp-16-u8}[sb] */
7654 M32C_INSN_XCHG16B_R0L_DST16_16_8_SB_RELATIVE_QI, "xchg16b-r0l-dst16-16-8-SB-relative-QI", "xchg.b", 24,
7655 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7657 /* xchg.b r0l,${Dsp-16-u16}[sb] */
7659 M32C_INSN_XCHG16B_R0L_DST16_16_16_SB_RELATIVE_QI, "xchg16b-r0l-dst16-16-16-SB-relative-QI", "xchg.b", 32,
7660 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7662 /* xchg.b r0l,${Dsp-16-s8}[fb] */
7664 M32C_INSN_XCHG16B_R0L_DST16_16_8_FB_RELATIVE_QI, "xchg16b-r0l-dst16-16-8-FB-relative-QI", "xchg.b", 24,
7665 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7667 /* xchg.b r0l,${Dsp-16-u16} */
7669 M32C_INSN_XCHG16B_R0L_DST16_16_16_ABSOLUTE_QI, "xchg16b-r0l-dst16-16-16-absolute-QI", "xchg.b", 32,
7670 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
7672 /* tst.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
7674 M32C_INSN_TST32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "tst32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "tst.w", 32,
7675 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7677 /* tst.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
7679 M32C_INSN_TST32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "tst32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "tst.w", 32,
7680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7682 /* tst.w${S} #${Imm-24-HI},${Dsp-8-u16} */
7684 M32C_INSN_TST32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "tst32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "tst.w", 40,
7685 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7687 /* tst.w${S} #${Imm-8-HI},r0 */
7689 M32C_INSN_TST32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "tst32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "tst.w", 24,
7690 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7692 /* tst.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
7694 M32C_INSN_TST32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "tst32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "tst.b", 24,
7695 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7697 /* tst.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
7699 M32C_INSN_TST32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "tst32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "tst.b", 24,
7700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7702 /* tst.b${S} #${Imm-24-QI},${Dsp-8-u16} */
7704 M32C_INSN_TST32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "tst32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "tst.b", 32,
7705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7707 /* tst.b${S} #${Imm-8-QI},r0l */
7709 M32C_INSN_TST32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "tst32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "tst.b", 16,
7710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7712 /* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
7714 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 32,
7715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7717 /* tst.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
7719 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 32,
7720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7722 /* tst.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
7724 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 32,
7725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7727 /* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
7729 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 32,
7730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7732 /* tst.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
7734 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 32,
7735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7737 /* tst.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
7739 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 32,
7740 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7742 /* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
7744 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 32,
7745 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7747 /* tst.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
7749 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 32,
7750 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7752 /* tst.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
7754 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 32,
7755 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7757 /* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
7759 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "tst.w", 40,
7760 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7762 /* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
7764 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "tst.w", 40,
7765 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7767 /* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
7769 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "tst.w", 40,
7770 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7772 /* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
7774 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "tst.w", 48,
7775 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7777 /* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
7779 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "tst.w", 48,
7780 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7782 /* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
7784 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "tst.w", 48,
7785 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7787 /* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
7789 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "tst.w", 56,
7790 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7792 /* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
7794 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "tst.w", 56,
7795 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7797 /* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
7799 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "tst.w", 56,
7800 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7802 /* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
7804 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "tst.w", 40,
7805 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7807 /* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
7809 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "tst.w", 40,
7810 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7812 /* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
7814 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "tst.w", 40,
7815 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7817 /* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
7819 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "tst.w", 48,
7820 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7822 /* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
7824 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "tst.w", 48,
7825 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7827 /* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
7829 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "tst.w", 48,
7830 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7832 /* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
7834 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "tst.w", 40,
7835 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7837 /* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
7839 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "tst.w", 40,
7840 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7842 /* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
7844 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "tst.w", 40,
7845 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7847 /* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
7849 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "tst.w", 48,
7850 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7852 /* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
7854 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "tst.w", 48,
7855 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7857 /* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
7859 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "tst.w", 48,
7860 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7862 /* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
7864 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "tst.w", 48,
7865 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7867 /* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
7869 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "tst.w", 48,
7870 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7872 /* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
7874 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "tst.w", 48,
7875 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7877 /* tst.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
7879 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "tst.w", 56,
7880 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7882 /* tst.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
7884 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "tst.w", 56,
7885 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7887 /* tst.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
7889 M32C_INSN_TST32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "tst.w", 56,
7890 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7892 /* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
7894 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 40,
7895 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7897 /* tst.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
7899 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 40,
7900 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7902 /* tst.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
7904 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 40,
7905 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7907 /* tst.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
7909 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 40,
7910 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7912 /* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
7914 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 40,
7915 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7917 /* tst.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
7919 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 40,
7920 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7922 /* tst.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
7924 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 40,
7925 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7927 /* tst.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
7929 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 40,
7930 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7932 /* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
7934 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 40,
7935 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7937 /* tst.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
7939 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 40,
7940 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7942 /* tst.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
7944 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 40,
7945 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7947 /* tst.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
7949 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 40,
7950 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7952 /* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
7954 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "tst.w", 48,
7955 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7957 /* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
7959 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "tst.w", 48,
7960 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7962 /* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
7964 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "tst.w", 48,
7965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7967 /* tst.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
7969 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "tst.w", 48,
7970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7972 /* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
7974 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "tst.w", 56,
7975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7977 /* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
7979 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "tst.w", 56,
7980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7982 /* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
7984 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "tst.w", 56,
7985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7987 /* tst.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
7989 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "tst.w", 56,
7990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7992 /* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
7994 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "tst.w", 64,
7995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
7997 /* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
7999 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "tst.w", 64,
8000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8002 /* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
8004 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "tst.w", 64,
8005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8007 /* tst.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
8009 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "tst.w", 64,
8010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8012 /* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
8014 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "tst.w", 48,
8015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8017 /* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
8019 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "tst.w", 48,
8020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8022 /* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
8024 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "tst.w", 48,
8025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8027 /* tst.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
8029 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "tst.w", 48,
8030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8032 /* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
8034 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "tst.w", 56,
8035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8037 /* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
8039 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "tst.w", 56,
8040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8042 /* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
8044 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "tst.w", 56,
8045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8047 /* tst.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
8049 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "tst.w", 56,
8050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8052 /* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
8054 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "tst.w", 48,
8055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8057 /* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
8059 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "tst.w", 48,
8060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8062 /* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
8064 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "tst.w", 48,
8065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8067 /* tst.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
8069 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "tst.w", 48,
8070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8072 /* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
8074 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "tst.w", 56,
8075 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8077 /* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
8079 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "tst.w", 56,
8080 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8082 /* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
8084 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "tst.w", 56,
8085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8087 /* tst.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
8089 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "tst.w", 56,
8090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8092 /* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
8094 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "tst.w", 56,
8095 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8097 /* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
8099 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "tst.w", 56,
8100 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8102 /* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
8104 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "tst.w", 56,
8105 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8107 /* tst.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
8109 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "tst.w", 56,
8110 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8112 /* tst.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
8114 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "tst.w", 64,
8115 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8117 /* tst.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
8119 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "tst.w", 64,
8120 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8122 /* tst.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
8124 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "tst.w", 64,
8125 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8127 /* tst.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
8129 M32C_INSN_TST32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "tst.w", 64,
8130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8132 /* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
8134 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 48,
8135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8137 /* tst.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
8139 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 48,
8140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8142 /* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
8144 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 48,
8145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8147 /* tst.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
8149 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 48,
8150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8152 /* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
8154 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 48,
8155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8157 /* tst.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
8159 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 48,
8160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8162 /* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
8164 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "tst.w", 56,
8165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8167 /* tst.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
8169 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "tst.w", 56,
8170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8172 /* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
8174 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "tst.w", 64,
8175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8177 /* tst.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
8179 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "tst.w", 64,
8180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8182 /* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
8184 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "tst.w", 72,
8185 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8187 /* tst.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
8189 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "tst.w", 72,
8190 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8192 /* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
8194 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "tst.w", 56,
8195 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8197 /* tst.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
8199 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "tst.w", 56,
8200 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8202 /* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
8204 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "tst.w", 64,
8205 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8207 /* tst.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
8209 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "tst.w", 64,
8210 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8212 /* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
8214 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "tst.w", 56,
8215 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8217 /* tst.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
8219 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "tst.w", 56,
8220 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8222 /* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
8224 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "tst.w", 64,
8225 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8227 /* tst.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
8229 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "tst.w", 64,
8230 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8232 /* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
8234 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "tst.w", 64,
8235 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8237 /* tst.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
8239 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "tst.w", 64,
8240 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8242 /* tst.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
8244 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "tst.w", 72,
8245 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8247 /* tst.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
8249 M32C_INSN_TST32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "tst32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "tst.w", 72,
8250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8252 /* tst.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
8254 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 24,
8255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8257 /* tst.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
8259 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 24,
8260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8262 /* tst.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
8264 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "tst.w", 24,
8265 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8267 /* tst.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
8269 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 24,
8270 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8272 /* tst.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
8274 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 24,
8275 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8277 /* tst.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
8279 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "tst.w", 24,
8280 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8282 /* tst.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
8284 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 24,
8285 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8287 /* tst.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
8289 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 24,
8290 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8292 /* tst.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
8294 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "tst.w", 24,
8295 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8297 /* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
8299 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "tst.w", 32,
8300 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8302 /* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
8304 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "tst.w", 32,
8305 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8307 /* tst.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
8309 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "tst.w", 32,
8310 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8312 /* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
8314 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "tst.w", 40,
8315 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8317 /* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
8319 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "tst.w", 40,
8320 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8322 /* tst.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
8324 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "tst.w", 40,
8325 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8327 /* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
8329 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "tst.w", 48,
8330 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8332 /* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
8334 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "tst.w", 48,
8335 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8337 /* tst.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
8339 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "tst.w", 48,
8340 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8342 /* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
8344 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "tst.w", 32,
8345 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8347 /* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
8349 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "tst.w", 32,
8350 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8352 /* tst.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
8354 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "tst.w", 32,
8355 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8357 /* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
8359 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "tst.w", 40,
8360 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8362 /* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
8364 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "tst.w", 40,
8365 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8367 /* tst.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
8369 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "tst.w", 40,
8370 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8372 /* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
8374 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "tst.w", 32,
8375 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8377 /* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
8379 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "tst.w", 32,
8380 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8382 /* tst.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
8384 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "tst.w", 32,
8385 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8387 /* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
8389 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "tst.w", 40,
8390 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8392 /* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
8394 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "tst.w", 40,
8395 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8397 /* tst.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
8399 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "tst.w", 40,
8400 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8402 /* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
8404 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "tst.w", 40,
8405 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8407 /* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
8409 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "tst.w", 40,
8410 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8412 /* tst.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
8414 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "tst.w", 40,
8415 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8417 /* tst.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
8419 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "tst.w", 48,
8420 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8422 /* tst.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
8424 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "tst.w", 48,
8425 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8427 /* tst.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
8429 M32C_INSN_TST32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "tst32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "tst.w", 48,
8430 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8432 /* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
8434 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 32,
8435 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8437 /* tst.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
8439 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 32,
8440 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8442 /* tst.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
8444 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 32,
8445 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8447 /* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
8449 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 32,
8450 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8452 /* tst.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
8454 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 32,
8455 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8457 /* tst.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
8459 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 32,
8460 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8462 /* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
8464 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 32,
8465 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8467 /* tst.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
8469 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 32,
8470 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8472 /* tst.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
8474 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 32,
8475 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8477 /* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
8479 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "tst.b", 40,
8480 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8482 /* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
8484 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "tst.b", 40,
8485 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8487 /* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
8489 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "tst.b", 40,
8490 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8492 /* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
8494 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "tst.b", 48,
8495 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8497 /* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
8499 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "tst.b", 48,
8500 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8502 /* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
8504 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "tst.b", 48,
8505 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8507 /* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
8509 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "tst.b", 56,
8510 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8512 /* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
8514 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "tst.b", 56,
8515 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8517 /* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
8519 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "tst.b", 56,
8520 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8522 /* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
8524 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "tst.b", 40,
8525 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8527 /* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
8529 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "tst.b", 40,
8530 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8532 /* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
8534 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "tst.b", 40,
8535 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8537 /* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
8539 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "tst.b", 48,
8540 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8542 /* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
8544 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "tst.b", 48,
8545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8547 /* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
8549 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "tst.b", 48,
8550 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8552 /* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
8554 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "tst.b", 40,
8555 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8557 /* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
8559 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "tst.b", 40,
8560 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8562 /* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
8564 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "tst.b", 40,
8565 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8567 /* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
8569 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "tst.b", 48,
8570 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8572 /* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
8574 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "tst.b", 48,
8575 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8577 /* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
8579 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "tst.b", 48,
8580 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8582 /* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
8584 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "tst.b", 48,
8585 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8587 /* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
8589 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "tst.b", 48,
8590 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8592 /* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
8594 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "tst.b", 48,
8595 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8597 /* tst.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
8599 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "tst.b", 56,
8600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8602 /* tst.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
8604 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "tst.b", 56,
8605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8607 /* tst.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
8609 M32C_INSN_TST32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "tst.b", 56,
8610 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8612 /* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
8614 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 40,
8615 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8617 /* tst.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
8619 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 40,
8620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8622 /* tst.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
8624 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 40,
8625 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8627 /* tst.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
8629 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 40,
8630 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8632 /* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
8634 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 40,
8635 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8637 /* tst.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
8639 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 40,
8640 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8642 /* tst.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
8644 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 40,
8645 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8647 /* tst.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
8649 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 40,
8650 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8652 /* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
8654 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 40,
8655 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8657 /* tst.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
8659 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 40,
8660 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8662 /* tst.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
8664 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 40,
8665 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8667 /* tst.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
8669 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 40,
8670 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8672 /* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
8674 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "tst.b", 48,
8675 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8677 /* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
8679 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "tst.b", 48,
8680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8682 /* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
8684 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "tst.b", 48,
8685 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8687 /* tst.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
8689 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "tst.b", 48,
8690 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8692 /* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
8694 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "tst.b", 56,
8695 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8697 /* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
8699 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "tst.b", 56,
8700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8702 /* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
8704 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "tst.b", 56,
8705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8707 /* tst.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
8709 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "tst.b", 56,
8710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8712 /* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
8714 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "tst.b", 64,
8715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8717 /* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
8719 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "tst.b", 64,
8720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8722 /* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
8724 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "tst.b", 64,
8725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8727 /* tst.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
8729 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "tst.b", 64,
8730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8732 /* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
8734 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "tst.b", 48,
8735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8737 /* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
8739 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "tst.b", 48,
8740 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8742 /* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
8744 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "tst.b", 48,
8745 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8747 /* tst.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
8749 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "tst.b", 48,
8750 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8752 /* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
8754 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "tst.b", 56,
8755 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8757 /* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
8759 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "tst.b", 56,
8760 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8762 /* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
8764 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "tst.b", 56,
8765 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8767 /* tst.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
8769 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "tst.b", 56,
8770 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8772 /* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
8774 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "tst.b", 48,
8775 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8777 /* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
8779 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "tst.b", 48,
8780 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8782 /* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
8784 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "tst.b", 48,
8785 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8787 /* tst.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
8789 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "tst.b", 48,
8790 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8792 /* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
8794 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "tst.b", 56,
8795 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8797 /* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
8799 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "tst.b", 56,
8800 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8802 /* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
8804 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "tst.b", 56,
8805 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8807 /* tst.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
8809 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "tst.b", 56,
8810 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8812 /* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
8814 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "tst.b", 56,
8815 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8817 /* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
8819 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "tst.b", 56,
8820 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8822 /* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
8824 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "tst.b", 56,
8825 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8827 /* tst.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
8829 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "tst.b", 56,
8830 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8832 /* tst.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
8834 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "tst.b", 64,
8835 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8837 /* tst.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
8839 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "tst.b", 64,
8840 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8842 /* tst.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
8844 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "tst.b", 64,
8845 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8847 /* tst.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
8849 M32C_INSN_TST32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "tst.b", 64,
8850 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8852 /* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
8854 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 48,
8855 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8857 /* tst.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
8859 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 48,
8860 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8862 /* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
8864 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 48,
8865 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8867 /* tst.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
8869 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 48,
8870 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8872 /* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
8874 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 48,
8875 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8877 /* tst.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
8879 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 48,
8880 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8882 /* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
8884 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "tst.b", 56,
8885 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8887 /* tst.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
8889 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "tst.b", 56,
8890 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8892 /* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
8894 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "tst.b", 64,
8895 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8897 /* tst.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
8899 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "tst.b", 64,
8900 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8902 /* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
8904 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "tst.b", 72,
8905 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8907 /* tst.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
8909 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "tst.b", 72,
8910 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8912 /* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
8914 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "tst.b", 56,
8915 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8917 /* tst.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
8919 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "tst.b", 56,
8920 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8922 /* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
8924 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "tst.b", 64,
8925 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8927 /* tst.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
8929 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "tst.b", 64,
8930 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8932 /* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
8934 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "tst.b", 56,
8935 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8937 /* tst.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
8939 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "tst.b", 56,
8940 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8942 /* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
8944 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "tst.b", 64,
8945 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8947 /* tst.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
8949 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "tst.b", 64,
8950 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8952 /* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
8954 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "tst.b", 64,
8955 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8957 /* tst.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
8959 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "tst.b", 64,
8960 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8962 /* tst.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
8964 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "tst.b", 72,
8965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8967 /* tst.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
8969 M32C_INSN_TST32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "tst32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "tst.b", 72,
8970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8972 /* tst.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
8974 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 24,
8975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8977 /* tst.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
8979 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 24,
8980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8982 /* tst.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
8984 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "tst.b", 24,
8985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8987 /* tst.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
8989 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 24,
8990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8992 /* tst.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
8994 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 24,
8995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
8997 /* tst.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
8999 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "tst.b", 24,
9000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9002 /* tst.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
9004 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 24,
9005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9007 /* tst.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
9009 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 24,
9010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9012 /* tst.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
9014 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "tst.b", 24,
9015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9017 /* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
9019 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "tst.b", 32,
9020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9022 /* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
9024 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "tst.b", 32,
9025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9027 /* tst.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
9029 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "tst.b", 32,
9030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9032 /* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
9034 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "tst.b", 40,
9035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9037 /* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
9039 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "tst.b", 40,
9040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9042 /* tst.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
9044 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "tst.b", 40,
9045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9047 /* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
9049 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "tst.b", 48,
9050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9052 /* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
9054 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "tst.b", 48,
9055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9057 /* tst.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
9059 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "tst.b", 48,
9060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9062 /* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
9064 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "tst.b", 32,
9065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9067 /* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
9069 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "tst.b", 32,
9070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9072 /* tst.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
9074 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "tst.b", 32,
9075 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9077 /* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
9079 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "tst.b", 40,
9080 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9082 /* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
9084 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "tst.b", 40,
9085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9087 /* tst.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
9089 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "tst.b", 40,
9090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9092 /* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
9094 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "tst.b", 32,
9095 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9097 /* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
9099 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "tst.b", 32,
9100 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9102 /* tst.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
9104 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "tst.b", 32,
9105 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9107 /* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
9109 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "tst.b", 40,
9110 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9112 /* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
9114 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "tst.b", 40,
9115 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9117 /* tst.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
9119 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "tst.b", 40,
9120 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9122 /* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
9124 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "tst.b", 40,
9125 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9127 /* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
9129 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "tst.b", 40,
9130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9132 /* tst.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
9134 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "tst.b", 40,
9135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9137 /* tst.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
9139 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "tst.b", 48,
9140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9142 /* tst.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
9144 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "tst.b", 48,
9145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9147 /* tst.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
9149 M32C_INSN_TST32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "tst32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "tst.b", 48,
9150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9152 /* tst.w${X} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
9154 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "tst.w", 24,
9155 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9157 /* tst.w${X} ${Dsp-16-u8}[sb],$Dst16RnHI */
9159 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "tst.w", 24,
9160 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9162 /* tst.w${X} ${Dsp-16-s8}[fb],$Dst16RnHI */
9164 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "tst.w", 24,
9165 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9167 /* tst.w${X} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
9169 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "tst.w", 24,
9170 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9172 /* tst.w${X} ${Dsp-16-u8}[sb],$Dst16AnHI */
9174 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "tst.w", 24,
9175 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9177 /* tst.w${X} ${Dsp-16-s8}[fb],$Dst16AnHI */
9179 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "tst.w", 24,
9180 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9182 /* tst.w${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
9184 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "tst.w", 24,
9185 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9187 /* tst.w${X} ${Dsp-16-u8}[sb],[$Dst16An] */
9189 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "tst.w", 24,
9190 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9192 /* tst.w${X} ${Dsp-16-s8}[fb],[$Dst16An] */
9194 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "tst.w", 24,
9195 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9197 /* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
9199 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "tst.w", 32,
9200 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9202 /* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
9204 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "tst.w", 32,
9205 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9207 /* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
9209 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "tst.w", 32,
9210 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9212 /* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
9214 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "tst.w", 40,
9215 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9217 /* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
9219 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "tst.w", 40,
9220 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9222 /* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
9224 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "tst.w", 40,
9225 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9227 /* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
9229 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "tst.w", 32,
9230 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9232 /* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
9234 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "tst.w", 32,
9235 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9237 /* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
9239 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "tst.w", 32,
9240 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9242 /* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
9244 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "tst.w", 40,
9245 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9247 /* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
9249 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "tst.w", 40,
9250 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9252 /* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
9254 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "tst.w", 40,
9255 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9257 /* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
9259 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "tst.w", 32,
9260 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9262 /* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
9264 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "tst.w", 32,
9265 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9267 /* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
9269 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "tst.w", 32,
9270 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9272 /* tst.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
9274 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "tst16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "tst.w", 40,
9275 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9277 /* tst.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
9279 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "tst16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "tst.w", 40,
9280 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9282 /* tst.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
9284 M32C_INSN_TST16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "tst16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "tst.w", 40,
9285 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9287 /* tst.w${X} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
9289 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "tst.w", 32,
9290 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9292 /* tst.w${X} ${Dsp-16-u16}[sb],$Dst16RnHI */
9294 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "tst.w", 32,
9295 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9297 /* tst.w${X} ${Dsp-16-u16},$Dst16RnHI */
9299 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "tst.w", 32,
9300 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9302 /* tst.w${X} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
9304 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "tst.w", 32,
9305 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9307 /* tst.w${X} ${Dsp-16-u16}[sb],$Dst16AnHI */
9309 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "tst.w", 32,
9310 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9312 /* tst.w${X} ${Dsp-16-u16},$Dst16AnHI */
9314 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "tst.w", 32,
9315 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9317 /* tst.w${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
9319 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "tst.w", 32,
9320 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9322 /* tst.w${X} ${Dsp-16-u16}[sb],[$Dst16An] */
9324 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "tst.w", 32,
9325 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9327 /* tst.w${X} ${Dsp-16-u16},[$Dst16An] */
9329 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "tst.w", 32,
9330 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9332 /* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
9334 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "tst.w", 40,
9335 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9337 /* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
9339 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "tst.w", 40,
9340 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9342 /* tst.w${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
9344 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "tst.w", 40,
9345 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9347 /* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
9349 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "tst.w", 48,
9350 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9352 /* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
9354 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "tst.w", 48,
9355 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9357 /* tst.w${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
9359 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "tst.w", 48,
9360 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9362 /* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
9364 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "tst.w", 40,
9365 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9367 /* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
9369 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "tst.w", 40,
9370 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9372 /* tst.w${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
9374 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "tst.w", 40,
9375 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9377 /* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
9379 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "tst.w", 48,
9380 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9382 /* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
9384 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "tst.w", 48,
9385 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9387 /* tst.w${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
9389 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "tst.w", 48,
9390 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9392 /* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
9394 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "tst.w", 40,
9395 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9397 /* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
9399 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "tst.w", 40,
9400 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9402 /* tst.w${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
9404 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "tst.w", 40,
9405 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9407 /* tst.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
9409 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "tst16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "tst.w", 48,
9410 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9412 /* tst.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
9414 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "tst16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "tst.w", 48,
9415 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9417 /* tst.w${X} ${Dsp-16-u16},${Dsp-32-u16} */
9419 M32C_INSN_TST16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "tst16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "tst.w", 48,
9420 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9422 /* tst.w${X} $Src16RnHI,$Dst16RnHI */
9424 M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "tst.w", 16,
9425 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9427 /* tst.w${X} $Src16AnHI,$Dst16RnHI */
9429 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "tst.w", 16,
9430 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9432 /* tst.w${X} [$Src16An],$Dst16RnHI */
9434 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "tst.w", 16,
9435 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9437 /* tst.w${X} $Src16RnHI,$Dst16AnHI */
9439 M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "tst.w", 16,
9440 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9442 /* tst.w${X} $Src16AnHI,$Dst16AnHI */
9444 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "tst.w", 16,
9445 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9447 /* tst.w${X} [$Src16An],$Dst16AnHI */
9449 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "tst.w", 16,
9450 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9452 /* tst.w${X} $Src16RnHI,[$Dst16An] */
9454 M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "tst.w", 16,
9455 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9457 /* tst.w${X} $Src16AnHI,[$Dst16An] */
9459 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "tst.w", 16,
9460 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9462 /* tst.w${X} [$Src16An],[$Dst16An] */
9464 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "tst.w", 16,
9465 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9467 /* tst.w${X} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
9469 M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "tst.w", 24,
9470 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9472 /* tst.w${X} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
9474 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "tst.w", 24,
9475 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9477 /* tst.w${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
9479 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "tst.w", 24,
9480 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9482 /* tst.w${X} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
9484 M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "tst.w", 32,
9485 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9487 /* tst.w${X} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
9489 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "tst.w", 32,
9490 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9492 /* tst.w${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
9494 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "tst.w", 32,
9495 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9497 /* tst.w${X} $Src16RnHI,${Dsp-16-u8}[sb] */
9499 M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "tst.w", 24,
9500 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9502 /* tst.w${X} $Src16AnHI,${Dsp-16-u8}[sb] */
9504 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "tst.w", 24,
9505 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9507 /* tst.w${X} [$Src16An],${Dsp-16-u8}[sb] */
9509 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "tst.w", 24,
9510 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9512 /* tst.w${X} $Src16RnHI,${Dsp-16-u16}[sb] */
9514 M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "tst.w", 32,
9515 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9517 /* tst.w${X} $Src16AnHI,${Dsp-16-u16}[sb] */
9519 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "tst.w", 32,
9520 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9522 /* tst.w${X} [$Src16An],${Dsp-16-u16}[sb] */
9524 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "tst.w", 32,
9525 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9527 /* tst.w${X} $Src16RnHI,${Dsp-16-s8}[fb] */
9529 M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "tst.w", 24,
9530 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9532 /* tst.w${X} $Src16AnHI,${Dsp-16-s8}[fb] */
9534 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "tst.w", 24,
9535 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9537 /* tst.w${X} [$Src16An],${Dsp-16-s8}[fb] */
9539 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "tst.w", 24,
9540 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9542 /* tst.w${X} $Src16RnHI,${Dsp-16-u16} */
9544 M32C_INSN_TST16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "tst16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "tst.w", 32,
9545 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9547 /* tst.w${X} $Src16AnHI,${Dsp-16-u16} */
9549 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "tst16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "tst.w", 32,
9550 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9552 /* tst.w${X} [$Src16An],${Dsp-16-u16} */
9554 M32C_INSN_TST16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "tst16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "tst.w", 32,
9555 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9557 /* tst.b${X} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
9559 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "tst.b", 24,
9560 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9562 /* tst.b${X} ${Dsp-16-u8}[sb],$Dst16RnQI */
9564 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "tst.b", 24,
9565 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9567 /* tst.b${X} ${Dsp-16-s8}[fb],$Dst16RnQI */
9569 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "tst.b", 24,
9570 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9572 /* tst.b${X} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
9574 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "tst.b", 24,
9575 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9577 /* tst.b${X} ${Dsp-16-u8}[sb],$Dst16AnQI */
9579 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "tst.b", 24,
9580 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9582 /* tst.b${X} ${Dsp-16-s8}[fb],$Dst16AnQI */
9584 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "tst.b", 24,
9585 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9587 /* tst.b${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
9589 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "tst.b", 24,
9590 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9592 /* tst.b${X} ${Dsp-16-u8}[sb],[$Dst16An] */
9594 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "tst.b", 24,
9595 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9597 /* tst.b${X} ${Dsp-16-s8}[fb],[$Dst16An] */
9599 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "tst.b", 24,
9600 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9602 /* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
9604 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "tst.b", 32,
9605 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9607 /* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
9609 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "tst.b", 32,
9610 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9612 /* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
9614 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "tst.b", 32,
9615 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9617 /* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
9619 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "tst.b", 40,
9620 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9622 /* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
9624 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "tst.b", 40,
9625 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9627 /* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
9629 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "tst.b", 40,
9630 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9632 /* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
9634 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "tst.b", 32,
9635 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9637 /* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
9639 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "tst.b", 32,
9640 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9642 /* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
9644 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "tst.b", 32,
9645 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9647 /* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
9649 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "tst.b", 40,
9650 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9652 /* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
9654 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "tst.b", 40,
9655 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9657 /* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
9659 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "tst.b", 40,
9660 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9662 /* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
9664 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "tst.b", 32,
9665 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9667 /* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
9669 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "tst.b", 32,
9670 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9672 /* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
9674 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "tst.b", 32,
9675 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9677 /* tst.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
9679 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "tst16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "tst.b", 40,
9680 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9682 /* tst.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
9684 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "tst16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "tst.b", 40,
9685 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9687 /* tst.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
9689 M32C_INSN_TST16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "tst16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "tst.b", 40,
9690 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9692 /* tst.b${X} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
9694 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "tst.b", 32,
9695 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9697 /* tst.b${X} ${Dsp-16-u16}[sb],$Dst16RnQI */
9699 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "tst.b", 32,
9700 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9702 /* tst.b${X} ${Dsp-16-u16},$Dst16RnQI */
9704 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "tst.b", 32,
9705 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9707 /* tst.b${X} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
9709 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "tst.b", 32,
9710 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9712 /* tst.b${X} ${Dsp-16-u16}[sb],$Dst16AnQI */
9714 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "tst.b", 32,
9715 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9717 /* tst.b${X} ${Dsp-16-u16},$Dst16AnQI */
9719 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "tst.b", 32,
9720 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9722 /* tst.b${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
9724 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "tst.b", 32,
9725 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9727 /* tst.b${X} ${Dsp-16-u16}[sb],[$Dst16An] */
9729 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "tst.b", 32,
9730 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9732 /* tst.b${X} ${Dsp-16-u16},[$Dst16An] */
9734 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "tst.b", 32,
9735 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9737 /* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
9739 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "tst.b", 40,
9740 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9742 /* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
9744 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "tst.b", 40,
9745 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9747 /* tst.b${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
9749 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "tst.b", 40,
9750 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9752 /* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
9754 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "tst.b", 48,
9755 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9757 /* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
9759 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "tst.b", 48,
9760 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9762 /* tst.b${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
9764 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "tst.b", 48,
9765 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9767 /* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
9769 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "tst.b", 40,
9770 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9772 /* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
9774 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "tst.b", 40,
9775 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9777 /* tst.b${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
9779 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "tst.b", 40,
9780 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9782 /* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
9784 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "tst.b", 48,
9785 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9787 /* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
9789 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "tst.b", 48,
9790 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9792 /* tst.b${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
9794 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "tst.b", 48,
9795 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9797 /* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
9799 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "tst.b", 40,
9800 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9802 /* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
9804 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "tst.b", 40,
9805 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9807 /* tst.b${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
9809 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "tst.b", 40,
9810 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9812 /* tst.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
9814 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "tst16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "tst.b", 48,
9815 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9817 /* tst.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
9819 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "tst16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "tst.b", 48,
9820 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9822 /* tst.b${X} ${Dsp-16-u16},${Dsp-32-u16} */
9824 M32C_INSN_TST16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "tst16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "tst.b", 48,
9825 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9827 /* tst.b${X} $Src16RnQI,$Dst16RnQI */
9829 M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "tst.b", 16,
9830 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9832 /* tst.b${X} $Src16AnQI,$Dst16RnQI */
9834 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "tst.b", 16,
9835 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9837 /* tst.b${X} [$Src16An],$Dst16RnQI */
9839 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "tst.b", 16,
9840 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9842 /* tst.b${X} $Src16RnQI,$Dst16AnQI */
9844 M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "tst.b", 16,
9845 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9847 /* tst.b${X} $Src16AnQI,$Dst16AnQI */
9849 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "tst.b", 16,
9850 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9852 /* tst.b${X} [$Src16An],$Dst16AnQI */
9854 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "tst.b", 16,
9855 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9857 /* tst.b${X} $Src16RnQI,[$Dst16An] */
9859 M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "tst.b", 16,
9860 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9862 /* tst.b${X} $Src16AnQI,[$Dst16An] */
9864 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "tst.b", 16,
9865 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9867 /* tst.b${X} [$Src16An],[$Dst16An] */
9869 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "tst.b", 16,
9870 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9872 /* tst.b${X} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
9874 M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "tst.b", 24,
9875 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9877 /* tst.b${X} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
9879 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "tst.b", 24,
9880 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9882 /* tst.b${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
9884 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "tst.b", 24,
9885 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9887 /* tst.b${X} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
9889 M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "tst.b", 32,
9890 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9892 /* tst.b${X} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
9894 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "tst.b", 32,
9895 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9897 /* tst.b${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
9899 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "tst.b", 32,
9900 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9902 /* tst.b${X} $Src16RnQI,${Dsp-16-u8}[sb] */
9904 M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "tst.b", 24,
9905 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9907 /* tst.b${X} $Src16AnQI,${Dsp-16-u8}[sb] */
9909 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "tst.b", 24,
9910 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9912 /* tst.b${X} [$Src16An],${Dsp-16-u8}[sb] */
9914 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "tst.b", 24,
9915 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9917 /* tst.b${X} $Src16RnQI,${Dsp-16-u16}[sb] */
9919 M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "tst.b", 32,
9920 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9922 /* tst.b${X} $Src16AnQI,${Dsp-16-u16}[sb] */
9924 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "tst.b", 32,
9925 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9927 /* tst.b${X} [$Src16An],${Dsp-16-u16}[sb] */
9929 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "tst.b", 32,
9930 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9932 /* tst.b${X} $Src16RnQI,${Dsp-16-s8}[fb] */
9934 M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "tst.b", 24,
9935 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9937 /* tst.b${X} $Src16AnQI,${Dsp-16-s8}[fb] */
9939 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "tst.b", 24,
9940 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9942 /* tst.b${X} [$Src16An],${Dsp-16-s8}[fb] */
9944 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "tst.b", 24,
9945 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9947 /* tst.b${X} $Src16RnQI,${Dsp-16-u16} */
9949 M32C_INSN_TST16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "tst16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "tst.b", 32,
9950 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9952 /* tst.b${X} $Src16AnQI,${Dsp-16-u16} */
9954 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "tst16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "tst.b", 32,
9955 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9957 /* tst.b${X} [$Src16An],${Dsp-16-u16} */
9959 M32C_INSN_TST16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "tst16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "tst.b", 32,
9960 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
9962 /* tst.w${X} #${Imm-16-HI},$Dst32RnUnprefixedHI */
9964 M32C_INSN_TST32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "tst32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "tst.w", 32,
9965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9967 /* tst.w${X} #${Imm-16-HI},$Dst32AnUnprefixedHI */
9969 M32C_INSN_TST32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "tst32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "tst.w", 32,
9970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9972 /* tst.w${X} #${Imm-16-HI},[$Dst32AnUnprefixed] */
9974 M32C_INSN_TST32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "tst32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "tst.w", 32,
9975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9977 /* tst.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
9979 M32C_INSN_TST32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "tst.w", 40,
9980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9982 /* tst.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
9984 M32C_INSN_TST32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "tst.w", 40,
9985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9987 /* tst.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
9989 M32C_INSN_TST32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "tst.w", 40,
9990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9992 /* tst.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
9994 M32C_INSN_TST32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "tst.w", 48,
9995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
9997 /* tst.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
9999 M32C_INSN_TST32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "tst.w", 48,
10000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10002 /* tst.w${X} #${Imm-32-HI},${Dsp-16-s16}[fb] */
10004 M32C_INSN_TST32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "tst.w", 48,
10005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10007 /* tst.w${X} #${Imm-32-HI},${Dsp-16-u16} */
10009 M32C_INSN_TST32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "tst32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "tst.w", 48,
10010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10012 /* tst.w${X} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
10014 M32C_INSN_TST32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "tst32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "tst.w", 56,
10015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10017 /* tst.w${X} #${Imm-40-HI},${Dsp-16-u24} */
10019 M32C_INSN_TST32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "tst32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "tst.w", 56,
10020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10022 /* tst.b${X} #${Imm-16-QI},$Dst32RnUnprefixedQI */
10024 M32C_INSN_TST32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "tst32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "tst.b", 24,
10025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10027 /* tst.b${X} #${Imm-16-QI},$Dst32AnUnprefixedQI */
10029 M32C_INSN_TST32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "tst32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "tst.b", 24,
10030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10032 /* tst.b${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
10034 M32C_INSN_TST32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "tst32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "tst.b", 24,
10035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10037 /* tst.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
10039 M32C_INSN_TST32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "tst.b", 32,
10040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10042 /* tst.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
10044 M32C_INSN_TST32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "tst.b", 32,
10045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10047 /* tst.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
10049 M32C_INSN_TST32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "tst.b", 32,
10050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10052 /* tst.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
10054 M32C_INSN_TST32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "tst.b", 40,
10055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10057 /* tst.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
10059 M32C_INSN_TST32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "tst.b", 40,
10060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10062 /* tst.b${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
10064 M32C_INSN_TST32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "tst.b", 40,
10065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10067 /* tst.b${X} #${Imm-32-QI},${Dsp-16-u16} */
10069 M32C_INSN_TST32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "tst32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "tst.b", 40,
10070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10072 /* tst.b${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
10074 M32C_INSN_TST32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "tst32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "tst.b", 48,
10075 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10077 /* tst.b${X} #${Imm-40-QI},${Dsp-16-u24} */
10079 M32C_INSN_TST32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "tst32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "tst.b", 48,
10080 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10082 /* tst.w${X} #${Imm-16-HI},$Dst16RnHI */
10084 M32C_INSN_TST16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "tst16.w-imm-G-basic-dst16-Rn-direct-HI", "tst.w", 32,
10085 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10087 /* tst.w${X} #${Imm-16-HI},$Dst16AnHI */
10089 M32C_INSN_TST16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "tst16.w-imm-G-basic-dst16-An-direct-HI", "tst.w", 32,
10090 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10092 /* tst.w${X} #${Imm-16-HI},[$Dst16An] */
10094 M32C_INSN_TST16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "tst16.w-imm-G-basic-dst16-An-indirect-HI", "tst.w", 32,
10095 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10097 /* tst.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
10099 M32C_INSN_TST16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "tst16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "tst.w", 40,
10100 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10102 /* tst.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
10104 M32C_INSN_TST16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "tst16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "tst.w", 40,
10105 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10107 /* tst.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
10109 M32C_INSN_TST16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "tst16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "tst.w", 40,
10110 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10112 /* tst.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
10114 M32C_INSN_TST16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "tst16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "tst.w", 48,
10115 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10117 /* tst.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
10119 M32C_INSN_TST16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "tst16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "tst.w", 48,
10120 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10122 /* tst.w${X} #${Imm-32-HI},${Dsp-16-u16} */
10124 M32C_INSN_TST16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "tst16.w-imm-G-16-16-dst16-16-16-absolute-HI", "tst.w", 48,
10125 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10127 /* tst.b${X} #${Imm-16-QI},$Dst16RnQI */
10129 M32C_INSN_TST16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "tst16.b-imm-G-basic-dst16-Rn-direct-QI", "tst.b", 24,
10130 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10132 /* tst.b${X} #${Imm-16-QI},$Dst16AnQI */
10134 M32C_INSN_TST16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "tst16.b-imm-G-basic-dst16-An-direct-QI", "tst.b", 24,
10135 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10137 /* tst.b${X} #${Imm-16-QI},[$Dst16An] */
10139 M32C_INSN_TST16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "tst16.b-imm-G-basic-dst16-An-indirect-QI", "tst.b", 24,
10140 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10142 /* tst.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
10144 M32C_INSN_TST16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "tst16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "tst.b", 32,
10145 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10147 /* tst.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
10149 M32C_INSN_TST16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "tst16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "tst.b", 32,
10150 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10152 /* tst.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
10154 M32C_INSN_TST16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "tst16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "tst.b", 32,
10155 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10157 /* tst.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
10159 M32C_INSN_TST16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "tst16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "tst.b", 40,
10160 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10162 /* tst.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
10164 M32C_INSN_TST16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "tst16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "tst.b", 40,
10165 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10167 /* tst.b${X} #${Imm-32-QI},${Dsp-16-u16} */
10169 M32C_INSN_TST16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "tst16.b-imm-G-16-16-dst16-16-16-absolute-QI", "tst.b", 40,
10170 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
10172 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
10174 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 24,
10175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10177 /* subx${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
10179 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 24,
10180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10182 /* subx${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
10184 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 24,
10185 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10187 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
10189 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 24,
10190 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10192 /* subx${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
10194 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 24,
10195 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10197 /* subx${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
10199 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 24,
10200 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10202 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
10204 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 24,
10205 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10207 /* subx${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
10209 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 24,
10210 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10212 /* subx${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
10214 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 24,
10215 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10217 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
10219 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "subx", 32,
10220 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10222 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
10224 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "subx", 32,
10225 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10227 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
10229 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "subx", 32,
10230 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10232 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
10234 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "subx", 40,
10235 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10237 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
10239 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "subx", 40,
10240 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10242 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
10244 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "subx", 40,
10245 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10247 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
10249 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "subx", 48,
10250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10252 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
10254 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "subx", 48,
10255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10257 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
10259 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "subx", 48,
10260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10262 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
10264 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "subx", 32,
10265 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10267 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
10269 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "subx", 32,
10270 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10272 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
10274 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "subx", 32,
10275 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10277 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
10279 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "subx", 40,
10280 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10282 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
10284 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "subx", 40,
10285 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10287 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
10289 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "subx", 40,
10290 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10292 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
10294 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "subx", 32,
10295 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10297 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
10299 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "subx", 32,
10300 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10302 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
10304 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "subx", 32,
10305 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10307 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
10309 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "subx", 40,
10310 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10312 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
10314 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "subx", 40,
10315 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10317 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
10319 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "subx", 40,
10320 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10322 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
10324 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "subx", 40,
10325 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10327 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
10329 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "subx", 40,
10330 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10332 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
10334 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "subx", 40,
10335 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10337 /* subx${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
10339 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "subx", 48,
10340 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10342 /* subx${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
10344 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "subx", 48,
10345 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10347 /* subx${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
10349 M32C_INSN_SUBX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "subx", 48,
10350 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10352 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
10354 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 32,
10355 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10357 /* subx${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
10359 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 32,
10360 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10362 /* subx${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
10364 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 32,
10365 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10367 /* subx${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
10369 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 32,
10370 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10372 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
10374 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 32,
10375 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10377 /* subx${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
10379 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 32,
10380 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10382 /* subx${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
10384 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 32,
10385 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10387 /* subx${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
10389 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 32,
10390 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10392 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
10394 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 32,
10395 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10397 /* subx${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
10399 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 32,
10400 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10402 /* subx${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
10404 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 32,
10405 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10407 /* subx${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
10409 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 32,
10410 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10412 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
10414 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "subx", 40,
10415 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10417 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
10419 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "subx", 40,
10420 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10422 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
10424 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "subx", 40,
10425 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10427 /* subx${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
10429 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "subx", 40,
10430 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10432 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
10434 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "subx", 48,
10435 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10437 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
10439 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "subx", 48,
10440 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10442 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
10444 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "subx", 48,
10445 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10447 /* subx${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
10449 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "subx", 48,
10450 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10452 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
10454 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "subx", 56,
10455 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10457 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
10459 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "subx", 56,
10460 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10462 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
10464 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "subx", 56,
10465 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10467 /* subx${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
10469 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "subx", 56,
10470 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10472 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
10474 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "subx", 40,
10475 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10477 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
10479 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "subx", 40,
10480 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10482 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
10484 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "subx", 40,
10485 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10487 /* subx${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
10489 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "subx", 40,
10490 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10492 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
10494 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "subx", 48,
10495 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10497 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
10499 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "subx", 48,
10500 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10502 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
10504 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "subx", 48,
10505 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10507 /* subx${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
10509 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "subx", 48,
10510 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10512 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
10514 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "subx", 40,
10515 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10517 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
10519 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "subx", 40,
10520 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10522 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
10524 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "subx", 40,
10525 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10527 /* subx${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
10529 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "subx", 40,
10530 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10532 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
10534 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "subx", 48,
10535 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10537 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
10539 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "subx", 48,
10540 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10542 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
10544 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "subx", 48,
10545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10547 /* subx${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
10549 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "subx", 48,
10550 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10552 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
10554 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "subx", 48,
10555 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10557 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
10559 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "subx", 48,
10560 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10562 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
10564 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "subx", 48,
10565 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10567 /* subx${G} ${Dsp-16-u16},${Dsp-32-u16} */
10569 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "subx", 48,
10570 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10572 /* subx${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
10574 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "subx", 56,
10575 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10577 /* subx${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
10579 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "subx", 56,
10580 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10582 /* subx${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
10584 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "subx", 56,
10585 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10587 /* subx${G} ${Dsp-16-u16},${Dsp-32-u24} */
10589 M32C_INSN_SUBX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "subx", 56,
10590 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10592 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
10594 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 40,
10595 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10597 /* subx${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
10599 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 40,
10600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10602 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
10604 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 40,
10605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10607 /* subx${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
10609 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 40,
10610 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10612 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
10614 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 40,
10615 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10617 /* subx${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
10619 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 40,
10620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10622 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
10624 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-SI", "subx", 48,
10625 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10627 /* subx${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
10629 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-SI", "subx", 48,
10630 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10632 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
10634 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-SI", "subx", 56,
10635 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10637 /* subx${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
10639 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-SI", "subx", 56,
10640 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10642 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
10644 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-SI", "subx", 64,
10645 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10647 /* subx${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
10649 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-SI", "subx", 64,
10650 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10652 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
10654 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-SI", "subx", 48,
10655 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10657 /* subx${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
10659 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-SI", "subx", 48,
10660 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10662 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
10664 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-SI", "subx", 56,
10665 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10667 /* subx${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
10669 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-SI", "subx", 56,
10670 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10672 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
10674 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-SI", "subx", 48,
10675 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10677 /* subx${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
10679 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-SI", "subx", 48,
10680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10682 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
10684 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-SI", "subx", 56,
10685 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10687 /* subx${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
10689 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-SI", "subx", 56,
10690 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10692 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
10694 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-SI", "subx", 56,
10695 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10697 /* subx${G} ${Dsp-16-u24},${Dsp-40-u16} */
10699 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-SI", "subx", 56,
10700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10702 /* subx${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
10704 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-SI", "subx", 64,
10705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10707 /* subx${G} ${Dsp-16-u24},${Dsp-40-u24} */
10709 M32C_INSN_SUBX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "subx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-SI", "subx", 64,
10710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10712 /* subx${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedSI */
10714 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 16,
10715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10717 /* subx${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedSI */
10719 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 16,
10720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10722 /* subx${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
10724 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "subx", 16,
10725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10727 /* subx${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedSI */
10729 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 16,
10730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10732 /* subx${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedSI */
10734 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 16,
10735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10737 /* subx${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
10739 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "subx", 16,
10740 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10742 /* subx${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
10744 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 16,
10745 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10747 /* subx${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
10749 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 16,
10750 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10752 /* subx${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
10754 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "subx", 16,
10755 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10757 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
10759 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "subx", 24,
10760 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10762 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
10764 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "subx", 24,
10765 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10767 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
10769 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "subx", 24,
10770 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10772 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
10774 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "subx", 32,
10775 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10777 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
10779 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "subx", 32,
10780 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10782 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
10784 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "subx", 32,
10785 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10787 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
10789 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "subx", 40,
10790 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10792 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
10794 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "subx", 40,
10795 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10797 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
10799 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "subx", 40,
10800 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10802 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
10804 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "subx", 24,
10805 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10807 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
10809 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "subx", 24,
10810 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10812 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
10814 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "subx", 24,
10815 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10817 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
10819 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "subx", 32,
10820 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10822 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
10824 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "subx", 32,
10825 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10827 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
10829 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "subx", 32,
10830 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10832 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
10834 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "subx", 24,
10835 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10837 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
10839 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "subx", 24,
10840 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10842 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
10844 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "subx", 24,
10845 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10847 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
10849 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "subx", 32,
10850 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10852 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
10854 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "subx", 32,
10855 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10857 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
10859 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "subx", 32,
10860 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10862 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
10864 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "subx", 32,
10865 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10867 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
10869 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "subx", 32,
10870 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10872 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
10874 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "subx", 32,
10875 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10877 /* subx${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
10879 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "subx", 40,
10880 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10882 /* subx${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
10884 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "subx", 40,
10885 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10887 /* subx${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
10889 M32C_INSN_SUBX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "subx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "subx", 40,
10890 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10892 /* subx${G} #${Imm-16-QI},$Dst32RnUnprefixedSI */
10894 M32C_INSN_SUBX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "subx32-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "subx", 24,
10895 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10897 /* subx${G} #${Imm-16-QI},$Dst32AnUnprefixedSI */
10899 M32C_INSN_SUBX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "subx32-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "subx", 24,
10900 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10902 /* subx${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
10904 M32C_INSN_SUBX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "subx32-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "subx", 24,
10905 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10907 /* subx${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
10909 M32C_INSN_SUBX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "subx", 32,
10910 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10912 /* subx${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
10914 M32C_INSN_SUBX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "subx", 32,
10915 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10917 /* subx${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
10919 M32C_INSN_SUBX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "subx", 32,
10920 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10922 /* subx${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
10924 M32C_INSN_SUBX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "subx", 40,
10925 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10927 /* subx${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
10929 M32C_INSN_SUBX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "subx", 40,
10930 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10932 /* subx${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
10934 M32C_INSN_SUBX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "subx", 40,
10935 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10937 /* subx${G} #${Imm-32-QI},${Dsp-16-u16} */
10939 M32C_INSN_SUBX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "subx32-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "subx", 40,
10940 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10942 /* subx${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
10944 M32C_INSN_SUBX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "subx32-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "subx", 48,
10945 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10947 /* subx${G} #${Imm-40-QI},${Dsp-16-u24} */
10949 M32C_INSN_SUBX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "subx32-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "subx", 48,
10950 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10952 /* stzx.w #${Imm-16-HI},#${Imm-32-HI},$Dst32RnUnprefixedHI */
10954 M32C_INSN_STZX32_W_IMM_16_HI_IMM_32_HI_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "stzx32.w-Imm-16-HI-Imm-32-HI-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "stzx.w", 48,
10955 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10957 /* stzx.w #${Imm-16-HI},#${Imm-32-HI},$Dst32AnUnprefixedHI */
10959 M32C_INSN_STZX32_W_IMM_16_HI_IMM_32_HI_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "stzx32.w-Imm-16-HI-Imm-32-HI-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "stzx.w", 48,
10960 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10962 /* stzx.w #${Imm-16-HI},#${Imm-32-HI},[$Dst32AnUnprefixed] */
10964 M32C_INSN_STZX32_W_IMM_16_HI_IMM_32_HI_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "stzx32.w-Imm-16-HI-Imm-32-HI-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "stzx.w", 48,
10965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10967 /* stzx.w #${Imm-24-HI},#${Imm-40-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
10969 M32C_INSN_STZX32_W_IMM_24_HI_IMM_40_HI_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-24-HI-Imm-40-HI-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "stzx.w", 56,
10970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10972 /* stzx.w #${Imm-24-HI},#${Imm-40-HI},${Dsp-16-u8}[sb] */
10974 M32C_INSN_STZX32_W_IMM_24_HI_IMM_40_HI_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-24-HI-Imm-40-HI-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "stzx.w", 56,
10975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10977 /* stzx.w #${Imm-24-HI},#${Imm-40-HI},${Dsp-16-s8}[fb] */
10979 M32C_INSN_STZX32_W_IMM_24_HI_IMM_40_HI_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-24-HI-Imm-40-HI-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "stzx.w", 56,
10980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10982 /* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
10984 M32C_INSN_STZX32_W_IMM_32_HI_IMM_48_HI_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-32-HI-Imm-48-HI-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "stzx.w", 64,
10985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10987 /* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-u16}[sb] */
10989 M32C_INSN_STZX32_W_IMM_32_HI_IMM_48_HI_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-32-HI-Imm-48-HI-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "stzx.w", 64,
10990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10992 /* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-s16}[fb] */
10994 M32C_INSN_STZX32_W_IMM_32_HI_IMM_48_HI_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-32-HI-Imm-48-HI-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "stzx.w", 64,
10995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
10997 /* stzx.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-16-u16} */
10999 M32C_INSN_STZX32_W_IMM_32_HI_IMM_48_HI_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "stzx32.w-Imm-32-HI-Imm-48-HI-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "stzx.w", 64,
11000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11002 /* stzx.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11004 M32C_INSN_STZX32_W_IMM_40_HI_IMM_56_HI_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "stzx32.w-Imm-40-HI-Imm-56-HI-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "stzx.w", 72,
11005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11007 /* stzx.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-16-u24} */
11009 M32C_INSN_STZX32_W_IMM_40_HI_IMM_56_HI_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "stzx32.w-Imm-40-HI-Imm-56-HI-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "stzx.w", 72,
11010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11012 /* stzx.b #${Imm-16-QI},#${Imm-24-QI},$Dst32RnUnprefixedQI */
11014 M32C_INSN_STZX32_B_IMM_16_QI_IMM_24_QI_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "stzx32.b-Imm-16-QI-Imm-24-QI-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "stzx.b", 32,
11015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11017 /* stzx.b #${Imm-16-QI},#${Imm-24-QI},$Dst32AnUnprefixedQI */
11019 M32C_INSN_STZX32_B_IMM_16_QI_IMM_24_QI_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "stzx32.b-Imm-16-QI-Imm-24-QI-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "stzx.b", 32,
11020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11022 /* stzx.b #${Imm-16-QI},#${Imm-24-QI},[$Dst32AnUnprefixed] */
11024 M32C_INSN_STZX32_B_IMM_16_QI_IMM_24_QI_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "stzx32.b-Imm-16-QI-Imm-24-QI-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "stzx.b", 32,
11025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11027 /* stzx.b #${Imm-24-QI},#${Imm-32-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11029 M32C_INSN_STZX32_B_IMM_24_QI_IMM_32_QI_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-24-QI-Imm-32-QI-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "stzx.b", 40,
11030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11032 /* stzx.b #${Imm-24-QI},#${Imm-32-QI},${Dsp-16-u8}[sb] */
11034 M32C_INSN_STZX32_B_IMM_24_QI_IMM_32_QI_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-24-QI-Imm-32-QI-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "stzx.b", 40,
11035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11037 /* stzx.b #${Imm-24-QI},#${Imm-32-QI},${Dsp-16-s8}[fb] */
11039 M32C_INSN_STZX32_B_IMM_24_QI_IMM_32_QI_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-24-QI-Imm-32-QI-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "stzx.b", 40,
11040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11042 /* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11044 M32C_INSN_STZX32_B_IMM_32_QI_IMM_40_QI_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-32-QI-Imm-40-QI-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "stzx.b", 48,
11045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11047 /* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-u16}[sb] */
11049 M32C_INSN_STZX32_B_IMM_32_QI_IMM_40_QI_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-32-QI-Imm-40-QI-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "stzx.b", 48,
11050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11052 /* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-s16}[fb] */
11054 M32C_INSN_STZX32_B_IMM_32_QI_IMM_40_QI_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-32-QI-Imm-40-QI-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "stzx.b", 48,
11055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11057 /* stzx.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-16-u16} */
11059 M32C_INSN_STZX32_B_IMM_32_QI_IMM_40_QI_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "stzx32.b-Imm-32-QI-Imm-40-QI-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "stzx.b", 48,
11060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11062 /* stzx.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11064 M32C_INSN_STZX32_B_IMM_40_QI_IMM_48_QI_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "stzx32.b-Imm-40-QI-Imm-48-QI-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "stzx.b", 56,
11065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11067 /* stzx.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-16-u24} */
11069 M32C_INSN_STZX32_B_IMM_40_QI_IMM_48_QI_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "stzx32.b-Imm-40-QI-Imm-48-QI-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "stzx.b", 56,
11070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11072 /* stz.w${X} #${Imm-16-HI},$Dst32RnUnprefixedHI */
11074 M32C_INSN_STZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "stz32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "stz.w", 32,
11075 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11077 /* stz.w${X} #${Imm-16-HI},$Dst32AnUnprefixedHI */
11079 M32C_INSN_STZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "stz32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "stz.w", 32,
11080 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11082 /* stz.w${X} #${Imm-16-HI},[$Dst32AnUnprefixed] */
11084 M32C_INSN_STZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "stz32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "stz.w", 32,
11085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11087 /* stz.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11089 M32C_INSN_STZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "stz.w", 40,
11090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11092 /* stz.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
11094 M32C_INSN_STZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "stz.w", 40,
11095 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11097 /* stz.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
11099 M32C_INSN_STZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "stz.w", 40,
11100 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11102 /* stz.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11104 M32C_INSN_STZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "stz.w", 48,
11105 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11107 /* stz.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
11109 M32C_INSN_STZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "stz.w", 48,
11110 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11112 /* stz.w${X} #${Imm-32-HI},${Dsp-16-s16}[fb] */
11114 M32C_INSN_STZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "stz.w", 48,
11115 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11117 /* stz.w${X} #${Imm-32-HI},${Dsp-16-u16} */
11119 M32C_INSN_STZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "stz32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "stz.w", 48,
11120 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11122 /* stz.w${X} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11124 M32C_INSN_STZ32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "stz32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "stz.w", 56,
11125 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11127 /* stz.w${X} #${Imm-40-HI},${Dsp-16-u24} */
11129 M32C_INSN_STZ32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "stz32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "stz.w", 56,
11130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11132 /* stz.b${X} #${Imm-16-QI},$Dst32RnUnprefixedQI */
11134 M32C_INSN_STZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "stz32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "stz.b", 24,
11135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11137 /* stz.b${X} #${Imm-16-QI},$Dst32AnUnprefixedQI */
11139 M32C_INSN_STZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "stz32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "stz.b", 24,
11140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11142 /* stz.b${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
11144 M32C_INSN_STZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "stz32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "stz.b", 24,
11145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11147 /* stz.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11149 M32C_INSN_STZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "stz.b", 32,
11150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11152 /* stz.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
11154 M32C_INSN_STZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "stz.b", 32,
11155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11157 /* stz.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
11159 M32C_INSN_STZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "stz.b", 32,
11160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11162 /* stz.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11164 M32C_INSN_STZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "stz.b", 40,
11165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11167 /* stz.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
11169 M32C_INSN_STZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "stz.b", 40,
11170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11172 /* stz.b${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
11174 M32C_INSN_STZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "stz.b", 40,
11175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11177 /* stz.b${X} #${Imm-32-QI},${Dsp-16-u16} */
11179 M32C_INSN_STZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "stz32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "stz.b", 40,
11180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11182 /* stz.b${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11184 M32C_INSN_STZ32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "stz32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "stz.b", 48,
11185 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11187 /* stz.b${X} #${Imm-40-QI},${Dsp-16-u24} */
11189 M32C_INSN_STZ32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "stz32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "stz.b", 48,
11190 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11192 /* stz${S} #${Imm-8-QI},r0l */
11194 M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "stz16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "stz", 16,
11195 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11197 /* stz${S} #${Imm-8-QI},r0h */
11199 M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "stz16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "stz", 16,
11200 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11202 /* stz${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
11204 M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "stz16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "stz", 24,
11205 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11207 /* stz${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
11209 M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "stz16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "stz", 24,
11210 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11212 /* stz${S} #${Imm-8-QI},${Dsp-16-u16} */
11214 M32C_INSN_STZ16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "stz16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "stz", 32,
11215 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11217 /* stnz.w${X} #${Imm-16-HI},$Dst32RnUnprefixedHI */
11219 M32C_INSN_STNZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "stnz32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "stnz.w", 32,
11220 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11222 /* stnz.w${X} #${Imm-16-HI},$Dst32AnUnprefixedHI */
11224 M32C_INSN_STNZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "stnz32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "stnz.w", 32,
11225 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11227 /* stnz.w${X} #${Imm-16-HI},[$Dst32AnUnprefixed] */
11229 M32C_INSN_STNZ32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "stnz32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "stnz.w", 32,
11230 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11232 /* stnz.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11234 M32C_INSN_STNZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "stnz.w", 40,
11235 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11237 /* stnz.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
11239 M32C_INSN_STNZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "stnz.w", 40,
11240 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11242 /* stnz.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
11244 M32C_INSN_STNZ32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "stnz.w", 40,
11245 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11247 /* stnz.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11249 M32C_INSN_STNZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "stnz.w", 48,
11250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11252 /* stnz.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
11254 M32C_INSN_STNZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "stnz.w", 48,
11255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11257 /* stnz.w${X} #${Imm-32-HI},${Dsp-16-s16}[fb] */
11259 M32C_INSN_STNZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "stnz.w", 48,
11260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11262 /* stnz.w${X} #${Imm-32-HI},${Dsp-16-u16} */
11264 M32C_INSN_STNZ32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "stnz32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "stnz.w", 48,
11265 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11267 /* stnz.w${X} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11269 M32C_INSN_STNZ32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "stnz32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "stnz.w", 56,
11270 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11272 /* stnz.w${X} #${Imm-40-HI},${Dsp-16-u24} */
11274 M32C_INSN_STNZ32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "stnz32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "stnz.w", 56,
11275 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11277 /* stnz.b${X} #${Imm-16-QI},$Dst32RnUnprefixedQI */
11279 M32C_INSN_STNZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "stnz32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "stnz.b", 24,
11280 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11282 /* stnz.b${X} #${Imm-16-QI},$Dst32AnUnprefixedQI */
11284 M32C_INSN_STNZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "stnz32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "stnz.b", 24,
11285 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11287 /* stnz.b${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
11289 M32C_INSN_STNZ32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "stnz32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "stnz.b", 24,
11290 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11292 /* stnz.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11294 M32C_INSN_STNZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "stnz.b", 32,
11295 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11297 /* stnz.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
11299 M32C_INSN_STNZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "stnz.b", 32,
11300 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11302 /* stnz.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
11304 M32C_INSN_STNZ32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "stnz.b", 32,
11305 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11307 /* stnz.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11309 M32C_INSN_STNZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "stnz.b", 40,
11310 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11312 /* stnz.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
11314 M32C_INSN_STNZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "stnz.b", 40,
11315 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11317 /* stnz.b${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
11319 M32C_INSN_STNZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "stnz.b", 40,
11320 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11322 /* stnz.b${X} #${Imm-32-QI},${Dsp-16-u16} */
11324 M32C_INSN_STNZ32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "stnz32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "stnz.b", 40,
11325 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11327 /* stnz.b${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11329 M32C_INSN_STNZ32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "stnz32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "stnz.b", 48,
11330 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11332 /* stnz.b${X} #${Imm-40-QI},${Dsp-16-u24} */
11334 M32C_INSN_STNZ32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "stnz32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "stnz.b", 48,
11335 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11337 /* stnz${S} #${Imm-8-QI},r0l */
11339 M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "stnz", 16,
11340 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11342 /* stnz${S} #${Imm-8-QI},r0h */
11344 M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "stnz", 16,
11345 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11347 /* stnz${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
11349 M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "stnz", 24,
11350 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11352 /* stnz${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
11354 M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "stnz", 24,
11355 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11357 /* stnz${S} #${Imm-8-QI},${Dsp-16-u16} */
11359 M32C_INSN_STNZ16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "stnz16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "stnz", 32,
11360 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11362 /* shlnc.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
11364 M32C_INSN_SHLNC32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "shlnc32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "shlnc.l", 24,
11365 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11367 /* shlnc.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
11369 M32C_INSN_SHLNC32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "shlnc32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "shlnc.l", 24,
11370 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11372 /* shlnc.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
11374 M32C_INSN_SHLNC32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "shlnc32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "shlnc.l", 24,
11375 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11377 /* shlnc.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11379 M32C_INSN_SHLNC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "shlnc.l", 32,
11380 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11382 /* shlnc.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
11384 M32C_INSN_SHLNC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "shlnc.l", 32,
11385 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11387 /* shlnc.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
11389 M32C_INSN_SHLNC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "shlnc.l", 32,
11390 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11392 /* shlnc.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11394 M32C_INSN_SHLNC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "shlnc.l", 40,
11395 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11397 /* shlnc.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
11399 M32C_INSN_SHLNC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "shlnc.l", 40,
11400 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11402 /* shlnc.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
11404 M32C_INSN_SHLNC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "shlnc.l", 40,
11405 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11407 /* shlnc.l${X} #${Imm-32-QI},${Dsp-16-u16} */
11409 M32C_INSN_SHLNC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "shlnc.l", 40,
11410 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11412 /* shlnc.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11414 M32C_INSN_SHLNC32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "shlnc.l", 48,
11415 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11417 /* shlnc.l${X} #${Imm-40-QI},${Dsp-16-u24} */
11419 M32C_INSN_SHLNC32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "shlnc32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "shlnc.l", 48,
11420 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11422 /* shl.l r1h,$Dst32RnUnprefixedSI */
11424 M32C_INSN_SHL32_L_DST_DST32_RN_DIRECT_UNPREFIXED_SI, "shl32.l-dst-dst32-Rn-direct-Unprefixed-SI", "shl.l", 16,
11425 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11427 /* shl.l r1h,$Dst32AnUnprefixedSI */
11429 M32C_INSN_SHL32_L_DST_DST32_AN_DIRECT_UNPREFIXED_SI, "shl32.l-dst-dst32-An-direct-Unprefixed-SI", "shl.l", 16,
11430 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11432 /* shl.l r1h,[$Dst32AnUnprefixed] */
11434 M32C_INSN_SHL32_L_DST_DST32_AN_INDIRECT_UNPREFIXED_SI, "shl32.l-dst-dst32-An-indirect-Unprefixed-SI", "shl.l", 16,
11435 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11437 /* shl.l r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
11439 M32C_INSN_SHL32_L_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-8-An-relative-Unprefixed-SI", "shl.l", 24,
11440 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11442 /* shl.l r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
11444 M32C_INSN_SHL32_L_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-16-An-relative-Unprefixed-SI", "shl.l", 32,
11445 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11447 /* shl.l r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
11449 M32C_INSN_SHL32_L_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-24-An-relative-Unprefixed-SI", "shl.l", 40,
11450 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11452 /* shl.l r1h,${Dsp-16-u8}[sb] */
11454 M32C_INSN_SHL32_L_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-8-SB-relative-Unprefixed-SI", "shl.l", 24,
11455 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11457 /* shl.l r1h,${Dsp-16-u16}[sb] */
11459 M32C_INSN_SHL32_L_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-16-SB-relative-Unprefixed-SI", "shl.l", 32,
11460 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11462 /* shl.l r1h,${Dsp-16-s8}[fb] */
11464 M32C_INSN_SHL32_L_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-8-FB-relative-Unprefixed-SI", "shl.l", 24,
11465 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11467 /* shl.l r1h,${Dsp-16-s16}[fb] */
11469 M32C_INSN_SHL32_L_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-16-FB-relative-Unprefixed-SI", "shl.l", 32,
11470 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11472 /* shl.l r1h,${Dsp-16-u16} */
11474 M32C_INSN_SHL32_L_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-16-absolute-Unprefixed-SI", "shl.l", 32,
11475 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11477 /* shl.l r1h,${Dsp-16-u24} */
11479 M32C_INSN_SHL32_L_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "shl32.l-dst-dst32-16-24-absolute-Unprefixed-SI", "shl.l", 40,
11480 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11482 /* shl.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
11484 M32C_INSN_SHL32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "shl32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "shl.l", 24,
11485 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11487 /* shl.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
11489 M32C_INSN_SHL32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "shl32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "shl.l", 24,
11490 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11492 /* shl.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
11494 M32C_INSN_SHL32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "shl32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "shl.l", 24,
11495 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11497 /* shl.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11499 M32C_INSN_SHL32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "shl.l", 32,
11500 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11502 /* shl.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
11504 M32C_INSN_SHL32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "shl.l", 32,
11505 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11507 /* shl.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
11509 M32C_INSN_SHL32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "shl.l", 32,
11510 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11512 /* shl.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11514 M32C_INSN_SHL32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "shl.l", 40,
11515 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11517 /* shl.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
11519 M32C_INSN_SHL32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "shl.l", 40,
11520 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11522 /* shl.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
11524 M32C_INSN_SHL32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "shl.l", 40,
11525 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11527 /* shl.l${X} #${Imm-32-QI},${Dsp-16-u16} */
11529 M32C_INSN_SHL32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "shl32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "shl.l", 40,
11530 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11532 /* shl.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11534 M32C_INSN_SHL32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "shl32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "shl.l", 48,
11535 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11537 /* shl.l${X} #${Imm-40-QI},${Dsp-16-u24} */
11539 M32C_INSN_SHL32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "shl32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "shl.l", 48,
11540 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11542 /* shl.w r1h,$Dst32RnUnprefixedHI */
11544 M32C_INSN_SHL32_W_DST_DST32_RN_DIRECT_UNPREFIXED_HI, "shl32.w-dst-dst32-Rn-direct-Unprefixed-HI", "shl.w", 16,
11545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11547 /* shl.w r1h,$Dst32AnUnprefixedHI */
11549 M32C_INSN_SHL32_W_DST_DST32_AN_DIRECT_UNPREFIXED_HI, "shl32.w-dst-dst32-An-direct-Unprefixed-HI", "shl.w", 16,
11550 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11552 /* shl.w r1h,[$Dst32AnUnprefixed] */
11554 M32C_INSN_SHL32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_HI, "shl32.w-dst-dst32-An-indirect-Unprefixed-HI", "shl.w", 16,
11555 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11557 /* shl.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
11559 M32C_INSN_SHL32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-8-An-relative-Unprefixed-HI", "shl.w", 24,
11560 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11562 /* shl.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
11564 M32C_INSN_SHL32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-16-An-relative-Unprefixed-HI", "shl.w", 32,
11565 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11567 /* shl.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
11569 M32C_INSN_SHL32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-24-An-relative-Unprefixed-HI", "shl.w", 40,
11570 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11572 /* shl.w r1h,${Dsp-16-u8}[sb] */
11574 M32C_INSN_SHL32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-8-SB-relative-Unprefixed-HI", "shl.w", 24,
11575 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11577 /* shl.w r1h,${Dsp-16-u16}[sb] */
11579 M32C_INSN_SHL32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-16-SB-relative-Unprefixed-HI", "shl.w", 32,
11580 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11582 /* shl.w r1h,${Dsp-16-s8}[fb] */
11584 M32C_INSN_SHL32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-8-FB-relative-Unprefixed-HI", "shl.w", 24,
11585 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11587 /* shl.w r1h,${Dsp-16-s16}[fb] */
11589 M32C_INSN_SHL32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-16-FB-relative-Unprefixed-HI", "shl.w", 32,
11590 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11592 /* shl.w r1h,${Dsp-16-u16} */
11594 M32C_INSN_SHL32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-16-absolute-Unprefixed-HI", "shl.w", 32,
11595 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11597 /* shl.w r1h,${Dsp-16-u24} */
11599 M32C_INSN_SHL32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "shl32.w-dst-dst32-16-24-absolute-Unprefixed-HI", "shl.w", 40,
11600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11602 /* shl.b r1h,$Dst32RnUnprefixedQI */
11604 M32C_INSN_SHL32_B_DST_DST32_RN_DIRECT_UNPREFIXED_QI, "shl32.b-dst-dst32-Rn-direct-Unprefixed-QI", "shl.b", 16,
11605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11607 /* shl.b r1h,$Dst32AnUnprefixedQI */
11609 M32C_INSN_SHL32_B_DST_DST32_AN_DIRECT_UNPREFIXED_QI, "shl32.b-dst-dst32-An-direct-Unprefixed-QI", "shl.b", 16,
11610 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11612 /* shl.b r1h,[$Dst32AnUnprefixed] */
11614 M32C_INSN_SHL32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_QI, "shl32.b-dst-dst32-An-indirect-Unprefixed-QI", "shl.b", 16,
11615 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11617 /* shl.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
11619 M32C_INSN_SHL32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-8-An-relative-Unprefixed-QI", "shl.b", 24,
11620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11622 /* shl.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
11624 M32C_INSN_SHL32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-16-An-relative-Unprefixed-QI", "shl.b", 32,
11625 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11627 /* shl.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
11629 M32C_INSN_SHL32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-24-An-relative-Unprefixed-QI", "shl.b", 40,
11630 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11632 /* shl.b r1h,${Dsp-16-u8}[sb] */
11634 M32C_INSN_SHL32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-8-SB-relative-Unprefixed-QI", "shl.b", 24,
11635 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11637 /* shl.b r1h,${Dsp-16-u16}[sb] */
11639 M32C_INSN_SHL32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-16-SB-relative-Unprefixed-QI", "shl.b", 32,
11640 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11642 /* shl.b r1h,${Dsp-16-s8}[fb] */
11644 M32C_INSN_SHL32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-8-FB-relative-Unprefixed-QI", "shl.b", 24,
11645 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11647 /* shl.b r1h,${Dsp-16-s16}[fb] */
11649 M32C_INSN_SHL32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-16-FB-relative-Unprefixed-QI", "shl.b", 32,
11650 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11652 /* shl.b r1h,${Dsp-16-u16} */
11654 M32C_INSN_SHL32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-16-absolute-Unprefixed-QI", "shl.b", 32,
11655 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11657 /* shl.b r1h,${Dsp-16-u24} */
11659 M32C_INSN_SHL32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "shl32.b-dst-dst32-16-24-absolute-Unprefixed-QI", "shl.b", 40,
11660 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11662 /* shl.w r1h,$Dst16RnHI */
11664 M32C_INSN_SHL16_W_DST_DST16_RN_DIRECT_HI, "shl16.w-dst-dst16-Rn-direct-HI", "shl.w", 16,
11665 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11667 /* shl.w r1h,$Dst16AnHI */
11669 M32C_INSN_SHL16_W_DST_DST16_AN_DIRECT_HI, "shl16.w-dst-dst16-An-direct-HI", "shl.w", 16,
11670 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11672 /* shl.w r1h,[$Dst16An] */
11674 M32C_INSN_SHL16_W_DST_DST16_AN_INDIRECT_HI, "shl16.w-dst-dst16-An-indirect-HI", "shl.w", 16,
11675 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11677 /* shl.w r1h,${Dsp-16-u8}[$Dst16An] */
11679 M32C_INSN_SHL16_W_DST_DST16_16_8_AN_RELATIVE_HI, "shl16.w-dst-dst16-16-8-An-relative-HI", "shl.w", 24,
11680 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11682 /* shl.w r1h,${Dsp-16-u16}[$Dst16An] */
11684 M32C_INSN_SHL16_W_DST_DST16_16_16_AN_RELATIVE_HI, "shl16.w-dst-dst16-16-16-An-relative-HI", "shl.w", 32,
11685 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11687 /* shl.w r1h,${Dsp-16-u8}[sb] */
11689 M32C_INSN_SHL16_W_DST_DST16_16_8_SB_RELATIVE_HI, "shl16.w-dst-dst16-16-8-SB-relative-HI", "shl.w", 24,
11690 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11692 /* shl.w r1h,${Dsp-16-u16}[sb] */
11694 M32C_INSN_SHL16_W_DST_DST16_16_16_SB_RELATIVE_HI, "shl16.w-dst-dst16-16-16-SB-relative-HI", "shl.w", 32,
11695 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11697 /* shl.w r1h,${Dsp-16-s8}[fb] */
11699 M32C_INSN_SHL16_W_DST_DST16_16_8_FB_RELATIVE_HI, "shl16.w-dst-dst16-16-8-FB-relative-HI", "shl.w", 24,
11700 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11702 /* shl.w r1h,${Dsp-16-u16} */
11704 M32C_INSN_SHL16_W_DST_DST16_16_16_ABSOLUTE_HI, "shl16.w-dst-dst16-16-16-absolute-HI", "shl.w", 32,
11705 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11707 /* shl.b r1h,$Dst16RnQI */
11709 M32C_INSN_SHL16_B_DST_DST16_RN_DIRECT_QI, "shl16.b-dst-dst16-Rn-direct-QI", "shl.b", 16,
11710 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11712 /* shl.b r1h,$Dst16AnQI */
11714 M32C_INSN_SHL16_B_DST_DST16_AN_DIRECT_QI, "shl16.b-dst-dst16-An-direct-QI", "shl.b", 16,
11715 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11717 /* shl.b r1h,[$Dst16An] */
11719 M32C_INSN_SHL16_B_DST_DST16_AN_INDIRECT_QI, "shl16.b-dst-dst16-An-indirect-QI", "shl.b", 16,
11720 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11722 /* shl.b r1h,${Dsp-16-u8}[$Dst16An] */
11724 M32C_INSN_SHL16_B_DST_DST16_16_8_AN_RELATIVE_QI, "shl16.b-dst-dst16-16-8-An-relative-QI", "shl.b", 24,
11725 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11727 /* shl.b r1h,${Dsp-16-u16}[$Dst16An] */
11729 M32C_INSN_SHL16_B_DST_DST16_16_16_AN_RELATIVE_QI, "shl16.b-dst-dst16-16-16-An-relative-QI", "shl.b", 32,
11730 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11732 /* shl.b r1h,${Dsp-16-u8}[sb] */
11734 M32C_INSN_SHL16_B_DST_DST16_16_8_SB_RELATIVE_QI, "shl16.b-dst-dst16-16-8-SB-relative-QI", "shl.b", 24,
11735 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11737 /* shl.b r1h,${Dsp-16-u16}[sb] */
11739 M32C_INSN_SHL16_B_DST_DST16_16_16_SB_RELATIVE_QI, "shl16.b-dst-dst16-16-16-SB-relative-QI", "shl.b", 32,
11740 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11742 /* shl.b r1h,${Dsp-16-s8}[fb] */
11744 M32C_INSN_SHL16_B_DST_DST16_16_8_FB_RELATIVE_QI, "shl16.b-dst-dst16-16-8-FB-relative-QI", "shl.b", 24,
11745 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11747 /* shl.b r1h,${Dsp-16-u16} */
11749 M32C_INSN_SHL16_B_DST_DST16_16_16_ABSOLUTE_QI, "shl16.b-dst-dst16-16-16-absolute-QI", "shl.b", 32,
11750 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11752 /* shl.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */
11754 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "shl.w", 16,
11755 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11757 /* shl.w${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedHI */
11759 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "shl.w", 16,
11760 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11762 /* shl.w${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
11764 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "shl.w", 16,
11765 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11767 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11769 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "shl.w", 24,
11770 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11772 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11774 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "shl.w", 32,
11775 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11777 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11779 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "shl.w", 40,
11780 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11782 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
11784 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "shl.w", 24,
11785 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11787 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
11789 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "shl.w", 32,
11790 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11792 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
11794 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "shl.w", 24,
11795 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11797 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
11799 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "shl.w", 32,
11800 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11802 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
11804 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "shl.w", 32,
11805 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11807 /* shl.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
11809 M32C_INSN_SHL32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "shl32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "shl.w", 40,
11810 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11812 /* shl.b${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedQI */
11814 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "shl.b", 16,
11815 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11817 /* shl.b${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedQI */
11819 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "shl.b", 16,
11820 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11822 /* shl.b${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
11824 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "shl.b", 16,
11825 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11827 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11829 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "shl.b", 24,
11830 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11832 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11834 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "shl.b", 32,
11835 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11837 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
11839 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "shl.b", 40,
11840 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11842 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
11844 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "shl.b", 24,
11845 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11847 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
11849 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "shl.b", 32,
11850 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11852 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
11854 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "shl.b", 24,
11855 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11857 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
11859 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "shl.b", 32,
11860 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11862 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
11864 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "shl.b", 32,
11865 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11867 /* shl.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
11869 M32C_INSN_SHL32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "shl32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "shl.b", 40,
11870 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11872 /* shl.w${Q} #${Imm-sh-8-s4},$Dst16RnHI */
11874 M32C_INSN_SHL16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "shl16.w-imm4-Q-16-dst16-Rn-direct-HI", "shl.w", 16,
11875 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11877 /* shl.w${Q} #${Imm-sh-8-s4},$Dst16AnHI */
11879 M32C_INSN_SHL16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "shl16.w-imm4-Q-16-dst16-An-direct-HI", "shl.w", 16,
11880 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11882 /* shl.w${Q} #${Imm-sh-8-s4},[$Dst16An] */
11884 M32C_INSN_SHL16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "shl16.w-imm4-Q-16-dst16-An-indirect-HI", "shl.w", 16,
11885 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11887 /* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
11889 M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "shl.w", 24,
11890 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11892 /* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
11894 M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "shl.w", 32,
11895 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11897 /* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
11899 M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "shl.w", 24,
11900 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11902 /* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
11904 M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "shl.w", 32,
11905 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11907 /* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
11909 M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "shl16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "shl.w", 24,
11910 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11912 /* shl.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
11914 M32C_INSN_SHL16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "shl16.w-imm4-Q-16-dst16-16-16-absolute-HI", "shl.w", 32,
11915 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11917 /* shl.b${Q} #${Imm-sh-8-s4},$Dst16RnQI */
11919 M32C_INSN_SHL16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "shl16.b-imm4-Q-16-dst16-Rn-direct-QI", "shl.b", 16,
11920 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11922 /* shl.b${Q} #${Imm-sh-8-s4},$Dst16AnQI */
11924 M32C_INSN_SHL16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "shl16.b-imm4-Q-16-dst16-An-direct-QI", "shl.b", 16,
11925 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11927 /* shl.b${Q} #${Imm-sh-8-s4},[$Dst16An] */
11929 M32C_INSN_SHL16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "shl16.b-imm4-Q-16-dst16-An-indirect-QI", "shl.b", 16,
11930 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11932 /* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
11934 M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "shl.b", 24,
11935 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11937 /* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
11939 M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "shl.b", 32,
11940 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11942 /* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
11944 M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "shl.b", 24,
11945 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11947 /* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
11949 M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "shl.b", 32,
11950 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11952 /* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
11954 M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "shl16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "shl.b", 24,
11955 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11957 /* shl.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
11959 M32C_INSN_SHL16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "shl16.b-imm4-Q-16-dst16-16-16-absolute-QI", "shl.b", 32,
11960 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
11962 /* shanc.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
11964 M32C_INSN_SHANC32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "shanc32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "shanc.l", 24,
11965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11967 /* shanc.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
11969 M32C_INSN_SHANC32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "shanc32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "shanc.l", 24,
11970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11972 /* shanc.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
11974 M32C_INSN_SHANC32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "shanc32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "shanc.l", 24,
11975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11977 /* shanc.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
11979 M32C_INSN_SHANC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "shanc.l", 32,
11980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11982 /* shanc.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
11984 M32C_INSN_SHANC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "shanc.l", 32,
11985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11987 /* shanc.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
11989 M32C_INSN_SHANC32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "shanc.l", 32,
11990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11992 /* shanc.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
11994 M32C_INSN_SHANC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "shanc.l", 40,
11995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
11997 /* shanc.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
11999 M32C_INSN_SHANC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "shanc.l", 40,
12000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12002 /* shanc.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
12004 M32C_INSN_SHANC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "shanc.l", 40,
12005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12007 /* shanc.l${X} #${Imm-32-QI},${Dsp-16-u16} */
12009 M32C_INSN_SHANC32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "shanc32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "shanc.l", 40,
12010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12012 /* shanc.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
12014 M32C_INSN_SHANC32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "shanc32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "shanc.l", 48,
12015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12017 /* shanc.l${X} #${Imm-40-QI},${Dsp-16-u24} */
12019 M32C_INSN_SHANC32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "shanc32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "shanc.l", 48,
12020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12022 /* sha.l r1h,$Dst32RnUnprefixedSI */
12024 M32C_INSN_SHA32_L_DST_DST32_RN_DIRECT_UNPREFIXED_SI, "sha32.l-dst-dst32-Rn-direct-Unprefixed-SI", "sha.l", 16,
12025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12027 /* sha.l r1h,$Dst32AnUnprefixedSI */
12029 M32C_INSN_SHA32_L_DST_DST32_AN_DIRECT_UNPREFIXED_SI, "sha32.l-dst-dst32-An-direct-Unprefixed-SI", "sha.l", 16,
12030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12032 /* sha.l r1h,[$Dst32AnUnprefixed] */
12034 M32C_INSN_SHA32_L_DST_DST32_AN_INDIRECT_UNPREFIXED_SI, "sha32.l-dst-dst32-An-indirect-Unprefixed-SI", "sha.l", 16,
12035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12037 /* sha.l r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
12039 M32C_INSN_SHA32_L_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-8-An-relative-Unprefixed-SI", "sha.l", 24,
12040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12042 /* sha.l r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
12044 M32C_INSN_SHA32_L_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-16-An-relative-Unprefixed-SI", "sha.l", 32,
12045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12047 /* sha.l r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
12049 M32C_INSN_SHA32_L_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-24-An-relative-Unprefixed-SI", "sha.l", 40,
12050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12052 /* sha.l r1h,${Dsp-16-u8}[sb] */
12054 M32C_INSN_SHA32_L_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-8-SB-relative-Unprefixed-SI", "sha.l", 24,
12055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12057 /* sha.l r1h,${Dsp-16-u16}[sb] */
12059 M32C_INSN_SHA32_L_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-16-SB-relative-Unprefixed-SI", "sha.l", 32,
12060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12062 /* sha.l r1h,${Dsp-16-s8}[fb] */
12064 M32C_INSN_SHA32_L_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-8-FB-relative-Unprefixed-SI", "sha.l", 24,
12065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12067 /* sha.l r1h,${Dsp-16-s16}[fb] */
12069 M32C_INSN_SHA32_L_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-16-FB-relative-Unprefixed-SI", "sha.l", 32,
12070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12072 /* sha.l r1h,${Dsp-16-u16} */
12074 M32C_INSN_SHA32_L_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-16-absolute-Unprefixed-SI", "sha.l", 32,
12075 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12077 /* sha.l r1h,${Dsp-16-u24} */
12079 M32C_INSN_SHA32_L_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sha32.l-dst-dst32-16-24-absolute-Unprefixed-SI", "sha.l", 40,
12080 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12082 /* sha.l${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
12084 M32C_INSN_SHA32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "sha32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "sha.l", 24,
12085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12087 /* sha.l${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
12089 M32C_INSN_SHA32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "sha32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "sha.l", 24,
12090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12092 /* sha.l${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
12094 M32C_INSN_SHA32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "sha32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "sha.l", 24,
12095 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12097 /* sha.l${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
12099 M32C_INSN_SHA32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "sha.l", 32,
12100 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12102 /* sha.l${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
12104 M32C_INSN_SHA32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "sha.l", 32,
12105 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12107 /* sha.l${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
12109 M32C_INSN_SHA32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "sha.l", 32,
12110 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12112 /* sha.l${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
12114 M32C_INSN_SHA32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "sha.l", 40,
12115 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12117 /* sha.l${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
12119 M32C_INSN_SHA32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "sha.l", 40,
12120 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12122 /* sha.l${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
12124 M32C_INSN_SHA32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "sha.l", 40,
12125 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12127 /* sha.l${X} #${Imm-32-QI},${Dsp-16-u16} */
12129 M32C_INSN_SHA32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sha32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "sha.l", 40,
12130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12132 /* sha.l${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
12134 M32C_INSN_SHA32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sha32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "sha.l", 48,
12135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12137 /* sha.l${X} #${Imm-40-QI},${Dsp-16-u24} */
12139 M32C_INSN_SHA32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sha32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "sha.l", 48,
12140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12142 /* sha.w r1h,$Dst32RnUnprefixedHI */
12144 M32C_INSN_SHA32_W_DST_DST32_RN_DIRECT_UNPREFIXED_HI, "sha32.w-dst-dst32-Rn-direct-Unprefixed-HI", "sha.w", 16,
12145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12147 /* sha.w r1h,$Dst32AnUnprefixedHI */
12149 M32C_INSN_SHA32_W_DST_DST32_AN_DIRECT_UNPREFIXED_HI, "sha32.w-dst-dst32-An-direct-Unprefixed-HI", "sha.w", 16,
12150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12152 /* sha.w r1h,[$Dst32AnUnprefixed] */
12154 M32C_INSN_SHA32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_HI, "sha32.w-dst-dst32-An-indirect-Unprefixed-HI", "sha.w", 16,
12155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12157 /* sha.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
12159 M32C_INSN_SHA32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-8-An-relative-Unprefixed-HI", "sha.w", 24,
12160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12162 /* sha.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
12164 M32C_INSN_SHA32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-16-An-relative-Unprefixed-HI", "sha.w", 32,
12165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12167 /* sha.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
12169 M32C_INSN_SHA32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-24-An-relative-Unprefixed-HI", "sha.w", 40,
12170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12172 /* sha.w r1h,${Dsp-16-u8}[sb] */
12174 M32C_INSN_SHA32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-8-SB-relative-Unprefixed-HI", "sha.w", 24,
12175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12177 /* sha.w r1h,${Dsp-16-u16}[sb] */
12179 M32C_INSN_SHA32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-16-SB-relative-Unprefixed-HI", "sha.w", 32,
12180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12182 /* sha.w r1h,${Dsp-16-s8}[fb] */
12184 M32C_INSN_SHA32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-8-FB-relative-Unprefixed-HI", "sha.w", 24,
12185 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12187 /* sha.w r1h,${Dsp-16-s16}[fb] */
12189 M32C_INSN_SHA32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-16-FB-relative-Unprefixed-HI", "sha.w", 32,
12190 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12192 /* sha.w r1h,${Dsp-16-u16} */
12194 M32C_INSN_SHA32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-16-absolute-Unprefixed-HI", "sha.w", 32,
12195 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12197 /* sha.w r1h,${Dsp-16-u24} */
12199 M32C_INSN_SHA32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sha32.w-dst-dst32-16-24-absolute-Unprefixed-HI", "sha.w", 40,
12200 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12202 /* sha.b r1h,$Dst32RnUnprefixedQI */
12204 M32C_INSN_SHA32_B_DST_DST32_RN_DIRECT_UNPREFIXED_QI, "sha32.b-dst-dst32-Rn-direct-Unprefixed-QI", "sha.b", 16,
12205 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12207 /* sha.b r1h,$Dst32AnUnprefixedQI */
12209 M32C_INSN_SHA32_B_DST_DST32_AN_DIRECT_UNPREFIXED_QI, "sha32.b-dst-dst32-An-direct-Unprefixed-QI", "sha.b", 16,
12210 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12212 /* sha.b r1h,[$Dst32AnUnprefixed] */
12214 M32C_INSN_SHA32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_QI, "sha32.b-dst-dst32-An-indirect-Unprefixed-QI", "sha.b", 16,
12215 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12217 /* sha.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
12219 M32C_INSN_SHA32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-8-An-relative-Unprefixed-QI", "sha.b", 24,
12220 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12222 /* sha.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
12224 M32C_INSN_SHA32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-16-An-relative-Unprefixed-QI", "sha.b", 32,
12225 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12227 /* sha.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
12229 M32C_INSN_SHA32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-24-An-relative-Unprefixed-QI", "sha.b", 40,
12230 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12232 /* sha.b r1h,${Dsp-16-u8}[sb] */
12234 M32C_INSN_SHA32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-8-SB-relative-Unprefixed-QI", "sha.b", 24,
12235 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12237 /* sha.b r1h,${Dsp-16-u16}[sb] */
12239 M32C_INSN_SHA32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-16-SB-relative-Unprefixed-QI", "sha.b", 32,
12240 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12242 /* sha.b r1h,${Dsp-16-s8}[fb] */
12244 M32C_INSN_SHA32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-8-FB-relative-Unprefixed-QI", "sha.b", 24,
12245 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12247 /* sha.b r1h,${Dsp-16-s16}[fb] */
12249 M32C_INSN_SHA32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-16-FB-relative-Unprefixed-QI", "sha.b", 32,
12250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12252 /* sha.b r1h,${Dsp-16-u16} */
12254 M32C_INSN_SHA32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-16-absolute-Unprefixed-QI", "sha.b", 32,
12255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12257 /* sha.b r1h,${Dsp-16-u24} */
12259 M32C_INSN_SHA32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sha32.b-dst-dst32-16-24-absolute-Unprefixed-QI", "sha.b", 40,
12260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12262 /* sha.w r1h,$Dst16RnHI */
12264 M32C_INSN_SHA16_W_DST_DST16_RN_DIRECT_HI, "sha16.w-dst-dst16-Rn-direct-HI", "sha.w", 16,
12265 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12267 /* sha.w r1h,$Dst16AnHI */
12269 M32C_INSN_SHA16_W_DST_DST16_AN_DIRECT_HI, "sha16.w-dst-dst16-An-direct-HI", "sha.w", 16,
12270 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12272 /* sha.w r1h,[$Dst16An] */
12274 M32C_INSN_SHA16_W_DST_DST16_AN_INDIRECT_HI, "sha16.w-dst-dst16-An-indirect-HI", "sha.w", 16,
12275 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12277 /* sha.w r1h,${Dsp-16-u8}[$Dst16An] */
12279 M32C_INSN_SHA16_W_DST_DST16_16_8_AN_RELATIVE_HI, "sha16.w-dst-dst16-16-8-An-relative-HI", "sha.w", 24,
12280 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12282 /* sha.w r1h,${Dsp-16-u16}[$Dst16An] */
12284 M32C_INSN_SHA16_W_DST_DST16_16_16_AN_RELATIVE_HI, "sha16.w-dst-dst16-16-16-An-relative-HI", "sha.w", 32,
12285 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12287 /* sha.w r1h,${Dsp-16-u8}[sb] */
12289 M32C_INSN_SHA16_W_DST_DST16_16_8_SB_RELATIVE_HI, "sha16.w-dst-dst16-16-8-SB-relative-HI", "sha.w", 24,
12290 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12292 /* sha.w r1h,${Dsp-16-u16}[sb] */
12294 M32C_INSN_SHA16_W_DST_DST16_16_16_SB_RELATIVE_HI, "sha16.w-dst-dst16-16-16-SB-relative-HI", "sha.w", 32,
12295 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12297 /* sha.w r1h,${Dsp-16-s8}[fb] */
12299 M32C_INSN_SHA16_W_DST_DST16_16_8_FB_RELATIVE_HI, "sha16.w-dst-dst16-16-8-FB-relative-HI", "sha.w", 24,
12300 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12302 /* sha.w r1h,${Dsp-16-u16} */
12304 M32C_INSN_SHA16_W_DST_DST16_16_16_ABSOLUTE_HI, "sha16.w-dst-dst16-16-16-absolute-HI", "sha.w", 32,
12305 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12307 /* sha.b r1h,$Dst16RnQI */
12309 M32C_INSN_SHA16_B_DST_DST16_RN_DIRECT_QI, "sha16.b-dst-dst16-Rn-direct-QI", "sha.b", 16,
12310 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12312 /* sha.b r1h,$Dst16AnQI */
12314 M32C_INSN_SHA16_B_DST_DST16_AN_DIRECT_QI, "sha16.b-dst-dst16-An-direct-QI", "sha.b", 16,
12315 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12317 /* sha.b r1h,[$Dst16An] */
12319 M32C_INSN_SHA16_B_DST_DST16_AN_INDIRECT_QI, "sha16.b-dst-dst16-An-indirect-QI", "sha.b", 16,
12320 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12322 /* sha.b r1h,${Dsp-16-u8}[$Dst16An] */
12324 M32C_INSN_SHA16_B_DST_DST16_16_8_AN_RELATIVE_QI, "sha16.b-dst-dst16-16-8-An-relative-QI", "sha.b", 24,
12325 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12327 /* sha.b r1h,${Dsp-16-u16}[$Dst16An] */
12329 M32C_INSN_SHA16_B_DST_DST16_16_16_AN_RELATIVE_QI, "sha16.b-dst-dst16-16-16-An-relative-QI", "sha.b", 32,
12330 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12332 /* sha.b r1h,${Dsp-16-u8}[sb] */
12334 M32C_INSN_SHA16_B_DST_DST16_16_8_SB_RELATIVE_QI, "sha16.b-dst-dst16-16-8-SB-relative-QI", "sha.b", 24,
12335 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12337 /* sha.b r1h,${Dsp-16-u16}[sb] */
12339 M32C_INSN_SHA16_B_DST_DST16_16_16_SB_RELATIVE_QI, "sha16.b-dst-dst16-16-16-SB-relative-QI", "sha.b", 32,
12340 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12342 /* sha.b r1h,${Dsp-16-s8}[fb] */
12344 M32C_INSN_SHA16_B_DST_DST16_16_8_FB_RELATIVE_QI, "sha16.b-dst-dst16-16-8-FB-relative-QI", "sha.b", 24,
12345 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12347 /* sha.b r1h,${Dsp-16-u16} */
12349 M32C_INSN_SHA16_B_DST_DST16_16_16_ABSOLUTE_QI, "sha16.b-dst-dst16-16-16-absolute-QI", "sha.b", 32,
12350 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12352 /* sha.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */
12354 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "sha.w", 16,
12355 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12357 /* sha.w${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedHI */
12359 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "sha.w", 16,
12360 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12362 /* sha.w${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
12364 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "sha.w", 16,
12365 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12367 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
12369 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "sha.w", 24,
12370 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12372 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
12374 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "sha.w", 32,
12375 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12377 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
12379 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "sha.w", 40,
12380 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12382 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
12384 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "sha.w", 24,
12385 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12387 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
12389 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "sha.w", 32,
12390 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12392 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
12394 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "sha.w", 24,
12395 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12397 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
12399 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "sha.w", 32,
12400 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12402 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
12404 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "sha.w", 32,
12405 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12407 /* sha.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
12409 M32C_INSN_SHA32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sha32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "sha.w", 40,
12410 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12412 /* sha.b${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedQI */
12414 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "sha.b", 16,
12415 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12417 /* sha.b${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedQI */
12419 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "sha.b", 16,
12420 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12422 /* sha.b${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
12424 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "sha.b", 16,
12425 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12427 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
12429 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "sha.b", 24,
12430 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12432 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
12434 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "sha.b", 32,
12435 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12437 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
12439 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "sha.b", 40,
12440 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12442 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
12444 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "sha.b", 24,
12445 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12447 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
12449 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "sha.b", 32,
12450 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12452 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
12454 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "sha.b", 24,
12455 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12457 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
12459 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "sha.b", 32,
12460 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12462 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
12464 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "sha.b", 32,
12465 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12467 /* sha.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
12469 M32C_INSN_SHA32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sha32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "sha.b", 40,
12470 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12472 /* sha.w${Q} #${Imm-sh-8-s4},$Dst16RnHI */
12474 M32C_INSN_SHA16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "sha16.w-imm4-Q-16-dst16-Rn-direct-HI", "sha.w", 16,
12475 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12477 /* sha.w${Q} #${Imm-sh-8-s4},$Dst16AnHI */
12479 M32C_INSN_SHA16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "sha16.w-imm4-Q-16-dst16-An-direct-HI", "sha.w", 16,
12480 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12482 /* sha.w${Q} #${Imm-sh-8-s4},[$Dst16An] */
12484 M32C_INSN_SHA16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "sha16.w-imm4-Q-16-dst16-An-indirect-HI", "sha.w", 16,
12485 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12487 /* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
12489 M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "sha.w", 24,
12490 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12492 /* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
12494 M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "sha.w", 32,
12495 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12497 /* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
12499 M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "sha.w", 24,
12500 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12502 /* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
12504 M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "sha.w", 32,
12505 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12507 /* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
12509 M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "sha16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "sha.w", 24,
12510 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12512 /* sha.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
12514 M32C_INSN_SHA16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "sha16.w-imm4-Q-16-dst16-16-16-absolute-HI", "sha.w", 32,
12515 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12517 /* sha.b${Q} #${Imm-sh-8-s4},$Dst16RnQI */
12519 M32C_INSN_SHA16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "sha16.b-imm4-Q-16-dst16-Rn-direct-QI", "sha.b", 16,
12520 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12522 /* sha.b${Q} #${Imm-sh-8-s4},$Dst16AnQI */
12524 M32C_INSN_SHA16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "sha16.b-imm4-Q-16-dst16-An-direct-QI", "sha.b", 16,
12525 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12527 /* sha.b${Q} #${Imm-sh-8-s4},[$Dst16An] */
12529 M32C_INSN_SHA16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "sha16.b-imm4-Q-16-dst16-An-indirect-QI", "sha.b", 16,
12530 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12532 /* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
12534 M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "sha.b", 24,
12535 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12537 /* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
12539 M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "sha.b", 32,
12540 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12542 /* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
12544 M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "sha.b", 24,
12545 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12547 /* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
12549 M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "sha.b", 32,
12550 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12552 /* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
12554 M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "sha16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "sha.b", 24,
12555 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12557 /* sha.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
12559 M32C_INSN_SHA16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "sha16.b-imm4-Q-16-dst16-16-16-absolute-QI", "sha.b", 32,
12560 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
12562 /* sc${sccond32} $Dst32RnUnprefixedHI */
12564 M32C_INSN_SCCND_DST32_RN_DIRECT_UNPREFIXED_HI, "sccnd-dst32-Rn-direct-Unprefixed-HI", "sc", 16,
12565 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12567 /* sc${sccond32} $Dst32AnUnprefixedHI */
12569 M32C_INSN_SCCND_DST32_AN_DIRECT_UNPREFIXED_HI, "sccnd-dst32-An-direct-Unprefixed-HI", "sc", 16,
12570 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12572 /* sc${sccond32} [$Dst32AnUnprefixed] */
12574 M32C_INSN_SCCND_DST32_AN_INDIRECT_UNPREFIXED_HI, "sccnd-dst32-An-indirect-Unprefixed-HI", "sc", 16,
12575 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12577 /* sc${sccond32} ${Dsp-16-u8}[$Dst32AnUnprefixed] */
12579 M32C_INSN_SCCND_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-8-An-relative-Unprefixed-HI", "sc", 24,
12580 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12582 /* sc${sccond32} ${Dsp-16-u16}[$Dst32AnUnprefixed] */
12584 M32C_INSN_SCCND_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-16-An-relative-Unprefixed-HI", "sc", 32,
12585 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12587 /* sc${sccond32} ${Dsp-16-u24}[$Dst32AnUnprefixed] */
12589 M32C_INSN_SCCND_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-24-An-relative-Unprefixed-HI", "sc", 40,
12590 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12592 /* sc${sccond32} ${Dsp-16-u8}[sb] */
12594 M32C_INSN_SCCND_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-8-SB-relative-Unprefixed-HI", "sc", 24,
12595 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12597 /* sc${sccond32} ${Dsp-16-u16}[sb] */
12599 M32C_INSN_SCCND_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-16-SB-relative-Unprefixed-HI", "sc", 32,
12600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12602 /* sc${sccond32} ${Dsp-16-s8}[fb] */
12604 M32C_INSN_SCCND_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-8-FB-relative-Unprefixed-HI", "sc", 24,
12605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12607 /* sc${sccond32} ${Dsp-16-s16}[fb] */
12609 M32C_INSN_SCCND_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sccnd-dst32-16-16-FB-relative-Unprefixed-HI", "sc", 32,
12610 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12612 /* sc${sccond32} ${Dsp-16-u16} */
12614 M32C_INSN_SCCND_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sccnd-dst32-16-16-absolute-Unprefixed-HI", "sc", 32,
12615 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12617 /* sc${sccond32} ${Dsp-16-u24} */
12619 M32C_INSN_SCCND_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sccnd-dst32-16-24-absolute-Unprefixed-HI", "sc", 40,
12620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12622 /* sbjnz.w #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
12624 M32C_INSN_SBJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "sbjnz.w", 32,
12625 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12627 /* sbjnz.w #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
12629 M32C_INSN_SBJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "sbjnz.w", 32,
12630 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12632 /* sbjnz.w #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
12634 M32C_INSN_SBJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "sbjnz.w", 32,
12635 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12637 /* sbjnz.w #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
12639 M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "sbjnz.w", 40,
12640 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12642 /* sbjnz.w #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
12644 M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "sbjnz.w", 40,
12645 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12647 /* sbjnz.w #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */
12649 M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "sbjnz.w", 40,
12650 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12652 /* sbjnz.w #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */
12654 M32C_INSN_SBJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "sbjnz.w", 40,
12655 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12657 /* sbjnz.w #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
12659 M32C_INSN_SBJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "sbjnz.w", 48,
12660 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12662 /* sbjnz.w #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */
12664 M32C_INSN_SBJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sbjnz32.w-imm4-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "sbjnz.w", 48,
12665 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12667 /* sbjnz.w #${Imm-12-s4},$Dst32RnUnprefixedHI,${Lab-16-8} */
12669 M32C_INSN_SBJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "sbjnz32.w-imm4-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "sbjnz.w", 24,
12670 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12672 /* sbjnz.w #${Imm-12-s4},$Dst32AnUnprefixedHI,${Lab-16-8} */
12674 M32C_INSN_SBJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "sbjnz32.w-imm4-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "sbjnz.w", 24,
12675 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12677 /* sbjnz.w #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */
12679 M32C_INSN_SBJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "sbjnz32.w-imm4-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "sbjnz.w", 24,
12680 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12682 /* sbjnz.b #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
12684 M32C_INSN_SBJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "sbjnz.b", 32,
12685 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12687 /* sbjnz.b #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
12689 M32C_INSN_SBJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "sbjnz.b", 32,
12690 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12692 /* sbjnz.b #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
12694 M32C_INSN_SBJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "sbjnz.b", 32,
12695 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12697 /* sbjnz.b #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
12699 M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "sbjnz.b", 40,
12700 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12702 /* sbjnz.b #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
12704 M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "sbjnz.b", 40,
12705 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12707 /* sbjnz.b #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */
12709 M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "sbjnz.b", 40,
12710 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12712 /* sbjnz.b #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */
12714 M32C_INSN_SBJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "sbjnz.b", 40,
12715 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12717 /* sbjnz.b #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
12719 M32C_INSN_SBJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "sbjnz.b", 48,
12720 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12722 /* sbjnz.b #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */
12724 M32C_INSN_SBJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sbjnz32.b-imm4-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "sbjnz.b", 48,
12725 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12727 /* sbjnz.b #${Imm-12-s4},$Dst32RnUnprefixedQI,${Lab-16-8} */
12729 M32C_INSN_SBJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "sbjnz32.b-imm4-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "sbjnz.b", 24,
12730 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12732 /* sbjnz.b #${Imm-12-s4},$Dst32AnUnprefixedQI,${Lab-16-8} */
12734 M32C_INSN_SBJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "sbjnz32.b-imm4-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "sbjnz.b", 24,
12735 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12737 /* sbjnz.b #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */
12739 M32C_INSN_SBJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "sbjnz32.b-imm4-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "sbjnz.b", 24,
12740 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
12742 /* sbjnz.w #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
12744 M32C_INSN_SBJNZ16_W_IMM4_16_8_DST16_16_8_AN_RELATIVE_HI, "sbjnz16.w-imm4-16-8-dst16-16-8-An-relative-HI", "sbjnz.w", 32,
12745 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12747 /* sbjnz.w #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
12749 M32C_INSN_SBJNZ16_W_IMM4_16_8_DST16_16_8_SB_RELATIVE_HI, "sbjnz16.w-imm4-16-8-dst16-16-8-SB-relative-HI", "sbjnz.w", 32,
12750 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12752 /* sbjnz.w #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
12754 M32C_INSN_SBJNZ16_W_IMM4_16_8_DST16_16_8_FB_RELATIVE_HI, "sbjnz16.w-imm4-16-8-dst16-16-8-FB-relative-HI", "sbjnz.w", 32,
12755 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12757 /* sbjnz.w #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
12759 M32C_INSN_SBJNZ16_W_IMM4_16_16_DST16_16_16_AN_RELATIVE_HI, "sbjnz16.w-imm4-16-16-dst16-16-16-An-relative-HI", "sbjnz.w", 40,
12760 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12762 /* sbjnz.w #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
12764 M32C_INSN_SBJNZ16_W_IMM4_16_16_DST16_16_16_SB_RELATIVE_HI, "sbjnz16.w-imm4-16-16-dst16-16-16-SB-relative-HI", "sbjnz.w", 40,
12765 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12767 /* sbjnz.w #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */
12769 M32C_INSN_SBJNZ16_W_IMM4_16_16_DST16_16_16_ABSOLUTE_HI, "sbjnz16.w-imm4-16-16-dst16-16-16-absolute-HI", "sbjnz.w", 40,
12770 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12772 /* sbjnz.w #${Imm-8-s4},$Dst16RnHI,${Lab-16-8} */
12774 M32C_INSN_SBJNZ16_W_IMM4_BASIC_DST16_RN_DIRECT_HI, "sbjnz16.w-imm4-basic-dst16-Rn-direct-HI", "sbjnz.w", 24,
12775 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12777 /* sbjnz.w #${Imm-8-s4},$Dst16AnHI,${Lab-16-8} */
12779 M32C_INSN_SBJNZ16_W_IMM4_BASIC_DST16_AN_DIRECT_HI, "sbjnz16.w-imm4-basic-dst16-An-direct-HI", "sbjnz.w", 24,
12780 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12782 /* sbjnz.w #${Imm-8-s4},[$Dst16An],${Lab-16-8} */
12784 M32C_INSN_SBJNZ16_W_IMM4_BASIC_DST16_AN_INDIRECT_HI, "sbjnz16.w-imm4-basic-dst16-An-indirect-HI", "sbjnz.w", 24,
12785 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12787 /* sbjnz.b #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
12789 M32C_INSN_SBJNZ16_B_IMM4_16_8_DST16_16_8_AN_RELATIVE_QI, "sbjnz16.b-imm4-16-8-dst16-16-8-An-relative-QI", "sbjnz.b", 32,
12790 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12792 /* sbjnz.b #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
12794 M32C_INSN_SBJNZ16_B_IMM4_16_8_DST16_16_8_SB_RELATIVE_QI, "sbjnz16.b-imm4-16-8-dst16-16-8-SB-relative-QI", "sbjnz.b", 32,
12795 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12797 /* sbjnz.b #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
12799 M32C_INSN_SBJNZ16_B_IMM4_16_8_DST16_16_8_FB_RELATIVE_QI, "sbjnz16.b-imm4-16-8-dst16-16-8-FB-relative-QI", "sbjnz.b", 32,
12800 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12802 /* sbjnz.b #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
12804 M32C_INSN_SBJNZ16_B_IMM4_16_16_DST16_16_16_AN_RELATIVE_QI, "sbjnz16.b-imm4-16-16-dst16-16-16-An-relative-QI", "sbjnz.b", 40,
12805 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12807 /* sbjnz.b #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
12809 M32C_INSN_SBJNZ16_B_IMM4_16_16_DST16_16_16_SB_RELATIVE_QI, "sbjnz16.b-imm4-16-16-dst16-16-16-SB-relative-QI", "sbjnz.b", 40,
12810 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12812 /* sbjnz.b #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */
12814 M32C_INSN_SBJNZ16_B_IMM4_16_16_DST16_16_16_ABSOLUTE_QI, "sbjnz16.b-imm4-16-16-dst16-16-16-absolute-QI", "sbjnz.b", 40,
12815 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12817 /* sbjnz.b #${Imm-8-s4},$Dst16RnQI,${Lab-16-8} */
12819 M32C_INSN_SBJNZ16_B_IMM4_BASIC_DST16_RN_DIRECT_QI, "sbjnz16.b-imm4-basic-dst16-Rn-direct-QI", "sbjnz.b", 24,
12820 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12822 /* sbjnz.b #${Imm-8-s4},$Dst16AnQI,${Lab-16-8} */
12824 M32C_INSN_SBJNZ16_B_IMM4_BASIC_DST16_AN_DIRECT_QI, "sbjnz16.b-imm4-basic-dst16-An-direct-QI", "sbjnz.b", 24,
12825 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12827 /* sbjnz.b #${Imm-8-s4},[$Dst16An],${Lab-16-8} */
12829 M32C_INSN_SBJNZ16_B_IMM4_BASIC_DST16_AN_INDIRECT_QI, "sbjnz16.b-imm4-basic-dst16-An-indirect-QI", "sbjnz.b", 24,
12830 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
12832 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
12834 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 32,
12835 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12837 /* sbb.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
12839 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 32,
12840 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12842 /* sbb.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
12844 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 32,
12845 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12847 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
12849 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 32,
12850 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12852 /* sbb.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
12854 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 32,
12855 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12857 /* sbb.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
12859 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 32,
12860 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12862 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
12864 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 32,
12865 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12867 /* sbb.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
12869 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 32,
12870 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12872 /* sbb.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
12874 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 32,
12875 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12877 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
12879 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "sbb.w", 40,
12880 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12882 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
12884 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "sbb.w", 40,
12885 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12887 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
12889 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "sbb.w", 40,
12890 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12892 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
12894 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "sbb.w", 48,
12895 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12897 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
12899 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "sbb.w", 48,
12900 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12902 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
12904 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "sbb.w", 48,
12905 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12907 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
12909 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "sbb.w", 56,
12910 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12912 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
12914 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "sbb.w", 56,
12915 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12917 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
12919 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "sbb.w", 56,
12920 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12922 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
12924 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "sbb.w", 40,
12925 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12927 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
12929 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "sbb.w", 40,
12930 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12932 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
12934 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "sbb.w", 40,
12935 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12937 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
12939 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "sbb.w", 48,
12940 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12942 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
12944 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "sbb.w", 48,
12945 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12947 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
12949 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "sbb.w", 48,
12950 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12952 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
12954 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "sbb.w", 40,
12955 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12957 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
12959 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "sbb.w", 40,
12960 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12962 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
12964 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "sbb.w", 40,
12965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12967 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
12969 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "sbb.w", 48,
12970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12972 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
12974 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "sbb.w", 48,
12975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12977 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
12979 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "sbb.w", 48,
12980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12982 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
12984 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "sbb.w", 48,
12985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12987 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
12989 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "sbb.w", 48,
12990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12992 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
12994 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "sbb.w", 48,
12995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
12997 /* sbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
12999 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "sbb.w", 56,
13000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13002 /* sbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
13004 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "sbb.w", 56,
13005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13007 /* sbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
13009 M32C_INSN_SBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "sbb.w", 56,
13010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13012 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
13014 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40,
13015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13017 /* sbb.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
13019 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40,
13020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13022 /* sbb.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
13024 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40,
13025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13027 /* sbb.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
13029 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40,
13030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13032 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
13034 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 40,
13035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13037 /* sbb.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
13039 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 40,
13040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13042 /* sbb.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
13044 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 40,
13045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13047 /* sbb.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
13049 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 40,
13050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13052 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
13054 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 40,
13055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13057 /* sbb.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
13059 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 40,
13060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13062 /* sbb.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
13064 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 40,
13065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13067 /* sbb.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
13069 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 40,
13070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13072 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
13074 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "sbb.w", 48,
13075 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13077 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
13079 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "sbb.w", 48,
13080 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13082 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
13084 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "sbb.w", 48,
13085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13087 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
13089 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "sbb.w", 48,
13090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13092 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
13094 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "sbb.w", 56,
13095 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13097 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
13099 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "sbb.w", 56,
13100 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13102 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
13104 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "sbb.w", 56,
13105 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13107 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
13109 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "sbb.w", 56,
13110 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13112 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
13114 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "sbb.w", 64,
13115 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13117 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
13119 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "sbb.w", 64,
13120 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13122 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
13124 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "sbb.w", 64,
13125 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13127 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
13129 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "sbb.w", 64,
13130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13132 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
13134 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "sbb.w", 48,
13135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13137 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
13139 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "sbb.w", 48,
13140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13142 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
13144 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "sbb.w", 48,
13145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13147 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
13149 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "sbb.w", 48,
13150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13152 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
13154 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "sbb.w", 56,
13155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13157 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
13159 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "sbb.w", 56,
13160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13162 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
13164 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "sbb.w", 56,
13165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13167 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
13169 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "sbb.w", 56,
13170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13172 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
13174 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "sbb.w", 48,
13175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13177 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
13179 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "sbb.w", 48,
13180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13182 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
13184 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "sbb.w", 48,
13185 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13187 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
13189 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "sbb.w", 48,
13190 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13192 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
13194 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "sbb.w", 56,
13195 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13197 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
13199 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "sbb.w", 56,
13200 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13202 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
13204 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "sbb.w", 56,
13205 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13207 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
13209 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "sbb.w", 56,
13210 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13212 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
13214 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "sbb.w", 56,
13215 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13217 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
13219 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "sbb.w", 56,
13220 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13222 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
13224 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "sbb.w", 56,
13225 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13227 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
13229 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "sbb.w", 56,
13230 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13232 /* sbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
13234 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "sbb.w", 64,
13235 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13237 /* sbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
13239 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "sbb.w", 64,
13240 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13242 /* sbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
13244 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "sbb.w", 64,
13245 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13247 /* sbb.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
13249 M32C_INSN_SBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "sbb.w", 64,
13250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13252 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
13254 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 48,
13255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13257 /* sbb.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
13259 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 48,
13260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13262 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
13264 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 48,
13265 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13267 /* sbb.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
13269 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 48,
13270 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13272 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
13274 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 48,
13275 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13277 /* sbb.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
13279 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 48,
13280 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13282 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
13284 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "sbb.w", 56,
13285 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13287 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
13289 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "sbb.w", 56,
13290 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13292 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
13294 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "sbb.w", 64,
13295 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13297 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
13299 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "sbb.w", 64,
13300 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13302 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
13304 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "sbb.w", 72,
13305 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13307 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
13309 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "sbb.w", 72,
13310 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13312 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
13314 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "sbb.w", 56,
13315 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13317 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
13319 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "sbb.w", 56,
13320 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13322 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
13324 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "sbb.w", 64,
13325 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13327 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
13329 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "sbb.w", 64,
13330 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13332 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
13334 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "sbb.w", 56,
13335 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13337 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
13339 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "sbb.w", 56,
13340 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13342 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
13344 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "sbb.w", 64,
13345 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13347 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
13349 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "sbb.w", 64,
13350 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13352 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
13354 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "sbb.w", 64,
13355 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13357 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
13359 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "sbb.w", 64,
13360 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13362 /* sbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
13364 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "sbb.w", 72,
13365 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13367 /* sbb.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
13369 M32C_INSN_SBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "sbb.w", 72,
13370 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13372 /* sbb.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
13374 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 24,
13375 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13377 /* sbb.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
13379 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 24,
13380 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13382 /* sbb.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
13384 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "sbb.w", 24,
13385 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13387 /* sbb.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
13389 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 24,
13390 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13392 /* sbb.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
13394 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 24,
13395 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13397 /* sbb.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
13399 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "sbb.w", 24,
13400 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13402 /* sbb.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
13404 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 24,
13405 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13407 /* sbb.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
13409 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 24,
13410 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13412 /* sbb.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
13414 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "sbb.w", 24,
13415 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13417 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
13419 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "sbb.w", 32,
13420 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13422 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
13424 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "sbb.w", 32,
13425 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13427 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
13429 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "sbb.w", 32,
13430 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13432 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
13434 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "sbb.w", 40,
13435 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13437 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
13439 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "sbb.w", 40,
13440 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13442 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
13444 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "sbb.w", 40,
13445 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13447 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
13449 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "sbb.w", 48,
13450 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13452 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
13454 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "sbb.w", 48,
13455 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13457 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
13459 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "sbb.w", 48,
13460 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13462 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
13464 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "sbb.w", 32,
13465 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13467 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
13469 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "sbb.w", 32,
13470 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13472 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
13474 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "sbb.w", 32,
13475 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13477 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
13479 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "sbb.w", 40,
13480 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13482 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
13484 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "sbb.w", 40,
13485 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13487 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
13489 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "sbb.w", 40,
13490 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13492 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
13494 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "sbb.w", 32,
13495 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13497 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
13499 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "sbb.w", 32,
13500 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13502 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
13504 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "sbb.w", 32,
13505 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13507 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
13509 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "sbb.w", 40,
13510 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13512 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
13514 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "sbb.w", 40,
13515 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13517 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
13519 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "sbb.w", 40,
13520 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13522 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
13524 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "sbb.w", 40,
13525 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13527 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
13529 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "sbb.w", 40,
13530 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13532 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
13534 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "sbb.w", 40,
13535 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13537 /* sbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
13539 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "sbb.w", 48,
13540 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13542 /* sbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
13544 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "sbb.w", 48,
13545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13547 /* sbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
13549 M32C_INSN_SBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "sbb.w", 48,
13550 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13552 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
13554 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 32,
13555 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13557 /* sbb.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
13559 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 32,
13560 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13562 /* sbb.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
13564 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 32,
13565 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13567 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
13569 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 32,
13570 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13572 /* sbb.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
13574 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 32,
13575 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13577 /* sbb.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
13579 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 32,
13580 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13582 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
13584 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 32,
13585 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13587 /* sbb.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
13589 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 32,
13590 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13592 /* sbb.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
13594 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 32,
13595 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13597 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
13599 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "sbb.b", 40,
13600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13602 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
13604 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "sbb.b", 40,
13605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13607 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
13609 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "sbb.b", 40,
13610 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13612 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
13614 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "sbb.b", 48,
13615 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13617 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
13619 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "sbb.b", 48,
13620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13622 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
13624 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "sbb.b", 48,
13625 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13627 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
13629 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "sbb.b", 56,
13630 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13632 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
13634 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "sbb.b", 56,
13635 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13637 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
13639 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "sbb.b", 56,
13640 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13642 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
13644 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "sbb.b", 40,
13645 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13647 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
13649 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "sbb.b", 40,
13650 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13652 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
13654 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "sbb.b", 40,
13655 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13657 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
13659 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "sbb.b", 48,
13660 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13662 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
13664 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "sbb.b", 48,
13665 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13667 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
13669 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "sbb.b", 48,
13670 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13672 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
13674 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "sbb.b", 40,
13675 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13677 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
13679 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "sbb.b", 40,
13680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13682 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
13684 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "sbb.b", 40,
13685 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13687 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
13689 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "sbb.b", 48,
13690 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13692 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
13694 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "sbb.b", 48,
13695 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13697 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
13699 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "sbb.b", 48,
13700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13702 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
13704 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "sbb.b", 48,
13705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13707 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
13709 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "sbb.b", 48,
13710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13712 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
13714 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "sbb.b", 48,
13715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13717 /* sbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
13719 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "sbb.b", 56,
13720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13722 /* sbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
13724 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "sbb.b", 56,
13725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13727 /* sbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
13729 M32C_INSN_SBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "sbb.b", 56,
13730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13732 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
13734 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 40,
13735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13737 /* sbb.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
13739 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 40,
13740 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13742 /* sbb.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
13744 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 40,
13745 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13747 /* sbb.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
13749 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 40,
13750 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13752 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
13754 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 40,
13755 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13757 /* sbb.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
13759 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 40,
13760 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13762 /* sbb.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
13764 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 40,
13765 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13767 /* sbb.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
13769 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 40,
13770 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13772 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
13774 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 40,
13775 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13777 /* sbb.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
13779 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 40,
13780 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13782 /* sbb.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
13784 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 40,
13785 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13787 /* sbb.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
13789 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 40,
13790 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13792 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
13794 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "sbb.b", 48,
13795 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13797 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
13799 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "sbb.b", 48,
13800 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13802 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
13804 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "sbb.b", 48,
13805 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13807 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
13809 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "sbb.b", 48,
13810 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13812 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
13814 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "sbb.b", 56,
13815 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13817 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
13819 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "sbb.b", 56,
13820 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13822 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
13824 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "sbb.b", 56,
13825 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13827 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
13829 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "sbb.b", 56,
13830 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13832 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
13834 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "sbb.b", 64,
13835 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13837 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
13839 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "sbb.b", 64,
13840 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13842 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
13844 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "sbb.b", 64,
13845 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13847 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
13849 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "sbb.b", 64,
13850 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13852 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
13854 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "sbb.b", 48,
13855 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13857 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
13859 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "sbb.b", 48,
13860 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13862 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
13864 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "sbb.b", 48,
13865 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13867 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
13869 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "sbb.b", 48,
13870 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13872 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
13874 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "sbb.b", 56,
13875 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13877 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
13879 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "sbb.b", 56,
13880 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13882 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
13884 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "sbb.b", 56,
13885 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13887 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
13889 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "sbb.b", 56,
13890 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13892 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
13894 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "sbb.b", 48,
13895 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13897 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
13899 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "sbb.b", 48,
13900 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13902 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
13904 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "sbb.b", 48,
13905 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13907 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
13909 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "sbb.b", 48,
13910 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13912 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
13914 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "sbb.b", 56,
13915 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13917 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
13919 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "sbb.b", 56,
13920 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13922 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
13924 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "sbb.b", 56,
13925 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13927 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
13929 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "sbb.b", 56,
13930 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13932 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
13934 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "sbb.b", 56,
13935 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13937 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
13939 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "sbb.b", 56,
13940 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13942 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
13944 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "sbb.b", 56,
13945 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13947 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
13949 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "sbb.b", 56,
13950 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13952 /* sbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
13954 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "sbb.b", 64,
13955 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13957 /* sbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
13959 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "sbb.b", 64,
13960 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13962 /* sbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
13964 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "sbb.b", 64,
13965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13967 /* sbb.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
13969 M32C_INSN_SBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "sbb.b", 64,
13970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13972 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
13974 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 48,
13975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13977 /* sbb.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
13979 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 48,
13980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13982 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
13984 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 48,
13985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13987 /* sbb.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
13989 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 48,
13990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13992 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
13994 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 48,
13995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
13997 /* sbb.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
13999 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 48,
14000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14002 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
14004 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "sbb.b", 56,
14005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14007 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
14009 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "sbb.b", 56,
14010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14012 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
14014 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "sbb.b", 64,
14015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14017 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
14019 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "sbb.b", 64,
14020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14022 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
14024 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "sbb.b", 72,
14025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14027 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
14029 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "sbb.b", 72,
14030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14032 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
14034 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "sbb.b", 56,
14035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14037 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
14039 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "sbb.b", 56,
14040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14042 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
14044 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "sbb.b", 64,
14045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14047 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
14049 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "sbb.b", 64,
14050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14052 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
14054 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "sbb.b", 56,
14055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14057 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
14059 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "sbb.b", 56,
14060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14062 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
14064 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "sbb.b", 64,
14065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14067 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
14069 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "sbb.b", 64,
14070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14072 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
14074 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "sbb.b", 64,
14075 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14077 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
14079 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "sbb.b", 64,
14080 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14082 /* sbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
14084 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "sbb.b", 72,
14085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14087 /* sbb.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
14089 M32C_INSN_SBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "sbb.b", 72,
14090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14092 /* sbb.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
14094 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 24,
14095 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14097 /* sbb.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
14099 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 24,
14100 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14102 /* sbb.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
14104 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "sbb.b", 24,
14105 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14107 /* sbb.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
14109 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 24,
14110 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14112 /* sbb.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
14114 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 24,
14115 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14117 /* sbb.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
14119 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "sbb.b", 24,
14120 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14122 /* sbb.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
14124 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 24,
14125 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14127 /* sbb.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
14129 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 24,
14130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14132 /* sbb.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
14134 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "sbb.b", 24,
14135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14137 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
14139 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "sbb.b", 32,
14140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14142 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
14144 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "sbb.b", 32,
14145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14147 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
14149 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "sbb.b", 32,
14150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14152 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
14154 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "sbb.b", 40,
14155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14157 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
14159 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "sbb.b", 40,
14160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14162 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
14164 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "sbb.b", 40,
14165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14167 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
14169 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "sbb.b", 48,
14170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14172 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
14174 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "sbb.b", 48,
14175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14177 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
14179 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "sbb.b", 48,
14180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14182 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
14184 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "sbb.b", 32,
14185 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14187 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
14189 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "sbb.b", 32,
14190 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14192 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
14194 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "sbb.b", 32,
14195 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14197 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
14199 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "sbb.b", 40,
14200 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14202 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
14204 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "sbb.b", 40,
14205 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14207 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
14209 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "sbb.b", 40,
14210 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14212 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
14214 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "sbb.b", 32,
14215 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14217 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
14219 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "sbb.b", 32,
14220 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14222 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
14224 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "sbb.b", 32,
14225 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14227 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
14229 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "sbb.b", 40,
14230 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14232 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
14234 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "sbb.b", 40,
14235 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14237 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
14239 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "sbb.b", 40,
14240 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14242 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
14244 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "sbb.b", 40,
14245 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14247 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
14249 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "sbb.b", 40,
14250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14252 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
14254 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "sbb.b", 40,
14255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14257 /* sbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
14259 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "sbb.b", 48,
14260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14262 /* sbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
14264 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "sbb.b", 48,
14265 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14267 /* sbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
14269 M32C_INSN_SBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "sbb.b", 48,
14270 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
14272 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
14274 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "sbb.w", 24,
14275 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14277 /* sbb.w${X} ${Dsp-16-u8}[sb],$Dst16RnHI */
14279 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "sbb.w", 24,
14280 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14282 /* sbb.w${X} ${Dsp-16-s8}[fb],$Dst16RnHI */
14284 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "sbb.w", 24,
14285 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14287 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
14289 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "sbb.w", 24,
14290 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14292 /* sbb.w${X} ${Dsp-16-u8}[sb],$Dst16AnHI */
14294 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "sbb.w", 24,
14295 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14297 /* sbb.w${X} ${Dsp-16-s8}[fb],$Dst16AnHI */
14299 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "sbb.w", 24,
14300 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14302 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
14304 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "sbb.w", 24,
14305 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14307 /* sbb.w${X} ${Dsp-16-u8}[sb],[$Dst16An] */
14309 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "sbb.w", 24,
14310 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14312 /* sbb.w${X} ${Dsp-16-s8}[fb],[$Dst16An] */
14314 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "sbb.w", 24,
14315 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14317 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
14319 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "sbb.w", 32,
14320 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14322 /* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
14324 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "sbb.w", 32,
14325 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14327 /* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
14329 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "sbb.w", 32,
14330 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14332 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
14334 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "sbb.w", 40,
14335 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14337 /* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
14339 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "sbb.w", 40,
14340 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14342 /* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
14344 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "sbb.w", 40,
14345 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14347 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
14349 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "sbb.w", 32,
14350 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14352 /* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
14354 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "sbb.w", 32,
14355 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14357 /* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
14359 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "sbb.w", 32,
14360 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14362 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
14364 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "sbb.w", 40,
14365 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14367 /* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
14369 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "sbb.w", 40,
14370 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14372 /* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
14374 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "sbb.w", 40,
14375 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14377 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
14379 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "sbb.w", 32,
14380 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14382 /* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
14384 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "sbb.w", 32,
14385 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14387 /* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
14389 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "sbb.w", 32,
14390 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14392 /* sbb.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
14394 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sbb16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "sbb.w", 40,
14395 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14397 /* sbb.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
14399 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sbb16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "sbb.w", 40,
14400 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14402 /* sbb.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
14404 M32C_INSN_SBB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sbb16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "sbb.w", 40,
14405 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14407 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
14409 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "sbb.w", 32,
14410 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14412 /* sbb.w${X} ${Dsp-16-u16}[sb],$Dst16RnHI */
14414 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "sbb.w", 32,
14415 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14417 /* sbb.w${X} ${Dsp-16-u16},$Dst16RnHI */
14419 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "sbb.w", 32,
14420 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14422 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
14424 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "sbb.w", 32,
14425 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14427 /* sbb.w${X} ${Dsp-16-u16}[sb],$Dst16AnHI */
14429 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "sbb.w", 32,
14430 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14432 /* sbb.w${X} ${Dsp-16-u16},$Dst16AnHI */
14434 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "sbb.w", 32,
14435 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14437 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
14439 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "sbb.w", 32,
14440 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14442 /* sbb.w${X} ${Dsp-16-u16}[sb],[$Dst16An] */
14444 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "sbb.w", 32,
14445 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14447 /* sbb.w${X} ${Dsp-16-u16},[$Dst16An] */
14449 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "sbb.w", 32,
14450 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14452 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
14454 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "sbb.w", 40,
14455 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14457 /* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
14459 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "sbb.w", 40,
14460 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14462 /* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
14464 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "sbb.w", 40,
14465 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14467 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
14469 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "sbb.w", 48,
14470 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14472 /* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
14474 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "sbb.w", 48,
14475 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14477 /* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
14479 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "sbb.w", 48,
14480 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14482 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
14484 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "sbb.w", 40,
14485 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14487 /* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
14489 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "sbb.w", 40,
14490 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14492 /* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
14494 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "sbb.w", 40,
14495 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14497 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
14499 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "sbb.w", 48,
14500 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14502 /* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
14504 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "sbb.w", 48,
14505 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14507 /* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
14509 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "sbb.w", 48,
14510 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14512 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
14514 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "sbb.w", 40,
14515 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14517 /* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
14519 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "sbb.w", 40,
14520 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14522 /* sbb.w${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
14524 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "sbb.w", 40,
14525 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14527 /* sbb.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
14529 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "sbb16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "sbb.w", 48,
14530 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14532 /* sbb.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
14534 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "sbb16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "sbb.w", 48,
14535 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14537 /* sbb.w${X} ${Dsp-16-u16},${Dsp-32-u16} */
14539 M32C_INSN_SBB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "sbb16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "sbb.w", 48,
14540 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14542 /* sbb.w${X} $Src16RnHI,$Dst16RnHI */
14544 M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "sbb.w", 16,
14545 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14547 /* sbb.w${X} $Src16AnHI,$Dst16RnHI */
14549 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "sbb.w", 16,
14550 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14552 /* sbb.w${X} [$Src16An],$Dst16RnHI */
14554 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "sbb.w", 16,
14555 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14557 /* sbb.w${X} $Src16RnHI,$Dst16AnHI */
14559 M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "sbb.w", 16,
14560 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14562 /* sbb.w${X} $Src16AnHI,$Dst16AnHI */
14564 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "sbb.w", 16,
14565 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14567 /* sbb.w${X} [$Src16An],$Dst16AnHI */
14569 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "sbb.w", 16,
14570 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14572 /* sbb.w${X} $Src16RnHI,[$Dst16An] */
14574 M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "sbb.w", 16,
14575 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14577 /* sbb.w${X} $Src16AnHI,[$Dst16An] */
14579 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "sbb.w", 16,
14580 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14582 /* sbb.w${X} [$Src16An],[$Dst16An] */
14584 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "sbb.w", 16,
14585 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14587 /* sbb.w${X} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
14589 M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "sbb.w", 24,
14590 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14592 /* sbb.w${X} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
14594 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "sbb.w", 24,
14595 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14597 /* sbb.w${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
14599 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "sbb.w", 24,
14600 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14602 /* sbb.w${X} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
14604 M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "sbb.w", 32,
14605 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14607 /* sbb.w${X} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
14609 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "sbb.w", 32,
14610 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14612 /* sbb.w${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
14614 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "sbb.w", 32,
14615 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14617 /* sbb.w${X} $Src16RnHI,${Dsp-16-u8}[sb] */
14619 M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "sbb.w", 24,
14620 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14622 /* sbb.w${X} $Src16AnHI,${Dsp-16-u8}[sb] */
14624 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "sbb.w", 24,
14625 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14627 /* sbb.w${X} [$Src16An],${Dsp-16-u8}[sb] */
14629 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "sbb.w", 24,
14630 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14632 /* sbb.w${X} $Src16RnHI,${Dsp-16-u16}[sb] */
14634 M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "sbb.w", 32,
14635 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14637 /* sbb.w${X} $Src16AnHI,${Dsp-16-u16}[sb] */
14639 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "sbb.w", 32,
14640 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14642 /* sbb.w${X} [$Src16An],${Dsp-16-u16}[sb] */
14644 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "sbb.w", 32,
14645 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14647 /* sbb.w${X} $Src16RnHI,${Dsp-16-s8}[fb] */
14649 M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "sbb.w", 24,
14650 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14652 /* sbb.w${X} $Src16AnHI,${Dsp-16-s8}[fb] */
14654 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "sbb.w", 24,
14655 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14657 /* sbb.w${X} [$Src16An],${Dsp-16-s8}[fb] */
14659 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "sbb.w", 24,
14660 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14662 /* sbb.w${X} $Src16RnHI,${Dsp-16-u16} */
14664 M32C_INSN_SBB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sbb16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "sbb.w", 32,
14665 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14667 /* sbb.w${X} $Src16AnHI,${Dsp-16-u16} */
14669 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sbb16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "sbb.w", 32,
14670 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14672 /* sbb.w${X} [$Src16An],${Dsp-16-u16} */
14674 M32C_INSN_SBB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sbb16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "sbb.w", 32,
14675 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14677 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
14679 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "sbb.b", 24,
14680 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14682 /* sbb.b${X} ${Dsp-16-u8}[sb],$Dst16RnQI */
14684 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "sbb.b", 24,
14685 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14687 /* sbb.b${X} ${Dsp-16-s8}[fb],$Dst16RnQI */
14689 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "sbb.b", 24,
14690 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14692 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
14694 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "sbb.b", 24,
14695 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14697 /* sbb.b${X} ${Dsp-16-u8}[sb],$Dst16AnQI */
14699 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "sbb.b", 24,
14700 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14702 /* sbb.b${X} ${Dsp-16-s8}[fb],$Dst16AnQI */
14704 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "sbb.b", 24,
14705 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14707 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
14709 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "sbb.b", 24,
14710 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14712 /* sbb.b${X} ${Dsp-16-u8}[sb],[$Dst16An] */
14714 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "sbb.b", 24,
14715 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14717 /* sbb.b${X} ${Dsp-16-s8}[fb],[$Dst16An] */
14719 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "sbb.b", 24,
14720 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14722 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
14724 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "sbb.b", 32,
14725 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14727 /* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
14729 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "sbb.b", 32,
14730 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14732 /* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
14734 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "sbb.b", 32,
14735 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14737 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
14739 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "sbb.b", 40,
14740 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14742 /* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
14744 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "sbb.b", 40,
14745 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14747 /* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
14749 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "sbb.b", 40,
14750 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14752 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
14754 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "sbb.b", 32,
14755 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14757 /* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
14759 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "sbb.b", 32,
14760 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14762 /* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
14764 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "sbb.b", 32,
14765 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14767 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
14769 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "sbb.b", 40,
14770 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14772 /* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
14774 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "sbb.b", 40,
14775 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14777 /* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
14779 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "sbb.b", 40,
14780 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14782 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
14784 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "sbb.b", 32,
14785 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14787 /* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
14789 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "sbb.b", 32,
14790 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14792 /* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
14794 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "sbb.b", 32,
14795 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14797 /* sbb.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
14799 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sbb16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "sbb.b", 40,
14800 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14802 /* sbb.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
14804 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sbb16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "sbb.b", 40,
14805 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14807 /* sbb.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
14809 M32C_INSN_SBB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sbb16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "sbb.b", 40,
14810 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14812 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
14814 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "sbb.b", 32,
14815 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14817 /* sbb.b${X} ${Dsp-16-u16}[sb],$Dst16RnQI */
14819 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "sbb.b", 32,
14820 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14822 /* sbb.b${X} ${Dsp-16-u16},$Dst16RnQI */
14824 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "sbb.b", 32,
14825 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14827 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
14829 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "sbb.b", 32,
14830 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14832 /* sbb.b${X} ${Dsp-16-u16}[sb],$Dst16AnQI */
14834 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "sbb.b", 32,
14835 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14837 /* sbb.b${X} ${Dsp-16-u16},$Dst16AnQI */
14839 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "sbb.b", 32,
14840 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14842 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
14844 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "sbb.b", 32,
14845 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14847 /* sbb.b${X} ${Dsp-16-u16}[sb],[$Dst16An] */
14849 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "sbb.b", 32,
14850 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14852 /* sbb.b${X} ${Dsp-16-u16},[$Dst16An] */
14854 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "sbb.b", 32,
14855 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14857 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
14859 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "sbb.b", 40,
14860 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14862 /* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
14864 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "sbb.b", 40,
14865 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14867 /* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
14869 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "sbb.b", 40,
14870 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14872 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
14874 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "sbb.b", 48,
14875 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14877 /* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
14879 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "sbb.b", 48,
14880 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14882 /* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
14884 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "sbb.b", 48,
14885 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14887 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
14889 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "sbb.b", 40,
14890 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14892 /* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
14894 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "sbb.b", 40,
14895 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14897 /* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
14899 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "sbb.b", 40,
14900 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14902 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
14904 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "sbb.b", 48,
14905 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14907 /* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
14909 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "sbb.b", 48,
14910 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14912 /* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
14914 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "sbb.b", 48,
14915 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14917 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
14919 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "sbb.b", 40,
14920 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14922 /* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
14924 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "sbb.b", 40,
14925 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14927 /* sbb.b${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
14929 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "sbb.b", 40,
14930 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14932 /* sbb.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
14934 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "sbb16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "sbb.b", 48,
14935 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14937 /* sbb.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
14939 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "sbb16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "sbb.b", 48,
14940 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14942 /* sbb.b${X} ${Dsp-16-u16},${Dsp-32-u16} */
14944 M32C_INSN_SBB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "sbb16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "sbb.b", 48,
14945 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14947 /* sbb.b${X} $Src16RnQI,$Dst16RnQI */
14949 M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "sbb.b", 16,
14950 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14952 /* sbb.b${X} $Src16AnQI,$Dst16RnQI */
14954 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "sbb.b", 16,
14955 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14957 /* sbb.b${X} [$Src16An],$Dst16RnQI */
14959 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "sbb.b", 16,
14960 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14962 /* sbb.b${X} $Src16RnQI,$Dst16AnQI */
14964 M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "sbb.b", 16,
14965 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14967 /* sbb.b${X} $Src16AnQI,$Dst16AnQI */
14969 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "sbb.b", 16,
14970 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14972 /* sbb.b${X} [$Src16An],$Dst16AnQI */
14974 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "sbb.b", 16,
14975 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14977 /* sbb.b${X} $Src16RnQI,[$Dst16An] */
14979 M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "sbb.b", 16,
14980 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14982 /* sbb.b${X} $Src16AnQI,[$Dst16An] */
14984 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "sbb.b", 16,
14985 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14987 /* sbb.b${X} [$Src16An],[$Dst16An] */
14989 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "sbb.b", 16,
14990 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14992 /* sbb.b${X} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
14994 M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "sbb.b", 24,
14995 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
14997 /* sbb.b${X} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
14999 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "sbb.b", 24,
15000 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15002 /* sbb.b${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
15004 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "sbb.b", 24,
15005 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15007 /* sbb.b${X} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
15009 M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "sbb.b", 32,
15010 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15012 /* sbb.b${X} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
15014 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "sbb.b", 32,
15015 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15017 /* sbb.b${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
15019 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "sbb.b", 32,
15020 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15022 /* sbb.b${X} $Src16RnQI,${Dsp-16-u8}[sb] */
15024 M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "sbb.b", 24,
15025 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15027 /* sbb.b${X} $Src16AnQI,${Dsp-16-u8}[sb] */
15029 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "sbb.b", 24,
15030 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15032 /* sbb.b${X} [$Src16An],${Dsp-16-u8}[sb] */
15034 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "sbb.b", 24,
15035 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15037 /* sbb.b${X} $Src16RnQI,${Dsp-16-u16}[sb] */
15039 M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "sbb.b", 32,
15040 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15042 /* sbb.b${X} $Src16AnQI,${Dsp-16-u16}[sb] */
15044 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "sbb.b", 32,
15045 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15047 /* sbb.b${X} [$Src16An],${Dsp-16-u16}[sb] */
15049 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "sbb.b", 32,
15050 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15052 /* sbb.b${X} $Src16RnQI,${Dsp-16-s8}[fb] */
15054 M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "sbb.b", 24,
15055 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15057 /* sbb.b${X} $Src16AnQI,${Dsp-16-s8}[fb] */
15059 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "sbb.b", 24,
15060 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15062 /* sbb.b${X} [$Src16An],${Dsp-16-s8}[fb] */
15064 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "sbb.b", 24,
15065 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15067 /* sbb.b${X} $Src16RnQI,${Dsp-16-u16} */
15069 M32C_INSN_SBB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sbb16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "sbb.b", 32,
15070 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15072 /* sbb.b${X} $Src16AnQI,${Dsp-16-u16} */
15074 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sbb16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "sbb.b", 32,
15075 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15077 /* sbb.b${X} [$Src16An],${Dsp-16-u16} */
15079 M32C_INSN_SBB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sbb16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "sbb.b", 32,
15080 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15082 /* sbb.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
15084 M32C_INSN_SBB32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "sbb32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "sbb.w", 40,
15085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15087 /* sbb.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
15089 M32C_INSN_SBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "sbb32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "sbb.w", 40,
15090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15092 /* sbb.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
15094 M32C_INSN_SBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "sbb32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "sbb.w", 40,
15095 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15097 /* sbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
15099 M32C_INSN_SBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "sbb.w", 48,
15100 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15102 /* sbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
15104 M32C_INSN_SBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "sbb.w", 48,
15105 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15107 /* sbb.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
15109 M32C_INSN_SBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "sbb.w", 48,
15110 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15112 /* sbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
15114 M32C_INSN_SBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "sbb.w", 56,
15115 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15117 /* sbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
15119 M32C_INSN_SBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "sbb.w", 56,
15120 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15122 /* sbb.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
15124 M32C_INSN_SBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "sbb.w", 56,
15125 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15127 /* sbb.w${X} #${Imm-40-HI},${Dsp-24-u16} */
15129 M32C_INSN_SBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "sbb32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "sbb.w", 56,
15130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15132 /* sbb.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
15134 M32C_INSN_SBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "sbb32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "sbb.w", 64,
15135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15137 /* sbb.w${X} #${Imm-48-HI},${Dsp-24-u24} */
15139 M32C_INSN_SBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "sbb32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "sbb.w", 64,
15140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15142 /* sbb.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
15144 M32C_INSN_SBB32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "sbb32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "sbb.b", 32,
15145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15147 /* sbb.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
15149 M32C_INSN_SBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "sbb32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "sbb.b", 32,
15150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15152 /* sbb.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
15154 M32C_INSN_SBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "sbb32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "sbb.b", 32,
15155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15157 /* sbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
15159 M32C_INSN_SBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "sbb.b", 40,
15160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15162 /* sbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
15164 M32C_INSN_SBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "sbb.b", 40,
15165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15167 /* sbb.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
15169 M32C_INSN_SBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "sbb.b", 40,
15170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15172 /* sbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
15174 M32C_INSN_SBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "sbb.b", 48,
15175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15177 /* sbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
15179 M32C_INSN_SBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "sbb.b", 48,
15180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15182 /* sbb.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
15184 M32C_INSN_SBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "sbb.b", 48,
15185 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15187 /* sbb.b${X} #${Imm-40-QI},${Dsp-24-u16} */
15189 M32C_INSN_SBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "sbb32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "sbb.b", 48,
15190 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15192 /* sbb.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
15194 M32C_INSN_SBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "sbb32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "sbb.b", 56,
15195 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15197 /* sbb.b${X} #${Imm-48-QI},${Dsp-24-u24} */
15199 M32C_INSN_SBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "sbb32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "sbb.b", 56,
15200 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15202 /* sbb.w${X} #${Imm-16-HI},$Dst16RnHI */
15204 M32C_INSN_SBB16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "sbb16.w-imm-G-basic-dst16-Rn-direct-HI", "sbb.w", 32,
15205 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15207 /* sbb.w${X} #${Imm-16-HI},$Dst16AnHI */
15209 M32C_INSN_SBB16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "sbb16.w-imm-G-basic-dst16-An-direct-HI", "sbb.w", 32,
15210 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15212 /* sbb.w${X} #${Imm-16-HI},[$Dst16An] */
15214 M32C_INSN_SBB16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "sbb16.w-imm-G-basic-dst16-An-indirect-HI", "sbb.w", 32,
15215 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15217 /* sbb.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
15219 M32C_INSN_SBB16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "sbb16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "sbb.w", 40,
15220 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15222 /* sbb.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
15224 M32C_INSN_SBB16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "sbb16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "sbb.w", 40,
15225 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15227 /* sbb.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
15229 M32C_INSN_SBB16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "sbb16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "sbb.w", 40,
15230 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15232 /* sbb.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
15234 M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "sbb16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "sbb.w", 48,
15235 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15237 /* sbb.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
15239 M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "sbb16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "sbb.w", 48,
15240 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15242 /* sbb.w${X} #${Imm-32-HI},${Dsp-16-u16} */
15244 M32C_INSN_SBB16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "sbb16.w-imm-G-16-16-dst16-16-16-absolute-HI", "sbb.w", 48,
15245 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15247 /* sbb.b${X} #${Imm-16-QI},$Dst16RnQI */
15249 M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "sbb16.b-imm-G-basic-dst16-Rn-direct-QI", "sbb.b", 24,
15250 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15252 /* sbb.b${X} #${Imm-16-QI},$Dst16AnQI */
15254 M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "sbb16.b-imm-G-basic-dst16-An-direct-QI", "sbb.b", 24,
15255 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15257 /* sbb.b${X} #${Imm-16-QI},[$Dst16An] */
15259 M32C_INSN_SBB16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "sbb16.b-imm-G-basic-dst16-An-indirect-QI", "sbb.b", 24,
15260 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15262 /* sbb.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
15264 M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "sbb16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "sbb.b", 32,
15265 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15267 /* sbb.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
15269 M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "sbb16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "sbb.b", 32,
15270 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15272 /* sbb.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
15274 M32C_INSN_SBB16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "sbb16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "sbb.b", 32,
15275 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15277 /* sbb.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
15279 M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "sbb16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "sbb.b", 40,
15280 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15282 /* sbb.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
15284 M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "sbb16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "sbb.b", 40,
15285 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15287 /* sbb.b${X} #${Imm-32-QI},${Dsp-16-u16} */
15289 M32C_INSN_SBB16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "sbb16.b-imm-G-16-16-dst16-16-16-absolute-QI", "sbb.b", 40,
15290 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15292 /* rot.w r1h,$Dst32RnUnprefixedSI */
15294 M32C_INSN_ROT32_W_DST_DST32_RN_DIRECT_UNPREFIXED_SI, "rot32.w-dst-dst32-Rn-direct-Unprefixed-SI", "rot.w", 16,
15295 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15297 /* rot.w r1h,$Dst32AnUnprefixedSI */
15299 M32C_INSN_ROT32_W_DST_DST32_AN_DIRECT_UNPREFIXED_SI, "rot32.w-dst-dst32-An-direct-Unprefixed-SI", "rot.w", 16,
15300 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15302 /* rot.w r1h,[$Dst32AnUnprefixed] */
15304 M32C_INSN_ROT32_W_DST_DST32_AN_INDIRECT_UNPREFIXED_SI, "rot32.w-dst-dst32-An-indirect-Unprefixed-SI", "rot.w", 16,
15305 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15307 /* rot.w r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
15309 M32C_INSN_ROT32_W_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "rot32.w-dst-dst32-16-8-An-relative-Unprefixed-SI", "rot.w", 24,
15310 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15312 /* rot.w r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
15314 M32C_INSN_ROT32_W_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "rot32.w-dst-dst32-16-16-An-relative-Unprefixed-SI", "rot.w", 32,
15315 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15317 /* rot.w r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
15319 M32C_INSN_ROT32_W_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "rot32.w-dst-dst32-16-24-An-relative-Unprefixed-SI", "rot.w", 40,
15320 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15322 /* rot.w r1h,${Dsp-16-u8}[sb] */
15324 M32C_INSN_ROT32_W_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "rot32.w-dst-dst32-16-8-SB-relative-Unprefixed-SI", "rot.w", 24,
15325 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15327 /* rot.w r1h,${Dsp-16-u16}[sb] */
15329 M32C_INSN_ROT32_W_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "rot32.w-dst-dst32-16-16-SB-relative-Unprefixed-SI", "rot.w", 32,
15330 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15332 /* rot.w r1h,${Dsp-16-s8}[fb] */
15334 M32C_INSN_ROT32_W_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "rot32.w-dst-dst32-16-8-FB-relative-Unprefixed-SI", "rot.w", 24,
15335 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15337 /* rot.w r1h,${Dsp-16-s16}[fb] */
15339 M32C_INSN_ROT32_W_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "rot32.w-dst-dst32-16-16-FB-relative-Unprefixed-SI", "rot.w", 32,
15340 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15342 /* rot.w r1h,${Dsp-16-u16} */
15344 M32C_INSN_ROT32_W_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "rot32.w-dst-dst32-16-16-absolute-Unprefixed-SI", "rot.w", 32,
15345 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15347 /* rot.w r1h,${Dsp-16-u24} */
15349 M32C_INSN_ROT32_W_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "rot32.w-dst-dst32-16-24-absolute-Unprefixed-SI", "rot.w", 40,
15350 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15352 /* rot.b r1h,$Dst32RnUnprefixedSI */
15354 M32C_INSN_ROT32_B_DST_DST32_RN_DIRECT_UNPREFIXED_SI, "rot32.b-dst-dst32-Rn-direct-Unprefixed-SI", "rot.b", 16,
15355 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15357 /* rot.b r1h,$Dst32AnUnprefixedSI */
15359 M32C_INSN_ROT32_B_DST_DST32_AN_DIRECT_UNPREFIXED_SI, "rot32.b-dst-dst32-An-direct-Unprefixed-SI", "rot.b", 16,
15360 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15362 /* rot.b r1h,[$Dst32AnUnprefixed] */
15364 M32C_INSN_ROT32_B_DST_DST32_AN_INDIRECT_UNPREFIXED_SI, "rot32.b-dst-dst32-An-indirect-Unprefixed-SI", "rot.b", 16,
15365 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15367 /* rot.b r1h,${Dsp-16-u8}[$Dst32AnUnprefixed] */
15369 M32C_INSN_ROT32_B_DST_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "rot32.b-dst-dst32-16-8-An-relative-Unprefixed-SI", "rot.b", 24,
15370 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15372 /* rot.b r1h,${Dsp-16-u16}[$Dst32AnUnprefixed] */
15374 M32C_INSN_ROT32_B_DST_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "rot32.b-dst-dst32-16-16-An-relative-Unprefixed-SI", "rot.b", 32,
15375 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15377 /* rot.b r1h,${Dsp-16-u24}[$Dst32AnUnprefixed] */
15379 M32C_INSN_ROT32_B_DST_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "rot32.b-dst-dst32-16-24-An-relative-Unprefixed-SI", "rot.b", 40,
15380 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15382 /* rot.b r1h,${Dsp-16-u8}[sb] */
15384 M32C_INSN_ROT32_B_DST_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "rot32.b-dst-dst32-16-8-SB-relative-Unprefixed-SI", "rot.b", 24,
15385 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15387 /* rot.b r1h,${Dsp-16-u16}[sb] */
15389 M32C_INSN_ROT32_B_DST_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "rot32.b-dst-dst32-16-16-SB-relative-Unprefixed-SI", "rot.b", 32,
15390 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15392 /* rot.b r1h,${Dsp-16-s8}[fb] */
15394 M32C_INSN_ROT32_B_DST_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "rot32.b-dst-dst32-16-8-FB-relative-Unprefixed-SI", "rot.b", 24,
15395 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15397 /* rot.b r1h,${Dsp-16-s16}[fb] */
15399 M32C_INSN_ROT32_B_DST_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "rot32.b-dst-dst32-16-16-FB-relative-Unprefixed-SI", "rot.b", 32,
15400 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15402 /* rot.b r1h,${Dsp-16-u16} */
15404 M32C_INSN_ROT32_B_DST_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "rot32.b-dst-dst32-16-16-absolute-Unprefixed-SI", "rot.b", 32,
15405 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15407 /* rot.b r1h,${Dsp-16-u24} */
15409 M32C_INSN_ROT32_B_DST_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "rot32.b-dst-dst32-16-24-absolute-Unprefixed-SI", "rot.b", 40,
15410 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15412 /* rot.w r1h,$Dst16RnHI */
15414 M32C_INSN_ROT16_W_DST_DST16_RN_DIRECT_HI, "rot16.w-dst-dst16-Rn-direct-HI", "rot.w", 16,
15415 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15417 /* rot.w r1h,$Dst16AnHI */
15419 M32C_INSN_ROT16_W_DST_DST16_AN_DIRECT_HI, "rot16.w-dst-dst16-An-direct-HI", "rot.w", 16,
15420 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15422 /* rot.w r1h,[$Dst16An] */
15424 M32C_INSN_ROT16_W_DST_DST16_AN_INDIRECT_HI, "rot16.w-dst-dst16-An-indirect-HI", "rot.w", 16,
15425 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15427 /* rot.w r1h,${Dsp-16-u8}[$Dst16An] */
15429 M32C_INSN_ROT16_W_DST_DST16_16_8_AN_RELATIVE_HI, "rot16.w-dst-dst16-16-8-An-relative-HI", "rot.w", 24,
15430 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15432 /* rot.w r1h,${Dsp-16-u16}[$Dst16An] */
15434 M32C_INSN_ROT16_W_DST_DST16_16_16_AN_RELATIVE_HI, "rot16.w-dst-dst16-16-16-An-relative-HI", "rot.w", 32,
15435 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15437 /* rot.w r1h,${Dsp-16-u8}[sb] */
15439 M32C_INSN_ROT16_W_DST_DST16_16_8_SB_RELATIVE_HI, "rot16.w-dst-dst16-16-8-SB-relative-HI", "rot.w", 24,
15440 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15442 /* rot.w r1h,${Dsp-16-u16}[sb] */
15444 M32C_INSN_ROT16_W_DST_DST16_16_16_SB_RELATIVE_HI, "rot16.w-dst-dst16-16-16-SB-relative-HI", "rot.w", 32,
15445 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15447 /* rot.w r1h,${Dsp-16-s8}[fb] */
15449 M32C_INSN_ROT16_W_DST_DST16_16_8_FB_RELATIVE_HI, "rot16.w-dst-dst16-16-8-FB-relative-HI", "rot.w", 24,
15450 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15452 /* rot.w r1h,${Dsp-16-u16} */
15454 M32C_INSN_ROT16_W_DST_DST16_16_16_ABSOLUTE_HI, "rot16.w-dst-dst16-16-16-absolute-HI", "rot.w", 32,
15455 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15457 /* rot.b r1h,$Dst16RnHI */
15459 M32C_INSN_ROT16_B_DST_DST16_RN_DIRECT_HI, "rot16.b-dst-dst16-Rn-direct-HI", "rot.b", 16,
15460 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15462 /* rot.b r1h,$Dst16AnHI */
15464 M32C_INSN_ROT16_B_DST_DST16_AN_DIRECT_HI, "rot16.b-dst-dst16-An-direct-HI", "rot.b", 16,
15465 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15467 /* rot.b r1h,[$Dst16An] */
15469 M32C_INSN_ROT16_B_DST_DST16_AN_INDIRECT_HI, "rot16.b-dst-dst16-An-indirect-HI", "rot.b", 16,
15470 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15472 /* rot.b r1h,${Dsp-16-u8}[$Dst16An] */
15474 M32C_INSN_ROT16_B_DST_DST16_16_8_AN_RELATIVE_HI, "rot16.b-dst-dst16-16-8-An-relative-HI", "rot.b", 24,
15475 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15477 /* rot.b r1h,${Dsp-16-u16}[$Dst16An] */
15479 M32C_INSN_ROT16_B_DST_DST16_16_16_AN_RELATIVE_HI, "rot16.b-dst-dst16-16-16-An-relative-HI", "rot.b", 32,
15480 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15482 /* rot.b r1h,${Dsp-16-u8}[sb] */
15484 M32C_INSN_ROT16_B_DST_DST16_16_8_SB_RELATIVE_HI, "rot16.b-dst-dst16-16-8-SB-relative-HI", "rot.b", 24,
15485 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15487 /* rot.b r1h,${Dsp-16-u16}[sb] */
15489 M32C_INSN_ROT16_B_DST_DST16_16_16_SB_RELATIVE_HI, "rot16.b-dst-dst16-16-16-SB-relative-HI", "rot.b", 32,
15490 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15492 /* rot.b r1h,${Dsp-16-s8}[fb] */
15494 M32C_INSN_ROT16_B_DST_DST16_16_8_FB_RELATIVE_HI, "rot16.b-dst-dst16-16-8-FB-relative-HI", "rot.b", 24,
15495 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15497 /* rot.b r1h,${Dsp-16-u16} */
15499 M32C_INSN_ROT16_B_DST_DST16_16_16_ABSOLUTE_HI, "rot16.b-dst-dst16-16-16-absolute-HI", "rot.b", 32,
15500 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15502 /* rot.w${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedHI */
15504 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "rot.w", 16,
15505 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15507 /* rot.w${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedHI */
15509 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "rot.w", 16,
15510 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15512 /* rot.w${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
15514 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "rot.w", 16,
15515 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15517 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
15519 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "rot.w", 24,
15520 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15522 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
15524 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "rot.w", 32,
15525 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15527 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
15529 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "rot.w", 40,
15530 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15532 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
15534 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "rot.w", 24,
15535 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15537 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
15539 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "rot.w", 32,
15540 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15542 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
15544 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "rot.w", 24,
15545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15547 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
15549 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "rot.w", 32,
15550 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15552 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
15554 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "rot.w", 32,
15555 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15557 /* rot.w${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
15559 M32C_INSN_ROT32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "rot32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "rot.w", 40,
15560 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15562 /* rot.b${Q} #${Imm-sh-12-s4},$Dst32RnUnprefixedQI */
15564 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "rot.b", 16,
15565 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15567 /* rot.b${Q} #${Imm-sh-12-s4},$Dst32AnUnprefixedQI */
15569 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "rot.b", 16,
15570 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15572 /* rot.b${Q} #${Imm-sh-12-s4},[$Dst32AnUnprefixed] */
15574 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "rot.b", 16,
15575 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15577 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
15579 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "rot.b", 24,
15580 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15582 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
15584 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "rot.b", 32,
15585 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15587 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
15589 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "rot.b", 40,
15590 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15592 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u8}[sb] */
15594 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "rot.b", 24,
15595 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15597 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16}[sb] */
15599 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "rot.b", 32,
15600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15602 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-s8}[fb] */
15604 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "rot.b", 24,
15605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15607 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-s16}[fb] */
15609 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "rot.b", 32,
15610 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15612 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u16} */
15614 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "rot.b", 32,
15615 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15617 /* rot.b${Q} #${Imm-sh-12-s4},${Dsp-16-u24} */
15619 M32C_INSN_ROT32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "rot32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "rot.b", 40,
15620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15622 /* rot.w${Q} #${Imm-sh-8-s4},$Dst16RnHI */
15624 M32C_INSN_ROT16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "rot16.w-imm4-Q-16-dst16-Rn-direct-HI", "rot.w", 16,
15625 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15627 /* rot.w${Q} #${Imm-sh-8-s4},$Dst16AnHI */
15629 M32C_INSN_ROT16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "rot16.w-imm4-Q-16-dst16-An-direct-HI", "rot.w", 16,
15630 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15632 /* rot.w${Q} #${Imm-sh-8-s4},[$Dst16An] */
15634 M32C_INSN_ROT16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "rot16.w-imm4-Q-16-dst16-An-indirect-HI", "rot.w", 16,
15635 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15637 /* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
15639 M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "rot.w", 24,
15640 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15642 /* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
15644 M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "rot.w", 32,
15645 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15647 /* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
15649 M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "rot.w", 24,
15650 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15652 /* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
15654 M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "rot.w", 32,
15655 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15657 /* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
15659 M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "rot16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "rot.w", 24,
15660 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15662 /* rot.w${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
15664 M32C_INSN_ROT16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "rot16.w-imm4-Q-16-dst16-16-16-absolute-HI", "rot.w", 32,
15665 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15667 /* rot.b${Q} #${Imm-sh-8-s4},$Dst16RnQI */
15669 M32C_INSN_ROT16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "rot16.b-imm4-Q-16-dst16-Rn-direct-QI", "rot.b", 16,
15670 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15672 /* rot.b${Q} #${Imm-sh-8-s4},$Dst16AnQI */
15674 M32C_INSN_ROT16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "rot16.b-imm4-Q-16-dst16-An-direct-QI", "rot.b", 16,
15675 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15677 /* rot.b${Q} #${Imm-sh-8-s4},[$Dst16An] */
15679 M32C_INSN_ROT16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "rot16.b-imm4-Q-16-dst16-An-indirect-QI", "rot.b", 16,
15680 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15682 /* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[$Dst16An] */
15684 M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "rot.b", 24,
15685 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15687 /* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[$Dst16An] */
15689 M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "rot.b", 32,
15690 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15692 /* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u8}[sb] */
15694 M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "rot.b", 24,
15695 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15697 /* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16}[sb] */
15699 M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "rot.b", 32,
15700 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15702 /* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-s8}[fb] */
15704 M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "rot16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "rot.b", 24,
15705 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15707 /* rot.b${Q} #${Imm-sh-8-s4},${Dsp-16-u16} */
15709 M32C_INSN_ROT16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "rot16.b-imm4-Q-16-dst16-16-16-absolute-QI", "rot.b", 32,
15710 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15712 /* rorc.w $Dst32RnUnprefixedHI */
15714 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "rorc.w", 16,
15715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15717 /* rorc.w $Dst32AnUnprefixedHI */
15719 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "rorc.w", 16,
15720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15722 /* rorc.w [$Dst32AnUnprefixed] */
15724 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "rorc.w", 16,
15725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15727 /* rorc.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
15729 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "rorc.w", 24,
15730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15732 /* rorc.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
15734 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "rorc.w", 32,
15735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15737 /* rorc.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
15739 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "rorc.w", 40,
15740 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15742 /* rorc.w ${Dsp-16-u8}[sb] */
15744 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "rorc.w", 24,
15745 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15747 /* rorc.w ${Dsp-16-u16}[sb] */
15749 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "rorc.w", 32,
15750 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15752 /* rorc.w ${Dsp-16-s8}[fb] */
15754 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "rorc.w", 24,
15755 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15757 /* rorc.w ${Dsp-16-s16}[fb] */
15759 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "rorc.w", 32,
15760 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15762 /* rorc.w ${Dsp-16-u16} */
15764 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "rorc.w", 32,
15765 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15767 /* rorc.w ${Dsp-16-u24} */
15769 M32C_INSN_RORC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "rorc32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "rorc.w", 40,
15770 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15772 /* rorc.b $Dst32RnUnprefixedQI */
15774 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "rorc.b", 16,
15775 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15777 /* rorc.b $Dst32AnUnprefixedQI */
15779 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "rorc.b", 16,
15780 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15782 /* rorc.b [$Dst32AnUnprefixed] */
15784 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "rorc.b", 16,
15785 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15787 /* rorc.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
15789 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "rorc.b", 24,
15790 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15792 /* rorc.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
15794 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "rorc.b", 32,
15795 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15797 /* rorc.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
15799 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "rorc.b", 40,
15800 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15802 /* rorc.b ${Dsp-16-u8}[sb] */
15804 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "rorc.b", 24,
15805 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15807 /* rorc.b ${Dsp-16-u16}[sb] */
15809 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "rorc.b", 32,
15810 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15812 /* rorc.b ${Dsp-16-s8}[fb] */
15814 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "rorc.b", 24,
15815 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15817 /* rorc.b ${Dsp-16-s16}[fb] */
15819 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "rorc.b", 32,
15820 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15822 /* rorc.b ${Dsp-16-u16} */
15824 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "rorc.b", 32,
15825 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15827 /* rorc.b ${Dsp-16-u24} */
15829 M32C_INSN_RORC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "rorc32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "rorc.b", 40,
15830 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15832 /* rorc.w $Dst16RnHI */
15834 M32C_INSN_RORC16_W_16_DST16_RN_DIRECT_HI, "rorc16.w-16-dst16-Rn-direct-HI", "rorc.w", 16,
15835 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15837 /* rorc.w $Dst16AnHI */
15839 M32C_INSN_RORC16_W_16_DST16_AN_DIRECT_HI, "rorc16.w-16-dst16-An-direct-HI", "rorc.w", 16,
15840 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15842 /* rorc.w [$Dst16An] */
15844 M32C_INSN_RORC16_W_16_DST16_AN_INDIRECT_HI, "rorc16.w-16-dst16-An-indirect-HI", "rorc.w", 16,
15845 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15847 /* rorc.w ${Dsp-16-u8}[$Dst16An] */
15849 M32C_INSN_RORC16_W_16_DST16_16_8_AN_RELATIVE_HI, "rorc16.w-16-dst16-16-8-An-relative-HI", "rorc.w", 24,
15850 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15852 /* rorc.w ${Dsp-16-u16}[$Dst16An] */
15854 M32C_INSN_RORC16_W_16_DST16_16_16_AN_RELATIVE_HI, "rorc16.w-16-dst16-16-16-An-relative-HI", "rorc.w", 32,
15855 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15857 /* rorc.w ${Dsp-16-u8}[sb] */
15859 M32C_INSN_RORC16_W_16_DST16_16_8_SB_RELATIVE_HI, "rorc16.w-16-dst16-16-8-SB-relative-HI", "rorc.w", 24,
15860 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15862 /* rorc.w ${Dsp-16-u16}[sb] */
15864 M32C_INSN_RORC16_W_16_DST16_16_16_SB_RELATIVE_HI, "rorc16.w-16-dst16-16-16-SB-relative-HI", "rorc.w", 32,
15865 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15867 /* rorc.w ${Dsp-16-s8}[fb] */
15869 M32C_INSN_RORC16_W_16_DST16_16_8_FB_RELATIVE_HI, "rorc16.w-16-dst16-16-8-FB-relative-HI", "rorc.w", 24,
15870 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15872 /* rorc.w ${Dsp-16-u16} */
15874 M32C_INSN_RORC16_W_16_DST16_16_16_ABSOLUTE_HI, "rorc16.w-16-dst16-16-16-absolute-HI", "rorc.w", 32,
15875 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15877 /* rorc.b $Dst16RnQI */
15879 M32C_INSN_RORC16_B_16_DST16_RN_DIRECT_QI, "rorc16.b-16-dst16-Rn-direct-QI", "rorc.b", 16,
15880 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15882 /* rorc.b $Dst16AnQI */
15884 M32C_INSN_RORC16_B_16_DST16_AN_DIRECT_QI, "rorc16.b-16-dst16-An-direct-QI", "rorc.b", 16,
15885 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15887 /* rorc.b [$Dst16An] */
15889 M32C_INSN_RORC16_B_16_DST16_AN_INDIRECT_QI, "rorc16.b-16-dst16-An-indirect-QI", "rorc.b", 16,
15890 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15892 /* rorc.b ${Dsp-16-u8}[$Dst16An] */
15894 M32C_INSN_RORC16_B_16_DST16_16_8_AN_RELATIVE_QI, "rorc16.b-16-dst16-16-8-An-relative-QI", "rorc.b", 24,
15895 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15897 /* rorc.b ${Dsp-16-u16}[$Dst16An] */
15899 M32C_INSN_RORC16_B_16_DST16_16_16_AN_RELATIVE_QI, "rorc16.b-16-dst16-16-16-An-relative-QI", "rorc.b", 32,
15900 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15902 /* rorc.b ${Dsp-16-u8}[sb] */
15904 M32C_INSN_RORC16_B_16_DST16_16_8_SB_RELATIVE_QI, "rorc16.b-16-dst16-16-8-SB-relative-QI", "rorc.b", 24,
15905 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15907 /* rorc.b ${Dsp-16-u16}[sb] */
15909 M32C_INSN_RORC16_B_16_DST16_16_16_SB_RELATIVE_QI, "rorc16.b-16-dst16-16-16-SB-relative-QI", "rorc.b", 32,
15910 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15912 /* rorc.b ${Dsp-16-s8}[fb] */
15914 M32C_INSN_RORC16_B_16_DST16_16_8_FB_RELATIVE_QI, "rorc16.b-16-dst16-16-8-FB-relative-QI", "rorc.b", 24,
15915 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15917 /* rorc.b ${Dsp-16-u16} */
15919 M32C_INSN_RORC16_B_16_DST16_16_16_ABSOLUTE_QI, "rorc16.b-16-dst16-16-16-absolute-QI", "rorc.b", 32,
15920 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
15922 /* rolc.w $Dst32RnUnprefixedHI */
15924 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "rolc.w", 16,
15925 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15927 /* rolc.w $Dst32AnUnprefixedHI */
15929 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "rolc.w", 16,
15930 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15932 /* rolc.w [$Dst32AnUnprefixed] */
15934 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "rolc.w", 16,
15935 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15937 /* rolc.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
15939 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "rolc.w", 24,
15940 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15942 /* rolc.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
15944 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "rolc.w", 32,
15945 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15947 /* rolc.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
15949 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "rolc.w", 40,
15950 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15952 /* rolc.w ${Dsp-16-u8}[sb] */
15954 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "rolc.w", 24,
15955 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15957 /* rolc.w ${Dsp-16-u16}[sb] */
15959 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "rolc.w", 32,
15960 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15962 /* rolc.w ${Dsp-16-s8}[fb] */
15964 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "rolc.w", 24,
15965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15967 /* rolc.w ${Dsp-16-s16}[fb] */
15969 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "rolc.w", 32,
15970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15972 /* rolc.w ${Dsp-16-u16} */
15974 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "rolc.w", 32,
15975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15977 /* rolc.w ${Dsp-16-u24} */
15979 M32C_INSN_ROLC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "rolc32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "rolc.w", 40,
15980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15982 /* rolc.b $Dst32RnUnprefixedQI */
15984 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "rolc.b", 16,
15985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15987 /* rolc.b $Dst32AnUnprefixedQI */
15989 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "rolc.b", 16,
15990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15992 /* rolc.b [$Dst32AnUnprefixed] */
15994 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "rolc.b", 16,
15995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
15997 /* rolc.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
15999 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "rolc.b", 24,
16000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16002 /* rolc.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
16004 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "rolc.b", 32,
16005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16007 /* rolc.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
16009 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "rolc.b", 40,
16010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16012 /* rolc.b ${Dsp-16-u8}[sb] */
16014 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "rolc.b", 24,
16015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16017 /* rolc.b ${Dsp-16-u16}[sb] */
16019 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "rolc.b", 32,
16020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16022 /* rolc.b ${Dsp-16-s8}[fb] */
16024 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "rolc.b", 24,
16025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16027 /* rolc.b ${Dsp-16-s16}[fb] */
16029 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "rolc.b", 32,
16030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16032 /* rolc.b ${Dsp-16-u16} */
16034 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "rolc.b", 32,
16035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16037 /* rolc.b ${Dsp-16-u24} */
16039 M32C_INSN_ROLC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "rolc32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "rolc.b", 40,
16040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16042 /* rolc.w $Dst16RnHI */
16044 M32C_INSN_ROLC16_W_16_DST16_RN_DIRECT_HI, "rolc16.w-16-dst16-Rn-direct-HI", "rolc.w", 16,
16045 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16047 /* rolc.w $Dst16AnHI */
16049 M32C_INSN_ROLC16_W_16_DST16_AN_DIRECT_HI, "rolc16.w-16-dst16-An-direct-HI", "rolc.w", 16,
16050 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16052 /* rolc.w [$Dst16An] */
16054 M32C_INSN_ROLC16_W_16_DST16_AN_INDIRECT_HI, "rolc16.w-16-dst16-An-indirect-HI", "rolc.w", 16,
16055 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16057 /* rolc.w ${Dsp-16-u8}[$Dst16An] */
16059 M32C_INSN_ROLC16_W_16_DST16_16_8_AN_RELATIVE_HI, "rolc16.w-16-dst16-16-8-An-relative-HI", "rolc.w", 24,
16060 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16062 /* rolc.w ${Dsp-16-u16}[$Dst16An] */
16064 M32C_INSN_ROLC16_W_16_DST16_16_16_AN_RELATIVE_HI, "rolc16.w-16-dst16-16-16-An-relative-HI", "rolc.w", 32,
16065 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16067 /* rolc.w ${Dsp-16-u8}[sb] */
16069 M32C_INSN_ROLC16_W_16_DST16_16_8_SB_RELATIVE_HI, "rolc16.w-16-dst16-16-8-SB-relative-HI", "rolc.w", 24,
16070 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16072 /* rolc.w ${Dsp-16-u16}[sb] */
16074 M32C_INSN_ROLC16_W_16_DST16_16_16_SB_RELATIVE_HI, "rolc16.w-16-dst16-16-16-SB-relative-HI", "rolc.w", 32,
16075 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16077 /* rolc.w ${Dsp-16-s8}[fb] */
16079 M32C_INSN_ROLC16_W_16_DST16_16_8_FB_RELATIVE_HI, "rolc16.w-16-dst16-16-8-FB-relative-HI", "rolc.w", 24,
16080 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16082 /* rolc.w ${Dsp-16-u16} */
16084 M32C_INSN_ROLC16_W_16_DST16_16_16_ABSOLUTE_HI, "rolc16.w-16-dst16-16-16-absolute-HI", "rolc.w", 32,
16085 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16087 /* rolc.b $Dst16RnQI */
16089 M32C_INSN_ROLC16_B_16_DST16_RN_DIRECT_QI, "rolc16.b-16-dst16-Rn-direct-QI", "rolc.b", 16,
16090 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16092 /* rolc.b $Dst16AnQI */
16094 M32C_INSN_ROLC16_B_16_DST16_AN_DIRECT_QI, "rolc16.b-16-dst16-An-direct-QI", "rolc.b", 16,
16095 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16097 /* rolc.b [$Dst16An] */
16099 M32C_INSN_ROLC16_B_16_DST16_AN_INDIRECT_QI, "rolc16.b-16-dst16-An-indirect-QI", "rolc.b", 16,
16100 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16102 /* rolc.b ${Dsp-16-u8}[$Dst16An] */
16104 M32C_INSN_ROLC16_B_16_DST16_16_8_AN_RELATIVE_QI, "rolc16.b-16-dst16-16-8-An-relative-QI", "rolc.b", 24,
16105 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16107 /* rolc.b ${Dsp-16-u16}[$Dst16An] */
16109 M32C_INSN_ROLC16_B_16_DST16_16_16_AN_RELATIVE_QI, "rolc16.b-16-dst16-16-16-An-relative-QI", "rolc.b", 32,
16110 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16112 /* rolc.b ${Dsp-16-u8}[sb] */
16114 M32C_INSN_ROLC16_B_16_DST16_16_8_SB_RELATIVE_QI, "rolc16.b-16-dst16-16-8-SB-relative-QI", "rolc.b", 24,
16115 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16117 /* rolc.b ${Dsp-16-u16}[sb] */
16119 M32C_INSN_ROLC16_B_16_DST16_16_16_SB_RELATIVE_QI, "rolc16.b-16-dst16-16-16-SB-relative-QI", "rolc.b", 32,
16120 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16122 /* rolc.b ${Dsp-16-s8}[fb] */
16124 M32C_INSN_ROLC16_B_16_DST16_16_8_FB_RELATIVE_QI, "rolc16.b-16-dst16-16-8-FB-relative-QI", "rolc.b", 24,
16125 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16127 /* rolc.b ${Dsp-16-u16} */
16129 M32C_INSN_ROLC16_B_16_DST16_16_16_ABSOLUTE_QI, "rolc16.b-16-dst16-16-16-absolute-QI", "rolc.b", 32,
16130 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16132 /* pusha [$Dst32AnUnprefixed] */
16134 M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-An-indirect-Unprefixed-Mova-SI", "pusha", 16,
16135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16137 /* pusha ${Dsp-16-u8}[$Dst32AnUnprefixed] */
16139 M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-8-An-relative-Unprefixed-Mova-SI", "pusha", 24,
16140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16142 /* pusha ${Dsp-16-u16}[$Dst32AnUnprefixed] */
16144 M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-16-An-relative-Unprefixed-Mova-SI", "pusha", 32,
16145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16147 /* pusha ${Dsp-16-u24}[$Dst32AnUnprefixed] */
16149 M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-24-An-relative-Unprefixed-Mova-SI", "pusha", 40,
16150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16152 /* pusha ${Dsp-16-u8}[sb] */
16154 M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "pusha", 24,
16155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16157 /* pusha ${Dsp-16-u16}[sb] */
16159 M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "pusha", 32,
16160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16162 /* pusha ${Dsp-16-s8}[fb] */
16164 M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "pusha", 24,
16165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16167 /* pusha ${Dsp-16-s16}[fb] */
16169 M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "pusha", 32,
16170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16172 /* pusha ${Dsp-16-u16} */
16174 M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-16-absolute-Unprefixed-Mova-SI", "pusha", 32,
16175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16177 /* pusha ${Dsp-16-u24} */
16179 M32C_INSN_PUSHA32_16_UNPREFIXED_MOVA_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "pusha32-16-Unprefixed-Mova-dst32-16-24-absolute-Unprefixed-Mova-SI", "pusha", 40,
16180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16182 /* pusha [$Dst16An] */
16184 M32C_INSN_PUSHA16_16_MOVA_DST16_AN_INDIRECT_MOVA_HI, "pusha16-16-Mova-dst16-An-indirect-Mova-HI", "pusha", 16,
16185 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16187 /* pusha ${Dsp-16-u8}[$Dst16An] */
16189 M32C_INSN_PUSHA16_16_MOVA_DST16_16_8_AN_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-8-An-relative-Mova-HI", "pusha", 24,
16190 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16192 /* pusha ${Dsp-16-u16}[$Dst16An] */
16194 M32C_INSN_PUSHA16_16_MOVA_DST16_16_16_AN_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-16-An-relative-Mova-HI", "pusha", 32,
16195 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16197 /* pusha ${Dsp-16-u8}[sb] */
16199 M32C_INSN_PUSHA16_16_MOVA_DST16_16_8_SB_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-8-SB-relative-Mova-HI", "pusha", 24,
16200 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16202 /* pusha ${Dsp-16-u16}[sb] */
16204 M32C_INSN_PUSHA16_16_MOVA_DST16_16_16_SB_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-16-SB-relative-Mova-HI", "pusha", 32,
16205 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16207 /* pusha ${Dsp-16-s8}[fb] */
16209 M32C_INSN_PUSHA16_16_MOVA_DST16_16_8_FB_RELATIVE_MOVA_HI, "pusha16-16-Mova-dst16-16-8-FB-relative-Mova-HI", "pusha", 24,
16210 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16212 /* pusha ${Dsp-16-u16} */
16214 M32C_INSN_PUSHA16_16_MOVA_DST16_16_16_ABSOLUTE_MOVA_HI, "pusha16-16-Mova-dst16-16-16-absolute-Mova-HI", "pusha", 32,
16215 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16217 /* push.l $Dst32RnUnprefixedSI */
16219 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "push.l", 16,
16220 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16222 /* push.l $Dst32AnUnprefixedSI */
16224 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-An-direct-Unprefixed-SI", "push.l", 16,
16225 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16227 /* push.l [$Dst32AnUnprefixed] */
16229 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-An-indirect-Unprefixed-SI", "push.l", 16,
16230 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16232 /* push.l ${Dsp-16-u8}[$Dst32AnUnprefixed] */
16234 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "push.l", 24,
16235 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16237 /* push.l ${Dsp-16-u16}[$Dst32AnUnprefixed] */
16239 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "push.l", 32,
16240 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16242 /* push.l ${Dsp-16-u24}[$Dst32AnUnprefixed] */
16244 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "push.l", 40,
16245 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16247 /* push.l ${Dsp-16-u8}[sb] */
16249 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "push.l", 24,
16250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16252 /* push.l ${Dsp-16-u16}[sb] */
16254 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "push.l", 32,
16255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16257 /* push.l ${Dsp-16-s8}[fb] */
16259 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "push.l", 24,
16260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16262 /* push.l ${Dsp-16-s16}[fb] */
16264 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "push.l", 32,
16265 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16267 /* push.l ${Dsp-16-u16} */
16269 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "push.l", 32,
16270 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16272 /* push.l ${Dsp-16-u24} */
16274 M32C_INSN_PUSH32_L_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "push32.l-16-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "push.l", 40,
16275 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16277 /* push.w${S} ${An16-push-S} */
16279 M32C_INSN_PUSH16_B_S_AN_AN16_PUSH_S_DERIVED, "push16.b-s-an-An16-push-S-derived", "push.w", 8,
16280 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16282 /* push.b${S} ${Rn16-push-S} */
16284 M32C_INSN_PUSH16_B_S_RN_RN16_PUSH_S_DERIVED, "push16.b-s-rn-Rn16-push-S-derived", "push.b", 8,
16285 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16287 /* push.w $Dst32RnUnprefixedHI */
16289 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "push.w", 16,
16290 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16292 /* push.w $Dst32AnUnprefixedHI */
16294 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "push.w", 16,
16295 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16297 /* push.w [$Dst32AnUnprefixed] */
16299 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "push.w", 16,
16300 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16302 /* push.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
16304 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "push.w", 24,
16305 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16307 /* push.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
16309 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "push.w", 32,
16310 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16312 /* push.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
16314 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "push.w", 40,
16315 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16317 /* push.w ${Dsp-16-u8}[sb] */
16319 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "push.w", 24,
16320 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16322 /* push.w ${Dsp-16-u16}[sb] */
16324 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "push.w", 32,
16325 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16327 /* push.w ${Dsp-16-s8}[fb] */
16329 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "push.w", 24,
16330 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16332 /* push.w ${Dsp-16-s16}[fb] */
16334 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "push.w", 32,
16335 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16337 /* push.w ${Dsp-16-u16} */
16339 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "push.w", 32,
16340 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16342 /* push.w ${Dsp-16-u24} */
16344 M32C_INSN_PUSH32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "push32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "push.w", 40,
16345 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16347 /* push.b $Dst32RnUnprefixedQI */
16349 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "push.b", 16,
16350 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16352 /* push.b $Dst32AnUnprefixedQI */
16354 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "push.b", 16,
16355 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16357 /* push.b [$Dst32AnUnprefixed] */
16359 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "push.b", 16,
16360 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16362 /* push.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
16364 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "push.b", 24,
16365 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16367 /* push.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
16369 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "push.b", 32,
16370 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16372 /* push.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
16374 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "push.b", 40,
16375 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16377 /* push.b ${Dsp-16-u8}[sb] */
16379 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "push.b", 24,
16380 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16382 /* push.b ${Dsp-16-u16}[sb] */
16384 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "push.b", 32,
16385 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16387 /* push.b ${Dsp-16-s8}[fb] */
16389 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "push.b", 24,
16390 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16392 /* push.b ${Dsp-16-s16}[fb] */
16394 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "push.b", 32,
16395 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16397 /* push.b ${Dsp-16-u16} */
16399 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "push.b", 32,
16400 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16402 /* push.b ${Dsp-16-u24} */
16404 M32C_INSN_PUSH32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "push32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "push.b", 40,
16405 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16407 /* push.w $Dst16RnHI */
16409 M32C_INSN_PUSH16_W_16_DST16_RN_DIRECT_HI, "push16.w-16-dst16-Rn-direct-HI", "push.w", 16,
16410 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16412 /* push.w $Dst16AnHI */
16414 M32C_INSN_PUSH16_W_16_DST16_AN_DIRECT_HI, "push16.w-16-dst16-An-direct-HI", "push.w", 16,
16415 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16417 /* push.w [$Dst16An] */
16419 M32C_INSN_PUSH16_W_16_DST16_AN_INDIRECT_HI, "push16.w-16-dst16-An-indirect-HI", "push.w", 16,
16420 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16422 /* push.w ${Dsp-16-u8}[$Dst16An] */
16424 M32C_INSN_PUSH16_W_16_DST16_16_8_AN_RELATIVE_HI, "push16.w-16-dst16-16-8-An-relative-HI", "push.w", 24,
16425 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16427 /* push.w ${Dsp-16-u16}[$Dst16An] */
16429 M32C_INSN_PUSH16_W_16_DST16_16_16_AN_RELATIVE_HI, "push16.w-16-dst16-16-16-An-relative-HI", "push.w", 32,
16430 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16432 /* push.w ${Dsp-16-u8}[sb] */
16434 M32C_INSN_PUSH16_W_16_DST16_16_8_SB_RELATIVE_HI, "push16.w-16-dst16-16-8-SB-relative-HI", "push.w", 24,
16435 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16437 /* push.w ${Dsp-16-u16}[sb] */
16439 M32C_INSN_PUSH16_W_16_DST16_16_16_SB_RELATIVE_HI, "push16.w-16-dst16-16-16-SB-relative-HI", "push.w", 32,
16440 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16442 /* push.w ${Dsp-16-s8}[fb] */
16444 M32C_INSN_PUSH16_W_16_DST16_16_8_FB_RELATIVE_HI, "push16.w-16-dst16-16-8-FB-relative-HI", "push.w", 24,
16445 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16447 /* push.w ${Dsp-16-u16} */
16449 M32C_INSN_PUSH16_W_16_DST16_16_16_ABSOLUTE_HI, "push16.w-16-dst16-16-16-absolute-HI", "push.w", 32,
16450 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16452 /* push.b $Dst16RnQI */
16454 M32C_INSN_PUSH16_B_16_DST16_RN_DIRECT_QI, "push16.b-16-dst16-Rn-direct-QI", "push.b", 16,
16455 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16457 /* push.b $Dst16AnQI */
16459 M32C_INSN_PUSH16_B_16_DST16_AN_DIRECT_QI, "push16.b-16-dst16-An-direct-QI", "push.b", 16,
16460 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16462 /* push.b [$Dst16An] */
16464 M32C_INSN_PUSH16_B_16_DST16_AN_INDIRECT_QI, "push16.b-16-dst16-An-indirect-QI", "push.b", 16,
16465 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16467 /* push.b ${Dsp-16-u8}[$Dst16An] */
16469 M32C_INSN_PUSH16_B_16_DST16_16_8_AN_RELATIVE_QI, "push16.b-16-dst16-16-8-An-relative-QI", "push.b", 24,
16470 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16472 /* push.b ${Dsp-16-u16}[$Dst16An] */
16474 M32C_INSN_PUSH16_B_16_DST16_16_16_AN_RELATIVE_QI, "push16.b-16-dst16-16-16-An-relative-QI", "push.b", 32,
16475 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16477 /* push.b ${Dsp-16-u8}[sb] */
16479 M32C_INSN_PUSH16_B_16_DST16_16_8_SB_RELATIVE_QI, "push16.b-16-dst16-16-8-SB-relative-QI", "push.b", 24,
16480 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16482 /* push.b ${Dsp-16-u16}[sb] */
16484 M32C_INSN_PUSH16_B_16_DST16_16_16_SB_RELATIVE_QI, "push16.b-16-dst16-16-16-SB-relative-QI", "push.b", 32,
16485 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16487 /* push.b ${Dsp-16-s8}[fb] */
16489 M32C_INSN_PUSH16_B_16_DST16_16_8_FB_RELATIVE_QI, "push16.b-16-dst16-16-8-FB-relative-QI", "push.b", 24,
16490 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16492 /* push.b ${Dsp-16-u16} */
16494 M32C_INSN_PUSH16_B_16_DST16_16_16_ABSOLUTE_QI, "push16.b-16-dst16-16-16-absolute-QI", "push.b", 32,
16495 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16497 /* pop.w${S} ${An16-push-S} */
16499 M32C_INSN_POP16_B_S_AN_AN16_PUSH_S_DERIVED, "pop16.b-s-an-An16-push-S-derived", "pop.w", 8,
16500 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16502 /* pop.b${S} ${Rn16-push-S} */
16504 M32C_INSN_POP16_B_S_RN_RN16_PUSH_S_DERIVED, "pop16.b-s-rn-Rn16-push-S-derived", "pop.b", 8,
16505 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16507 /* pop.w $Dst32RnUnprefixedHI */
16509 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "pop.w", 16,
16510 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16512 /* pop.w $Dst32AnUnprefixedHI */
16514 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "pop.w", 16,
16515 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16517 /* pop.w [$Dst32AnUnprefixed] */
16519 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "pop.w", 16,
16520 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16522 /* pop.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
16524 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "pop.w", 24,
16525 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16527 /* pop.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
16529 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "pop.w", 32,
16530 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16532 /* pop.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
16534 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "pop.w", 40,
16535 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16537 /* pop.w ${Dsp-16-u8}[sb] */
16539 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "pop.w", 24,
16540 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16542 /* pop.w ${Dsp-16-u16}[sb] */
16544 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "pop.w", 32,
16545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16547 /* pop.w ${Dsp-16-s8}[fb] */
16549 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "pop.w", 24,
16550 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16552 /* pop.w ${Dsp-16-s16}[fb] */
16554 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "pop.w", 32,
16555 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16557 /* pop.w ${Dsp-16-u16} */
16559 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "pop.w", 32,
16560 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16562 /* pop.w ${Dsp-16-u24} */
16564 M32C_INSN_POP32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "pop32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "pop.w", 40,
16565 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16567 /* pop.b $Dst32RnUnprefixedQI */
16569 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "pop.b", 16,
16570 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16572 /* pop.b $Dst32AnUnprefixedQI */
16574 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "pop.b", 16,
16575 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16577 /* pop.b [$Dst32AnUnprefixed] */
16579 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "pop.b", 16,
16580 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16582 /* pop.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
16584 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "pop.b", 24,
16585 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16587 /* pop.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
16589 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "pop.b", 32,
16590 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16592 /* pop.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
16594 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "pop.b", 40,
16595 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16597 /* pop.b ${Dsp-16-u8}[sb] */
16599 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "pop.b", 24,
16600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16602 /* pop.b ${Dsp-16-u16}[sb] */
16604 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "pop.b", 32,
16605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16607 /* pop.b ${Dsp-16-s8}[fb] */
16609 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "pop.b", 24,
16610 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16612 /* pop.b ${Dsp-16-s16}[fb] */
16614 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "pop.b", 32,
16615 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16617 /* pop.b ${Dsp-16-u16} */
16619 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "pop.b", 32,
16620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16622 /* pop.b ${Dsp-16-u24} */
16624 M32C_INSN_POP32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "pop32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "pop.b", 40,
16625 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16627 /* pop.w $Dst16RnHI */
16629 M32C_INSN_POP16_W_16_DST16_RN_DIRECT_HI, "pop16.w-16-dst16-Rn-direct-HI", "pop.w", 16,
16630 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16632 /* pop.w $Dst16AnHI */
16634 M32C_INSN_POP16_W_16_DST16_AN_DIRECT_HI, "pop16.w-16-dst16-An-direct-HI", "pop.w", 16,
16635 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16637 /* pop.w [$Dst16An] */
16639 M32C_INSN_POP16_W_16_DST16_AN_INDIRECT_HI, "pop16.w-16-dst16-An-indirect-HI", "pop.w", 16,
16640 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16642 /* pop.w ${Dsp-16-u8}[$Dst16An] */
16644 M32C_INSN_POP16_W_16_DST16_16_8_AN_RELATIVE_HI, "pop16.w-16-dst16-16-8-An-relative-HI", "pop.w", 24,
16645 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16647 /* pop.w ${Dsp-16-u16}[$Dst16An] */
16649 M32C_INSN_POP16_W_16_DST16_16_16_AN_RELATIVE_HI, "pop16.w-16-dst16-16-16-An-relative-HI", "pop.w", 32,
16650 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16652 /* pop.w ${Dsp-16-u8}[sb] */
16654 M32C_INSN_POP16_W_16_DST16_16_8_SB_RELATIVE_HI, "pop16.w-16-dst16-16-8-SB-relative-HI", "pop.w", 24,
16655 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16657 /* pop.w ${Dsp-16-u16}[sb] */
16659 M32C_INSN_POP16_W_16_DST16_16_16_SB_RELATIVE_HI, "pop16.w-16-dst16-16-16-SB-relative-HI", "pop.w", 32,
16660 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16662 /* pop.w ${Dsp-16-s8}[fb] */
16664 M32C_INSN_POP16_W_16_DST16_16_8_FB_RELATIVE_HI, "pop16.w-16-dst16-16-8-FB-relative-HI", "pop.w", 24,
16665 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16667 /* pop.w ${Dsp-16-u16} */
16669 M32C_INSN_POP16_W_16_DST16_16_16_ABSOLUTE_HI, "pop16.w-16-dst16-16-16-absolute-HI", "pop.w", 32,
16670 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16672 /* pop.b $Dst16RnQI */
16674 M32C_INSN_POP16_B_16_DST16_RN_DIRECT_QI, "pop16.b-16-dst16-Rn-direct-QI", "pop.b", 16,
16675 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16677 /* pop.b $Dst16AnQI */
16679 M32C_INSN_POP16_B_16_DST16_AN_DIRECT_QI, "pop16.b-16-dst16-An-direct-QI", "pop.b", 16,
16680 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16682 /* pop.b [$Dst16An] */
16684 M32C_INSN_POP16_B_16_DST16_AN_INDIRECT_QI, "pop16.b-16-dst16-An-indirect-QI", "pop.b", 16,
16685 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16687 /* pop.b ${Dsp-16-u8}[$Dst16An] */
16689 M32C_INSN_POP16_B_16_DST16_16_8_AN_RELATIVE_QI, "pop16.b-16-dst16-16-8-An-relative-QI", "pop.b", 24,
16690 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16692 /* pop.b ${Dsp-16-u16}[$Dst16An] */
16694 M32C_INSN_POP16_B_16_DST16_16_16_AN_RELATIVE_QI, "pop16.b-16-dst16-16-16-An-relative-QI", "pop.b", 32,
16695 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16697 /* pop.b ${Dsp-16-u8}[sb] */
16699 M32C_INSN_POP16_B_16_DST16_16_8_SB_RELATIVE_QI, "pop16.b-16-dst16-16-8-SB-relative-QI", "pop.b", 24,
16700 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16702 /* pop.b ${Dsp-16-u16}[sb] */
16704 M32C_INSN_POP16_B_16_DST16_16_16_SB_RELATIVE_QI, "pop16.b-16-dst16-16-16-SB-relative-QI", "pop.b", 32,
16705 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16707 /* pop.b ${Dsp-16-s8}[fb] */
16709 M32C_INSN_POP16_B_16_DST16_16_8_FB_RELATIVE_QI, "pop16.b-16-dst16-16-8-FB-relative-QI", "pop.b", 24,
16710 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16712 /* pop.b ${Dsp-16-u16} */
16714 M32C_INSN_POP16_B_16_DST16_16_16_ABSOLUTE_QI, "pop16.b-16-dst16-16-16-absolute-QI", "pop.b", 32,
16715 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
16717 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
16719 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 24,
16720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16722 /* or.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
16724 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 24,
16725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16727 /* or.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
16729 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 24,
16730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16732 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
16734 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 24,
16735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16737 /* or.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
16739 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 24,
16740 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16742 /* or.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
16744 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 24,
16745 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16747 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
16749 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 24,
16750 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16752 /* or.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
16754 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 24,
16755 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16757 /* or.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
16759 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 24,
16760 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16762 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
16764 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "or.w", 32,
16765 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16767 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
16769 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "or.w", 32,
16770 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16772 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
16774 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "or.w", 32,
16775 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16777 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
16779 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "or.w", 40,
16780 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16782 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
16784 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "or.w", 40,
16785 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16787 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
16789 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "or.w", 40,
16790 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16792 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
16794 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "or.w", 48,
16795 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16797 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
16799 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "or.w", 48,
16800 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16802 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
16804 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "or.w", 48,
16805 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16807 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
16809 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "or.w", 32,
16810 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16812 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
16814 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "or.w", 32,
16815 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16817 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
16819 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "or.w", 32,
16820 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16822 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
16824 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "or.w", 40,
16825 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16827 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
16829 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "or.w", 40,
16830 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16832 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
16834 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "or.w", 40,
16835 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16837 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
16839 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "or.w", 32,
16840 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16842 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
16844 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "or.w", 32,
16845 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16847 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
16849 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "or.w", 32,
16850 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16852 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
16854 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "or.w", 40,
16855 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16857 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
16859 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "or.w", 40,
16860 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16862 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
16864 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "or.w", 40,
16865 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16867 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
16869 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "or.w", 40,
16870 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16872 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
16874 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "or.w", 40,
16875 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16877 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
16879 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "or.w", 40,
16880 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16882 /* or.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
16884 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "or.w", 48,
16885 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16887 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
16889 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "or.w", 48,
16890 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16892 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
16894 M32C_INSN_OR32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "or.w", 48,
16895 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16897 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
16899 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 32,
16900 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16902 /* or.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
16904 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 32,
16905 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16907 /* or.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
16909 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 32,
16910 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16912 /* or.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
16914 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 32,
16915 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16917 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
16919 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 32,
16920 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16922 /* or.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
16924 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 32,
16925 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16927 /* or.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
16929 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 32,
16930 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16932 /* or.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
16934 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 32,
16935 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16937 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
16939 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 32,
16940 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16942 /* or.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
16944 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 32,
16945 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16947 /* or.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
16949 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 32,
16950 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16952 /* or.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
16954 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 32,
16955 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16957 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
16959 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "or.w", 40,
16960 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16962 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
16964 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "or.w", 40,
16965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16967 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
16969 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "or.w", 40,
16970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16972 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
16974 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "or.w", 40,
16975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16977 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
16979 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "or.w", 48,
16980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16982 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
16984 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "or.w", 48,
16985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16987 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
16989 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "or.w", 48,
16990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16992 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
16994 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "or.w", 48,
16995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
16997 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
16999 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "or.w", 56,
17000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17002 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
17004 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "or.w", 56,
17005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17007 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
17009 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "or.w", 56,
17010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17012 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
17014 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "or.w", 56,
17015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17017 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
17019 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "or.w", 40,
17020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17022 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
17024 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "or.w", 40,
17025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17027 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
17029 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "or.w", 40,
17030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17032 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
17034 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "or.w", 40,
17035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17037 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
17039 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "or.w", 48,
17040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17042 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
17044 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "or.w", 48,
17045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17047 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
17049 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "or.w", 48,
17050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17052 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
17054 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "or.w", 48,
17055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17057 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
17059 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "or.w", 40,
17060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17062 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
17064 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "or.w", 40,
17065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17067 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
17069 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "or.w", 40,
17070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17072 /* or.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
17074 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "or.w", 40,
17075 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17077 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
17079 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "or.w", 48,
17080 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17082 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
17084 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "or.w", 48,
17085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17087 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
17089 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "or.w", 48,
17090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17092 /* or.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
17094 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "or.w", 48,
17095 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17097 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
17099 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "or.w", 48,
17100 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17102 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
17104 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "or.w", 48,
17105 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17107 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
17109 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "or.w", 48,
17110 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17112 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
17114 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "or.w", 48,
17115 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17117 /* or.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
17119 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "or.w", 56,
17120 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17122 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
17124 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "or.w", 56,
17125 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17127 /* or.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
17129 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "or.w", 56,
17130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17132 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
17134 M32C_INSN_OR32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "or.w", 56,
17135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17137 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
17139 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 40,
17140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17142 /* or.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
17144 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 40,
17145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17147 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
17149 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 40,
17150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17152 /* or.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
17154 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 40,
17155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17157 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
17159 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 40,
17160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17162 /* or.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
17164 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 40,
17165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17167 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
17169 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "or.w", 48,
17170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17172 /* or.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
17174 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "or.w", 48,
17175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17177 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
17179 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "or.w", 56,
17180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17182 /* or.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
17184 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "or.w", 56,
17185 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17187 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
17189 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "or.w", 64,
17190 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17192 /* or.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
17194 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "or.w", 64,
17195 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17197 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
17199 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "or.w", 48,
17200 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17202 /* or.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
17204 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "or.w", 48,
17205 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17207 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
17209 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "or.w", 56,
17210 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17212 /* or.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
17214 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "or.w", 56,
17215 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17217 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
17219 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "or.w", 48,
17220 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17222 /* or.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
17224 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "or.w", 48,
17225 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17227 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
17229 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "or.w", 56,
17230 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17232 /* or.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
17234 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "or.w", 56,
17235 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17237 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
17239 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "or.w", 56,
17240 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17242 /* or.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
17244 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "or.w", 56,
17245 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17247 /* or.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
17249 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "or.w", 64,
17250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17252 /* or.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
17254 M32C_INSN_OR32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "or.w", 64,
17255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17257 /* or.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
17259 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 16,
17260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17262 /* or.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
17264 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 16,
17265 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17267 /* or.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
17269 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "or.w", 16,
17270 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17272 /* or.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
17274 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 16,
17275 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17277 /* or.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
17279 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 16,
17280 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17282 /* or.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
17284 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "or.w", 16,
17285 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17287 /* or.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
17289 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 16,
17290 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17292 /* or.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
17294 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 16,
17295 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17297 /* or.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
17299 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "or.w", 16,
17300 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17302 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
17304 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "or.w", 24,
17305 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17307 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
17309 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "or.w", 24,
17310 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17312 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
17314 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "or.w", 24,
17315 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17317 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
17319 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "or.w", 32,
17320 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17322 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
17324 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "or.w", 32,
17325 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17327 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
17329 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "or.w", 32,
17330 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17332 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
17334 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "or.w", 40,
17335 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17337 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
17339 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "or.w", 40,
17340 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17342 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
17344 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "or.w", 40,
17345 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17347 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
17349 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "or.w", 24,
17350 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17352 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
17354 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "or.w", 24,
17355 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17357 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
17359 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "or.w", 24,
17360 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17362 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
17364 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "or.w", 32,
17365 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17367 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
17369 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "or.w", 32,
17370 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17372 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
17374 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "or.w", 32,
17375 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17377 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
17379 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "or.w", 24,
17380 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17382 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
17384 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "or.w", 24,
17385 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17387 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
17389 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "or.w", 24,
17390 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17392 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
17394 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "or.w", 32,
17395 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17397 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
17399 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "or.w", 32,
17400 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17402 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
17404 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "or.w", 32,
17405 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17407 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
17409 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "or.w", 32,
17410 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17412 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
17414 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "or.w", 32,
17415 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17417 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
17419 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "or.w", 32,
17420 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17422 /* or.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
17424 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "or.w", 40,
17425 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17427 /* or.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
17429 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "or.w", 40,
17430 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17432 /* or.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
17434 M32C_INSN_OR32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "or.w", 40,
17435 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17437 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
17439 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 24,
17440 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17442 /* or.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
17444 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 24,
17445 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17447 /* or.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
17449 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 24,
17450 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17452 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
17454 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 24,
17455 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17457 /* or.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
17459 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 24,
17460 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17462 /* or.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
17464 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 24,
17465 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17467 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
17469 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 24,
17470 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17472 /* or.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
17474 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 24,
17475 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17477 /* or.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
17479 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 24,
17480 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17482 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
17484 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "or.b", 32,
17485 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17487 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
17489 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "or.b", 32,
17490 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17492 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
17494 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "or.b", 32,
17495 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17497 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
17499 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "or.b", 40,
17500 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17502 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
17504 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "or.b", 40,
17505 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17507 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
17509 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "or.b", 40,
17510 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17512 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
17514 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "or.b", 48,
17515 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17517 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
17519 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "or.b", 48,
17520 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17522 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
17524 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "or.b", 48,
17525 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17527 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
17529 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "or.b", 32,
17530 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17532 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
17534 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "or.b", 32,
17535 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17537 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
17539 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "or.b", 32,
17540 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17542 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
17544 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "or.b", 40,
17545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17547 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
17549 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "or.b", 40,
17550 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17552 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
17554 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "or.b", 40,
17555 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17557 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
17559 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "or.b", 32,
17560 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17562 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
17564 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "or.b", 32,
17565 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17567 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
17569 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "or.b", 32,
17570 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17572 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
17574 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "or.b", 40,
17575 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17577 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
17579 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "or.b", 40,
17580 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17582 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
17584 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "or.b", 40,
17585 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17587 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
17589 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "or.b", 40,
17590 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17592 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
17594 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "or.b", 40,
17595 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17597 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
17599 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "or.b", 40,
17600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17602 /* or.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
17604 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "or.b", 48,
17605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17607 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
17609 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "or.b", 48,
17610 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17612 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
17614 M32C_INSN_OR32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "or.b", 48,
17615 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17617 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
17619 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 32,
17620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17622 /* or.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
17624 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 32,
17625 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17627 /* or.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
17629 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 32,
17630 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17632 /* or.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
17634 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 32,
17635 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17637 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
17639 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 32,
17640 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17642 /* or.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
17644 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 32,
17645 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17647 /* or.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
17649 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 32,
17650 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17652 /* or.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
17654 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 32,
17655 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17657 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
17659 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 32,
17660 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17662 /* or.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
17664 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 32,
17665 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17667 /* or.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
17669 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 32,
17670 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17672 /* or.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
17674 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 32,
17675 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17677 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
17679 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "or.b", 40,
17680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17682 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
17684 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "or.b", 40,
17685 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17687 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
17689 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "or.b", 40,
17690 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17692 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
17694 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "or.b", 40,
17695 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17697 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
17699 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "or.b", 48,
17700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17702 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
17704 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "or.b", 48,
17705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17707 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
17709 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "or.b", 48,
17710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17712 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
17714 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "or.b", 48,
17715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17717 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
17719 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "or.b", 56,
17720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17722 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
17724 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "or.b", 56,
17725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17727 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
17729 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "or.b", 56,
17730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17732 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
17734 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "or.b", 56,
17735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17737 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
17739 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "or.b", 40,
17740 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17742 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
17744 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "or.b", 40,
17745 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17747 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
17749 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "or.b", 40,
17750 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17752 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
17754 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "or.b", 40,
17755 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17757 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
17759 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "or.b", 48,
17760 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17762 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
17764 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "or.b", 48,
17765 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17767 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
17769 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "or.b", 48,
17770 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17772 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
17774 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "or.b", 48,
17775 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17777 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
17779 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "or.b", 40,
17780 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17782 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
17784 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "or.b", 40,
17785 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17787 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
17789 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "or.b", 40,
17790 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17792 /* or.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
17794 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "or.b", 40,
17795 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17797 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
17799 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "or.b", 48,
17800 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17802 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
17804 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "or.b", 48,
17805 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17807 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
17809 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "or.b", 48,
17810 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17812 /* or.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
17814 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "or.b", 48,
17815 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17817 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
17819 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "or.b", 48,
17820 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17822 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
17824 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "or.b", 48,
17825 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17827 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
17829 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "or.b", 48,
17830 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17832 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
17834 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "or.b", 48,
17835 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17837 /* or.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
17839 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "or.b", 56,
17840 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17842 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
17844 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "or.b", 56,
17845 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17847 /* or.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
17849 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "or.b", 56,
17850 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17852 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
17854 M32C_INSN_OR32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "or.b", 56,
17855 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17857 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
17859 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 40,
17860 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17862 /* or.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
17864 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 40,
17865 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17867 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
17869 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 40,
17870 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17872 /* or.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
17874 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 40,
17875 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17877 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
17879 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 40,
17880 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17882 /* or.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
17884 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 40,
17885 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17887 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
17889 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "or.b", 48,
17890 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17892 /* or.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
17894 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "or.b", 48,
17895 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17897 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
17899 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "or.b", 56,
17900 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17902 /* or.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
17904 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "or.b", 56,
17905 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17907 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
17909 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "or.b", 64,
17910 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17912 /* or.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
17914 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "or.b", 64,
17915 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17917 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
17919 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "or.b", 48,
17920 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17922 /* or.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
17924 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "or.b", 48,
17925 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17927 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
17929 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "or.b", 56,
17930 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17932 /* or.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
17934 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "or.b", 56,
17935 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17937 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
17939 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "or.b", 48,
17940 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17942 /* or.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
17944 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "or.b", 48,
17945 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17947 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
17949 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "or.b", 56,
17950 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17952 /* or.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
17954 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "or.b", 56,
17955 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17957 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
17959 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "or.b", 56,
17960 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17962 /* or.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
17964 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "or.b", 56,
17965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17967 /* or.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
17969 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "or.b", 64,
17970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17972 /* or.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
17974 M32C_INSN_OR32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "or.b", 64,
17975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17977 /* or.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
17979 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 16,
17980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17982 /* or.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
17984 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 16,
17985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17987 /* or.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
17989 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "or.b", 16,
17990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17992 /* or.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
17994 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 16,
17995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
17997 /* or.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
17999 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 16,
18000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18002 /* or.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
18004 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "or.b", 16,
18005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18007 /* or.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
18009 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 16,
18010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18012 /* or.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
18014 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 16,
18015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18017 /* or.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
18019 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "or.b", 16,
18020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18022 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
18024 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "or.b", 24,
18025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18027 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
18029 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "or.b", 24,
18030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18032 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
18034 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "or.b", 24,
18035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18037 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
18039 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "or.b", 32,
18040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18042 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
18044 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "or.b", 32,
18045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18047 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
18049 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "or.b", 32,
18050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18052 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
18054 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "or.b", 40,
18055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18057 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
18059 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "or.b", 40,
18060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18062 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
18064 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "or.b", 40,
18065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18067 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
18069 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "or.b", 24,
18070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18072 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
18074 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "or.b", 24,
18075 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18077 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
18079 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "or.b", 24,
18080 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18082 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
18084 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "or.b", 32,
18085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18087 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
18089 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "or.b", 32,
18090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18092 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
18094 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "or.b", 32,
18095 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18097 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
18099 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "or.b", 24,
18100 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18102 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
18104 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "or.b", 24,
18105 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18107 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
18109 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "or.b", 24,
18110 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18112 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
18114 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "or.b", 32,
18115 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18117 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
18119 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "or.b", 32,
18120 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18122 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
18124 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "or.b", 32,
18125 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18127 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
18129 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "or.b", 32,
18130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18132 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
18134 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "or.b", 32,
18135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18137 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
18139 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "or.b", 32,
18140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18142 /* or.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
18144 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "or.b", 40,
18145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18147 /* or.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
18149 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "or.b", 40,
18150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18152 /* or.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
18154 M32C_INSN_OR32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "or.b", 40,
18155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18157 /* or.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
18159 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "or.w", 24,
18160 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18162 /* or.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
18164 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "or.w", 24,
18165 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18167 /* or.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
18169 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "or.w", 24,
18170 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18172 /* or.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
18174 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "or.w", 24,
18175 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18177 /* or.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
18179 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "or.w", 24,
18180 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18182 /* or.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
18184 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "or.w", 24,
18185 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18187 /* or.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
18189 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "or.w", 24,
18190 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18192 /* or.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
18194 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "or.w", 24,
18195 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18197 /* or.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
18199 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "or.w", 24,
18200 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18202 /* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
18204 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "or.w", 32,
18205 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18207 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
18209 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "or.w", 32,
18210 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18212 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
18214 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "or.w", 32,
18215 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18217 /* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
18219 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "or.w", 40,
18220 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18222 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
18224 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "or.w", 40,
18225 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18227 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
18229 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "or.w", 40,
18230 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18232 /* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
18234 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "or.w", 32,
18235 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18237 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
18239 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "or.w", 32,
18240 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18242 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
18244 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "or.w", 32,
18245 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18247 /* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
18249 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "or.w", 40,
18250 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18252 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
18254 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "or.w", 40,
18255 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18257 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
18259 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "or.w", 40,
18260 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18262 /* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
18264 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "or.w", 32,
18265 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18267 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
18269 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "or.w", 32,
18270 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18272 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
18274 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "or.w", 32,
18275 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18277 /* or.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
18279 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "or16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "or.w", 40,
18280 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18282 /* or.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
18284 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "or16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "or.w", 40,
18285 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18287 /* or.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
18289 M32C_INSN_OR16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "or16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "or.w", 40,
18290 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18292 /* or.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
18294 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "or.w", 32,
18295 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18297 /* or.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
18299 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "or.w", 32,
18300 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18302 /* or.w${G} ${Dsp-16-u16},$Dst16RnHI */
18304 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "or.w", 32,
18305 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18307 /* or.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
18309 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "or.w", 32,
18310 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18312 /* or.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
18314 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "or.w", 32,
18315 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18317 /* or.w${G} ${Dsp-16-u16},$Dst16AnHI */
18319 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "or.w", 32,
18320 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18322 /* or.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
18324 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "or.w", 32,
18325 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18327 /* or.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
18329 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "or.w", 32,
18330 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18332 /* or.w${G} ${Dsp-16-u16},[$Dst16An] */
18334 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "or.w", 32,
18335 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18337 /* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
18339 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "or.w", 40,
18340 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18342 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
18344 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "or.w", 40,
18345 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18347 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
18349 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "or.w", 40,
18350 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18352 /* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
18354 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "or.w", 48,
18355 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18357 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
18359 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "or.w", 48,
18360 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18362 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
18364 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "or.w", 48,
18365 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18367 /* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
18369 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "or.w", 40,
18370 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18372 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
18374 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "or.w", 40,
18375 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18377 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
18379 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "or.w", 40,
18380 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18382 /* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
18384 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "or.w", 48,
18385 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18387 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
18389 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "or.w", 48,
18390 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18392 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
18394 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "or.w", 48,
18395 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18397 /* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
18399 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "or.w", 40,
18400 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18402 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
18404 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "or.w", 40,
18405 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18407 /* or.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
18409 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "or.w", 40,
18410 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18412 /* or.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
18414 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "or16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "or.w", 48,
18415 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18417 /* or.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
18419 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "or16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "or.w", 48,
18420 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18422 /* or.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
18424 M32C_INSN_OR16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "or16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "or.w", 48,
18425 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18427 /* or.w${G} $Src16RnHI,$Dst16RnHI */
18429 M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "or.w", 16,
18430 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18432 /* or.w${G} $Src16AnHI,$Dst16RnHI */
18434 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "or.w", 16,
18435 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18437 /* or.w${G} [$Src16An],$Dst16RnHI */
18439 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "or.w", 16,
18440 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18442 /* or.w${G} $Src16RnHI,$Dst16AnHI */
18444 M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "or.w", 16,
18445 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18447 /* or.w${G} $Src16AnHI,$Dst16AnHI */
18449 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "or.w", 16,
18450 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18452 /* or.w${G} [$Src16An],$Dst16AnHI */
18454 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "or.w", 16,
18455 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18457 /* or.w${G} $Src16RnHI,[$Dst16An] */
18459 M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "or.w", 16,
18460 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18462 /* or.w${G} $Src16AnHI,[$Dst16An] */
18464 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "or.w", 16,
18465 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18467 /* or.w${G} [$Src16An],[$Dst16An] */
18469 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "or.w", 16,
18470 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18472 /* or.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
18474 M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "or.w", 24,
18475 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18477 /* or.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
18479 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "or.w", 24,
18480 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18482 /* or.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
18484 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "or.w", 24,
18485 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18487 /* or.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
18489 M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "or.w", 32,
18490 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18492 /* or.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
18494 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "or.w", 32,
18495 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18497 /* or.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
18499 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "or.w", 32,
18500 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18502 /* or.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
18504 M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "or.w", 24,
18505 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18507 /* or.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
18509 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "or.w", 24,
18510 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18512 /* or.w${G} [$Src16An],${Dsp-16-u8}[sb] */
18514 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "or.w", 24,
18515 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18517 /* or.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
18519 M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "or.w", 32,
18520 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18522 /* or.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
18524 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "or.w", 32,
18525 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18527 /* or.w${G} [$Src16An],${Dsp-16-u16}[sb] */
18529 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "or.w", 32,
18530 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18532 /* or.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
18534 M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "or.w", 24,
18535 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18537 /* or.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
18539 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "or.w", 24,
18540 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18542 /* or.w${G} [$Src16An],${Dsp-16-s8}[fb] */
18544 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "or.w", 24,
18545 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18547 /* or.w${G} $Src16RnHI,${Dsp-16-u16} */
18549 M32C_INSN_OR16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "or16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "or.w", 32,
18550 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18552 /* or.w${G} $Src16AnHI,${Dsp-16-u16} */
18554 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "or16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "or.w", 32,
18555 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18557 /* or.w${G} [$Src16An],${Dsp-16-u16} */
18559 M32C_INSN_OR16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "or16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "or.w", 32,
18560 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18562 /* or.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
18564 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "or.b", 24,
18565 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18567 /* or.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
18569 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "or.b", 24,
18570 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18572 /* or.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
18574 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "or.b", 24,
18575 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18577 /* or.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
18579 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "or.b", 24,
18580 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18582 /* or.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
18584 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "or.b", 24,
18585 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18587 /* or.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
18589 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "or.b", 24,
18590 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18592 /* or.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
18594 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "or.b", 24,
18595 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18597 /* or.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
18599 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "or.b", 24,
18600 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18602 /* or.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
18604 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "or.b", 24,
18605 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18607 /* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
18609 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "or.b", 32,
18610 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18612 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
18614 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "or.b", 32,
18615 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18617 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
18619 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "or.b", 32,
18620 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18622 /* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
18624 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "or.b", 40,
18625 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18627 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
18629 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "or.b", 40,
18630 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18632 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
18634 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "or.b", 40,
18635 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18637 /* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
18639 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "or.b", 32,
18640 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18642 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
18644 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "or.b", 32,
18645 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18647 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
18649 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "or.b", 32,
18650 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18652 /* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
18654 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "or.b", 40,
18655 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18657 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
18659 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "or.b", 40,
18660 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18662 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
18664 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "or.b", 40,
18665 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18667 /* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
18669 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "or.b", 32,
18670 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18672 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
18674 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "or.b", 32,
18675 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18677 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
18679 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "or.b", 32,
18680 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18682 /* or.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
18684 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "or16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "or.b", 40,
18685 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18687 /* or.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
18689 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "or16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "or.b", 40,
18690 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18692 /* or.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
18694 M32C_INSN_OR16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "or16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "or.b", 40,
18695 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18697 /* or.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
18699 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "or.b", 32,
18700 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18702 /* or.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
18704 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "or.b", 32,
18705 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18707 /* or.b${G} ${Dsp-16-u16},$Dst16RnQI */
18709 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "or.b", 32,
18710 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18712 /* or.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
18714 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "or.b", 32,
18715 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18717 /* or.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
18719 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "or.b", 32,
18720 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18722 /* or.b${G} ${Dsp-16-u16},$Dst16AnQI */
18724 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "or.b", 32,
18725 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18727 /* or.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
18729 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "or.b", 32,
18730 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18732 /* or.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
18734 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "or.b", 32,
18735 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18737 /* or.b${G} ${Dsp-16-u16},[$Dst16An] */
18739 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "or.b", 32,
18740 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18742 /* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
18744 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "or.b", 40,
18745 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18747 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
18749 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "or.b", 40,
18750 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18752 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
18754 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "or.b", 40,
18755 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18757 /* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
18759 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "or.b", 48,
18760 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18762 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
18764 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "or.b", 48,
18765 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18767 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
18769 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "or.b", 48,
18770 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18772 /* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
18774 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "or.b", 40,
18775 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18777 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
18779 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "or.b", 40,
18780 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18782 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
18784 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "or.b", 40,
18785 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18787 /* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
18789 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "or.b", 48,
18790 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18792 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
18794 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "or.b", 48,
18795 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18797 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
18799 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "or.b", 48,
18800 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18802 /* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
18804 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "or.b", 40,
18805 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18807 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
18809 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "or.b", 40,
18810 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18812 /* or.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
18814 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "or.b", 40,
18815 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18817 /* or.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
18819 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "or16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "or.b", 48,
18820 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18822 /* or.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
18824 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "or16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "or.b", 48,
18825 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18827 /* or.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
18829 M32C_INSN_OR16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "or16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "or.b", 48,
18830 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18832 /* or.b${G} $Src16RnQI,$Dst16RnQI */
18834 M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "or.b", 16,
18835 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18837 /* or.b${G} $Src16AnQI,$Dst16RnQI */
18839 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "or.b", 16,
18840 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18842 /* or.b${G} [$Src16An],$Dst16RnQI */
18844 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "or.b", 16,
18845 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18847 /* or.b${G} $Src16RnQI,$Dst16AnQI */
18849 M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "or.b", 16,
18850 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18852 /* or.b${G} $Src16AnQI,$Dst16AnQI */
18854 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "or.b", 16,
18855 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18857 /* or.b${G} [$Src16An],$Dst16AnQI */
18859 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "or.b", 16,
18860 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18862 /* or.b${G} $Src16RnQI,[$Dst16An] */
18864 M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "or.b", 16,
18865 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18867 /* or.b${G} $Src16AnQI,[$Dst16An] */
18869 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "or.b", 16,
18870 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18872 /* or.b${G} [$Src16An],[$Dst16An] */
18874 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "or.b", 16,
18875 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18877 /* or.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
18879 M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "or.b", 24,
18880 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18882 /* or.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
18884 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "or.b", 24,
18885 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18887 /* or.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
18889 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "or.b", 24,
18890 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18892 /* or.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
18894 M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "or.b", 32,
18895 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18897 /* or.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
18899 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "or.b", 32,
18900 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18902 /* or.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
18904 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "or.b", 32,
18905 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18907 /* or.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
18909 M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "or.b", 24,
18910 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18912 /* or.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
18914 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "or.b", 24,
18915 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18917 /* or.b${G} [$Src16An],${Dsp-16-u8}[sb] */
18919 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "or.b", 24,
18920 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18922 /* or.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
18924 M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "or.b", 32,
18925 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18927 /* or.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
18929 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "or.b", 32,
18930 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18932 /* or.b${G} [$Src16An],${Dsp-16-u16}[sb] */
18934 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "or.b", 32,
18935 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18937 /* or.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
18939 M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "or.b", 24,
18940 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18942 /* or.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
18944 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "or.b", 24,
18945 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18947 /* or.b${G} [$Src16An],${Dsp-16-s8}[fb] */
18949 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "or.b", 24,
18950 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18952 /* or.b${G} $Src16RnQI,${Dsp-16-u16} */
18954 M32C_INSN_OR16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "or16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "or.b", 32,
18955 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18957 /* or.b${G} $Src16AnQI,${Dsp-16-u16} */
18959 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "or16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "or.b", 32,
18960 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18962 /* or.b${G} [$Src16An],${Dsp-16-u16} */
18964 M32C_INSN_OR16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "or16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "or.b", 32,
18965 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
18967 /* or.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
18969 M32C_INSN_OR32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "or32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "or.w", 32,
18970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18972 /* or.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
18974 M32C_INSN_OR32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "or32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "or.w", 32,
18975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18977 /* or.w${S} #${Imm-24-HI},${Dsp-8-u16} */
18979 M32C_INSN_OR32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "or32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "or.w", 40,
18980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18982 /* or.w${S} #${Imm-8-HI},r0 */
18984 M32C_INSN_OR32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "or32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "or.w", 24,
18985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18987 /* or.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
18989 M32C_INSN_OR32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "or32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "or.b", 24,
18990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18992 /* or.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
18994 M32C_INSN_OR32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "or32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "or.b", 24,
18995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
18997 /* or.b${S} #${Imm-24-QI},${Dsp-8-u16} */
18999 M32C_INSN_OR32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "or32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "or.b", 32,
19000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19002 /* or.b${S} #${Imm-8-QI},r0l */
19004 M32C_INSN_OR32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "or32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "or.b", 16,
19005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19007 /* or.b${S} #${Imm-8-QI},r0l */
19009 M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "or16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "or.b", 16,
19010 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19012 /* or.b${S} #${Imm-8-QI},r0h */
19014 M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "or16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "or.b", 16,
19015 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19017 /* or.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
19019 M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "or16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "or.b", 24,
19020 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19022 /* or.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
19024 M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "or16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "or.b", 24,
19025 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19027 /* or.b${S} #${Imm-8-QI},${Dsp-16-u16} */
19029 M32C_INSN_OR16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "or16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "or.b", 32,
19030 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19032 /* or.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
19034 M32C_INSN_OR32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "or32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "or.w", 32,
19035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19037 /* or.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
19039 M32C_INSN_OR32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "or32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "or.w", 32,
19040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19042 /* or.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
19044 M32C_INSN_OR32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "or32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "or.w", 32,
19045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19047 /* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
19049 M32C_INSN_OR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "or.w", 40,
19050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19052 /* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
19054 M32C_INSN_OR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "or.w", 40,
19055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19057 /* or.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
19059 M32C_INSN_OR32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "or.w", 40,
19060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19062 /* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
19064 M32C_INSN_OR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "or.w", 48,
19065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19067 /* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
19069 M32C_INSN_OR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "or.w", 48,
19070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19072 /* or.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
19074 M32C_INSN_OR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "or.w", 48,
19075 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19077 /* or.w${G} #${Imm-32-HI},${Dsp-16-u16} */
19079 M32C_INSN_OR32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "or32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "or.w", 48,
19080 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19082 /* or.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
19084 M32C_INSN_OR32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "or32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "or.w", 56,
19085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19087 /* or.w${G} #${Imm-40-HI},${Dsp-16-u24} */
19089 M32C_INSN_OR32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "or32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "or.w", 56,
19090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19092 /* or.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
19094 M32C_INSN_OR32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "or32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "or.b", 24,
19095 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19097 /* or.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
19099 M32C_INSN_OR32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "or32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "or.b", 24,
19100 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19102 /* or.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
19104 M32C_INSN_OR32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "or32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "or.b", 24,
19105 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19107 /* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
19109 M32C_INSN_OR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "or.b", 32,
19110 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19112 /* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
19114 M32C_INSN_OR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "or.b", 32,
19115 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19117 /* or.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
19119 M32C_INSN_OR32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "or.b", 32,
19120 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19122 /* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
19124 M32C_INSN_OR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "or.b", 40,
19125 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19127 /* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
19129 M32C_INSN_OR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "or.b", 40,
19130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19132 /* or.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
19134 M32C_INSN_OR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "or.b", 40,
19135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19137 /* or.b${G} #${Imm-32-QI},${Dsp-16-u16} */
19139 M32C_INSN_OR32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "or32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "or.b", 40,
19140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19142 /* or.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
19144 M32C_INSN_OR32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "or32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "or.b", 48,
19145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19147 /* or.b${G} #${Imm-40-QI},${Dsp-16-u24} */
19149 M32C_INSN_OR32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "or32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "or.b", 48,
19150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19152 /* or.w${G} #${Imm-16-HI},$Dst16RnHI */
19154 M32C_INSN_OR16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "or16.w-imm-G-basic-dst16-Rn-direct-HI", "or.w", 32,
19155 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19157 /* or.w${G} #${Imm-16-HI},$Dst16AnHI */
19159 M32C_INSN_OR16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "or16.w-imm-G-basic-dst16-An-direct-HI", "or.w", 32,
19160 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19162 /* or.w${G} #${Imm-16-HI},[$Dst16An] */
19164 M32C_INSN_OR16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "or16.w-imm-G-basic-dst16-An-indirect-HI", "or.w", 32,
19165 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19167 /* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
19169 M32C_INSN_OR16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "or16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "or.w", 40,
19170 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19172 /* or.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
19174 M32C_INSN_OR16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "or16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "or.w", 40,
19175 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19177 /* or.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
19179 M32C_INSN_OR16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "or16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "or.w", 40,
19180 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19182 /* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
19184 M32C_INSN_OR16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "or16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "or.w", 48,
19185 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19187 /* or.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
19189 M32C_INSN_OR16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "or16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "or.w", 48,
19190 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19192 /* or.w${G} #${Imm-32-HI},${Dsp-16-u16} */
19194 M32C_INSN_OR16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "or16.w-imm-G-16-16-dst16-16-16-absolute-HI", "or.w", 48,
19195 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19197 /* or.b${G} #${Imm-16-QI},$Dst16RnQI */
19199 M32C_INSN_OR16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "or16.b-imm-G-basic-dst16-Rn-direct-QI", "or.b", 24,
19200 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19202 /* or.b${G} #${Imm-16-QI},$Dst16AnQI */
19204 M32C_INSN_OR16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "or16.b-imm-G-basic-dst16-An-direct-QI", "or.b", 24,
19205 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19207 /* or.b${G} #${Imm-16-QI},[$Dst16An] */
19209 M32C_INSN_OR16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "or16.b-imm-G-basic-dst16-An-indirect-QI", "or.b", 24,
19210 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19212 /* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
19214 M32C_INSN_OR16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "or16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "or.b", 32,
19215 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19217 /* or.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
19219 M32C_INSN_OR16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "or16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "or.b", 32,
19220 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19222 /* or.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
19224 M32C_INSN_OR16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "or16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "or.b", 32,
19225 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19227 /* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
19229 M32C_INSN_OR16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "or16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "or.b", 40,
19230 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19232 /* or.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
19234 M32C_INSN_OR16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "or16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "or.b", 40,
19235 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19237 /* or.b${G} #${Imm-32-QI},${Dsp-16-u16} */
19239 M32C_INSN_OR16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "or16.b-imm-G-16-16-dst16-16-16-absolute-QI", "or.b", 40,
19240 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19242 /* not.w $Dst32RnUnprefixedHI */
19244 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "not.w", 16,
19245 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19247 /* not.w $Dst32AnUnprefixedHI */
19249 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "not.w", 16,
19250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19252 /* not.w [$Dst32AnUnprefixed] */
19254 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "not.w", 16,
19255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19257 /* not.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
19259 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "not.w", 24,
19260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19262 /* not.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
19264 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "not.w", 32,
19265 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19267 /* not.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
19269 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "not.w", 40,
19270 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19272 /* not.w ${Dsp-16-u8}[sb] */
19274 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "not.w", 24,
19275 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19277 /* not.w ${Dsp-16-u16}[sb] */
19279 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "not.w", 32,
19280 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19282 /* not.w ${Dsp-16-s8}[fb] */
19284 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "not.w", 24,
19285 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19287 /* not.w ${Dsp-16-s16}[fb] */
19289 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "not.w", 32,
19290 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19292 /* not.w ${Dsp-16-u16} */
19294 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "not.w", 32,
19295 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19297 /* not.w ${Dsp-16-u24} */
19299 M32C_INSN_NOT32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "not32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "not.w", 40,
19300 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19302 /* not.b $Dst32RnUnprefixedQI */
19304 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "not.b", 16,
19305 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19307 /* not.b $Dst32AnUnprefixedQI */
19309 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "not.b", 16,
19310 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19312 /* not.b [$Dst32AnUnprefixed] */
19314 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "not.b", 16,
19315 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19317 /* not.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
19319 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "not.b", 24,
19320 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19322 /* not.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
19324 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "not.b", 32,
19325 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19327 /* not.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
19329 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "not.b", 40,
19330 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19332 /* not.b ${Dsp-16-u8}[sb] */
19334 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "not.b", 24,
19335 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19337 /* not.b ${Dsp-16-u16}[sb] */
19339 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "not.b", 32,
19340 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19342 /* not.b ${Dsp-16-s8}[fb] */
19344 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "not.b", 24,
19345 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19347 /* not.b ${Dsp-16-s16}[fb] */
19349 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "not.b", 32,
19350 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19352 /* not.b ${Dsp-16-u16} */
19354 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "not.b", 32,
19355 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19357 /* not.b ${Dsp-16-u24} */
19359 M32C_INSN_NOT32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "not32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "not.b", 40,
19360 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19362 /* not.w $Dst16RnHI */
19364 M32C_INSN_NOT16_W_16_DST16_RN_DIRECT_HI, "not16.w-16-dst16-Rn-direct-HI", "not.w", 16,
19365 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19367 /* not.w $Dst16AnHI */
19369 M32C_INSN_NOT16_W_16_DST16_AN_DIRECT_HI, "not16.w-16-dst16-An-direct-HI", "not.w", 16,
19370 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19372 /* not.w [$Dst16An] */
19374 M32C_INSN_NOT16_W_16_DST16_AN_INDIRECT_HI, "not16.w-16-dst16-An-indirect-HI", "not.w", 16,
19375 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19377 /* not.w ${Dsp-16-u8}[$Dst16An] */
19379 M32C_INSN_NOT16_W_16_DST16_16_8_AN_RELATIVE_HI, "not16.w-16-dst16-16-8-An-relative-HI", "not.w", 24,
19380 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19382 /* not.w ${Dsp-16-u16}[$Dst16An] */
19384 M32C_INSN_NOT16_W_16_DST16_16_16_AN_RELATIVE_HI, "not16.w-16-dst16-16-16-An-relative-HI", "not.w", 32,
19385 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19387 /* not.w ${Dsp-16-u8}[sb] */
19389 M32C_INSN_NOT16_W_16_DST16_16_8_SB_RELATIVE_HI, "not16.w-16-dst16-16-8-SB-relative-HI", "not.w", 24,
19390 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19392 /* not.w ${Dsp-16-u16}[sb] */
19394 M32C_INSN_NOT16_W_16_DST16_16_16_SB_RELATIVE_HI, "not16.w-16-dst16-16-16-SB-relative-HI", "not.w", 32,
19395 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19397 /* not.w ${Dsp-16-s8}[fb] */
19399 M32C_INSN_NOT16_W_16_DST16_16_8_FB_RELATIVE_HI, "not16.w-16-dst16-16-8-FB-relative-HI", "not.w", 24,
19400 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19402 /* not.w ${Dsp-16-u16} */
19404 M32C_INSN_NOT16_W_16_DST16_16_16_ABSOLUTE_HI, "not16.w-16-dst16-16-16-absolute-HI", "not.w", 32,
19405 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19407 /* not.b $Dst16RnQI */
19409 M32C_INSN_NOT16_B_16_DST16_RN_DIRECT_QI, "not16.b-16-dst16-Rn-direct-QI", "not.b", 16,
19410 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19412 /* not.b $Dst16AnQI */
19414 M32C_INSN_NOT16_B_16_DST16_AN_DIRECT_QI, "not16.b-16-dst16-An-direct-QI", "not.b", 16,
19415 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19417 /* not.b [$Dst16An] */
19419 M32C_INSN_NOT16_B_16_DST16_AN_INDIRECT_QI, "not16.b-16-dst16-An-indirect-QI", "not.b", 16,
19420 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19422 /* not.b ${Dsp-16-u8}[$Dst16An] */
19424 M32C_INSN_NOT16_B_16_DST16_16_8_AN_RELATIVE_QI, "not16.b-16-dst16-16-8-An-relative-QI", "not.b", 24,
19425 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19427 /* not.b ${Dsp-16-u16}[$Dst16An] */
19429 M32C_INSN_NOT16_B_16_DST16_16_16_AN_RELATIVE_QI, "not16.b-16-dst16-16-16-An-relative-QI", "not.b", 32,
19430 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19432 /* not.b ${Dsp-16-u8}[sb] */
19434 M32C_INSN_NOT16_B_16_DST16_16_8_SB_RELATIVE_QI, "not16.b-16-dst16-16-8-SB-relative-QI", "not.b", 24,
19435 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19437 /* not.b ${Dsp-16-u16}[sb] */
19439 M32C_INSN_NOT16_B_16_DST16_16_16_SB_RELATIVE_QI, "not16.b-16-dst16-16-16-SB-relative-QI", "not.b", 32,
19440 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19442 /* not.b ${Dsp-16-s8}[fb] */
19444 M32C_INSN_NOT16_B_16_DST16_16_8_FB_RELATIVE_QI, "not16.b-16-dst16-16-8-FB-relative-QI", "not.b", 24,
19445 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19447 /* not.b ${Dsp-16-u16} */
19449 M32C_INSN_NOT16_B_16_DST16_16_16_ABSOLUTE_QI, "not16.b-16-dst16-16-16-absolute-QI", "not.b", 32,
19450 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19452 /* neg.w $Dst32RnUnprefixedHI */
19454 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "neg.w", 16,
19455 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19457 /* neg.w $Dst32AnUnprefixedHI */
19459 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "neg.w", 16,
19460 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19462 /* neg.w [$Dst32AnUnprefixed] */
19464 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "neg.w", 16,
19465 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19467 /* neg.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
19469 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "neg.w", 24,
19470 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19472 /* neg.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
19474 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "neg.w", 32,
19475 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19477 /* neg.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
19479 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "neg.w", 40,
19480 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19482 /* neg.w ${Dsp-16-u8}[sb] */
19484 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "neg.w", 24,
19485 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19487 /* neg.w ${Dsp-16-u16}[sb] */
19489 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "neg.w", 32,
19490 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19492 /* neg.w ${Dsp-16-s8}[fb] */
19494 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "neg.w", 24,
19495 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19497 /* neg.w ${Dsp-16-s16}[fb] */
19499 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "neg.w", 32,
19500 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19502 /* neg.w ${Dsp-16-u16} */
19504 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "neg.w", 32,
19505 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19507 /* neg.w ${Dsp-16-u24} */
19509 M32C_INSN_NEG32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "neg32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "neg.w", 40,
19510 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19512 /* neg.b $Dst32RnUnprefixedQI */
19514 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "neg.b", 16,
19515 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19517 /* neg.b $Dst32AnUnprefixedQI */
19519 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "neg.b", 16,
19520 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19522 /* neg.b [$Dst32AnUnprefixed] */
19524 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "neg.b", 16,
19525 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19527 /* neg.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
19529 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "neg.b", 24,
19530 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19532 /* neg.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
19534 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "neg.b", 32,
19535 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19537 /* neg.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
19539 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "neg.b", 40,
19540 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19542 /* neg.b ${Dsp-16-u8}[sb] */
19544 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "neg.b", 24,
19545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19547 /* neg.b ${Dsp-16-u16}[sb] */
19549 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "neg.b", 32,
19550 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19552 /* neg.b ${Dsp-16-s8}[fb] */
19554 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "neg.b", 24,
19555 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19557 /* neg.b ${Dsp-16-s16}[fb] */
19559 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "neg.b", 32,
19560 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19562 /* neg.b ${Dsp-16-u16} */
19564 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "neg.b", 32,
19565 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19567 /* neg.b ${Dsp-16-u24} */
19569 M32C_INSN_NEG32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "neg32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "neg.b", 40,
19570 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19572 /* neg.w $Dst16RnHI */
19574 M32C_INSN_NEG16_W_16_DST16_RN_DIRECT_HI, "neg16.w-16-dst16-Rn-direct-HI", "neg.w", 16,
19575 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19577 /* neg.w $Dst16AnHI */
19579 M32C_INSN_NEG16_W_16_DST16_AN_DIRECT_HI, "neg16.w-16-dst16-An-direct-HI", "neg.w", 16,
19580 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19582 /* neg.w [$Dst16An] */
19584 M32C_INSN_NEG16_W_16_DST16_AN_INDIRECT_HI, "neg16.w-16-dst16-An-indirect-HI", "neg.w", 16,
19585 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19587 /* neg.w ${Dsp-16-u8}[$Dst16An] */
19589 M32C_INSN_NEG16_W_16_DST16_16_8_AN_RELATIVE_HI, "neg16.w-16-dst16-16-8-An-relative-HI", "neg.w", 24,
19590 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19592 /* neg.w ${Dsp-16-u16}[$Dst16An] */
19594 M32C_INSN_NEG16_W_16_DST16_16_16_AN_RELATIVE_HI, "neg16.w-16-dst16-16-16-An-relative-HI", "neg.w", 32,
19595 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19597 /* neg.w ${Dsp-16-u8}[sb] */
19599 M32C_INSN_NEG16_W_16_DST16_16_8_SB_RELATIVE_HI, "neg16.w-16-dst16-16-8-SB-relative-HI", "neg.w", 24,
19600 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19602 /* neg.w ${Dsp-16-u16}[sb] */
19604 M32C_INSN_NEG16_W_16_DST16_16_16_SB_RELATIVE_HI, "neg16.w-16-dst16-16-16-SB-relative-HI", "neg.w", 32,
19605 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19607 /* neg.w ${Dsp-16-s8}[fb] */
19609 M32C_INSN_NEG16_W_16_DST16_16_8_FB_RELATIVE_HI, "neg16.w-16-dst16-16-8-FB-relative-HI", "neg.w", 24,
19610 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19612 /* neg.w ${Dsp-16-u16} */
19614 M32C_INSN_NEG16_W_16_DST16_16_16_ABSOLUTE_HI, "neg16.w-16-dst16-16-16-absolute-HI", "neg.w", 32,
19615 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19617 /* neg.b $Dst16RnQI */
19619 M32C_INSN_NEG16_B_16_DST16_RN_DIRECT_QI, "neg16.b-16-dst16-Rn-direct-QI", "neg.b", 16,
19620 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19622 /* neg.b $Dst16AnQI */
19624 M32C_INSN_NEG16_B_16_DST16_AN_DIRECT_QI, "neg16.b-16-dst16-An-direct-QI", "neg.b", 16,
19625 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19627 /* neg.b [$Dst16An] */
19629 M32C_INSN_NEG16_B_16_DST16_AN_INDIRECT_QI, "neg16.b-16-dst16-An-indirect-QI", "neg.b", 16,
19630 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19632 /* neg.b ${Dsp-16-u8}[$Dst16An] */
19634 M32C_INSN_NEG16_B_16_DST16_16_8_AN_RELATIVE_QI, "neg16.b-16-dst16-16-8-An-relative-QI", "neg.b", 24,
19635 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19637 /* neg.b ${Dsp-16-u16}[$Dst16An] */
19639 M32C_INSN_NEG16_B_16_DST16_16_16_AN_RELATIVE_QI, "neg16.b-16-dst16-16-16-An-relative-QI", "neg.b", 32,
19640 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19642 /* neg.b ${Dsp-16-u8}[sb] */
19644 M32C_INSN_NEG16_B_16_DST16_16_8_SB_RELATIVE_QI, "neg16.b-16-dst16-16-8-SB-relative-QI", "neg.b", 24,
19645 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19647 /* neg.b ${Dsp-16-u16}[sb] */
19649 M32C_INSN_NEG16_B_16_DST16_16_16_SB_RELATIVE_QI, "neg16.b-16-dst16-16-16-SB-relative-QI", "neg.b", 32,
19650 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19652 /* neg.b ${Dsp-16-s8}[fb] */
19654 M32C_INSN_NEG16_B_16_DST16_16_8_FB_RELATIVE_QI, "neg16.b-16-dst16-16-8-FB-relative-QI", "neg.b", 24,
19655 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19657 /* neg.b ${Dsp-16-u16} */
19659 M32C_INSN_NEG16_B_16_DST16_16_16_ABSOLUTE_QI, "neg16.b-16-dst16-16-16-absolute-QI", "neg.b", 32,
19660 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
19662 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
19664 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 24,
19665 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19667 /* mulu.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
19669 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 24,
19670 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19672 /* mulu.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
19674 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 24,
19675 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19677 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
19679 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 24,
19680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19682 /* mulu.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
19684 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 24,
19685 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19687 /* mulu.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
19689 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 24,
19690 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19692 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
19694 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 24,
19695 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19697 /* mulu.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
19699 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 24,
19700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19702 /* mulu.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
19704 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 24,
19705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19707 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
19709 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mulu.w", 32,
19710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19712 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
19714 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mulu.w", 32,
19715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19717 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
19719 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mulu.w", 32,
19720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19722 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
19724 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mulu.w", 40,
19725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19727 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
19729 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mulu.w", 40,
19730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19732 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
19734 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mulu.w", 40,
19735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19737 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
19739 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mulu.w", 48,
19740 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19742 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
19744 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mulu.w", 48,
19745 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19747 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
19749 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mulu.w", 48,
19750 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19752 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
19754 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mulu.w", 32,
19755 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19757 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
19759 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mulu.w", 32,
19760 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19762 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
19764 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mulu.w", 32,
19765 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19767 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
19769 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mulu.w", 40,
19770 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19772 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
19774 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mulu.w", 40,
19775 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19777 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
19779 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mulu.w", 40,
19780 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19782 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
19784 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mulu.w", 32,
19785 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19787 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
19789 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mulu.w", 32,
19790 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19792 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
19794 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mulu.w", 32,
19795 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19797 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
19799 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mulu.w", 40,
19800 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19802 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
19804 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mulu.w", 40,
19805 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19807 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
19809 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mulu.w", 40,
19810 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19812 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
19814 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mulu.w", 40,
19815 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19817 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
19819 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mulu.w", 40,
19820 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19822 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
19824 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mulu.w", 40,
19825 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19827 /* mulu.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
19829 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mulu.w", 48,
19830 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19832 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
19834 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mulu.w", 48,
19835 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19837 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
19839 M32C_INSN_MULU32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mulu.w", 48,
19840 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19842 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
19844 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32,
19845 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19847 /* mulu.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
19849 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32,
19850 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19852 /* mulu.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
19854 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32,
19855 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19857 /* mulu.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
19859 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32,
19860 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19862 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
19864 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 32,
19865 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19867 /* mulu.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
19869 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 32,
19870 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19872 /* mulu.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
19874 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 32,
19875 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19877 /* mulu.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
19879 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 32,
19880 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19882 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
19884 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32,
19885 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19887 /* mulu.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
19889 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32,
19890 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19892 /* mulu.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
19894 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32,
19895 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19897 /* mulu.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
19899 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32,
19900 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19902 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
19904 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mulu.w", 40,
19905 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19907 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
19909 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mulu.w", 40,
19910 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19912 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
19914 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mulu.w", 40,
19915 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19917 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
19919 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mulu.w", 40,
19920 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19922 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
19924 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mulu.w", 48,
19925 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19927 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
19929 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mulu.w", 48,
19930 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19932 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
19934 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mulu.w", 48,
19935 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19937 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
19939 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mulu.w", 48,
19940 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19942 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
19944 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mulu.w", 56,
19945 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19947 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
19949 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mulu.w", 56,
19950 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19952 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
19954 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mulu.w", 56,
19955 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19957 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
19959 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mulu.w", 56,
19960 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19962 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
19964 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mulu.w", 40,
19965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19967 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
19969 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mulu.w", 40,
19970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19972 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
19974 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mulu.w", 40,
19975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19977 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
19979 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mulu.w", 40,
19980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19982 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
19984 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mulu.w", 48,
19985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19987 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
19989 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mulu.w", 48,
19990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19992 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
19994 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mulu.w", 48,
19995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
19997 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
19999 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mulu.w", 48,
20000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20002 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
20004 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mulu.w", 40,
20005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20007 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
20009 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mulu.w", 40,
20010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20012 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
20014 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mulu.w", 40,
20015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20017 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
20019 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mulu.w", 40,
20020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20022 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
20024 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mulu.w", 48,
20025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20027 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
20029 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mulu.w", 48,
20030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20032 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
20034 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mulu.w", 48,
20035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20037 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
20039 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mulu.w", 48,
20040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20042 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
20044 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mulu.w", 48,
20045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20047 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
20049 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mulu.w", 48,
20050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20052 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
20054 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mulu.w", 48,
20055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20057 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
20059 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mulu.w", 48,
20060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20062 /* mulu.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
20064 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mulu.w", 56,
20065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20067 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
20069 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mulu.w", 56,
20070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20072 /* mulu.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
20074 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mulu.w", 56,
20075 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20077 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
20079 M32C_INSN_MULU32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mulu.w", 56,
20080 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20082 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
20084 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 40,
20085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20087 /* mulu.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
20089 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 40,
20090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20092 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
20094 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 40,
20095 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20097 /* mulu.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
20099 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 40,
20100 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20102 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
20104 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 40,
20105 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20107 /* mulu.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
20109 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 40,
20110 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20112 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
20114 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mulu.w", 48,
20115 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20117 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
20119 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mulu.w", 48,
20120 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20122 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
20124 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mulu.w", 56,
20125 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20127 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
20129 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mulu.w", 56,
20130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20132 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
20134 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mulu.w", 64,
20135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20137 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
20139 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mulu.w", 64,
20140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20142 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
20144 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mulu.w", 48,
20145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20147 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
20149 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mulu.w", 48,
20150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20152 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
20154 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mulu.w", 56,
20155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20157 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
20159 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mulu.w", 56,
20160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20162 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
20164 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mulu.w", 48,
20165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20167 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
20169 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mulu.w", 48,
20170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20172 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
20174 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mulu.w", 56,
20175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20177 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
20179 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mulu.w", 56,
20180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20182 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
20184 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mulu.w", 56,
20185 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20187 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
20189 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mulu.w", 56,
20190 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20192 /* mulu.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
20194 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mulu.w", 64,
20195 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20197 /* mulu.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
20199 M32C_INSN_MULU32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mulu.w", 64,
20200 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20202 /* mulu.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
20204 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 16,
20205 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20207 /* mulu.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
20209 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 16,
20210 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20212 /* mulu.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
20214 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 16,
20215 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20217 /* mulu.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
20219 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 16,
20220 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20222 /* mulu.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
20224 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 16,
20225 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20227 /* mulu.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
20229 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mulu.w", 16,
20230 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20232 /* mulu.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
20234 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 16,
20235 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20237 /* mulu.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
20239 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 16,
20240 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20242 /* mulu.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
20244 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mulu.w", 16,
20245 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20247 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
20249 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mulu.w", 24,
20250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20252 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
20254 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mulu.w", 24,
20255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20257 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
20259 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mulu.w", 24,
20260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20262 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
20264 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mulu.w", 32,
20265 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20267 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
20269 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mulu.w", 32,
20270 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20272 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
20274 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mulu.w", 32,
20275 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20277 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
20279 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mulu.w", 40,
20280 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20282 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
20284 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mulu.w", 40,
20285 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20287 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
20289 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mulu.w", 40,
20290 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20292 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
20294 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mulu.w", 24,
20295 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20297 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
20299 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mulu.w", 24,
20300 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20302 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
20304 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mulu.w", 24,
20305 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20307 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
20309 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mulu.w", 32,
20310 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20312 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
20314 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mulu.w", 32,
20315 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20317 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
20319 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mulu.w", 32,
20320 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20322 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
20324 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mulu.w", 24,
20325 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20327 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
20329 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mulu.w", 24,
20330 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20332 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
20334 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mulu.w", 24,
20335 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20337 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
20339 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mulu.w", 32,
20340 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20342 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
20344 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mulu.w", 32,
20345 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20347 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
20349 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mulu.w", 32,
20350 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20352 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
20354 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mulu.w", 32,
20355 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20357 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
20359 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mulu.w", 32,
20360 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20362 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
20364 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mulu.w", 32,
20365 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20367 /* mulu.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
20369 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mulu.w", 40,
20370 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20372 /* mulu.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
20374 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mulu.w", 40,
20375 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20377 /* mulu.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
20379 M32C_INSN_MULU32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mulu.w", 40,
20380 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20382 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
20384 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 24,
20385 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20387 /* mulu.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
20389 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 24,
20390 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20392 /* mulu.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
20394 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 24,
20395 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20397 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
20399 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 24,
20400 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20402 /* mulu.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
20404 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 24,
20405 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20407 /* mulu.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
20409 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 24,
20410 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20412 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
20414 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 24,
20415 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20417 /* mulu.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
20419 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 24,
20420 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20422 /* mulu.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
20424 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 24,
20425 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20427 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
20429 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mulu.b", 32,
20430 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20432 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
20434 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mulu.b", 32,
20435 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20437 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
20439 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mulu.b", 32,
20440 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20442 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
20444 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mulu.b", 40,
20445 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20447 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
20449 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mulu.b", 40,
20450 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20452 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
20454 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mulu.b", 40,
20455 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20457 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
20459 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mulu.b", 48,
20460 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20462 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
20464 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mulu.b", 48,
20465 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20467 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
20469 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mulu.b", 48,
20470 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20472 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
20474 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mulu.b", 32,
20475 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20477 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
20479 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mulu.b", 32,
20480 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20482 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
20484 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mulu.b", 32,
20485 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20487 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
20489 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mulu.b", 40,
20490 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20492 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
20494 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mulu.b", 40,
20495 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20497 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
20499 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mulu.b", 40,
20500 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20502 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
20504 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mulu.b", 32,
20505 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20507 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
20509 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mulu.b", 32,
20510 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20512 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
20514 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mulu.b", 32,
20515 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20517 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
20519 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mulu.b", 40,
20520 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20522 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
20524 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mulu.b", 40,
20525 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20527 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
20529 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mulu.b", 40,
20530 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20532 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
20534 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mulu.b", 40,
20535 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20537 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
20539 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mulu.b", 40,
20540 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20542 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
20544 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mulu.b", 40,
20545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20547 /* mulu.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
20549 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mulu.b", 48,
20550 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20552 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
20554 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mulu.b", 48,
20555 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20557 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
20559 M32C_INSN_MULU32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mulu.b", 48,
20560 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20562 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
20564 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 32,
20565 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20567 /* mulu.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
20569 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 32,
20570 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20572 /* mulu.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
20574 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 32,
20575 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20577 /* mulu.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
20579 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 32,
20580 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20582 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
20584 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 32,
20585 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20587 /* mulu.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
20589 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 32,
20590 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20592 /* mulu.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
20594 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 32,
20595 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20597 /* mulu.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
20599 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 32,
20600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20602 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
20604 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 32,
20605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20607 /* mulu.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
20609 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 32,
20610 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20612 /* mulu.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
20614 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 32,
20615 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20617 /* mulu.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
20619 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 32,
20620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20622 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
20624 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mulu.b", 40,
20625 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20627 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
20629 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mulu.b", 40,
20630 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20632 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
20634 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mulu.b", 40,
20635 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20637 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
20639 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mulu.b", 40,
20640 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20642 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
20644 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mulu.b", 48,
20645 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20647 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
20649 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mulu.b", 48,
20650 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20652 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
20654 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mulu.b", 48,
20655 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20657 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
20659 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mulu.b", 48,
20660 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20662 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
20664 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mulu.b", 56,
20665 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20667 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
20669 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mulu.b", 56,
20670 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20672 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
20674 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mulu.b", 56,
20675 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20677 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
20679 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mulu.b", 56,
20680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20682 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
20684 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mulu.b", 40,
20685 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20687 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
20689 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mulu.b", 40,
20690 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20692 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
20694 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mulu.b", 40,
20695 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20697 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
20699 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mulu.b", 40,
20700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20702 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
20704 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mulu.b", 48,
20705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20707 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
20709 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mulu.b", 48,
20710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20712 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
20714 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mulu.b", 48,
20715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20717 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
20719 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mulu.b", 48,
20720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20722 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
20724 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mulu.b", 40,
20725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20727 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
20729 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mulu.b", 40,
20730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20732 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
20734 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mulu.b", 40,
20735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20737 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
20739 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mulu.b", 40,
20740 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20742 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
20744 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mulu.b", 48,
20745 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20747 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
20749 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mulu.b", 48,
20750 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20752 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
20754 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mulu.b", 48,
20755 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20757 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
20759 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mulu.b", 48,
20760 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20762 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
20764 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mulu.b", 48,
20765 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20767 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
20769 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mulu.b", 48,
20770 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20772 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
20774 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mulu.b", 48,
20775 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20777 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
20779 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mulu.b", 48,
20780 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20782 /* mulu.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
20784 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mulu.b", 56,
20785 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20787 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
20789 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mulu.b", 56,
20790 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20792 /* mulu.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
20794 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mulu.b", 56,
20795 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20797 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
20799 M32C_INSN_MULU32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mulu.b", 56,
20800 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20802 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
20804 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 40,
20805 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20807 /* mulu.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
20809 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 40,
20810 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20812 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
20814 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 40,
20815 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20817 /* mulu.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
20819 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 40,
20820 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20822 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
20824 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 40,
20825 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20827 /* mulu.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
20829 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 40,
20830 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20832 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
20834 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mulu.b", 48,
20835 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20837 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
20839 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mulu.b", 48,
20840 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20842 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
20844 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mulu.b", 56,
20845 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20847 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
20849 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mulu.b", 56,
20850 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20852 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
20854 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mulu.b", 64,
20855 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20857 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
20859 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mulu.b", 64,
20860 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20862 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
20864 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mulu.b", 48,
20865 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20867 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
20869 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mulu.b", 48,
20870 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20872 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
20874 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mulu.b", 56,
20875 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20877 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
20879 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mulu.b", 56,
20880 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20882 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
20884 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mulu.b", 48,
20885 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20887 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
20889 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mulu.b", 48,
20890 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20892 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
20894 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mulu.b", 56,
20895 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20897 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
20899 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mulu.b", 56,
20900 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20902 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
20904 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mulu.b", 56,
20905 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20907 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
20909 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mulu.b", 56,
20910 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20912 /* mulu.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
20914 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mulu.b", 64,
20915 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20917 /* mulu.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
20919 M32C_INSN_MULU32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mulu.b", 64,
20920 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20922 /* mulu.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
20924 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 16,
20925 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20927 /* mulu.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
20929 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 16,
20930 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20932 /* mulu.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
20934 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 16,
20935 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20937 /* mulu.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
20939 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 16,
20940 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20942 /* mulu.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
20944 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 16,
20945 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20947 /* mulu.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
20949 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mulu.b", 16,
20950 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20952 /* mulu.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
20954 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 16,
20955 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20957 /* mulu.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
20959 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 16,
20960 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20962 /* mulu.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
20964 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mulu.b", 16,
20965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20967 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
20969 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mulu.b", 24,
20970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20972 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
20974 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mulu.b", 24,
20975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20977 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
20979 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mulu.b", 24,
20980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20982 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
20984 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mulu.b", 32,
20985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20987 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
20989 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mulu.b", 32,
20990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20992 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
20994 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mulu.b", 32,
20995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
20997 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
20999 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mulu.b", 40,
21000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21002 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
21004 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mulu.b", 40,
21005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21007 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
21009 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mulu.b", 40,
21010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21012 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
21014 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mulu.b", 24,
21015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21017 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
21019 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mulu.b", 24,
21020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21022 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
21024 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mulu.b", 24,
21025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21027 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
21029 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mulu.b", 32,
21030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21032 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
21034 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mulu.b", 32,
21035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21037 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
21039 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mulu.b", 32,
21040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21042 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
21044 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mulu.b", 24,
21045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21047 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
21049 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mulu.b", 24,
21050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21052 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
21054 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mulu.b", 24,
21055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21057 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
21059 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mulu.b", 32,
21060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21062 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
21064 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mulu.b", 32,
21065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21067 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
21069 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mulu.b", 32,
21070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21072 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
21074 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mulu.b", 32,
21075 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21077 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
21079 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mulu.b", 32,
21080 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21082 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
21084 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mulu.b", 32,
21085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21087 /* mulu.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
21089 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mulu.b", 40,
21090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21092 /* mulu.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
21094 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mulu.b", 40,
21095 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21097 /* mulu.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
21099 M32C_INSN_MULU32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mulu.b", 40,
21100 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21102 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
21104 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "mulu.w", 24,
21105 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21107 /* mulu.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
21109 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "mulu.w", 24,
21110 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21112 /* mulu.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
21114 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "mulu.w", 24,
21115 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21117 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
21119 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "mulu.w", 24,
21120 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21122 /* mulu.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
21124 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "mulu.w", 24,
21125 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21127 /* mulu.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
21129 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "mulu.w", 24,
21130 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21132 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
21134 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "mulu.w", 24,
21135 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21137 /* mulu.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
21139 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "mulu.w", 24,
21140 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21142 /* mulu.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
21144 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "mulu.w", 24,
21145 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21147 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
21149 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "mulu.w", 32,
21150 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21152 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
21154 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "mulu.w", 32,
21155 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21157 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
21159 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "mulu.w", 32,
21160 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21162 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
21164 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "mulu.w", 40,
21165 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21167 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
21169 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "mulu.w", 40,
21170 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21172 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
21174 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "mulu.w", 40,
21175 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21177 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
21179 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "mulu.w", 32,
21180 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21182 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
21184 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "mulu.w", 32,
21185 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21187 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
21189 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "mulu.w", 32,
21190 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21192 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
21194 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "mulu.w", 40,
21195 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21197 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
21199 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "mulu.w", 40,
21200 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21202 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
21204 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "mulu.w", 40,
21205 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21207 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
21209 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "mulu.w", 32,
21210 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21212 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
21214 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "mulu.w", 32,
21215 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21217 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
21219 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "mulu.w", 32,
21220 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21222 /* mulu.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
21224 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mulu16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "mulu.w", 40,
21225 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21227 /* mulu.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
21229 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mulu16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "mulu.w", 40,
21230 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21232 /* mulu.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
21234 M32C_INSN_MULU16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mulu16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "mulu.w", 40,
21235 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21237 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
21239 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "mulu.w", 32,
21240 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21242 /* mulu.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
21244 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "mulu.w", 32,
21245 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21247 /* mulu.w${G} ${Dsp-16-u16},$Dst16RnHI */
21249 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "mulu.w", 32,
21250 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21252 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
21254 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "mulu.w", 32,
21255 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21257 /* mulu.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
21259 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "mulu.w", 32,
21260 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21262 /* mulu.w${G} ${Dsp-16-u16},$Dst16AnHI */
21264 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "mulu.w", 32,
21265 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21267 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
21269 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "mulu.w", 32,
21270 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21272 /* mulu.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
21274 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "mulu.w", 32,
21275 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21277 /* mulu.w${G} ${Dsp-16-u16},[$Dst16An] */
21279 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "mulu.w", 32,
21280 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21282 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
21284 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "mulu.w", 40,
21285 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21287 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
21289 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "mulu.w", 40,
21290 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21292 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
21294 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "mulu.w", 40,
21295 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21297 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
21299 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "mulu.w", 48,
21300 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21302 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
21304 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "mulu.w", 48,
21305 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21307 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
21309 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "mulu.w", 48,
21310 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21312 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
21314 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "mulu.w", 40,
21315 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21317 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
21319 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "mulu.w", 40,
21320 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21322 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
21324 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "mulu.w", 40,
21325 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21327 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
21329 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "mulu.w", 48,
21330 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21332 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
21334 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "mulu.w", 48,
21335 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21337 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
21339 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "mulu.w", 48,
21340 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21342 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
21344 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "mulu.w", 40,
21345 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21347 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
21349 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "mulu.w", 40,
21350 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21352 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
21354 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "mulu.w", 40,
21355 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21357 /* mulu.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
21359 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mulu16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "mulu.w", 48,
21360 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21362 /* mulu.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
21364 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mulu16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "mulu.w", 48,
21365 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21367 /* mulu.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
21369 M32C_INSN_MULU16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "mulu16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "mulu.w", 48,
21370 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21372 /* mulu.w${G} $Src16RnHI,$Dst16RnHI */
21374 M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "mulu.w", 16,
21375 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21377 /* mulu.w${G} $Src16AnHI,$Dst16RnHI */
21379 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "mulu.w", 16,
21380 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21382 /* mulu.w${G} [$Src16An],$Dst16RnHI */
21384 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "mulu.w", 16,
21385 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21387 /* mulu.w${G} $Src16RnHI,$Dst16AnHI */
21389 M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "mulu.w", 16,
21390 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21392 /* mulu.w${G} $Src16AnHI,$Dst16AnHI */
21394 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "mulu.w", 16,
21395 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21397 /* mulu.w${G} [$Src16An],$Dst16AnHI */
21399 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "mulu.w", 16,
21400 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21402 /* mulu.w${G} $Src16RnHI,[$Dst16An] */
21404 M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "mulu.w", 16,
21405 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21407 /* mulu.w${G} $Src16AnHI,[$Dst16An] */
21409 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "mulu.w", 16,
21410 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21412 /* mulu.w${G} [$Src16An],[$Dst16An] */
21414 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "mulu.w", 16,
21415 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21417 /* mulu.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
21419 M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "mulu.w", 24,
21420 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21422 /* mulu.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
21424 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "mulu.w", 24,
21425 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21427 /* mulu.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
21429 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "mulu.w", 24,
21430 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21432 /* mulu.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
21434 M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "mulu.w", 32,
21435 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21437 /* mulu.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
21439 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "mulu.w", 32,
21440 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21442 /* mulu.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
21444 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "mulu.w", 32,
21445 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21447 /* mulu.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
21449 M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "mulu.w", 24,
21450 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21452 /* mulu.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
21454 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "mulu.w", 24,
21455 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21457 /* mulu.w${G} [$Src16An],${Dsp-16-u8}[sb] */
21459 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "mulu.w", 24,
21460 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21462 /* mulu.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
21464 M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "mulu.w", 32,
21465 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21467 /* mulu.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
21469 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "mulu.w", 32,
21470 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21472 /* mulu.w${G} [$Src16An],${Dsp-16-u16}[sb] */
21474 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "mulu.w", 32,
21475 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21477 /* mulu.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
21479 M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "mulu.w", 24,
21480 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21482 /* mulu.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
21484 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "mulu.w", 24,
21485 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21487 /* mulu.w${G} [$Src16An],${Dsp-16-s8}[fb] */
21489 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "mulu.w", 24,
21490 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21492 /* mulu.w${G} $Src16RnHI,${Dsp-16-u16} */
21494 M32C_INSN_MULU16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mulu16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "mulu.w", 32,
21495 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21497 /* mulu.w${G} $Src16AnHI,${Dsp-16-u16} */
21499 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mulu16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "mulu.w", 32,
21500 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21502 /* mulu.w${G} [$Src16An],${Dsp-16-u16} */
21504 M32C_INSN_MULU16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mulu16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "mulu.w", 32,
21505 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21507 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
21509 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "mulu.b", 24,
21510 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21512 /* mulu.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
21514 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "mulu.b", 24,
21515 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21517 /* mulu.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
21519 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "mulu.b", 24,
21520 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21522 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
21524 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "mulu.b", 24,
21525 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21527 /* mulu.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
21529 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "mulu.b", 24,
21530 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21532 /* mulu.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
21534 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "mulu.b", 24,
21535 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21537 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
21539 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "mulu.b", 24,
21540 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21542 /* mulu.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
21544 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "mulu.b", 24,
21545 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21547 /* mulu.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
21549 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "mulu.b", 24,
21550 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21552 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
21554 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "mulu.b", 32,
21555 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21557 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
21559 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "mulu.b", 32,
21560 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21562 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
21564 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "mulu.b", 32,
21565 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21567 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
21569 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "mulu.b", 40,
21570 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21572 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
21574 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "mulu.b", 40,
21575 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21577 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
21579 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "mulu.b", 40,
21580 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21582 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
21584 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "mulu.b", 32,
21585 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21587 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
21589 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "mulu.b", 32,
21590 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21592 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
21594 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "mulu.b", 32,
21595 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21597 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
21599 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "mulu.b", 40,
21600 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21602 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
21604 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "mulu.b", 40,
21605 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21607 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
21609 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "mulu.b", 40,
21610 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21612 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
21614 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "mulu.b", 32,
21615 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21617 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
21619 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "mulu.b", 32,
21620 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21622 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
21624 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "mulu.b", 32,
21625 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21627 /* mulu.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
21629 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mulu16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "mulu.b", 40,
21630 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21632 /* mulu.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
21634 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mulu16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "mulu.b", 40,
21635 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21637 /* mulu.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
21639 M32C_INSN_MULU16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mulu16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "mulu.b", 40,
21640 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21642 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
21644 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "mulu.b", 32,
21645 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21647 /* mulu.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
21649 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "mulu.b", 32,
21650 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21652 /* mulu.b${G} ${Dsp-16-u16},$Dst16RnQI */
21654 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "mulu.b", 32,
21655 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21657 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
21659 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "mulu.b", 32,
21660 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21662 /* mulu.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
21664 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "mulu.b", 32,
21665 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21667 /* mulu.b${G} ${Dsp-16-u16},$Dst16AnQI */
21669 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "mulu.b", 32,
21670 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21672 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
21674 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "mulu.b", 32,
21675 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21677 /* mulu.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
21679 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "mulu.b", 32,
21680 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21682 /* mulu.b${G} ${Dsp-16-u16},[$Dst16An] */
21684 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "mulu.b", 32,
21685 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21687 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
21689 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "mulu.b", 40,
21690 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21692 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
21694 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "mulu.b", 40,
21695 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21697 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
21699 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "mulu.b", 40,
21700 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21702 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
21704 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "mulu.b", 48,
21705 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21707 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
21709 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "mulu.b", 48,
21710 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21712 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
21714 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "mulu.b", 48,
21715 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21717 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
21719 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "mulu.b", 40,
21720 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21722 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
21724 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "mulu.b", 40,
21725 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21727 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
21729 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "mulu.b", 40,
21730 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21732 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
21734 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "mulu.b", 48,
21735 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21737 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
21739 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "mulu.b", 48,
21740 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21742 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
21744 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "mulu.b", 48,
21745 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21747 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
21749 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "mulu.b", 40,
21750 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21752 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
21754 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "mulu.b", 40,
21755 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21757 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
21759 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "mulu.b", 40,
21760 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21762 /* mulu.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
21764 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mulu16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "mulu.b", 48,
21765 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21767 /* mulu.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
21769 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mulu16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "mulu.b", 48,
21770 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21772 /* mulu.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
21774 M32C_INSN_MULU16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "mulu16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "mulu.b", 48,
21775 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21777 /* mulu.b${G} $Src16RnQI,$Dst16RnQI */
21779 M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "mulu.b", 16,
21780 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21782 /* mulu.b${G} $Src16AnQI,$Dst16RnQI */
21784 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "mulu.b", 16,
21785 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21787 /* mulu.b${G} [$Src16An],$Dst16RnQI */
21789 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "mulu.b", 16,
21790 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21792 /* mulu.b${G} $Src16RnQI,$Dst16AnQI */
21794 M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "mulu.b", 16,
21795 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21797 /* mulu.b${G} $Src16AnQI,$Dst16AnQI */
21799 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "mulu.b", 16,
21800 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21802 /* mulu.b${G} [$Src16An],$Dst16AnQI */
21804 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "mulu.b", 16,
21805 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21807 /* mulu.b${G} $Src16RnQI,[$Dst16An] */
21809 M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "mulu.b", 16,
21810 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21812 /* mulu.b${G} $Src16AnQI,[$Dst16An] */
21814 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "mulu.b", 16,
21815 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21817 /* mulu.b${G} [$Src16An],[$Dst16An] */
21819 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "mulu.b", 16,
21820 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21822 /* mulu.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
21824 M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "mulu.b", 24,
21825 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21827 /* mulu.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
21829 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "mulu.b", 24,
21830 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21832 /* mulu.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
21834 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "mulu.b", 24,
21835 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21837 /* mulu.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
21839 M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "mulu.b", 32,
21840 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21842 /* mulu.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
21844 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "mulu.b", 32,
21845 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21847 /* mulu.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
21849 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "mulu.b", 32,
21850 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21852 /* mulu.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
21854 M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "mulu.b", 24,
21855 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21857 /* mulu.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
21859 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "mulu.b", 24,
21860 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21862 /* mulu.b${G} [$Src16An],${Dsp-16-u8}[sb] */
21864 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "mulu.b", 24,
21865 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21867 /* mulu.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
21869 M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "mulu.b", 32,
21870 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21872 /* mulu.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
21874 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "mulu.b", 32,
21875 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21877 /* mulu.b${G} [$Src16An],${Dsp-16-u16}[sb] */
21879 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "mulu.b", 32,
21880 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21882 /* mulu.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
21884 M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "mulu.b", 24,
21885 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21887 /* mulu.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
21889 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "mulu.b", 24,
21890 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21892 /* mulu.b${G} [$Src16An],${Dsp-16-s8}[fb] */
21894 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "mulu.b", 24,
21895 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21897 /* mulu.b${G} $Src16RnQI,${Dsp-16-u16} */
21899 M32C_INSN_MULU16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mulu16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "mulu.b", 32,
21900 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21902 /* mulu.b${G} $Src16AnQI,${Dsp-16-u16} */
21904 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mulu16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "mulu.b", 32,
21905 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21907 /* mulu.b${G} [$Src16An],${Dsp-16-u16} */
21909 M32C_INSN_MULU16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mulu16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "mulu.b", 32,
21910 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
21912 /* mulu.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
21914 M32C_INSN_MULU32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mulu32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mulu.w", 32,
21915 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21917 /* mulu.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
21919 M32C_INSN_MULU32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mulu32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mulu.w", 32,
21920 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21922 /* mulu.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
21924 M32C_INSN_MULU32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulu32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mulu.w", 32,
21925 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21927 /* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
21929 M32C_INSN_MULU32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mulu.w", 40,
21930 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21932 /* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
21934 M32C_INSN_MULU32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mulu.w", 40,
21935 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21937 /* mulu.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
21939 M32C_INSN_MULU32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mulu.w", 40,
21940 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21942 /* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
21944 M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mulu.w", 48,
21945 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21947 /* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
21949 M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mulu.w", 48,
21950 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21952 /* mulu.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
21954 M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mulu.w", 48,
21955 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21957 /* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16} */
21959 M32C_INSN_MULU32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mulu.w", 48,
21960 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21962 /* mulu.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
21964 M32C_INSN_MULU32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulu32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mulu.w", 56,
21965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21967 /* mulu.w${G} #${Imm-40-HI},${Dsp-16-u24} */
21969 M32C_INSN_MULU32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulu32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mulu.w", 56,
21970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21972 /* mulu.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
21974 M32C_INSN_MULU32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mulu32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mulu.b", 24,
21975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21977 /* mulu.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
21979 M32C_INSN_MULU32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mulu32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mulu.b", 24,
21980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21982 /* mulu.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
21984 M32C_INSN_MULU32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mulu32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mulu.b", 24,
21985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21987 /* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
21989 M32C_INSN_MULU32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mulu.b", 32,
21990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21992 /* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
21994 M32C_INSN_MULU32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mulu.b", 32,
21995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
21997 /* mulu.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
21999 M32C_INSN_MULU32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mulu.b", 32,
22000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22002 /* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
22004 M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mulu.b", 40,
22005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22007 /* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
22009 M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mulu.b", 40,
22010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22012 /* mulu.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
22014 M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mulu.b", 40,
22015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22017 /* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16} */
22019 M32C_INSN_MULU32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mulu.b", 40,
22020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22022 /* mulu.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
22024 M32C_INSN_MULU32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mulu32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mulu.b", 48,
22025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22027 /* mulu.b${G} #${Imm-40-QI},${Dsp-16-u24} */
22029 M32C_INSN_MULU32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mulu32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mulu.b", 48,
22030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22032 /* mulu.w${G} #${Imm-16-HI},$Dst16RnHI */
22034 M32C_INSN_MULU16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "mulu16.w-imm-G-basic-dst16-Rn-direct-HI", "mulu.w", 32,
22035 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22037 /* mulu.w${G} #${Imm-16-HI},$Dst16AnHI */
22039 M32C_INSN_MULU16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "mulu16.w-imm-G-basic-dst16-An-direct-HI", "mulu.w", 32,
22040 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22042 /* mulu.w${G} #${Imm-16-HI},[$Dst16An] */
22044 M32C_INSN_MULU16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "mulu16.w-imm-G-basic-dst16-An-indirect-HI", "mulu.w", 32,
22045 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22047 /* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
22049 M32C_INSN_MULU16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "mulu16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "mulu.w", 40,
22050 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22052 /* mulu.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
22054 M32C_INSN_MULU16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "mulu16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "mulu.w", 40,
22055 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22057 /* mulu.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
22059 M32C_INSN_MULU16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "mulu16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "mulu.w", 40,
22060 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22062 /* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
22064 M32C_INSN_MULU16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "mulu16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "mulu.w", 48,
22065 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22067 /* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
22069 M32C_INSN_MULU16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "mulu16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "mulu.w", 48,
22070 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22072 /* mulu.w${G} #${Imm-32-HI},${Dsp-16-u16} */
22074 M32C_INSN_MULU16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "mulu16.w-imm-G-16-16-dst16-16-16-absolute-HI", "mulu.w", 48,
22075 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22077 /* mulu.b${G} #${Imm-16-QI},$Dst16RnQI */
22079 M32C_INSN_MULU16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "mulu16.b-imm-G-basic-dst16-Rn-direct-QI", "mulu.b", 24,
22080 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22082 /* mulu.b${G} #${Imm-16-QI},$Dst16AnQI */
22084 M32C_INSN_MULU16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "mulu16.b-imm-G-basic-dst16-An-direct-QI", "mulu.b", 24,
22085 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22087 /* mulu.b${G} #${Imm-16-QI},[$Dst16An] */
22089 M32C_INSN_MULU16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "mulu16.b-imm-G-basic-dst16-An-indirect-QI", "mulu.b", 24,
22090 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22092 /* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
22094 M32C_INSN_MULU16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "mulu16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "mulu.b", 32,
22095 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22097 /* mulu.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
22099 M32C_INSN_MULU16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "mulu16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "mulu.b", 32,
22100 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22102 /* mulu.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
22104 M32C_INSN_MULU16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "mulu16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "mulu.b", 32,
22105 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22107 /* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
22109 M32C_INSN_MULU16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "mulu16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "mulu.b", 40,
22110 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22112 /* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
22114 M32C_INSN_MULU16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "mulu16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "mulu.b", 40,
22115 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22117 /* mulu.b${G} #${Imm-32-QI},${Dsp-16-u16} */
22119 M32C_INSN_MULU16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "mulu16.b-imm-G-16-16-dst16-16-16-absolute-QI", "mulu.b", 40,
22120 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
22124 M32C_INSN_MULEX_DST32_R3_DIRECT_UNPREFIXED_HI, "mulex-dst32-R3-direct-Unprefixed-HI", "mulex", 16,
22125 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22127 /* mulex $Dst32AnUnprefixedHI */
22129 M32C_INSN_MULEX_DST32_AN_DIRECT_UNPREFIXED_HI, "mulex-dst32-An-direct-Unprefixed-HI", "mulex", 16,
22130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22132 /* mulex [$Dst32AnUnprefixed] */
22134 M32C_INSN_MULEX_DST32_AN_INDIRECT_UNPREFIXED_HI, "mulex-dst32-An-indirect-Unprefixed-HI", "mulex", 16,
22135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22137 /* mulex ${Dsp-16-u8}[$Dst32AnUnprefixed] */
22139 M32C_INSN_MULEX_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-8-An-relative-Unprefixed-HI", "mulex", 24,
22140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22142 /* mulex ${Dsp-16-u16}[$Dst32AnUnprefixed] */
22144 M32C_INSN_MULEX_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-16-An-relative-Unprefixed-HI", "mulex", 32,
22145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22147 /* mulex ${Dsp-16-u24}[$Dst32AnUnprefixed] */
22149 M32C_INSN_MULEX_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-24-An-relative-Unprefixed-HI", "mulex", 40,
22150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22152 /* mulex ${Dsp-16-u8}[sb] */
22154 M32C_INSN_MULEX_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-8-SB-relative-Unprefixed-HI", "mulex", 24,
22155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22157 /* mulex ${Dsp-16-u16}[sb] */
22159 M32C_INSN_MULEX_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-16-SB-relative-Unprefixed-HI", "mulex", 32,
22160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22162 /* mulex ${Dsp-16-s8}[fb] */
22164 M32C_INSN_MULEX_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-8-FB-relative-Unprefixed-HI", "mulex", 24,
22165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22167 /* mulex ${Dsp-16-s16}[fb] */
22169 M32C_INSN_MULEX_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mulex-dst32-16-16-FB-relative-Unprefixed-HI", "mulex", 32,
22170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22172 /* mulex ${Dsp-16-u16} */
22174 M32C_INSN_MULEX_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mulex-dst32-16-16-absolute-Unprefixed-HI", "mulex", 32,
22175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22177 /* mulex ${Dsp-16-u24} */
22179 M32C_INSN_MULEX_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mulex-dst32-16-24-absolute-Unprefixed-HI", "mulex", 40,
22180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22182 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
22184 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 24,
22185 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22187 /* mul.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
22189 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 24,
22190 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22192 /* mul.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
22194 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 24,
22195 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22197 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
22199 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 24,
22200 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22202 /* mul.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
22204 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 24,
22205 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22207 /* mul.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
22209 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 24,
22210 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22212 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
22214 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 24,
22215 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22217 /* mul.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
22219 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 24,
22220 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22222 /* mul.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
22224 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 24,
22225 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22227 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
22229 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mul.w", 32,
22230 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22232 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
22234 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mul.w", 32,
22235 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22237 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
22239 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mul.w", 32,
22240 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22242 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
22244 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mul.w", 40,
22245 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22247 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
22249 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mul.w", 40,
22250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22252 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
22254 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mul.w", 40,
22255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22257 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
22259 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mul.w", 48,
22260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22262 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
22264 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mul.w", 48,
22265 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22267 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
22269 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mul.w", 48,
22270 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22272 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
22274 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mul.w", 32,
22275 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22277 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
22279 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mul.w", 32,
22280 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22282 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
22284 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mul.w", 32,
22285 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22287 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
22289 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mul.w", 40,
22290 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22292 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
22294 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mul.w", 40,
22295 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22297 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
22299 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mul.w", 40,
22300 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22302 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
22304 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mul.w", 32,
22305 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22307 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
22309 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mul.w", 32,
22310 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22312 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
22314 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mul.w", 32,
22315 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22317 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
22319 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mul.w", 40,
22320 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22322 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
22324 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mul.w", 40,
22325 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22327 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
22329 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mul.w", 40,
22330 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22332 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
22334 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mul.w", 40,
22335 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22337 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
22339 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mul.w", 40,
22340 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22342 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
22344 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mul.w", 40,
22345 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22347 /* mul.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
22349 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mul.w", 48,
22350 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22352 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
22354 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mul.w", 48,
22355 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22357 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
22359 M32C_INSN_MUL32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mul.w", 48,
22360 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22362 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
22364 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32,
22365 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22367 /* mul.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
22369 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32,
22370 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22372 /* mul.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
22374 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32,
22375 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22377 /* mul.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
22379 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32,
22380 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22382 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
22384 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 32,
22385 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22387 /* mul.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
22389 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 32,
22390 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22392 /* mul.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
22394 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 32,
22395 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22397 /* mul.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
22399 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 32,
22400 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22402 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
22404 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 32,
22405 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22407 /* mul.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
22409 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 32,
22410 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22412 /* mul.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
22414 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 32,
22415 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22417 /* mul.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
22419 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 32,
22420 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22422 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
22424 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mul.w", 40,
22425 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22427 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
22429 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mul.w", 40,
22430 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22432 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
22434 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mul.w", 40,
22435 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22437 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
22439 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mul.w", 40,
22440 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22442 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
22444 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mul.w", 48,
22445 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22447 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
22449 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mul.w", 48,
22450 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22452 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
22454 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mul.w", 48,
22455 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22457 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
22459 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mul.w", 48,
22460 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22462 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
22464 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mul.w", 56,
22465 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22467 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
22469 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mul.w", 56,
22470 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22472 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
22474 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mul.w", 56,
22475 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22477 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
22479 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mul.w", 56,
22480 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22482 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
22484 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mul.w", 40,
22485 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22487 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
22489 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mul.w", 40,
22490 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22492 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
22494 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mul.w", 40,
22495 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22497 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
22499 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mul.w", 40,
22500 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22502 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
22504 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mul.w", 48,
22505 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22507 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
22509 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mul.w", 48,
22510 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22512 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
22514 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mul.w", 48,
22515 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22517 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
22519 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mul.w", 48,
22520 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22522 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
22524 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mul.w", 40,
22525 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22527 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
22529 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mul.w", 40,
22530 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22532 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
22534 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mul.w", 40,
22535 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22537 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
22539 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mul.w", 40,
22540 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22542 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
22544 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mul.w", 48,
22545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22547 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
22549 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mul.w", 48,
22550 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22552 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
22554 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mul.w", 48,
22555 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22557 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
22559 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mul.w", 48,
22560 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22562 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
22564 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mul.w", 48,
22565 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22567 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
22569 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mul.w", 48,
22570 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22572 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
22574 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mul.w", 48,
22575 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22577 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
22579 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mul.w", 48,
22580 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22582 /* mul.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
22584 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mul.w", 56,
22585 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22587 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
22589 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mul.w", 56,
22590 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22592 /* mul.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
22594 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mul.w", 56,
22595 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22597 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
22599 M32C_INSN_MUL32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mul.w", 56,
22600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22602 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
22604 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 40,
22605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22607 /* mul.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
22609 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 40,
22610 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22612 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
22614 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 40,
22615 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22617 /* mul.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
22619 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 40,
22620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22622 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
22624 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 40,
22625 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22627 /* mul.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
22629 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 40,
22630 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22632 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
22634 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mul.w", 48,
22635 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22637 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
22639 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mul.w", 48,
22640 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22642 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
22644 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mul.w", 56,
22645 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22647 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
22649 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mul.w", 56,
22650 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22652 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
22654 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mul.w", 64,
22655 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22657 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
22659 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mul.w", 64,
22660 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22662 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
22664 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mul.w", 48,
22665 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22667 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
22669 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mul.w", 48,
22670 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22672 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
22674 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mul.w", 56,
22675 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22677 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
22679 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mul.w", 56,
22680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22682 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
22684 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mul.w", 48,
22685 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22687 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
22689 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mul.w", 48,
22690 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22692 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
22694 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mul.w", 56,
22695 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22697 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
22699 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mul.w", 56,
22700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22702 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
22704 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mul.w", 56,
22705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22707 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
22709 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mul.w", 56,
22710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22712 /* mul.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
22714 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mul.w", 64,
22715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22717 /* mul.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
22719 M32C_INSN_MUL32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mul.w", 64,
22720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22722 /* mul.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
22724 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 16,
22725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22727 /* mul.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
22729 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 16,
22730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22732 /* mul.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
22734 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mul.w", 16,
22735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22737 /* mul.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
22739 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 16,
22740 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22742 /* mul.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
22744 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 16,
22745 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22747 /* mul.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
22749 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mul.w", 16,
22750 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22752 /* mul.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
22754 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 16,
22755 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22757 /* mul.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
22759 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 16,
22760 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22762 /* mul.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
22764 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mul.w", 16,
22765 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22767 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
22769 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mul.w", 24,
22770 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22772 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
22774 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mul.w", 24,
22775 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22777 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
22779 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mul.w", 24,
22780 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22782 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
22784 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mul.w", 32,
22785 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22787 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
22789 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mul.w", 32,
22790 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22792 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
22794 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mul.w", 32,
22795 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22797 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
22799 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mul.w", 40,
22800 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22802 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
22804 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mul.w", 40,
22805 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22807 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
22809 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mul.w", 40,
22810 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22812 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
22814 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mul.w", 24,
22815 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22817 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
22819 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mul.w", 24,
22820 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22822 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
22824 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mul.w", 24,
22825 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22827 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
22829 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mul.w", 32,
22830 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22832 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
22834 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mul.w", 32,
22835 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22837 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
22839 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mul.w", 32,
22840 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22842 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
22844 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mul.w", 24,
22845 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22847 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
22849 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mul.w", 24,
22850 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22852 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
22854 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mul.w", 24,
22855 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22857 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
22859 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mul.w", 32,
22860 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22862 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
22864 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mul.w", 32,
22865 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22867 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
22869 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mul.w", 32,
22870 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22872 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
22874 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mul.w", 32,
22875 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22877 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
22879 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mul.w", 32,
22880 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22882 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
22884 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mul.w", 32,
22885 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22887 /* mul.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
22889 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mul.w", 40,
22890 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22892 /* mul.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
22894 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mul.w", 40,
22895 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22897 /* mul.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
22899 M32C_INSN_MUL32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mul.w", 40,
22900 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22902 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
22904 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 24,
22905 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22907 /* mul.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
22909 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 24,
22910 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22912 /* mul.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
22914 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 24,
22915 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22917 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
22919 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 24,
22920 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22922 /* mul.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
22924 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 24,
22925 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22927 /* mul.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
22929 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 24,
22930 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22932 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
22934 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 24,
22935 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22937 /* mul.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
22939 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 24,
22940 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22942 /* mul.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
22944 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 24,
22945 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22947 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
22949 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mul.b", 32,
22950 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22952 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
22954 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mul.b", 32,
22955 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22957 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
22959 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mul.b", 32,
22960 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22962 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
22964 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mul.b", 40,
22965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22967 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
22969 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mul.b", 40,
22970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22972 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
22974 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mul.b", 40,
22975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22977 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
22979 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mul.b", 48,
22980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22982 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
22984 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mul.b", 48,
22985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22987 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
22989 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mul.b", 48,
22990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22992 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
22994 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mul.b", 32,
22995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
22997 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
22999 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mul.b", 32,
23000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23002 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
23004 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mul.b", 32,
23005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23007 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
23009 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mul.b", 40,
23010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23012 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
23014 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mul.b", 40,
23015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23017 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
23019 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mul.b", 40,
23020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23022 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
23024 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mul.b", 32,
23025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23027 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
23029 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mul.b", 32,
23030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23032 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
23034 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mul.b", 32,
23035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23037 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
23039 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mul.b", 40,
23040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23042 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
23044 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mul.b", 40,
23045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23047 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
23049 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mul.b", 40,
23050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23052 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
23054 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mul.b", 40,
23055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23057 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
23059 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mul.b", 40,
23060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23062 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
23064 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mul.b", 40,
23065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23067 /* mul.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
23069 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mul.b", 48,
23070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23072 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
23074 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mul.b", 48,
23075 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23077 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
23079 M32C_INSN_MUL32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mul.b", 48,
23080 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23082 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
23084 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 32,
23085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23087 /* mul.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
23089 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 32,
23090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23092 /* mul.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
23094 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 32,
23095 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23097 /* mul.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
23099 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 32,
23100 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23102 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
23104 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 32,
23105 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23107 /* mul.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
23109 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 32,
23110 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23112 /* mul.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
23114 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 32,
23115 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23117 /* mul.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
23119 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 32,
23120 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23122 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
23124 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 32,
23125 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23127 /* mul.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
23129 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 32,
23130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23132 /* mul.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
23134 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 32,
23135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23137 /* mul.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
23139 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 32,
23140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23142 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
23144 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mul.b", 40,
23145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23147 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
23149 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mul.b", 40,
23150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23152 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
23154 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mul.b", 40,
23155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23157 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
23159 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mul.b", 40,
23160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23162 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
23164 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mul.b", 48,
23165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23167 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
23169 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mul.b", 48,
23170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23172 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
23174 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mul.b", 48,
23175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23177 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
23179 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mul.b", 48,
23180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23182 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
23184 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mul.b", 56,
23185 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23187 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
23189 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mul.b", 56,
23190 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23192 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
23194 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mul.b", 56,
23195 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23197 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
23199 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mul.b", 56,
23200 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23202 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
23204 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mul.b", 40,
23205 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23207 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
23209 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mul.b", 40,
23210 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23212 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
23214 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mul.b", 40,
23215 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23217 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
23219 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mul.b", 40,
23220 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23222 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
23224 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mul.b", 48,
23225 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23227 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
23229 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mul.b", 48,
23230 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23232 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
23234 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mul.b", 48,
23235 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23237 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
23239 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mul.b", 48,
23240 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23242 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
23244 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mul.b", 40,
23245 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23247 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
23249 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mul.b", 40,
23250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23252 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
23254 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mul.b", 40,
23255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23257 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
23259 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mul.b", 40,
23260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23262 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
23264 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mul.b", 48,
23265 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23267 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
23269 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mul.b", 48,
23270 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23272 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
23274 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mul.b", 48,
23275 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23277 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
23279 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mul.b", 48,
23280 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23282 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
23284 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mul.b", 48,
23285 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23287 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
23289 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mul.b", 48,
23290 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23292 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
23294 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mul.b", 48,
23295 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23297 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
23299 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mul.b", 48,
23300 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23302 /* mul.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
23304 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mul.b", 56,
23305 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23307 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
23309 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mul.b", 56,
23310 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23312 /* mul.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
23314 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mul.b", 56,
23315 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23317 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
23319 M32C_INSN_MUL32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mul.b", 56,
23320 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23322 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
23324 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 40,
23325 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23327 /* mul.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
23329 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 40,
23330 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23332 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
23334 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 40,
23335 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23337 /* mul.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
23339 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 40,
23340 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23342 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
23344 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 40,
23345 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23347 /* mul.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
23349 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 40,
23350 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23352 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
23354 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mul.b", 48,
23355 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23357 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
23359 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mul.b", 48,
23360 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23362 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
23364 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mul.b", 56,
23365 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23367 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
23369 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mul.b", 56,
23370 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23372 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
23374 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mul.b", 64,
23375 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23377 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
23379 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mul.b", 64,
23380 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23382 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
23384 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mul.b", 48,
23385 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23387 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
23389 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mul.b", 48,
23390 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23392 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
23394 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mul.b", 56,
23395 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23397 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
23399 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mul.b", 56,
23400 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23402 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
23404 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mul.b", 48,
23405 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23407 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
23409 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mul.b", 48,
23410 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23412 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
23414 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mul.b", 56,
23415 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23417 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
23419 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mul.b", 56,
23420 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23422 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
23424 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mul.b", 56,
23425 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23427 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
23429 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mul.b", 56,
23430 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23432 /* mul.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
23434 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mul.b", 64,
23435 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23437 /* mul.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
23439 M32C_INSN_MUL32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mul.b", 64,
23440 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23442 /* mul.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
23444 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 16,
23445 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23447 /* mul.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
23449 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 16,
23450 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23452 /* mul.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
23454 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mul.b", 16,
23455 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23457 /* mul.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
23459 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 16,
23460 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23462 /* mul.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
23464 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 16,
23465 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23467 /* mul.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
23469 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mul.b", 16,
23470 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23472 /* mul.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
23474 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 16,
23475 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23477 /* mul.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
23479 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 16,
23480 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23482 /* mul.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
23484 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mul.b", 16,
23485 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23487 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
23489 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mul.b", 24,
23490 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23492 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
23494 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mul.b", 24,
23495 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23497 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
23499 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mul.b", 24,
23500 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23502 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
23504 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mul.b", 32,
23505 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23507 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
23509 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mul.b", 32,
23510 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23512 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
23514 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mul.b", 32,
23515 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23517 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
23519 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mul.b", 40,
23520 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23522 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
23524 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mul.b", 40,
23525 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23527 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
23529 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mul.b", 40,
23530 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23532 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
23534 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mul.b", 24,
23535 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23537 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
23539 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mul.b", 24,
23540 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23542 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
23544 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mul.b", 24,
23545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23547 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
23549 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mul.b", 32,
23550 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23552 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
23554 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mul.b", 32,
23555 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23557 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
23559 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mul.b", 32,
23560 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23562 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
23564 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mul.b", 24,
23565 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23567 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
23569 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mul.b", 24,
23570 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23572 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
23574 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mul.b", 24,
23575 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23577 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
23579 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mul.b", 32,
23580 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23582 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
23584 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mul.b", 32,
23585 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23587 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
23589 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mul.b", 32,
23590 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23592 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
23594 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mul.b", 32,
23595 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23597 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
23599 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mul.b", 32,
23600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23602 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
23604 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mul.b", 32,
23605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23607 /* mul.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
23609 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mul.b", 40,
23610 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23612 /* mul.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
23614 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mul.b", 40,
23615 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23617 /* mul.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
23619 M32C_INSN_MUL32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mul.b", 40,
23620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
23622 /* mul.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
23624 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "mul.w", 24,
23625 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23627 /* mul.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
23629 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "mul.w", 24,
23630 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23632 /* mul.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
23634 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "mul.w", 24,
23635 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23637 /* mul.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
23639 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "mul.w", 24,
23640 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23642 /* mul.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
23644 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "mul.w", 24,
23645 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23647 /* mul.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
23649 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "mul.w", 24,
23650 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23652 /* mul.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
23654 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "mul.w", 24,
23655 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23657 /* mul.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
23659 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "mul.w", 24,
23660 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23662 /* mul.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
23664 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "mul.w", 24,
23665 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23667 /* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
23669 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "mul.w", 32,
23670 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23672 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
23674 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "mul.w", 32,
23675 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23677 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
23679 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "mul.w", 32,
23680 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23682 /* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
23684 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "mul.w", 40,
23685 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23687 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
23689 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "mul.w", 40,
23690 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23692 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
23694 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "mul.w", 40,
23695 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23697 /* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
23699 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "mul.w", 32,
23700 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23702 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
23704 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "mul.w", 32,
23705 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23707 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
23709 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "mul.w", 32,
23710 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23712 /* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
23714 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "mul.w", 40,
23715 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23717 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
23719 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "mul.w", 40,
23720 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23722 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
23724 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "mul.w", 40,
23725 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23727 /* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
23729 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "mul.w", 32,
23730 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23732 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
23734 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "mul.w", 32,
23735 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23737 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
23739 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "mul.w", 32,
23740 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23742 /* mul.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
23744 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mul16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "mul.w", 40,
23745 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23747 /* mul.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
23749 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mul16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "mul.w", 40,
23750 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23752 /* mul.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
23754 M32C_INSN_MUL16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mul16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "mul.w", 40,
23755 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23757 /* mul.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
23759 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "mul.w", 32,
23760 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23762 /* mul.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
23764 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "mul.w", 32,
23765 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23767 /* mul.w${G} ${Dsp-16-u16},$Dst16RnHI */
23769 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "mul.w", 32,
23770 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23772 /* mul.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
23774 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "mul.w", 32,
23775 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23777 /* mul.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
23779 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "mul.w", 32,
23780 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23782 /* mul.w${G} ${Dsp-16-u16},$Dst16AnHI */
23784 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "mul.w", 32,
23785 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23787 /* mul.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
23789 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "mul.w", 32,
23790 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23792 /* mul.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
23794 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "mul.w", 32,
23795 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23797 /* mul.w${G} ${Dsp-16-u16},[$Dst16An] */
23799 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "mul.w", 32,
23800 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23802 /* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
23804 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "mul.w", 40,
23805 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23807 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
23809 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "mul.w", 40,
23810 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23812 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
23814 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "mul.w", 40,
23815 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23817 /* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
23819 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "mul.w", 48,
23820 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23822 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
23824 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "mul.w", 48,
23825 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23827 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
23829 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "mul.w", 48,
23830 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23832 /* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
23834 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "mul.w", 40,
23835 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23837 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
23839 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "mul.w", 40,
23840 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23842 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
23844 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "mul.w", 40,
23845 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23847 /* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
23849 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "mul.w", 48,
23850 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23852 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
23854 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "mul.w", 48,
23855 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23857 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
23859 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "mul.w", 48,
23860 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23862 /* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
23864 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "mul.w", 40,
23865 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23867 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
23869 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "mul.w", 40,
23870 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23872 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
23874 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "mul.w", 40,
23875 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23877 /* mul.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
23879 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mul16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "mul.w", 48,
23880 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23882 /* mul.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
23884 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mul16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "mul.w", 48,
23885 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23887 /* mul.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
23889 M32C_INSN_MUL16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "mul16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "mul.w", 48,
23890 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23892 /* mul.w${G} $Src16RnHI,$Dst16RnHI */
23894 M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "mul.w", 16,
23895 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23897 /* mul.w${G} $Src16AnHI,$Dst16RnHI */
23899 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "mul.w", 16,
23900 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23902 /* mul.w${G} [$Src16An],$Dst16RnHI */
23904 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "mul.w", 16,
23905 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23907 /* mul.w${G} $Src16RnHI,$Dst16AnHI */
23909 M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "mul.w", 16,
23910 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23912 /* mul.w${G} $Src16AnHI,$Dst16AnHI */
23914 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "mul.w", 16,
23915 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23917 /* mul.w${G} [$Src16An],$Dst16AnHI */
23919 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "mul.w", 16,
23920 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23922 /* mul.w${G} $Src16RnHI,[$Dst16An] */
23924 M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "mul.w", 16,
23925 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23927 /* mul.w${G} $Src16AnHI,[$Dst16An] */
23929 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "mul.w", 16,
23930 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23932 /* mul.w${G} [$Src16An],[$Dst16An] */
23934 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "mul.w", 16,
23935 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23937 /* mul.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
23939 M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "mul.w", 24,
23940 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23942 /* mul.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
23944 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "mul.w", 24,
23945 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23947 /* mul.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
23949 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "mul.w", 24,
23950 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23952 /* mul.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
23954 M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "mul.w", 32,
23955 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23957 /* mul.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
23959 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "mul.w", 32,
23960 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23962 /* mul.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
23964 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "mul.w", 32,
23965 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23967 /* mul.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
23969 M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "mul.w", 24,
23970 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23972 /* mul.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
23974 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "mul.w", 24,
23975 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23977 /* mul.w${G} [$Src16An],${Dsp-16-u8}[sb] */
23979 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "mul.w", 24,
23980 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23982 /* mul.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
23984 M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "mul.w", 32,
23985 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23987 /* mul.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
23989 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "mul.w", 32,
23990 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23992 /* mul.w${G} [$Src16An],${Dsp-16-u16}[sb] */
23994 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "mul.w", 32,
23995 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
23997 /* mul.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
23999 M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "mul.w", 24,
24000 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24002 /* mul.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
24004 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "mul.w", 24,
24005 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24007 /* mul.w${G} [$Src16An],${Dsp-16-s8}[fb] */
24009 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "mul.w", 24,
24010 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24012 /* mul.w${G} $Src16RnHI,${Dsp-16-u16} */
24014 M32C_INSN_MUL16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mul16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "mul.w", 32,
24015 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24017 /* mul.w${G} $Src16AnHI,${Dsp-16-u16} */
24019 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mul16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "mul.w", 32,
24020 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24022 /* mul.w${G} [$Src16An],${Dsp-16-u16} */
24024 M32C_INSN_MUL16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mul16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "mul.w", 32,
24025 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24027 /* mul.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
24029 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "mul.b", 24,
24030 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24032 /* mul.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
24034 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "mul.b", 24,
24035 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24037 /* mul.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
24039 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "mul.b", 24,
24040 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24042 /* mul.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
24044 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "mul.b", 24,
24045 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24047 /* mul.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
24049 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "mul.b", 24,
24050 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24052 /* mul.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
24054 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "mul.b", 24,
24055 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24057 /* mul.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
24059 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "mul.b", 24,
24060 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24062 /* mul.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
24064 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "mul.b", 24,
24065 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24067 /* mul.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
24069 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "mul.b", 24,
24070 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24072 /* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
24074 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "mul.b", 32,
24075 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24077 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
24079 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "mul.b", 32,
24080 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24082 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
24084 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "mul.b", 32,
24085 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24087 /* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
24089 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "mul.b", 40,
24090 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24092 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
24094 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "mul.b", 40,
24095 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24097 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
24099 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "mul.b", 40,
24100 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24102 /* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
24104 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "mul.b", 32,
24105 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24107 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
24109 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "mul.b", 32,
24110 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24112 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
24114 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "mul.b", 32,
24115 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24117 /* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
24119 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "mul.b", 40,
24120 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24122 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
24124 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "mul.b", 40,
24125 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24127 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
24129 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "mul.b", 40,
24130 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24132 /* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
24134 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "mul.b", 32,
24135 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24137 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
24139 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "mul.b", 32,
24140 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24142 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
24144 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "mul.b", 32,
24145 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24147 /* mul.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
24149 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mul16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "mul.b", 40,
24150 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24152 /* mul.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
24154 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mul16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "mul.b", 40,
24155 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24157 /* mul.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
24159 M32C_INSN_MUL16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mul16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "mul.b", 40,
24160 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24162 /* mul.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
24164 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "mul.b", 32,
24165 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24167 /* mul.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
24169 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "mul.b", 32,
24170 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24172 /* mul.b${G} ${Dsp-16-u16},$Dst16RnQI */
24174 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "mul.b", 32,
24175 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24177 /* mul.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
24179 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "mul.b", 32,
24180 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24182 /* mul.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
24184 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "mul.b", 32,
24185 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24187 /* mul.b${G} ${Dsp-16-u16},$Dst16AnQI */
24189 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "mul.b", 32,
24190 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24192 /* mul.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
24194 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "mul.b", 32,
24195 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24197 /* mul.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
24199 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "mul.b", 32,
24200 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24202 /* mul.b${G} ${Dsp-16-u16},[$Dst16An] */
24204 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "mul.b", 32,
24205 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24207 /* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
24209 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "mul.b", 40,
24210 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24212 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
24214 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "mul.b", 40,
24215 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24217 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
24219 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "mul.b", 40,
24220 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24222 /* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
24224 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "mul.b", 48,
24225 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24227 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
24229 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "mul.b", 48,
24230 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24232 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
24234 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "mul.b", 48,
24235 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24237 /* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
24239 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "mul.b", 40,
24240 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24242 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
24244 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "mul.b", 40,
24245 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24247 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
24249 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "mul.b", 40,
24250 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24252 /* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
24254 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "mul.b", 48,
24255 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24257 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
24259 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "mul.b", 48,
24260 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24262 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
24264 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "mul.b", 48,
24265 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24267 /* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
24269 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "mul.b", 40,
24270 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24272 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
24274 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "mul.b", 40,
24275 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24277 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
24279 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "mul.b", 40,
24280 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24282 /* mul.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
24284 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mul16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "mul.b", 48,
24285 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24287 /* mul.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
24289 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mul16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "mul.b", 48,
24290 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24292 /* mul.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
24294 M32C_INSN_MUL16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "mul16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "mul.b", 48,
24295 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24297 /* mul.b${G} $Src16RnQI,$Dst16RnQI */
24299 M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "mul.b", 16,
24300 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24302 /* mul.b${G} $Src16AnQI,$Dst16RnQI */
24304 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "mul.b", 16,
24305 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24307 /* mul.b${G} [$Src16An],$Dst16RnQI */
24309 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "mul.b", 16,
24310 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24312 /* mul.b${G} $Src16RnQI,$Dst16AnQI */
24314 M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "mul.b", 16,
24315 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24317 /* mul.b${G} $Src16AnQI,$Dst16AnQI */
24319 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "mul.b", 16,
24320 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24322 /* mul.b${G} [$Src16An],$Dst16AnQI */
24324 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "mul.b", 16,
24325 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24327 /* mul.b${G} $Src16RnQI,[$Dst16An] */
24329 M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "mul.b", 16,
24330 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24332 /* mul.b${G} $Src16AnQI,[$Dst16An] */
24334 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "mul.b", 16,
24335 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24337 /* mul.b${G} [$Src16An],[$Dst16An] */
24339 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "mul.b", 16,
24340 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24342 /* mul.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
24344 M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "mul.b", 24,
24345 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24347 /* mul.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
24349 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "mul.b", 24,
24350 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24352 /* mul.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
24354 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "mul.b", 24,
24355 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24357 /* mul.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
24359 M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "mul.b", 32,
24360 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24362 /* mul.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
24364 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "mul.b", 32,
24365 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24367 /* mul.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
24369 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "mul.b", 32,
24370 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24372 /* mul.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
24374 M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "mul.b", 24,
24375 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24377 /* mul.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
24379 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "mul.b", 24,
24380 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24382 /* mul.b${G} [$Src16An],${Dsp-16-u8}[sb] */
24384 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "mul.b", 24,
24385 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24387 /* mul.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
24389 M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "mul.b", 32,
24390 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24392 /* mul.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
24394 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "mul.b", 32,
24395 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24397 /* mul.b${G} [$Src16An],${Dsp-16-u16}[sb] */
24399 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "mul.b", 32,
24400 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24402 /* mul.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
24404 M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "mul.b", 24,
24405 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24407 /* mul.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
24409 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "mul.b", 24,
24410 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24412 /* mul.b${G} [$Src16An],${Dsp-16-s8}[fb] */
24414 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "mul.b", 24,
24415 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24417 /* mul.b${G} $Src16RnQI,${Dsp-16-u16} */
24419 M32C_INSN_MUL16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mul16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "mul.b", 32,
24420 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24422 /* mul.b${G} $Src16AnQI,${Dsp-16-u16} */
24424 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mul16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "mul.b", 32,
24425 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24427 /* mul.b${G} [$Src16An],${Dsp-16-u16} */
24429 M32C_INSN_MUL16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mul16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "mul.b", 32,
24430 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24432 /* mul.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
24434 M32C_INSN_MUL32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mul32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mul.w", 32,
24435 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24437 /* mul.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
24439 M32C_INSN_MUL32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mul32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mul.w", 32,
24440 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24442 /* mul.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
24444 M32C_INSN_MUL32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mul32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mul.w", 32,
24445 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24447 /* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
24449 M32C_INSN_MUL32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mul.w", 40,
24450 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24452 /* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
24454 M32C_INSN_MUL32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mul.w", 40,
24455 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24457 /* mul.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
24459 M32C_INSN_MUL32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mul.w", 40,
24460 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24462 /* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
24464 M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mul.w", 48,
24465 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24467 /* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
24469 M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mul.w", 48,
24470 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24472 /* mul.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
24474 M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mul.w", 48,
24475 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24477 /* mul.w${G} #${Imm-32-HI},${Dsp-16-u16} */
24479 M32C_INSN_MUL32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mul32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mul.w", 48,
24480 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24482 /* mul.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
24484 M32C_INSN_MUL32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mul32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mul.w", 56,
24485 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24487 /* mul.w${G} #${Imm-40-HI},${Dsp-16-u24} */
24489 M32C_INSN_MUL32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mul32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mul.w", 56,
24490 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24492 /* mul.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
24494 M32C_INSN_MUL32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mul32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mul.b", 24,
24495 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24497 /* mul.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
24499 M32C_INSN_MUL32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mul32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mul.b", 24,
24500 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24502 /* mul.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
24504 M32C_INSN_MUL32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mul32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mul.b", 24,
24505 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24507 /* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
24509 M32C_INSN_MUL32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mul.b", 32,
24510 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24512 /* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
24514 M32C_INSN_MUL32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mul.b", 32,
24515 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24517 /* mul.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
24519 M32C_INSN_MUL32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mul.b", 32,
24520 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24522 /* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
24524 M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mul.b", 40,
24525 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24527 /* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
24529 M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mul.b", 40,
24530 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24532 /* mul.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
24534 M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mul.b", 40,
24535 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24537 /* mul.b${G} #${Imm-32-QI},${Dsp-16-u16} */
24539 M32C_INSN_MUL32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mul32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mul.b", 40,
24540 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24542 /* mul.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
24544 M32C_INSN_MUL32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mul32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mul.b", 48,
24545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24547 /* mul.b${G} #${Imm-40-QI},${Dsp-16-u24} */
24549 M32C_INSN_MUL32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mul32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mul.b", 48,
24550 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24552 /* mul.w${G} #${Imm-16-HI},$Dst16RnHI */
24554 M32C_INSN_MUL16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "mul16.w-imm-G-basic-dst16-Rn-direct-HI", "mul.w", 32,
24555 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24557 /* mul.w${G} #${Imm-16-HI},$Dst16AnHI */
24559 M32C_INSN_MUL16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "mul16.w-imm-G-basic-dst16-An-direct-HI", "mul.w", 32,
24560 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24562 /* mul.w${G} #${Imm-16-HI},[$Dst16An] */
24564 M32C_INSN_MUL16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "mul16.w-imm-G-basic-dst16-An-indirect-HI", "mul.w", 32,
24565 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24567 /* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
24569 M32C_INSN_MUL16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "mul16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "mul.w", 40,
24570 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24572 /* mul.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
24574 M32C_INSN_MUL16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "mul16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "mul.w", 40,
24575 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24577 /* mul.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
24579 M32C_INSN_MUL16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "mul16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "mul.w", 40,
24580 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24582 /* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
24584 M32C_INSN_MUL16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "mul16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "mul.w", 48,
24585 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24587 /* mul.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
24589 M32C_INSN_MUL16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "mul16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "mul.w", 48,
24590 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24592 /* mul.w${G} #${Imm-32-HI},${Dsp-16-u16} */
24594 M32C_INSN_MUL16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "mul16.w-imm-G-16-16-dst16-16-16-absolute-HI", "mul.w", 48,
24595 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24597 /* mul.b${G} #${Imm-16-QI},$Dst16RnQI */
24599 M32C_INSN_MUL16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "mul16.b-imm-G-basic-dst16-Rn-direct-QI", "mul.b", 24,
24600 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24602 /* mul.b${G} #${Imm-16-QI},$Dst16AnQI */
24604 M32C_INSN_MUL16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "mul16.b-imm-G-basic-dst16-An-direct-QI", "mul.b", 24,
24605 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24607 /* mul.b${G} #${Imm-16-QI},[$Dst16An] */
24609 M32C_INSN_MUL16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "mul16.b-imm-G-basic-dst16-An-indirect-QI", "mul.b", 24,
24610 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24612 /* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
24614 M32C_INSN_MUL16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "mul16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "mul.b", 32,
24615 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24617 /* mul.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
24619 M32C_INSN_MUL16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "mul16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "mul.b", 32,
24620 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24622 /* mul.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
24624 M32C_INSN_MUL16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "mul16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "mul.b", 32,
24625 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24627 /* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
24629 M32C_INSN_MUL16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "mul16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "mul.b", 40,
24630 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24632 /* mul.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
24634 M32C_INSN_MUL16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "mul16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "mul.b", 40,
24635 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24637 /* mul.b${G} #${Imm-32-QI},${Dsp-16-u16} */
24639 M32C_INSN_MUL16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "mul16.b-imm-G-16-16-dst16-16-16-absolute-QI", "mul.b", 40,
24640 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
24642 /* movx${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
24644 M32C_INSN_MOVX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "movx32-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "movx", 24,
24645 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24647 /* movx${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
24649 M32C_INSN_MOVX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "movx32-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "movx", 24,
24650 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24652 /* movx${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
24654 M32C_INSN_MOVX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "movx32-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "movx", 24,
24655 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24657 /* movx${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
24659 M32C_INSN_MOVX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "movx", 32,
24660 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24662 /* movx${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
24664 M32C_INSN_MOVX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "movx", 32,
24665 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24667 /* movx${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
24669 M32C_INSN_MOVX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "movx", 32,
24670 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24672 /* movx${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
24674 M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "movx", 40,
24675 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24677 /* movx${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
24679 M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "movx", 40,
24680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24682 /* movx${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
24684 M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "movx", 40,
24685 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24687 /* movx${X} #${Imm-32-QI},${Dsp-16-u16} */
24689 M32C_INSN_MOVX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "movx32-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "movx", 40,
24690 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24692 /* movx${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
24694 M32C_INSN_MOVX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "movx32-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "movx", 48,
24695 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24697 /* movx${X} #${Imm-40-QI},${Dsp-16-u24} */
24699 M32C_INSN_MOVX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "movx32-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "movx", 48,
24700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24702 /* movhh $Dst32RnPrefixedQI,r0l */
24704 M32C_INSN_MOVHH32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI, "movhh32.src-r0l-dst32-Rn-direct-Prefixed-QI", "movhh", 24,
24705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24707 /* movhh $Dst32AnPrefixedQI,r0l */
24709 M32C_INSN_MOVHH32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, "movhh32.src-r0l-dst32-An-direct-Prefixed-QI", "movhh", 24,
24710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24712 /* movhh [$Dst32AnPrefixed],r0l */
24714 M32C_INSN_MOVHH32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, "movhh32.src-r0l-dst32-An-indirect-Prefixed-QI", "movhh", 24,
24715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24717 /* movhh ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */
24719 M32C_INSN_MOVHH32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-8-An-relative-Prefixed-QI", "movhh", 32,
24720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24722 /* movhh ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */
24724 M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-16-An-relative-Prefixed-QI", "movhh", 40,
24725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24727 /* movhh ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */
24729 M32C_INSN_MOVHH32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-24-An-relative-Prefixed-QI", "movhh", 48,
24730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24732 /* movhh ${Dsp-24-u8}[sb],r0l */
24734 M32C_INSN_MOVHH32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-8-SB-relative-Prefixed-QI", "movhh", 32,
24735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24737 /* movhh ${Dsp-24-u16}[sb],r0l */
24739 M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-16-SB-relative-Prefixed-QI", "movhh", 40,
24740 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24742 /* movhh ${Dsp-24-s8}[fb],r0l */
24744 M32C_INSN_MOVHH32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-8-FB-relative-Prefixed-QI", "movhh", 32,
24745 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24747 /* movhh ${Dsp-24-s16}[fb],r0l */
24749 M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-16-FB-relative-Prefixed-QI", "movhh", 40,
24750 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24752 /* movhh ${Dsp-24-u16},r0l */
24754 M32C_INSN_MOVHH32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-16-absolute-Prefixed-QI", "movhh", 40,
24755 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24757 /* movhh ${Dsp-24-u24},r0l */
24759 M32C_INSN_MOVHH32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movhh32.src-r0l-dst32-24-24-absolute-Prefixed-QI", "movhh", 48,
24760 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24762 /* movhl $Dst32RnPrefixedQI,r0l */
24764 M32C_INSN_MOVHL32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI, "movhl32.src-r0l-dst32-Rn-direct-Prefixed-QI", "movhl", 24,
24765 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24767 /* movhl $Dst32AnPrefixedQI,r0l */
24769 M32C_INSN_MOVHL32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, "movhl32.src-r0l-dst32-An-direct-Prefixed-QI", "movhl", 24,
24770 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24772 /* movhl [$Dst32AnPrefixed],r0l */
24774 M32C_INSN_MOVHL32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, "movhl32.src-r0l-dst32-An-indirect-Prefixed-QI", "movhl", 24,
24775 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24777 /* movhl ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */
24779 M32C_INSN_MOVHL32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-8-An-relative-Prefixed-QI", "movhl", 32,
24780 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24782 /* movhl ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */
24784 M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-16-An-relative-Prefixed-QI", "movhl", 40,
24785 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24787 /* movhl ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */
24789 M32C_INSN_MOVHL32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-24-An-relative-Prefixed-QI", "movhl", 48,
24790 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24792 /* movhl ${Dsp-24-u8}[sb],r0l */
24794 M32C_INSN_MOVHL32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-8-SB-relative-Prefixed-QI", "movhl", 32,
24795 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24797 /* movhl ${Dsp-24-u16}[sb],r0l */
24799 M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-16-SB-relative-Prefixed-QI", "movhl", 40,
24800 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24802 /* movhl ${Dsp-24-s8}[fb],r0l */
24804 M32C_INSN_MOVHL32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-8-FB-relative-Prefixed-QI", "movhl", 32,
24805 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24807 /* movhl ${Dsp-24-s16}[fb],r0l */
24809 M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-16-FB-relative-Prefixed-QI", "movhl", 40,
24810 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24812 /* movhl ${Dsp-24-u16},r0l */
24814 M32C_INSN_MOVHL32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-16-absolute-Prefixed-QI", "movhl", 40,
24815 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24817 /* movhl ${Dsp-24-u24},r0l */
24819 M32C_INSN_MOVHL32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movhl32.src-r0l-dst32-24-24-absolute-Prefixed-QI", "movhl", 48,
24820 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24822 /* movlh $Dst32RnPrefixedQI,r0l */
24824 M32C_INSN_MOVLH32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI, "movlh32.src-r0l-dst32-Rn-direct-Prefixed-QI", "movlh", 24,
24825 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24827 /* movlh $Dst32AnPrefixedQI,r0l */
24829 M32C_INSN_MOVLH32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, "movlh32.src-r0l-dst32-An-direct-Prefixed-QI", "movlh", 24,
24830 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24832 /* movlh [$Dst32AnPrefixed],r0l */
24834 M32C_INSN_MOVLH32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, "movlh32.src-r0l-dst32-An-indirect-Prefixed-QI", "movlh", 24,
24835 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24837 /* movlh ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */
24839 M32C_INSN_MOVLH32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-8-An-relative-Prefixed-QI", "movlh", 32,
24840 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24842 /* movlh ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */
24844 M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-16-An-relative-Prefixed-QI", "movlh", 40,
24845 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24847 /* movlh ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */
24849 M32C_INSN_MOVLH32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-24-An-relative-Prefixed-QI", "movlh", 48,
24850 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24852 /* movlh ${Dsp-24-u8}[sb],r0l */
24854 M32C_INSN_MOVLH32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-8-SB-relative-Prefixed-QI", "movlh", 32,
24855 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24857 /* movlh ${Dsp-24-u16}[sb],r0l */
24859 M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-16-SB-relative-Prefixed-QI", "movlh", 40,
24860 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24862 /* movlh ${Dsp-24-s8}[fb],r0l */
24864 M32C_INSN_MOVLH32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-8-FB-relative-Prefixed-QI", "movlh", 32,
24865 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24867 /* movlh ${Dsp-24-s16}[fb],r0l */
24869 M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-16-FB-relative-Prefixed-QI", "movlh", 40,
24870 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24872 /* movlh ${Dsp-24-u16},r0l */
24874 M32C_INSN_MOVLH32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-16-absolute-Prefixed-QI", "movlh", 40,
24875 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24877 /* movlh ${Dsp-24-u24},r0l */
24879 M32C_INSN_MOVLH32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movlh32.src-r0l-dst32-24-24-absolute-Prefixed-QI", "movlh", 48,
24880 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24882 /* movll $Dst32RnPrefixedQI,r0l */
24884 M32C_INSN_MOVLL32_SRC_R0L_DST32_RN_DIRECT_PREFIXED_QI, "movll32.src-r0l-dst32-Rn-direct-Prefixed-QI", "movll", 24,
24885 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24887 /* movll $Dst32AnPrefixedQI,r0l */
24889 M32C_INSN_MOVLL32_SRC_R0L_DST32_AN_DIRECT_PREFIXED_QI, "movll32.src-r0l-dst32-An-direct-Prefixed-QI", "movll", 24,
24890 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24892 /* movll [$Dst32AnPrefixed],r0l */
24894 M32C_INSN_MOVLL32_SRC_R0L_DST32_AN_INDIRECT_PREFIXED_QI, "movll32.src-r0l-dst32-An-indirect-Prefixed-QI", "movll", 24,
24895 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24897 /* movll ${Dsp-24-u8}[$Dst32AnPrefixed],r0l */
24899 M32C_INSN_MOVLL32_SRC_R0L_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-8-An-relative-Prefixed-QI", "movll", 32,
24900 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24902 /* movll ${Dsp-24-u16}[$Dst32AnPrefixed],r0l */
24904 M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-16-An-relative-Prefixed-QI", "movll", 40,
24905 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24907 /* movll ${Dsp-24-u24}[$Dst32AnPrefixed],r0l */
24909 M32C_INSN_MOVLL32_SRC_R0L_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-24-An-relative-Prefixed-QI", "movll", 48,
24910 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24912 /* movll ${Dsp-24-u8}[sb],r0l */
24914 M32C_INSN_MOVLL32_SRC_R0L_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-8-SB-relative-Prefixed-QI", "movll", 32,
24915 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24917 /* movll ${Dsp-24-u16}[sb],r0l */
24919 M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-16-SB-relative-Prefixed-QI", "movll", 40,
24920 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24922 /* movll ${Dsp-24-s8}[fb],r0l */
24924 M32C_INSN_MOVLL32_SRC_R0L_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-8-FB-relative-Prefixed-QI", "movll", 32,
24925 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24927 /* movll ${Dsp-24-s16}[fb],r0l */
24929 M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movll32.src-r0l-dst32-24-16-FB-relative-Prefixed-QI", "movll", 40,
24930 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24932 /* movll ${Dsp-24-u16},r0l */
24934 M32C_INSN_MOVLL32_SRC_R0L_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movll32.src-r0l-dst32-24-16-absolute-Prefixed-QI", "movll", 40,
24935 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24937 /* movll ${Dsp-24-u24},r0l */
24939 M32C_INSN_MOVLL32_SRC_R0L_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movll32.src-r0l-dst32-24-24-absolute-Prefixed-QI", "movll", 48,
24940 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24942 /* movhh r0l,$Dst32RnPrefixedQI */
24944 M32C_INSN_MOVHH32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI, "movhh32.r0l-dst-dst32-Rn-direct-Prefixed-QI", "movhh", 24,
24945 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24947 /* movhh r0l,$Dst32AnPrefixedQI */
24949 M32C_INSN_MOVHH32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, "movhh32.r0l-dst-dst32-An-direct-Prefixed-QI", "movhh", 24,
24950 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24952 /* movhh r0l,[$Dst32AnPrefixed] */
24954 M32C_INSN_MOVHH32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, "movhh32.r0l-dst-dst32-An-indirect-Prefixed-QI", "movhh", 24,
24955 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24957 /* movhh r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */
24959 M32C_INSN_MOVHH32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-8-An-relative-Prefixed-QI", "movhh", 32,
24960 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24962 /* movhh r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */
24964 M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-16-An-relative-Prefixed-QI", "movhh", 40,
24965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24967 /* movhh r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */
24969 M32C_INSN_MOVHH32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-24-An-relative-Prefixed-QI", "movhh", 48,
24970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24972 /* movhh r0l,${Dsp-24-u8}[sb] */
24974 M32C_INSN_MOVHH32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-8-SB-relative-Prefixed-QI", "movhh", 32,
24975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24977 /* movhh r0l,${Dsp-24-u16}[sb] */
24979 M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-16-SB-relative-Prefixed-QI", "movhh", 40,
24980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24982 /* movhh r0l,${Dsp-24-s8}[fb] */
24984 M32C_INSN_MOVHH32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-8-FB-relative-Prefixed-QI", "movhh", 32,
24985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24987 /* movhh r0l,${Dsp-24-s16}[fb] */
24989 M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-16-FB-relative-Prefixed-QI", "movhh", 40,
24990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24992 /* movhh r0l,${Dsp-24-u16} */
24994 M32C_INSN_MOVHH32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-16-absolute-Prefixed-QI", "movhh", 40,
24995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
24997 /* movhh r0l,${Dsp-24-u24} */
24999 M32C_INSN_MOVHH32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movhh32.r0l-dst-dst32-24-24-absolute-Prefixed-QI", "movhh", 48,
25000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25002 /* movhl r0l,$Dst32RnPrefixedQI */
25004 M32C_INSN_MOVHL32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI, "movhl32.r0l-dst-dst32-Rn-direct-Prefixed-QI", "movhl", 24,
25005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25007 /* movhl r0l,$Dst32AnPrefixedQI */
25009 M32C_INSN_MOVHL32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, "movhl32.r0l-dst-dst32-An-direct-Prefixed-QI", "movhl", 24,
25010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25012 /* movhl r0l,[$Dst32AnPrefixed] */
25014 M32C_INSN_MOVHL32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, "movhl32.r0l-dst-dst32-An-indirect-Prefixed-QI", "movhl", 24,
25015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25017 /* movhl r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */
25019 M32C_INSN_MOVHL32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-8-An-relative-Prefixed-QI", "movhl", 32,
25020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25022 /* movhl r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */
25024 M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-16-An-relative-Prefixed-QI", "movhl", 40,
25025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25027 /* movhl r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */
25029 M32C_INSN_MOVHL32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-24-An-relative-Prefixed-QI", "movhl", 48,
25030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25032 /* movhl r0l,${Dsp-24-u8}[sb] */
25034 M32C_INSN_MOVHL32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-8-SB-relative-Prefixed-QI", "movhl", 32,
25035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25037 /* movhl r0l,${Dsp-24-u16}[sb] */
25039 M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-16-SB-relative-Prefixed-QI", "movhl", 40,
25040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25042 /* movhl r0l,${Dsp-24-s8}[fb] */
25044 M32C_INSN_MOVHL32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-8-FB-relative-Prefixed-QI", "movhl", 32,
25045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25047 /* movhl r0l,${Dsp-24-s16}[fb] */
25049 M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-16-FB-relative-Prefixed-QI", "movhl", 40,
25050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25052 /* movhl r0l,${Dsp-24-u16} */
25054 M32C_INSN_MOVHL32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-16-absolute-Prefixed-QI", "movhl", 40,
25055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25057 /* movhl r0l,${Dsp-24-u24} */
25059 M32C_INSN_MOVHL32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movhl32.r0l-dst-dst32-24-24-absolute-Prefixed-QI", "movhl", 48,
25060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25062 /* movlh r0l,$Dst32RnPrefixedQI */
25064 M32C_INSN_MOVLH32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI, "movlh32.r0l-dst-dst32-Rn-direct-Prefixed-QI", "movlh", 24,
25065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25067 /* movlh r0l,$Dst32AnPrefixedQI */
25069 M32C_INSN_MOVLH32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, "movlh32.r0l-dst-dst32-An-direct-Prefixed-QI", "movlh", 24,
25070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25072 /* movlh r0l,[$Dst32AnPrefixed] */
25074 M32C_INSN_MOVLH32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, "movlh32.r0l-dst-dst32-An-indirect-Prefixed-QI", "movlh", 24,
25075 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25077 /* movlh r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */
25079 M32C_INSN_MOVLH32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-8-An-relative-Prefixed-QI", "movlh", 32,
25080 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25082 /* movlh r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */
25084 M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-16-An-relative-Prefixed-QI", "movlh", 40,
25085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25087 /* movlh r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */
25089 M32C_INSN_MOVLH32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-24-An-relative-Prefixed-QI", "movlh", 48,
25090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25092 /* movlh r0l,${Dsp-24-u8}[sb] */
25094 M32C_INSN_MOVLH32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-8-SB-relative-Prefixed-QI", "movlh", 32,
25095 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25097 /* movlh r0l,${Dsp-24-u16}[sb] */
25099 M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-16-SB-relative-Prefixed-QI", "movlh", 40,
25100 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25102 /* movlh r0l,${Dsp-24-s8}[fb] */
25104 M32C_INSN_MOVLH32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-8-FB-relative-Prefixed-QI", "movlh", 32,
25105 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25107 /* movlh r0l,${Dsp-24-s16}[fb] */
25109 M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-16-FB-relative-Prefixed-QI", "movlh", 40,
25110 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25112 /* movlh r0l,${Dsp-24-u16} */
25114 M32C_INSN_MOVLH32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-16-absolute-Prefixed-QI", "movlh", 40,
25115 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25117 /* movlh r0l,${Dsp-24-u24} */
25119 M32C_INSN_MOVLH32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movlh32.r0l-dst-dst32-24-24-absolute-Prefixed-QI", "movlh", 48,
25120 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25122 /* movll r0l,$Dst32RnPrefixedQI */
25124 M32C_INSN_MOVLL32_R0L_DST_DST32_RN_DIRECT_PREFIXED_QI, "movll32.r0l-dst-dst32-Rn-direct-Prefixed-QI", "movll", 24,
25125 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25127 /* movll r0l,$Dst32AnPrefixedQI */
25129 M32C_INSN_MOVLL32_R0L_DST_DST32_AN_DIRECT_PREFIXED_QI, "movll32.r0l-dst-dst32-An-direct-Prefixed-QI", "movll", 24,
25130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25132 /* movll r0l,[$Dst32AnPrefixed] */
25134 M32C_INSN_MOVLL32_R0L_DST_DST32_AN_INDIRECT_PREFIXED_QI, "movll32.r0l-dst-dst32-An-indirect-Prefixed-QI", "movll", 24,
25135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25137 /* movll r0l,${Dsp-24-u8}[$Dst32AnPrefixed] */
25139 M32C_INSN_MOVLL32_R0L_DST_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-8-An-relative-Prefixed-QI", "movll", 32,
25140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25142 /* movll r0l,${Dsp-24-u16}[$Dst32AnPrefixed] */
25144 M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-16-An-relative-Prefixed-QI", "movll", 40,
25145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25147 /* movll r0l,${Dsp-24-u24}[$Dst32AnPrefixed] */
25149 M32C_INSN_MOVLL32_R0L_DST_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-24-An-relative-Prefixed-QI", "movll", 48,
25150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25152 /* movll r0l,${Dsp-24-u8}[sb] */
25154 M32C_INSN_MOVLL32_R0L_DST_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-8-SB-relative-Prefixed-QI", "movll", 32,
25155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25157 /* movll r0l,${Dsp-24-u16}[sb] */
25159 M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-16-SB-relative-Prefixed-QI", "movll", 40,
25160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25162 /* movll r0l,${Dsp-24-s8}[fb] */
25164 M32C_INSN_MOVLL32_R0L_DST_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-8-FB-relative-Prefixed-QI", "movll", 32,
25165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25167 /* movll r0l,${Dsp-24-s16}[fb] */
25169 M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-16-FB-relative-Prefixed-QI", "movll", 40,
25170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25172 /* movll r0l,${Dsp-24-u16} */
25174 M32C_INSN_MOVLL32_R0L_DST_DST32_24_16_ABSOLUTE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-16-absolute-Prefixed-QI", "movll", 40,
25175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25177 /* movll r0l,${Dsp-24-u24} */
25179 M32C_INSN_MOVLL32_R0L_DST_DST32_24_24_ABSOLUTE_PREFIXED_QI, "movll32.r0l-dst-dst32-24-24-absolute-Prefixed-QI", "movll", 48,
25180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25182 /* movhh $Dst16RnQI,r0l */
25184 M32C_INSN_MOVHH16_SRC_R0L_DST16_RN_DIRECT_QI, "movhh16.src-r0l-dst16-Rn-direct-QI", "movhh", 16,
25185 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25187 /* movhh $Dst16AnQI,r0l */
25189 M32C_INSN_MOVHH16_SRC_R0L_DST16_AN_DIRECT_QI, "movhh16.src-r0l-dst16-An-direct-QI", "movhh", 16,
25190 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25192 /* movhh [$Dst16An],r0l */
25194 M32C_INSN_MOVHH16_SRC_R0L_DST16_AN_INDIRECT_QI, "movhh16.src-r0l-dst16-An-indirect-QI", "movhh", 16,
25195 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25197 /* movhh ${Dsp-16-u8}[$Dst16An],r0l */
25199 M32C_INSN_MOVHH16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, "movhh16.src-r0l-dst16-16-8-An-relative-QI", "movhh", 24,
25200 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25202 /* movhh ${Dsp-16-u16}[$Dst16An],r0l */
25204 M32C_INSN_MOVHH16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, "movhh16.src-r0l-dst16-16-16-An-relative-QI", "movhh", 32,
25205 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25207 /* movhh ${Dsp-16-u8}[sb],r0l */
25209 M32C_INSN_MOVHH16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, "movhh16.src-r0l-dst16-16-8-SB-relative-QI", "movhh", 24,
25210 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25212 /* movhh ${Dsp-16-u16}[sb],r0l */
25214 M32C_INSN_MOVHH16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, "movhh16.src-r0l-dst16-16-16-SB-relative-QI", "movhh", 32,
25215 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25217 /* movhh ${Dsp-16-s8}[fb],r0l */
25219 M32C_INSN_MOVHH16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, "movhh16.src-r0l-dst16-16-8-FB-relative-QI", "movhh", 24,
25220 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25222 /* movhh ${Dsp-16-u16},r0l */
25224 M32C_INSN_MOVHH16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, "movhh16.src-r0l-dst16-16-16-absolute-QI", "movhh", 32,
25225 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25227 /* movhl $Dst16RnQI,r0l */
25229 M32C_INSN_MOVHL16_SRC_R0L_DST16_RN_DIRECT_QI, "movhl16.src-r0l-dst16-Rn-direct-QI", "movhl", 16,
25230 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25232 /* movhl $Dst16AnQI,r0l */
25234 M32C_INSN_MOVHL16_SRC_R0L_DST16_AN_DIRECT_QI, "movhl16.src-r0l-dst16-An-direct-QI", "movhl", 16,
25235 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25237 /* movhl [$Dst16An],r0l */
25239 M32C_INSN_MOVHL16_SRC_R0L_DST16_AN_INDIRECT_QI, "movhl16.src-r0l-dst16-An-indirect-QI", "movhl", 16,
25240 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25242 /* movhl ${Dsp-16-u8}[$Dst16An],r0l */
25244 M32C_INSN_MOVHL16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, "movhl16.src-r0l-dst16-16-8-An-relative-QI", "movhl", 24,
25245 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25247 /* movhl ${Dsp-16-u16}[$Dst16An],r0l */
25249 M32C_INSN_MOVHL16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, "movhl16.src-r0l-dst16-16-16-An-relative-QI", "movhl", 32,
25250 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25252 /* movhl ${Dsp-16-u8}[sb],r0l */
25254 M32C_INSN_MOVHL16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, "movhl16.src-r0l-dst16-16-8-SB-relative-QI", "movhl", 24,
25255 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25257 /* movhl ${Dsp-16-u16}[sb],r0l */
25259 M32C_INSN_MOVHL16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, "movhl16.src-r0l-dst16-16-16-SB-relative-QI", "movhl", 32,
25260 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25262 /* movhl ${Dsp-16-s8}[fb],r0l */
25264 M32C_INSN_MOVHL16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, "movhl16.src-r0l-dst16-16-8-FB-relative-QI", "movhl", 24,
25265 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25267 /* movhl ${Dsp-16-u16},r0l */
25269 M32C_INSN_MOVHL16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, "movhl16.src-r0l-dst16-16-16-absolute-QI", "movhl", 32,
25270 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25272 /* movlh $Dst16RnQI,r0l */
25274 M32C_INSN_MOVLH16_SRC_R0L_DST16_RN_DIRECT_QI, "movlh16.src-r0l-dst16-Rn-direct-QI", "movlh", 16,
25275 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25277 /* movlh $Dst16AnQI,r0l */
25279 M32C_INSN_MOVLH16_SRC_R0L_DST16_AN_DIRECT_QI, "movlh16.src-r0l-dst16-An-direct-QI", "movlh", 16,
25280 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25282 /* movlh [$Dst16An],r0l */
25284 M32C_INSN_MOVLH16_SRC_R0L_DST16_AN_INDIRECT_QI, "movlh16.src-r0l-dst16-An-indirect-QI", "movlh", 16,
25285 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25287 /* movlh ${Dsp-16-u8}[$Dst16An],r0l */
25289 M32C_INSN_MOVLH16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, "movlh16.src-r0l-dst16-16-8-An-relative-QI", "movlh", 24,
25290 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25292 /* movlh ${Dsp-16-u16}[$Dst16An],r0l */
25294 M32C_INSN_MOVLH16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, "movlh16.src-r0l-dst16-16-16-An-relative-QI", "movlh", 32,
25295 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25297 /* movlh ${Dsp-16-u8}[sb],r0l */
25299 M32C_INSN_MOVLH16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, "movlh16.src-r0l-dst16-16-8-SB-relative-QI", "movlh", 24,
25300 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25302 /* movlh ${Dsp-16-u16}[sb],r0l */
25304 M32C_INSN_MOVLH16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, "movlh16.src-r0l-dst16-16-16-SB-relative-QI", "movlh", 32,
25305 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25307 /* movlh ${Dsp-16-s8}[fb],r0l */
25309 M32C_INSN_MOVLH16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, "movlh16.src-r0l-dst16-16-8-FB-relative-QI", "movlh", 24,
25310 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25312 /* movlh ${Dsp-16-u16},r0l */
25314 M32C_INSN_MOVLH16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, "movlh16.src-r0l-dst16-16-16-absolute-QI", "movlh", 32,
25315 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25317 /* movll $Dst16RnQI,r0l */
25319 M32C_INSN_MOVLL16_SRC_R0L_DST16_RN_DIRECT_QI, "movll16.src-r0l-dst16-Rn-direct-QI", "movll", 16,
25320 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25322 /* movll $Dst16AnQI,r0l */
25324 M32C_INSN_MOVLL16_SRC_R0L_DST16_AN_DIRECT_QI, "movll16.src-r0l-dst16-An-direct-QI", "movll", 16,
25325 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25327 /* movll [$Dst16An],r0l */
25329 M32C_INSN_MOVLL16_SRC_R0L_DST16_AN_INDIRECT_QI, "movll16.src-r0l-dst16-An-indirect-QI", "movll", 16,
25330 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25332 /* movll ${Dsp-16-u8}[$Dst16An],r0l */
25334 M32C_INSN_MOVLL16_SRC_R0L_DST16_16_8_AN_RELATIVE_QI, "movll16.src-r0l-dst16-16-8-An-relative-QI", "movll", 24,
25335 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25337 /* movll ${Dsp-16-u16}[$Dst16An],r0l */
25339 M32C_INSN_MOVLL16_SRC_R0L_DST16_16_16_AN_RELATIVE_QI, "movll16.src-r0l-dst16-16-16-An-relative-QI", "movll", 32,
25340 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25342 /* movll ${Dsp-16-u8}[sb],r0l */
25344 M32C_INSN_MOVLL16_SRC_R0L_DST16_16_8_SB_RELATIVE_QI, "movll16.src-r0l-dst16-16-8-SB-relative-QI", "movll", 24,
25345 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25347 /* movll ${Dsp-16-u16}[sb],r0l */
25349 M32C_INSN_MOVLL16_SRC_R0L_DST16_16_16_SB_RELATIVE_QI, "movll16.src-r0l-dst16-16-16-SB-relative-QI", "movll", 32,
25350 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25352 /* movll ${Dsp-16-s8}[fb],r0l */
25354 M32C_INSN_MOVLL16_SRC_R0L_DST16_16_8_FB_RELATIVE_QI, "movll16.src-r0l-dst16-16-8-FB-relative-QI", "movll", 24,
25355 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25357 /* movll ${Dsp-16-u16},r0l */
25359 M32C_INSN_MOVLL16_SRC_R0L_DST16_16_16_ABSOLUTE_QI, "movll16.src-r0l-dst16-16-16-absolute-QI", "movll", 32,
25360 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25362 /* movhh r0l,$Dst16RnQI */
25364 M32C_INSN_MOVHH16_R0L_DST_DST16_RN_DIRECT_QI, "movhh16.r0l-dst-dst16-Rn-direct-QI", "movhh", 16,
25365 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25367 /* movhh r0l,$Dst16AnQI */
25369 M32C_INSN_MOVHH16_R0L_DST_DST16_AN_DIRECT_QI, "movhh16.r0l-dst-dst16-An-direct-QI", "movhh", 16,
25370 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25372 /* movhh r0l,[$Dst16An] */
25374 M32C_INSN_MOVHH16_R0L_DST_DST16_AN_INDIRECT_QI, "movhh16.r0l-dst-dst16-An-indirect-QI", "movhh", 16,
25375 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25377 /* movhh r0l,${Dsp-16-u8}[$Dst16An] */
25379 M32C_INSN_MOVHH16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-8-An-relative-QI", "movhh", 24,
25380 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25382 /* movhh r0l,${Dsp-16-u16}[$Dst16An] */
25384 M32C_INSN_MOVHH16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-16-An-relative-QI", "movhh", 32,
25385 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25387 /* movhh r0l,${Dsp-16-u8}[sb] */
25389 M32C_INSN_MOVHH16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-8-SB-relative-QI", "movhh", 24,
25390 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25392 /* movhh r0l,${Dsp-16-u16}[sb] */
25394 M32C_INSN_MOVHH16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-16-SB-relative-QI", "movhh", 32,
25395 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25397 /* movhh r0l,${Dsp-16-s8}[fb] */
25399 M32C_INSN_MOVHH16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, "movhh16.r0l-dst-dst16-16-8-FB-relative-QI", "movhh", 24,
25400 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25402 /* movhh r0l,${Dsp-16-u16} */
25404 M32C_INSN_MOVHH16_R0L_DST_DST16_16_16_ABSOLUTE_QI, "movhh16.r0l-dst-dst16-16-16-absolute-QI", "movhh", 32,
25405 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25407 /* movhl r0l,$Dst16RnQI */
25409 M32C_INSN_MOVHL16_R0L_DST_DST16_RN_DIRECT_QI, "movhl16.r0l-dst-dst16-Rn-direct-QI", "movhl", 16,
25410 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25412 /* movhl r0l,$Dst16AnQI */
25414 M32C_INSN_MOVHL16_R0L_DST_DST16_AN_DIRECT_QI, "movhl16.r0l-dst-dst16-An-direct-QI", "movhl", 16,
25415 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25417 /* movhl r0l,[$Dst16An] */
25419 M32C_INSN_MOVHL16_R0L_DST_DST16_AN_INDIRECT_QI, "movhl16.r0l-dst-dst16-An-indirect-QI", "movhl", 16,
25420 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25422 /* movhl r0l,${Dsp-16-u8}[$Dst16An] */
25424 M32C_INSN_MOVHL16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-8-An-relative-QI", "movhl", 24,
25425 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25427 /* movhl r0l,${Dsp-16-u16}[$Dst16An] */
25429 M32C_INSN_MOVHL16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-16-An-relative-QI", "movhl", 32,
25430 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25432 /* movhl r0l,${Dsp-16-u8}[sb] */
25434 M32C_INSN_MOVHL16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-8-SB-relative-QI", "movhl", 24,
25435 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25437 /* movhl r0l,${Dsp-16-u16}[sb] */
25439 M32C_INSN_MOVHL16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-16-SB-relative-QI", "movhl", 32,
25440 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25442 /* movhl r0l,${Dsp-16-s8}[fb] */
25444 M32C_INSN_MOVHL16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, "movhl16.r0l-dst-dst16-16-8-FB-relative-QI", "movhl", 24,
25445 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25447 /* movhl r0l,${Dsp-16-u16} */
25449 M32C_INSN_MOVHL16_R0L_DST_DST16_16_16_ABSOLUTE_QI, "movhl16.r0l-dst-dst16-16-16-absolute-QI", "movhl", 32,
25450 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25452 /* movlh r0l,$Dst16RnQI */
25454 M32C_INSN_MOVLH16_R0L_DST_DST16_RN_DIRECT_QI, "movlh16.r0l-dst-dst16-Rn-direct-QI", "movlh", 16,
25455 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25457 /* movlh r0l,$Dst16AnQI */
25459 M32C_INSN_MOVLH16_R0L_DST_DST16_AN_DIRECT_QI, "movlh16.r0l-dst-dst16-An-direct-QI", "movlh", 16,
25460 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25462 /* movlh r0l,[$Dst16An] */
25464 M32C_INSN_MOVLH16_R0L_DST_DST16_AN_INDIRECT_QI, "movlh16.r0l-dst-dst16-An-indirect-QI", "movlh", 16,
25465 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25467 /* movlh r0l,${Dsp-16-u8}[$Dst16An] */
25469 M32C_INSN_MOVLH16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-8-An-relative-QI", "movlh", 24,
25470 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25472 /* movlh r0l,${Dsp-16-u16}[$Dst16An] */
25474 M32C_INSN_MOVLH16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-16-An-relative-QI", "movlh", 32,
25475 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25477 /* movlh r0l,${Dsp-16-u8}[sb] */
25479 M32C_INSN_MOVLH16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-8-SB-relative-QI", "movlh", 24,
25480 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25482 /* movlh r0l,${Dsp-16-u16}[sb] */
25484 M32C_INSN_MOVLH16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-16-SB-relative-QI", "movlh", 32,
25485 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25487 /* movlh r0l,${Dsp-16-s8}[fb] */
25489 M32C_INSN_MOVLH16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, "movlh16.r0l-dst-dst16-16-8-FB-relative-QI", "movlh", 24,
25490 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25492 /* movlh r0l,${Dsp-16-u16} */
25494 M32C_INSN_MOVLH16_R0L_DST_DST16_16_16_ABSOLUTE_QI, "movlh16.r0l-dst-dst16-16-16-absolute-QI", "movlh", 32,
25495 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25497 /* movll r0l,$Dst16RnQI */
25499 M32C_INSN_MOVLL16_R0L_DST_DST16_RN_DIRECT_QI, "movll16.r0l-dst-dst16-Rn-direct-QI", "movll", 16,
25500 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25502 /* movll r0l,$Dst16AnQI */
25504 M32C_INSN_MOVLL16_R0L_DST_DST16_AN_DIRECT_QI, "movll16.r0l-dst-dst16-An-direct-QI", "movll", 16,
25505 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25507 /* movll r0l,[$Dst16An] */
25509 M32C_INSN_MOVLL16_R0L_DST_DST16_AN_INDIRECT_QI, "movll16.r0l-dst-dst16-An-indirect-QI", "movll", 16,
25510 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25512 /* movll r0l,${Dsp-16-u8}[$Dst16An] */
25514 M32C_INSN_MOVLL16_R0L_DST_DST16_16_8_AN_RELATIVE_QI, "movll16.r0l-dst-dst16-16-8-An-relative-QI", "movll", 24,
25515 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25517 /* movll r0l,${Dsp-16-u16}[$Dst16An] */
25519 M32C_INSN_MOVLL16_R0L_DST_DST16_16_16_AN_RELATIVE_QI, "movll16.r0l-dst-dst16-16-16-An-relative-QI", "movll", 32,
25520 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25522 /* movll r0l,${Dsp-16-u8}[sb] */
25524 M32C_INSN_MOVLL16_R0L_DST_DST16_16_8_SB_RELATIVE_QI, "movll16.r0l-dst-dst16-16-8-SB-relative-QI", "movll", 24,
25525 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25527 /* movll r0l,${Dsp-16-u16}[sb] */
25529 M32C_INSN_MOVLL16_R0L_DST_DST16_16_16_SB_RELATIVE_QI, "movll16.r0l-dst-dst16-16-16-SB-relative-QI", "movll", 32,
25530 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25532 /* movll r0l,${Dsp-16-s8}[fb] */
25534 M32C_INSN_MOVLL16_R0L_DST_DST16_16_8_FB_RELATIVE_QI, "movll16.r0l-dst-dst16-16-8-FB-relative-QI", "movll", 24,
25535 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25537 /* movll r0l,${Dsp-16-u16} */
25539 M32C_INSN_MOVLL16_R0L_DST_DST16_16_16_ABSOLUTE_QI, "movll16.r0l-dst-dst16-16-16-absolute-QI", "movll", 32,
25540 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25542 /* mova [$Dst32AnUnprefixed],a1 */
25544 M32C_INSN_MOVA32_SRC_A1_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-An-indirect-Unprefixed-Mova-SI", "mova", 16,
25545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25547 /* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],a1 */
25549 M32C_INSN_MOVA32_SRC_A1_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-8-An-relative-Unprefixed-Mova-SI", "mova", 24,
25550 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25552 /* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],a1 */
25554 M32C_INSN_MOVA32_SRC_A1_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-16-An-relative-Unprefixed-Mova-SI", "mova", 32,
25555 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25557 /* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],a1 */
25559 M32C_INSN_MOVA32_SRC_A1_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-24-An-relative-Unprefixed-Mova-SI", "mova", 40,
25560 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25562 /* mova ${Dsp-16-u8}[sb],a1 */
25564 M32C_INSN_MOVA32_SRC_A1_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "mova", 24,
25565 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25567 /* mova ${Dsp-16-u16}[sb],a1 */
25569 M32C_INSN_MOVA32_SRC_A1_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "mova", 32,
25570 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25572 /* mova ${Dsp-16-s8}[fb],a1 */
25574 M32C_INSN_MOVA32_SRC_A1_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "mova", 24,
25575 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25577 /* mova ${Dsp-16-s16}[fb],a1 */
25579 M32C_INSN_MOVA32_SRC_A1_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "mova", 32,
25580 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25582 /* mova ${Dsp-16-u16},a1 */
25584 M32C_INSN_MOVA32_SRC_A1_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-16-absolute-Unprefixed-Mova-SI", "mova", 32,
25585 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25587 /* mova ${Dsp-16-u24},a1 */
25589 M32C_INSN_MOVA32_SRC_A1_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-a1-dst32-16-24-absolute-Unprefixed-Mova-SI", "mova", 40,
25590 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25592 /* mova [$Dst32AnUnprefixed],a0 */
25594 M32C_INSN_MOVA32_SRC_A0_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-An-indirect-Unprefixed-Mova-SI", "mova", 16,
25595 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25597 /* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],a0 */
25599 M32C_INSN_MOVA32_SRC_A0_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-8-An-relative-Unprefixed-Mova-SI", "mova", 24,
25600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25602 /* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],a0 */
25604 M32C_INSN_MOVA32_SRC_A0_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-16-An-relative-Unprefixed-Mova-SI", "mova", 32,
25605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25607 /* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],a0 */
25609 M32C_INSN_MOVA32_SRC_A0_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-24-An-relative-Unprefixed-Mova-SI", "mova", 40,
25610 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25612 /* mova ${Dsp-16-u8}[sb],a0 */
25614 M32C_INSN_MOVA32_SRC_A0_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "mova", 24,
25615 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25617 /* mova ${Dsp-16-u16}[sb],a0 */
25619 M32C_INSN_MOVA32_SRC_A0_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "mova", 32,
25620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25622 /* mova ${Dsp-16-s8}[fb],a0 */
25624 M32C_INSN_MOVA32_SRC_A0_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "mova", 24,
25625 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25627 /* mova ${Dsp-16-s16}[fb],a0 */
25629 M32C_INSN_MOVA32_SRC_A0_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "mova", 32,
25630 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25632 /* mova ${Dsp-16-u16},a0 */
25634 M32C_INSN_MOVA32_SRC_A0_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-16-absolute-Unprefixed-Mova-SI", "mova", 32,
25635 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25637 /* mova ${Dsp-16-u24},a0 */
25639 M32C_INSN_MOVA32_SRC_A0_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-a0-dst32-16-24-absolute-Unprefixed-Mova-SI", "mova", 40,
25640 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25642 /* mova [$Dst32AnUnprefixed],r3r1 */
25644 M32C_INSN_MOVA32_SRC_R3R1_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-An-indirect-Unprefixed-Mova-SI", "mova", 16,
25645 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25647 /* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],r3r1 */
25649 M32C_INSN_MOVA32_SRC_R3R1_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-8-An-relative-Unprefixed-Mova-SI", "mova", 24,
25650 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25652 /* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],r3r1 */
25654 M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-16-An-relative-Unprefixed-Mova-SI", "mova", 32,
25655 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25657 /* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],r3r1 */
25659 M32C_INSN_MOVA32_SRC_R3R1_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-24-An-relative-Unprefixed-Mova-SI", "mova", 40,
25660 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25662 /* mova ${Dsp-16-u8}[sb],r3r1 */
25664 M32C_INSN_MOVA32_SRC_R3R1_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "mova", 24,
25665 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25667 /* mova ${Dsp-16-u16}[sb],r3r1 */
25669 M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "mova", 32,
25670 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25672 /* mova ${Dsp-16-s8}[fb],r3r1 */
25674 M32C_INSN_MOVA32_SRC_R3R1_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "mova", 24,
25675 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25677 /* mova ${Dsp-16-s16}[fb],r3r1 */
25679 M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "mova", 32,
25680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25682 /* mova ${Dsp-16-u16},r3r1 */
25684 M32C_INSN_MOVA32_SRC_R3R1_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-16-absolute-Unprefixed-Mova-SI", "mova", 32,
25685 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25687 /* mova ${Dsp-16-u24},r3r1 */
25689 M32C_INSN_MOVA32_SRC_R3R1_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-r3r1-dst32-16-24-absolute-Unprefixed-Mova-SI", "mova", 40,
25690 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25692 /* mova [$Dst32AnUnprefixed],r2r0 */
25694 M32C_INSN_MOVA32_SRC_R2R0_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-An-indirect-Unprefixed-Mova-SI", "mova", 16,
25695 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25697 /* mova ${Dsp-16-u8}[$Dst32AnUnprefixed],r2r0 */
25699 M32C_INSN_MOVA32_SRC_R2R0_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-8-An-relative-Unprefixed-Mova-SI", "mova", 24,
25700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25702 /* mova ${Dsp-16-u16}[$Dst32AnUnprefixed],r2r0 */
25704 M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-16-An-relative-Unprefixed-Mova-SI", "mova", 32,
25705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25707 /* mova ${Dsp-16-u24}[$Dst32AnUnprefixed],r2r0 */
25709 M32C_INSN_MOVA32_SRC_R2R0_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-24-An-relative-Unprefixed-Mova-SI", "mova", 40,
25710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25712 /* mova ${Dsp-16-u8}[sb],r2r0 */
25714 M32C_INSN_MOVA32_SRC_R2R0_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-8-SB-relative-Unprefixed-Mova-SI", "mova", 24,
25715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25717 /* mova ${Dsp-16-u16}[sb],r2r0 */
25719 M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-16-SB-relative-Unprefixed-Mova-SI", "mova", 32,
25720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25722 /* mova ${Dsp-16-s8}[fb],r2r0 */
25724 M32C_INSN_MOVA32_SRC_R2R0_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-8-FB-relative-Unprefixed-Mova-SI", "mova", 24,
25725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25727 /* mova ${Dsp-16-s16}[fb],r2r0 */
25729 M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-16-FB-relative-Unprefixed-Mova-SI", "mova", 32,
25730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25732 /* mova ${Dsp-16-u16},r2r0 */
25734 M32C_INSN_MOVA32_SRC_R2R0_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-16-absolute-Unprefixed-Mova-SI", "mova", 32,
25735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25737 /* mova ${Dsp-16-u24},r2r0 */
25739 M32C_INSN_MOVA32_SRC_R2R0_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, "mova32.src-r2r0-dst32-16-24-absolute-Unprefixed-Mova-SI", "mova", 40,
25740 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25742 /* mova [$Dst16An],a1 */
25744 M32C_INSN_MOVA16_SRC_A1_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-a1-dst16-An-indirect-Mova-HI", "mova", 16,
25745 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25747 /* mova ${Dsp-16-u8}[$Dst16An],a1 */
25749 M32C_INSN_MOVA16_SRC_A1_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-8-An-relative-Mova-HI", "mova", 24,
25750 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25752 /* mova ${Dsp-16-u16}[$Dst16An],a1 */
25754 M32C_INSN_MOVA16_SRC_A1_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-16-An-relative-Mova-HI", "mova", 32,
25755 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25757 /* mova ${Dsp-16-u8}[sb],a1 */
25759 M32C_INSN_MOVA16_SRC_A1_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-8-SB-relative-Mova-HI", "mova", 24,
25760 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25762 /* mova ${Dsp-16-u16}[sb],a1 */
25764 M32C_INSN_MOVA16_SRC_A1_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-16-SB-relative-Mova-HI", "mova", 32,
25765 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25767 /* mova ${Dsp-16-s8}[fb],a1 */
25769 M32C_INSN_MOVA16_SRC_A1_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-a1-dst16-16-8-FB-relative-Mova-HI", "mova", 24,
25770 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25772 /* mova ${Dsp-16-u16},a1 */
25774 M32C_INSN_MOVA16_SRC_A1_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-a1-dst16-16-16-absolute-Mova-HI", "mova", 32,
25775 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25777 /* mova [$Dst16An],a0 */
25779 M32C_INSN_MOVA16_SRC_A0_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-a0-dst16-An-indirect-Mova-HI", "mova", 16,
25780 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25782 /* mova ${Dsp-16-u8}[$Dst16An],a0 */
25784 M32C_INSN_MOVA16_SRC_A0_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-8-An-relative-Mova-HI", "mova", 24,
25785 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25787 /* mova ${Dsp-16-u16}[$Dst16An],a0 */
25789 M32C_INSN_MOVA16_SRC_A0_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-16-An-relative-Mova-HI", "mova", 32,
25790 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25792 /* mova ${Dsp-16-u8}[sb],a0 */
25794 M32C_INSN_MOVA16_SRC_A0_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-8-SB-relative-Mova-HI", "mova", 24,
25795 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25797 /* mova ${Dsp-16-u16}[sb],a0 */
25799 M32C_INSN_MOVA16_SRC_A0_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-16-SB-relative-Mova-HI", "mova", 32,
25800 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25802 /* mova ${Dsp-16-s8}[fb],a0 */
25804 M32C_INSN_MOVA16_SRC_A0_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-a0-dst16-16-8-FB-relative-Mova-HI", "mova", 24,
25805 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25807 /* mova ${Dsp-16-u16},a0 */
25809 M32C_INSN_MOVA16_SRC_A0_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-a0-dst16-16-16-absolute-Mova-HI", "mova", 32,
25810 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25812 /* mova [$Dst16An],r3 */
25814 M32C_INSN_MOVA16_SRC_R3_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-r3-dst16-An-indirect-Mova-HI", "mova", 16,
25815 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25817 /* mova ${Dsp-16-u8}[$Dst16An],r3 */
25819 M32C_INSN_MOVA16_SRC_R3_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-8-An-relative-Mova-HI", "mova", 24,
25820 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25822 /* mova ${Dsp-16-u16}[$Dst16An],r3 */
25824 M32C_INSN_MOVA16_SRC_R3_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-16-An-relative-Mova-HI", "mova", 32,
25825 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25827 /* mova ${Dsp-16-u8}[sb],r3 */
25829 M32C_INSN_MOVA16_SRC_R3_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-8-SB-relative-Mova-HI", "mova", 24,
25830 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25832 /* mova ${Dsp-16-u16}[sb],r3 */
25834 M32C_INSN_MOVA16_SRC_R3_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-16-SB-relative-Mova-HI", "mova", 32,
25835 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25837 /* mova ${Dsp-16-s8}[fb],r3 */
25839 M32C_INSN_MOVA16_SRC_R3_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-r3-dst16-16-8-FB-relative-Mova-HI", "mova", 24,
25840 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25842 /* mova ${Dsp-16-u16},r3 */
25844 M32C_INSN_MOVA16_SRC_R3_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-r3-dst16-16-16-absolute-Mova-HI", "mova", 32,
25845 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25847 /* mova [$Dst16An],r2 */
25849 M32C_INSN_MOVA16_SRC_R2_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-r2-dst16-An-indirect-Mova-HI", "mova", 16,
25850 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25852 /* mova ${Dsp-16-u8}[$Dst16An],r2 */
25854 M32C_INSN_MOVA16_SRC_R2_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-8-An-relative-Mova-HI", "mova", 24,
25855 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25857 /* mova ${Dsp-16-u16}[$Dst16An],r2 */
25859 M32C_INSN_MOVA16_SRC_R2_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-16-An-relative-Mova-HI", "mova", 32,
25860 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25862 /* mova ${Dsp-16-u8}[sb],r2 */
25864 M32C_INSN_MOVA16_SRC_R2_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-8-SB-relative-Mova-HI", "mova", 24,
25865 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25867 /* mova ${Dsp-16-u16}[sb],r2 */
25869 M32C_INSN_MOVA16_SRC_R2_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-16-SB-relative-Mova-HI", "mova", 32,
25870 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25872 /* mova ${Dsp-16-s8}[fb],r2 */
25874 M32C_INSN_MOVA16_SRC_R2_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-r2-dst16-16-8-FB-relative-Mova-HI", "mova", 24,
25875 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25877 /* mova ${Dsp-16-u16},r2 */
25879 M32C_INSN_MOVA16_SRC_R2_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-r2-dst16-16-16-absolute-Mova-HI", "mova", 32,
25880 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25882 /* mova [$Dst16An],r1 */
25884 M32C_INSN_MOVA16_SRC_R1_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-r1-dst16-An-indirect-Mova-HI", "mova", 16,
25885 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25887 /* mova ${Dsp-16-u8}[$Dst16An],r1 */
25889 M32C_INSN_MOVA16_SRC_R1_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-8-An-relative-Mova-HI", "mova", 24,
25890 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25892 /* mova ${Dsp-16-u16}[$Dst16An],r1 */
25894 M32C_INSN_MOVA16_SRC_R1_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-16-An-relative-Mova-HI", "mova", 32,
25895 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25897 /* mova ${Dsp-16-u8}[sb],r1 */
25899 M32C_INSN_MOVA16_SRC_R1_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-8-SB-relative-Mova-HI", "mova", 24,
25900 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25902 /* mova ${Dsp-16-u16}[sb],r1 */
25904 M32C_INSN_MOVA16_SRC_R1_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-16-SB-relative-Mova-HI", "mova", 32,
25905 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25907 /* mova ${Dsp-16-s8}[fb],r1 */
25909 M32C_INSN_MOVA16_SRC_R1_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-r1-dst16-16-8-FB-relative-Mova-HI", "mova", 24,
25910 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25912 /* mova ${Dsp-16-u16},r1 */
25914 M32C_INSN_MOVA16_SRC_R1_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-r1-dst16-16-16-absolute-Mova-HI", "mova", 32,
25915 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25917 /* mova [$Dst16An],r0 */
25919 M32C_INSN_MOVA16_SRC_R0_DST16_AN_INDIRECT_MOVA_HI, "mova16.src-r0-dst16-An-indirect-Mova-HI", "mova", 16,
25920 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25922 /* mova ${Dsp-16-u8}[$Dst16An],r0 */
25924 M32C_INSN_MOVA16_SRC_R0_DST16_16_8_AN_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-8-An-relative-Mova-HI", "mova", 24,
25925 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25927 /* mova ${Dsp-16-u16}[$Dst16An],r0 */
25929 M32C_INSN_MOVA16_SRC_R0_DST16_16_16_AN_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-16-An-relative-Mova-HI", "mova", 32,
25930 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25932 /* mova ${Dsp-16-u8}[sb],r0 */
25934 M32C_INSN_MOVA16_SRC_R0_DST16_16_8_SB_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-8-SB-relative-Mova-HI", "mova", 24,
25935 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25937 /* mova ${Dsp-16-u16}[sb],r0 */
25939 M32C_INSN_MOVA16_SRC_R0_DST16_16_16_SB_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-16-SB-relative-Mova-HI", "mova", 32,
25940 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25942 /* mova ${Dsp-16-s8}[fb],r0 */
25944 M32C_INSN_MOVA16_SRC_R0_DST16_16_8_FB_RELATIVE_MOVA_HI, "mova16.src-r0-dst16-16-8-FB-relative-Mova-HI", "mova", 24,
25945 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25947 /* mova ${Dsp-16-u16},r0 */
25949 M32C_INSN_MOVA16_SRC_R0_DST16_16_16_ABSOLUTE_MOVA_HI, "mova16.src-r0-dst16-16-16-absolute-Mova-HI", "mova", 32,
25950 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
25952 /* mov.w ${Dsp-16-u8}[$Dst32AnUnprefixed],${Dsp-24-u8}[sp] */
25954 M32C_INSN_MOV32_W_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 32,
25955 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25957 /* mov.w ${Dsp-16-u8}[sb],${Dsp-24-u8}[sp] */
25959 M32C_INSN_MOV32_W_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 32,
25960 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25962 /* mov.w ${Dsp-16-s8}[fb],${Dsp-24-u8}[sp] */
25964 M32C_INSN_MOV32_W_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 32,
25965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25967 /* mov.w ${Dsp-16-u16}[$Dst32AnUnprefixed],${Dsp-32-u8}[sp] */
25969 M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 40,
25970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25972 /* mov.w ${Dsp-16-u16}[sb],${Dsp-32-u8}[sp] */
25974 M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 40,
25975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25977 /* mov.w ${Dsp-16-s16}[fb],${Dsp-32-u8}[sp] */
25979 M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 40,
25980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25982 /* mov.w ${Dsp-16-u16},${Dsp-32-u8}[sp] */
25984 M32C_INSN_MOV32_W_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 40,
25985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25987 /* mov.w ${Dsp-16-u24}[$Dst32AnUnprefixed],${Dsp-40-u8}[sp] */
25989 M32C_INSN_MOV32_W_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 48,
25990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25992 /* mov.w ${Dsp-16-u24},${Dsp-40-u8}[sp] */
25994 M32C_INSN_MOV32_W_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-dst-dspsp-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 48,
25995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
25997 /* mov.w $Dst32RnUnprefixedHI,${Dsp-16-u8}[sp] */
25999 M32C_INSN_MOV32_W_DST_DSPSP_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-dst-dspsp-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24,
26000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26002 /* mov.w $Dst32AnUnprefixedHI,${Dsp-16-u8}[sp] */
26004 M32C_INSN_MOV32_W_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-dst-dspsp-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mov.w", 24,
26005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26007 /* mov.w [$Dst32AnUnprefixed],${Dsp-16-u8}[sp] */
26009 M32C_INSN_MOV32_W_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-dst-dspsp-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mov.w", 24,
26010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26012 /* mov.b ${Dsp-16-u8}[$Dst32AnUnprefixed],${Dsp-24-u8}[sp] */
26014 M32C_INSN_MOV32_B_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 32,
26015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26017 /* mov.b ${Dsp-16-u8}[sb],${Dsp-24-u8}[sp] */
26019 M32C_INSN_MOV32_B_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 32,
26020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26022 /* mov.b ${Dsp-16-s8}[fb],${Dsp-24-u8}[sp] */
26024 M32C_INSN_MOV32_B_DST_DSPSP_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 32,
26025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26027 /* mov.b ${Dsp-16-u16}[$Dst32AnUnprefixed],${Dsp-32-u8}[sp] */
26029 M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 40,
26030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26032 /* mov.b ${Dsp-16-u16}[sb],${Dsp-32-u8}[sp] */
26034 M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 40,
26035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26037 /* mov.b ${Dsp-16-s16}[fb],${Dsp-32-u8}[sp] */
26039 M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 40,
26040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26042 /* mov.b ${Dsp-16-u16},${Dsp-32-u8}[sp] */
26044 M32C_INSN_MOV32_B_DST_DSPSP_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 40,
26045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26047 /* mov.b ${Dsp-16-u24}[$Dst32AnUnprefixed],${Dsp-40-u8}[sp] */
26049 M32C_INSN_MOV32_B_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 48,
26050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26052 /* mov.b ${Dsp-16-u24},${Dsp-40-u8}[sp] */
26054 M32C_INSN_MOV32_B_DST_DSPSP_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-dst-dspsp-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 48,
26055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26057 /* mov.b $Dst32RnUnprefixedQI,${Dsp-16-u8}[sp] */
26059 M32C_INSN_MOV32_B_DST_DSPSP_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-dst-dspsp-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24,
26060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26062 /* mov.b $Dst32AnUnprefixedQI,${Dsp-16-u8}[sp] */
26064 M32C_INSN_MOV32_B_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-dst-dspsp-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mov.b", 24,
26065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26067 /* mov.b [$Dst32AnUnprefixed],${Dsp-16-u8}[sp] */
26069 M32C_INSN_MOV32_B_DST_DSPSP_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-dst-dspsp-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mov.b", 24,
26070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26072 /* mov.w ${Dsp-16-u8}[$Dst16An],${Dsp-24-u8}[sp] */
26074 M32C_INSN_MOV16_W_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_HI, "mov16.w-dst-dspsp-16-8-dst16-16-8-An-relative-HI", "mov.w", 32,
26075 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26077 /* mov.w ${Dsp-16-u8}[sb],${Dsp-24-u8}[sp] */
26079 M32C_INSN_MOV16_W_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_HI, "mov16.w-dst-dspsp-16-8-dst16-16-8-SB-relative-HI", "mov.w", 32,
26080 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26082 /* mov.w ${Dsp-16-s8}[fb],${Dsp-24-u8}[sp] */
26084 M32C_INSN_MOV16_W_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_HI, "mov16.w-dst-dspsp-16-8-dst16-16-8-FB-relative-HI", "mov.w", 32,
26085 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26087 /* mov.w ${Dsp-16-u16}[$Dst16An],${Dsp-32-u8}[sp] */
26089 M32C_INSN_MOV16_W_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_HI, "mov16.w-dst-dspsp-16-16-dst16-16-16-An-relative-HI", "mov.w", 40,
26090 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26092 /* mov.w ${Dsp-16-u16}[sb],${Dsp-32-u8}[sp] */
26094 M32C_INSN_MOV16_W_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_HI, "mov16.w-dst-dspsp-16-16-dst16-16-16-SB-relative-HI", "mov.w", 40,
26095 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26097 /* mov.w ${Dsp-16-u16},${Dsp-32-u8}[sp] */
26099 M32C_INSN_MOV16_W_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_HI, "mov16.w-dst-dspsp-16-16-dst16-16-16-absolute-HI", "mov.w", 40,
26100 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26102 /* mov.w $Dst16RnHI,${Dsp-16-u8}[sp] */
26104 M32C_INSN_MOV16_W_DST_DSPSP_BASIC_DST16_RN_DIRECT_HI, "mov16.w-dst-dspsp-basic-dst16-Rn-direct-HI", "mov.w", 24,
26105 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26107 /* mov.w $Dst16AnHI,${Dsp-16-u8}[sp] */
26109 M32C_INSN_MOV16_W_DST_DSPSP_BASIC_DST16_AN_DIRECT_HI, "mov16.w-dst-dspsp-basic-dst16-An-direct-HI", "mov.w", 24,
26110 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26112 /* mov.w [$Dst16An],${Dsp-16-u8}[sp] */
26114 M32C_INSN_MOV16_W_DST_DSPSP_BASIC_DST16_AN_INDIRECT_HI, "mov16.w-dst-dspsp-basic-dst16-An-indirect-HI", "mov.w", 24,
26115 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26117 /* mov.b ${Dsp-16-u8}[$Dst16An],${Dsp-24-u8}[sp] */
26119 M32C_INSN_MOV16_B_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_QI, "mov16.b-dst-dspsp-16-8-dst16-16-8-An-relative-QI", "mov.b", 32,
26120 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26122 /* mov.b ${Dsp-16-u8}[sb],${Dsp-24-u8}[sp] */
26124 M32C_INSN_MOV16_B_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_QI, "mov16.b-dst-dspsp-16-8-dst16-16-8-SB-relative-QI", "mov.b", 32,
26125 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26127 /* mov.b ${Dsp-16-s8}[fb],${Dsp-24-u8}[sp] */
26129 M32C_INSN_MOV16_B_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_QI, "mov16.b-dst-dspsp-16-8-dst16-16-8-FB-relative-QI", "mov.b", 32,
26130 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26132 /* mov.b ${Dsp-16-u16}[$Dst16An],${Dsp-32-u8}[sp] */
26134 M32C_INSN_MOV16_B_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_QI, "mov16.b-dst-dspsp-16-16-dst16-16-16-An-relative-QI", "mov.b", 40,
26135 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26137 /* mov.b ${Dsp-16-u16}[sb],${Dsp-32-u8}[sp] */
26139 M32C_INSN_MOV16_B_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_QI, "mov16.b-dst-dspsp-16-16-dst16-16-16-SB-relative-QI", "mov.b", 40,
26140 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26142 /* mov.b ${Dsp-16-u16},${Dsp-32-u8}[sp] */
26144 M32C_INSN_MOV16_B_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_QI, "mov16.b-dst-dspsp-16-16-dst16-16-16-absolute-QI", "mov.b", 40,
26145 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26147 /* mov.b $Dst16RnQI,${Dsp-16-u8}[sp] */
26149 M32C_INSN_MOV16_B_DST_DSPSP_BASIC_DST16_RN_DIRECT_QI, "mov16.b-dst-dspsp-basic-dst16-Rn-direct-QI", "mov.b", 24,
26150 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26152 /* mov.b $Dst16AnQI,${Dsp-16-u8}[sp] */
26154 M32C_INSN_MOV16_B_DST_DSPSP_BASIC_DST16_AN_DIRECT_QI, "mov16.b-dst-dspsp-basic-dst16-An-direct-QI", "mov.b", 24,
26155 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26157 /* mov.b [$Dst16An],${Dsp-16-u8}[sp] */
26159 M32C_INSN_MOV16_B_DST_DSPSP_BASIC_DST16_AN_INDIRECT_QI, "mov16.b-dst-dspsp-basic-dst16-An-indirect-QI", "mov.b", 24,
26160 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26162 /* mov.w ${Dsp-24-u8}[sp],${Dsp-16-u8}[$Dst32AnUnprefixed] */
26164 M32C_INSN_MOV32_W_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 32,
26165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26167 /* mov.w ${Dsp-24-u8}[sp],${Dsp-16-u8}[sb] */
26169 M32C_INSN_MOV32_W_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 32,
26170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26172 /* mov.w ${Dsp-24-u8}[sp],${Dsp-16-s8}[fb] */
26174 M32C_INSN_MOV32_W_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 32,
26175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26177 /* mov.w ${Dsp-32-u8}[sp],${Dsp-16-u16}[$Dst32AnUnprefixed] */
26179 M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 40,
26180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26182 /* mov.w ${Dsp-32-u8}[sp],${Dsp-16-u16}[sb] */
26184 M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 40,
26185 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26187 /* mov.w ${Dsp-32-u8}[sp],${Dsp-16-s16}[fb] */
26189 M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 40,
26190 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26192 /* mov.w ${Dsp-32-u8}[sp],${Dsp-16-u16} */
26194 M32C_INSN_MOV32_W_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 40,
26195 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26197 /* mov.w ${Dsp-40-u8}[sp],${Dsp-16-u24}[$Dst32AnUnprefixed] */
26199 M32C_INSN_MOV32_W_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 48,
26200 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26202 /* mov.w ${Dsp-40-u8}[sp],${Dsp-16-u24} */
26204 M32C_INSN_MOV32_W_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-dspsp-dst-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 48,
26205 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26207 /* mov.w ${Dsp-16-u8}[sp],$Dst32RnUnprefixedHI */
26209 M32C_INSN_MOV32_W_DSPSP_DST_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-dspsp-dst-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24,
26210 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26212 /* mov.w ${Dsp-16-u8}[sp],$Dst32AnUnprefixedHI */
26214 M32C_INSN_MOV32_W_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-dspsp-dst-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mov.w", 24,
26215 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26217 /* mov.w ${Dsp-16-u8}[sp],[$Dst32AnUnprefixed] */
26219 M32C_INSN_MOV32_W_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-dspsp-dst-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mov.w", 24,
26220 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26222 /* mov.b ${Dsp-24-u8}[sp],${Dsp-16-u8}[$Dst32AnUnprefixed] */
26224 M32C_INSN_MOV32_B_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 32,
26225 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26227 /* mov.b ${Dsp-24-u8}[sp],${Dsp-16-u8}[sb] */
26229 M32C_INSN_MOV32_B_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 32,
26230 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26232 /* mov.b ${Dsp-24-u8}[sp],${Dsp-16-s8}[fb] */
26234 M32C_INSN_MOV32_B_DSPSP_DST_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 32,
26235 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26237 /* mov.b ${Dsp-32-u8}[sp],${Dsp-16-u16}[$Dst32AnUnprefixed] */
26239 M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 40,
26240 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26242 /* mov.b ${Dsp-32-u8}[sp],${Dsp-16-u16}[sb] */
26244 M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 40,
26245 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26247 /* mov.b ${Dsp-32-u8}[sp],${Dsp-16-s16}[fb] */
26249 M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 40,
26250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26252 /* mov.b ${Dsp-32-u8}[sp],${Dsp-16-u16} */
26254 M32C_INSN_MOV32_B_DSPSP_DST_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 40,
26255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26257 /* mov.b ${Dsp-40-u8}[sp],${Dsp-16-u24}[$Dst32AnUnprefixed] */
26259 M32C_INSN_MOV32_B_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 48,
26260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26262 /* mov.b ${Dsp-40-u8}[sp],${Dsp-16-u24} */
26264 M32C_INSN_MOV32_B_DSPSP_DST_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-dspsp-dst-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 48,
26265 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26267 /* mov.b ${Dsp-16-u8}[sp],$Dst32RnUnprefixedQI */
26269 M32C_INSN_MOV32_B_DSPSP_DST_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-dspsp-dst-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24,
26270 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26272 /* mov.b ${Dsp-16-u8}[sp],$Dst32AnUnprefixedQI */
26274 M32C_INSN_MOV32_B_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-dspsp-dst-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mov.b", 24,
26275 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26277 /* mov.b ${Dsp-16-u8}[sp],[$Dst32AnUnprefixed] */
26279 M32C_INSN_MOV32_B_DSPSP_DST_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-dspsp-dst-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mov.b", 24,
26280 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26282 /* mov.w ${Dsp-24-u8}[sp],${Dsp-16-u8}[$Dst16An] */
26284 M32C_INSN_MOV16_W_DSPSP_DST_16_8_DST16_16_8_AN_RELATIVE_HI, "mov16.w-dspsp-dst-16-8-dst16-16-8-An-relative-HI", "mov.w", 32,
26285 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26287 /* mov.w ${Dsp-24-u8}[sp],${Dsp-16-u8}[sb] */
26289 M32C_INSN_MOV16_W_DSPSP_DST_16_8_DST16_16_8_SB_RELATIVE_HI, "mov16.w-dspsp-dst-16-8-dst16-16-8-SB-relative-HI", "mov.w", 32,
26290 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26292 /* mov.w ${Dsp-24-u8}[sp],${Dsp-16-s8}[fb] */
26294 M32C_INSN_MOV16_W_DSPSP_DST_16_8_DST16_16_8_FB_RELATIVE_HI, "mov16.w-dspsp-dst-16-8-dst16-16-8-FB-relative-HI", "mov.w", 32,
26295 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26297 /* mov.w ${Dsp-32-u8}[sp],${Dsp-16-u16}[$Dst16An] */
26299 M32C_INSN_MOV16_W_DSPSP_DST_16_16_DST16_16_16_AN_RELATIVE_HI, "mov16.w-dspsp-dst-16-16-dst16-16-16-An-relative-HI", "mov.w", 40,
26300 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26302 /* mov.w ${Dsp-32-u8}[sp],${Dsp-16-u16}[sb] */
26304 M32C_INSN_MOV16_W_DSPSP_DST_16_16_DST16_16_16_SB_RELATIVE_HI, "mov16.w-dspsp-dst-16-16-dst16-16-16-SB-relative-HI", "mov.w", 40,
26305 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26307 /* mov.w ${Dsp-32-u8}[sp],${Dsp-16-u16} */
26309 M32C_INSN_MOV16_W_DSPSP_DST_16_16_DST16_16_16_ABSOLUTE_HI, "mov16.w-dspsp-dst-16-16-dst16-16-16-absolute-HI", "mov.w", 40,
26310 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26312 /* mov.w ${Dsp-16-u8}[sp],$Dst16RnHI */
26314 M32C_INSN_MOV16_W_DSPSP_DST_BASIC_DST16_RN_DIRECT_HI, "mov16.w-dspsp-dst-basic-dst16-Rn-direct-HI", "mov.w", 24,
26315 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26317 /* mov.w ${Dsp-16-u8}[sp],$Dst16AnHI */
26319 M32C_INSN_MOV16_W_DSPSP_DST_BASIC_DST16_AN_DIRECT_HI, "mov16.w-dspsp-dst-basic-dst16-An-direct-HI", "mov.w", 24,
26320 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26322 /* mov.w ${Dsp-16-u8}[sp],[$Dst16An] */
26324 M32C_INSN_MOV16_W_DSPSP_DST_BASIC_DST16_AN_INDIRECT_HI, "mov16.w-dspsp-dst-basic-dst16-An-indirect-HI", "mov.w", 24,
26325 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26327 /* mov.b ${Dsp-24-u8}[sp],${Dsp-16-u8}[$Dst16An] */
26329 M32C_INSN_MOV16_B_DSPSP_DST_16_8_DST16_16_8_AN_RELATIVE_QI, "mov16.b-dspsp-dst-16-8-dst16-16-8-An-relative-QI", "mov.b", 32,
26330 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26332 /* mov.b ${Dsp-24-u8}[sp],${Dsp-16-u8}[sb] */
26334 M32C_INSN_MOV16_B_DSPSP_DST_16_8_DST16_16_8_SB_RELATIVE_QI, "mov16.b-dspsp-dst-16-8-dst16-16-8-SB-relative-QI", "mov.b", 32,
26335 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26337 /* mov.b ${Dsp-24-u8}[sp],${Dsp-16-s8}[fb] */
26339 M32C_INSN_MOV16_B_DSPSP_DST_16_8_DST16_16_8_FB_RELATIVE_QI, "mov16.b-dspsp-dst-16-8-dst16-16-8-FB-relative-QI", "mov.b", 32,
26340 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26342 /* mov.b ${Dsp-32-u8}[sp],${Dsp-16-u16}[$Dst16An] */
26344 M32C_INSN_MOV16_B_DSPSP_DST_16_16_DST16_16_16_AN_RELATIVE_QI, "mov16.b-dspsp-dst-16-16-dst16-16-16-An-relative-QI", "mov.b", 40,
26345 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26347 /* mov.b ${Dsp-32-u8}[sp],${Dsp-16-u16}[sb] */
26349 M32C_INSN_MOV16_B_DSPSP_DST_16_16_DST16_16_16_SB_RELATIVE_QI, "mov16.b-dspsp-dst-16-16-dst16-16-16-SB-relative-QI", "mov.b", 40,
26350 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26352 /* mov.b ${Dsp-32-u8}[sp],${Dsp-16-u16} */
26354 M32C_INSN_MOV16_B_DSPSP_DST_16_16_DST16_16_16_ABSOLUTE_QI, "mov16.b-dspsp-dst-16-16-dst16-16-16-absolute-QI", "mov.b", 40,
26355 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26357 /* mov.b ${Dsp-16-u8}[sp],$Dst16RnQI */
26359 M32C_INSN_MOV16_B_DSPSP_DST_BASIC_DST16_RN_DIRECT_QI, "mov16.b-dspsp-dst-basic-dst16-Rn-direct-QI", "mov.b", 24,
26360 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26362 /* mov.b ${Dsp-16-u8}[sp],$Dst16AnQI */
26364 M32C_INSN_MOV16_B_DSPSP_DST_BASIC_DST16_AN_DIRECT_QI, "mov16.b-dspsp-dst-basic-dst16-An-direct-QI", "mov.b", 24,
26365 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26367 /* mov.b ${Dsp-16-u8}[sp],[$Dst16An] */
26369 M32C_INSN_MOV16_B_DSPSP_DST_BASIC_DST16_AN_INDIRECT_QI, "mov16.b-dspsp-dst-basic-dst16-An-indirect-QI", "mov.b", 24,
26370 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26372 /* mov.l${S} ${Dsp-8-u8}[sb],a1 */
26374 M32C_INSN_MOV32_SZ_DST32_2_S_8_A1_DST32_2_S_8_SB_RELATIVE_SI, "mov32.sz-dst32-2-S-8-a1-dst32-2-S-8-SB-relative-SI", "mov.l", 16,
26375 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26377 /* mov.l${S} ${Dsp-8-s8}[fb],a1 */
26379 M32C_INSN_MOV32_SZ_DST32_2_S_8_A1_DST32_2_S_8_FB_RELATIVE_SI, "mov32.sz-dst32-2-S-8-a1-dst32-2-S-8-FB-relative-SI", "mov.l", 16,
26380 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26382 /* mov.l${S} ${Dsp-8-u8}[sb],a0 */
26384 M32C_INSN_MOV32_SZ_DST32_2_S_8_A0_DST32_2_S_8_SB_RELATIVE_SI, "mov32.sz-dst32-2-S-8-a0-dst32-2-S-8-SB-relative-SI", "mov.l", 16,
26385 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26387 /* mov.l${S} ${Dsp-8-s8}[fb],a0 */
26389 M32C_INSN_MOV32_SZ_DST32_2_S_8_A0_DST32_2_S_8_FB_RELATIVE_SI, "mov32.sz-dst32-2-S-8-a0-dst32-2-S-8-FB-relative-SI", "mov.l", 16,
26390 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26392 /* mov.l${S} ${Dsp-8-u16},a1 */
26394 M32C_INSN_MOV32_SZ_DST32_2_S_16_A1_DST32_2_S_16_ABSOLUTE_SI, "mov32.sz-dst32-2-S-16-a1-dst32-2-S-16-absolute-SI", "mov.l", 24,
26395 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26397 /* mov.l${S} ${Dsp-8-u16},a0 */
26399 M32C_INSN_MOV32_SZ_DST32_2_S_16_A0_DST32_2_S_16_ABSOLUTE_SI, "mov32.sz-dst32-2-S-16-a0-dst32-2-S-16-absolute-SI", "mov.l", 24,
26400 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26402 /* mov.w${S} r0,${Dsp-8-u8}[sb] */
26404 M32C_INSN_MOV32_W_R0_DST32_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-r0-dst32-2-S-8-dst32-2-S-8-SB-relative-HI", "mov.w", 16,
26405 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26407 /* mov.w${S} r0,${Dsp-8-s8}[fb] */
26409 M32C_INSN_MOV32_W_R0_DST32_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-r0-dst32-2-S-8-dst32-2-S-8-FB-relative-HI", "mov.w", 16,
26410 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26412 /* mov.b${S} r0l,${Dsp-8-u8}[sb] */
26414 M32C_INSN_MOV32_B_R0L_DST32_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-r0l-dst32-2-S-8-dst32-2-S-8-SB-relative-QI", "mov.b", 16,
26415 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26417 /* mov.b${S} r0l,${Dsp-8-s8}[fb] */
26419 M32C_INSN_MOV32_B_R0L_DST32_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-r0l-dst32-2-S-8-dst32-2-S-8-FB-relative-QI", "mov.b", 16,
26420 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26422 /* mov.w${S} r0,${Dsp-8-u16} */
26424 M32C_INSN_MOV32_W_R0_DST32_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-r0-dst32-2-S-16-dst32-2-S-16-absolute-HI", "mov.w", 24,
26425 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26427 /* mov.b${S} r0l,${Dsp-8-u16} */
26429 M32C_INSN_MOV32_B_R0L_DST32_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-r0l-dst32-2-S-16-dst32-2-S-16-absolute-QI", "mov.b", 24,
26430 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26432 /* mov.w${S} ${Dsp-8-u8}[sb],r1 */
26434 M32C_INSN_MOV32_W_DST32_2_S_8_R1_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-dst32-2-S-8-r1-dst32-2-S-8-SB-relative-HI", "mov.w", 16,
26435 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26437 /* mov.w${S} ${Dsp-8-s8}[fb],r1 */
26439 M32C_INSN_MOV32_W_DST32_2_S_8_R1_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-dst32-2-S-8-r1-dst32-2-S-8-FB-relative-HI", "mov.w", 16,
26440 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26442 /* mov.b${S} ${Dsp-8-u8}[sb],r1l */
26444 M32C_INSN_MOV32_B_DST32_2_S_8_R1L_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-dst32-2-S-8-r1l-dst32-2-S-8-SB-relative-QI", "mov.b", 16,
26445 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26447 /* mov.b${S} ${Dsp-8-s8}[fb],r1l */
26449 M32C_INSN_MOV32_B_DST32_2_S_8_R1L_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-dst32-2-S-8-r1l-dst32-2-S-8-FB-relative-QI", "mov.b", 16,
26450 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26452 /* mov.w${S} ${Dsp-8-u16},r1 */
26454 M32C_INSN_MOV32_W_DST32_2_S_16_R1_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-dst32-2-S-16-r1-dst32-2-S-16-absolute-HI", "mov.w", 24,
26455 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26457 /* mov.b${S} ${Dsp-8-u16},r1l */
26459 M32C_INSN_MOV32_B_DST32_2_S_16_R1L_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-dst32-2-S-16-r1l-dst32-2-S-16-absolute-QI", "mov.b", 24,
26460 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26462 /* mov.w${S} r0,r1l */
26464 M32C_INSN_MOV32_W_DST32_2_S_BASIC_R1L_DST32_2_S_R0_DIRECT_HI, "mov32.w-dst32-2-S-basic-r1l-dst32-2-S-R0-direct-HI", "mov.w", 8,
26465 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26467 /* mov.b${S} r0l,r1l */
26469 M32C_INSN_MOV32_B_DST32_2_S_BASIC_R1L_DST32_2_S_R0L_DIRECT_QI, "mov32.b-dst32-2-S-basic-r1l-dst32-2-S-R0l-direct-QI", "mov.b", 8,
26470 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26472 /* mov.w${S} ${Dsp-8-u8}[sb],r0 */
26474 M32C_INSN_MOV32_W_DST32_2_S_8_R0_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-dst32-2-S-8-r0-dst32-2-S-8-SB-relative-HI", "mov.w", 16,
26475 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26477 /* mov.w${S} ${Dsp-8-s8}[fb],r0 */
26479 M32C_INSN_MOV32_W_DST32_2_S_8_R0_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-dst32-2-S-8-r0-dst32-2-S-8-FB-relative-HI", "mov.w", 16,
26480 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26482 /* mov.b${S} ${Dsp-8-u8}[sb],r0l */
26484 M32C_INSN_MOV32_B_DST32_2_S_8_R0L_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-dst32-2-S-8-r0l-dst32-2-S-8-SB-relative-QI", "mov.b", 16,
26485 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26487 /* mov.b${S} ${Dsp-8-s8}[fb],r0l */
26489 M32C_INSN_MOV32_B_DST32_2_S_8_R0L_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-dst32-2-S-8-r0l-dst32-2-S-8-FB-relative-QI", "mov.b", 16,
26490 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26492 /* mov.w${S} ${Dsp-8-u16},r0 */
26494 M32C_INSN_MOV32_W_DST32_2_S_16_R0_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-dst32-2-S-16-r0-dst32-2-S-16-absolute-HI", "mov.w", 24,
26495 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26497 /* mov.b${S} ${Dsp-8-u16},r0l */
26499 M32C_INSN_MOV32_B_DST32_2_S_16_R0L_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-dst32-2-S-16-r0l-dst32-2-S-16-absolute-QI", "mov.b", 24,
26500 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26502 /* mov.b${S} ${SrcDst16-r0l-r0h-S-normal} */
26504 M32C_INSN_MOV16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, "mov16.b.S-r0l-r0h-srcdst16-r0l-r0h-S-derived", "mov.b", 8,
26505 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26507 /* mov.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
26509 M32C_INSN_MOV16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, "mov16.b.S-src2-src16-2-S-8-SB-relative-QI", "mov.b", 16,
26510 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26512 /* mov.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
26514 M32C_INSN_MOV16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, "mov16.b.S-src2-src16-2-S-8-FB-relative-QI", "mov.b", 16,
26515 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26517 /* mov.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
26519 M32C_INSN_MOV16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, "mov16.b.S-src2-src16-2-S-16-absolute-QI", "mov.b", 24,
26520 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26522 /* mov.b${S} ${Dst16RnQI-S},${Dsp-8-u8}[sb] */
26524 M32C_INSN_MOV16_B_S_RN_AN_SRC16_2_S_8_SB_RELATIVE_QI, "mov16.b.S-Rn-An-src16-2-S-8-SB-relative-QI", "mov.b", 16,
26525 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26527 /* mov.b${S} ${Dst16RnQI-S},${Dsp-8-s8}[fb] */
26529 M32C_INSN_MOV16_B_S_RN_AN_SRC16_2_S_8_FB_RELATIVE_QI, "mov16.b.S-Rn-An-src16-2-S-8-FB-relative-QI", "mov.b", 16,
26530 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26532 /* mov.b${S} ${Dst16RnQI-S},${Dsp-8-u16} */
26534 M32C_INSN_MOV16_B_S_RN_AN_SRC16_2_S_16_ABSOLUTE_QI, "mov16.b.S-Rn-An-src16-2-S-16-absolute-QI", "mov.b", 24,
26535 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
26537 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
26539 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 24,
26540 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26542 /* mov.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
26544 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 24,
26545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26547 /* mov.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
26549 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 24,
26550 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26552 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
26554 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 24,
26555 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26557 /* mov.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
26559 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 24,
26560 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26562 /* mov.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
26564 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 24,
26565 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26567 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
26569 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 24,
26570 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26572 /* mov.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
26574 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 24,
26575 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26577 /* mov.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
26579 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 24,
26580 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26582 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
26584 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "mov.l", 32,
26585 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26587 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
26589 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "mov.l", 32,
26590 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26592 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
26594 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "mov.l", 32,
26595 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26597 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
26599 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "mov.l", 40,
26600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26602 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
26604 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "mov.l", 40,
26605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26607 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
26609 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "mov.l", 40,
26610 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26612 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
26614 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "mov.l", 48,
26615 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26617 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
26619 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "mov.l", 48,
26620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26622 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
26624 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "mov.l", 48,
26625 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26627 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
26629 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "mov.l", 32,
26630 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26632 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
26634 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "mov.l", 32,
26635 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26637 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
26639 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "mov.l", 32,
26640 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26642 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
26644 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "mov.l", 40,
26645 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26647 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
26649 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "mov.l", 40,
26650 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26652 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
26654 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "mov.l", 40,
26655 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26657 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
26659 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "mov.l", 32,
26660 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26662 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
26664 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "mov.l", 32,
26665 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26667 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
26669 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "mov.l", 32,
26670 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26672 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
26674 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "mov.l", 40,
26675 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26677 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
26679 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "mov.l", 40,
26680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26682 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
26684 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "mov.l", 40,
26685 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26687 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
26689 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "mov.l", 40,
26690 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26692 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
26694 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "mov.l", 40,
26695 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26697 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
26699 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "mov.l", 40,
26700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26702 /* mov.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
26704 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "mov.l", 48,
26705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26707 /* mov.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
26709 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "mov.l", 48,
26710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26712 /* mov.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
26714 M32C_INSN_MOV32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "mov.l", 48,
26715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26717 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
26719 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 32,
26720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26722 /* mov.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
26724 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 32,
26725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26727 /* mov.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
26729 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 32,
26730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26732 /* mov.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
26734 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 32,
26735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26737 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
26739 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 32,
26740 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26742 /* mov.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
26744 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 32,
26745 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26747 /* mov.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
26749 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 32,
26750 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26752 /* mov.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
26754 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 32,
26755 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26757 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
26759 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 32,
26760 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26762 /* mov.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
26764 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 32,
26765 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26767 /* mov.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
26769 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 32,
26770 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26772 /* mov.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
26774 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 32,
26775 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26777 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
26779 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "mov.l", 40,
26780 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26782 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
26784 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "mov.l", 40,
26785 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26787 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
26789 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "mov.l", 40,
26790 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26792 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
26794 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "mov.l", 40,
26795 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26797 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
26799 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "mov.l", 48,
26800 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26802 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
26804 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "mov.l", 48,
26805 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26807 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
26809 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "mov.l", 48,
26810 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26812 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
26814 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "mov.l", 48,
26815 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26817 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
26819 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "mov.l", 56,
26820 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26822 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
26824 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "mov.l", 56,
26825 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26827 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
26829 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "mov.l", 56,
26830 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26832 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
26834 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "mov.l", 56,
26835 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26837 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
26839 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "mov.l", 40,
26840 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26842 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
26844 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "mov.l", 40,
26845 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26847 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
26849 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "mov.l", 40,
26850 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26852 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
26854 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "mov.l", 40,
26855 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26857 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
26859 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "mov.l", 48,
26860 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26862 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
26864 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "mov.l", 48,
26865 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26867 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
26869 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "mov.l", 48,
26870 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26872 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
26874 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "mov.l", 48,
26875 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26877 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
26879 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "mov.l", 40,
26880 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26882 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
26884 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "mov.l", 40,
26885 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26887 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
26889 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "mov.l", 40,
26890 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26892 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
26894 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "mov.l", 40,
26895 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26897 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
26899 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "mov.l", 48,
26900 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26902 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
26904 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "mov.l", 48,
26905 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26907 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
26909 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "mov.l", 48,
26910 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26912 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
26914 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "mov.l", 48,
26915 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26917 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
26919 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "mov.l", 48,
26920 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26922 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
26924 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "mov.l", 48,
26925 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26927 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
26929 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "mov.l", 48,
26930 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26932 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u16} */
26934 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "mov.l", 48,
26935 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26937 /* mov.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
26939 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "mov.l", 56,
26940 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26942 /* mov.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
26944 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "mov.l", 56,
26945 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26947 /* mov.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
26949 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "mov.l", 56,
26950 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26952 /* mov.l${G} ${Dsp-16-u16},${Dsp-32-u24} */
26954 M32C_INSN_MOV32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "mov.l", 56,
26955 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26957 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
26959 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 40,
26960 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26962 /* mov.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
26964 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 40,
26965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26967 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
26969 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 40,
26970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26972 /* mov.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
26974 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 40,
26975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26977 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
26979 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 40,
26980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26982 /* mov.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
26984 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 40,
26985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26987 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
26989 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "mov.l", 48,
26990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26992 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
26994 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "mov.l", 48,
26995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
26997 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
26999 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "mov.l", 56,
27000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27002 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
27004 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "mov.l", 56,
27005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27007 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
27009 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "mov.l", 64,
27010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27012 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
27014 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "mov.l", 64,
27015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27017 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
27019 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "mov.l", 48,
27020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27022 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
27024 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "mov.l", 48,
27025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27027 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
27029 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "mov.l", 56,
27030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27032 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
27034 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "mov.l", 56,
27035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27037 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
27039 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "mov.l", 48,
27040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27042 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
27044 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "mov.l", 48,
27045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27047 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
27049 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "mov.l", 56,
27050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27052 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
27054 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "mov.l", 56,
27055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27057 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
27059 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "mov.l", 56,
27060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27062 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u16} */
27064 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "mov.l", 56,
27065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27067 /* mov.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
27069 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "mov.l", 64,
27070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27072 /* mov.l${G} ${Dsp-16-u24},${Dsp-40-u24} */
27074 M32C_INSN_MOV32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "mov.l", 64,
27075 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27077 /* mov.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */
27079 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 16,
27080 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27082 /* mov.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */
27084 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 16,
27085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27087 /* mov.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
27089 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "mov.l", 16,
27090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27092 /* mov.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */
27094 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 16,
27095 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27097 /* mov.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */
27099 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 16,
27100 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27102 /* mov.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
27104 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "mov.l", 16,
27105 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27107 /* mov.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */
27109 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 16,
27110 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27112 /* mov.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */
27114 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 16,
27115 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27117 /* mov.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
27119 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "mov.l", 16,
27120 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27122 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
27124 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "mov.l", 24,
27125 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27127 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
27129 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "mov.l", 24,
27130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27132 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
27134 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "mov.l", 24,
27135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27137 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
27139 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "mov.l", 32,
27140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27142 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
27144 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "mov.l", 32,
27145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27147 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
27149 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "mov.l", 32,
27150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27152 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
27154 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "mov.l", 40,
27155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27157 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
27159 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "mov.l", 40,
27160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27162 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
27164 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "mov.l", 40,
27165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27167 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */
27169 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "mov.l", 24,
27170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27172 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */
27174 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "mov.l", 24,
27175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27177 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
27179 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "mov.l", 24,
27180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27182 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */
27184 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "mov.l", 32,
27185 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27187 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */
27189 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "mov.l", 32,
27190 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27192 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
27194 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "mov.l", 32,
27195 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27197 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */
27199 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "mov.l", 24,
27200 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27202 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */
27204 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "mov.l", 24,
27205 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27207 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
27209 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "mov.l", 24,
27210 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27212 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */
27214 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "mov.l", 32,
27215 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27217 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */
27219 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "mov.l", 32,
27220 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27222 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
27224 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "mov.l", 32,
27225 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27227 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */
27229 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "mov.l", 32,
27230 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27232 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */
27234 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "mov.l", 32,
27235 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27237 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
27239 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "mov.l", 32,
27240 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27242 /* mov.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */
27244 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "mov.l", 40,
27245 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27247 /* mov.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */
27249 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "mov.l", 40,
27250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27252 /* mov.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
27254 M32C_INSN_MOV32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "mov.l", 40,
27255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27257 /* mov.b${S} ${Dsp-8-u8}[sb],${Dst16AnQI-S} */
27259 M32C_INSN_MOV16_B_S_AN_SRC16_2_S_8_SB_RELATIVE_QI, "mov16.b.S-An-src16-2-S-8-SB-relative-QI", "mov.b", 16,
27260 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
27262 /* mov.b${S} ${Dsp-8-s8}[fb],${Dst16AnQI-S} */
27264 M32C_INSN_MOV16_B_S_AN_SRC16_2_S_8_FB_RELATIVE_QI, "mov16.b.S-An-src16-2-S-8-FB-relative-QI", "mov.b", 16,
27265 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
27267 /* mov.b${S} ${Dsp-8-u16},${Dst16AnQI-S} */
27269 M32C_INSN_MOV16_B_S_AN_SRC16_2_S_16_ABSOLUTE_QI, "mov16.b.S-An-src16-2-S-16-absolute-QI", "mov.b", 24,
27270 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
27272 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
27274 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24,
27275 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27277 /* mov.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
27279 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24,
27280 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27282 /* mov.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
27284 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 24,
27285 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27287 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
27289 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 24,
27290 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27292 /* mov.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
27294 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 24,
27295 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27297 /* mov.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
27299 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 24,
27300 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27302 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
27304 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 24,
27305 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27307 /* mov.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
27309 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 24,
27310 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27312 /* mov.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
27314 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 24,
27315 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27317 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
27319 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mov.w", 32,
27320 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27322 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
27324 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mov.w", 32,
27325 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27327 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
27329 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "mov.w", 32,
27330 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27332 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
27334 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mov.w", 40,
27335 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27337 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
27339 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mov.w", 40,
27340 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27342 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
27344 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "mov.w", 40,
27345 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27347 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
27349 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mov.w", 48,
27350 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27352 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
27354 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mov.w", 48,
27355 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27357 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
27359 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "mov.w", 48,
27360 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27362 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
27364 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mov.w", 32,
27365 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27367 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
27369 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mov.w", 32,
27370 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27372 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
27374 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "mov.w", 32,
27375 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27377 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
27379 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mov.w", 40,
27380 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27382 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
27384 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mov.w", 40,
27385 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27387 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
27389 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "mov.w", 40,
27390 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27392 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
27394 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mov.w", 32,
27395 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27397 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
27399 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mov.w", 32,
27400 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27402 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
27404 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "mov.w", 32,
27405 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27407 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
27409 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mov.w", 40,
27410 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27412 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
27414 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mov.w", 40,
27415 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27417 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
27419 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "mov.w", 40,
27420 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27422 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
27424 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mov.w", 40,
27425 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27427 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
27429 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mov.w", 40,
27430 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27432 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
27434 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "mov.w", 40,
27435 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27437 /* mov.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
27439 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mov.w", 48,
27440 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27442 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
27444 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mov.w", 48,
27445 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27447 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
27449 M32C_INSN_MOV32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "mov.w", 48,
27450 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27452 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
27454 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32,
27455 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27457 /* mov.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
27459 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32,
27460 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27462 /* mov.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
27464 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32,
27465 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27467 /* mov.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
27469 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32,
27470 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27472 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
27474 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 32,
27475 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27477 /* mov.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
27479 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 32,
27480 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27482 /* mov.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
27484 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 32,
27485 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27487 /* mov.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
27489 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 32,
27490 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27492 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
27494 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 32,
27495 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27497 /* mov.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
27499 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 32,
27500 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27502 /* mov.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
27504 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 32,
27505 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27507 /* mov.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
27509 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 32,
27510 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27512 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
27514 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mov.w", 40,
27515 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27517 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
27519 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mov.w", 40,
27520 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27522 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
27524 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mov.w", 40,
27525 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27527 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
27529 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "mov.w", 40,
27530 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27532 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
27534 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mov.w", 48,
27535 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27537 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
27539 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mov.w", 48,
27540 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27542 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
27544 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mov.w", 48,
27545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27547 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
27549 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "mov.w", 48,
27550 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27552 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
27554 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mov.w", 56,
27555 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27557 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
27559 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mov.w", 56,
27560 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27562 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
27564 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mov.w", 56,
27565 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27567 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
27569 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "mov.w", 56,
27570 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27572 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
27574 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mov.w", 40,
27575 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27577 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
27579 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mov.w", 40,
27580 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27582 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
27584 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mov.w", 40,
27585 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27587 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
27589 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "mov.w", 40,
27590 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27592 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
27594 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mov.w", 48,
27595 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27597 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
27599 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mov.w", 48,
27600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27602 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
27604 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mov.w", 48,
27605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27607 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
27609 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "mov.w", 48,
27610 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27612 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
27614 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mov.w", 40,
27615 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27617 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
27619 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mov.w", 40,
27620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27622 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
27624 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mov.w", 40,
27625 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27627 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
27629 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "mov.w", 40,
27630 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27632 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
27634 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mov.w", 48,
27635 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27637 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
27639 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mov.w", 48,
27640 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27642 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
27644 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mov.w", 48,
27645 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27647 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
27649 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "mov.w", 48,
27650 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27652 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
27654 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mov.w", 48,
27655 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27657 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
27659 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mov.w", 48,
27660 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27662 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
27664 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mov.w", 48,
27665 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27667 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
27669 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "mov.w", 48,
27670 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27672 /* mov.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
27674 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mov.w", 56,
27675 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27677 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
27679 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mov.w", 56,
27680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27682 /* mov.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
27684 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mov.w", 56,
27685 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27687 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
27689 M32C_INSN_MOV32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "mov.w", 56,
27690 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27692 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
27694 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 40,
27695 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27697 /* mov.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
27699 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 40,
27700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27702 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
27704 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 40,
27705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27707 /* mov.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
27709 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 40,
27710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27712 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
27714 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 40,
27715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27717 /* mov.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
27719 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 40,
27720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27722 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
27724 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mov.w", 48,
27725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27727 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
27729 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "mov.w", 48,
27730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27732 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
27734 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mov.w", 56,
27735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27737 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
27739 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "mov.w", 56,
27740 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27742 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
27744 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mov.w", 64,
27745 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27747 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
27749 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "mov.w", 64,
27750 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27752 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
27754 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mov.w", 48,
27755 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27757 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
27759 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "mov.w", 48,
27760 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27762 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
27764 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mov.w", 56,
27765 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27767 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
27769 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "mov.w", 56,
27770 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27772 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
27774 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mov.w", 48,
27775 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27777 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
27779 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "mov.w", 48,
27780 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27782 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
27784 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mov.w", 56,
27785 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27787 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
27789 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "mov.w", 56,
27790 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27792 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
27794 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mov.w", 56,
27795 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27797 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
27799 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "mov.w", 56,
27800 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27802 /* mov.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
27804 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mov.w", 64,
27805 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27807 /* mov.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
27809 M32C_INSN_MOV32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "mov.w", 64,
27810 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27812 /* mov.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
27814 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 16,
27815 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27817 /* mov.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
27819 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 16,
27820 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27822 /* mov.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
27824 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "mov.w", 16,
27825 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27827 /* mov.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
27829 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 16,
27830 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27832 /* mov.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
27834 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 16,
27835 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27837 /* mov.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
27839 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "mov.w", 16,
27840 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27842 /* mov.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
27844 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 16,
27845 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27847 /* mov.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
27849 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 16,
27850 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27852 /* mov.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
27854 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "mov.w", 16,
27855 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27857 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
27859 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 24,
27860 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27862 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
27864 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 24,
27865 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27867 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
27869 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 24,
27870 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27872 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
27874 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 32,
27875 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27877 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
27879 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 32,
27880 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27882 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
27884 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 32,
27885 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27887 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
27889 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 40,
27890 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27892 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
27894 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 40,
27895 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27897 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
27899 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 40,
27900 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27902 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
27904 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 24,
27905 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27907 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
27909 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 24,
27910 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27912 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
27914 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 24,
27915 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27917 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
27919 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 32,
27920 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27922 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
27924 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 32,
27925 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27927 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
27929 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 32,
27930 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27932 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
27934 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 24,
27935 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27937 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
27939 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 24,
27940 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27942 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
27944 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 24,
27945 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27947 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
27949 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 32,
27950 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27952 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
27954 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 32,
27955 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27957 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
27959 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 32,
27960 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27962 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
27964 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 32,
27965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27967 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
27969 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 32,
27970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27972 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
27974 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 32,
27975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27977 /* mov.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
27979 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 40,
27980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27982 /* mov.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
27984 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 40,
27985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27987 /* mov.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
27989 M32C_INSN_MOV32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 40,
27990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27992 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
27994 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24,
27995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
27997 /* mov.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
27999 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24,
28000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28002 /* mov.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
28004 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24,
28005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28007 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
28009 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 24,
28010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28012 /* mov.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
28014 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 24,
28015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28017 /* mov.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
28019 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 24,
28020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28022 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
28024 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 24,
28025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28027 /* mov.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
28029 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 24,
28030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28032 /* mov.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
28034 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 24,
28035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28037 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
28039 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mov.b", 32,
28040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28042 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
28044 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mov.b", 32,
28045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28047 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
28049 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "mov.b", 32,
28050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28052 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
28054 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mov.b", 40,
28055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28057 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
28059 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mov.b", 40,
28060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28062 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
28064 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "mov.b", 40,
28065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28067 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
28069 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mov.b", 48,
28070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28072 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
28074 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mov.b", 48,
28075 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28077 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
28079 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "mov.b", 48,
28080 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28082 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
28084 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mov.b", 32,
28085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28087 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
28089 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mov.b", 32,
28090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28092 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
28094 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "mov.b", 32,
28095 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28097 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
28099 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mov.b", 40,
28100 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28102 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
28104 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mov.b", 40,
28105 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28107 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
28109 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "mov.b", 40,
28110 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28112 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
28114 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mov.b", 32,
28115 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28117 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
28119 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mov.b", 32,
28120 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28122 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
28124 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "mov.b", 32,
28125 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28127 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
28129 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mov.b", 40,
28130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28132 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
28134 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mov.b", 40,
28135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28137 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
28139 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "mov.b", 40,
28140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28142 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
28144 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mov.b", 40,
28145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28147 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
28149 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mov.b", 40,
28150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28152 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
28154 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "mov.b", 40,
28155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28157 /* mov.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
28159 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mov.b", 48,
28160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28162 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
28164 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mov.b", 48,
28165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28167 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
28169 M32C_INSN_MOV32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "mov.b", 48,
28170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28172 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
28174 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 32,
28175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28177 /* mov.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
28179 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 32,
28180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28182 /* mov.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
28184 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 32,
28185 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28187 /* mov.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
28189 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 32,
28190 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28192 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
28194 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 32,
28195 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28197 /* mov.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
28199 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 32,
28200 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28202 /* mov.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
28204 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 32,
28205 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28207 /* mov.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
28209 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 32,
28210 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28212 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
28214 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 32,
28215 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28217 /* mov.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
28219 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 32,
28220 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28222 /* mov.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
28224 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 32,
28225 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28227 /* mov.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
28229 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 32,
28230 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28232 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
28234 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mov.b", 40,
28235 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28237 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
28239 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mov.b", 40,
28240 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28242 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
28244 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mov.b", 40,
28245 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28247 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
28249 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "mov.b", 40,
28250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28252 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
28254 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mov.b", 48,
28255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28257 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
28259 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mov.b", 48,
28260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28262 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
28264 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mov.b", 48,
28265 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28267 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
28269 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "mov.b", 48,
28270 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28272 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
28274 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mov.b", 56,
28275 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28277 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
28279 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mov.b", 56,
28280 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28282 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
28284 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mov.b", 56,
28285 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28287 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
28289 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "mov.b", 56,
28290 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28292 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
28294 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mov.b", 40,
28295 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28297 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
28299 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mov.b", 40,
28300 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28302 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
28304 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mov.b", 40,
28305 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28307 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
28309 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "mov.b", 40,
28310 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28312 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
28314 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mov.b", 48,
28315 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28317 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
28319 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mov.b", 48,
28320 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28322 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
28324 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mov.b", 48,
28325 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28327 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
28329 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "mov.b", 48,
28330 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28332 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
28334 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mov.b", 40,
28335 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28337 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
28339 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mov.b", 40,
28340 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28342 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
28344 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mov.b", 40,
28345 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28347 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
28349 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "mov.b", 40,
28350 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28352 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
28354 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mov.b", 48,
28355 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28357 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
28359 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mov.b", 48,
28360 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28362 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
28364 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mov.b", 48,
28365 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28367 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
28369 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "mov.b", 48,
28370 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28372 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
28374 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mov.b", 48,
28375 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28377 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
28379 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mov.b", 48,
28380 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28382 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
28384 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mov.b", 48,
28385 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28387 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
28389 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "mov.b", 48,
28390 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28392 /* mov.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
28394 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mov.b", 56,
28395 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28397 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
28399 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mov.b", 56,
28400 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28402 /* mov.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
28404 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mov.b", 56,
28405 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28407 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
28409 M32C_INSN_MOV32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "mov.b", 56,
28410 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28412 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
28414 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 40,
28415 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28417 /* mov.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
28419 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 40,
28420 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28422 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
28424 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 40,
28425 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28427 /* mov.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
28429 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 40,
28430 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28432 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
28434 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 40,
28435 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28437 /* mov.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
28439 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 40,
28440 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28442 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
28444 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mov.b", 48,
28445 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28447 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
28449 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "mov.b", 48,
28450 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28452 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
28454 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mov.b", 56,
28455 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28457 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
28459 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "mov.b", 56,
28460 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28462 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
28464 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mov.b", 64,
28465 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28467 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
28469 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "mov.b", 64,
28470 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28472 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
28474 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mov.b", 48,
28475 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28477 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
28479 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "mov.b", 48,
28480 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28482 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
28484 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mov.b", 56,
28485 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28487 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
28489 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "mov.b", 56,
28490 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28492 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
28494 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mov.b", 48,
28495 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28497 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
28499 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "mov.b", 48,
28500 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28502 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
28504 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mov.b", 56,
28505 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28507 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
28509 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "mov.b", 56,
28510 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28512 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
28514 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mov.b", 56,
28515 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28517 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
28519 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "mov.b", 56,
28520 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28522 /* mov.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
28524 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mov.b", 64,
28525 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28527 /* mov.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
28529 M32C_INSN_MOV32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "mov.b", 64,
28530 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28532 /* mov.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
28534 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 16,
28535 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28537 /* mov.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
28539 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 16,
28540 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28542 /* mov.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
28544 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "mov.b", 16,
28545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28547 /* mov.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
28549 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 16,
28550 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28552 /* mov.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
28554 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 16,
28555 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28557 /* mov.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
28559 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "mov.b", 16,
28560 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28562 /* mov.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
28564 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 16,
28565 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28567 /* mov.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
28569 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 16,
28570 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28572 /* mov.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
28574 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "mov.b", 16,
28575 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28577 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
28579 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 24,
28580 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28582 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
28584 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 24,
28585 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28587 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
28589 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 24,
28590 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28592 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
28594 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 32,
28595 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28597 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
28599 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 32,
28600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28602 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
28604 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 32,
28605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28607 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
28609 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 40,
28610 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28612 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
28614 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 40,
28615 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28617 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
28619 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 40,
28620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28622 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
28624 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 24,
28625 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28627 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
28629 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 24,
28630 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28632 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
28634 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 24,
28635 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28637 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
28639 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 32,
28640 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28642 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
28644 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 32,
28645 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28647 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
28649 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 32,
28650 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28652 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
28654 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 24,
28655 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28657 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
28659 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 24,
28660 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28662 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
28664 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 24,
28665 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28667 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
28669 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 32,
28670 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28672 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
28674 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 32,
28675 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28677 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
28679 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 32,
28680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28682 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
28684 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 32,
28685 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28687 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
28689 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 32,
28690 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28692 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
28694 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 32,
28695 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28697 /* mov.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
28699 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 40,
28700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28702 /* mov.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
28704 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 40,
28705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28707 /* mov.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
28709 M32C_INSN_MOV32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 40,
28710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
28712 /* mov.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
28714 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "mov.w", 24,
28715 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28717 /* mov.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
28719 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "mov.w", 24,
28720 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28722 /* mov.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
28724 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "mov.w", 24,
28725 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28727 /* mov.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
28729 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "mov.w", 24,
28730 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28732 /* mov.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
28734 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "mov.w", 24,
28735 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28737 /* mov.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
28739 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "mov.w", 24,
28740 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28742 /* mov.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
28744 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "mov.w", 24,
28745 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28747 /* mov.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
28749 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "mov.w", 24,
28750 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28752 /* mov.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
28754 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "mov.w", 24,
28755 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28757 /* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
28759 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "mov.w", 32,
28760 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28762 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
28764 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "mov.w", 32,
28765 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28767 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
28769 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "mov.w", 32,
28770 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28772 /* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
28774 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "mov.w", 40,
28775 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28777 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
28779 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "mov.w", 40,
28780 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28782 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
28784 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "mov.w", 40,
28785 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28787 /* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
28789 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "mov.w", 32,
28790 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28792 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
28794 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "mov.w", 32,
28795 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28797 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
28799 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "mov.w", 32,
28800 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28802 /* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
28804 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "mov.w", 40,
28805 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28807 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
28809 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "mov.w", 40,
28810 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28812 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
28814 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "mov.w", 40,
28815 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28817 /* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
28819 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "mov.w", 32,
28820 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28822 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
28824 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "mov.w", 32,
28825 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28827 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
28829 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "mov.w", 32,
28830 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28832 /* mov.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
28834 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mov16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "mov.w", 40,
28835 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28837 /* mov.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
28839 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mov16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "mov.w", 40,
28840 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28842 /* mov.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
28844 M32C_INSN_MOV16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "mov16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "mov.w", 40,
28845 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28847 /* mov.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
28849 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "mov.w", 32,
28850 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28852 /* mov.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
28854 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "mov.w", 32,
28855 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28857 /* mov.w${G} ${Dsp-16-u16},$Dst16RnHI */
28859 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "mov.w", 32,
28860 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28862 /* mov.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
28864 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "mov.w", 32,
28865 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28867 /* mov.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
28869 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "mov.w", 32,
28870 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28872 /* mov.w${G} ${Dsp-16-u16},$Dst16AnHI */
28874 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "mov.w", 32,
28875 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28877 /* mov.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
28879 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "mov.w", 32,
28880 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28882 /* mov.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
28884 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "mov.w", 32,
28885 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28887 /* mov.w${G} ${Dsp-16-u16},[$Dst16An] */
28889 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "mov.w", 32,
28890 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28892 /* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
28894 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "mov.w", 40,
28895 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28897 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
28899 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "mov.w", 40,
28900 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28902 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
28904 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "mov.w", 40,
28905 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28907 /* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
28909 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "mov.w", 48,
28910 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28912 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
28914 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "mov.w", 48,
28915 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28917 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
28919 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "mov.w", 48,
28920 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28922 /* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
28924 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "mov.w", 40,
28925 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28927 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
28929 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "mov.w", 40,
28930 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28932 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
28934 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "mov.w", 40,
28935 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28937 /* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
28939 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "mov.w", 48,
28940 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28942 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
28944 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "mov.w", 48,
28945 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28947 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
28949 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "mov.w", 48,
28950 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28952 /* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
28954 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "mov.w", 40,
28955 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28957 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
28959 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "mov.w", 40,
28960 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28962 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
28964 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "mov.w", 40,
28965 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28967 /* mov.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
28969 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mov16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "mov.w", 48,
28970 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28972 /* mov.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
28974 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "mov16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "mov.w", 48,
28975 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28977 /* mov.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
28979 M32C_INSN_MOV16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "mov16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "mov.w", 48,
28980 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28982 /* mov.w${G} $Src16RnHI,$Dst16RnHI */
28984 M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "mov.w", 16,
28985 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28987 /* mov.w${G} $Src16AnHI,$Dst16RnHI */
28989 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "mov.w", 16,
28990 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28992 /* mov.w${G} [$Src16An],$Dst16RnHI */
28994 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "mov.w", 16,
28995 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
28997 /* mov.w${G} $Src16RnHI,$Dst16AnHI */
28999 M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "mov.w", 16,
29000 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29002 /* mov.w${G} $Src16AnHI,$Dst16AnHI */
29004 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "mov.w", 16,
29005 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29007 /* mov.w${G} [$Src16An],$Dst16AnHI */
29009 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "mov.w", 16,
29010 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29012 /* mov.w${G} $Src16RnHI,[$Dst16An] */
29014 M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "mov.w", 16,
29015 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29017 /* mov.w${G} $Src16AnHI,[$Dst16An] */
29019 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "mov.w", 16,
29020 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29022 /* mov.w${G} [$Src16An],[$Dst16An] */
29024 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "mov.w", 16,
29025 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29027 /* mov.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
29029 M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "mov.w", 24,
29030 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29032 /* mov.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
29034 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "mov.w", 24,
29035 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29037 /* mov.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
29039 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "mov.w", 24,
29040 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29042 /* mov.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
29044 M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "mov.w", 32,
29045 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29047 /* mov.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
29049 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "mov.w", 32,
29050 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29052 /* mov.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
29054 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "mov.w", 32,
29055 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29057 /* mov.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
29059 M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "mov.w", 24,
29060 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29062 /* mov.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
29064 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "mov.w", 24,
29065 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29067 /* mov.w${G} [$Src16An],${Dsp-16-u8}[sb] */
29069 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "mov.w", 24,
29070 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29072 /* mov.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
29074 M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "mov.w", 32,
29075 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29077 /* mov.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
29079 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "mov.w", 32,
29080 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29082 /* mov.w${G} [$Src16An],${Dsp-16-u16}[sb] */
29084 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "mov.w", 32,
29085 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29087 /* mov.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
29089 M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "mov.w", 24,
29090 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29092 /* mov.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
29094 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "mov.w", 24,
29095 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29097 /* mov.w${G} [$Src16An],${Dsp-16-s8}[fb] */
29099 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "mov.w", 24,
29100 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29102 /* mov.w${G} $Src16RnHI,${Dsp-16-u16} */
29104 M32C_INSN_MOV16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mov16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "mov.w", 32,
29105 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29107 /* mov.w${G} $Src16AnHI,${Dsp-16-u16} */
29109 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mov16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "mov.w", 32,
29110 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29112 /* mov.w${G} [$Src16An],${Dsp-16-u16} */
29114 M32C_INSN_MOV16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "mov16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "mov.w", 32,
29115 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29117 /* mov.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
29119 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "mov.b", 24,
29120 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29122 /* mov.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
29124 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "mov.b", 24,
29125 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29127 /* mov.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
29129 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "mov.b", 24,
29130 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29132 /* mov.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
29134 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "mov.b", 24,
29135 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29137 /* mov.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
29139 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "mov.b", 24,
29140 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29142 /* mov.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
29144 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "mov.b", 24,
29145 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29147 /* mov.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
29149 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "mov.b", 24,
29150 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29152 /* mov.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
29154 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "mov.b", 24,
29155 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29157 /* mov.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
29159 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "mov.b", 24,
29160 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29162 /* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
29164 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "mov.b", 32,
29165 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29167 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
29169 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "mov.b", 32,
29170 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29172 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
29174 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "mov.b", 32,
29175 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29177 /* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
29179 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "mov.b", 40,
29180 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29182 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
29184 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "mov.b", 40,
29185 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29187 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
29189 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "mov.b", 40,
29190 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29192 /* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
29194 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "mov.b", 32,
29195 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29197 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
29199 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "mov.b", 32,
29200 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29202 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
29204 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "mov.b", 32,
29205 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29207 /* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
29209 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "mov.b", 40,
29210 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29212 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
29214 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "mov.b", 40,
29215 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29217 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
29219 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "mov.b", 40,
29220 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29222 /* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
29224 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "mov.b", 32,
29225 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29227 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
29229 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "mov.b", 32,
29230 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29232 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
29234 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "mov.b", 32,
29235 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29237 /* mov.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
29239 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mov16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "mov.b", 40,
29240 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29242 /* mov.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
29244 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mov16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "mov.b", 40,
29245 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29247 /* mov.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
29249 M32C_INSN_MOV16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "mov16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "mov.b", 40,
29250 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29252 /* mov.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
29254 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "mov.b", 32,
29255 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29257 /* mov.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
29259 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "mov.b", 32,
29260 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29262 /* mov.b${G} ${Dsp-16-u16},$Dst16RnQI */
29264 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "mov.b", 32,
29265 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29267 /* mov.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
29269 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "mov.b", 32,
29270 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29272 /* mov.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
29274 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "mov.b", 32,
29275 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29277 /* mov.b${G} ${Dsp-16-u16},$Dst16AnQI */
29279 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "mov.b", 32,
29280 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29282 /* mov.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
29284 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "mov.b", 32,
29285 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29287 /* mov.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
29289 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "mov.b", 32,
29290 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29292 /* mov.b${G} ${Dsp-16-u16},[$Dst16An] */
29294 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "mov.b", 32,
29295 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29297 /* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
29299 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "mov.b", 40,
29300 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29302 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
29304 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "mov.b", 40,
29305 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29307 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
29309 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "mov.b", 40,
29310 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29312 /* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
29314 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "mov.b", 48,
29315 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29317 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
29319 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "mov.b", 48,
29320 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29322 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
29324 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "mov.b", 48,
29325 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29327 /* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
29329 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "mov.b", 40,
29330 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29332 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
29334 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "mov.b", 40,
29335 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29337 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
29339 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "mov.b", 40,
29340 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29342 /* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
29344 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "mov.b", 48,
29345 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29347 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
29349 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "mov.b", 48,
29350 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29352 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
29354 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "mov.b", 48,
29355 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29357 /* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
29359 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "mov.b", 40,
29360 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29362 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
29364 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "mov.b", 40,
29365 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29367 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
29369 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "mov.b", 40,
29370 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29372 /* mov.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
29374 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mov16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "mov.b", 48,
29375 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29377 /* mov.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
29379 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "mov16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "mov.b", 48,
29380 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29382 /* mov.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
29384 M32C_INSN_MOV16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "mov16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "mov.b", 48,
29385 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29387 /* mov.b${G} $Src16RnQI,$Dst16RnQI */
29389 M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "mov.b", 16,
29390 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29392 /* mov.b${G} $Src16AnQI,$Dst16RnQI */
29394 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "mov.b", 16,
29395 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29397 /* mov.b${G} [$Src16An],$Dst16RnQI */
29399 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "mov.b", 16,
29400 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29402 /* mov.b${G} $Src16RnQI,$Dst16AnQI */
29404 M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "mov.b", 16,
29405 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29407 /* mov.b${G} $Src16AnQI,$Dst16AnQI */
29409 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "mov.b", 16,
29410 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29412 /* mov.b${G} [$Src16An],$Dst16AnQI */
29414 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "mov.b", 16,
29415 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29417 /* mov.b${G} $Src16RnQI,[$Dst16An] */
29419 M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "mov.b", 16,
29420 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29422 /* mov.b${G} $Src16AnQI,[$Dst16An] */
29424 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "mov.b", 16,
29425 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29427 /* mov.b${G} [$Src16An],[$Dst16An] */
29429 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "mov.b", 16,
29430 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29432 /* mov.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
29434 M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "mov.b", 24,
29435 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29437 /* mov.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
29439 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "mov.b", 24,
29440 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29442 /* mov.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
29444 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "mov.b", 24,
29445 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29447 /* mov.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
29449 M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "mov.b", 32,
29450 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29452 /* mov.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
29454 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "mov.b", 32,
29455 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29457 /* mov.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
29459 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "mov.b", 32,
29460 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29462 /* mov.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
29464 M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "mov.b", 24,
29465 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29467 /* mov.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
29469 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "mov.b", 24,
29470 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29472 /* mov.b${G} [$Src16An],${Dsp-16-u8}[sb] */
29474 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "mov.b", 24,
29475 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29477 /* mov.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
29479 M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "mov.b", 32,
29480 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29482 /* mov.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
29484 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "mov.b", 32,
29485 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29487 /* mov.b${G} [$Src16An],${Dsp-16-u16}[sb] */
29489 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "mov.b", 32,
29490 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29492 /* mov.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
29494 M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "mov.b", 24,
29495 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29497 /* mov.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
29499 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "mov.b", 24,
29500 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29502 /* mov.b${G} [$Src16An],${Dsp-16-s8}[fb] */
29504 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "mov.b", 24,
29505 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29507 /* mov.b${G} $Src16RnQI,${Dsp-16-u16} */
29509 M32C_INSN_MOV16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mov16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "mov.b", 32,
29510 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29512 /* mov.b${G} $Src16AnQI,${Dsp-16-u16} */
29514 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mov16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "mov.b", 32,
29515 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29517 /* mov.b${G} [$Src16An],${Dsp-16-u16} */
29519 M32C_INSN_MOV16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "mov16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "mov.b", 32,
29520 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29522 /* mov.w${Z} #0,${Dsp-8-u8}[sb] */
29524 M32C_INSN_MOV32_W_IMM_Z_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-imm-Z-2-S-8-dst32-2-S-8-SB-relative-HI", "mov.w", 16,
29525 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29527 /* mov.w${Z} #0,${Dsp-8-s8}[fb] */
29529 M32C_INSN_MOV32_W_IMM_Z_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-imm-Z-2-S-8-dst32-2-S-8-FB-relative-HI", "mov.w", 16,
29530 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29532 /* mov.w${Z} #0,${Dsp-8-u16} */
29534 M32C_INSN_MOV32_W_IMM_Z_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-imm-Z-2-S-16-dst32-2-S-16-absolute-HI", "mov.w", 24,
29535 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29537 /* mov.w${Z} #0,r0 */
29539 M32C_INSN_MOV32_W_IMM_Z_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "mov32.w-imm-Z-2-S-basic-dst32-2-S-R0-direct-HI", "mov.w", 8,
29540 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29542 /* mov.b${Z} #0,${Dsp-8-u8}[sb] */
29544 M32C_INSN_MOV32_B_IMM_Z_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-imm-Z-2-S-8-dst32-2-S-8-SB-relative-QI", "mov.b", 16,
29545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29547 /* mov.b${Z} #0,${Dsp-8-s8}[fb] */
29549 M32C_INSN_MOV32_B_IMM_Z_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-imm-Z-2-S-8-dst32-2-S-8-FB-relative-QI", "mov.b", 16,
29550 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29552 /* mov.b${Z} #0,${Dsp-8-u16} */
29554 M32C_INSN_MOV32_B_IMM_Z_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-imm-Z-2-S-16-dst32-2-S-16-absolute-QI", "mov.b", 24,
29555 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29557 /* mov.b${Z} #0,r0l */
29559 M32C_INSN_MOV32_B_IMM_Z_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "mov32.b-imm-Z-2-S-basic-dst32-2-S-R0l-direct-QI", "mov.b", 8,
29560 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29562 /* mov.b${Z} #0,r0l */
29564 M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-R0l-direct-QI", "mov.b", 8,
29565 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29567 /* mov.b${Z} #0,r0h */
29569 M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-R0h-direct-QI", "mov.b", 8,
29570 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29572 /* mov.b${Z} #0,${Dsp-8-u8}[sb] */
29574 M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_8_SB_RELATIVE_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-8-8-SB-relative-QI", "mov.b", 16,
29575 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29577 /* mov.b${Z} #0,${Dsp-8-s8}[fb] */
29579 M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_8_FB_RELATIVE_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-8-8-FB-relative-QI", "mov.b", 16,
29580 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29582 /* mov.b${Z} #0,${Dsp-8-u16} */
29584 M32C_INSN_MOV16_B_Z_IMM8_DST3_DST16_3_S_8_16_ABSOLUTE_QI, "mov16.b-Z-imm8-dst3-dst16-3-S-8-16-absolute-QI", "mov.b", 24,
29585 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29587 /* mov.b${S} #${Imm-8-QI},r0l */
29589 M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "mov16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "mov.b", 16,
29590 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29592 /* mov.b${S} #${Imm-8-QI},r0h */
29594 M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "mov16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "mov.b", 16,
29595 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29597 /* mov.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
29599 M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "mov16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "mov.b", 24,
29600 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29602 /* mov.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
29604 M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "mov16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "mov.b", 24,
29605 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29607 /* mov.b${S} #${Imm-8-QI},${Dsp-16-u16} */
29609 M32C_INSN_MOV16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "mov16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "mov.b", 32,
29610 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29612 /* mov.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
29614 M32C_INSN_MOV32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "mov32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "mov.w", 32,
29615 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29617 /* mov.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
29619 M32C_INSN_MOV32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "mov32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "mov.w", 32,
29620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29622 /* mov.w${S} #${Imm-24-HI},${Dsp-8-u16} */
29624 M32C_INSN_MOV32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "mov32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "mov.w", 40,
29625 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29627 /* mov.w${S} #${Imm-8-HI},r0 */
29629 M32C_INSN_MOV32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "mov32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "mov.w", 24,
29630 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29632 /* mov.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
29634 M32C_INSN_MOV32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "mov32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "mov.b", 24,
29635 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29637 /* mov.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
29639 M32C_INSN_MOV32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "mov32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "mov.b", 24,
29640 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29642 /* mov.b${S} #${Imm-24-QI},${Dsp-8-u16} */
29644 M32C_INSN_MOV32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "mov32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "mov.b", 32,
29645 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29647 /* mov.b${S} #${Imm-8-QI},r0l */
29649 M32C_INSN_MOV32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "mov32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "mov.b", 16,
29650 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29652 /* mov.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */
29654 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mov.w", 16,
29655 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29657 /* mov.w${Q} #${Imm-12-s4},$Dst32AnUnprefixedHI */
29659 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "mov.w", 16,
29660 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29662 /* mov.w${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
29664 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mov.w", 16,
29665 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29667 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
29669 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 24,
29670 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29672 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
29674 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 32,
29675 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29677 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
29679 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 40,
29680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29682 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
29684 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 24,
29685 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29687 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
29689 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 32,
29690 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29692 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
29694 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 24,
29695 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29697 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
29699 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 32,
29700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29702 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u16} */
29704 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 32,
29705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29707 /* mov.w${Q} #${Imm-12-s4},${Dsp-16-u24} */
29709 M32C_INSN_MOV32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 40,
29710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29712 /* mov.b${Q} #${Imm-12-s4},$Dst32RnUnprefixedQI */
29714 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mov.b", 16,
29715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29717 /* mov.b${Q} #${Imm-12-s4},$Dst32AnUnprefixedQI */
29719 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "mov.b", 16,
29720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29722 /* mov.b${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
29724 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mov.b", 16,
29725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29727 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
29729 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 24,
29730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29732 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
29734 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 32,
29735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29737 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
29739 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 40,
29740 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29742 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
29744 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 24,
29745 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29747 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
29749 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 32,
29750 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29752 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
29754 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 24,
29755 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29757 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
29759 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 32,
29760 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29762 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u16} */
29764 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 32,
29765 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29767 /* mov.b${Q} #${Imm-12-s4},${Dsp-16-u24} */
29769 M32C_INSN_MOV32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 40,
29770 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29772 /* mov.w${Q} #${Imm-8-s4},$Dst16RnQI */
29774 M32C_INSN_MOV16_W_IMM4_Q_16_DST16_RN_DIRECT_QI, "mov16.w-imm4-Q-16-dst16-Rn-direct-QI", "mov.w", 16,
29775 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29777 /* mov.w${Q} #${Imm-8-s4},$Dst16AnQI */
29779 M32C_INSN_MOV16_W_IMM4_Q_16_DST16_AN_DIRECT_QI, "mov16.w-imm4-Q-16-dst16-An-direct-QI", "mov.w", 16,
29780 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29782 /* mov.w${Q} #${Imm-8-s4},[$Dst16An] */
29784 M32C_INSN_MOV16_W_IMM4_Q_16_DST16_AN_INDIRECT_QI, "mov16.w-imm4-Q-16-dst16-An-indirect-QI", "mov.w", 16,
29785 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29787 /* mov.w${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
29789 M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "mov16.w-imm4-Q-16-dst16-16-8-An-relative-QI", "mov.w", 24,
29790 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29792 /* mov.w${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
29794 M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "mov16.w-imm4-Q-16-dst16-16-16-An-relative-QI", "mov.w", 32,
29795 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29797 /* mov.w${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
29799 M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "mov16.w-imm4-Q-16-dst16-16-8-SB-relative-QI", "mov.w", 24,
29800 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29802 /* mov.w${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
29804 M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "mov16.w-imm4-Q-16-dst16-16-16-SB-relative-QI", "mov.w", 32,
29805 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29807 /* mov.w${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
29809 M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "mov16.w-imm4-Q-16-dst16-16-8-FB-relative-QI", "mov.w", 24,
29810 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29812 /* mov.w${Q} #${Imm-8-s4},${Dsp-16-u16} */
29814 M32C_INSN_MOV16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "mov16.w-imm4-Q-16-dst16-16-16-absolute-QI", "mov.w", 32,
29815 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29817 /* mov.b${Q} #${Imm-8-s4},$Dst16RnQI */
29819 M32C_INSN_MOV16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "mov16.b-imm4-Q-16-dst16-Rn-direct-QI", "mov.b", 16,
29820 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29822 /* mov.b${Q} #${Imm-8-s4},$Dst16AnQI */
29824 M32C_INSN_MOV16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "mov16.b-imm4-Q-16-dst16-An-direct-QI", "mov.b", 16,
29825 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29827 /* mov.b${Q} #${Imm-8-s4},[$Dst16An] */
29829 M32C_INSN_MOV16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "mov16.b-imm4-Q-16-dst16-An-indirect-QI", "mov.b", 16,
29830 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29832 /* mov.b${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
29834 M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "mov.b", 24,
29835 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29837 /* mov.b${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
29839 M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "mov.b", 32,
29840 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29842 /* mov.b${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
29844 M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "mov.b", 24,
29845 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29847 /* mov.b${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
29849 M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "mov.b", 32,
29850 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29852 /* mov.b${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
29854 M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "mov16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "mov.b", 24,
29855 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29857 /* mov.b${Q} #${Imm-8-s4},${Dsp-16-u16} */
29859 M32C_INSN_MOV16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "mov16.b-imm4-Q-16-dst16-16-16-absolute-QI", "mov.b", 32,
29860 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
29862 /* mov.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */
29864 M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "mov32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "mov.l", 48,
29865 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29867 /* mov.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */
29869 M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "mov32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "mov.l", 48,
29870 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29872 /* mov.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */
29874 M32C_INSN_MOV32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "mov32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "mov.l", 48,
29875 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29877 /* mov.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
29879 M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "mov.l", 56,
29880 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29882 /* mov.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */
29884 M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "mov.l", 56,
29885 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29887 /* mov.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */
29889 M32C_INSN_MOV32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "mov.l", 56,
29890 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29892 /* mov.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
29894 M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "mov.l", 64,
29895 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29897 /* mov.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */
29899 M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "mov.l", 64,
29900 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29902 /* mov.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */
29904 M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "mov.l", 64,
29905 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29907 /* mov.l${G} #${Imm-32-SI},${Dsp-16-u16} */
29909 M32C_INSN_MOV32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "mov32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "mov.l", 64,
29910 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29912 /* mov.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
29914 M32C_INSN_MOV32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "mov32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "mov.l", 72,
29915 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29917 /* mov.l${G} #${Imm-40-SI},${Dsp-16-u24} */
29919 M32C_INSN_MOV32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "mov32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "mov.l", 72,
29920 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29922 /* mov.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
29924 M32C_INSN_MOV32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "mov32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "mov.w", 32,
29925 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29927 /* mov.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
29929 M32C_INSN_MOV32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "mov32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "mov.w", 32,
29930 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29932 /* mov.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
29934 M32C_INSN_MOV32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "mov32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "mov.w", 32,
29935 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29937 /* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
29939 M32C_INSN_MOV32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "mov.w", 40,
29940 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29942 /* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
29944 M32C_INSN_MOV32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "mov.w", 40,
29945 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29947 /* mov.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
29949 M32C_INSN_MOV32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "mov.w", 40,
29950 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29952 /* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
29954 M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "mov.w", 48,
29955 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29957 /* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
29959 M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "mov.w", 48,
29960 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29962 /* mov.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
29964 M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "mov.w", 48,
29965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29967 /* mov.w${G} #${Imm-32-HI},${Dsp-16-u16} */
29969 M32C_INSN_MOV32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "mov32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "mov.w", 48,
29970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29972 /* mov.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
29974 M32C_INSN_MOV32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "mov32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "mov.w", 56,
29975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29977 /* mov.w${G} #${Imm-40-HI},${Dsp-16-u24} */
29979 M32C_INSN_MOV32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "mov32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "mov.w", 56,
29980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29982 /* mov.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
29984 M32C_INSN_MOV32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "mov32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "mov.b", 24,
29985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29987 /* mov.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
29989 M32C_INSN_MOV32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "mov32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "mov.b", 24,
29990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29992 /* mov.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
29994 M32C_INSN_MOV32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "mov32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "mov.b", 24,
29995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
29997 /* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
29999 M32C_INSN_MOV32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "mov.b", 32,
30000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30002 /* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
30004 M32C_INSN_MOV32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "mov.b", 32,
30005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30007 /* mov.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
30009 M32C_INSN_MOV32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "mov.b", 32,
30010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30012 /* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
30014 M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "mov.b", 40,
30015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30017 /* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
30019 M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "mov.b", 40,
30020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30022 /* mov.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
30024 M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "mov.b", 40,
30025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30027 /* mov.b${G} #${Imm-32-QI},${Dsp-16-u16} */
30029 M32C_INSN_MOV32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "mov32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "mov.b", 40,
30030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30032 /* mov.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
30034 M32C_INSN_MOV32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "mov32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "mov.b", 48,
30035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30037 /* mov.b${G} #${Imm-40-QI},${Dsp-16-u24} */
30039 M32C_INSN_MOV32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "mov32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "mov.b", 48,
30040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30042 /* mov.w${G} #${Imm-16-HI},$Dst16RnHI */
30044 M32C_INSN_MOV16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "mov16.w-imm-G-basic-dst16-Rn-direct-HI", "mov.w", 32,
30045 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30047 /* mov.w${G} #${Imm-16-HI},$Dst16AnHI */
30049 M32C_INSN_MOV16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "mov16.w-imm-G-basic-dst16-An-direct-HI", "mov.w", 32,
30050 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30052 /* mov.w${G} #${Imm-16-HI},[$Dst16An] */
30054 M32C_INSN_MOV16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "mov16.w-imm-G-basic-dst16-An-indirect-HI", "mov.w", 32,
30055 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30057 /* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
30059 M32C_INSN_MOV16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "mov16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "mov.w", 40,
30060 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30062 /* mov.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
30064 M32C_INSN_MOV16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "mov16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "mov.w", 40,
30065 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30067 /* mov.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
30069 M32C_INSN_MOV16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "mov16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "mov.w", 40,
30070 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30072 /* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
30074 M32C_INSN_MOV16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "mov16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "mov.w", 48,
30075 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30077 /* mov.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
30079 M32C_INSN_MOV16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "mov16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "mov.w", 48,
30080 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30082 /* mov.w${G} #${Imm-32-HI},${Dsp-16-u16} */
30084 M32C_INSN_MOV16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "mov16.w-imm-G-16-16-dst16-16-16-absolute-HI", "mov.w", 48,
30085 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30087 /* mov.b${G} #${Imm-16-QI},$Dst16RnQI */
30089 M32C_INSN_MOV16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "mov16.b-imm-G-basic-dst16-Rn-direct-QI", "mov.b", 24,
30090 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30092 /* mov.b${G} #${Imm-16-QI},$Dst16AnQI */
30094 M32C_INSN_MOV16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "mov16.b-imm-G-basic-dst16-An-direct-QI", "mov.b", 24,
30095 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30097 /* mov.b${G} #${Imm-16-QI},[$Dst16An] */
30099 M32C_INSN_MOV16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "mov16.b-imm-G-basic-dst16-An-indirect-QI", "mov.b", 24,
30100 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30102 /* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
30104 M32C_INSN_MOV16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "mov16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "mov.b", 32,
30105 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30107 /* mov.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
30109 M32C_INSN_MOV16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "mov16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "mov.b", 32,
30110 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30112 /* mov.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
30114 M32C_INSN_MOV16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "mov16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "mov.b", 32,
30115 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30117 /* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
30119 M32C_INSN_MOV16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "mov16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "mov.b", 40,
30120 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30122 /* mov.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
30124 M32C_INSN_MOV16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "mov16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "mov.b", 40,
30125 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30127 /* mov.b${G} #${Imm-32-QI},${Dsp-16-u16} */
30129 M32C_INSN_MOV16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "mov16.b-imm-G-16-16-dst16-16-16-absolute-QI", "mov.b", 40,
30130 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
30132 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
30134 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 32,
30135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30137 /* min.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
30139 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 32,
30140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30142 /* min.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
30144 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 32,
30145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30147 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
30149 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 32,
30150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30152 /* min.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
30154 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 32,
30155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30157 /* min.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
30159 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 32,
30160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30162 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
30164 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 32,
30165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30167 /* min.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
30169 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 32,
30170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30172 /* min.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
30174 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 32,
30175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30177 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
30179 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "min.w", 40,
30180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30182 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
30184 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "min.w", 40,
30185 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30187 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
30189 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "min.w", 40,
30190 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30192 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
30194 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "min.w", 48,
30195 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30197 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
30199 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "min.w", 48,
30200 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30202 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
30204 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "min.w", 48,
30205 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30207 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
30209 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "min.w", 56,
30210 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30212 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
30214 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "min.w", 56,
30215 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30217 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
30219 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "min.w", 56,
30220 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30222 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
30224 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "min.w", 40,
30225 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30227 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
30229 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "min.w", 40,
30230 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30232 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
30234 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "min.w", 40,
30235 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30237 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
30239 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "min.w", 48,
30240 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30242 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
30244 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "min.w", 48,
30245 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30247 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
30249 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "min.w", 48,
30250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30252 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
30254 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "min.w", 40,
30255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30257 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
30259 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "min.w", 40,
30260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30262 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
30264 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "min.w", 40,
30265 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30267 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
30269 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "min.w", 48,
30270 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30272 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
30274 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "min.w", 48,
30275 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30277 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
30279 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "min.w", 48,
30280 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30282 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
30284 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "min.w", 48,
30285 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30287 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
30289 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "min.w", 48,
30290 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30292 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
30294 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "min.w", 48,
30295 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30297 /* min.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
30299 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "min.w", 56,
30300 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30302 /* min.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
30304 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "min.w", 56,
30305 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30307 /* min.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
30309 M32C_INSN_MIN32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "min.w", 56,
30310 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30312 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
30314 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 40,
30315 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30317 /* min.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
30319 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 40,
30320 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30322 /* min.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
30324 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 40,
30325 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30327 /* min.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
30329 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 40,
30330 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30332 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
30334 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 40,
30335 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30337 /* min.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
30339 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 40,
30340 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30342 /* min.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
30344 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 40,
30345 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30347 /* min.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
30349 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 40,
30350 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30352 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
30354 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 40,
30355 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30357 /* min.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
30359 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 40,
30360 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30362 /* min.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
30364 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 40,
30365 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30367 /* min.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
30369 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 40,
30370 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30372 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
30374 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "min.w", 48,
30375 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30377 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
30379 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "min.w", 48,
30380 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30382 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
30384 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "min.w", 48,
30385 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30387 /* min.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
30389 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "min.w", 48,
30390 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30392 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
30394 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "min.w", 56,
30395 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30397 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
30399 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "min.w", 56,
30400 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30402 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
30404 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "min.w", 56,
30405 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30407 /* min.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
30409 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "min.w", 56,
30410 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30412 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
30414 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "min.w", 64,
30415 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30417 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
30419 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "min.w", 64,
30420 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30422 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
30424 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "min.w", 64,
30425 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30427 /* min.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
30429 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "min.w", 64,
30430 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30432 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
30434 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "min.w", 48,
30435 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30437 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
30439 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "min.w", 48,
30440 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30442 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
30444 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "min.w", 48,
30445 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30447 /* min.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
30449 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "min.w", 48,
30450 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30452 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
30454 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "min.w", 56,
30455 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30457 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
30459 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "min.w", 56,
30460 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30462 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
30464 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "min.w", 56,
30465 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30467 /* min.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
30469 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "min.w", 56,
30470 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30472 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
30474 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "min.w", 48,
30475 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30477 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
30479 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "min.w", 48,
30480 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30482 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
30484 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "min.w", 48,
30485 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30487 /* min.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
30489 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "min.w", 48,
30490 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30492 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
30494 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "min.w", 56,
30495 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30497 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
30499 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "min.w", 56,
30500 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30502 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
30504 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "min.w", 56,
30505 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30507 /* min.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
30509 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "min.w", 56,
30510 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30512 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
30514 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "min.w", 56,
30515 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30517 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
30519 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "min.w", 56,
30520 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30522 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
30524 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "min.w", 56,
30525 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30527 /* min.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
30529 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "min.w", 56,
30530 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30532 /* min.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
30534 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "min.w", 64,
30535 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30537 /* min.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
30539 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "min.w", 64,
30540 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30542 /* min.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
30544 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "min.w", 64,
30545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30547 /* min.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
30549 M32C_INSN_MIN32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "min.w", 64,
30550 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30552 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
30554 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 48,
30555 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30557 /* min.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
30559 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 48,
30560 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30562 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
30564 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 48,
30565 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30567 /* min.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
30569 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 48,
30570 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30572 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
30574 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 48,
30575 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30577 /* min.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
30579 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 48,
30580 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30582 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
30584 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "min.w", 56,
30585 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30587 /* min.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
30589 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "min.w", 56,
30590 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30592 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
30594 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "min.w", 64,
30595 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30597 /* min.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
30599 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "min.w", 64,
30600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30602 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
30604 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "min.w", 72,
30605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30607 /* min.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
30609 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "min.w", 72,
30610 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30612 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
30614 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "min.w", 56,
30615 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30617 /* min.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
30619 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "min.w", 56,
30620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30622 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
30624 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "min.w", 64,
30625 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30627 /* min.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
30629 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "min.w", 64,
30630 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30632 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
30634 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "min.w", 56,
30635 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30637 /* min.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
30639 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "min.w", 56,
30640 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30642 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
30644 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "min.w", 64,
30645 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30647 /* min.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
30649 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "min.w", 64,
30650 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30652 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
30654 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "min.w", 64,
30655 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30657 /* min.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
30659 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "min.w", 64,
30660 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30662 /* min.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
30664 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "min.w", 72,
30665 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30667 /* min.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
30669 M32C_INSN_MIN32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "min32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "min.w", 72,
30670 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30672 /* min.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
30674 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 24,
30675 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30677 /* min.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
30679 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 24,
30680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30682 /* min.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
30684 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "min.w", 24,
30685 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30687 /* min.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
30689 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 24,
30690 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30692 /* min.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
30694 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 24,
30695 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30697 /* min.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
30699 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "min.w", 24,
30700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30702 /* min.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
30704 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 24,
30705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30707 /* min.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
30709 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 24,
30710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30712 /* min.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
30714 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "min.w", 24,
30715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30717 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
30719 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "min.w", 32,
30720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30722 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
30724 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "min.w", 32,
30725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30727 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
30729 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "min.w", 32,
30730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30732 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
30734 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "min.w", 40,
30735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30737 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
30739 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "min.w", 40,
30740 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30742 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
30744 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "min.w", 40,
30745 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30747 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
30749 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "min.w", 48,
30750 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30752 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
30754 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "min.w", 48,
30755 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30757 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
30759 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "min.w", 48,
30760 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30762 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
30764 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "min.w", 32,
30765 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30767 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
30769 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "min.w", 32,
30770 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30772 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
30774 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "min.w", 32,
30775 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30777 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
30779 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "min.w", 40,
30780 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30782 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
30784 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "min.w", 40,
30785 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30787 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
30789 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "min.w", 40,
30790 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30792 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
30794 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "min.w", 32,
30795 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30797 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
30799 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "min.w", 32,
30800 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30802 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
30804 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "min.w", 32,
30805 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30807 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
30809 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "min.w", 40,
30810 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30812 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
30814 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "min.w", 40,
30815 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30817 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
30819 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "min.w", 40,
30820 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30822 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
30824 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "min.w", 40,
30825 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30827 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
30829 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "min.w", 40,
30830 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30832 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
30834 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "min.w", 40,
30835 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30837 /* min.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
30839 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "min.w", 48,
30840 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30842 /* min.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
30844 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "min.w", 48,
30845 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30847 /* min.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
30849 M32C_INSN_MIN32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "min32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "min.w", 48,
30850 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30852 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
30854 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 32,
30855 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30857 /* min.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
30859 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 32,
30860 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30862 /* min.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
30864 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 32,
30865 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30867 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
30869 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 32,
30870 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30872 /* min.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
30874 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 32,
30875 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30877 /* min.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
30879 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 32,
30880 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30882 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
30884 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 32,
30885 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30887 /* min.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
30889 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 32,
30890 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30892 /* min.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
30894 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 32,
30895 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30897 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
30899 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "min.b", 40,
30900 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30902 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
30904 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "min.b", 40,
30905 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30907 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
30909 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "min.b", 40,
30910 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30912 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
30914 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "min.b", 48,
30915 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30917 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
30919 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "min.b", 48,
30920 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30922 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
30924 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "min.b", 48,
30925 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30927 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
30929 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "min.b", 56,
30930 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30932 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
30934 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "min.b", 56,
30935 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30937 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
30939 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "min.b", 56,
30940 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30942 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
30944 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "min.b", 40,
30945 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30947 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
30949 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "min.b", 40,
30950 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30952 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
30954 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "min.b", 40,
30955 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30957 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
30959 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "min.b", 48,
30960 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30962 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
30964 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "min.b", 48,
30965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30967 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
30969 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "min.b", 48,
30970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30972 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
30974 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "min.b", 40,
30975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30977 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
30979 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "min.b", 40,
30980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30982 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
30984 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "min.b", 40,
30985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30987 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
30989 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "min.b", 48,
30990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30992 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
30994 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "min.b", 48,
30995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
30997 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
30999 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "min.b", 48,
31000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31002 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
31004 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "min.b", 48,
31005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31007 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
31009 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "min.b", 48,
31010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31012 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
31014 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "min.b", 48,
31015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31017 /* min.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
31019 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "min.b", 56,
31020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31022 /* min.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
31024 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "min.b", 56,
31025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31027 /* min.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
31029 M32C_INSN_MIN32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "min.b", 56,
31030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31032 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
31034 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 40,
31035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31037 /* min.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
31039 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 40,
31040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31042 /* min.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
31044 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 40,
31045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31047 /* min.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
31049 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 40,
31050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31052 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
31054 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 40,
31055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31057 /* min.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
31059 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 40,
31060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31062 /* min.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
31064 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 40,
31065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31067 /* min.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
31069 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 40,
31070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31072 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
31074 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 40,
31075 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31077 /* min.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
31079 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 40,
31080 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31082 /* min.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
31084 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 40,
31085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31087 /* min.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
31089 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 40,
31090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31092 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
31094 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "min.b", 48,
31095 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31097 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
31099 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "min.b", 48,
31100 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31102 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
31104 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "min.b", 48,
31105 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31107 /* min.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
31109 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "min.b", 48,
31110 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31112 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
31114 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "min.b", 56,
31115 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31117 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
31119 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "min.b", 56,
31120 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31122 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
31124 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "min.b", 56,
31125 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31127 /* min.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
31129 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "min.b", 56,
31130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31132 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
31134 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "min.b", 64,
31135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31137 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
31139 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "min.b", 64,
31140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31142 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
31144 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "min.b", 64,
31145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31147 /* min.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
31149 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "min.b", 64,
31150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31152 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
31154 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "min.b", 48,
31155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31157 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
31159 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "min.b", 48,
31160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31162 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
31164 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "min.b", 48,
31165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31167 /* min.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
31169 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "min.b", 48,
31170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31172 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
31174 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "min.b", 56,
31175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31177 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
31179 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "min.b", 56,
31180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31182 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
31184 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "min.b", 56,
31185 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31187 /* min.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
31189 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "min.b", 56,
31190 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31192 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
31194 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "min.b", 48,
31195 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31197 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
31199 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "min.b", 48,
31200 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31202 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
31204 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "min.b", 48,
31205 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31207 /* min.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
31209 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "min.b", 48,
31210 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31212 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
31214 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "min.b", 56,
31215 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31217 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
31219 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "min.b", 56,
31220 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31222 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
31224 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "min.b", 56,
31225 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31227 /* min.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
31229 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "min.b", 56,
31230 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31232 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
31234 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "min.b", 56,
31235 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31237 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
31239 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "min.b", 56,
31240 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31242 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
31244 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "min.b", 56,
31245 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31247 /* min.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
31249 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "min.b", 56,
31250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31252 /* min.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
31254 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "min.b", 64,
31255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31257 /* min.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
31259 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "min.b", 64,
31260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31262 /* min.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
31264 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "min.b", 64,
31265 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31267 /* min.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
31269 M32C_INSN_MIN32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "min.b", 64,
31270 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31272 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
31274 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 48,
31275 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31277 /* min.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
31279 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 48,
31280 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31282 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
31284 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 48,
31285 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31287 /* min.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
31289 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 48,
31290 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31292 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
31294 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 48,
31295 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31297 /* min.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
31299 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 48,
31300 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31302 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
31304 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "min.b", 56,
31305 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31307 /* min.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
31309 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "min.b", 56,
31310 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31312 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
31314 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "min.b", 64,
31315 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31317 /* min.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
31319 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "min.b", 64,
31320 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31322 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
31324 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "min.b", 72,
31325 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31327 /* min.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
31329 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "min.b", 72,
31330 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31332 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
31334 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "min.b", 56,
31335 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31337 /* min.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
31339 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "min.b", 56,
31340 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31342 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
31344 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "min.b", 64,
31345 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31347 /* min.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
31349 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "min.b", 64,
31350 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31352 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
31354 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "min.b", 56,
31355 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31357 /* min.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
31359 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "min.b", 56,
31360 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31362 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
31364 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "min.b", 64,
31365 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31367 /* min.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
31369 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "min.b", 64,
31370 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31372 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
31374 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "min.b", 64,
31375 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31377 /* min.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
31379 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "min.b", 64,
31380 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31382 /* min.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
31384 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "min.b", 72,
31385 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31387 /* min.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
31389 M32C_INSN_MIN32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "min32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "min.b", 72,
31390 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31392 /* min.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
31394 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 24,
31395 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31397 /* min.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
31399 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 24,
31400 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31402 /* min.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
31404 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "min.b", 24,
31405 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31407 /* min.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
31409 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 24,
31410 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31412 /* min.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
31414 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 24,
31415 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31417 /* min.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
31419 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "min.b", 24,
31420 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31422 /* min.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
31424 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 24,
31425 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31427 /* min.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
31429 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 24,
31430 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31432 /* min.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
31434 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "min.b", 24,
31435 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31437 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
31439 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "min.b", 32,
31440 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31442 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
31444 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "min.b", 32,
31445 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31447 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
31449 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "min.b", 32,
31450 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31452 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
31454 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "min.b", 40,
31455 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31457 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
31459 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "min.b", 40,
31460 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31462 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
31464 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "min.b", 40,
31465 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31467 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
31469 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "min.b", 48,
31470 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31472 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
31474 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "min.b", 48,
31475 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31477 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
31479 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "min.b", 48,
31480 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31482 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
31484 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "min.b", 32,
31485 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31487 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
31489 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "min.b", 32,
31490 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31492 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
31494 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "min.b", 32,
31495 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31497 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
31499 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "min.b", 40,
31500 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31502 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
31504 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "min.b", 40,
31505 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31507 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
31509 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "min.b", 40,
31510 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31512 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
31514 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "min.b", 32,
31515 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31517 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
31519 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "min.b", 32,
31520 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31522 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
31524 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "min.b", 32,
31525 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31527 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
31529 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "min.b", 40,
31530 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31532 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
31534 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "min.b", 40,
31535 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31537 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
31539 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "min.b", 40,
31540 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31542 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
31544 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "min.b", 40,
31545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31547 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
31549 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "min.b", 40,
31550 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31552 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
31554 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "min.b", 40,
31555 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31557 /* min.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
31559 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "min.b", 48,
31560 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31562 /* min.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
31564 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "min.b", 48,
31565 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31567 /* min.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
31569 M32C_INSN_MIN32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "min32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "min.b", 48,
31570 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31572 /* min.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
31574 M32C_INSN_MIN32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "min32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "min.w", 40,
31575 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31577 /* min.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
31579 M32C_INSN_MIN32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "min32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "min.w", 40,
31580 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31582 /* min.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
31584 M32C_INSN_MIN32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "min32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "min.w", 40,
31585 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31587 /* min.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
31589 M32C_INSN_MIN32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "min.w", 48,
31590 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31592 /* min.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
31594 M32C_INSN_MIN32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "min.w", 48,
31595 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31597 /* min.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
31599 M32C_INSN_MIN32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "min.w", 48,
31600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31602 /* min.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
31604 M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "min.w", 56,
31605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31607 /* min.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
31609 M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "min.w", 56,
31610 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31612 /* min.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
31614 M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "min.w", 56,
31615 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31617 /* min.w${X} #${Imm-40-HI},${Dsp-24-u16} */
31619 M32C_INSN_MIN32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "min32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "min.w", 56,
31620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31622 /* min.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
31624 M32C_INSN_MIN32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "min32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "min.w", 64,
31625 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31627 /* min.w${X} #${Imm-48-HI},${Dsp-24-u24} */
31629 M32C_INSN_MIN32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "min32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "min.w", 64,
31630 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31632 /* min.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
31634 M32C_INSN_MIN32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "min32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "min.b", 32,
31635 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31637 /* min.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
31639 M32C_INSN_MIN32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "min32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "min.b", 32,
31640 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31642 /* min.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
31644 M32C_INSN_MIN32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "min32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "min.b", 32,
31645 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31647 /* min.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
31649 M32C_INSN_MIN32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "min.b", 40,
31650 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31652 /* min.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
31654 M32C_INSN_MIN32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "min.b", 40,
31655 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31657 /* min.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
31659 M32C_INSN_MIN32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "min.b", 40,
31660 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31662 /* min.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
31664 M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "min.b", 48,
31665 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31667 /* min.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
31669 M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "min.b", 48,
31670 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31672 /* min.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
31674 M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "min.b", 48,
31675 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31677 /* min.b${X} #${Imm-40-QI},${Dsp-24-u16} */
31679 M32C_INSN_MIN32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "min32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "min.b", 48,
31680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31682 /* min.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
31684 M32C_INSN_MIN32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "min32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "min.b", 56,
31685 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31687 /* min.b${X} #${Imm-48-QI},${Dsp-24-u24} */
31689 M32C_INSN_MIN32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "min32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "min.b", 56,
31690 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31692 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
31694 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 32,
31695 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31697 /* max.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
31699 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 32,
31700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31702 /* max.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
31704 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 32,
31705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31707 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
31709 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 32,
31710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31712 /* max.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
31714 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 32,
31715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31717 /* max.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
31719 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 32,
31720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31722 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
31724 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 32,
31725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31727 /* max.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
31729 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 32,
31730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31732 /* max.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
31734 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 32,
31735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31737 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
31739 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "max.w", 40,
31740 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31742 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
31744 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "max.w", 40,
31745 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31747 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
31749 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "max.w", 40,
31750 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31752 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
31754 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "max.w", 48,
31755 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31757 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
31759 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "max.w", 48,
31760 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31762 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
31764 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "max.w", 48,
31765 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31767 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
31769 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "max.w", 56,
31770 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31772 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
31774 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "max.w", 56,
31775 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31777 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
31779 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "max.w", 56,
31780 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31782 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
31784 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "max.w", 40,
31785 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31787 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
31789 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "max.w", 40,
31790 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31792 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
31794 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "max.w", 40,
31795 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31797 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
31799 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "max.w", 48,
31800 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31802 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
31804 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "max.w", 48,
31805 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31807 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
31809 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "max.w", 48,
31810 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31812 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
31814 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "max.w", 40,
31815 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31817 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
31819 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "max.w", 40,
31820 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31822 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
31824 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "max.w", 40,
31825 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31827 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
31829 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "max.w", 48,
31830 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31832 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
31834 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "max.w", 48,
31835 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31837 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
31839 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "max.w", 48,
31840 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31842 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
31844 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "max.w", 48,
31845 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31847 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
31849 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "max.w", 48,
31850 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31852 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
31854 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "max.w", 48,
31855 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31857 /* max.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
31859 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "max.w", 56,
31860 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31862 /* max.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
31864 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "max.w", 56,
31865 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31867 /* max.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
31869 M32C_INSN_MAX32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "max.w", 56,
31870 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31872 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
31874 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 40,
31875 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31877 /* max.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
31879 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 40,
31880 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31882 /* max.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
31884 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 40,
31885 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31887 /* max.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
31889 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 40,
31890 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31892 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
31894 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 40,
31895 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31897 /* max.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
31899 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 40,
31900 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31902 /* max.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
31904 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 40,
31905 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31907 /* max.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
31909 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 40,
31910 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31912 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
31914 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 40,
31915 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31917 /* max.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
31919 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 40,
31920 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31922 /* max.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
31924 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 40,
31925 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31927 /* max.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
31929 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 40,
31930 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31932 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
31934 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "max.w", 48,
31935 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31937 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
31939 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "max.w", 48,
31940 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31942 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
31944 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "max.w", 48,
31945 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31947 /* max.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
31949 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "max.w", 48,
31950 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31952 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
31954 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "max.w", 56,
31955 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31957 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
31959 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "max.w", 56,
31960 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31962 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
31964 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "max.w", 56,
31965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31967 /* max.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
31969 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "max.w", 56,
31970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31972 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
31974 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "max.w", 64,
31975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31977 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
31979 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "max.w", 64,
31980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31982 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
31984 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "max.w", 64,
31985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31987 /* max.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
31989 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "max.w", 64,
31990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31992 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
31994 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "max.w", 48,
31995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
31997 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
31999 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "max.w", 48,
32000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32002 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
32004 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "max.w", 48,
32005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32007 /* max.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
32009 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "max.w", 48,
32010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32012 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
32014 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "max.w", 56,
32015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32017 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
32019 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "max.w", 56,
32020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32022 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
32024 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "max.w", 56,
32025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32027 /* max.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
32029 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "max.w", 56,
32030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32032 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
32034 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "max.w", 48,
32035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32037 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
32039 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "max.w", 48,
32040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32042 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
32044 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "max.w", 48,
32045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32047 /* max.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
32049 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "max.w", 48,
32050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32052 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
32054 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "max.w", 56,
32055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32057 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
32059 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "max.w", 56,
32060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32062 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
32064 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "max.w", 56,
32065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32067 /* max.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
32069 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "max.w", 56,
32070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32072 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
32074 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "max.w", 56,
32075 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32077 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
32079 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "max.w", 56,
32080 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32082 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
32084 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "max.w", 56,
32085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32087 /* max.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
32089 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "max.w", 56,
32090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32092 /* max.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
32094 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "max.w", 64,
32095 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32097 /* max.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
32099 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "max.w", 64,
32100 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32102 /* max.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
32104 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "max.w", 64,
32105 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32107 /* max.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
32109 M32C_INSN_MAX32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "max.w", 64,
32110 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32112 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
32114 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 48,
32115 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32117 /* max.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
32119 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 48,
32120 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32122 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
32124 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 48,
32125 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32127 /* max.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
32129 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 48,
32130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32132 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
32134 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 48,
32135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32137 /* max.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
32139 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 48,
32140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32142 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
32144 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "max.w", 56,
32145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32147 /* max.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
32149 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "max.w", 56,
32150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32152 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
32154 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "max.w", 64,
32155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32157 /* max.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
32159 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "max.w", 64,
32160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32162 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
32164 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "max.w", 72,
32165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32167 /* max.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
32169 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "max.w", 72,
32170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32172 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
32174 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "max.w", 56,
32175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32177 /* max.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
32179 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "max.w", 56,
32180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32182 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
32184 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "max.w", 64,
32185 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32187 /* max.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
32189 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "max.w", 64,
32190 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32192 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
32194 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "max.w", 56,
32195 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32197 /* max.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
32199 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "max.w", 56,
32200 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32202 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
32204 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "max.w", 64,
32205 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32207 /* max.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
32209 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "max.w", 64,
32210 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32212 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
32214 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "max.w", 64,
32215 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32217 /* max.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
32219 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "max.w", 64,
32220 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32222 /* max.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
32224 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "max.w", 72,
32225 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32227 /* max.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
32229 M32C_INSN_MAX32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "max32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "max.w", 72,
32230 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32232 /* max.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
32234 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 24,
32235 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32237 /* max.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
32239 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 24,
32240 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32242 /* max.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
32244 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "max.w", 24,
32245 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32247 /* max.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
32249 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 24,
32250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32252 /* max.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
32254 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 24,
32255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32257 /* max.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
32259 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "max.w", 24,
32260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32262 /* max.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
32264 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 24,
32265 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32267 /* max.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
32269 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 24,
32270 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32272 /* max.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
32274 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "max.w", 24,
32275 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32277 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
32279 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "max.w", 32,
32280 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32282 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
32284 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "max.w", 32,
32285 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32287 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
32289 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "max.w", 32,
32290 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32292 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
32294 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "max.w", 40,
32295 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32297 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
32299 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "max.w", 40,
32300 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32302 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
32304 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "max.w", 40,
32305 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32307 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
32309 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "max.w", 48,
32310 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32312 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
32314 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "max.w", 48,
32315 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32317 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
32319 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "max.w", 48,
32320 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32322 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
32324 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "max.w", 32,
32325 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32327 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
32329 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "max.w", 32,
32330 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32332 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
32334 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "max.w", 32,
32335 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32337 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
32339 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "max.w", 40,
32340 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32342 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
32344 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "max.w", 40,
32345 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32347 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
32349 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "max.w", 40,
32350 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32352 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
32354 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "max.w", 32,
32355 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32357 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
32359 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "max.w", 32,
32360 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32362 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
32364 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "max.w", 32,
32365 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32367 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
32369 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "max.w", 40,
32370 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32372 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
32374 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "max.w", 40,
32375 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32377 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
32379 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "max.w", 40,
32380 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32382 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
32384 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "max.w", 40,
32385 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32387 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
32389 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "max.w", 40,
32390 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32392 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
32394 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "max.w", 40,
32395 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32397 /* max.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
32399 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "max.w", 48,
32400 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32402 /* max.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
32404 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "max.w", 48,
32405 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32407 /* max.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
32409 M32C_INSN_MAX32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "max32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "max.w", 48,
32410 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32412 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
32414 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 32,
32415 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32417 /* max.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
32419 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 32,
32420 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32422 /* max.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
32424 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 32,
32425 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32427 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
32429 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 32,
32430 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32432 /* max.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
32434 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 32,
32435 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32437 /* max.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
32439 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 32,
32440 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32442 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
32444 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 32,
32445 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32447 /* max.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
32449 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 32,
32450 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32452 /* max.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
32454 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 32,
32455 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32457 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
32459 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "max.b", 40,
32460 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32462 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
32464 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "max.b", 40,
32465 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32467 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
32469 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "max.b", 40,
32470 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32472 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
32474 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "max.b", 48,
32475 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32477 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
32479 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "max.b", 48,
32480 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32482 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
32484 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "max.b", 48,
32485 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32487 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
32489 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "max.b", 56,
32490 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32492 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
32494 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "max.b", 56,
32495 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32497 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
32499 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "max.b", 56,
32500 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32502 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
32504 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "max.b", 40,
32505 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32507 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
32509 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "max.b", 40,
32510 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32512 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
32514 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "max.b", 40,
32515 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32517 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
32519 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "max.b", 48,
32520 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32522 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
32524 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "max.b", 48,
32525 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32527 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
32529 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "max.b", 48,
32530 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32532 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
32534 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "max.b", 40,
32535 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32537 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
32539 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "max.b", 40,
32540 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32542 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
32544 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "max.b", 40,
32545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32547 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
32549 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "max.b", 48,
32550 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32552 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
32554 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "max.b", 48,
32555 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32557 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
32559 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "max.b", 48,
32560 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32562 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
32564 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "max.b", 48,
32565 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32567 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
32569 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "max.b", 48,
32570 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32572 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
32574 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "max.b", 48,
32575 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32577 /* max.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
32579 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "max.b", 56,
32580 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32582 /* max.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
32584 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "max.b", 56,
32585 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32587 /* max.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
32589 M32C_INSN_MAX32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "max.b", 56,
32590 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32592 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
32594 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 40,
32595 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32597 /* max.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
32599 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 40,
32600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32602 /* max.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
32604 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 40,
32605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32607 /* max.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
32609 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 40,
32610 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32612 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
32614 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 40,
32615 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32617 /* max.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
32619 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 40,
32620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32622 /* max.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
32624 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 40,
32625 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32627 /* max.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
32629 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 40,
32630 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32632 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
32634 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 40,
32635 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32637 /* max.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
32639 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 40,
32640 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32642 /* max.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
32644 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 40,
32645 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32647 /* max.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
32649 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 40,
32650 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32652 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
32654 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "max.b", 48,
32655 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32657 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
32659 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "max.b", 48,
32660 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32662 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
32664 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "max.b", 48,
32665 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32667 /* max.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
32669 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "max.b", 48,
32670 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32672 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
32674 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "max.b", 56,
32675 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32677 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
32679 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "max.b", 56,
32680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32682 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
32684 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "max.b", 56,
32685 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32687 /* max.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
32689 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "max.b", 56,
32690 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32692 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
32694 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "max.b", 64,
32695 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32697 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
32699 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "max.b", 64,
32700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32702 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
32704 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "max.b", 64,
32705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32707 /* max.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
32709 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "max.b", 64,
32710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32712 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
32714 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "max.b", 48,
32715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32717 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
32719 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "max.b", 48,
32720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32722 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
32724 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "max.b", 48,
32725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32727 /* max.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
32729 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "max.b", 48,
32730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32732 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
32734 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "max.b", 56,
32735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32737 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
32739 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "max.b", 56,
32740 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32742 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
32744 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "max.b", 56,
32745 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32747 /* max.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
32749 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "max.b", 56,
32750 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32752 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
32754 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "max.b", 48,
32755 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32757 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
32759 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "max.b", 48,
32760 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32762 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
32764 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "max.b", 48,
32765 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32767 /* max.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
32769 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "max.b", 48,
32770 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32772 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
32774 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "max.b", 56,
32775 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32777 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
32779 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "max.b", 56,
32780 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32782 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
32784 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "max.b", 56,
32785 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32787 /* max.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
32789 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "max.b", 56,
32790 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32792 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
32794 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "max.b", 56,
32795 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32797 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
32799 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "max.b", 56,
32800 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32802 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
32804 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "max.b", 56,
32805 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32807 /* max.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
32809 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "max.b", 56,
32810 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32812 /* max.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
32814 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "max.b", 64,
32815 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32817 /* max.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
32819 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "max.b", 64,
32820 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32822 /* max.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
32824 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "max.b", 64,
32825 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32827 /* max.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
32829 M32C_INSN_MAX32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "max.b", 64,
32830 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32832 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
32834 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 48,
32835 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32837 /* max.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
32839 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 48,
32840 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32842 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
32844 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 48,
32845 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32847 /* max.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
32849 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 48,
32850 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32852 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
32854 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 48,
32855 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32857 /* max.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
32859 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 48,
32860 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32862 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
32864 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "max.b", 56,
32865 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32867 /* max.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
32869 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "max.b", 56,
32870 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32872 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
32874 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "max.b", 64,
32875 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32877 /* max.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
32879 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "max.b", 64,
32880 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32882 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
32884 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "max.b", 72,
32885 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32887 /* max.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
32889 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "max.b", 72,
32890 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32892 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
32894 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "max.b", 56,
32895 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32897 /* max.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
32899 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "max.b", 56,
32900 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32902 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
32904 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "max.b", 64,
32905 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32907 /* max.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
32909 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "max.b", 64,
32910 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32912 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
32914 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "max.b", 56,
32915 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32917 /* max.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
32919 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "max.b", 56,
32920 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32922 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
32924 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "max.b", 64,
32925 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32927 /* max.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
32929 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "max.b", 64,
32930 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32932 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
32934 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "max.b", 64,
32935 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32937 /* max.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
32939 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "max.b", 64,
32940 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32942 /* max.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
32944 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "max.b", 72,
32945 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32947 /* max.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
32949 M32C_INSN_MAX32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "max32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "max.b", 72,
32950 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32952 /* max.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
32954 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 24,
32955 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32957 /* max.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
32959 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 24,
32960 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32962 /* max.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
32964 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "max.b", 24,
32965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32967 /* max.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
32969 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 24,
32970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32972 /* max.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
32974 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 24,
32975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32977 /* max.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
32979 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "max.b", 24,
32980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32982 /* max.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
32984 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 24,
32985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32987 /* max.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
32989 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 24,
32990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32992 /* max.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
32994 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "max.b", 24,
32995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
32997 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
32999 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "max.b", 32,
33000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33002 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
33004 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "max.b", 32,
33005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33007 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
33009 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "max.b", 32,
33010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33012 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
33014 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "max.b", 40,
33015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33017 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
33019 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "max.b", 40,
33020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33022 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
33024 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "max.b", 40,
33025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33027 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
33029 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "max.b", 48,
33030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33032 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
33034 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "max.b", 48,
33035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33037 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
33039 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "max.b", 48,
33040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33042 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
33044 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "max.b", 32,
33045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33047 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
33049 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "max.b", 32,
33050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33052 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
33054 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "max.b", 32,
33055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33057 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
33059 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "max.b", 40,
33060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33062 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
33064 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "max.b", 40,
33065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33067 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
33069 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "max.b", 40,
33070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33072 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
33074 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "max.b", 32,
33075 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33077 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
33079 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "max.b", 32,
33080 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33082 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
33084 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "max.b", 32,
33085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33087 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
33089 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "max.b", 40,
33090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33092 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
33094 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "max.b", 40,
33095 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33097 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
33099 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "max.b", 40,
33100 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33102 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
33104 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "max.b", 40,
33105 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33107 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
33109 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "max.b", 40,
33110 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33112 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
33114 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "max.b", 40,
33115 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33117 /* max.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
33119 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "max.b", 48,
33120 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33122 /* max.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
33124 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "max.b", 48,
33125 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33127 /* max.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
33129 M32C_INSN_MAX32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "max32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "max.b", 48,
33130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33132 /* max.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
33134 M32C_INSN_MAX32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "max32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "max.w", 40,
33135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33137 /* max.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
33139 M32C_INSN_MAX32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "max32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "max.w", 40,
33140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33142 /* max.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
33144 M32C_INSN_MAX32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "max32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "max.w", 40,
33145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33147 /* max.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
33149 M32C_INSN_MAX32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "max.w", 48,
33150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33152 /* max.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
33154 M32C_INSN_MAX32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "max.w", 48,
33155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33157 /* max.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
33159 M32C_INSN_MAX32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "max.w", 48,
33160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33162 /* max.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
33164 M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "max.w", 56,
33165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33167 /* max.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
33169 M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "max.w", 56,
33170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33172 /* max.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
33174 M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "max.w", 56,
33175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33177 /* max.w${X} #${Imm-40-HI},${Dsp-24-u16} */
33179 M32C_INSN_MAX32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "max32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "max.w", 56,
33180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33182 /* max.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
33184 M32C_INSN_MAX32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "max32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "max.w", 64,
33185 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33187 /* max.w${X} #${Imm-48-HI},${Dsp-24-u24} */
33189 M32C_INSN_MAX32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "max32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "max.w", 64,
33190 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33192 /* max.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
33194 M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "max32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "max.b", 32,
33195 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33197 /* max.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
33199 M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "max32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "max.b", 32,
33200 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33202 /* max.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
33204 M32C_INSN_MAX32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "max32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "max.b", 32,
33205 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33207 /* max.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
33209 M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "max.b", 40,
33210 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33212 /* max.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
33214 M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "max.b", 40,
33215 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33217 /* max.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
33219 M32C_INSN_MAX32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "max.b", 40,
33220 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33222 /* max.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
33224 M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "max.b", 48,
33225 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33227 /* max.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
33229 M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "max.b", 48,
33230 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33232 /* max.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
33234 M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "max.b", 48,
33235 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33237 /* max.b${X} #${Imm-40-QI},${Dsp-24-u16} */
33239 M32C_INSN_MAX32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "max32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "max.b", 48,
33240 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33242 /* max.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
33244 M32C_INSN_MAX32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "max32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "max.b", 56,
33245 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33247 /* max.b${X} #${Imm-48-QI},${Dsp-24-u24} */
33249 M32C_INSN_MAX32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "max32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "max.b", 56,
33250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33252 /* ste.w ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20} */
33254 M32C_INSN_STE16_W_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_HI, "ste16.w-dst-dspsp-16-8-dst16-16-8-An-relative-HI", "ste.w", 48,
33255 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33257 /* ste.w ${Dsp-16-u8}[sb],${Dsp-24-u20} */
33259 M32C_INSN_STE16_W_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_HI, "ste16.w-dst-dspsp-16-8-dst16-16-8-SB-relative-HI", "ste.w", 48,
33260 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33262 /* ste.w ${Dsp-16-s8}[fb],${Dsp-24-u20} */
33264 M32C_INSN_STE16_W_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_HI, "ste16.w-dst-dspsp-16-8-dst16-16-8-FB-relative-HI", "ste.w", 48,
33265 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33267 /* ste.w ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20} */
33269 M32C_INSN_STE16_W_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_HI, "ste16.w-dst-dspsp-16-16-dst16-16-16-An-relative-HI", "ste.w", 56,
33270 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33272 /* ste.w ${Dsp-16-u16}[sb],${Dsp-32-u20} */
33274 M32C_INSN_STE16_W_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_HI, "ste16.w-dst-dspsp-16-16-dst16-16-16-SB-relative-HI", "ste.w", 56,
33275 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33277 /* ste.w ${Dsp-16-u16},${Dsp-32-u20} */
33279 M32C_INSN_STE16_W_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_HI, "ste16.w-dst-dspsp-16-16-dst16-16-16-absolute-HI", "ste.w", 56,
33280 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33282 /* ste.w $Dst16RnHI,${Dsp-16-u20} */
33284 M32C_INSN_STE16_W_DST_DSPSP_BASIC_DST16_RN_DIRECT_HI, "ste16.w-dst-dspsp-basic-dst16-Rn-direct-HI", "ste.w", 40,
33285 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33287 /* ste.w $Dst16AnHI,${Dsp-16-u20} */
33289 M32C_INSN_STE16_W_DST_DSPSP_BASIC_DST16_AN_DIRECT_HI, "ste16.w-dst-dspsp-basic-dst16-An-direct-HI", "ste.w", 40,
33290 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33292 /* ste.w [$Dst16An],${Dsp-16-u20} */
33294 M32C_INSN_STE16_W_DST_DSPSP_BASIC_DST16_AN_INDIRECT_HI, "ste16.w-dst-dspsp-basic-dst16-An-indirect-HI", "ste.w", 40,
33295 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33297 /* ste.b ${Dsp-16-u8}[$Dst16An],${Dsp-24-u20} */
33299 M32C_INSN_STE16_B_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_QI, "ste16.b-dst-dspsp-16-8-dst16-16-8-An-relative-QI", "ste.b", 48,
33300 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33302 /* ste.b ${Dsp-16-u8}[sb],${Dsp-24-u20} */
33304 M32C_INSN_STE16_B_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_QI, "ste16.b-dst-dspsp-16-8-dst16-16-8-SB-relative-QI", "ste.b", 48,
33305 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33307 /* ste.b ${Dsp-16-s8}[fb],${Dsp-24-u20} */
33309 M32C_INSN_STE16_B_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_QI, "ste16.b-dst-dspsp-16-8-dst16-16-8-FB-relative-QI", "ste.b", 48,
33310 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33312 /* ste.b ${Dsp-16-u16}[$Dst16An],${Dsp-32-u20} */
33314 M32C_INSN_STE16_B_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_QI, "ste16.b-dst-dspsp-16-16-dst16-16-16-An-relative-QI", "ste.b", 56,
33315 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33317 /* ste.b ${Dsp-16-u16}[sb],${Dsp-32-u20} */
33319 M32C_INSN_STE16_B_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_QI, "ste16.b-dst-dspsp-16-16-dst16-16-16-SB-relative-QI", "ste.b", 56,
33320 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33322 /* ste.b ${Dsp-16-u16},${Dsp-32-u20} */
33324 M32C_INSN_STE16_B_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_QI, "ste16.b-dst-dspsp-16-16-dst16-16-16-absolute-QI", "ste.b", 56,
33325 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33327 /* ste.b $Dst16RnQI,${Dsp-16-u20} */
33329 M32C_INSN_STE16_B_DST_DSPSP_BASIC_DST16_RN_DIRECT_QI, "ste16.b-dst-dspsp-basic-dst16-Rn-direct-QI", "ste.b", 40,
33330 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33332 /* ste.b $Dst16AnQI,${Dsp-16-u20} */
33334 M32C_INSN_STE16_B_DST_DSPSP_BASIC_DST16_AN_DIRECT_QI, "ste16.b-dst-dspsp-basic-dst16-An-direct-QI", "ste.b", 40,
33335 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33337 /* ste.b [$Dst16An],${Dsp-16-u20} */
33339 M32C_INSN_STE16_B_DST_DSPSP_BASIC_DST16_AN_INDIRECT_QI, "ste16.b-dst-dspsp-basic-dst16-An-indirect-QI", "ste.b", 40,
33340 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33342 /* lde.w ${Dsp-24-u20},${Dsp-16-u8}[$Dst16An] */
33344 M32C_INSN_LDE16_W_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_HI, "lde16.w-dst-dspsp-16-8-dst16-16-8-An-relative-HI", "lde.w", 48,
33345 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33347 /* lde.w ${Dsp-24-u20},${Dsp-16-u8}[sb] */
33349 M32C_INSN_LDE16_W_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_HI, "lde16.w-dst-dspsp-16-8-dst16-16-8-SB-relative-HI", "lde.w", 48,
33350 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33352 /* lde.w ${Dsp-24-u20},${Dsp-16-s8}[fb] */
33354 M32C_INSN_LDE16_W_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_HI, "lde16.w-dst-dspsp-16-8-dst16-16-8-FB-relative-HI", "lde.w", 48,
33355 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33357 /* lde.w ${Dsp-32-u20},${Dsp-16-u16}[$Dst16An] */
33359 M32C_INSN_LDE16_W_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_HI, "lde16.w-dst-dspsp-16-16-dst16-16-16-An-relative-HI", "lde.w", 56,
33360 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33362 /* lde.w ${Dsp-32-u20},${Dsp-16-u16}[sb] */
33364 M32C_INSN_LDE16_W_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_HI, "lde16.w-dst-dspsp-16-16-dst16-16-16-SB-relative-HI", "lde.w", 56,
33365 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33367 /* lde.w ${Dsp-32-u20},${Dsp-16-u16} */
33369 M32C_INSN_LDE16_W_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_HI, "lde16.w-dst-dspsp-16-16-dst16-16-16-absolute-HI", "lde.w", 56,
33370 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33372 /* lde.w ${Dsp-16-u20},$Dst16RnHI */
33374 M32C_INSN_LDE16_W_DST_DSPSP_BASIC_DST16_RN_DIRECT_HI, "lde16.w-dst-dspsp-basic-dst16-Rn-direct-HI", "lde.w", 40,
33375 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33377 /* lde.w ${Dsp-16-u20},$Dst16AnHI */
33379 M32C_INSN_LDE16_W_DST_DSPSP_BASIC_DST16_AN_DIRECT_HI, "lde16.w-dst-dspsp-basic-dst16-An-direct-HI", "lde.w", 40,
33380 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33382 /* lde.w ${Dsp-16-u20},[$Dst16An] */
33384 M32C_INSN_LDE16_W_DST_DSPSP_BASIC_DST16_AN_INDIRECT_HI, "lde16.w-dst-dspsp-basic-dst16-An-indirect-HI", "lde.w", 40,
33385 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33387 /* lde.b ${Dsp-24-u20},${Dsp-16-u8}[$Dst16An] */
33389 M32C_INSN_LDE16_B_DST_DSPSP_16_8_DST16_16_8_AN_RELATIVE_QI, "lde16.b-dst-dspsp-16-8-dst16-16-8-An-relative-QI", "lde.b", 48,
33390 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33392 /* lde.b ${Dsp-24-u20},${Dsp-16-u8}[sb] */
33394 M32C_INSN_LDE16_B_DST_DSPSP_16_8_DST16_16_8_SB_RELATIVE_QI, "lde16.b-dst-dspsp-16-8-dst16-16-8-SB-relative-QI", "lde.b", 48,
33395 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33397 /* lde.b ${Dsp-24-u20},${Dsp-16-s8}[fb] */
33399 M32C_INSN_LDE16_B_DST_DSPSP_16_8_DST16_16_8_FB_RELATIVE_QI, "lde16.b-dst-dspsp-16-8-dst16-16-8-FB-relative-QI", "lde.b", 48,
33400 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33402 /* lde.b ${Dsp-32-u20},${Dsp-16-u16}[$Dst16An] */
33404 M32C_INSN_LDE16_B_DST_DSPSP_16_16_DST16_16_16_AN_RELATIVE_QI, "lde16.b-dst-dspsp-16-16-dst16-16-16-An-relative-QI", "lde.b", 56,
33405 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33407 /* lde.b ${Dsp-32-u20},${Dsp-16-u16}[sb] */
33409 M32C_INSN_LDE16_B_DST_DSPSP_16_16_DST16_16_16_SB_RELATIVE_QI, "lde16.b-dst-dspsp-16-16-dst16-16-16-SB-relative-QI", "lde.b", 56,
33410 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33412 /* lde.b ${Dsp-32-u20},${Dsp-16-u16} */
33414 M32C_INSN_LDE16_B_DST_DSPSP_16_16_DST16_16_16_ABSOLUTE_QI, "lde16.b-dst-dspsp-16-16-dst16-16-16-absolute-QI", "lde.b", 56,
33415 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33417 /* lde.b ${Dsp-16-u20},$Dst16RnQI */
33419 M32C_INSN_LDE16_B_DST_DSPSP_BASIC_DST16_RN_DIRECT_QI, "lde16.b-dst-dspsp-basic-dst16-Rn-direct-QI", "lde.b", 40,
33420 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33422 /* lde.b ${Dsp-16-u20},$Dst16AnQI */
33424 M32C_INSN_LDE16_B_DST_DSPSP_BASIC_DST16_AN_DIRECT_QI, "lde16.b-dst-dspsp-basic-dst16-An-direct-QI", "lde.b", 40,
33425 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33427 /* lde.b ${Dsp-16-u20},[$Dst16An] */
33429 M32C_INSN_LDE16_B_DST_DSPSP_BASIC_DST16_AN_INDIRECT_QI, "lde16.b-dst-dspsp-basic-dst16-An-indirect-QI", "lde.b", 40,
33430 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33432 /* stc ${cr3-Prefixed-32},$Dst32RnPrefixedSI */
33434 M32C_INSN_STC32_SRC_CR3_DST32_RN_DIRECT_PREFIXED_SI, "stc32.src-cr3-dst32-Rn-direct-Prefixed-SI", "stc", 24,
33435 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33437 /* stc ${cr3-Prefixed-32},$Dst32AnPrefixedSI */
33439 M32C_INSN_STC32_SRC_CR3_DST32_AN_DIRECT_PREFIXED_SI, "stc32.src-cr3-dst32-An-direct-Prefixed-SI", "stc", 24,
33440 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33442 /* stc ${cr3-Prefixed-32},[$Dst32AnPrefixed] */
33444 M32C_INSN_STC32_SRC_CR3_DST32_AN_INDIRECT_PREFIXED_SI, "stc32.src-cr3-dst32-An-indirect-Prefixed-SI", "stc", 24,
33445 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33447 /* stc ${cr3-Prefixed-32},${Dsp-24-u8}[$Dst32AnPrefixed] */
33449 M32C_INSN_STC32_SRC_CR3_DST32_24_8_AN_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-8-An-relative-Prefixed-SI", "stc", 32,
33450 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33452 /* stc ${cr3-Prefixed-32},${Dsp-24-u16}[$Dst32AnPrefixed] */
33454 M32C_INSN_STC32_SRC_CR3_DST32_24_16_AN_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-16-An-relative-Prefixed-SI", "stc", 40,
33455 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33457 /* stc ${cr3-Prefixed-32},${Dsp-24-u24}[$Dst32AnPrefixed] */
33459 M32C_INSN_STC32_SRC_CR3_DST32_24_24_AN_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-24-An-relative-Prefixed-SI", "stc", 48,
33460 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33462 /* stc ${cr3-Prefixed-32},${Dsp-24-u8}[sb] */
33464 M32C_INSN_STC32_SRC_CR3_DST32_24_8_SB_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-8-SB-relative-Prefixed-SI", "stc", 32,
33465 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33467 /* stc ${cr3-Prefixed-32},${Dsp-24-u16}[sb] */
33469 M32C_INSN_STC32_SRC_CR3_DST32_24_16_SB_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-16-SB-relative-Prefixed-SI", "stc", 40,
33470 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33472 /* stc ${cr3-Prefixed-32},${Dsp-24-s8}[fb] */
33474 M32C_INSN_STC32_SRC_CR3_DST32_24_8_FB_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-8-FB-relative-Prefixed-SI", "stc", 32,
33475 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33477 /* stc ${cr3-Prefixed-32},${Dsp-24-s16}[fb] */
33479 M32C_INSN_STC32_SRC_CR3_DST32_24_16_FB_RELATIVE_PREFIXED_SI, "stc32.src-cr3-dst32-24-16-FB-relative-Prefixed-SI", "stc", 40,
33480 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33482 /* stc ${cr3-Prefixed-32},${Dsp-24-u16} */
33484 M32C_INSN_STC32_SRC_CR3_DST32_24_16_ABSOLUTE_PREFIXED_SI, "stc32.src-cr3-dst32-24-16-absolute-Prefixed-SI", "stc", 40,
33485 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33487 /* stc ${cr3-Prefixed-32},${Dsp-24-u24} */
33489 M32C_INSN_STC32_SRC_CR3_DST32_24_24_ABSOLUTE_PREFIXED_SI, "stc32.src-cr3-dst32-24-24-absolute-Prefixed-SI", "stc", 48,
33490 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33492 /* stc ${cr2-32},$Dst32RnUnprefixedSI */
33494 M32C_INSN_STC32_SRC_CR2_DST32_RN_DIRECT_UNPREFIXED_SI, "stc32.src-cr2-dst32-Rn-direct-Unprefixed-SI", "stc", 16,
33495 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33497 /* stc ${cr2-32},$Dst32AnUnprefixedSI */
33499 M32C_INSN_STC32_SRC_CR2_DST32_AN_DIRECT_UNPREFIXED_SI, "stc32.src-cr2-dst32-An-direct-Unprefixed-SI", "stc", 16,
33500 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33502 /* stc ${cr2-32},[$Dst32AnUnprefixed] */
33504 M32C_INSN_STC32_SRC_CR2_DST32_AN_INDIRECT_UNPREFIXED_SI, "stc32.src-cr2-dst32-An-indirect-Unprefixed-SI", "stc", 16,
33505 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33507 /* stc ${cr2-32},${Dsp-16-u8}[$Dst32AnUnprefixed] */
33509 M32C_INSN_STC32_SRC_CR2_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-8-An-relative-Unprefixed-SI", "stc", 24,
33510 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33512 /* stc ${cr2-32},${Dsp-16-u16}[$Dst32AnUnprefixed] */
33514 M32C_INSN_STC32_SRC_CR2_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-16-An-relative-Unprefixed-SI", "stc", 32,
33515 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33517 /* stc ${cr2-32},${Dsp-16-u24}[$Dst32AnUnprefixed] */
33519 M32C_INSN_STC32_SRC_CR2_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-24-An-relative-Unprefixed-SI", "stc", 40,
33520 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33522 /* stc ${cr2-32},${Dsp-16-u8}[sb] */
33524 M32C_INSN_STC32_SRC_CR2_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-8-SB-relative-Unprefixed-SI", "stc", 24,
33525 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33527 /* stc ${cr2-32},${Dsp-16-u16}[sb] */
33529 M32C_INSN_STC32_SRC_CR2_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-16-SB-relative-Unprefixed-SI", "stc", 32,
33530 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33532 /* stc ${cr2-32},${Dsp-16-s8}[fb] */
33534 M32C_INSN_STC32_SRC_CR2_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-8-FB-relative-Unprefixed-SI", "stc", 24,
33535 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33537 /* stc ${cr2-32},${Dsp-16-s16}[fb] */
33539 M32C_INSN_STC32_SRC_CR2_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-16-FB-relative-Unprefixed-SI", "stc", 32,
33540 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33542 /* stc ${cr2-32},${Dsp-16-u16} */
33544 M32C_INSN_STC32_SRC_CR2_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-16-absolute-Unprefixed-SI", "stc", 32,
33545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33547 /* stc ${cr2-32},${Dsp-16-u24} */
33549 M32C_INSN_STC32_SRC_CR2_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "stc32.src-cr2-dst32-16-24-absolute-Unprefixed-SI", "stc", 40,
33550 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33552 /* stc ${cr1-Prefixed-32},$Dst32RnPrefixedHI */
33554 M32C_INSN_STC32_SRC_CR1_DST32_RN_DIRECT_PREFIXED_HI, "stc32.src-cr1-dst32-Rn-direct-Prefixed-HI", "stc", 24,
33555 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33557 /* stc ${cr1-Prefixed-32},$Dst32AnPrefixedHI */
33559 M32C_INSN_STC32_SRC_CR1_DST32_AN_DIRECT_PREFIXED_HI, "stc32.src-cr1-dst32-An-direct-Prefixed-HI", "stc", 24,
33560 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33562 /* stc ${cr1-Prefixed-32},[$Dst32AnPrefixed] */
33564 M32C_INSN_STC32_SRC_CR1_DST32_AN_INDIRECT_PREFIXED_HI, "stc32.src-cr1-dst32-An-indirect-Prefixed-HI", "stc", 24,
33565 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33567 /* stc ${cr1-Prefixed-32},${Dsp-24-u8}[$Dst32AnPrefixed] */
33569 M32C_INSN_STC32_SRC_CR1_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-8-An-relative-Prefixed-HI", "stc", 32,
33570 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33572 /* stc ${cr1-Prefixed-32},${Dsp-24-u16}[$Dst32AnPrefixed] */
33574 M32C_INSN_STC32_SRC_CR1_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-16-An-relative-Prefixed-HI", "stc", 40,
33575 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33577 /* stc ${cr1-Prefixed-32},${Dsp-24-u24}[$Dst32AnPrefixed] */
33579 M32C_INSN_STC32_SRC_CR1_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-24-An-relative-Prefixed-HI", "stc", 48,
33580 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33582 /* stc ${cr1-Prefixed-32},${Dsp-24-u8}[sb] */
33584 M32C_INSN_STC32_SRC_CR1_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-8-SB-relative-Prefixed-HI", "stc", 32,
33585 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33587 /* stc ${cr1-Prefixed-32},${Dsp-24-u16}[sb] */
33589 M32C_INSN_STC32_SRC_CR1_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-16-SB-relative-Prefixed-HI", "stc", 40,
33590 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33592 /* stc ${cr1-Prefixed-32},${Dsp-24-s8}[fb] */
33594 M32C_INSN_STC32_SRC_CR1_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-8-FB-relative-Prefixed-HI", "stc", 32,
33595 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33597 /* stc ${cr1-Prefixed-32},${Dsp-24-s16}[fb] */
33599 M32C_INSN_STC32_SRC_CR1_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "stc32.src-cr1-dst32-24-16-FB-relative-Prefixed-HI", "stc", 40,
33600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33602 /* stc ${cr1-Prefixed-32},${Dsp-24-u16} */
33604 M32C_INSN_STC32_SRC_CR1_DST32_24_16_ABSOLUTE_PREFIXED_HI, "stc32.src-cr1-dst32-24-16-absolute-Prefixed-HI", "stc", 40,
33605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33607 /* stc ${cr1-Prefixed-32},${Dsp-24-u24} */
33609 M32C_INSN_STC32_SRC_CR1_DST32_24_24_ABSOLUTE_PREFIXED_HI, "stc32.src-cr1-dst32-24-24-absolute-Prefixed-HI", "stc", 48,
33610 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33612 /* stc pc,$Dst16RnHI */
33614 M32C_INSN_STC16_PC_DST16_RN_DIRECT_HI, "stc16.pc-dst16-Rn-direct-HI", "stc", 16,
33615 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33617 /* stc pc,$Dst16AnHI */
33619 M32C_INSN_STC16_PC_DST16_AN_DIRECT_HI, "stc16.pc-dst16-An-direct-HI", "stc", 16,
33620 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33622 /* stc pc,[$Dst16An] */
33624 M32C_INSN_STC16_PC_DST16_AN_INDIRECT_HI, "stc16.pc-dst16-An-indirect-HI", "stc", 16,
33625 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33627 /* stc pc,${Dsp-16-u8}[$Dst16An] */
33629 M32C_INSN_STC16_PC_DST16_16_8_AN_RELATIVE_HI, "stc16.pc-dst16-16-8-An-relative-HI", "stc", 24,
33630 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33632 /* stc pc,${Dsp-16-u16}[$Dst16An] */
33634 M32C_INSN_STC16_PC_DST16_16_16_AN_RELATIVE_HI, "stc16.pc-dst16-16-16-An-relative-HI", "stc", 32,
33635 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33637 /* stc pc,${Dsp-16-u8}[sb] */
33639 M32C_INSN_STC16_PC_DST16_16_8_SB_RELATIVE_HI, "stc16.pc-dst16-16-8-SB-relative-HI", "stc", 24,
33640 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33642 /* stc pc,${Dsp-16-u16}[sb] */
33644 M32C_INSN_STC16_PC_DST16_16_16_SB_RELATIVE_HI, "stc16.pc-dst16-16-16-SB-relative-HI", "stc", 32,
33645 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33647 /* stc pc,${Dsp-16-s8}[fb] */
33649 M32C_INSN_STC16_PC_DST16_16_8_FB_RELATIVE_HI, "stc16.pc-dst16-16-8-FB-relative-HI", "stc", 24,
33650 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33652 /* stc pc,${Dsp-16-u16} */
33654 M32C_INSN_STC16_PC_DST16_16_16_ABSOLUTE_HI, "stc16.pc-dst16-16-16-absolute-HI", "stc", 32,
33655 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33657 /* stc ${cr16},$Dst16RnHI */
33659 M32C_INSN_STC16_SRC_DST16_RN_DIRECT_HI, "stc16.src-dst16-Rn-direct-HI", "stc", 16,
33660 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33662 /* stc ${cr16},$Dst16AnHI */
33664 M32C_INSN_STC16_SRC_DST16_AN_DIRECT_HI, "stc16.src-dst16-An-direct-HI", "stc", 16,
33665 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33667 /* stc ${cr16},[$Dst16An] */
33669 M32C_INSN_STC16_SRC_DST16_AN_INDIRECT_HI, "stc16.src-dst16-An-indirect-HI", "stc", 16,
33670 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33672 /* stc ${cr16},${Dsp-16-u8}[$Dst16An] */
33674 M32C_INSN_STC16_SRC_DST16_16_8_AN_RELATIVE_HI, "stc16.src-dst16-16-8-An-relative-HI", "stc", 24,
33675 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33677 /* stc ${cr16},${Dsp-16-u16}[$Dst16An] */
33679 M32C_INSN_STC16_SRC_DST16_16_16_AN_RELATIVE_HI, "stc16.src-dst16-16-16-An-relative-HI", "stc", 32,
33680 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33682 /* stc ${cr16},${Dsp-16-u8}[sb] */
33684 M32C_INSN_STC16_SRC_DST16_16_8_SB_RELATIVE_HI, "stc16.src-dst16-16-8-SB-relative-HI", "stc", 24,
33685 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33687 /* stc ${cr16},${Dsp-16-u16}[sb] */
33689 M32C_INSN_STC16_SRC_DST16_16_16_SB_RELATIVE_HI, "stc16.src-dst16-16-16-SB-relative-HI", "stc", 32,
33690 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33692 /* stc ${cr16},${Dsp-16-s8}[fb] */
33694 M32C_INSN_STC16_SRC_DST16_16_8_FB_RELATIVE_HI, "stc16.src-dst16-16-8-FB-relative-HI", "stc", 24,
33695 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33697 /* stc ${cr16},${Dsp-16-u16} */
33699 M32C_INSN_STC16_SRC_DST16_16_16_ABSOLUTE_HI, "stc16.src-dst16-16-16-absolute-HI", "stc", 32,
33700 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33702 /* ldc $Dst32RnPrefixedSI,${cr3-Prefixed-32} */
33704 M32C_INSN_LDC32_SRC_CR3_DST32_RN_DIRECT_PREFIXED_SI, "ldc32.src-cr3-dst32-Rn-direct-Prefixed-SI", "ldc", 24,
33705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33707 /* ldc $Dst32AnPrefixedSI,${cr3-Prefixed-32} */
33709 M32C_INSN_LDC32_SRC_CR3_DST32_AN_DIRECT_PREFIXED_SI, "ldc32.src-cr3-dst32-An-direct-Prefixed-SI", "ldc", 24,
33710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33712 /* ldc [$Dst32AnPrefixed],${cr3-Prefixed-32} */
33714 M32C_INSN_LDC32_SRC_CR3_DST32_AN_INDIRECT_PREFIXED_SI, "ldc32.src-cr3-dst32-An-indirect-Prefixed-SI", "ldc", 24,
33715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33717 /* ldc ${Dsp-24-u8}[$Dst32AnPrefixed],${cr3-Prefixed-32} */
33719 M32C_INSN_LDC32_SRC_CR3_DST32_24_8_AN_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-8-An-relative-Prefixed-SI", "ldc", 32,
33720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33722 /* ldc ${Dsp-24-u16}[$Dst32AnPrefixed],${cr3-Prefixed-32} */
33724 M32C_INSN_LDC32_SRC_CR3_DST32_24_16_AN_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-16-An-relative-Prefixed-SI", "ldc", 40,
33725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33727 /* ldc ${Dsp-24-u24}[$Dst32AnPrefixed],${cr3-Prefixed-32} */
33729 M32C_INSN_LDC32_SRC_CR3_DST32_24_24_AN_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-24-An-relative-Prefixed-SI", "ldc", 48,
33730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33732 /* ldc ${Dsp-24-u8}[sb],${cr3-Prefixed-32} */
33734 M32C_INSN_LDC32_SRC_CR3_DST32_24_8_SB_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-8-SB-relative-Prefixed-SI", "ldc", 32,
33735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33737 /* ldc ${Dsp-24-u16}[sb],${cr3-Prefixed-32} */
33739 M32C_INSN_LDC32_SRC_CR3_DST32_24_16_SB_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-16-SB-relative-Prefixed-SI", "ldc", 40,
33740 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33742 /* ldc ${Dsp-24-s8}[fb],${cr3-Prefixed-32} */
33744 M32C_INSN_LDC32_SRC_CR3_DST32_24_8_FB_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-8-FB-relative-Prefixed-SI", "ldc", 32,
33745 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33747 /* ldc ${Dsp-24-s16}[fb],${cr3-Prefixed-32} */
33749 M32C_INSN_LDC32_SRC_CR3_DST32_24_16_FB_RELATIVE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-16-FB-relative-Prefixed-SI", "ldc", 40,
33750 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33752 /* ldc ${Dsp-24-u16},${cr3-Prefixed-32} */
33754 M32C_INSN_LDC32_SRC_CR3_DST32_24_16_ABSOLUTE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-16-absolute-Prefixed-SI", "ldc", 40,
33755 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33757 /* ldc ${Dsp-24-u24},${cr3-Prefixed-32} */
33759 M32C_INSN_LDC32_SRC_CR3_DST32_24_24_ABSOLUTE_PREFIXED_SI, "ldc32.src-cr3-dst32-24-24-absolute-Prefixed-SI", "ldc", 48,
33760 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33762 /* ldc $Dst32RnUnprefixedSI,${cr2-32} */
33764 M32C_INSN_LDC32_SRC_CR2_DST32_RN_DIRECT_UNPREFIXED_SI, "ldc32.src-cr2-dst32-Rn-direct-Unprefixed-SI", "ldc", 16,
33765 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33767 /* ldc $Dst32AnUnprefixedSI,${cr2-32} */
33769 M32C_INSN_LDC32_SRC_CR2_DST32_AN_DIRECT_UNPREFIXED_SI, "ldc32.src-cr2-dst32-An-direct-Unprefixed-SI", "ldc", 16,
33770 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33772 /* ldc [$Dst32AnUnprefixed],${cr2-32} */
33774 M32C_INSN_LDC32_SRC_CR2_DST32_AN_INDIRECT_UNPREFIXED_SI, "ldc32.src-cr2-dst32-An-indirect-Unprefixed-SI", "ldc", 16,
33775 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33777 /* ldc ${Dsp-16-u8}[$Dst32AnUnprefixed],${cr2-32} */
33779 M32C_INSN_LDC32_SRC_CR2_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-8-An-relative-Unprefixed-SI", "ldc", 24,
33780 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33782 /* ldc ${Dsp-16-u16}[$Dst32AnUnprefixed],${cr2-32} */
33784 M32C_INSN_LDC32_SRC_CR2_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-16-An-relative-Unprefixed-SI", "ldc", 32,
33785 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33787 /* ldc ${Dsp-16-u24}[$Dst32AnUnprefixed],${cr2-32} */
33789 M32C_INSN_LDC32_SRC_CR2_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-24-An-relative-Unprefixed-SI", "ldc", 40,
33790 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33792 /* ldc ${Dsp-16-u8}[sb],${cr2-32} */
33794 M32C_INSN_LDC32_SRC_CR2_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-8-SB-relative-Unprefixed-SI", "ldc", 24,
33795 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33797 /* ldc ${Dsp-16-u16}[sb],${cr2-32} */
33799 M32C_INSN_LDC32_SRC_CR2_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-16-SB-relative-Unprefixed-SI", "ldc", 32,
33800 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33802 /* ldc ${Dsp-16-s8}[fb],${cr2-32} */
33804 M32C_INSN_LDC32_SRC_CR2_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-8-FB-relative-Unprefixed-SI", "ldc", 24,
33805 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33807 /* ldc ${Dsp-16-s16}[fb],${cr2-32} */
33809 M32C_INSN_LDC32_SRC_CR2_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-16-FB-relative-Unprefixed-SI", "ldc", 32,
33810 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33812 /* ldc ${Dsp-16-u16},${cr2-32} */
33814 M32C_INSN_LDC32_SRC_CR2_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-16-absolute-Unprefixed-SI", "ldc", 32,
33815 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33817 /* ldc ${Dsp-16-u24},${cr2-32} */
33819 M32C_INSN_LDC32_SRC_CR2_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "ldc32.src-cr2-dst32-16-24-absolute-Unprefixed-SI", "ldc", 40,
33820 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33822 /* ldc $Dst32RnPrefixedHI,${cr1-Prefixed-32} */
33824 M32C_INSN_LDC32_SRC_CR1_DST32_RN_DIRECT_PREFIXED_HI, "ldc32.src-cr1-dst32-Rn-direct-Prefixed-HI", "ldc", 24,
33825 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33827 /* ldc $Dst32AnPrefixedHI,${cr1-Prefixed-32} */
33829 M32C_INSN_LDC32_SRC_CR1_DST32_AN_DIRECT_PREFIXED_HI, "ldc32.src-cr1-dst32-An-direct-Prefixed-HI", "ldc", 24,
33830 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33832 /* ldc [$Dst32AnPrefixed],${cr1-Prefixed-32} */
33834 M32C_INSN_LDC32_SRC_CR1_DST32_AN_INDIRECT_PREFIXED_HI, "ldc32.src-cr1-dst32-An-indirect-Prefixed-HI", "ldc", 24,
33835 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33837 /* ldc ${Dsp-24-u8}[$Dst32AnPrefixed],${cr1-Prefixed-32} */
33839 M32C_INSN_LDC32_SRC_CR1_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-8-An-relative-Prefixed-HI", "ldc", 32,
33840 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33842 /* ldc ${Dsp-24-u16}[$Dst32AnPrefixed],${cr1-Prefixed-32} */
33844 M32C_INSN_LDC32_SRC_CR1_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-16-An-relative-Prefixed-HI", "ldc", 40,
33845 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33847 /* ldc ${Dsp-24-u24}[$Dst32AnPrefixed],${cr1-Prefixed-32} */
33849 M32C_INSN_LDC32_SRC_CR1_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-24-An-relative-Prefixed-HI", "ldc", 48,
33850 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33852 /* ldc ${Dsp-24-u8}[sb],${cr1-Prefixed-32} */
33854 M32C_INSN_LDC32_SRC_CR1_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-8-SB-relative-Prefixed-HI", "ldc", 32,
33855 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33857 /* ldc ${Dsp-24-u16}[sb],${cr1-Prefixed-32} */
33859 M32C_INSN_LDC32_SRC_CR1_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-16-SB-relative-Prefixed-HI", "ldc", 40,
33860 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33862 /* ldc ${Dsp-24-s8}[fb],${cr1-Prefixed-32} */
33864 M32C_INSN_LDC32_SRC_CR1_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-8-FB-relative-Prefixed-HI", "ldc", 32,
33865 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33867 /* ldc ${Dsp-24-s16}[fb],${cr1-Prefixed-32} */
33869 M32C_INSN_LDC32_SRC_CR1_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-16-FB-relative-Prefixed-HI", "ldc", 40,
33870 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33872 /* ldc ${Dsp-24-u16},${cr1-Prefixed-32} */
33874 M32C_INSN_LDC32_SRC_CR1_DST32_24_16_ABSOLUTE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-16-absolute-Prefixed-HI", "ldc", 40,
33875 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33877 /* ldc ${Dsp-24-u24},${cr1-Prefixed-32} */
33879 M32C_INSN_LDC32_SRC_CR1_DST32_24_24_ABSOLUTE_PREFIXED_HI, "ldc32.src-cr1-dst32-24-24-absolute-Prefixed-HI", "ldc", 48,
33880 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
33882 /* ldc $Dst16RnHI,${cr16} */
33884 M32C_INSN_LDC16_DST_DST16_RN_DIRECT_HI, "ldc16.dst-dst16-Rn-direct-HI", "ldc", 16,
33885 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33887 /* ldc $Dst16AnHI,${cr16} */
33889 M32C_INSN_LDC16_DST_DST16_AN_DIRECT_HI, "ldc16.dst-dst16-An-direct-HI", "ldc", 16,
33890 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33892 /* ldc [$Dst16An],${cr16} */
33894 M32C_INSN_LDC16_DST_DST16_AN_INDIRECT_HI, "ldc16.dst-dst16-An-indirect-HI", "ldc", 16,
33895 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33897 /* ldc ${Dsp-16-u8}[$Dst16An],${cr16} */
33899 M32C_INSN_LDC16_DST_DST16_16_8_AN_RELATIVE_HI, "ldc16.dst-dst16-16-8-An-relative-HI", "ldc", 24,
33900 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33902 /* ldc ${Dsp-16-u16}[$Dst16An],${cr16} */
33904 M32C_INSN_LDC16_DST_DST16_16_16_AN_RELATIVE_HI, "ldc16.dst-dst16-16-16-An-relative-HI", "ldc", 32,
33905 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33907 /* ldc ${Dsp-16-u8}[sb],${cr16} */
33909 M32C_INSN_LDC16_DST_DST16_16_8_SB_RELATIVE_HI, "ldc16.dst-dst16-16-8-SB-relative-HI", "ldc", 24,
33910 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33912 /* ldc ${Dsp-16-u16}[sb],${cr16} */
33914 M32C_INSN_LDC16_DST_DST16_16_16_SB_RELATIVE_HI, "ldc16.dst-dst16-16-16-SB-relative-HI", "ldc", 32,
33915 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33917 /* ldc ${Dsp-16-s8}[fb],${cr16} */
33919 M32C_INSN_LDC16_DST_DST16_16_8_FB_RELATIVE_HI, "ldc16.dst-dst16-16-8-FB-relative-HI", "ldc", 24,
33920 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33922 /* ldc ${Dsp-16-u16},${cr16} */
33924 M32C_INSN_LDC16_DST_DST16_16_16_ABSOLUTE_HI, "ldc16.dst-dst16-16-16-absolute-HI", "ldc", 32,
33925 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
33927 /* jsri.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
33929 M32C_INSN_JSRI32_A_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "jsri32.a-dst32-16-24-An-relative-Unprefixed-SI", "jsri.w", 40,
33930 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
33932 /* jsri.w ${Dsp-16-u24} */
33934 M32C_INSN_JSRI32_A_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "jsri32.a-dst32-16-24-absolute-Unprefixed-SI", "jsri.w", 40,
33935 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
33937 /* jsri.a ${Dsp-16-u16}[$Dst32AnUnprefixed] */
33939 M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-16-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "jsri.a", 32,
33940 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
33942 /* jsri.a ${Dsp-16-u16}[sb] */
33944 M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-16-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "jsri.a", 32,
33945 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
33947 /* jsri.a ${Dsp-16-s16}[fb] */
33949 M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-16-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "jsri.a", 32,
33950 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
33952 /* jsri.a ${Dsp-16-u16} */
33954 M32C_INSN_JSRI32A_DST32_16_16_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "jsri32a-dst32-16-16-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "jsri.a", 32,
33955 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
33957 /* jsri.a ${Dsp-16-u16}[$Dst16An] */
33959 M32C_INSN_JSRI16A_DST16_16_16_SI_DST16_16_16_AN_RELATIVE_SI, "jsri16a-dst16-16-16-SI-dst16-16-16-An-relative-SI", "jsri.a", 32,
33960 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
33962 /* jsri.a ${Dsp-16-u16}[sb] */
33964 M32C_INSN_JSRI16A_DST16_16_16_SI_DST16_16_16_SB_RELATIVE_SI, "jsri16a-dst16-16-16-SI-dst16-16-16-SB-relative-SI", "jsri.a", 32,
33965 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
33967 /* jsri.a ${Dsp-16-u16} */
33969 M32C_INSN_JSRI16A_DST16_16_16_SI_DST16_16_16_ABSOLUTE_SI, "jsri16a-dst16-16-16-SI-dst16-16-16-absolute-SI", "jsri.a", 32,
33970 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
33972 /* jsri.a ${Dsp-16-u8}[$Dst32AnUnprefixed] */
33974 M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-8-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "jsri.a", 24,
33975 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
33977 /* jsri.a ${Dsp-16-u8}[sb] */
33979 M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-8-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "jsri.a", 24,
33980 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
33982 /* jsri.a ${Dsp-16-s8}[fb] */
33984 M32C_INSN_JSRI32A_DST32_16_8_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "jsri32a-dst32-16-8-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "jsri.a", 24,
33985 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
33987 /* jsri.a ${Dsp-16-u8}[$Dst16An] */
33989 M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_AN_RELATIVE_SI, "jsri16a-dst16-16-8-SI-dst16-16-8-An-relative-SI", "jsri.a", 24,
33990 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
33992 /* jsri.a ${Dsp-16-u8}[sb] */
33994 M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_SB_RELATIVE_SI, "jsri16a-dst16-16-8-SI-dst16-16-8-SB-relative-SI", "jsri.a", 24,
33995 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
33997 /* jsri.a ${Dsp-16-s8}[fb] */
33999 M32C_INSN_JSRI16A_DST16_16_8_SI_DST16_16_8_FB_RELATIVE_SI, "jsri16a-dst16-16-8-SI-dst16-16-8-FB-relative-SI", "jsri.a", 24,
34000 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34002 /* jsri.a $Dst32RnUnprefixedSI */
34004 M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "jsri32a-dst32-basic-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "jsri.a", 16,
34005 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34007 /* jsri.a $Dst32AnUnprefixedSI */
34009 M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "jsri32a-dst32-basic-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "jsri.a", 16,
34010 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34012 /* jsri.a [$Dst32AnUnprefixed] */
34014 M32C_INSN_JSRI32A_DST32_BASIC_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "jsri32a-dst32-basic-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "jsri.a", 16,
34015 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34017 /* jsri.a $Dst16RnSI */
34019 M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_RN_DIRECT_SI, "jsri16a-dst16-basic-SI-dst16-Rn-direct-SI", "jsri.a", 16,
34020 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34022 /* jsri.a $Dst16AnSI */
34024 M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_AN_DIRECT_SI, "jsri16a-dst16-basic-SI-dst16-An-direct-SI", "jsri.a", 16,
34025 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34027 /* jsri.a [$Dst16An] */
34029 M32C_INSN_JSRI16A_DST16_BASIC_SI_DST16_AN_INDIRECT_SI, "jsri16a-dst16-basic-SI-dst16-An-indirect-SI", "jsri.a", 16,
34030 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34032 /* jsri.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34034 M32C_INSN_JSRI32_W_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "jsri32.w-dst32-16-24-An-relative-Unprefixed-HI", "jsri.w", 40,
34035 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34037 /* jsri.w ${Dsp-16-u24} */
34039 M32C_INSN_JSRI32_W_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "jsri32.w-dst32-16-24-absolute-Unprefixed-HI", "jsri.w", 40,
34040 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34042 /* jsri.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34044 M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-16-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "jsri.w", 32,
34045 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34047 /* jsri.w ${Dsp-16-u16}[sb] */
34049 M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-16-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "jsri.w", 32,
34050 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34052 /* jsri.w ${Dsp-16-s16}[fb] */
34054 M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-16-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "jsri.w", 32,
34055 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34057 /* jsri.w ${Dsp-16-u16} */
34059 M32C_INSN_JSRI32W_DST32_16_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "jsri32w-dst32-16-16-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "jsri.w", 32,
34060 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34062 /* jsri.w ${Dsp-16-u16}[$Dst16An] */
34064 M32C_INSN_JSRI16W_DST16_16_16_HI_DST16_16_16_AN_RELATIVE_HI, "jsri16w-dst16-16-16-HI-dst16-16-16-An-relative-HI", "jsri.w", 32,
34065 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34067 /* jsri.w ${Dsp-16-u16}[sb] */
34069 M32C_INSN_JSRI16W_DST16_16_16_HI_DST16_16_16_SB_RELATIVE_HI, "jsri16w-dst16-16-16-HI-dst16-16-16-SB-relative-HI", "jsri.w", 32,
34070 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34072 /* jsri.w ${Dsp-16-u16} */
34074 M32C_INSN_JSRI16W_DST16_16_16_HI_DST16_16_16_ABSOLUTE_HI, "jsri16w-dst16-16-16-HI-dst16-16-16-absolute-HI", "jsri.w", 32,
34075 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34077 /* jsri.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34079 M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-8-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "jsri.w", 24,
34080 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34082 /* jsri.w ${Dsp-16-u8}[sb] */
34084 M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-8-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "jsri.w", 24,
34085 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34087 /* jsri.w ${Dsp-16-s8}[fb] */
34089 M32C_INSN_JSRI32W_DST32_16_8_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "jsri32w-dst32-16-8-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "jsri.w", 24,
34090 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34092 /* jsri.w ${Dsp-16-u8}[$Dst16An] */
34094 M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_AN_RELATIVE_HI, "jsri16w-dst16-16-8-HI-dst16-16-8-An-relative-HI", "jsri.w", 24,
34095 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34097 /* jsri.w ${Dsp-16-u8}[sb] */
34099 M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_SB_RELATIVE_HI, "jsri16w-dst16-16-8-HI-dst16-16-8-SB-relative-HI", "jsri.w", 24,
34100 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34102 /* jsri.w ${Dsp-16-s8}[fb] */
34104 M32C_INSN_JSRI16W_DST16_16_8_HI_DST16_16_8_FB_RELATIVE_HI, "jsri16w-dst16-16-8-HI-dst16-16-8-FB-relative-HI", "jsri.w", 24,
34105 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34107 /* jsri.w $Dst32RnUnprefixedHI */
34109 M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "jsri32w-dst32-basic-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "jsri.w", 16,
34110 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34112 /* jsri.w $Dst32AnUnprefixedHI */
34114 M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "jsri32w-dst32-basic-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "jsri.w", 16,
34115 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34117 /* jsri.w [$Dst32AnUnprefixed] */
34119 M32C_INSN_JSRI32W_DST32_BASIC_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "jsri32w-dst32-basic-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "jsri.w", 16,
34120 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34122 /* jsri.w $Dst16RnHI */
34124 M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_RN_DIRECT_HI, "jsri16w-dst16-basic-HI-dst16-Rn-direct-HI", "jsri.w", 16,
34125 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34127 /* jsri.w $Dst16AnHI */
34129 M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_AN_DIRECT_HI, "jsri16w-dst16-basic-HI-dst16-An-direct-HI", "jsri.w", 16,
34130 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34132 /* jsri.w [$Dst16An] */
34134 M32C_INSN_JSRI16W_DST16_BASIC_HI_DST16_AN_INDIRECT_HI, "jsri16w-dst16-basic-HI-dst16-An-indirect-HI", "jsri.w", 16,
34135 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34137 /* jmpi.a $Dst32RnUnprefixedSI */
34139 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "jmpi.a", 16,
34140 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34142 /* jmpi.a $Dst32AnUnprefixedSI */
34144 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-An-direct-Unprefixed-SI", "jmpi.a", 16,
34145 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34147 /* jmpi.a [$Dst32AnUnprefixed] */
34149 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-An-indirect-Unprefixed-SI", "jmpi.a", 16,
34150 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34152 /* jmpi.a ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34154 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "jmpi.a", 24,
34155 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34157 /* jmpi.a ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34159 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "jmpi.a", 32,
34160 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34162 /* jmpi.a ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34164 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "jmpi.a", 40,
34165 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34167 /* jmpi.a ${Dsp-16-u8}[sb] */
34169 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "jmpi.a", 24,
34170 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34172 /* jmpi.a ${Dsp-16-u16}[sb] */
34174 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "jmpi.a", 32,
34175 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34177 /* jmpi.a ${Dsp-16-s8}[fb] */
34179 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "jmpi.a", 24,
34180 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34182 /* jmpi.a ${Dsp-16-s16}[fb] */
34184 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "jmpi.a", 32,
34185 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34187 /* jmpi.a ${Dsp-16-u16} */
34189 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "jmpi.a", 32,
34190 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34192 /* jmpi.a ${Dsp-16-u24} */
34194 M32C_INSN_JMPI32_A_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "jmpi32.a-16-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "jmpi.a", 40,
34195 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34197 /* jmpi.a $Dst16RnSI */
34199 M32C_INSN_JMPI16_A_16_DST16_RN_DIRECT_SI, "jmpi16.a-16-dst16-Rn-direct-SI", "jmpi.a", 16,
34200 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34202 /* jmpi.a $Dst16AnSI */
34204 M32C_INSN_JMPI16_A_16_DST16_AN_DIRECT_SI, "jmpi16.a-16-dst16-An-direct-SI", "jmpi.a", 16,
34205 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34207 /* jmpi.a [$Dst16An] */
34209 M32C_INSN_JMPI16_A_16_DST16_AN_INDIRECT_SI, "jmpi16.a-16-dst16-An-indirect-SI", "jmpi.a", 16,
34210 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34212 /* jmpi.a ${Dsp-16-u8}[$Dst16An] */
34214 M32C_INSN_JMPI16_A_16_DST16_16_8_AN_RELATIVE_SI, "jmpi16.a-16-dst16-16-8-An-relative-SI", "jmpi.a", 24,
34215 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34217 /* jmpi.a ${Dsp-16-u16}[$Dst16An] */
34219 M32C_INSN_JMPI16_A_16_DST16_16_16_AN_RELATIVE_SI, "jmpi16.a-16-dst16-16-16-An-relative-SI", "jmpi.a", 32,
34220 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34222 /* jmpi.a ${Dsp-16-u8}[sb] */
34224 M32C_INSN_JMPI16_A_16_DST16_16_8_SB_RELATIVE_SI, "jmpi16.a-16-dst16-16-8-SB-relative-SI", "jmpi.a", 24,
34225 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34227 /* jmpi.a ${Dsp-16-u16}[sb] */
34229 M32C_INSN_JMPI16_A_16_DST16_16_16_SB_RELATIVE_SI, "jmpi16.a-16-dst16-16-16-SB-relative-SI", "jmpi.a", 32,
34230 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34232 /* jmpi.a ${Dsp-16-s8}[fb] */
34234 M32C_INSN_JMPI16_A_16_DST16_16_8_FB_RELATIVE_SI, "jmpi16.a-16-dst16-16-8-FB-relative-SI", "jmpi.a", 24,
34235 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34237 /* jmpi.a ${Dsp-16-u16} */
34239 M32C_INSN_JMPI16_A_16_DST16_16_16_ABSOLUTE_SI, "jmpi16.a-16-dst16-16-16-absolute-SI", "jmpi.a", 32,
34240 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34242 /* jmpi.w $Dst32RnUnprefixedHI */
34244 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "jmpi.w", 16,
34245 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34247 /* jmpi.w $Dst32AnUnprefixedHI */
34249 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "jmpi.w", 16,
34250 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34252 /* jmpi.w [$Dst32AnUnprefixed] */
34254 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "jmpi.w", 16,
34255 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34257 /* jmpi.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34259 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "jmpi.w", 24,
34260 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34262 /* jmpi.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34264 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "jmpi.w", 32,
34265 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34267 /* jmpi.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34269 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "jmpi.w", 40,
34270 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34272 /* jmpi.w ${Dsp-16-u8}[sb] */
34274 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "jmpi.w", 24,
34275 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34277 /* jmpi.w ${Dsp-16-u16}[sb] */
34279 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "jmpi.w", 32,
34280 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34282 /* jmpi.w ${Dsp-16-s8}[fb] */
34284 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "jmpi.w", 24,
34285 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34287 /* jmpi.w ${Dsp-16-s16}[fb] */
34289 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "jmpi.w", 32,
34290 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34292 /* jmpi.w ${Dsp-16-u16} */
34294 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "jmpi.w", 32,
34295 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34297 /* jmpi.w ${Dsp-16-u24} */
34299 M32C_INSN_JMPI32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "jmpi32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "jmpi.w", 40,
34300 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
34302 /* jmpi.w $Dst16RnHI */
34304 M32C_INSN_JMPI16_W_16_DST16_RN_DIRECT_HI, "jmpi16.w-16-dst16-Rn-direct-HI", "jmpi.w", 16,
34305 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34307 /* jmpi.w $Dst16AnHI */
34309 M32C_INSN_JMPI16_W_16_DST16_AN_DIRECT_HI, "jmpi16.w-16-dst16-An-direct-HI", "jmpi.w", 16,
34310 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34312 /* jmpi.w [$Dst16An] */
34314 M32C_INSN_JMPI16_W_16_DST16_AN_INDIRECT_HI, "jmpi16.w-16-dst16-An-indirect-HI", "jmpi.w", 16,
34315 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34317 /* jmpi.w ${Dsp-16-u8}[$Dst16An] */
34319 M32C_INSN_JMPI16_W_16_DST16_16_8_AN_RELATIVE_HI, "jmpi16.w-16-dst16-16-8-An-relative-HI", "jmpi.w", 24,
34320 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34322 /* jmpi.w ${Dsp-16-u16}[$Dst16An] */
34324 M32C_INSN_JMPI16_W_16_DST16_16_16_AN_RELATIVE_HI, "jmpi16.w-16-dst16-16-16-An-relative-HI", "jmpi.w", 32,
34325 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34327 /* jmpi.w ${Dsp-16-u8}[sb] */
34329 M32C_INSN_JMPI16_W_16_DST16_16_8_SB_RELATIVE_HI, "jmpi16.w-16-dst16-16-8-SB-relative-HI", "jmpi.w", 24,
34330 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34332 /* jmpi.w ${Dsp-16-u16}[sb] */
34334 M32C_INSN_JMPI16_W_16_DST16_16_16_SB_RELATIVE_HI, "jmpi16.w-16-dst16-16-16-SB-relative-HI", "jmpi.w", 32,
34335 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34337 /* jmpi.w ${Dsp-16-s8}[fb] */
34339 M32C_INSN_JMPI16_W_16_DST16_16_8_FB_RELATIVE_HI, "jmpi16.w-16-dst16-16-8-FB-relative-HI", "jmpi.w", 24,
34340 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34342 /* jmpi.w ${Dsp-16-u16} */
34344 M32C_INSN_JMPI16_W_16_DST16_16_16_ABSOLUTE_HI, "jmpi16.w-16-dst16-16-16-absolute-HI", "jmpi.w", 32,
34345 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
34347 /* indexws.w $Dst32RnUnprefixedHI */
34349 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexws.w", 16,
34350 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34352 /* indexws.w $Dst32AnUnprefixedHI */
34354 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexws.w", 16,
34355 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34357 /* indexws.w [$Dst32AnUnprefixed] */
34359 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexws.w", 16,
34360 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34362 /* indexws.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34364 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexws.w", 24,
34365 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34367 /* indexws.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34369 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexws.w", 32,
34370 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34372 /* indexws.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34374 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexws.w", 40,
34375 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34377 /* indexws.w ${Dsp-16-u8}[sb] */
34379 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexws.w", 24,
34380 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34382 /* indexws.w ${Dsp-16-u16}[sb] */
34384 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexws.w", 32,
34385 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34387 /* indexws.w ${Dsp-16-s8}[fb] */
34389 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexws.w", 24,
34390 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34392 /* indexws.w ${Dsp-16-s16}[fb] */
34394 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexws.w", 32,
34395 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34397 /* indexws.w ${Dsp-16-u16} */
34399 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexws.w", 32,
34400 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34402 /* indexws.w ${Dsp-16-u24} */
34404 M32C_INSN_INDEXWS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexws32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexws.w", 40,
34405 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34407 /* indexws.b $Dst32RnUnprefixedQI */
34409 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexws.b", 16,
34410 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34412 /* indexws.b $Dst32AnUnprefixedQI */
34414 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexws.b", 16,
34415 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34417 /* indexws.b [$Dst32AnUnprefixed] */
34419 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexws.b", 16,
34420 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34422 /* indexws.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34424 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexws.b", 24,
34425 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34427 /* indexws.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34429 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexws.b", 32,
34430 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34432 /* indexws.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34434 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexws.b", 40,
34435 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34437 /* indexws.b ${Dsp-16-u8}[sb] */
34439 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexws.b", 24,
34440 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34442 /* indexws.b ${Dsp-16-u16}[sb] */
34444 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexws.b", 32,
34445 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34447 /* indexws.b ${Dsp-16-s8}[fb] */
34449 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexws.b", 24,
34450 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34452 /* indexws.b ${Dsp-16-s16}[fb] */
34454 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexws.b", 32,
34455 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34457 /* indexws.b ${Dsp-16-u16} */
34459 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexws.b", 32,
34460 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34462 /* indexws.b ${Dsp-16-u24} */
34464 M32C_INSN_INDEXWS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexws32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexws.b", 40,
34465 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34467 /* indexwd.w $Dst32RnUnprefixedHI */
34469 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexwd.w", 16,
34470 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34472 /* indexwd.w $Dst32AnUnprefixedHI */
34474 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexwd.w", 16,
34475 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34477 /* indexwd.w [$Dst32AnUnprefixed] */
34479 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexwd.w", 16,
34480 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34482 /* indexwd.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34484 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexwd.w", 24,
34485 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34487 /* indexwd.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34489 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexwd.w", 32,
34490 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34492 /* indexwd.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34494 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexwd.w", 40,
34495 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34497 /* indexwd.w ${Dsp-16-u8}[sb] */
34499 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexwd.w", 24,
34500 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34502 /* indexwd.w ${Dsp-16-u16}[sb] */
34504 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexwd.w", 32,
34505 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34507 /* indexwd.w ${Dsp-16-s8}[fb] */
34509 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexwd.w", 24,
34510 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34512 /* indexwd.w ${Dsp-16-s16}[fb] */
34514 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexwd.w", 32,
34515 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34517 /* indexwd.w ${Dsp-16-u16} */
34519 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexwd.w", 32,
34520 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34522 /* indexwd.w ${Dsp-16-u24} */
34524 M32C_INSN_INDEXWD32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexwd32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexwd.w", 40,
34525 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34527 /* indexwd.b $Dst32RnUnprefixedQI */
34529 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexwd.b", 16,
34530 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34532 /* indexwd.b $Dst32AnUnprefixedQI */
34534 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexwd.b", 16,
34535 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34537 /* indexwd.b [$Dst32AnUnprefixed] */
34539 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexwd.b", 16,
34540 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34542 /* indexwd.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34544 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexwd.b", 24,
34545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34547 /* indexwd.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34549 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexwd.b", 32,
34550 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34552 /* indexwd.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34554 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexwd.b", 40,
34555 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34557 /* indexwd.b ${Dsp-16-u8}[sb] */
34559 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexwd.b", 24,
34560 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34562 /* indexwd.b ${Dsp-16-u16}[sb] */
34564 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexwd.b", 32,
34565 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34567 /* indexwd.b ${Dsp-16-s8}[fb] */
34569 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexwd.b", 24,
34570 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34572 /* indexwd.b ${Dsp-16-s16}[fb] */
34574 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexwd.b", 32,
34575 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34577 /* indexwd.b ${Dsp-16-u16} */
34579 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexwd.b", 32,
34580 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34582 /* indexwd.b ${Dsp-16-u24} */
34584 M32C_INSN_INDEXWD32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexwd32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexwd.b", 40,
34585 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34587 /* indexw.w $Dst32RnUnprefixedHI */
34589 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexw.w", 16,
34590 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34592 /* indexw.w $Dst32AnUnprefixedHI */
34594 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexw.w", 16,
34595 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34597 /* indexw.w [$Dst32AnUnprefixed] */
34599 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexw.w", 16,
34600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34602 /* indexw.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34604 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexw.w", 24,
34605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34607 /* indexw.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34609 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexw.w", 32,
34610 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34612 /* indexw.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34614 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexw.w", 40,
34615 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34617 /* indexw.w ${Dsp-16-u8}[sb] */
34619 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexw.w", 24,
34620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34622 /* indexw.w ${Dsp-16-u16}[sb] */
34624 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexw.w", 32,
34625 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34627 /* indexw.w ${Dsp-16-s8}[fb] */
34629 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexw.w", 24,
34630 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34632 /* indexw.w ${Dsp-16-s16}[fb] */
34634 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexw.w", 32,
34635 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34637 /* indexw.w ${Dsp-16-u16} */
34639 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexw.w", 32,
34640 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34642 /* indexw.w ${Dsp-16-u24} */
34644 M32C_INSN_INDEXW32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexw32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexw.w", 40,
34645 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34647 /* indexw.b $Dst32RnUnprefixedQI */
34649 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexw.b", 16,
34650 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34652 /* indexw.b $Dst32AnUnprefixedQI */
34654 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexw.b", 16,
34655 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34657 /* indexw.b [$Dst32AnUnprefixed] */
34659 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexw.b", 16,
34660 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34662 /* indexw.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34664 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexw.b", 24,
34665 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34667 /* indexw.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34669 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexw.b", 32,
34670 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34672 /* indexw.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34674 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexw.b", 40,
34675 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34677 /* indexw.b ${Dsp-16-u8}[sb] */
34679 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexw.b", 24,
34680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34682 /* indexw.b ${Dsp-16-u16}[sb] */
34684 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexw.b", 32,
34685 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34687 /* indexw.b ${Dsp-16-s8}[fb] */
34689 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexw.b", 24,
34690 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34692 /* indexw.b ${Dsp-16-s16}[fb] */
34694 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexw.b", 32,
34695 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34697 /* indexw.b ${Dsp-16-u16} */
34699 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexw.b", 32,
34700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34702 /* indexw.b ${Dsp-16-u24} */
34704 M32C_INSN_INDEXW32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexw32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexw.b", 40,
34705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34707 /* indexls.w $Dst32RnUnprefixedHI */
34709 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexls.w", 16,
34710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34712 /* indexls.w $Dst32AnUnprefixedHI */
34714 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexls.w", 16,
34715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34717 /* indexls.w [$Dst32AnUnprefixed] */
34719 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexls.w", 16,
34720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34722 /* indexls.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34724 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexls.w", 24,
34725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34727 /* indexls.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34729 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexls.w", 32,
34730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34732 /* indexls.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34734 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexls.w", 40,
34735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34737 /* indexls.w ${Dsp-16-u8}[sb] */
34739 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexls.w", 24,
34740 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34742 /* indexls.w ${Dsp-16-u16}[sb] */
34744 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexls.w", 32,
34745 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34747 /* indexls.w ${Dsp-16-s8}[fb] */
34749 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexls.w", 24,
34750 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34752 /* indexls.w ${Dsp-16-s16}[fb] */
34754 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexls.w", 32,
34755 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34757 /* indexls.w ${Dsp-16-u16} */
34759 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexls.w", 32,
34760 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34762 /* indexls.w ${Dsp-16-u24} */
34764 M32C_INSN_INDEXLS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexls32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexls.w", 40,
34765 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34767 /* indexls.b $Dst32RnUnprefixedQI */
34769 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexls.b", 16,
34770 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34772 /* indexls.b $Dst32AnUnprefixedQI */
34774 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexls.b", 16,
34775 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34777 /* indexls.b [$Dst32AnUnprefixed] */
34779 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexls.b", 16,
34780 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34782 /* indexls.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34784 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexls.b", 24,
34785 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34787 /* indexls.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34789 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexls.b", 32,
34790 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34792 /* indexls.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34794 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexls.b", 40,
34795 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34797 /* indexls.b ${Dsp-16-u8}[sb] */
34799 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexls.b", 24,
34800 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34802 /* indexls.b ${Dsp-16-u16}[sb] */
34804 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexls.b", 32,
34805 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34807 /* indexls.b ${Dsp-16-s8}[fb] */
34809 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexls.b", 24,
34810 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34812 /* indexls.b ${Dsp-16-s16}[fb] */
34814 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexls.b", 32,
34815 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34817 /* indexls.b ${Dsp-16-u16} */
34819 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexls.b", 32,
34820 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34822 /* indexls.b ${Dsp-16-u24} */
34824 M32C_INSN_INDEXLS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexls32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexls.b", 40,
34825 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34827 /* indexld.w $Dst32RnUnprefixedHI */
34829 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexld.w", 16,
34830 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34832 /* indexld.w $Dst32AnUnprefixedHI */
34834 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexld.w", 16,
34835 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34837 /* indexld.w [$Dst32AnUnprefixed] */
34839 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexld.w", 16,
34840 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34842 /* indexld.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34844 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexld.w", 24,
34845 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34847 /* indexld.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34849 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexld.w", 32,
34850 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34852 /* indexld.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34854 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexld.w", 40,
34855 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34857 /* indexld.w ${Dsp-16-u8}[sb] */
34859 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexld.w", 24,
34860 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34862 /* indexld.w ${Dsp-16-u16}[sb] */
34864 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexld.w", 32,
34865 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34867 /* indexld.w ${Dsp-16-s8}[fb] */
34869 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexld.w", 24,
34870 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34872 /* indexld.w ${Dsp-16-s16}[fb] */
34874 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexld.w", 32,
34875 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34877 /* indexld.w ${Dsp-16-u16} */
34879 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexld.w", 32,
34880 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34882 /* indexld.w ${Dsp-16-u24} */
34884 M32C_INSN_INDEXLD32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexld32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexld.w", 40,
34885 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34887 /* indexld.b $Dst32RnUnprefixedQI */
34889 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexld.b", 16,
34890 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34892 /* indexld.b $Dst32AnUnprefixedQI */
34894 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexld.b", 16,
34895 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34897 /* indexld.b [$Dst32AnUnprefixed] */
34899 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexld.b", 16,
34900 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34902 /* indexld.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34904 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexld.b", 24,
34905 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34907 /* indexld.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34909 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexld.b", 32,
34910 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34912 /* indexld.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34914 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexld.b", 40,
34915 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34917 /* indexld.b ${Dsp-16-u8}[sb] */
34919 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexld.b", 24,
34920 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34922 /* indexld.b ${Dsp-16-u16}[sb] */
34924 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexld.b", 32,
34925 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34927 /* indexld.b ${Dsp-16-s8}[fb] */
34929 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexld.b", 24,
34930 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34932 /* indexld.b ${Dsp-16-s16}[fb] */
34934 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexld.b", 32,
34935 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34937 /* indexld.b ${Dsp-16-u16} */
34939 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexld.b", 32,
34940 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34942 /* indexld.b ${Dsp-16-u24} */
34944 M32C_INSN_INDEXLD32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexld32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexld.b", 40,
34945 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34947 /* indexl.w $Dst32RnUnprefixedHI */
34949 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexl.w", 16,
34950 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34952 /* indexl.w $Dst32AnUnprefixedHI */
34954 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexl.w", 16,
34955 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34957 /* indexl.w [$Dst32AnUnprefixed] */
34959 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexl.w", 16,
34960 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34962 /* indexl.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
34964 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexl.w", 24,
34965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34967 /* indexl.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
34969 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexl.w", 32,
34970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34972 /* indexl.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
34974 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexl.w", 40,
34975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34977 /* indexl.w ${Dsp-16-u8}[sb] */
34979 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexl.w", 24,
34980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34982 /* indexl.w ${Dsp-16-u16}[sb] */
34984 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexl.w", 32,
34985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34987 /* indexl.w ${Dsp-16-s8}[fb] */
34989 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexl.w", 24,
34990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34992 /* indexl.w ${Dsp-16-s16}[fb] */
34994 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexl.w", 32,
34995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
34997 /* indexl.w ${Dsp-16-u16} */
34999 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexl.w", 32,
35000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35002 /* indexl.w ${Dsp-16-u24} */
35004 M32C_INSN_INDEXL32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexl32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexl.w", 40,
35005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35007 /* indexl.b $Dst32RnUnprefixedQI */
35009 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexl.b", 16,
35010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35012 /* indexl.b $Dst32AnUnprefixedQI */
35014 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexl.b", 16,
35015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35017 /* indexl.b [$Dst32AnUnprefixed] */
35019 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexl.b", 16,
35020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35022 /* indexl.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35024 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexl.b", 24,
35025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35027 /* indexl.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35029 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexl.b", 32,
35030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35032 /* indexl.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35034 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexl.b", 40,
35035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35037 /* indexl.b ${Dsp-16-u8}[sb] */
35039 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexl.b", 24,
35040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35042 /* indexl.b ${Dsp-16-u16}[sb] */
35044 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexl.b", 32,
35045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35047 /* indexl.b ${Dsp-16-s8}[fb] */
35049 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexl.b", 24,
35050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35052 /* indexl.b ${Dsp-16-s16}[fb] */
35054 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexl.b", 32,
35055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35057 /* indexl.b ${Dsp-16-u16} */
35059 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexl.b", 32,
35060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35062 /* indexl.b ${Dsp-16-u24} */
35064 M32C_INSN_INDEXL32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexl32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexl.b", 40,
35065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35067 /* indexbs.w $Dst32RnUnprefixedHI */
35069 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexbs.w", 16,
35070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35072 /* indexbs.w $Dst32AnUnprefixedHI */
35074 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexbs.w", 16,
35075 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35077 /* indexbs.w [$Dst32AnUnprefixed] */
35079 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexbs.w", 16,
35080 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35082 /* indexbs.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35084 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexbs.w", 24,
35085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35087 /* indexbs.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35089 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexbs.w", 32,
35090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35092 /* indexbs.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35094 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexbs.w", 40,
35095 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35097 /* indexbs.w ${Dsp-16-u8}[sb] */
35099 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexbs.w", 24,
35100 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35102 /* indexbs.w ${Dsp-16-u16}[sb] */
35104 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexbs.w", 32,
35105 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35107 /* indexbs.w ${Dsp-16-s8}[fb] */
35109 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexbs.w", 24,
35110 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35112 /* indexbs.w ${Dsp-16-s16}[fb] */
35114 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexbs.w", 32,
35115 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35117 /* indexbs.w ${Dsp-16-u16} */
35119 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexbs.w", 32,
35120 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35122 /* indexbs.w ${Dsp-16-u24} */
35124 M32C_INSN_INDEXBS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexbs32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexbs.w", 40,
35125 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35127 /* indexbs.b $Dst32RnUnprefixedQI */
35129 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexbs.b", 16,
35130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35132 /* indexbs.b $Dst32AnUnprefixedQI */
35134 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexbs.b", 16,
35135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35137 /* indexbs.b [$Dst32AnUnprefixed] */
35139 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexbs.b", 16,
35140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35142 /* indexbs.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35144 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexbs.b", 24,
35145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35147 /* indexbs.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35149 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexbs.b", 32,
35150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35152 /* indexbs.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35154 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexbs.b", 40,
35155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35157 /* indexbs.b ${Dsp-16-u8}[sb] */
35159 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexbs.b", 24,
35160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35162 /* indexbs.b ${Dsp-16-u16}[sb] */
35164 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexbs.b", 32,
35165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35167 /* indexbs.b ${Dsp-16-s8}[fb] */
35169 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexbs.b", 24,
35170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35172 /* indexbs.b ${Dsp-16-s16}[fb] */
35174 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexbs.b", 32,
35175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35177 /* indexbs.b ${Dsp-16-u16} */
35179 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexbs.b", 32,
35180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35182 /* indexbs.b ${Dsp-16-u24} */
35184 M32C_INSN_INDEXBS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexbs32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexbs.b", 40,
35185 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35187 /* indexbd.w $Dst32RnUnprefixedHI */
35189 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexbd.w", 16,
35190 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35192 /* indexbd.w $Dst32AnUnprefixedHI */
35194 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexbd.w", 16,
35195 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35197 /* indexbd.w [$Dst32AnUnprefixed] */
35199 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexbd.w", 16,
35200 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35202 /* indexbd.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35204 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexbd.w", 24,
35205 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35207 /* indexbd.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35209 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexbd.w", 32,
35210 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35212 /* indexbd.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35214 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexbd.w", 40,
35215 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35217 /* indexbd.w ${Dsp-16-u8}[sb] */
35219 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexbd.w", 24,
35220 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35222 /* indexbd.w ${Dsp-16-u16}[sb] */
35224 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexbd.w", 32,
35225 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35227 /* indexbd.w ${Dsp-16-s8}[fb] */
35229 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexbd.w", 24,
35230 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35232 /* indexbd.w ${Dsp-16-s16}[fb] */
35234 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexbd.w", 32,
35235 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35237 /* indexbd.w ${Dsp-16-u16} */
35239 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexbd.w", 32,
35240 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35242 /* indexbd.w ${Dsp-16-u24} */
35244 M32C_INSN_INDEXBD32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexbd32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexbd.w", 40,
35245 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35247 /* indexbd.b $Dst32RnUnprefixedQI */
35249 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexbd.b", 16,
35250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35252 /* indexbd.b $Dst32AnUnprefixedQI */
35254 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexbd.b", 16,
35255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35257 /* indexbd.b [$Dst32AnUnprefixed] */
35259 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexbd.b", 16,
35260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35262 /* indexbd.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35264 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexbd.b", 24,
35265 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35267 /* indexbd.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35269 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexbd.b", 32,
35270 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35272 /* indexbd.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35274 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexbd.b", 40,
35275 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35277 /* indexbd.b ${Dsp-16-u8}[sb] */
35279 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexbd.b", 24,
35280 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35282 /* indexbd.b ${Dsp-16-u16}[sb] */
35284 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexbd.b", 32,
35285 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35287 /* indexbd.b ${Dsp-16-s8}[fb] */
35289 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexbd.b", 24,
35290 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35292 /* indexbd.b ${Dsp-16-s16}[fb] */
35294 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexbd.b", 32,
35295 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35297 /* indexbd.b ${Dsp-16-u16} */
35299 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexbd.b", 32,
35300 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35302 /* indexbd.b ${Dsp-16-u24} */
35304 M32C_INSN_INDEXBD32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexbd32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexbd.b", 40,
35305 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35307 /* indexb.w $Dst32RnUnprefixedHI */
35309 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "indexb.w", 16,
35310 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35312 /* indexb.w $Dst32AnUnprefixedHI */
35314 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "indexb.w", 16,
35315 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35317 /* indexb.w [$Dst32AnUnprefixed] */
35319 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "indexb.w", 16,
35320 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35322 /* indexb.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35324 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "indexb.w", 24,
35325 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35327 /* indexb.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35329 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "indexb.w", 32,
35330 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35332 /* indexb.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35334 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "indexb.w", 40,
35335 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35337 /* indexb.w ${Dsp-16-u8}[sb] */
35339 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "indexb.w", 24,
35340 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35342 /* indexb.w ${Dsp-16-u16}[sb] */
35344 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "indexb.w", 32,
35345 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35347 /* indexb.w ${Dsp-16-s8}[fb] */
35349 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "indexb.w", 24,
35350 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35352 /* indexb.w ${Dsp-16-s16}[fb] */
35354 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "indexb.w", 32,
35355 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35357 /* indexb.w ${Dsp-16-u16} */
35359 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "indexb.w", 32,
35360 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35362 /* indexb.w ${Dsp-16-u24} */
35364 M32C_INSN_INDEXB32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "indexb32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "indexb.w", 40,
35365 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35367 /* indexb.b $Dst32RnUnprefixedQI */
35369 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "indexb.b", 16,
35370 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35372 /* indexb.b $Dst32AnUnprefixedQI */
35374 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "indexb.b", 16,
35375 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35377 /* indexb.b [$Dst32AnUnprefixed] */
35379 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "indexb.b", 16,
35380 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35382 /* indexb.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35384 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "indexb.b", 24,
35385 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35387 /* indexb.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35389 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "indexb.b", 32,
35390 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35392 /* indexb.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35394 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "indexb.b", 40,
35395 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35397 /* indexb.b ${Dsp-16-u8}[sb] */
35399 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "indexb.b", 24,
35400 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35402 /* indexb.b ${Dsp-16-u16}[sb] */
35404 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "indexb.b", 32,
35405 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35407 /* indexb.b ${Dsp-16-s8}[fb] */
35409 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "indexb.b", 24,
35410 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35412 /* indexb.b ${Dsp-16-s16}[fb] */
35414 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "indexb.b", 32,
35415 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35417 /* indexb.b ${Dsp-16-u16} */
35419 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "indexb.b", 32,
35420 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35422 /* indexb.b ${Dsp-16-u24} */
35424 M32C_INSN_INDEXB32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "indexb32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "indexb.b", 40,
35425 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35427 /* inc.w $Dst32RnUnprefixedHI */
35429 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "inc.w", 16,
35430 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35432 /* inc.w $Dst32AnUnprefixedHI */
35434 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "inc.w", 16,
35435 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35437 /* inc.w [$Dst32AnUnprefixed] */
35439 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "inc.w", 16,
35440 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35442 /* inc.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35444 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "inc.w", 24,
35445 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35447 /* inc.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35449 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "inc.w", 32,
35450 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35452 /* inc.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35454 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "inc.w", 40,
35455 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35457 /* inc.w ${Dsp-16-u8}[sb] */
35459 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "inc.w", 24,
35460 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35462 /* inc.w ${Dsp-16-u16}[sb] */
35464 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "inc.w", 32,
35465 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35467 /* inc.w ${Dsp-16-s8}[fb] */
35469 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "inc.w", 24,
35470 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35472 /* inc.w ${Dsp-16-s16}[fb] */
35474 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "inc.w", 32,
35475 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35477 /* inc.w ${Dsp-16-u16} */
35479 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "inc.w", 32,
35480 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35482 /* inc.w ${Dsp-16-u24} */
35484 M32C_INSN_INC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "inc32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "inc.w", 40,
35485 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35487 /* inc.b $Dst32RnUnprefixedQI */
35489 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "inc.b", 16,
35490 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35492 /* inc.b $Dst32AnUnprefixedQI */
35494 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "inc.b", 16,
35495 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35497 /* inc.b [$Dst32AnUnprefixed] */
35499 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "inc.b", 16,
35500 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35502 /* inc.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
35504 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "inc.b", 24,
35505 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35507 /* inc.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
35509 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "inc.b", 32,
35510 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35512 /* inc.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
35514 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "inc.b", 40,
35515 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35517 /* inc.b ${Dsp-16-u8}[sb] */
35519 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "inc.b", 24,
35520 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35522 /* inc.b ${Dsp-16-u16}[sb] */
35524 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "inc.b", 32,
35525 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35527 /* inc.b ${Dsp-16-s8}[fb] */
35529 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "inc.b", 24,
35530 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35532 /* inc.b ${Dsp-16-s16}[fb] */
35534 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "inc.b", 32,
35535 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35537 /* inc.b ${Dsp-16-u16} */
35539 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "inc.b", 32,
35540 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35542 /* inc.b ${Dsp-16-u24} */
35544 M32C_INSN_INC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "inc32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "inc.b", 40,
35545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35549 M32C_INSN_INC16_B_DST16_3_S_R0L_DIRECT_QI, "inc16.b-dst16-3-S-R0l-direct-QI", "inc.b", 8,
35550 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
35554 M32C_INSN_INC16_B_DST16_3_S_R0H_DIRECT_QI, "inc16.b-dst16-3-S-R0h-direct-QI", "inc.b", 8,
35555 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
35557 /* inc.b ${Dsp-8-u8}[sb] */
35559 M32C_INSN_INC16_B_DST16_3_S_8_8_SB_RELATIVE_QI, "inc16.b-dst16-3-S-8-8-SB-relative-QI", "inc.b", 16,
35560 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
35562 /* inc.b ${Dsp-8-s8}[fb] */
35564 M32C_INSN_INC16_B_DST16_3_S_8_8_FB_RELATIVE_QI, "inc16.b-dst16-3-S-8-8-FB-relative-QI", "inc.b", 16,
35565 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
35567 /* inc.b ${Dsp-8-u16} */
35569 M32C_INSN_INC16_B_DST16_3_S_8_16_ABSOLUTE_QI, "inc16.b-dst16-3-S-8-16-absolute-QI", "inc.b", 24,
35570 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
35572 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
35574 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 24,
35575 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35577 /* sub.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
35579 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 24,
35580 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35582 /* sub.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
35584 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 24,
35585 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35587 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
35589 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 24,
35590 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35592 /* sub.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
35594 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 24,
35595 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35597 /* sub.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
35599 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 24,
35600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35602 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
35604 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 24,
35605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35607 /* sub.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
35609 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 24,
35610 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35612 /* sub.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
35614 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 24,
35615 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35617 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
35619 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "sub.l", 32,
35620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35622 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
35624 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "sub.l", 32,
35625 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35627 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
35629 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "sub.l", 32,
35630 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35632 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
35634 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "sub.l", 40,
35635 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35637 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
35639 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "sub.l", 40,
35640 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35642 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
35644 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "sub.l", 40,
35645 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35647 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
35649 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "sub.l", 48,
35650 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35652 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
35654 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "sub.l", 48,
35655 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35657 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
35659 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "sub.l", 48,
35660 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35662 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
35664 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "sub.l", 32,
35665 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35667 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
35669 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "sub.l", 32,
35670 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35672 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
35674 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "sub.l", 32,
35675 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35677 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
35679 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "sub.l", 40,
35680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35682 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
35684 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "sub.l", 40,
35685 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35687 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
35689 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "sub.l", 40,
35690 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35692 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
35694 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "sub.l", 32,
35695 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35697 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
35699 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "sub.l", 32,
35700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35702 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
35704 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "sub.l", 32,
35705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35707 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
35709 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "sub.l", 40,
35710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35712 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
35714 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "sub.l", 40,
35715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35717 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
35719 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "sub.l", 40,
35720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35722 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
35724 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "sub.l", 40,
35725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35727 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
35729 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "sub.l", 40,
35730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35732 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
35734 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "sub.l", 40,
35735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35737 /* sub.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
35739 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "sub.l", 48,
35740 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35742 /* sub.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
35744 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "sub.l", 48,
35745 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35747 /* sub.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
35749 M32C_INSN_SUB32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "sub.l", 48,
35750 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35752 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
35754 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 32,
35755 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35757 /* sub.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
35759 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 32,
35760 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35762 /* sub.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
35764 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 32,
35765 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35767 /* sub.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
35769 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 32,
35770 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35772 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
35774 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 32,
35775 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35777 /* sub.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
35779 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 32,
35780 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35782 /* sub.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
35784 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 32,
35785 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35787 /* sub.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
35789 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 32,
35790 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35792 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
35794 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 32,
35795 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35797 /* sub.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
35799 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 32,
35800 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35802 /* sub.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
35804 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 32,
35805 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35807 /* sub.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
35809 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 32,
35810 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35812 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
35814 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "sub.l", 40,
35815 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35817 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
35819 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "sub.l", 40,
35820 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35822 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
35824 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "sub.l", 40,
35825 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35827 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
35829 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "sub.l", 40,
35830 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35832 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
35834 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "sub.l", 48,
35835 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35837 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
35839 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "sub.l", 48,
35840 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35842 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
35844 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "sub.l", 48,
35845 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35847 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
35849 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "sub.l", 48,
35850 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35852 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
35854 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "sub.l", 56,
35855 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35857 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
35859 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "sub.l", 56,
35860 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35862 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
35864 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "sub.l", 56,
35865 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35867 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
35869 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "sub.l", 56,
35870 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35872 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
35874 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "sub.l", 40,
35875 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35877 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
35879 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "sub.l", 40,
35880 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35882 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
35884 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "sub.l", 40,
35885 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35887 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
35889 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "sub.l", 40,
35890 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35892 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
35894 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "sub.l", 48,
35895 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35897 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
35899 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "sub.l", 48,
35900 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35902 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
35904 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "sub.l", 48,
35905 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35907 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
35909 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "sub.l", 48,
35910 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35912 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
35914 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "sub.l", 40,
35915 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35917 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
35919 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "sub.l", 40,
35920 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35922 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
35924 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "sub.l", 40,
35925 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35927 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
35929 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "sub.l", 40,
35930 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35932 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
35934 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "sub.l", 48,
35935 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35937 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
35939 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "sub.l", 48,
35940 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35942 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
35944 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "sub.l", 48,
35945 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35947 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
35949 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "sub.l", 48,
35950 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35952 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
35954 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "sub.l", 48,
35955 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35957 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
35959 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "sub.l", 48,
35960 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35962 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
35964 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "sub.l", 48,
35965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35967 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-u16} */
35969 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "sub.l", 48,
35970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35972 /* sub.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
35974 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "sub.l", 56,
35975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35977 /* sub.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
35979 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "sub.l", 56,
35980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35982 /* sub.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
35984 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "sub.l", 56,
35985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35987 /* sub.l${G} ${Dsp-16-u16},${Dsp-32-u24} */
35989 M32C_INSN_SUB32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "sub.l", 56,
35990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35992 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
35994 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 40,
35995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
35997 /* sub.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
35999 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 40,
36000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36002 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
36004 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 40,
36005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36007 /* sub.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
36009 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 40,
36010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36012 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
36014 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 40,
36015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36017 /* sub.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
36019 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 40,
36020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36022 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
36024 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "sub.l", 48,
36025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36027 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
36029 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "sub.l", 48,
36030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36032 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
36034 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "sub.l", 56,
36035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36037 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
36039 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "sub.l", 56,
36040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36042 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
36044 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "sub.l", 64,
36045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36047 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
36049 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "sub.l", 64,
36050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36052 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
36054 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "sub.l", 48,
36055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36057 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
36059 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "sub.l", 48,
36060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36062 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
36064 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "sub.l", 56,
36065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36067 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
36069 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "sub.l", 56,
36070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36072 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
36074 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "sub.l", 48,
36075 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36077 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
36079 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "sub.l", 48,
36080 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36082 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
36084 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "sub.l", 56,
36085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36087 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
36089 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "sub.l", 56,
36090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36092 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
36094 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "sub.l", 56,
36095 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36097 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-u16} */
36099 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "sub.l", 56,
36100 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36102 /* sub.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
36104 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "sub.l", 64,
36105 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36107 /* sub.l${G} ${Dsp-16-u24},${Dsp-40-u24} */
36109 M32C_INSN_SUB32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "sub.l", 64,
36110 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36112 /* sub.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */
36114 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 16,
36115 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36117 /* sub.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */
36119 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 16,
36120 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36122 /* sub.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
36124 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "sub.l", 16,
36125 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36127 /* sub.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */
36129 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 16,
36130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36132 /* sub.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */
36134 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 16,
36135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36137 /* sub.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
36139 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "sub.l", 16,
36140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36142 /* sub.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */
36144 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 16,
36145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36147 /* sub.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */
36149 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 16,
36150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36152 /* sub.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
36154 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "sub.l", 16,
36155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36157 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
36159 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "sub.l", 24,
36160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36162 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
36164 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "sub.l", 24,
36165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36167 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
36169 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "sub.l", 24,
36170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36172 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
36174 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "sub.l", 32,
36175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36177 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
36179 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "sub.l", 32,
36180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36182 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
36184 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "sub.l", 32,
36185 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36187 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
36189 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "sub.l", 40,
36190 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36192 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
36194 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "sub.l", 40,
36195 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36197 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
36199 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "sub.l", 40,
36200 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36202 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */
36204 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "sub.l", 24,
36205 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36207 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */
36209 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "sub.l", 24,
36210 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36212 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
36214 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "sub.l", 24,
36215 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36217 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */
36219 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "sub.l", 32,
36220 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36222 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */
36224 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "sub.l", 32,
36225 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36227 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
36229 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "sub.l", 32,
36230 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36232 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */
36234 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "sub.l", 24,
36235 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36237 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */
36239 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "sub.l", 24,
36240 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36242 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
36244 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "sub.l", 24,
36245 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36247 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */
36249 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "sub.l", 32,
36250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36252 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */
36254 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "sub.l", 32,
36255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36257 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
36259 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "sub.l", 32,
36260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36262 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */
36264 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "sub.l", 32,
36265 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36267 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */
36269 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "sub.l", 32,
36270 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36272 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
36274 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "sub.l", 32,
36275 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36277 /* sub.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */
36279 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "sub.l", 40,
36280 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36282 /* sub.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */
36284 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "sub.l", 40,
36285 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36287 /* sub.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
36289 M32C_INSN_SUB32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "sub.l", 40,
36290 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36292 /* sub.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
36294 M32C_INSN_SUB32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "sub32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "sub.w", 32,
36295 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36297 /* sub.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
36299 M32C_INSN_SUB32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "sub32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "sub.w", 32,
36300 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36302 /* sub.w${S} #${Imm-24-HI},${Dsp-8-u16} */
36304 M32C_INSN_SUB32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "sub32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "sub.w", 40,
36305 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36307 /* sub.w${S} #${Imm-8-HI},r0 */
36309 M32C_INSN_SUB32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "sub32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "sub.w", 24,
36310 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36312 /* sub.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
36314 M32C_INSN_SUB32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "sub32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "sub.b", 24,
36315 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36317 /* sub.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
36319 M32C_INSN_SUB32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "sub32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "sub.b", 24,
36320 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36322 /* sub.b${S} #${Imm-24-QI},${Dsp-8-u16} */
36324 M32C_INSN_SUB32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "sub32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "sub.b", 32,
36325 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36327 /* sub.b${S} #${Imm-8-QI},r0l */
36329 M32C_INSN_SUB32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "sub32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "sub.b", 16,
36330 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36332 /* sub.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */
36334 M32C_INSN_SUB32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "sub32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "sub.l", 48,
36335 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36337 /* sub.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */
36339 M32C_INSN_SUB32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "sub32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "sub.l", 48,
36340 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36342 /* sub.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */
36344 M32C_INSN_SUB32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "sub32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "sub.l", 48,
36345 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36347 /* sub.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
36349 M32C_INSN_SUB32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "sub.l", 56,
36350 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36352 /* sub.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */
36354 M32C_INSN_SUB32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "sub.l", 56,
36355 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36357 /* sub.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */
36359 M32C_INSN_SUB32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "sub.l", 56,
36360 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36362 /* sub.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
36364 M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "sub.l", 64,
36365 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36367 /* sub.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */
36369 M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "sub.l", 64,
36370 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36372 /* sub.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */
36374 M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "sub.l", 64,
36375 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36377 /* sub.l${G} #${Imm-32-SI},${Dsp-16-u16} */
36379 M32C_INSN_SUB32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "sub32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "sub.l", 64,
36380 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36382 /* sub.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
36384 M32C_INSN_SUB32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "sub32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "sub.l", 72,
36385 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36387 /* sub.l${G} #${Imm-40-SI},${Dsp-16-u24} */
36389 M32C_INSN_SUB32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "sub32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "sub.l", 72,
36390 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36392 /* sub.b${S} ${SrcDst16-r0l-r0h-S-normal} */
36394 M32C_INSN_SUB16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, "sub16.b.S-r0l-r0h-srcdst16-r0l-r0h-S-derived", "sub.b", 8,
36395 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
36397 /* sub.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
36399 M32C_INSN_SUB16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, "sub16.b.S-src2-src16-2-S-8-SB-relative-QI", "sub.b", 16,
36400 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
36402 /* sub.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
36404 M32C_INSN_SUB16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, "sub16.b.S-src2-src16-2-S-8-FB-relative-QI", "sub.b", 16,
36405 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
36407 /* sub.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
36409 M32C_INSN_SUB16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, "sub16.b.S-src2-src16-2-S-16-absolute-QI", "sub.b", 24,
36410 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
36412 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
36414 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 24,
36415 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36417 /* sub.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
36419 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 24,
36420 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36422 /* sub.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
36424 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 24,
36425 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36427 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
36429 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 24,
36430 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36432 /* sub.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
36434 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 24,
36435 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36437 /* sub.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
36439 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 24,
36440 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36442 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
36444 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 24,
36445 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36447 /* sub.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
36449 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 24,
36450 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36452 /* sub.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
36454 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 24,
36455 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36457 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
36459 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "sub.w", 32,
36460 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36462 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
36464 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "sub.w", 32,
36465 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36467 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
36469 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "sub.w", 32,
36470 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36472 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
36474 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "sub.w", 40,
36475 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36477 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
36479 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "sub.w", 40,
36480 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36482 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
36484 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "sub.w", 40,
36485 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36487 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
36489 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "sub.w", 48,
36490 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36492 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
36494 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "sub.w", 48,
36495 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36497 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
36499 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "sub.w", 48,
36500 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36502 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
36504 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "sub.w", 32,
36505 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36507 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
36509 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "sub.w", 32,
36510 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36512 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
36514 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "sub.w", 32,
36515 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36517 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
36519 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "sub.w", 40,
36520 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36522 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
36524 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "sub.w", 40,
36525 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36527 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
36529 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "sub.w", 40,
36530 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36532 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
36534 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "sub.w", 32,
36535 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36537 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
36539 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "sub.w", 32,
36540 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36542 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
36544 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "sub.w", 32,
36545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36547 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
36549 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "sub.w", 40,
36550 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36552 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
36554 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "sub.w", 40,
36555 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36557 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
36559 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "sub.w", 40,
36560 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36562 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
36564 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "sub.w", 40,
36565 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36567 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
36569 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "sub.w", 40,
36570 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36572 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
36574 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "sub.w", 40,
36575 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36577 /* sub.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
36579 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "sub.w", 48,
36580 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36582 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
36584 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "sub.w", 48,
36585 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36587 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
36589 M32C_INSN_SUB32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "sub.w", 48,
36590 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36592 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
36594 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 32,
36595 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36597 /* sub.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
36599 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 32,
36600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36602 /* sub.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
36604 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 32,
36605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36607 /* sub.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
36609 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 32,
36610 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36612 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
36614 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 32,
36615 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36617 /* sub.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
36619 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 32,
36620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36622 /* sub.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
36624 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 32,
36625 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36627 /* sub.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
36629 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 32,
36630 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36632 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
36634 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 32,
36635 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36637 /* sub.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
36639 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 32,
36640 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36642 /* sub.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
36644 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 32,
36645 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36647 /* sub.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
36649 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 32,
36650 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36652 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
36654 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "sub.w", 40,
36655 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36657 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
36659 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "sub.w", 40,
36660 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36662 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
36664 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "sub.w", 40,
36665 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36667 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
36669 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "sub.w", 40,
36670 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36672 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
36674 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "sub.w", 48,
36675 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36677 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
36679 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "sub.w", 48,
36680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36682 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
36684 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "sub.w", 48,
36685 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36687 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
36689 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "sub.w", 48,
36690 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36692 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
36694 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "sub.w", 56,
36695 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36697 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
36699 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "sub.w", 56,
36700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36702 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
36704 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "sub.w", 56,
36705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36707 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
36709 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "sub.w", 56,
36710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36712 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
36714 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "sub.w", 40,
36715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36717 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
36719 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "sub.w", 40,
36720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36722 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
36724 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "sub.w", 40,
36725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36727 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
36729 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "sub.w", 40,
36730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36732 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
36734 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "sub.w", 48,
36735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36737 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
36739 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "sub.w", 48,
36740 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36742 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
36744 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "sub.w", 48,
36745 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36747 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
36749 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "sub.w", 48,
36750 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36752 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
36754 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "sub.w", 40,
36755 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36757 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
36759 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "sub.w", 40,
36760 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36762 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
36764 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "sub.w", 40,
36765 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36767 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
36769 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "sub.w", 40,
36770 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36772 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
36774 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "sub.w", 48,
36775 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36777 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
36779 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "sub.w", 48,
36780 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36782 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
36784 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "sub.w", 48,
36785 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36787 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
36789 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "sub.w", 48,
36790 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36792 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
36794 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "sub.w", 48,
36795 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36797 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
36799 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "sub.w", 48,
36800 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36802 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
36804 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "sub.w", 48,
36805 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36807 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
36809 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "sub.w", 48,
36810 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36812 /* sub.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
36814 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "sub.w", 56,
36815 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36817 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
36819 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "sub.w", 56,
36820 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36822 /* sub.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
36824 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "sub.w", 56,
36825 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36827 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
36829 M32C_INSN_SUB32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "sub.w", 56,
36830 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36832 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
36834 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 40,
36835 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36837 /* sub.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
36839 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 40,
36840 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36842 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
36844 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 40,
36845 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36847 /* sub.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
36849 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 40,
36850 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36852 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
36854 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 40,
36855 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36857 /* sub.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
36859 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 40,
36860 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36862 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
36864 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "sub.w", 48,
36865 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36867 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
36869 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "sub.w", 48,
36870 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36872 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
36874 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "sub.w", 56,
36875 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36877 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
36879 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "sub.w", 56,
36880 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36882 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
36884 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "sub.w", 64,
36885 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36887 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
36889 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "sub.w", 64,
36890 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36892 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
36894 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "sub.w", 48,
36895 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36897 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
36899 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "sub.w", 48,
36900 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36902 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
36904 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "sub.w", 56,
36905 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36907 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
36909 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "sub.w", 56,
36910 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36912 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
36914 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "sub.w", 48,
36915 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36917 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
36919 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "sub.w", 48,
36920 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36922 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
36924 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "sub.w", 56,
36925 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36927 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
36929 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "sub.w", 56,
36930 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36932 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
36934 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "sub.w", 56,
36935 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36937 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
36939 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "sub.w", 56,
36940 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36942 /* sub.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
36944 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "sub.w", 64,
36945 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36947 /* sub.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
36949 M32C_INSN_SUB32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "sub.w", 64,
36950 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36952 /* sub.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
36954 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 16,
36955 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36957 /* sub.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
36959 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 16,
36960 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36962 /* sub.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
36964 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "sub.w", 16,
36965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36967 /* sub.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
36969 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 16,
36970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36972 /* sub.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
36974 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 16,
36975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36977 /* sub.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
36979 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "sub.w", 16,
36980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36982 /* sub.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
36984 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 16,
36985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36987 /* sub.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
36989 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 16,
36990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36992 /* sub.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
36994 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "sub.w", 16,
36995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
36997 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
36999 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "sub.w", 24,
37000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37002 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
37004 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "sub.w", 24,
37005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37007 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
37009 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "sub.w", 24,
37010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37012 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
37014 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "sub.w", 32,
37015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37017 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
37019 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "sub.w", 32,
37020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37022 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
37024 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "sub.w", 32,
37025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37027 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
37029 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "sub.w", 40,
37030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37032 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
37034 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "sub.w", 40,
37035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37037 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
37039 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "sub.w", 40,
37040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37042 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
37044 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "sub.w", 24,
37045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37047 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
37049 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "sub.w", 24,
37050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37052 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
37054 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "sub.w", 24,
37055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37057 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
37059 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "sub.w", 32,
37060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37062 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
37064 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "sub.w", 32,
37065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37067 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
37069 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "sub.w", 32,
37070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37072 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
37074 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "sub.w", 24,
37075 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37077 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
37079 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "sub.w", 24,
37080 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37082 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
37084 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "sub.w", 24,
37085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37087 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
37089 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "sub.w", 32,
37090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37092 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
37094 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "sub.w", 32,
37095 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37097 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
37099 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "sub.w", 32,
37100 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37102 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
37104 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "sub.w", 32,
37105 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37107 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
37109 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "sub.w", 32,
37110 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37112 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
37114 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "sub.w", 32,
37115 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37117 /* sub.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
37119 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "sub.w", 40,
37120 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37122 /* sub.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
37124 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "sub.w", 40,
37125 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37127 /* sub.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
37129 M32C_INSN_SUB32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "sub.w", 40,
37130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37132 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
37134 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 24,
37135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37137 /* sub.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
37139 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 24,
37140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37142 /* sub.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
37144 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 24,
37145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37147 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
37149 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 24,
37150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37152 /* sub.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
37154 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 24,
37155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37157 /* sub.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
37159 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 24,
37160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37162 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
37164 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 24,
37165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37167 /* sub.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
37169 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 24,
37170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37172 /* sub.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
37174 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 24,
37175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37177 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
37179 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "sub.b", 32,
37180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37182 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
37184 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "sub.b", 32,
37185 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37187 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
37189 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "sub.b", 32,
37190 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37192 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
37194 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "sub.b", 40,
37195 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37197 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
37199 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "sub.b", 40,
37200 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37202 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
37204 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "sub.b", 40,
37205 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37207 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
37209 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "sub.b", 48,
37210 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37212 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
37214 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "sub.b", 48,
37215 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37217 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
37219 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "sub.b", 48,
37220 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37222 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
37224 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "sub.b", 32,
37225 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37227 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
37229 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "sub.b", 32,
37230 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37232 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
37234 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "sub.b", 32,
37235 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37237 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
37239 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "sub.b", 40,
37240 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37242 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
37244 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "sub.b", 40,
37245 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37247 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
37249 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "sub.b", 40,
37250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37252 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
37254 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "sub.b", 32,
37255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37257 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
37259 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "sub.b", 32,
37260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37262 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
37264 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "sub.b", 32,
37265 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37267 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
37269 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "sub.b", 40,
37270 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37272 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
37274 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "sub.b", 40,
37275 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37277 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
37279 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "sub.b", 40,
37280 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37282 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
37284 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "sub.b", 40,
37285 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37287 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
37289 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "sub.b", 40,
37290 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37292 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
37294 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "sub.b", 40,
37295 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37297 /* sub.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
37299 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "sub.b", 48,
37300 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37302 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
37304 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "sub.b", 48,
37305 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37307 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
37309 M32C_INSN_SUB32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "sub.b", 48,
37310 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37312 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
37314 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 32,
37315 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37317 /* sub.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
37319 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 32,
37320 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37322 /* sub.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
37324 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 32,
37325 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37327 /* sub.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
37329 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 32,
37330 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37332 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
37334 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 32,
37335 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37337 /* sub.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
37339 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 32,
37340 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37342 /* sub.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
37344 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 32,
37345 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37347 /* sub.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
37349 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 32,
37350 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37352 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
37354 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 32,
37355 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37357 /* sub.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
37359 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 32,
37360 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37362 /* sub.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
37364 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 32,
37365 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37367 /* sub.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
37369 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 32,
37370 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37372 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
37374 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "sub.b", 40,
37375 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37377 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
37379 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "sub.b", 40,
37380 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37382 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
37384 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "sub.b", 40,
37385 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37387 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
37389 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "sub.b", 40,
37390 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37392 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
37394 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "sub.b", 48,
37395 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37397 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
37399 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "sub.b", 48,
37400 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37402 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
37404 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "sub.b", 48,
37405 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37407 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
37409 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "sub.b", 48,
37410 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37412 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
37414 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "sub.b", 56,
37415 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37417 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
37419 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "sub.b", 56,
37420 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37422 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
37424 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "sub.b", 56,
37425 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37427 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
37429 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "sub.b", 56,
37430 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37432 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
37434 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "sub.b", 40,
37435 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37437 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
37439 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "sub.b", 40,
37440 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37442 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
37444 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "sub.b", 40,
37445 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37447 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
37449 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "sub.b", 40,
37450 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37452 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
37454 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "sub.b", 48,
37455 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37457 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
37459 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "sub.b", 48,
37460 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37462 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
37464 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "sub.b", 48,
37465 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37467 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
37469 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "sub.b", 48,
37470 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37472 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
37474 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "sub.b", 40,
37475 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37477 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
37479 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "sub.b", 40,
37480 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37482 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
37484 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "sub.b", 40,
37485 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37487 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
37489 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "sub.b", 40,
37490 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37492 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
37494 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "sub.b", 48,
37495 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37497 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
37499 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "sub.b", 48,
37500 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37502 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
37504 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "sub.b", 48,
37505 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37507 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
37509 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "sub.b", 48,
37510 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37512 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
37514 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "sub.b", 48,
37515 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37517 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
37519 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "sub.b", 48,
37520 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37522 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
37524 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "sub.b", 48,
37525 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37527 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
37529 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "sub.b", 48,
37530 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37532 /* sub.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
37534 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "sub.b", 56,
37535 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37537 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
37539 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "sub.b", 56,
37540 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37542 /* sub.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
37544 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "sub.b", 56,
37545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37547 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
37549 M32C_INSN_SUB32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "sub.b", 56,
37550 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37552 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
37554 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 40,
37555 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37557 /* sub.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
37559 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 40,
37560 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37562 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
37564 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 40,
37565 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37567 /* sub.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
37569 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 40,
37570 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37572 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
37574 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 40,
37575 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37577 /* sub.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
37579 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 40,
37580 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37582 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
37584 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "sub.b", 48,
37585 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37587 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
37589 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "sub.b", 48,
37590 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37592 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
37594 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "sub.b", 56,
37595 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37597 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
37599 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "sub.b", 56,
37600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37602 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
37604 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "sub.b", 64,
37605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37607 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
37609 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "sub.b", 64,
37610 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37612 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
37614 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "sub.b", 48,
37615 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37617 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
37619 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "sub.b", 48,
37620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37622 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
37624 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "sub.b", 56,
37625 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37627 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
37629 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "sub.b", 56,
37630 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37632 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
37634 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "sub.b", 48,
37635 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37637 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
37639 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "sub.b", 48,
37640 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37642 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
37644 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "sub.b", 56,
37645 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37647 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
37649 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "sub.b", 56,
37650 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37652 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
37654 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "sub.b", 56,
37655 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37657 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
37659 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "sub.b", 56,
37660 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37662 /* sub.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
37664 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "sub.b", 64,
37665 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37667 /* sub.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
37669 M32C_INSN_SUB32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "sub.b", 64,
37670 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37672 /* sub.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
37674 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 16,
37675 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37677 /* sub.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
37679 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 16,
37680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37682 /* sub.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
37684 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "sub.b", 16,
37685 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37687 /* sub.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
37689 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 16,
37690 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37692 /* sub.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
37694 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 16,
37695 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37697 /* sub.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
37699 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "sub.b", 16,
37700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37702 /* sub.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
37704 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 16,
37705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37707 /* sub.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
37709 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 16,
37710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37712 /* sub.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
37714 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "sub.b", 16,
37715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37717 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
37719 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "sub.b", 24,
37720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37722 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
37724 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "sub.b", 24,
37725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37727 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
37729 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "sub.b", 24,
37730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37732 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
37734 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "sub.b", 32,
37735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37737 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
37739 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "sub.b", 32,
37740 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37742 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
37744 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "sub.b", 32,
37745 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37747 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
37749 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "sub.b", 40,
37750 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37752 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
37754 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "sub.b", 40,
37755 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37757 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
37759 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "sub.b", 40,
37760 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37762 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
37764 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "sub.b", 24,
37765 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37767 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
37769 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "sub.b", 24,
37770 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37772 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
37774 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "sub.b", 24,
37775 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37777 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
37779 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "sub.b", 32,
37780 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37782 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
37784 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "sub.b", 32,
37785 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37787 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
37789 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "sub.b", 32,
37790 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37792 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
37794 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "sub.b", 24,
37795 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37797 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
37799 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "sub.b", 24,
37800 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37802 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
37804 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "sub.b", 24,
37805 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37807 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
37809 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "sub.b", 32,
37810 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37812 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
37814 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "sub.b", 32,
37815 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37817 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
37819 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "sub.b", 32,
37820 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37822 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
37824 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "sub.b", 32,
37825 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37827 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
37829 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "sub.b", 32,
37830 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37832 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
37834 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "sub.b", 32,
37835 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37837 /* sub.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
37839 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "sub.b", 40,
37840 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37842 /* sub.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
37844 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "sub.b", 40,
37845 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37847 /* sub.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
37849 M32C_INSN_SUB32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "sub.b", 40,
37850 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
37852 /* sub.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
37854 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "sub.w", 24,
37855 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
37857 /* sub.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
37859 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "sub.w", 24,
37860 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
37862 /* sub.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
37864 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "sub.w", 24,
37865 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
37867 /* sub.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
37869 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "sub.w", 24,
37870 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
37872 /* sub.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
37874 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "sub.w", 24,
37875 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
37877 /* sub.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
37879 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "sub.w", 24,
37880 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
37882 /* sub.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
37884 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "sub.w", 24,
37885 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
37887 /* sub.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
37889 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "sub.w", 24,
37890 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
37892 /* sub.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
37894 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "sub.w", 24,
37895 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
37897 /* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
37899 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "sub.w", 32,
37900 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
37902 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
37904 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "sub.w", 32,
37905 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
37907 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
37909 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "sub.w", 32,
37910 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
37912 /* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
37914 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "sub.w", 40,
37915 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
37917 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
37919 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "sub.w", 40,
37920 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
37922 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
37924 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "sub.w", 40,
37925 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
37927 /* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
37929 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "sub.w", 32,
37930 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
37932 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
37934 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "sub.w", 32,
37935 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
37937 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
37939 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "sub.w", 32,
37940 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
37942 /* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
37944 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "sub.w", 40,
37945 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
37947 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
37949 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "sub.w", 40,
37950 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
37952 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
37954 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "sub.w", 40,
37955 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
37957 /* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
37959 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "sub.w", 32,
37960 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
37962 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
37964 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "sub.w", 32,
37965 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
37967 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
37969 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "sub.w", 32,
37970 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
37972 /* sub.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
37974 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sub16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "sub.w", 40,
37975 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
37977 /* sub.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
37979 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sub16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "sub.w", 40,
37980 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
37982 /* sub.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
37984 M32C_INSN_SUB16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "sub16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "sub.w", 40,
37985 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
37987 /* sub.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
37989 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "sub.w", 32,
37990 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
37992 /* sub.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
37994 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "sub.w", 32,
37995 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
37997 /* sub.w${G} ${Dsp-16-u16},$Dst16RnHI */
37999 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "sub.w", 32,
38000 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38002 /* sub.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
38004 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "sub.w", 32,
38005 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38007 /* sub.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
38009 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "sub.w", 32,
38010 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38012 /* sub.w${G} ${Dsp-16-u16},$Dst16AnHI */
38014 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "sub.w", 32,
38015 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38017 /* sub.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
38019 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "sub.w", 32,
38020 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38022 /* sub.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
38024 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "sub.w", 32,
38025 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38027 /* sub.w${G} ${Dsp-16-u16},[$Dst16An] */
38029 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "sub.w", 32,
38030 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38032 /* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
38034 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "sub.w", 40,
38035 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38037 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
38039 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "sub.w", 40,
38040 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38042 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
38044 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "sub.w", 40,
38045 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38047 /* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
38049 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "sub.w", 48,
38050 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38052 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
38054 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "sub.w", 48,
38055 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38057 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
38059 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "sub.w", 48,
38060 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38062 /* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
38064 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "sub.w", 40,
38065 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38067 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
38069 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "sub.w", 40,
38070 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38072 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
38074 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "sub.w", 40,
38075 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38077 /* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
38079 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "sub.w", 48,
38080 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38082 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
38084 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "sub.w", 48,
38085 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38087 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
38089 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "sub.w", 48,
38090 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38092 /* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
38094 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "sub.w", 40,
38095 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38097 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
38099 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "sub.w", 40,
38100 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38102 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
38104 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "sub.w", 40,
38105 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38107 /* sub.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
38109 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "sub16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "sub.w", 48,
38110 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38112 /* sub.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
38114 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "sub16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "sub.w", 48,
38115 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38117 /* sub.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
38119 M32C_INSN_SUB16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "sub16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "sub.w", 48,
38120 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38122 /* sub.w${G} $Src16RnHI,$Dst16RnHI */
38124 M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "sub.w", 16,
38125 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38127 /* sub.w${G} $Src16AnHI,$Dst16RnHI */
38129 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "sub.w", 16,
38130 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38132 /* sub.w${G} [$Src16An],$Dst16RnHI */
38134 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "sub.w", 16,
38135 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38137 /* sub.w${G} $Src16RnHI,$Dst16AnHI */
38139 M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "sub.w", 16,
38140 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38142 /* sub.w${G} $Src16AnHI,$Dst16AnHI */
38144 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "sub.w", 16,
38145 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38147 /* sub.w${G} [$Src16An],$Dst16AnHI */
38149 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "sub.w", 16,
38150 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38152 /* sub.w${G} $Src16RnHI,[$Dst16An] */
38154 M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "sub.w", 16,
38155 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38157 /* sub.w${G} $Src16AnHI,[$Dst16An] */
38159 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "sub.w", 16,
38160 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38162 /* sub.w${G} [$Src16An],[$Dst16An] */
38164 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "sub.w", 16,
38165 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38167 /* sub.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
38169 M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "sub.w", 24,
38170 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38172 /* sub.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
38174 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "sub.w", 24,
38175 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38177 /* sub.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
38179 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "sub.w", 24,
38180 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38182 /* sub.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
38184 M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "sub.w", 32,
38185 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38187 /* sub.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
38189 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "sub.w", 32,
38190 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38192 /* sub.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
38194 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "sub.w", 32,
38195 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38197 /* sub.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
38199 M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "sub.w", 24,
38200 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38202 /* sub.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
38204 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "sub.w", 24,
38205 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38207 /* sub.w${G} [$Src16An],${Dsp-16-u8}[sb] */
38209 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "sub.w", 24,
38210 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38212 /* sub.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
38214 M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "sub.w", 32,
38215 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38217 /* sub.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
38219 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "sub.w", 32,
38220 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38222 /* sub.w${G} [$Src16An],${Dsp-16-u16}[sb] */
38224 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "sub.w", 32,
38225 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38227 /* sub.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
38229 M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "sub.w", 24,
38230 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38232 /* sub.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
38234 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "sub.w", 24,
38235 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38237 /* sub.w${G} [$Src16An],${Dsp-16-s8}[fb] */
38239 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "sub.w", 24,
38240 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38242 /* sub.w${G} $Src16RnHI,${Dsp-16-u16} */
38244 M32C_INSN_SUB16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sub16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "sub.w", 32,
38245 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38247 /* sub.w${G} $Src16AnHI,${Dsp-16-u16} */
38249 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sub16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "sub.w", 32,
38250 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38252 /* sub.w${G} [$Src16An],${Dsp-16-u16} */
38254 M32C_INSN_SUB16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "sub16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "sub.w", 32,
38255 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38257 /* sub.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
38259 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "sub.b", 24,
38260 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38262 /* sub.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
38264 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "sub.b", 24,
38265 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38267 /* sub.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
38269 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "sub.b", 24,
38270 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38272 /* sub.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
38274 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "sub.b", 24,
38275 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38277 /* sub.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
38279 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "sub.b", 24,
38280 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38282 /* sub.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
38284 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "sub.b", 24,
38285 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38287 /* sub.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
38289 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "sub.b", 24,
38290 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38292 /* sub.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
38294 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "sub.b", 24,
38295 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38297 /* sub.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
38299 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "sub.b", 24,
38300 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38302 /* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
38304 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "sub.b", 32,
38305 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38307 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
38309 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "sub.b", 32,
38310 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38312 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
38314 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "sub.b", 32,
38315 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38317 /* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
38319 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "sub.b", 40,
38320 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38322 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
38324 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "sub.b", 40,
38325 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38327 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
38329 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "sub.b", 40,
38330 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38332 /* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
38334 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "sub.b", 32,
38335 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38337 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
38339 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "sub.b", 32,
38340 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38342 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
38344 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "sub.b", 32,
38345 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38347 /* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
38349 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "sub.b", 40,
38350 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38352 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
38354 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "sub.b", 40,
38355 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38357 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
38359 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "sub.b", 40,
38360 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38362 /* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
38364 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "sub.b", 32,
38365 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38367 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
38369 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "sub.b", 32,
38370 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38372 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
38374 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "sub.b", 32,
38375 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38377 /* sub.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
38379 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sub16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "sub.b", 40,
38380 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38382 /* sub.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
38384 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sub16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "sub.b", 40,
38385 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38387 /* sub.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
38389 M32C_INSN_SUB16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "sub16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "sub.b", 40,
38390 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38392 /* sub.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
38394 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "sub.b", 32,
38395 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38397 /* sub.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
38399 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "sub.b", 32,
38400 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38402 /* sub.b${G} ${Dsp-16-u16},$Dst16RnQI */
38404 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "sub.b", 32,
38405 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38407 /* sub.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
38409 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "sub.b", 32,
38410 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38412 /* sub.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
38414 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "sub.b", 32,
38415 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38417 /* sub.b${G} ${Dsp-16-u16},$Dst16AnQI */
38419 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "sub.b", 32,
38420 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38422 /* sub.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
38424 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "sub.b", 32,
38425 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38427 /* sub.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
38429 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "sub.b", 32,
38430 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38432 /* sub.b${G} ${Dsp-16-u16},[$Dst16An] */
38434 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "sub.b", 32,
38435 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38437 /* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
38439 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "sub.b", 40,
38440 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38442 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
38444 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "sub.b", 40,
38445 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38447 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
38449 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "sub.b", 40,
38450 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38452 /* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
38454 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "sub.b", 48,
38455 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38457 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
38459 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "sub.b", 48,
38460 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38462 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
38464 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "sub.b", 48,
38465 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38467 /* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
38469 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "sub.b", 40,
38470 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38472 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
38474 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "sub.b", 40,
38475 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38477 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
38479 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "sub.b", 40,
38480 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38482 /* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
38484 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "sub.b", 48,
38485 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38487 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
38489 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "sub.b", 48,
38490 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38492 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
38494 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "sub.b", 48,
38495 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38497 /* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
38499 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "sub.b", 40,
38500 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38502 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
38504 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "sub.b", 40,
38505 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38507 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
38509 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "sub.b", 40,
38510 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38512 /* sub.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
38514 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "sub16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "sub.b", 48,
38515 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38517 /* sub.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
38519 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "sub16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "sub.b", 48,
38520 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38522 /* sub.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
38524 M32C_INSN_SUB16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "sub16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "sub.b", 48,
38525 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38527 /* sub.b${G} $Src16RnQI,$Dst16RnQI */
38529 M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "sub.b", 16,
38530 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38532 /* sub.b${G} $Src16AnQI,$Dst16RnQI */
38534 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "sub.b", 16,
38535 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38537 /* sub.b${G} [$Src16An],$Dst16RnQI */
38539 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "sub.b", 16,
38540 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38542 /* sub.b${G} $Src16RnQI,$Dst16AnQI */
38544 M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "sub.b", 16,
38545 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38547 /* sub.b${G} $Src16AnQI,$Dst16AnQI */
38549 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "sub.b", 16,
38550 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38552 /* sub.b${G} [$Src16An],$Dst16AnQI */
38554 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "sub.b", 16,
38555 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38557 /* sub.b${G} $Src16RnQI,[$Dst16An] */
38559 M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "sub.b", 16,
38560 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38562 /* sub.b${G} $Src16AnQI,[$Dst16An] */
38564 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "sub.b", 16,
38565 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38567 /* sub.b${G} [$Src16An],[$Dst16An] */
38569 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "sub.b", 16,
38570 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38572 /* sub.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
38574 M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "sub.b", 24,
38575 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38577 /* sub.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
38579 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "sub.b", 24,
38580 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38582 /* sub.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
38584 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "sub.b", 24,
38585 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38587 /* sub.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
38589 M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "sub.b", 32,
38590 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38592 /* sub.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
38594 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "sub.b", 32,
38595 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38597 /* sub.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
38599 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "sub.b", 32,
38600 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38602 /* sub.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
38604 M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "sub.b", 24,
38605 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38607 /* sub.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
38609 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "sub.b", 24,
38610 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38612 /* sub.b${G} [$Src16An],${Dsp-16-u8}[sb] */
38614 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "sub.b", 24,
38615 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38617 /* sub.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
38619 M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "sub.b", 32,
38620 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38622 /* sub.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
38624 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "sub.b", 32,
38625 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38627 /* sub.b${G} [$Src16An],${Dsp-16-u16}[sb] */
38629 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "sub.b", 32,
38630 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38632 /* sub.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
38634 M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "sub.b", 24,
38635 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38637 /* sub.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
38639 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "sub.b", 24,
38640 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38642 /* sub.b${G} [$Src16An],${Dsp-16-s8}[fb] */
38644 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "sub.b", 24,
38645 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38647 /* sub.b${G} $Src16RnQI,${Dsp-16-u16} */
38649 M32C_INSN_SUB16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sub16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "sub.b", 32,
38650 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38652 /* sub.b${G} $Src16AnQI,${Dsp-16-u16} */
38654 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sub16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "sub.b", 32,
38655 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38657 /* sub.b${G} [$Src16An],${Dsp-16-u16} */
38659 M32C_INSN_SUB16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "sub16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "sub.b", 32,
38660 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38662 /* sub.b${S} #${Imm-8-QI},r0l */
38664 M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "sub16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "sub.b", 16,
38665 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38667 /* sub.b${S} #${Imm-8-QI},r0h */
38669 M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "sub16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "sub.b", 16,
38670 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38672 /* sub.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
38674 M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "sub16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "sub.b", 24,
38675 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38677 /* sub.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
38679 M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "sub16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "sub.b", 24,
38680 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38682 /* sub.b${S} #${Imm-8-QI},${Dsp-16-u16} */
38684 M32C_INSN_SUB16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "sub16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "sub.b", 32,
38685 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38687 /* sub.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
38689 M32C_INSN_SUB32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "sub32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "sub.w", 32,
38690 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38692 /* sub.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
38694 M32C_INSN_SUB32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "sub32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "sub.w", 32,
38695 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38697 /* sub.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
38699 M32C_INSN_SUB32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "sub32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "sub.w", 32,
38700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38702 /* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
38704 M32C_INSN_SUB32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "sub.w", 40,
38705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38707 /* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
38709 M32C_INSN_SUB32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "sub.w", 40,
38710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38712 /* sub.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
38714 M32C_INSN_SUB32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "sub.w", 40,
38715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38717 /* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
38719 M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "sub.w", 48,
38720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38722 /* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
38724 M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "sub.w", 48,
38725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38727 /* sub.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
38729 M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "sub.w", 48,
38730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38732 /* sub.w${G} #${Imm-32-HI},${Dsp-16-u16} */
38734 M32C_INSN_SUB32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "sub32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "sub.w", 48,
38735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38737 /* sub.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
38739 M32C_INSN_SUB32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "sub32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "sub.w", 56,
38740 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38742 /* sub.w${G} #${Imm-40-HI},${Dsp-16-u24} */
38744 M32C_INSN_SUB32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "sub32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "sub.w", 56,
38745 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38747 /* sub.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
38749 M32C_INSN_SUB32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "sub32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "sub.b", 24,
38750 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38752 /* sub.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
38754 M32C_INSN_SUB32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "sub32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "sub.b", 24,
38755 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38757 /* sub.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
38759 M32C_INSN_SUB32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "sub32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "sub.b", 24,
38760 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38762 /* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
38764 M32C_INSN_SUB32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "sub.b", 32,
38765 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38767 /* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
38769 M32C_INSN_SUB32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "sub.b", 32,
38770 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38772 /* sub.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
38774 M32C_INSN_SUB32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "sub.b", 32,
38775 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38777 /* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
38779 M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "sub.b", 40,
38780 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38782 /* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
38784 M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "sub.b", 40,
38785 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38787 /* sub.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
38789 M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "sub.b", 40,
38790 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38792 /* sub.b${G} #${Imm-32-QI},${Dsp-16-u16} */
38794 M32C_INSN_SUB32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "sub32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "sub.b", 40,
38795 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38797 /* sub.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
38799 M32C_INSN_SUB32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "sub32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "sub.b", 48,
38800 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38802 /* sub.b${G} #${Imm-40-QI},${Dsp-16-u24} */
38804 M32C_INSN_SUB32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "sub32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "sub.b", 48,
38805 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38807 /* sub.w${G} #${Imm-16-HI},$Dst16RnHI */
38809 M32C_INSN_SUB16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "sub16.w-imm-G-basic-dst16-Rn-direct-HI", "sub.w", 32,
38810 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38812 /* sub.w${G} #${Imm-16-HI},$Dst16AnHI */
38814 M32C_INSN_SUB16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "sub16.w-imm-G-basic-dst16-An-direct-HI", "sub.w", 32,
38815 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38817 /* sub.w${G} #${Imm-16-HI},[$Dst16An] */
38819 M32C_INSN_SUB16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "sub16.w-imm-G-basic-dst16-An-indirect-HI", "sub.w", 32,
38820 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38822 /* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
38824 M32C_INSN_SUB16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "sub16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "sub.w", 40,
38825 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38827 /* sub.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
38829 M32C_INSN_SUB16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "sub16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "sub.w", 40,
38830 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38832 /* sub.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
38834 M32C_INSN_SUB16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "sub16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "sub.w", 40,
38835 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38837 /* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
38839 M32C_INSN_SUB16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "sub16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "sub.w", 48,
38840 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38842 /* sub.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
38844 M32C_INSN_SUB16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "sub16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "sub.w", 48,
38845 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38847 /* sub.w${G} #${Imm-32-HI},${Dsp-16-u16} */
38849 M32C_INSN_SUB16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "sub16.w-imm-G-16-16-dst16-16-16-absolute-HI", "sub.w", 48,
38850 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38852 /* sub.b${G} #${Imm-16-QI},$Dst16RnQI */
38854 M32C_INSN_SUB16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "sub16.b-imm-G-basic-dst16-Rn-direct-QI", "sub.b", 24,
38855 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38857 /* sub.b${G} #${Imm-16-QI},$Dst16AnQI */
38859 M32C_INSN_SUB16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "sub16.b-imm-G-basic-dst16-An-direct-QI", "sub.b", 24,
38860 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38862 /* sub.b${G} #${Imm-16-QI},[$Dst16An] */
38864 M32C_INSN_SUB16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "sub16.b-imm-G-basic-dst16-An-indirect-QI", "sub.b", 24,
38865 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38867 /* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
38869 M32C_INSN_SUB16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "sub16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "sub.b", 32,
38870 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38872 /* sub.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
38874 M32C_INSN_SUB16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "sub16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "sub.b", 32,
38875 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38877 /* sub.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
38879 M32C_INSN_SUB16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "sub16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "sub.b", 32,
38880 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38882 /* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
38884 M32C_INSN_SUB16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "sub16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "sub.b", 40,
38885 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38887 /* sub.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
38889 M32C_INSN_SUB16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "sub16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "sub.b", 40,
38890 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38892 /* sub.b${G} #${Imm-32-QI},${Dsp-16-u16} */
38894 M32C_INSN_SUB16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "sub16.b-imm-G-16-16-dst16-16-16-absolute-QI", "sub.b", 40,
38895 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
38897 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
38899 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 32,
38900 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38902 /* dsub.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
38904 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 32,
38905 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38907 /* dsub.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
38909 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 32,
38910 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38912 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
38914 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 32,
38915 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38917 /* dsub.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
38919 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 32,
38920 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38922 /* dsub.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
38924 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 32,
38925 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38927 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
38929 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 32,
38930 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38932 /* dsub.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
38934 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 32,
38935 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38937 /* dsub.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
38939 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 32,
38940 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38942 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
38944 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsub.w", 40,
38945 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38947 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
38949 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsub.w", 40,
38950 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38952 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
38954 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsub.w", 40,
38955 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38957 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
38959 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsub.w", 48,
38960 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38962 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
38964 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsub.w", 48,
38965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38967 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
38969 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsub.w", 48,
38970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38972 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
38974 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsub.w", 56,
38975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38977 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
38979 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsub.w", 56,
38980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38982 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
38984 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsub.w", 56,
38985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38987 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
38989 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsub.w", 40,
38990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38992 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
38994 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsub.w", 40,
38995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
38997 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
38999 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsub.w", 40,
39000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39002 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
39004 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsub.w", 48,
39005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39007 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
39009 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsub.w", 48,
39010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39012 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
39014 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsub.w", 48,
39015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39017 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
39019 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsub.w", 40,
39020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39022 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
39024 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsub.w", 40,
39025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39027 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
39029 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsub.w", 40,
39030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39032 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
39034 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsub.w", 48,
39035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39037 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
39039 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsub.w", 48,
39040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39042 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
39044 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsub.w", 48,
39045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39047 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
39049 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsub.w", 48,
39050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39052 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
39054 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsub.w", 48,
39055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39057 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
39059 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsub.w", 48,
39060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39062 /* dsub.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
39064 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsub.w", 56,
39065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39067 /* dsub.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
39069 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsub.w", 56,
39070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39072 /* dsub.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
39074 M32C_INSN_DSUB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsub.w", 56,
39075 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39077 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
39079 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 40,
39080 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39082 /* dsub.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
39084 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 40,
39085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39087 /* dsub.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
39089 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 40,
39090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39092 /* dsub.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
39094 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 40,
39095 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39097 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
39099 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 40,
39100 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39102 /* dsub.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
39104 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 40,
39105 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39107 /* dsub.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
39109 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 40,
39110 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39112 /* dsub.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
39114 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 40,
39115 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39117 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
39119 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 40,
39120 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39122 /* dsub.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
39124 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 40,
39125 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39127 /* dsub.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
39129 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 40,
39130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39132 /* dsub.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
39134 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 40,
39135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39137 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
39139 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsub.w", 48,
39140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39142 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
39144 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsub.w", 48,
39145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39147 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
39149 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsub.w", 48,
39150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39152 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
39154 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsub.w", 48,
39155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39157 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
39159 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsub.w", 56,
39160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39162 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
39164 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsub.w", 56,
39165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39167 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
39169 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsub.w", 56,
39170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39172 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
39174 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsub.w", 56,
39175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39177 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
39179 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsub.w", 64,
39180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39182 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
39184 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsub.w", 64,
39185 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39187 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
39189 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsub.w", 64,
39190 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39192 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
39194 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsub.w", 64,
39195 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39197 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
39199 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsub.w", 48,
39200 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39202 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
39204 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsub.w", 48,
39205 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39207 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
39209 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsub.w", 48,
39210 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39212 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
39214 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsub.w", 48,
39215 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39217 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
39219 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsub.w", 56,
39220 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39222 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
39224 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsub.w", 56,
39225 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39227 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
39229 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsub.w", 56,
39230 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39232 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
39234 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsub.w", 56,
39235 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39237 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
39239 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsub.w", 48,
39240 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39242 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
39244 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsub.w", 48,
39245 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39247 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
39249 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsub.w", 48,
39250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39252 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
39254 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsub.w", 48,
39255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39257 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
39259 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsub.w", 56,
39260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39262 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
39264 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsub.w", 56,
39265 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39267 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
39269 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsub.w", 56,
39270 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39272 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
39274 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsub.w", 56,
39275 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39277 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
39279 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsub.w", 56,
39280 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39282 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
39284 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsub.w", 56,
39285 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39287 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
39289 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsub.w", 56,
39290 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39292 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
39294 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsub.w", 56,
39295 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39297 /* dsub.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
39299 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsub.w", 64,
39300 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39302 /* dsub.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
39304 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsub.w", 64,
39305 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39307 /* dsub.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
39309 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsub.w", 64,
39310 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39312 /* dsub.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
39314 M32C_INSN_DSUB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsub.w", 64,
39315 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39317 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
39319 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 48,
39320 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39322 /* dsub.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
39324 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 48,
39325 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39327 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
39329 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 48,
39330 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39332 /* dsub.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
39334 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 48,
39335 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39337 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
39339 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 48,
39340 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39342 /* dsub.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
39344 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 48,
39345 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39347 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
39349 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dsub.w", 56,
39350 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39352 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
39354 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dsub.w", 56,
39355 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39357 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
39359 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dsub.w", 64,
39360 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39362 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
39364 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dsub.w", 64,
39365 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39367 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
39369 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dsub.w", 72,
39370 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39372 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
39374 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dsub.w", 72,
39375 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39377 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
39379 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dsub.w", 56,
39380 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39382 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
39384 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dsub.w", 56,
39385 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39387 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
39389 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dsub.w", 64,
39390 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39392 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
39394 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dsub.w", 64,
39395 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39397 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
39399 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dsub.w", 56,
39400 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39402 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
39404 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dsub.w", 56,
39405 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39407 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
39409 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dsub.w", 64,
39410 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39412 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
39414 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dsub.w", 64,
39415 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39417 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
39419 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dsub.w", 64,
39420 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39422 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
39424 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dsub.w", 64,
39425 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39427 /* dsub.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
39429 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dsub.w", 72,
39430 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39432 /* dsub.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
39434 M32C_INSN_DSUB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dsub.w", 72,
39435 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39437 /* dsub.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
39439 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 24,
39440 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39442 /* dsub.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
39444 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 24,
39445 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39447 /* dsub.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
39449 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsub.w", 24,
39450 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39452 /* dsub.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
39454 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 24,
39455 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39457 /* dsub.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
39459 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 24,
39460 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39462 /* dsub.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
39464 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsub.w", 24,
39465 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39467 /* dsub.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
39469 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 24,
39470 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39472 /* dsub.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
39474 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 24,
39475 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39477 /* dsub.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
39479 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsub.w", 24,
39480 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39482 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
39484 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsub.w", 32,
39485 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39487 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
39489 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsub.w", 32,
39490 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39492 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
39494 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsub.w", 32,
39495 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39497 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
39499 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsub.w", 40,
39500 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39502 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
39504 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsub.w", 40,
39505 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39507 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
39509 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsub.w", 40,
39510 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39512 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
39514 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsub.w", 48,
39515 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39517 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
39519 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsub.w", 48,
39520 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39522 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
39524 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsub.w", 48,
39525 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39527 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
39529 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsub.w", 32,
39530 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39532 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
39534 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsub.w", 32,
39535 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39537 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
39539 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsub.w", 32,
39540 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39542 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
39544 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsub.w", 40,
39545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39547 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
39549 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsub.w", 40,
39550 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39552 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
39554 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsub.w", 40,
39555 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39557 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
39559 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsub.w", 32,
39560 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39562 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
39564 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsub.w", 32,
39565 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39567 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
39569 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsub.w", 32,
39570 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39572 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
39574 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsub.w", 40,
39575 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39577 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
39579 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsub.w", 40,
39580 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39582 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
39584 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsub.w", 40,
39585 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39587 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
39589 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsub.w", 40,
39590 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39592 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
39594 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsub.w", 40,
39595 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39597 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
39599 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsub.w", 40,
39600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39602 /* dsub.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
39604 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsub.w", 48,
39605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39607 /* dsub.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
39609 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsub.w", 48,
39610 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39612 /* dsub.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
39614 M32C_INSN_DSUB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsub.w", 48,
39615 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39617 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
39619 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 32,
39620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39622 /* dsub.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
39624 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 32,
39625 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39627 /* dsub.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
39629 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 32,
39630 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39632 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
39634 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 32,
39635 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39637 /* dsub.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
39639 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 32,
39640 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39642 /* dsub.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
39644 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 32,
39645 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39647 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
39649 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 32,
39650 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39652 /* dsub.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
39654 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 32,
39655 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39657 /* dsub.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
39659 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 32,
39660 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39662 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
39664 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsub.b", 40,
39665 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39667 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
39669 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsub.b", 40,
39670 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39672 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
39674 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsub.b", 40,
39675 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39677 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
39679 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsub.b", 48,
39680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39682 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
39684 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsub.b", 48,
39685 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39687 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
39689 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsub.b", 48,
39690 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39692 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
39694 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsub.b", 56,
39695 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39697 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
39699 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsub.b", 56,
39700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39702 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
39704 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsub.b", 56,
39705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39707 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
39709 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsub.b", 40,
39710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39712 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
39714 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsub.b", 40,
39715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39717 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
39719 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsub.b", 40,
39720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39722 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
39724 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsub.b", 48,
39725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39727 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
39729 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsub.b", 48,
39730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39732 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
39734 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsub.b", 48,
39735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39737 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
39739 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsub.b", 40,
39740 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39742 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
39744 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsub.b", 40,
39745 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39747 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
39749 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsub.b", 40,
39750 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39752 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
39754 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsub.b", 48,
39755 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39757 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
39759 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsub.b", 48,
39760 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39762 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
39764 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsub.b", 48,
39765 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39767 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
39769 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsub.b", 48,
39770 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39772 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
39774 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsub.b", 48,
39775 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39777 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
39779 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsub.b", 48,
39780 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39782 /* dsub.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
39784 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsub.b", 56,
39785 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39787 /* dsub.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
39789 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsub.b", 56,
39790 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39792 /* dsub.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
39794 M32C_INSN_DSUB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsub.b", 56,
39795 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39797 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
39799 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 40,
39800 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39802 /* dsub.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
39804 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 40,
39805 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39807 /* dsub.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
39809 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 40,
39810 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39812 /* dsub.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
39814 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 40,
39815 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39817 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
39819 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 40,
39820 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39822 /* dsub.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
39824 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 40,
39825 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39827 /* dsub.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
39829 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 40,
39830 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39832 /* dsub.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
39834 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 40,
39835 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39837 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
39839 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 40,
39840 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39842 /* dsub.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
39844 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 40,
39845 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39847 /* dsub.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
39849 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 40,
39850 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39852 /* dsub.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
39854 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 40,
39855 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39857 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
39859 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsub.b", 48,
39860 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39862 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
39864 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsub.b", 48,
39865 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39867 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
39869 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsub.b", 48,
39870 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39872 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
39874 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsub.b", 48,
39875 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39877 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
39879 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsub.b", 56,
39880 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39882 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
39884 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsub.b", 56,
39885 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39887 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
39889 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsub.b", 56,
39890 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39892 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
39894 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsub.b", 56,
39895 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39897 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
39899 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsub.b", 64,
39900 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39902 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
39904 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsub.b", 64,
39905 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39907 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
39909 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsub.b", 64,
39910 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39912 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
39914 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsub.b", 64,
39915 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39917 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
39919 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsub.b", 48,
39920 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39922 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
39924 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsub.b", 48,
39925 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39927 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
39929 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsub.b", 48,
39930 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39932 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
39934 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsub.b", 48,
39935 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39937 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
39939 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsub.b", 56,
39940 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39942 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
39944 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsub.b", 56,
39945 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39947 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
39949 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsub.b", 56,
39950 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39952 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
39954 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsub.b", 56,
39955 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39957 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
39959 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsub.b", 48,
39960 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39962 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
39964 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsub.b", 48,
39965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39967 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
39969 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsub.b", 48,
39970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39972 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
39974 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsub.b", 48,
39975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39977 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
39979 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsub.b", 56,
39980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39982 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
39984 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsub.b", 56,
39985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39987 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
39989 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsub.b", 56,
39990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39992 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
39994 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsub.b", 56,
39995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
39997 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
39999 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsub.b", 56,
40000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40002 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
40004 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsub.b", 56,
40005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40007 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
40009 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsub.b", 56,
40010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40012 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
40014 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsub.b", 56,
40015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40017 /* dsub.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
40019 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsub.b", 64,
40020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40022 /* dsub.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
40024 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsub.b", 64,
40025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40027 /* dsub.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
40029 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsub.b", 64,
40030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40032 /* dsub.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
40034 M32C_INSN_DSUB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsub.b", 64,
40035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40037 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
40039 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 48,
40040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40042 /* dsub.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
40044 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 48,
40045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40047 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
40049 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 48,
40050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40052 /* dsub.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
40054 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 48,
40055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40057 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
40059 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 48,
40060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40062 /* dsub.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
40064 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 48,
40065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40067 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
40069 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dsub.b", 56,
40070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40072 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
40074 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dsub.b", 56,
40075 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40077 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
40079 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dsub.b", 64,
40080 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40082 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
40084 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dsub.b", 64,
40085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40087 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
40089 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dsub.b", 72,
40090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40092 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
40094 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dsub.b", 72,
40095 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40097 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
40099 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dsub.b", 56,
40100 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40102 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
40104 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dsub.b", 56,
40105 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40107 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
40109 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dsub.b", 64,
40110 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40112 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
40114 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dsub.b", 64,
40115 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40117 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
40119 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dsub.b", 56,
40120 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40122 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
40124 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dsub.b", 56,
40125 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40127 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
40129 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dsub.b", 64,
40130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40132 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
40134 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dsub.b", 64,
40135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40137 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
40139 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dsub.b", 64,
40140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40142 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
40144 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dsub.b", 64,
40145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40147 /* dsub.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
40149 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dsub.b", 72,
40150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40152 /* dsub.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
40154 M32C_INSN_DSUB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dsub.b", 72,
40155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40157 /* dsub.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
40159 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 24,
40160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40162 /* dsub.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
40164 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 24,
40165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40167 /* dsub.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
40169 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsub.b", 24,
40170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40172 /* dsub.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
40174 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 24,
40175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40177 /* dsub.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
40179 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 24,
40180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40182 /* dsub.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
40184 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsub.b", 24,
40185 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40187 /* dsub.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
40189 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 24,
40190 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40192 /* dsub.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
40194 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 24,
40195 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40197 /* dsub.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
40199 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsub.b", 24,
40200 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40202 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
40204 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsub.b", 32,
40205 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40207 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
40209 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsub.b", 32,
40210 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40212 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
40214 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsub.b", 32,
40215 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40217 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
40219 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsub.b", 40,
40220 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40222 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
40224 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsub.b", 40,
40225 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40227 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
40229 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsub.b", 40,
40230 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40232 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
40234 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsub.b", 48,
40235 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40237 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
40239 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsub.b", 48,
40240 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40242 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
40244 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsub.b", 48,
40245 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40247 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
40249 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsub.b", 32,
40250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40252 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
40254 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsub.b", 32,
40255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40257 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
40259 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsub.b", 32,
40260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40262 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
40264 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsub.b", 40,
40265 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40267 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
40269 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsub.b", 40,
40270 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40272 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
40274 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsub.b", 40,
40275 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40277 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
40279 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsub.b", 32,
40280 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40282 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
40284 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsub.b", 32,
40285 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40287 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
40289 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsub.b", 32,
40290 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40292 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
40294 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsub.b", 40,
40295 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40297 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
40299 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsub.b", 40,
40300 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40302 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
40304 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsub.b", 40,
40305 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40307 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
40309 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsub.b", 40,
40310 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40312 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
40314 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsub.b", 40,
40315 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40317 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
40319 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsub.b", 40,
40320 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40322 /* dsub.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
40324 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsub.b", 48,
40325 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40327 /* dsub.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
40329 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsub.b", 48,
40330 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40332 /* dsub.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
40334 M32C_INSN_DSUB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsub.b", 48,
40335 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40337 /* dsub.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
40339 M32C_INSN_DSUB32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "dsub32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "dsub.w", 40,
40340 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40342 /* dsub.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
40344 M32C_INSN_DSUB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "dsub32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "dsub.w", 40,
40345 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40347 /* dsub.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
40349 M32C_INSN_DSUB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "dsub32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "dsub.w", 40,
40350 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40352 /* dsub.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
40354 M32C_INSN_DSUB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "dsub.w", 48,
40355 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40357 /* dsub.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
40359 M32C_INSN_DSUB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "dsub.w", 48,
40360 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40362 /* dsub.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
40364 M32C_INSN_DSUB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "dsub.w", 48,
40365 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40367 /* dsub.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
40369 M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "dsub.w", 56,
40370 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40372 /* dsub.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
40374 M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "dsub.w", 56,
40375 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40377 /* dsub.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
40379 M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "dsub.w", 56,
40380 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40382 /* dsub.w${X} #${Imm-40-HI},${Dsp-24-u16} */
40384 M32C_INSN_DSUB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsub32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "dsub.w", 56,
40385 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40387 /* dsub.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
40389 M32C_INSN_DSUB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsub32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "dsub.w", 64,
40390 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40392 /* dsub.w${X} #${Imm-48-HI},${Dsp-24-u24} */
40394 M32C_INSN_DSUB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsub32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "dsub.w", 64,
40395 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40397 /* dsub.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
40399 M32C_INSN_DSUB32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "dsub32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "dsub.b", 32,
40400 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40402 /* dsub.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
40404 M32C_INSN_DSUB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "dsub32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "dsub.b", 32,
40405 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40407 /* dsub.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
40409 M32C_INSN_DSUB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "dsub32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "dsub.b", 32,
40410 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40412 /* dsub.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
40414 M32C_INSN_DSUB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "dsub.b", 40,
40415 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40417 /* dsub.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
40419 M32C_INSN_DSUB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "dsub.b", 40,
40420 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40422 /* dsub.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
40424 M32C_INSN_DSUB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "dsub.b", 40,
40425 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40427 /* dsub.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
40429 M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "dsub.b", 48,
40430 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40432 /* dsub.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
40434 M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "dsub.b", 48,
40435 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40437 /* dsub.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
40439 M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "dsub.b", 48,
40440 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40442 /* dsub.b${X} #${Imm-40-QI},${Dsp-24-u16} */
40444 M32C_INSN_DSUB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsub32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "dsub.b", 48,
40445 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40447 /* dsub.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
40449 M32C_INSN_DSUB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsub32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "dsub.b", 56,
40450 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40452 /* dsub.b${X} #${Imm-48-QI},${Dsp-24-u24} */
40454 M32C_INSN_DSUB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsub32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "dsub.b", 56,
40455 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40457 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
40459 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 32,
40460 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40462 /* dsbb.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
40464 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 32,
40465 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40467 /* dsbb.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
40469 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 32,
40470 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40472 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
40474 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 32,
40475 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40477 /* dsbb.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
40479 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 32,
40480 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40482 /* dsbb.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
40484 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 32,
40485 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40487 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
40489 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 32,
40490 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40492 /* dsbb.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
40494 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 32,
40495 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40497 /* dsbb.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
40499 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 32,
40500 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40502 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
40504 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsbb.w", 40,
40505 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40507 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
40509 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsbb.w", 40,
40510 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40512 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
40514 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dsbb.w", 40,
40515 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40517 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
40519 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsbb.w", 48,
40520 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40522 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
40524 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsbb.w", 48,
40525 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40527 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
40529 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dsbb.w", 48,
40530 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40532 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
40534 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsbb.w", 56,
40535 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40537 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
40539 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsbb.w", 56,
40540 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40542 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
40544 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dsbb.w", 56,
40545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40547 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
40549 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsbb.w", 40,
40550 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40552 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
40554 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsbb.w", 40,
40555 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40557 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
40559 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dsbb.w", 40,
40560 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40562 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
40564 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsbb.w", 48,
40565 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40567 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
40569 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsbb.w", 48,
40570 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40572 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
40574 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dsbb.w", 48,
40575 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40577 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
40579 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsbb.w", 40,
40580 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40582 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
40584 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsbb.w", 40,
40585 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40587 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
40589 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dsbb.w", 40,
40590 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40592 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
40594 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsbb.w", 48,
40595 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40597 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
40599 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsbb.w", 48,
40600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40602 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
40604 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dsbb.w", 48,
40605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40607 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
40609 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsbb.w", 48,
40610 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40612 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
40614 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsbb.w", 48,
40615 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40617 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
40619 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dsbb.w", 48,
40620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40622 /* dsbb.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
40624 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsbb.w", 56,
40625 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40627 /* dsbb.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
40629 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsbb.w", 56,
40630 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40632 /* dsbb.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
40634 M32C_INSN_DSBB32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dsbb.w", 56,
40635 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40637 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
40639 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 40,
40640 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40642 /* dsbb.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
40644 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 40,
40645 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40647 /* dsbb.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
40649 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 40,
40650 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40652 /* dsbb.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
40654 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 40,
40655 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40657 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
40659 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 40,
40660 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40662 /* dsbb.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
40664 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 40,
40665 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40667 /* dsbb.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
40669 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 40,
40670 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40672 /* dsbb.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
40674 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 40,
40675 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40677 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
40679 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 40,
40680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40682 /* dsbb.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
40684 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 40,
40685 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40687 /* dsbb.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
40689 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 40,
40690 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40692 /* dsbb.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
40694 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 40,
40695 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40697 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
40699 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsbb.w", 48,
40700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40702 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
40704 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsbb.w", 48,
40705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40707 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
40709 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsbb.w", 48,
40710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40712 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
40714 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dsbb.w", 48,
40715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40717 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
40719 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsbb.w", 56,
40720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40722 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
40724 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsbb.w", 56,
40725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40727 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
40729 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsbb.w", 56,
40730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40732 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
40734 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dsbb.w", 56,
40735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40737 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
40739 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsbb.w", 64,
40740 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40742 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
40744 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsbb.w", 64,
40745 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40747 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
40749 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsbb.w", 64,
40750 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40752 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
40754 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dsbb.w", 64,
40755 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40757 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
40759 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsbb.w", 48,
40760 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40762 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
40764 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsbb.w", 48,
40765 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40767 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
40769 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsbb.w", 48,
40770 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40772 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
40774 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dsbb.w", 48,
40775 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40777 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
40779 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsbb.w", 56,
40780 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40782 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
40784 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsbb.w", 56,
40785 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40787 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
40789 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsbb.w", 56,
40790 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40792 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
40794 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dsbb.w", 56,
40795 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40797 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
40799 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsbb.w", 48,
40800 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40802 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
40804 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsbb.w", 48,
40805 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40807 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
40809 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsbb.w", 48,
40810 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40812 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
40814 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dsbb.w", 48,
40815 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40817 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
40819 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsbb.w", 56,
40820 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40822 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
40824 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsbb.w", 56,
40825 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40827 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
40829 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsbb.w", 56,
40830 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40832 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
40834 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dsbb.w", 56,
40835 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40837 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
40839 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsbb.w", 56,
40840 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40842 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
40844 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsbb.w", 56,
40845 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40847 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
40849 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsbb.w", 56,
40850 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40852 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
40854 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dsbb.w", 56,
40855 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40857 /* dsbb.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
40859 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsbb.w", 64,
40860 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40862 /* dsbb.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
40864 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsbb.w", 64,
40865 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40867 /* dsbb.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
40869 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsbb.w", 64,
40870 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40872 /* dsbb.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
40874 M32C_INSN_DSBB32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dsbb.w", 64,
40875 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40877 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
40879 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 48,
40880 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40882 /* dsbb.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
40884 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 48,
40885 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40887 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
40889 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 48,
40890 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40892 /* dsbb.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
40894 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 48,
40895 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40897 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
40899 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 48,
40900 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40902 /* dsbb.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
40904 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 48,
40905 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40907 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
40909 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dsbb.w", 56,
40910 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40912 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
40914 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dsbb.w", 56,
40915 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40917 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
40919 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dsbb.w", 64,
40920 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40922 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
40924 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dsbb.w", 64,
40925 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40927 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
40929 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dsbb.w", 72,
40930 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40932 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
40934 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dsbb.w", 72,
40935 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40937 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
40939 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dsbb.w", 56,
40940 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40942 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
40944 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dsbb.w", 56,
40945 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40947 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
40949 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dsbb.w", 64,
40950 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40952 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
40954 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dsbb.w", 64,
40955 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40957 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
40959 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dsbb.w", 56,
40960 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40962 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
40964 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dsbb.w", 56,
40965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40967 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
40969 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dsbb.w", 64,
40970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40972 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
40974 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dsbb.w", 64,
40975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40977 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
40979 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dsbb.w", 64,
40980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40982 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
40984 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dsbb.w", 64,
40985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40987 /* dsbb.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
40989 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dsbb.w", 72,
40990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40992 /* dsbb.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
40994 M32C_INSN_DSBB32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dsbb.w", 72,
40995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
40997 /* dsbb.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
40999 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 24,
41000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41002 /* dsbb.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
41004 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 24,
41005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41007 /* dsbb.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
41009 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 24,
41010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41012 /* dsbb.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
41014 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 24,
41015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41017 /* dsbb.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
41019 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 24,
41020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41022 /* dsbb.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
41024 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dsbb.w", 24,
41025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41027 /* dsbb.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
41029 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 24,
41030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41032 /* dsbb.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
41034 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 24,
41035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41037 /* dsbb.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
41039 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dsbb.w", 24,
41040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41042 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
41044 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsbb.w", 32,
41045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41047 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
41049 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsbb.w", 32,
41050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41052 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
41054 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dsbb.w", 32,
41055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41057 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
41059 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsbb.w", 40,
41060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41062 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
41064 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsbb.w", 40,
41065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41067 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
41069 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dsbb.w", 40,
41070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41072 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
41074 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsbb.w", 48,
41075 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41077 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
41079 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsbb.w", 48,
41080 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41082 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
41084 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dsbb.w", 48,
41085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41087 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
41089 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsbb.w", 32,
41090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41092 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
41094 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsbb.w", 32,
41095 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41097 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
41099 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dsbb.w", 32,
41100 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41102 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
41104 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsbb.w", 40,
41105 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41107 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
41109 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsbb.w", 40,
41110 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41112 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
41114 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dsbb.w", 40,
41115 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41117 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
41119 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsbb.w", 32,
41120 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41122 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
41124 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsbb.w", 32,
41125 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41127 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
41129 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dsbb.w", 32,
41130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41132 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
41134 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsbb.w", 40,
41135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41137 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
41139 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsbb.w", 40,
41140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41142 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
41144 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dsbb.w", 40,
41145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41147 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
41149 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsbb.w", 40,
41150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41152 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
41154 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsbb.w", 40,
41155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41157 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
41159 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dsbb.w", 40,
41160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41162 /* dsbb.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
41164 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsbb.w", 48,
41165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41167 /* dsbb.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
41169 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsbb.w", 48,
41170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41172 /* dsbb.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
41174 M32C_INSN_DSBB32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dsbb.w", 48,
41175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41177 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
41179 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 32,
41180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41182 /* dsbb.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
41184 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 32,
41185 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41187 /* dsbb.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
41189 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 32,
41190 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41192 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
41194 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 32,
41195 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41197 /* dsbb.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
41199 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 32,
41200 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41202 /* dsbb.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
41204 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 32,
41205 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41207 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
41209 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 32,
41210 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41212 /* dsbb.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
41214 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 32,
41215 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41217 /* dsbb.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
41219 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 32,
41220 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41222 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
41224 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsbb.b", 40,
41225 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41227 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
41229 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsbb.b", 40,
41230 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41232 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
41234 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dsbb.b", 40,
41235 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41237 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
41239 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsbb.b", 48,
41240 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41242 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
41244 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsbb.b", 48,
41245 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41247 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
41249 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dsbb.b", 48,
41250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41252 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
41254 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsbb.b", 56,
41255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41257 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
41259 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsbb.b", 56,
41260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41262 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
41264 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dsbb.b", 56,
41265 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41267 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
41269 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsbb.b", 40,
41270 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41272 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
41274 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsbb.b", 40,
41275 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41277 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
41279 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dsbb.b", 40,
41280 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41282 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
41284 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsbb.b", 48,
41285 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41287 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
41289 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsbb.b", 48,
41290 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41292 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
41294 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dsbb.b", 48,
41295 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41297 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
41299 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsbb.b", 40,
41300 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41302 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
41304 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsbb.b", 40,
41305 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41307 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
41309 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dsbb.b", 40,
41310 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41312 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
41314 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsbb.b", 48,
41315 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41317 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
41319 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsbb.b", 48,
41320 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41322 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
41324 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dsbb.b", 48,
41325 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41327 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
41329 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsbb.b", 48,
41330 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41332 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
41334 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsbb.b", 48,
41335 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41337 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
41339 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dsbb.b", 48,
41340 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41342 /* dsbb.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
41344 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsbb.b", 56,
41345 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41347 /* dsbb.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
41349 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsbb.b", 56,
41350 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41352 /* dsbb.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
41354 M32C_INSN_DSBB32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dsbb.b", 56,
41355 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41357 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
41359 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 40,
41360 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41362 /* dsbb.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
41364 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 40,
41365 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41367 /* dsbb.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
41369 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 40,
41370 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41372 /* dsbb.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
41374 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 40,
41375 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41377 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
41379 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 40,
41380 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41382 /* dsbb.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
41384 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 40,
41385 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41387 /* dsbb.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
41389 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 40,
41390 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41392 /* dsbb.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
41394 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 40,
41395 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41397 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
41399 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 40,
41400 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41402 /* dsbb.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
41404 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 40,
41405 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41407 /* dsbb.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
41409 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 40,
41410 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41412 /* dsbb.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
41414 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 40,
41415 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41417 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
41419 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsbb.b", 48,
41420 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41422 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
41424 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsbb.b", 48,
41425 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41427 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
41429 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsbb.b", 48,
41430 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41432 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
41434 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dsbb.b", 48,
41435 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41437 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
41439 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsbb.b", 56,
41440 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41442 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
41444 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsbb.b", 56,
41445 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41447 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
41449 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsbb.b", 56,
41450 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41452 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
41454 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dsbb.b", 56,
41455 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41457 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
41459 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsbb.b", 64,
41460 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41462 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
41464 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsbb.b", 64,
41465 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41467 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
41469 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsbb.b", 64,
41470 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41472 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
41474 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dsbb.b", 64,
41475 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41477 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
41479 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsbb.b", 48,
41480 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41482 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
41484 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsbb.b", 48,
41485 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41487 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
41489 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsbb.b", 48,
41490 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41492 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
41494 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dsbb.b", 48,
41495 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41497 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
41499 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsbb.b", 56,
41500 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41502 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
41504 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsbb.b", 56,
41505 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41507 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
41509 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsbb.b", 56,
41510 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41512 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
41514 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dsbb.b", 56,
41515 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41517 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
41519 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsbb.b", 48,
41520 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41522 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
41524 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsbb.b", 48,
41525 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41527 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
41529 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsbb.b", 48,
41530 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41532 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
41534 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dsbb.b", 48,
41535 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41537 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
41539 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsbb.b", 56,
41540 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41542 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
41544 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsbb.b", 56,
41545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41547 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
41549 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsbb.b", 56,
41550 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41552 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
41554 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dsbb.b", 56,
41555 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41557 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
41559 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsbb.b", 56,
41560 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41562 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
41564 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsbb.b", 56,
41565 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41567 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
41569 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsbb.b", 56,
41570 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41572 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
41574 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dsbb.b", 56,
41575 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41577 /* dsbb.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
41579 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsbb.b", 64,
41580 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41582 /* dsbb.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
41584 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsbb.b", 64,
41585 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41587 /* dsbb.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
41589 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsbb.b", 64,
41590 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41592 /* dsbb.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
41594 M32C_INSN_DSBB32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dsbb.b", 64,
41595 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41597 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
41599 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 48,
41600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41602 /* dsbb.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
41604 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 48,
41605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41607 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
41609 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 48,
41610 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41612 /* dsbb.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
41614 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 48,
41615 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41617 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
41619 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 48,
41620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41622 /* dsbb.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
41624 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 48,
41625 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41627 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
41629 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dsbb.b", 56,
41630 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41632 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
41634 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dsbb.b", 56,
41635 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41637 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
41639 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dsbb.b", 64,
41640 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41642 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
41644 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dsbb.b", 64,
41645 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41647 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
41649 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dsbb.b", 72,
41650 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41652 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
41654 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dsbb.b", 72,
41655 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41657 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
41659 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dsbb.b", 56,
41660 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41662 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
41664 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dsbb.b", 56,
41665 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41667 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
41669 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dsbb.b", 64,
41670 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41672 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
41674 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dsbb.b", 64,
41675 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41677 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
41679 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dsbb.b", 56,
41680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41682 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
41684 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dsbb.b", 56,
41685 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41687 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
41689 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dsbb.b", 64,
41690 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41692 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
41694 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dsbb.b", 64,
41695 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41697 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
41699 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dsbb.b", 64,
41700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41702 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
41704 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dsbb.b", 64,
41705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41707 /* dsbb.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
41709 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dsbb.b", 72,
41710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41712 /* dsbb.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
41714 M32C_INSN_DSBB32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dsbb.b", 72,
41715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41717 /* dsbb.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
41719 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 24,
41720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41722 /* dsbb.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
41724 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 24,
41725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41727 /* dsbb.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
41729 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 24,
41730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41732 /* dsbb.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
41734 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 24,
41735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41737 /* dsbb.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
41739 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 24,
41740 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41742 /* dsbb.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
41744 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dsbb.b", 24,
41745 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41747 /* dsbb.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
41749 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 24,
41750 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41752 /* dsbb.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
41754 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 24,
41755 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41757 /* dsbb.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
41759 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dsbb.b", 24,
41760 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41762 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
41764 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsbb.b", 32,
41765 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41767 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
41769 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsbb.b", 32,
41770 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41772 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
41774 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dsbb.b", 32,
41775 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41777 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
41779 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsbb.b", 40,
41780 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41782 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
41784 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsbb.b", 40,
41785 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41787 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
41789 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dsbb.b", 40,
41790 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41792 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
41794 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsbb.b", 48,
41795 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41797 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
41799 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsbb.b", 48,
41800 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41802 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
41804 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dsbb.b", 48,
41805 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41807 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
41809 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsbb.b", 32,
41810 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41812 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
41814 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsbb.b", 32,
41815 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41817 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
41819 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dsbb.b", 32,
41820 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41822 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
41824 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsbb.b", 40,
41825 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41827 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
41829 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsbb.b", 40,
41830 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41832 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
41834 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dsbb.b", 40,
41835 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41837 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
41839 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsbb.b", 32,
41840 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41842 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
41844 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsbb.b", 32,
41845 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41847 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
41849 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dsbb.b", 32,
41850 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41852 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
41854 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsbb.b", 40,
41855 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41857 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
41859 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsbb.b", 40,
41860 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41862 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
41864 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dsbb.b", 40,
41865 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41867 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
41869 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsbb.b", 40,
41870 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41872 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
41874 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsbb.b", 40,
41875 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41877 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
41879 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dsbb.b", 40,
41880 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41882 /* dsbb.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
41884 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsbb.b", 48,
41885 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41887 /* dsbb.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
41889 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsbb.b", 48,
41890 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41892 /* dsbb.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
41894 M32C_INSN_DSBB32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dsbb.b", 48,
41895 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41897 /* dsbb.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
41899 M32C_INSN_DSBB32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "dsbb32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "dsbb.w", 40,
41900 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41902 /* dsbb.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
41904 M32C_INSN_DSBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "dsbb32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "dsbb.w", 40,
41905 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41907 /* dsbb.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
41909 M32C_INSN_DSBB32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "dsbb32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "dsbb.w", 40,
41910 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41912 /* dsbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
41914 M32C_INSN_DSBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "dsbb.w", 48,
41915 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41917 /* dsbb.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
41919 M32C_INSN_DSBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "dsbb.w", 48,
41920 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41922 /* dsbb.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
41924 M32C_INSN_DSBB32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "dsbb.w", 48,
41925 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41927 /* dsbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
41929 M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "dsbb.w", 56,
41930 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41932 /* dsbb.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
41934 M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "dsbb.w", 56,
41935 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41937 /* dsbb.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
41939 M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "dsbb.w", 56,
41940 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41942 /* dsbb.w${X} #${Imm-40-HI},${Dsp-24-u16} */
41944 M32C_INSN_DSBB32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dsbb32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "dsbb.w", 56,
41945 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41947 /* dsbb.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
41949 M32C_INSN_DSBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dsbb32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "dsbb.w", 64,
41950 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41952 /* dsbb.w${X} #${Imm-48-HI},${Dsp-24-u24} */
41954 M32C_INSN_DSBB32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dsbb32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "dsbb.w", 64,
41955 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41957 /* dsbb.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
41959 M32C_INSN_DSBB32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "dsbb32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "dsbb.b", 32,
41960 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41962 /* dsbb.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
41964 M32C_INSN_DSBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "dsbb32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "dsbb.b", 32,
41965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41967 /* dsbb.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
41969 M32C_INSN_DSBB32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "dsbb32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "dsbb.b", 32,
41970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41972 /* dsbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
41974 M32C_INSN_DSBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "dsbb.b", 40,
41975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41977 /* dsbb.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
41979 M32C_INSN_DSBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "dsbb.b", 40,
41980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41982 /* dsbb.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
41984 M32C_INSN_DSBB32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "dsbb.b", 40,
41985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41987 /* dsbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
41989 M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "dsbb.b", 48,
41990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41992 /* dsbb.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
41994 M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "dsbb.b", 48,
41995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
41997 /* dsbb.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
41999 M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "dsbb.b", 48,
42000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42002 /* dsbb.b${X} #${Imm-40-QI},${Dsp-24-u16} */
42004 M32C_INSN_DSBB32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dsbb32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "dsbb.b", 48,
42005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42007 /* dsbb.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
42009 M32C_INSN_DSBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dsbb32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "dsbb.b", 56,
42010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42012 /* dsbb.b${X} #${Imm-48-QI},${Dsp-24-u24} */
42014 M32C_INSN_DSBB32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dsbb32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "dsbb.b", 56,
42015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42017 /* divx.l $Dst32RnPrefixedSI */
42019 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_RN_DIRECT_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-Rn-direct-Prefixed-SI", "divx.l", 24,
42020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42022 /* divx.l $Dst32AnPrefixedSI */
42024 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_AN_DIRECT_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-An-direct-Prefixed-SI", "divx.l", 24,
42025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42027 /* divx.l [$Dst32AnPrefixed] */
42029 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_AN_INDIRECT_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-An-indirect-Prefixed-SI", "divx.l", 24,
42030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42032 /* divx.l ${Dsp-24-u8}[$Dst32AnPrefixed] */
42034 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_8_AN_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-8-An-relative-Prefixed-SI", "divx.l", 32,
42035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42037 /* divx.l ${Dsp-24-u16}[$Dst32AnPrefixed] */
42039 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_AN_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-16-An-relative-Prefixed-SI", "divx.l", 40,
42040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42042 /* divx.l ${Dsp-24-u24}[$Dst32AnPrefixed] */
42044 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_24_AN_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-24-An-relative-Prefixed-SI", "divx.l", 48,
42045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42047 /* divx.l ${Dsp-24-u8}[sb] */
42049 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_8_SB_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-8-SB-relative-Prefixed-SI", "divx.l", 32,
42050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42052 /* divx.l ${Dsp-24-u16}[sb] */
42054 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_SB_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-16-SB-relative-Prefixed-SI", "divx.l", 40,
42055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42057 /* divx.l ${Dsp-24-s8}[fb] */
42059 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_8_FB_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-8-FB-relative-Prefixed-SI", "divx.l", 32,
42060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42062 /* divx.l ${Dsp-24-s16}[fb] */
42064 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_FB_RELATIVE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-16-FB-relative-Prefixed-SI", "divx.l", 40,
42065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42067 /* divx.l ${Dsp-24-u16} */
42069 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_16_ABSOLUTE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-16-absolute-Prefixed-SI", "divx.l", 40,
42070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42072 /* divx.l ${Dsp-24-u24} */
42074 M32C_INSN_DIVX32_L_DST32_24_PREFIXED_SI_DST32_24_24_ABSOLUTE_PREFIXED_SI, "divx32.l-dst32-24-Prefixed-SI-dst32-24-24-absolute-Prefixed-SI", "divx.l", 48,
42075 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42077 /* divu.l $Dst32RnPrefixedSI */
42079 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_RN_DIRECT_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-Rn-direct-Prefixed-SI", "divu.l", 24,
42080 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42082 /* divu.l $Dst32AnPrefixedSI */
42084 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_AN_DIRECT_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-An-direct-Prefixed-SI", "divu.l", 24,
42085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42087 /* divu.l [$Dst32AnPrefixed] */
42089 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_AN_INDIRECT_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-An-indirect-Prefixed-SI", "divu.l", 24,
42090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42092 /* divu.l ${Dsp-24-u8}[$Dst32AnPrefixed] */
42094 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_8_AN_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-8-An-relative-Prefixed-SI", "divu.l", 32,
42095 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42097 /* divu.l ${Dsp-24-u16}[$Dst32AnPrefixed] */
42099 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_AN_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-16-An-relative-Prefixed-SI", "divu.l", 40,
42100 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42102 /* divu.l ${Dsp-24-u24}[$Dst32AnPrefixed] */
42104 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_24_AN_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-24-An-relative-Prefixed-SI", "divu.l", 48,
42105 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42107 /* divu.l ${Dsp-24-u8}[sb] */
42109 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_8_SB_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-8-SB-relative-Prefixed-SI", "divu.l", 32,
42110 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42112 /* divu.l ${Dsp-24-u16}[sb] */
42114 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_SB_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-16-SB-relative-Prefixed-SI", "divu.l", 40,
42115 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42117 /* divu.l ${Dsp-24-s8}[fb] */
42119 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_8_FB_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-8-FB-relative-Prefixed-SI", "divu.l", 32,
42120 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42122 /* divu.l ${Dsp-24-s16}[fb] */
42124 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_FB_RELATIVE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-16-FB-relative-Prefixed-SI", "divu.l", 40,
42125 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42127 /* divu.l ${Dsp-24-u16} */
42129 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_16_ABSOLUTE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-16-absolute-Prefixed-SI", "divu.l", 40,
42130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42132 /* divu.l ${Dsp-24-u24} */
42134 M32C_INSN_DIVU32_L_DST32_24_PREFIXED_SI_DST32_24_24_ABSOLUTE_PREFIXED_SI, "divu32.l-dst32-24-Prefixed-SI-dst32-24-24-absolute-Prefixed-SI", "divu.l", 48,
42135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42137 /* div.l $Dst32RnPrefixedSI */
42139 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_RN_DIRECT_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-Rn-direct-Prefixed-SI", "div.l", 24,
42140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42142 /* div.l $Dst32AnPrefixedSI */
42144 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_AN_DIRECT_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-An-direct-Prefixed-SI", "div.l", 24,
42145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42147 /* div.l [$Dst32AnPrefixed] */
42149 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_AN_INDIRECT_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-An-indirect-Prefixed-SI", "div.l", 24,
42150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42152 /* div.l ${Dsp-24-u8}[$Dst32AnPrefixed] */
42154 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_8_AN_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-8-An-relative-Prefixed-SI", "div.l", 32,
42155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42157 /* div.l ${Dsp-24-u16}[$Dst32AnPrefixed] */
42159 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_AN_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-16-An-relative-Prefixed-SI", "div.l", 40,
42160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42162 /* div.l ${Dsp-24-u24}[$Dst32AnPrefixed] */
42164 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_24_AN_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-24-An-relative-Prefixed-SI", "div.l", 48,
42165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42167 /* div.l ${Dsp-24-u8}[sb] */
42169 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_8_SB_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-8-SB-relative-Prefixed-SI", "div.l", 32,
42170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42172 /* div.l ${Dsp-24-u16}[sb] */
42174 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_SB_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-16-SB-relative-Prefixed-SI", "div.l", 40,
42175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42177 /* div.l ${Dsp-24-s8}[fb] */
42179 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_8_FB_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-8-FB-relative-Prefixed-SI", "div.l", 32,
42180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42182 /* div.l ${Dsp-24-s16}[fb] */
42184 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_FB_RELATIVE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-16-FB-relative-Prefixed-SI", "div.l", 40,
42185 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42187 /* div.l ${Dsp-24-u16} */
42189 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_16_ABSOLUTE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-16-absolute-Prefixed-SI", "div.l", 40,
42190 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42192 /* div.l ${Dsp-24-u24} */
42194 M32C_INSN_DIV32_L_DST32_24_PREFIXED_SI_DST32_24_24_ABSOLUTE_PREFIXED_SI, "div32.l-dst32-24-Prefixed-SI-dst32-24-24-absolute-Prefixed-SI", "div.l", 48,
42195 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42197 /* divx.w $Dst32RnUnprefixedHI */
42199 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "divx.w", 16,
42200 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42202 /* divx.w $Dst32AnUnprefixedHI */
42204 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "divx.w", 16,
42205 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42207 /* divx.w [$Dst32AnUnprefixed] */
42209 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "divx.w", 16,
42210 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42212 /* divx.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
42214 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "divx.w", 24,
42215 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42217 /* divx.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
42219 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "divx.w", 32,
42220 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42222 /* divx.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
42224 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "divx.w", 40,
42225 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42227 /* divx.w ${Dsp-16-u8}[sb] */
42229 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "divx.w", 24,
42230 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42232 /* divx.w ${Dsp-16-u16}[sb] */
42234 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "divx.w", 32,
42235 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42237 /* divx.w ${Dsp-16-s8}[fb] */
42239 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "divx.w", 24,
42240 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42242 /* divx.w ${Dsp-16-s16}[fb] */
42244 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "divx.w", 32,
42245 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42247 /* divx.w ${Dsp-16-u16} */
42249 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "divx.w", 32,
42250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42252 /* divx.w ${Dsp-16-u24} */
42254 M32C_INSN_DIVX32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "divx32.w-dst32-16-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "divx.w", 40,
42255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42257 /* divx.b $Dst32RnUnprefixedQI */
42259 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "divx.b", 16,
42260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42262 /* divx.b $Dst32AnUnprefixedQI */
42264 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "divx.b", 16,
42265 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42267 /* divx.b [$Dst32AnUnprefixed] */
42269 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "divx.b", 16,
42270 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42272 /* divx.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
42274 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "divx.b", 24,
42275 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42277 /* divx.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
42279 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "divx.b", 32,
42280 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42282 /* divx.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
42284 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "divx.b", 40,
42285 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42287 /* divx.b ${Dsp-16-u8}[sb] */
42289 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "divx.b", 24,
42290 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42292 /* divx.b ${Dsp-16-u16}[sb] */
42294 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "divx.b", 32,
42295 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42297 /* divx.b ${Dsp-16-s8}[fb] */
42299 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "divx.b", 24,
42300 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42302 /* divx.b ${Dsp-16-s16}[fb] */
42304 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "divx.b", 32,
42305 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42307 /* divx.b ${Dsp-16-u16} */
42309 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "divx.b", 32,
42310 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42312 /* divx.b ${Dsp-16-u24} */
42314 M32C_INSN_DIVX32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "divx32.b-dst32-16-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "divx.b", 40,
42315 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42317 /* divx.w $Dst16RnHI */
42319 M32C_INSN_DIVX16_W_DST16_16_HI_DST16_RN_DIRECT_HI, "divx16.w-dst16-16-HI-dst16-Rn-direct-HI", "divx.w", 16,
42320 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42322 /* divx.w $Dst16AnHI */
42324 M32C_INSN_DIVX16_W_DST16_16_HI_DST16_AN_DIRECT_HI, "divx16.w-dst16-16-HI-dst16-An-direct-HI", "divx.w", 16,
42325 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42327 /* divx.w [$Dst16An] */
42329 M32C_INSN_DIVX16_W_DST16_16_HI_DST16_AN_INDIRECT_HI, "divx16.w-dst16-16-HI-dst16-An-indirect-HI", "divx.w", 16,
42330 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42332 /* divx.w ${Dsp-16-u8}[$Dst16An] */
42334 M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_8_AN_RELATIVE_HI, "divx16.w-dst16-16-HI-dst16-16-8-An-relative-HI", "divx.w", 24,
42335 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42337 /* divx.w ${Dsp-16-u16}[$Dst16An] */
42339 M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_16_AN_RELATIVE_HI, "divx16.w-dst16-16-HI-dst16-16-16-An-relative-HI", "divx.w", 32,
42340 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42342 /* divx.w ${Dsp-16-u8}[sb] */
42344 M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_8_SB_RELATIVE_HI, "divx16.w-dst16-16-HI-dst16-16-8-SB-relative-HI", "divx.w", 24,
42345 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42347 /* divx.w ${Dsp-16-u16}[sb] */
42349 M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_16_SB_RELATIVE_HI, "divx16.w-dst16-16-HI-dst16-16-16-SB-relative-HI", "divx.w", 32,
42350 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42352 /* divx.w ${Dsp-16-s8}[fb] */
42354 M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_8_FB_RELATIVE_HI, "divx16.w-dst16-16-HI-dst16-16-8-FB-relative-HI", "divx.w", 24,
42355 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42357 /* divx.w ${Dsp-16-u16} */
42359 M32C_INSN_DIVX16_W_DST16_16_HI_DST16_16_16_ABSOLUTE_HI, "divx16.w-dst16-16-HI-dst16-16-16-absolute-HI", "divx.w", 32,
42360 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42362 /* divx.b $Dst16RnQI */
42364 M32C_INSN_DIVX16_B_DST16_16_QI_DST16_RN_DIRECT_QI, "divx16.b-dst16-16-QI-dst16-Rn-direct-QI", "divx.b", 16,
42365 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42367 /* divx.b $Dst16AnQI */
42369 M32C_INSN_DIVX16_B_DST16_16_QI_DST16_AN_DIRECT_QI, "divx16.b-dst16-16-QI-dst16-An-direct-QI", "divx.b", 16,
42370 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42372 /* divx.b [$Dst16An] */
42374 M32C_INSN_DIVX16_B_DST16_16_QI_DST16_AN_INDIRECT_QI, "divx16.b-dst16-16-QI-dst16-An-indirect-QI", "divx.b", 16,
42375 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42377 /* divx.b ${Dsp-16-u8}[$Dst16An] */
42379 M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_8_AN_RELATIVE_QI, "divx16.b-dst16-16-QI-dst16-16-8-An-relative-QI", "divx.b", 24,
42380 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42382 /* divx.b ${Dsp-16-u16}[$Dst16An] */
42384 M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_16_AN_RELATIVE_QI, "divx16.b-dst16-16-QI-dst16-16-16-An-relative-QI", "divx.b", 32,
42385 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42387 /* divx.b ${Dsp-16-u8}[sb] */
42389 M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_8_SB_RELATIVE_QI, "divx16.b-dst16-16-QI-dst16-16-8-SB-relative-QI", "divx.b", 24,
42390 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42392 /* divx.b ${Dsp-16-u16}[sb] */
42394 M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_16_SB_RELATIVE_QI, "divx16.b-dst16-16-QI-dst16-16-16-SB-relative-QI", "divx.b", 32,
42395 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42397 /* divx.b ${Dsp-16-s8}[fb] */
42399 M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_8_FB_RELATIVE_QI, "divx16.b-dst16-16-QI-dst16-16-8-FB-relative-QI", "divx.b", 24,
42400 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42402 /* divx.b ${Dsp-16-u16} */
42404 M32C_INSN_DIVX16_B_DST16_16_QI_DST16_16_16_ABSOLUTE_QI, "divx16.b-dst16-16-QI-dst16-16-16-absolute-QI", "divx.b", 32,
42405 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42407 /* divu.w $Dst32RnUnprefixedHI */
42409 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "divu.w", 16,
42410 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42412 /* divu.w $Dst32AnUnprefixedHI */
42414 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "divu.w", 16,
42415 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42417 /* divu.w [$Dst32AnUnprefixed] */
42419 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "divu.w", 16,
42420 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42422 /* divu.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
42424 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "divu.w", 24,
42425 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42427 /* divu.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
42429 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "divu.w", 32,
42430 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42432 /* divu.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
42434 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "divu.w", 40,
42435 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42437 /* divu.w ${Dsp-16-u8}[sb] */
42439 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "divu.w", 24,
42440 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42442 /* divu.w ${Dsp-16-u16}[sb] */
42444 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "divu.w", 32,
42445 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42447 /* divu.w ${Dsp-16-s8}[fb] */
42449 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "divu.w", 24,
42450 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42452 /* divu.w ${Dsp-16-s16}[fb] */
42454 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "divu.w", 32,
42455 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42457 /* divu.w ${Dsp-16-u16} */
42459 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "divu.w", 32,
42460 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42462 /* divu.w ${Dsp-16-u24} */
42464 M32C_INSN_DIVU32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "divu32.w-dst32-16-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "divu.w", 40,
42465 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42467 /* divu.b $Dst32RnUnprefixedQI */
42469 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "divu.b", 16,
42470 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42472 /* divu.b $Dst32AnUnprefixedQI */
42474 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "divu.b", 16,
42475 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42477 /* divu.b [$Dst32AnUnprefixed] */
42479 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "divu.b", 16,
42480 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42482 /* divu.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
42484 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "divu.b", 24,
42485 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42487 /* divu.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
42489 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "divu.b", 32,
42490 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42492 /* divu.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
42494 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "divu.b", 40,
42495 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42497 /* divu.b ${Dsp-16-u8}[sb] */
42499 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "divu.b", 24,
42500 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42502 /* divu.b ${Dsp-16-u16}[sb] */
42504 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "divu.b", 32,
42505 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42507 /* divu.b ${Dsp-16-s8}[fb] */
42509 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "divu.b", 24,
42510 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42512 /* divu.b ${Dsp-16-s16}[fb] */
42514 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "divu.b", 32,
42515 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42517 /* divu.b ${Dsp-16-u16} */
42519 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "divu.b", 32,
42520 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42522 /* divu.b ${Dsp-16-u24} */
42524 M32C_INSN_DIVU32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "divu32.b-dst32-16-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "divu.b", 40,
42525 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42527 /* divu.w $Dst16RnHI */
42529 M32C_INSN_DIVU16_W_DST16_16_HI_DST16_RN_DIRECT_HI, "divu16.w-dst16-16-HI-dst16-Rn-direct-HI", "divu.w", 16,
42530 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42532 /* divu.w $Dst16AnHI */
42534 M32C_INSN_DIVU16_W_DST16_16_HI_DST16_AN_DIRECT_HI, "divu16.w-dst16-16-HI-dst16-An-direct-HI", "divu.w", 16,
42535 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42537 /* divu.w [$Dst16An] */
42539 M32C_INSN_DIVU16_W_DST16_16_HI_DST16_AN_INDIRECT_HI, "divu16.w-dst16-16-HI-dst16-An-indirect-HI", "divu.w", 16,
42540 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42542 /* divu.w ${Dsp-16-u8}[$Dst16An] */
42544 M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_8_AN_RELATIVE_HI, "divu16.w-dst16-16-HI-dst16-16-8-An-relative-HI", "divu.w", 24,
42545 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42547 /* divu.w ${Dsp-16-u16}[$Dst16An] */
42549 M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_16_AN_RELATIVE_HI, "divu16.w-dst16-16-HI-dst16-16-16-An-relative-HI", "divu.w", 32,
42550 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42552 /* divu.w ${Dsp-16-u8}[sb] */
42554 M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_8_SB_RELATIVE_HI, "divu16.w-dst16-16-HI-dst16-16-8-SB-relative-HI", "divu.w", 24,
42555 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42557 /* divu.w ${Dsp-16-u16}[sb] */
42559 M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_16_SB_RELATIVE_HI, "divu16.w-dst16-16-HI-dst16-16-16-SB-relative-HI", "divu.w", 32,
42560 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42562 /* divu.w ${Dsp-16-s8}[fb] */
42564 M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_8_FB_RELATIVE_HI, "divu16.w-dst16-16-HI-dst16-16-8-FB-relative-HI", "divu.w", 24,
42565 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42567 /* divu.w ${Dsp-16-u16} */
42569 M32C_INSN_DIVU16_W_DST16_16_HI_DST16_16_16_ABSOLUTE_HI, "divu16.w-dst16-16-HI-dst16-16-16-absolute-HI", "divu.w", 32,
42570 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42572 /* divu.b $Dst16RnQI */
42574 M32C_INSN_DIVU16_B_DST16_16_QI_DST16_RN_DIRECT_QI, "divu16.b-dst16-16-QI-dst16-Rn-direct-QI", "divu.b", 16,
42575 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42577 /* divu.b $Dst16AnQI */
42579 M32C_INSN_DIVU16_B_DST16_16_QI_DST16_AN_DIRECT_QI, "divu16.b-dst16-16-QI-dst16-An-direct-QI", "divu.b", 16,
42580 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42582 /* divu.b [$Dst16An] */
42584 M32C_INSN_DIVU16_B_DST16_16_QI_DST16_AN_INDIRECT_QI, "divu16.b-dst16-16-QI-dst16-An-indirect-QI", "divu.b", 16,
42585 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42587 /* divu.b ${Dsp-16-u8}[$Dst16An] */
42589 M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_8_AN_RELATIVE_QI, "divu16.b-dst16-16-QI-dst16-16-8-An-relative-QI", "divu.b", 24,
42590 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42592 /* divu.b ${Dsp-16-u16}[$Dst16An] */
42594 M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_16_AN_RELATIVE_QI, "divu16.b-dst16-16-QI-dst16-16-16-An-relative-QI", "divu.b", 32,
42595 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42597 /* divu.b ${Dsp-16-u8}[sb] */
42599 M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_8_SB_RELATIVE_QI, "divu16.b-dst16-16-QI-dst16-16-8-SB-relative-QI", "divu.b", 24,
42600 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42602 /* divu.b ${Dsp-16-u16}[sb] */
42604 M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_16_SB_RELATIVE_QI, "divu16.b-dst16-16-QI-dst16-16-16-SB-relative-QI", "divu.b", 32,
42605 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42607 /* divu.b ${Dsp-16-s8}[fb] */
42609 M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_8_FB_RELATIVE_QI, "divu16.b-dst16-16-QI-dst16-16-8-FB-relative-QI", "divu.b", 24,
42610 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42612 /* divu.b ${Dsp-16-u16} */
42614 M32C_INSN_DIVU16_B_DST16_16_QI_DST16_16_16_ABSOLUTE_QI, "divu16.b-dst16-16-QI-dst16-16-16-absolute-QI", "divu.b", 32,
42615 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42617 /* div.w $Dst32RnUnprefixedHI */
42619 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "div.w", 16,
42620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42622 /* div.w $Dst32AnUnprefixedHI */
42624 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "div.w", 16,
42625 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42627 /* div.w [$Dst32AnUnprefixed] */
42629 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "div.w", 16,
42630 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42632 /* div.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
42634 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "div.w", 24,
42635 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42637 /* div.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
42639 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "div.w", 32,
42640 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42642 /* div.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
42644 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "div.w", 40,
42645 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42647 /* div.w ${Dsp-16-u8}[sb] */
42649 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "div.w", 24,
42650 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42652 /* div.w ${Dsp-16-u16}[sb] */
42654 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "div.w", 32,
42655 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42657 /* div.w ${Dsp-16-s8}[fb] */
42659 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "div.w", 24,
42660 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42662 /* div.w ${Dsp-16-s16}[fb] */
42664 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "div.w", 32,
42665 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42667 /* div.w ${Dsp-16-u16} */
42669 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "div.w", 32,
42670 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42672 /* div.w ${Dsp-16-u24} */
42674 M32C_INSN_DIV32_W_DST32_16_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "div32.w-dst32-16-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "div.w", 40,
42675 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42677 /* div.b $Dst32RnUnprefixedQI */
42679 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "div.b", 16,
42680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42682 /* div.b $Dst32AnUnprefixedQI */
42684 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "div.b", 16,
42685 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42687 /* div.b [$Dst32AnUnprefixed] */
42689 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "div.b", 16,
42690 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42692 /* div.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
42694 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "div.b", 24,
42695 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42697 /* div.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
42699 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "div.b", 32,
42700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42702 /* div.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
42704 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "div.b", 40,
42705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42707 /* div.b ${Dsp-16-u8}[sb] */
42709 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "div.b", 24,
42710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42712 /* div.b ${Dsp-16-u16}[sb] */
42714 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "div.b", 32,
42715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42717 /* div.b ${Dsp-16-s8}[fb] */
42719 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "div.b", 24,
42720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42722 /* div.b ${Dsp-16-s16}[fb] */
42724 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "div.b", 32,
42725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42727 /* div.b ${Dsp-16-u16} */
42729 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "div.b", 32,
42730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42732 /* div.b ${Dsp-16-u24} */
42734 M32C_INSN_DIV32_B_DST32_16_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "div32.b-dst32-16-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "div.b", 40,
42735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42737 /* div.w $Dst16RnHI */
42739 M32C_INSN_DIV16_W_DST16_16_HI_DST16_RN_DIRECT_HI, "div16.w-dst16-16-HI-dst16-Rn-direct-HI", "div.w", 16,
42740 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42742 /* div.w $Dst16AnHI */
42744 M32C_INSN_DIV16_W_DST16_16_HI_DST16_AN_DIRECT_HI, "div16.w-dst16-16-HI-dst16-An-direct-HI", "div.w", 16,
42745 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42747 /* div.w [$Dst16An] */
42749 M32C_INSN_DIV16_W_DST16_16_HI_DST16_AN_INDIRECT_HI, "div16.w-dst16-16-HI-dst16-An-indirect-HI", "div.w", 16,
42750 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42752 /* div.w ${Dsp-16-u8}[$Dst16An] */
42754 M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_8_AN_RELATIVE_HI, "div16.w-dst16-16-HI-dst16-16-8-An-relative-HI", "div.w", 24,
42755 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42757 /* div.w ${Dsp-16-u16}[$Dst16An] */
42759 M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_16_AN_RELATIVE_HI, "div16.w-dst16-16-HI-dst16-16-16-An-relative-HI", "div.w", 32,
42760 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42762 /* div.w ${Dsp-16-u8}[sb] */
42764 M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_8_SB_RELATIVE_HI, "div16.w-dst16-16-HI-dst16-16-8-SB-relative-HI", "div.w", 24,
42765 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42767 /* div.w ${Dsp-16-u16}[sb] */
42769 M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_16_SB_RELATIVE_HI, "div16.w-dst16-16-HI-dst16-16-16-SB-relative-HI", "div.w", 32,
42770 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42772 /* div.w ${Dsp-16-s8}[fb] */
42774 M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_8_FB_RELATIVE_HI, "div16.w-dst16-16-HI-dst16-16-8-FB-relative-HI", "div.w", 24,
42775 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42777 /* div.w ${Dsp-16-u16} */
42779 M32C_INSN_DIV16_W_DST16_16_HI_DST16_16_16_ABSOLUTE_HI, "div16.w-dst16-16-HI-dst16-16-16-absolute-HI", "div.w", 32,
42780 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42782 /* div.b $Dst16RnQI */
42784 M32C_INSN_DIV16_B_DST16_16_QI_DST16_RN_DIRECT_QI, "div16.b-dst16-16-QI-dst16-Rn-direct-QI", "div.b", 16,
42785 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42787 /* div.b $Dst16AnQI */
42789 M32C_INSN_DIV16_B_DST16_16_QI_DST16_AN_DIRECT_QI, "div16.b-dst16-16-QI-dst16-An-direct-QI", "div.b", 16,
42790 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42792 /* div.b [$Dst16An] */
42794 M32C_INSN_DIV16_B_DST16_16_QI_DST16_AN_INDIRECT_QI, "div16.b-dst16-16-QI-dst16-An-indirect-QI", "div.b", 16,
42795 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42797 /* div.b ${Dsp-16-u8}[$Dst16An] */
42799 M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_8_AN_RELATIVE_QI, "div16.b-dst16-16-QI-dst16-16-8-An-relative-QI", "div.b", 24,
42800 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42802 /* div.b ${Dsp-16-u16}[$Dst16An] */
42804 M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_16_AN_RELATIVE_QI, "div16.b-dst16-16-QI-dst16-16-16-An-relative-QI", "div.b", 32,
42805 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42807 /* div.b ${Dsp-16-u8}[sb] */
42809 M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_8_SB_RELATIVE_QI, "div16.b-dst16-16-QI-dst16-16-8-SB-relative-QI", "div.b", 24,
42810 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42812 /* div.b ${Dsp-16-u16}[sb] */
42814 M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_16_SB_RELATIVE_QI, "div16.b-dst16-16-QI-dst16-16-16-SB-relative-QI", "div.b", 32,
42815 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42817 /* div.b ${Dsp-16-s8}[fb] */
42819 M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_8_FB_RELATIVE_QI, "div16.b-dst16-16-QI-dst16-16-8-FB-relative-QI", "div.b", 24,
42820 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42822 /* div.b ${Dsp-16-u16} */
42824 M32C_INSN_DIV16_B_DST16_16_QI_DST16_16_16_ABSOLUTE_QI, "div16.b-dst16-16-QI-dst16-16-16-absolute-QI", "div.b", 32,
42825 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42827 /* dec.w $Dst32RnUnprefixedHI */
42829 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "dec.w", 16,
42830 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42832 /* dec.w $Dst32AnUnprefixedHI */
42834 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "dec.w", 16,
42835 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42837 /* dec.w [$Dst32AnUnprefixed] */
42839 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "dec.w", 16,
42840 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42842 /* dec.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
42844 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "dec.w", 24,
42845 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42847 /* dec.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
42849 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "dec.w", 32,
42850 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42852 /* dec.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
42854 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "dec.w", 40,
42855 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42857 /* dec.w ${Dsp-16-u8}[sb] */
42859 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "dec.w", 24,
42860 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42862 /* dec.w ${Dsp-16-u16}[sb] */
42864 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "dec.w", 32,
42865 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42867 /* dec.w ${Dsp-16-s8}[fb] */
42869 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "dec.w", 24,
42870 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42872 /* dec.w ${Dsp-16-s16}[fb] */
42874 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "dec.w", 32,
42875 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42877 /* dec.w ${Dsp-16-u16} */
42879 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "dec.w", 32,
42880 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42882 /* dec.w ${Dsp-16-u24} */
42884 M32C_INSN_DEC32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "dec32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "dec.w", 40,
42885 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42887 /* dec.b $Dst32RnUnprefixedQI */
42889 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "dec.b", 16,
42890 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42892 /* dec.b $Dst32AnUnprefixedQI */
42894 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "dec.b", 16,
42895 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42897 /* dec.b [$Dst32AnUnprefixed] */
42899 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "dec.b", 16,
42900 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42902 /* dec.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
42904 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "dec.b", 24,
42905 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42907 /* dec.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
42909 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "dec.b", 32,
42910 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42912 /* dec.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
42914 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "dec.b", 40,
42915 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42917 /* dec.b ${Dsp-16-u8}[sb] */
42919 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "dec.b", 24,
42920 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42922 /* dec.b ${Dsp-16-u16}[sb] */
42924 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "dec.b", 32,
42925 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42927 /* dec.b ${Dsp-16-s8}[fb] */
42929 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "dec.b", 24,
42930 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42932 /* dec.b ${Dsp-16-s16}[fb] */
42934 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "dec.b", 32,
42935 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42937 /* dec.b ${Dsp-16-u16} */
42939 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "dec.b", 32,
42940 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42942 /* dec.b ${Dsp-16-u24} */
42944 M32C_INSN_DEC32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "dec32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "dec.b", 40,
42945 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42949 M32C_INSN_DEC16_B_DST16_3_S_R0L_DIRECT_QI, "dec16.b-dst16-3-S-R0l-direct-QI", "dec.b", 8,
42950 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42954 M32C_INSN_DEC16_B_DST16_3_S_R0H_DIRECT_QI, "dec16.b-dst16-3-S-R0h-direct-QI", "dec.b", 8,
42955 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42957 /* dec.b ${Dsp-8-u8}[sb] */
42959 M32C_INSN_DEC16_B_DST16_3_S_8_8_SB_RELATIVE_QI, "dec16.b-dst16-3-S-8-8-SB-relative-QI", "dec.b", 16,
42960 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42962 /* dec.b ${Dsp-8-s8}[fb] */
42964 M32C_INSN_DEC16_B_DST16_3_S_8_8_FB_RELATIVE_QI, "dec16.b-dst16-3-S-8-8-FB-relative-QI", "dec.b", 16,
42965 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42967 /* dec.b ${Dsp-8-u16} */
42969 M32C_INSN_DEC16_B_DST16_3_S_8_16_ABSOLUTE_QI, "dec16.b-dst16-3-S-8-16-absolute-QI", "dec.b", 24,
42970 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
42972 /* cmpx${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
42974 M32C_INSN_CMPX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "cmpx32-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "cmpx", 24,
42975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42977 /* cmpx${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
42979 M32C_INSN_CMPX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "cmpx32-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "cmpx", 24,
42980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42982 /* cmpx${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
42984 M32C_INSN_CMPX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmpx32-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "cmpx", 24,
42985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42987 /* cmpx${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
42989 M32C_INSN_CMPX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "cmpx", 32,
42990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42992 /* cmpx${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
42994 M32C_INSN_CMPX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "cmpx", 32,
42995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
42997 /* cmpx${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
42999 M32C_INSN_CMPX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "cmpx", 32,
43000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43002 /* cmpx${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
43004 M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "cmpx", 40,
43005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43007 /* cmpx${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
43009 M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "cmpx", 40,
43010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43012 /* cmpx${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
43014 M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "cmpx", 40,
43015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43017 /* cmpx${X} #${Imm-32-QI},${Dsp-16-u16} */
43019 M32C_INSN_CMPX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "cmpx32-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "cmpx", 40,
43020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43022 /* cmpx${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
43024 M32C_INSN_CMPX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "cmpx32-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "cmpx", 48,
43025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43027 /* cmpx${X} #${Imm-40-QI},${Dsp-16-u24} */
43029 M32C_INSN_CMPX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "cmpx32-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "cmpx", 48,
43030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43032 /* cmp.w${S} ${Dsp-8-u8}[sb],${Dst32R0HI-S} */
43034 M32C_INSN_CMP32_W_S_SRC2_R0_HI_SRC32_2_S_8_SB_RELATIVE_HI, "cmp32.w.S-src2-r0-HI-src32-2-S-8-SB-relative-HI", "cmp.w", 16,
43035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43037 /* cmp.w${S} ${Dsp-8-s8}[fb],${Dst32R0HI-S} */
43039 M32C_INSN_CMP32_W_S_SRC2_R0_HI_SRC32_2_S_8_FB_RELATIVE_HI, "cmp32.w.S-src2-r0-HI-src32-2-S-8-FB-relative-HI", "cmp.w", 16,
43040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43042 /* cmp.w${S} ${Dsp-8-u16},${Dst32R0HI-S} */
43044 M32C_INSN_CMP32_W_S_SRC2_R0_HI_SRC32_2_S_16_ABSOLUTE_HI, "cmp32.w.S-src2-r0-HI-src32-2-S-16-absolute-HI", "cmp.w", 24,
43045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43047 /* cmp.b${S} ${Dsp-8-u8}[sb],${Dst32R0QI-S} */
43049 M32C_INSN_CMP32_B_S_SRC2_R0_QI_SRC32_2_S_8_SB_RELATIVE_QI, "cmp32.b.S-src2-r0-QI-src32-2-S-8-SB-relative-QI", "cmp.b", 16,
43050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43052 /* cmp.b${S} ${Dsp-8-s8}[fb],${Dst32R0QI-S} */
43054 M32C_INSN_CMP32_B_S_SRC2_R0_QI_SRC32_2_S_8_FB_RELATIVE_QI, "cmp32.b.S-src2-r0-QI-src32-2-S-8-FB-relative-QI", "cmp.b", 16,
43055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43057 /* cmp.b${S} ${Dsp-8-u16},${Dst32R0QI-S} */
43059 M32C_INSN_CMP32_B_S_SRC2_R0_QI_SRC32_2_S_16_ABSOLUTE_QI, "cmp32.b.S-src2-r0-QI-src32-2-S-16-absolute-QI", "cmp.b", 24,
43060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43062 /* cmp.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
43064 M32C_INSN_CMP32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "cmp32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "cmp.w", 32,
43065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43067 /* cmp.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
43069 M32C_INSN_CMP32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "cmp32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "cmp.w", 32,
43070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43072 /* cmp.w${S} #${Imm-24-HI},${Dsp-8-u16} */
43074 M32C_INSN_CMP32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "cmp32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "cmp.w", 40,
43075 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43077 /* cmp.w${S} #${Imm-8-HI},r0 */
43079 M32C_INSN_CMP32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "cmp32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "cmp.w", 24,
43080 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43082 /* cmp.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
43084 M32C_INSN_CMP32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "cmp32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "cmp.b", 24,
43085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43087 /* cmp.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
43089 M32C_INSN_CMP32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "cmp32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "cmp.b", 24,
43090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43092 /* cmp.b${S} #${Imm-24-QI},${Dsp-8-u16} */
43094 M32C_INSN_CMP32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "cmp32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "cmp.b", 32,
43095 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43097 /* cmp.b${S} #${Imm-8-QI},r0l */
43099 M32C_INSN_CMP32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "cmp32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "cmp.b", 16,
43100 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43102 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
43104 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 24,
43105 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43107 /* cmp.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
43109 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 24,
43110 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43112 /* cmp.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
43114 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 24,
43115 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43117 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
43119 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 24,
43120 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43122 /* cmp.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
43124 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 24,
43125 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43127 /* cmp.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
43129 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 24,
43130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43132 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
43134 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 24,
43135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43137 /* cmp.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
43139 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 24,
43140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43142 /* cmp.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
43144 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 24,
43145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43147 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
43149 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "cmp.l", 32,
43150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43152 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
43154 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "cmp.l", 32,
43155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43157 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
43159 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "cmp.l", 32,
43160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43162 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
43164 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "cmp.l", 40,
43165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43167 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
43169 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "cmp.l", 40,
43170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43172 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
43174 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "cmp.l", 40,
43175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43177 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
43179 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "cmp.l", 48,
43180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43182 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
43184 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "cmp.l", 48,
43185 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43187 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
43189 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "cmp.l", 48,
43190 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43192 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
43194 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "cmp.l", 32,
43195 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43197 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
43199 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "cmp.l", 32,
43200 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43202 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
43204 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "cmp.l", 32,
43205 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43207 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
43209 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "cmp.l", 40,
43210 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43212 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
43214 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "cmp.l", 40,
43215 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43217 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
43219 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "cmp.l", 40,
43220 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43222 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
43224 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "cmp.l", 32,
43225 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43227 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
43229 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "cmp.l", 32,
43230 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43232 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
43234 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "cmp.l", 32,
43235 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43237 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
43239 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "cmp.l", 40,
43240 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43242 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
43244 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "cmp.l", 40,
43245 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43247 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
43249 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "cmp.l", 40,
43250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43252 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
43254 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "cmp.l", 40,
43255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43257 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
43259 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "cmp.l", 40,
43260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43262 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
43264 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "cmp.l", 40,
43265 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43267 /* cmp.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
43269 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "cmp.l", 48,
43270 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43272 /* cmp.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
43274 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "cmp.l", 48,
43275 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43277 /* cmp.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
43279 M32C_INSN_CMP32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "cmp.l", 48,
43280 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43282 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
43284 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 32,
43285 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43287 /* cmp.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
43289 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 32,
43290 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43292 /* cmp.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
43294 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 32,
43295 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43297 /* cmp.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
43299 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 32,
43300 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43302 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
43304 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 32,
43305 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43307 /* cmp.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
43309 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 32,
43310 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43312 /* cmp.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
43314 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 32,
43315 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43317 /* cmp.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
43319 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 32,
43320 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43322 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
43324 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 32,
43325 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43327 /* cmp.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
43329 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 32,
43330 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43332 /* cmp.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
43334 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 32,
43335 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43337 /* cmp.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
43339 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 32,
43340 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43342 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
43344 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "cmp.l", 40,
43345 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43347 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
43349 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "cmp.l", 40,
43350 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43352 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
43354 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "cmp.l", 40,
43355 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43357 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
43359 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "cmp.l", 40,
43360 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43362 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
43364 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "cmp.l", 48,
43365 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43367 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
43369 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "cmp.l", 48,
43370 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43372 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
43374 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "cmp.l", 48,
43375 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43377 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
43379 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "cmp.l", 48,
43380 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43382 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
43384 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "cmp.l", 56,
43385 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43387 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
43389 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "cmp.l", 56,
43390 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43392 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
43394 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "cmp.l", 56,
43395 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43397 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
43399 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "cmp.l", 56,
43400 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43402 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
43404 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "cmp.l", 40,
43405 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43407 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
43409 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "cmp.l", 40,
43410 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43412 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
43414 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "cmp.l", 40,
43415 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43417 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
43419 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "cmp.l", 40,
43420 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43422 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
43424 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "cmp.l", 48,
43425 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43427 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
43429 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "cmp.l", 48,
43430 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43432 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
43434 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "cmp.l", 48,
43435 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43437 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
43439 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "cmp.l", 48,
43440 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43442 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
43444 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "cmp.l", 40,
43445 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43447 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
43449 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "cmp.l", 40,
43450 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43452 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
43454 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "cmp.l", 40,
43455 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43457 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
43459 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "cmp.l", 40,
43460 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43462 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
43464 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "cmp.l", 48,
43465 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43467 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
43469 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "cmp.l", 48,
43470 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43472 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
43474 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "cmp.l", 48,
43475 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43477 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
43479 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "cmp.l", 48,
43480 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43482 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
43484 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "cmp.l", 48,
43485 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43487 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
43489 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "cmp.l", 48,
43490 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43492 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
43494 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "cmp.l", 48,
43495 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43497 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u16} */
43499 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "cmp.l", 48,
43500 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43502 /* cmp.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
43504 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "cmp.l", 56,
43505 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43507 /* cmp.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
43509 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "cmp.l", 56,
43510 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43512 /* cmp.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
43514 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "cmp.l", 56,
43515 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43517 /* cmp.l${G} ${Dsp-16-u16},${Dsp-32-u24} */
43519 M32C_INSN_CMP32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "cmp.l", 56,
43520 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43522 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
43524 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 40,
43525 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43527 /* cmp.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
43529 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 40,
43530 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43532 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
43534 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 40,
43535 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43537 /* cmp.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
43539 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 40,
43540 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43542 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
43544 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 40,
43545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43547 /* cmp.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
43549 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 40,
43550 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43552 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
43554 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "cmp.l", 48,
43555 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43557 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
43559 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "cmp.l", 48,
43560 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43562 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
43564 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "cmp.l", 56,
43565 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43567 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
43569 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "cmp.l", 56,
43570 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43572 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
43574 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "cmp.l", 64,
43575 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43577 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
43579 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "cmp.l", 64,
43580 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43582 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
43584 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "cmp.l", 48,
43585 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43587 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
43589 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "cmp.l", 48,
43590 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43592 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
43594 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "cmp.l", 56,
43595 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43597 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
43599 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "cmp.l", 56,
43600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43602 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
43604 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "cmp.l", 48,
43605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43607 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
43609 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "cmp.l", 48,
43610 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43612 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
43614 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "cmp.l", 56,
43615 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43617 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
43619 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "cmp.l", 56,
43620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43622 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
43624 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "cmp.l", 56,
43625 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43627 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u16} */
43629 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "cmp.l", 56,
43630 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43632 /* cmp.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
43634 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "cmp.l", 64,
43635 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43637 /* cmp.l${G} ${Dsp-16-u24},${Dsp-40-u24} */
43639 M32C_INSN_CMP32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "cmp.l", 64,
43640 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43642 /* cmp.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */
43644 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 16,
43645 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43647 /* cmp.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */
43649 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 16,
43650 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43652 /* cmp.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
43654 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 16,
43655 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43657 /* cmp.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */
43659 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 16,
43660 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43662 /* cmp.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */
43664 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 16,
43665 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43667 /* cmp.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
43669 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "cmp.l", 16,
43670 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43672 /* cmp.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */
43674 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 16,
43675 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43677 /* cmp.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */
43679 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 16,
43680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43682 /* cmp.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
43684 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "cmp.l", 16,
43685 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43687 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
43689 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "cmp.l", 24,
43690 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43692 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
43694 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "cmp.l", 24,
43695 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43697 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
43699 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "cmp.l", 24,
43700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43702 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
43704 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "cmp.l", 32,
43705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43707 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
43709 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "cmp.l", 32,
43710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43712 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
43714 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "cmp.l", 32,
43715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43717 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
43719 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "cmp.l", 40,
43720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43722 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
43724 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "cmp.l", 40,
43725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43727 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
43729 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "cmp.l", 40,
43730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43732 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */
43734 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "cmp.l", 24,
43735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43737 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */
43739 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "cmp.l", 24,
43740 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43742 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
43744 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "cmp.l", 24,
43745 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43747 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */
43749 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "cmp.l", 32,
43750 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43752 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */
43754 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "cmp.l", 32,
43755 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43757 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
43759 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "cmp.l", 32,
43760 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43762 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */
43764 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "cmp.l", 24,
43765 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43767 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */
43769 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "cmp.l", 24,
43770 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43772 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
43774 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "cmp.l", 24,
43775 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43777 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */
43779 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "cmp.l", 32,
43780 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43782 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */
43784 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "cmp.l", 32,
43785 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43787 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
43789 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "cmp.l", 32,
43790 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43792 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */
43794 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "cmp.l", 32,
43795 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43797 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */
43799 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "cmp.l", 32,
43800 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43802 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
43804 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "cmp.l", 32,
43805 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43807 /* cmp.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */
43809 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "cmp.l", 40,
43810 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43812 /* cmp.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */
43814 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "cmp.l", 40,
43815 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43817 /* cmp.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
43819 M32C_INSN_CMP32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "cmp.l", 40,
43820 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43822 /* cmp.b${S} ${SrcDst16-r0l-r0h-S-normal} */
43824 M32C_INSN_CMP16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, "cmp16.b.S-r0l-r0h-srcdst16-r0l-r0h-S-derived", "cmp.b", 8,
43825 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43827 /* cmp.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
43829 M32C_INSN_CMP16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, "cmp16.b.S-src2-src16-2-S-8-SB-relative-QI", "cmp.b", 16,
43830 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43832 /* cmp.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
43834 M32C_INSN_CMP16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, "cmp16.b.S-src2-src16-2-S-8-FB-relative-QI", "cmp.b", 16,
43835 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43837 /* cmp.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
43839 M32C_INSN_CMP16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, "cmp16.b.S-src2-src16-2-S-16-absolute-QI", "cmp.b", 24,
43840 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
43842 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
43844 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 24,
43845 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43847 /* cmp.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
43849 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 24,
43850 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43852 /* cmp.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
43854 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 24,
43855 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43857 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
43859 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 24,
43860 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43862 /* cmp.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
43864 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 24,
43865 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43867 /* cmp.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
43869 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 24,
43870 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43872 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
43874 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 24,
43875 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43877 /* cmp.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
43879 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 24,
43880 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43882 /* cmp.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
43884 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 24,
43885 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43887 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
43889 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "cmp.w", 32,
43890 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43892 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
43894 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "cmp.w", 32,
43895 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43897 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
43899 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "cmp.w", 32,
43900 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43902 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
43904 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "cmp.w", 40,
43905 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43907 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
43909 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "cmp.w", 40,
43910 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43912 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
43914 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "cmp.w", 40,
43915 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43917 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
43919 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "cmp.w", 48,
43920 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43922 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
43924 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "cmp.w", 48,
43925 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43927 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
43929 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "cmp.w", 48,
43930 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43932 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
43934 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "cmp.w", 32,
43935 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43937 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
43939 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "cmp.w", 32,
43940 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43942 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
43944 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "cmp.w", 32,
43945 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43947 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
43949 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "cmp.w", 40,
43950 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43952 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
43954 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "cmp.w", 40,
43955 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43957 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
43959 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "cmp.w", 40,
43960 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43962 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
43964 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "cmp.w", 32,
43965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43967 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
43969 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "cmp.w", 32,
43970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43972 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
43974 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "cmp.w", 32,
43975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43977 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
43979 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "cmp.w", 40,
43980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43982 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
43984 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "cmp.w", 40,
43985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43987 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
43989 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "cmp.w", 40,
43990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43992 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
43994 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "cmp.w", 40,
43995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
43997 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
43999 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "cmp.w", 40,
44000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44002 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
44004 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "cmp.w", 40,
44005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44007 /* cmp.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
44009 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "cmp.w", 48,
44010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44012 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
44014 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "cmp.w", 48,
44015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44017 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
44019 M32C_INSN_CMP32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "cmp.w", 48,
44020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44022 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
44024 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 32,
44025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44027 /* cmp.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
44029 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 32,
44030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44032 /* cmp.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
44034 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 32,
44035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44037 /* cmp.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
44039 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 32,
44040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44042 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
44044 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 32,
44045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44047 /* cmp.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
44049 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 32,
44050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44052 /* cmp.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
44054 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 32,
44055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44057 /* cmp.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
44059 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 32,
44060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44062 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
44064 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 32,
44065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44067 /* cmp.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
44069 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 32,
44070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44072 /* cmp.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
44074 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 32,
44075 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44077 /* cmp.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
44079 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 32,
44080 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44082 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
44084 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "cmp.w", 40,
44085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44087 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
44089 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "cmp.w", 40,
44090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44092 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
44094 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "cmp.w", 40,
44095 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44097 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
44099 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "cmp.w", 40,
44100 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44102 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
44104 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "cmp.w", 48,
44105 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44107 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
44109 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "cmp.w", 48,
44110 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44112 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
44114 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "cmp.w", 48,
44115 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44117 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
44119 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "cmp.w", 48,
44120 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44122 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
44124 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "cmp.w", 56,
44125 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44127 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
44129 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "cmp.w", 56,
44130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44132 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
44134 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "cmp.w", 56,
44135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44137 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
44139 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "cmp.w", 56,
44140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44142 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
44144 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "cmp.w", 40,
44145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44147 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
44149 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "cmp.w", 40,
44150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44152 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
44154 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "cmp.w", 40,
44155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44157 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
44159 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "cmp.w", 40,
44160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44162 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
44164 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "cmp.w", 48,
44165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44167 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
44169 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "cmp.w", 48,
44170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44172 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
44174 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "cmp.w", 48,
44175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44177 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
44179 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "cmp.w", 48,
44180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44182 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
44184 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "cmp.w", 40,
44185 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44187 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
44189 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "cmp.w", 40,
44190 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44192 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
44194 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "cmp.w", 40,
44195 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44197 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
44199 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "cmp.w", 40,
44200 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44202 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
44204 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "cmp.w", 48,
44205 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44207 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
44209 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "cmp.w", 48,
44210 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44212 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
44214 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "cmp.w", 48,
44215 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44217 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
44219 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "cmp.w", 48,
44220 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44222 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
44224 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "cmp.w", 48,
44225 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44227 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
44229 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "cmp.w", 48,
44230 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44232 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
44234 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "cmp.w", 48,
44235 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44237 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
44239 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "cmp.w", 48,
44240 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44242 /* cmp.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
44244 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "cmp.w", 56,
44245 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44247 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
44249 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "cmp.w", 56,
44250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44252 /* cmp.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
44254 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "cmp.w", 56,
44255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44257 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
44259 M32C_INSN_CMP32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "cmp.w", 56,
44260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44262 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
44264 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 40,
44265 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44267 /* cmp.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
44269 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 40,
44270 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44272 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
44274 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 40,
44275 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44277 /* cmp.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
44279 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 40,
44280 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44282 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
44284 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 40,
44285 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44287 /* cmp.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
44289 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 40,
44290 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44292 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
44294 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "cmp.w", 48,
44295 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44297 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
44299 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "cmp.w", 48,
44300 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44302 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
44304 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "cmp.w", 56,
44305 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44307 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
44309 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "cmp.w", 56,
44310 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44312 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
44314 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "cmp.w", 64,
44315 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44317 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
44319 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "cmp.w", 64,
44320 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44322 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
44324 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "cmp.w", 48,
44325 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44327 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
44329 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "cmp.w", 48,
44330 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44332 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
44334 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "cmp.w", 56,
44335 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44337 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
44339 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "cmp.w", 56,
44340 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44342 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
44344 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "cmp.w", 48,
44345 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44347 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
44349 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "cmp.w", 48,
44350 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44352 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
44354 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "cmp.w", 56,
44355 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44357 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
44359 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "cmp.w", 56,
44360 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44362 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
44364 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "cmp.w", 56,
44365 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44367 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
44369 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "cmp.w", 56,
44370 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44372 /* cmp.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
44374 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "cmp.w", 64,
44375 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44377 /* cmp.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
44379 M32C_INSN_CMP32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "cmp.w", 64,
44380 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44382 /* cmp.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
44384 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 16,
44385 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44387 /* cmp.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
44389 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 16,
44390 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44392 /* cmp.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
44394 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 16,
44395 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44397 /* cmp.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
44399 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 16,
44400 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44402 /* cmp.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
44404 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 16,
44405 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44407 /* cmp.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
44409 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "cmp.w", 16,
44410 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44412 /* cmp.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
44414 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 16,
44415 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44417 /* cmp.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
44419 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 16,
44420 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44422 /* cmp.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
44424 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "cmp.w", 16,
44425 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44427 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
44429 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "cmp.w", 24,
44430 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44432 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
44434 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "cmp.w", 24,
44435 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44437 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
44439 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "cmp.w", 24,
44440 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44442 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
44444 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "cmp.w", 32,
44445 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44447 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
44449 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "cmp.w", 32,
44450 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44452 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
44454 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "cmp.w", 32,
44455 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44457 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
44459 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "cmp.w", 40,
44460 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44462 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
44464 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "cmp.w", 40,
44465 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44467 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
44469 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "cmp.w", 40,
44470 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44472 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
44474 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "cmp.w", 24,
44475 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44477 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
44479 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "cmp.w", 24,
44480 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44482 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
44484 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "cmp.w", 24,
44485 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44487 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
44489 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "cmp.w", 32,
44490 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44492 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
44494 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "cmp.w", 32,
44495 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44497 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
44499 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "cmp.w", 32,
44500 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44502 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
44504 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "cmp.w", 24,
44505 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44507 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
44509 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "cmp.w", 24,
44510 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44512 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
44514 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "cmp.w", 24,
44515 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44517 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
44519 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "cmp.w", 32,
44520 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44522 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
44524 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "cmp.w", 32,
44525 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44527 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
44529 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "cmp.w", 32,
44530 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44532 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
44534 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "cmp.w", 32,
44535 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44537 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
44539 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "cmp.w", 32,
44540 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44542 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
44544 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "cmp.w", 32,
44545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44547 /* cmp.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
44549 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "cmp.w", 40,
44550 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44552 /* cmp.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
44554 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "cmp.w", 40,
44555 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44557 /* cmp.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
44559 M32C_INSN_CMP32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "cmp.w", 40,
44560 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44562 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
44564 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 24,
44565 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44567 /* cmp.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
44569 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 24,
44570 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44572 /* cmp.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
44574 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 24,
44575 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44577 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
44579 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 24,
44580 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44582 /* cmp.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
44584 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 24,
44585 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44587 /* cmp.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
44589 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 24,
44590 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44592 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
44594 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 24,
44595 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44597 /* cmp.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
44599 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 24,
44600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44602 /* cmp.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
44604 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 24,
44605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44607 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
44609 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "cmp.b", 32,
44610 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44612 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
44614 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "cmp.b", 32,
44615 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44617 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
44619 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "cmp.b", 32,
44620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44622 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
44624 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "cmp.b", 40,
44625 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44627 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
44629 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "cmp.b", 40,
44630 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44632 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
44634 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "cmp.b", 40,
44635 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44637 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
44639 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "cmp.b", 48,
44640 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44642 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
44644 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "cmp.b", 48,
44645 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44647 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
44649 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "cmp.b", 48,
44650 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44652 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
44654 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "cmp.b", 32,
44655 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44657 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
44659 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "cmp.b", 32,
44660 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44662 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
44664 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "cmp.b", 32,
44665 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44667 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
44669 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "cmp.b", 40,
44670 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44672 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
44674 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "cmp.b", 40,
44675 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44677 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
44679 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "cmp.b", 40,
44680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44682 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
44684 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "cmp.b", 32,
44685 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44687 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
44689 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "cmp.b", 32,
44690 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44692 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
44694 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "cmp.b", 32,
44695 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44697 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
44699 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "cmp.b", 40,
44700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44702 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
44704 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "cmp.b", 40,
44705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44707 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
44709 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "cmp.b", 40,
44710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44712 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
44714 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "cmp.b", 40,
44715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44717 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
44719 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "cmp.b", 40,
44720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44722 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
44724 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "cmp.b", 40,
44725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44727 /* cmp.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
44729 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "cmp.b", 48,
44730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44732 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
44734 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "cmp.b", 48,
44735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44737 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
44739 M32C_INSN_CMP32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "cmp.b", 48,
44740 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44742 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
44744 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 32,
44745 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44747 /* cmp.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
44749 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 32,
44750 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44752 /* cmp.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
44754 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 32,
44755 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44757 /* cmp.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
44759 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 32,
44760 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44762 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
44764 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 32,
44765 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44767 /* cmp.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
44769 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 32,
44770 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44772 /* cmp.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
44774 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 32,
44775 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44777 /* cmp.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
44779 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 32,
44780 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44782 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
44784 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 32,
44785 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44787 /* cmp.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
44789 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 32,
44790 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44792 /* cmp.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
44794 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 32,
44795 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44797 /* cmp.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
44799 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 32,
44800 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44802 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
44804 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "cmp.b", 40,
44805 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44807 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
44809 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "cmp.b", 40,
44810 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44812 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
44814 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "cmp.b", 40,
44815 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44817 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
44819 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "cmp.b", 40,
44820 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44822 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
44824 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "cmp.b", 48,
44825 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44827 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
44829 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "cmp.b", 48,
44830 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44832 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
44834 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "cmp.b", 48,
44835 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44837 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
44839 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "cmp.b", 48,
44840 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44842 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
44844 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "cmp.b", 56,
44845 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44847 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
44849 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "cmp.b", 56,
44850 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44852 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
44854 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "cmp.b", 56,
44855 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44857 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
44859 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "cmp.b", 56,
44860 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44862 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
44864 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "cmp.b", 40,
44865 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44867 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
44869 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "cmp.b", 40,
44870 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44872 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
44874 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "cmp.b", 40,
44875 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44877 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
44879 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "cmp.b", 40,
44880 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44882 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
44884 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "cmp.b", 48,
44885 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44887 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
44889 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "cmp.b", 48,
44890 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44892 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
44894 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "cmp.b", 48,
44895 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44897 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
44899 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "cmp.b", 48,
44900 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44902 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
44904 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "cmp.b", 40,
44905 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44907 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
44909 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "cmp.b", 40,
44910 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44912 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
44914 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "cmp.b", 40,
44915 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44917 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
44919 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "cmp.b", 40,
44920 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44922 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
44924 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "cmp.b", 48,
44925 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44927 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
44929 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "cmp.b", 48,
44930 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44932 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
44934 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "cmp.b", 48,
44935 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44937 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
44939 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "cmp.b", 48,
44940 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44942 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
44944 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "cmp.b", 48,
44945 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44947 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
44949 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "cmp.b", 48,
44950 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44952 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
44954 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "cmp.b", 48,
44955 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44957 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
44959 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "cmp.b", 48,
44960 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44962 /* cmp.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
44964 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "cmp.b", 56,
44965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44967 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
44969 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "cmp.b", 56,
44970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44972 /* cmp.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
44974 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "cmp.b", 56,
44975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44977 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
44979 M32C_INSN_CMP32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "cmp.b", 56,
44980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44982 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
44984 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 40,
44985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44987 /* cmp.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
44989 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 40,
44990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44992 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
44994 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 40,
44995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
44997 /* cmp.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
44999 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 40,
45000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45002 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
45004 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 40,
45005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45007 /* cmp.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
45009 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 40,
45010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45012 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
45014 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "cmp.b", 48,
45015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45017 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
45019 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "cmp.b", 48,
45020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45022 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
45024 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "cmp.b", 56,
45025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45027 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
45029 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "cmp.b", 56,
45030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45032 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
45034 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "cmp.b", 64,
45035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45037 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
45039 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "cmp.b", 64,
45040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45042 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
45044 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "cmp.b", 48,
45045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45047 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
45049 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "cmp.b", 48,
45050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45052 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
45054 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "cmp.b", 56,
45055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45057 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
45059 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "cmp.b", 56,
45060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45062 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
45064 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "cmp.b", 48,
45065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45067 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
45069 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "cmp.b", 48,
45070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45072 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
45074 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "cmp.b", 56,
45075 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45077 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
45079 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "cmp.b", 56,
45080 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45082 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
45084 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "cmp.b", 56,
45085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45087 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
45089 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "cmp.b", 56,
45090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45092 /* cmp.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
45094 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "cmp.b", 64,
45095 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45097 /* cmp.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
45099 M32C_INSN_CMP32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "cmp.b", 64,
45100 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45102 /* cmp.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
45104 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 16,
45105 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45107 /* cmp.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
45109 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 16,
45110 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45112 /* cmp.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
45114 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 16,
45115 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45117 /* cmp.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
45119 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 16,
45120 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45122 /* cmp.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
45124 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 16,
45125 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45127 /* cmp.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
45129 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "cmp.b", 16,
45130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45132 /* cmp.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
45134 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 16,
45135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45137 /* cmp.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
45139 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 16,
45140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45142 /* cmp.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
45144 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "cmp.b", 16,
45145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45147 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
45149 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "cmp.b", 24,
45150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45152 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
45154 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "cmp.b", 24,
45155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45157 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
45159 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "cmp.b", 24,
45160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45162 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
45164 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "cmp.b", 32,
45165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45167 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
45169 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "cmp.b", 32,
45170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45172 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
45174 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "cmp.b", 32,
45175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45177 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
45179 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "cmp.b", 40,
45180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45182 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
45184 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "cmp.b", 40,
45185 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45187 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
45189 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "cmp.b", 40,
45190 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45192 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
45194 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "cmp.b", 24,
45195 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45197 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
45199 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "cmp.b", 24,
45200 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45202 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
45204 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "cmp.b", 24,
45205 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45207 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
45209 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "cmp.b", 32,
45210 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45212 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
45214 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "cmp.b", 32,
45215 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45217 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
45219 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "cmp.b", 32,
45220 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45222 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
45224 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "cmp.b", 24,
45225 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45227 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
45229 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "cmp.b", 24,
45230 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45232 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
45234 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "cmp.b", 24,
45235 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45237 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
45239 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "cmp.b", 32,
45240 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45242 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
45244 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "cmp.b", 32,
45245 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45247 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
45249 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "cmp.b", 32,
45250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45252 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
45254 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "cmp.b", 32,
45255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45257 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
45259 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "cmp.b", 32,
45260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45262 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
45264 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "cmp.b", 32,
45265 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45267 /* cmp.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
45269 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "cmp.b", 40,
45270 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45272 /* cmp.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
45274 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "cmp.b", 40,
45275 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45277 /* cmp.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
45279 M32C_INSN_CMP32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "cmp.b", 40,
45280 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
45282 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
45284 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "cmp.w", 24,
45285 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45287 /* cmp.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
45289 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "cmp.w", 24,
45290 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45292 /* cmp.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
45294 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "cmp.w", 24,
45295 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45297 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
45299 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "cmp.w", 24,
45300 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45302 /* cmp.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
45304 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "cmp.w", 24,
45305 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45307 /* cmp.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
45309 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "cmp.w", 24,
45310 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45312 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
45314 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "cmp.w", 24,
45315 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45317 /* cmp.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
45319 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "cmp.w", 24,
45320 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45322 /* cmp.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
45324 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "cmp.w", 24,
45325 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45327 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
45329 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "cmp.w", 32,
45330 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45332 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
45334 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "cmp.w", 32,
45335 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45337 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
45339 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "cmp.w", 32,
45340 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45342 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
45344 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "cmp.w", 40,
45345 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45347 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
45349 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "cmp.w", 40,
45350 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45352 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
45354 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "cmp.w", 40,
45355 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45357 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
45359 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "cmp.w", 32,
45360 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45362 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
45364 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "cmp.w", 32,
45365 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45367 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
45369 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "cmp.w", 32,
45370 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45372 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
45374 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "cmp.w", 40,
45375 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45377 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
45379 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "cmp.w", 40,
45380 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45382 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
45384 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "cmp.w", 40,
45385 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45387 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
45389 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "cmp.w", 32,
45390 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45392 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
45394 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "cmp.w", 32,
45395 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45397 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
45399 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "cmp.w", 32,
45400 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45402 /* cmp.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
45404 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "cmp16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "cmp.w", 40,
45405 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45407 /* cmp.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
45409 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "cmp16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "cmp.w", 40,
45410 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45412 /* cmp.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
45414 M32C_INSN_CMP16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "cmp16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "cmp.w", 40,
45415 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45417 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
45419 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "cmp.w", 32,
45420 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45422 /* cmp.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
45424 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "cmp.w", 32,
45425 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45427 /* cmp.w${G} ${Dsp-16-u16},$Dst16RnHI */
45429 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "cmp.w", 32,
45430 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45432 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
45434 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "cmp.w", 32,
45435 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45437 /* cmp.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
45439 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "cmp.w", 32,
45440 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45442 /* cmp.w${G} ${Dsp-16-u16},$Dst16AnHI */
45444 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "cmp.w", 32,
45445 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45447 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
45449 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "cmp.w", 32,
45450 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45452 /* cmp.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
45454 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "cmp.w", 32,
45455 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45457 /* cmp.w${G} ${Dsp-16-u16},[$Dst16An] */
45459 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "cmp.w", 32,
45460 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45462 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
45464 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "cmp.w", 40,
45465 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45467 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
45469 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "cmp.w", 40,
45470 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45472 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
45474 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "cmp.w", 40,
45475 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45477 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
45479 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "cmp.w", 48,
45480 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45482 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
45484 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "cmp.w", 48,
45485 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45487 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
45489 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "cmp.w", 48,
45490 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45492 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
45494 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "cmp.w", 40,
45495 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45497 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
45499 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "cmp.w", 40,
45500 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45502 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
45504 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "cmp.w", 40,
45505 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45507 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
45509 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "cmp.w", 48,
45510 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45512 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
45514 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "cmp.w", 48,
45515 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45517 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
45519 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "cmp.w", 48,
45520 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45522 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
45524 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "cmp.w", 40,
45525 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45527 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
45529 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "cmp.w", 40,
45530 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45532 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
45534 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "cmp.w", 40,
45535 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45537 /* cmp.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
45539 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "cmp16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "cmp.w", 48,
45540 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45542 /* cmp.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
45544 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "cmp16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "cmp.w", 48,
45545 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45547 /* cmp.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
45549 M32C_INSN_CMP16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "cmp16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "cmp.w", 48,
45550 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45552 /* cmp.w${G} $Src16RnHI,$Dst16RnHI */
45554 M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "cmp.w", 16,
45555 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45557 /* cmp.w${G} $Src16AnHI,$Dst16RnHI */
45559 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "cmp.w", 16,
45560 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45562 /* cmp.w${G} [$Src16An],$Dst16RnHI */
45564 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "cmp.w", 16,
45565 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45567 /* cmp.w${G} $Src16RnHI,$Dst16AnHI */
45569 M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "cmp.w", 16,
45570 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45572 /* cmp.w${G} $Src16AnHI,$Dst16AnHI */
45574 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "cmp.w", 16,
45575 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45577 /* cmp.w${G} [$Src16An],$Dst16AnHI */
45579 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "cmp.w", 16,
45580 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45582 /* cmp.w${G} $Src16RnHI,[$Dst16An] */
45584 M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "cmp.w", 16,
45585 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45587 /* cmp.w${G} $Src16AnHI,[$Dst16An] */
45589 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "cmp.w", 16,
45590 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45592 /* cmp.w${G} [$Src16An],[$Dst16An] */
45594 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "cmp.w", 16,
45595 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45597 /* cmp.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
45599 M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "cmp.w", 24,
45600 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45602 /* cmp.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
45604 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "cmp.w", 24,
45605 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45607 /* cmp.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
45609 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "cmp.w", 24,
45610 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45612 /* cmp.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
45614 M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "cmp.w", 32,
45615 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45617 /* cmp.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
45619 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "cmp.w", 32,
45620 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45622 /* cmp.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
45624 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "cmp.w", 32,
45625 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45627 /* cmp.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
45629 M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "cmp.w", 24,
45630 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45632 /* cmp.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
45634 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "cmp.w", 24,
45635 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45637 /* cmp.w${G} [$Src16An],${Dsp-16-u8}[sb] */
45639 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "cmp.w", 24,
45640 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45642 /* cmp.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
45644 M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "cmp.w", 32,
45645 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45647 /* cmp.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
45649 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "cmp.w", 32,
45650 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45652 /* cmp.w${G} [$Src16An],${Dsp-16-u16}[sb] */
45654 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "cmp.w", 32,
45655 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45657 /* cmp.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
45659 M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "cmp.w", 24,
45660 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45662 /* cmp.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
45664 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "cmp.w", 24,
45665 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45667 /* cmp.w${G} [$Src16An],${Dsp-16-s8}[fb] */
45669 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "cmp.w", 24,
45670 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45672 /* cmp.w${G} $Src16RnHI,${Dsp-16-u16} */
45674 M32C_INSN_CMP16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "cmp16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "cmp.w", 32,
45675 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45677 /* cmp.w${G} $Src16AnHI,${Dsp-16-u16} */
45679 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "cmp16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "cmp.w", 32,
45680 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45682 /* cmp.w${G} [$Src16An],${Dsp-16-u16} */
45684 M32C_INSN_CMP16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "cmp16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "cmp.w", 32,
45685 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45687 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
45689 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "cmp.b", 24,
45690 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45692 /* cmp.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
45694 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "cmp.b", 24,
45695 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45697 /* cmp.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
45699 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "cmp.b", 24,
45700 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45702 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
45704 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "cmp.b", 24,
45705 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45707 /* cmp.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
45709 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "cmp.b", 24,
45710 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45712 /* cmp.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
45714 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "cmp.b", 24,
45715 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45717 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
45719 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "cmp.b", 24,
45720 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45722 /* cmp.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
45724 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "cmp.b", 24,
45725 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45727 /* cmp.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
45729 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "cmp.b", 24,
45730 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45732 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
45734 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "cmp.b", 32,
45735 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45737 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
45739 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "cmp.b", 32,
45740 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45742 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
45744 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "cmp.b", 32,
45745 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45747 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
45749 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "cmp.b", 40,
45750 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45752 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
45754 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "cmp.b", 40,
45755 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45757 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
45759 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "cmp.b", 40,
45760 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45762 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
45764 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "cmp.b", 32,
45765 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45767 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
45769 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "cmp.b", 32,
45770 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45772 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
45774 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "cmp.b", 32,
45775 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45777 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
45779 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "cmp.b", 40,
45780 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45782 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
45784 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "cmp.b", 40,
45785 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45787 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
45789 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "cmp.b", 40,
45790 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45792 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
45794 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "cmp.b", 32,
45795 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45797 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
45799 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "cmp.b", 32,
45800 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45802 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
45804 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "cmp.b", 32,
45805 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45807 /* cmp.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
45809 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "cmp16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "cmp.b", 40,
45810 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45812 /* cmp.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
45814 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "cmp16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "cmp.b", 40,
45815 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45817 /* cmp.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
45819 M32C_INSN_CMP16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "cmp16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "cmp.b", 40,
45820 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45822 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
45824 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "cmp.b", 32,
45825 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45827 /* cmp.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
45829 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "cmp.b", 32,
45830 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45832 /* cmp.b${G} ${Dsp-16-u16},$Dst16RnQI */
45834 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "cmp.b", 32,
45835 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45837 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
45839 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "cmp.b", 32,
45840 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45842 /* cmp.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
45844 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "cmp.b", 32,
45845 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45847 /* cmp.b${G} ${Dsp-16-u16},$Dst16AnQI */
45849 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "cmp.b", 32,
45850 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45852 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
45854 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "cmp.b", 32,
45855 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45857 /* cmp.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
45859 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "cmp.b", 32,
45860 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45862 /* cmp.b${G} ${Dsp-16-u16},[$Dst16An] */
45864 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "cmp.b", 32,
45865 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45867 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
45869 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "cmp.b", 40,
45870 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45872 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
45874 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "cmp.b", 40,
45875 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45877 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
45879 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "cmp.b", 40,
45880 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45882 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
45884 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "cmp.b", 48,
45885 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45887 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
45889 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "cmp.b", 48,
45890 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45892 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
45894 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "cmp.b", 48,
45895 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45897 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
45899 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "cmp.b", 40,
45900 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45902 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
45904 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "cmp.b", 40,
45905 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45907 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
45909 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "cmp.b", 40,
45910 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45912 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
45914 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "cmp.b", 48,
45915 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45917 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
45919 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "cmp.b", 48,
45920 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45922 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
45924 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "cmp.b", 48,
45925 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45927 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
45929 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "cmp.b", 40,
45930 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45932 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
45934 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "cmp.b", 40,
45935 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45937 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
45939 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "cmp.b", 40,
45940 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45942 /* cmp.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
45944 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "cmp16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "cmp.b", 48,
45945 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45947 /* cmp.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
45949 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "cmp16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "cmp.b", 48,
45950 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45952 /* cmp.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
45954 M32C_INSN_CMP16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "cmp16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "cmp.b", 48,
45955 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45957 /* cmp.b${G} $Src16RnQI,$Dst16RnQI */
45959 M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "cmp.b", 16,
45960 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45962 /* cmp.b${G} $Src16AnQI,$Dst16RnQI */
45964 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "cmp.b", 16,
45965 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45967 /* cmp.b${G} [$Src16An],$Dst16RnQI */
45969 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "cmp.b", 16,
45970 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45972 /* cmp.b${G} $Src16RnQI,$Dst16AnQI */
45974 M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "cmp.b", 16,
45975 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45977 /* cmp.b${G} $Src16AnQI,$Dst16AnQI */
45979 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "cmp.b", 16,
45980 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45982 /* cmp.b${G} [$Src16An],$Dst16AnQI */
45984 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "cmp.b", 16,
45985 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45987 /* cmp.b${G} $Src16RnQI,[$Dst16An] */
45989 M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "cmp.b", 16,
45990 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45992 /* cmp.b${G} $Src16AnQI,[$Dst16An] */
45994 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "cmp.b", 16,
45995 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
45997 /* cmp.b${G} [$Src16An],[$Dst16An] */
45999 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "cmp.b", 16,
46000 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46002 /* cmp.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
46004 M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "cmp.b", 24,
46005 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46007 /* cmp.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
46009 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "cmp.b", 24,
46010 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46012 /* cmp.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
46014 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "cmp.b", 24,
46015 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46017 /* cmp.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
46019 M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "cmp.b", 32,
46020 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46022 /* cmp.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
46024 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "cmp.b", 32,
46025 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46027 /* cmp.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
46029 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "cmp.b", 32,
46030 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46032 /* cmp.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
46034 M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "cmp.b", 24,
46035 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46037 /* cmp.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
46039 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "cmp.b", 24,
46040 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46042 /* cmp.b${G} [$Src16An],${Dsp-16-u8}[sb] */
46044 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "cmp.b", 24,
46045 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46047 /* cmp.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
46049 M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "cmp.b", 32,
46050 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46052 /* cmp.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
46054 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "cmp.b", 32,
46055 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46057 /* cmp.b${G} [$Src16An],${Dsp-16-u16}[sb] */
46059 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "cmp.b", 32,
46060 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46062 /* cmp.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
46064 M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "cmp.b", 24,
46065 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46067 /* cmp.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
46069 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "cmp.b", 24,
46070 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46072 /* cmp.b${G} [$Src16An],${Dsp-16-s8}[fb] */
46074 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "cmp.b", 24,
46075 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46077 /* cmp.b${G} $Src16RnQI,${Dsp-16-u16} */
46079 M32C_INSN_CMP16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "cmp16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "cmp.b", 32,
46080 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46082 /* cmp.b${G} $Src16AnQI,${Dsp-16-u16} */
46084 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "cmp16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "cmp.b", 32,
46085 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46087 /* cmp.b${G} [$Src16An],${Dsp-16-u16} */
46089 M32C_INSN_CMP16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "cmp16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "cmp.b", 32,
46090 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46092 /* cmp.b${S} #${Imm-8-QI},r0l */
46094 M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "cmp16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "cmp.b", 16,
46095 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46097 /* cmp.b${S} #${Imm-8-QI},r0h */
46099 M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "cmp16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "cmp.b", 16,
46100 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46102 /* cmp.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
46104 M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "cmp16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "cmp.b", 24,
46105 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46107 /* cmp.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
46109 M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "cmp16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "cmp.b", 24,
46110 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46112 /* cmp.b${S} #${Imm-8-QI},${Dsp-16-u16} */
46114 M32C_INSN_CMP16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "cmp16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "cmp.b", 32,
46115 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46117 /* cmp.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */
46119 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 16,
46120 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46122 /* cmp.w${Q} #${Imm-12-s4},$Dst32AnUnprefixedHI */
46124 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "cmp.w", 16,
46125 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46127 /* cmp.w${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
46129 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "cmp.w", 16,
46130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46132 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
46134 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "cmp.w", 24,
46135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46137 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
46139 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "cmp.w", 32,
46140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46142 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
46144 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "cmp.w", 40,
46145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46147 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
46149 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "cmp.w", 24,
46150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46152 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
46154 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "cmp.w", 32,
46155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46157 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
46159 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "cmp.w", 24,
46160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46162 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
46164 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "cmp.w", 32,
46165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46167 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u16} */
46169 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "cmp.w", 32,
46170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46172 /* cmp.w${Q} #${Imm-12-s4},${Dsp-16-u24} */
46174 M32C_INSN_CMP32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "cmp.w", 40,
46175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46177 /* cmp.b${Q} #${Imm-12-s4},$Dst32RnUnprefixedQI */
46179 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 16,
46180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46182 /* cmp.b${Q} #${Imm-12-s4},$Dst32AnUnprefixedQI */
46184 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "cmp.b", 16,
46185 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46187 /* cmp.b${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
46189 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "cmp.b", 16,
46190 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46192 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
46194 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "cmp.b", 24,
46195 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46197 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
46199 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "cmp.b", 32,
46200 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46202 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
46204 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "cmp.b", 40,
46205 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46207 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
46209 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "cmp.b", 24,
46210 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46212 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
46214 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "cmp.b", 32,
46215 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46217 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
46219 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "cmp.b", 24,
46220 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46222 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
46224 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "cmp.b", 32,
46225 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46227 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u16} */
46229 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "cmp.b", 32,
46230 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46232 /* cmp.b${Q} #${Imm-12-s4},${Dsp-16-u24} */
46234 M32C_INSN_CMP32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "cmp.b", 40,
46235 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46237 /* cmp.w${Q} #${Imm-8-s4},$Dst16RnHI */
46239 M32C_INSN_CMP16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "cmp16.w-imm4-Q-16-dst16-Rn-direct-HI", "cmp.w", 16,
46240 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46242 /* cmp.w${Q} #${Imm-8-s4},$Dst16AnHI */
46244 M32C_INSN_CMP16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "cmp16.w-imm4-Q-16-dst16-An-direct-HI", "cmp.w", 16,
46245 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46247 /* cmp.w${Q} #${Imm-8-s4},[$Dst16An] */
46249 M32C_INSN_CMP16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "cmp16.w-imm4-Q-16-dst16-An-indirect-HI", "cmp.w", 16,
46250 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46252 /* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
46254 M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "cmp16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "cmp.w", 24,
46255 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46257 /* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
46259 M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "cmp16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "cmp.w", 32,
46260 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46262 /* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
46264 M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "cmp16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "cmp.w", 24,
46265 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46267 /* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
46269 M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "cmp16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "cmp.w", 32,
46270 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46272 /* cmp.w${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
46274 M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "cmp16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "cmp.w", 24,
46275 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46277 /* cmp.w${Q} #${Imm-8-s4},${Dsp-16-u16} */
46279 M32C_INSN_CMP16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "cmp16.w-imm4-Q-16-dst16-16-16-absolute-HI", "cmp.w", 32,
46280 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46282 /* cmp.b${Q} #${Imm-8-s4},$Dst16RnQI */
46284 M32C_INSN_CMP16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "cmp16.b-imm4-Q-16-dst16-Rn-direct-QI", "cmp.b", 16,
46285 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46287 /* cmp.b${Q} #${Imm-8-s4},$Dst16AnQI */
46289 M32C_INSN_CMP16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "cmp16.b-imm4-Q-16-dst16-An-direct-QI", "cmp.b", 16,
46290 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46292 /* cmp.b${Q} #${Imm-8-s4},[$Dst16An] */
46294 M32C_INSN_CMP16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "cmp16.b-imm4-Q-16-dst16-An-indirect-QI", "cmp.b", 16,
46295 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46297 /* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
46299 M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "cmp16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "cmp.b", 24,
46300 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46302 /* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
46304 M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "cmp16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "cmp.b", 32,
46305 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46307 /* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
46309 M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "cmp16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "cmp.b", 24,
46310 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46312 /* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
46314 M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "cmp16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "cmp.b", 32,
46315 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46317 /* cmp.b${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
46319 M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "cmp16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "cmp.b", 24,
46320 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46322 /* cmp.b${Q} #${Imm-8-s4},${Dsp-16-u16} */
46324 M32C_INSN_CMP16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "cmp16.b-imm4-Q-16-dst16-16-16-absolute-QI", "cmp.b", 32,
46325 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46327 /* cmp.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
46329 M32C_INSN_CMP32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "cmp32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "cmp.w", 32,
46330 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46332 /* cmp.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
46334 M32C_INSN_CMP32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "cmp32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "cmp.w", 32,
46335 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46337 /* cmp.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
46339 M32C_INSN_CMP32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "cmp32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "cmp.w", 32,
46340 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46342 /* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
46344 M32C_INSN_CMP32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "cmp.w", 40,
46345 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46347 /* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
46349 M32C_INSN_CMP32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "cmp.w", 40,
46350 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46352 /* cmp.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
46354 M32C_INSN_CMP32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "cmp.w", 40,
46355 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46357 /* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
46359 M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "cmp.w", 48,
46360 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46362 /* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
46364 M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "cmp.w", 48,
46365 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46367 /* cmp.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
46369 M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "cmp.w", 48,
46370 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46372 /* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16} */
46374 M32C_INSN_CMP32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "cmp.w", 48,
46375 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46377 /* cmp.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
46379 M32C_INSN_CMP32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "cmp32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "cmp.w", 56,
46380 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46382 /* cmp.w${G} #${Imm-40-HI},${Dsp-16-u24} */
46384 M32C_INSN_CMP32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "cmp32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "cmp.w", 56,
46385 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46387 /* cmp.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
46389 M32C_INSN_CMP32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "cmp32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "cmp.b", 24,
46390 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46392 /* cmp.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
46394 M32C_INSN_CMP32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "cmp32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "cmp.b", 24,
46395 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46397 /* cmp.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
46399 M32C_INSN_CMP32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "cmp32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "cmp.b", 24,
46400 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46402 /* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
46404 M32C_INSN_CMP32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "cmp.b", 32,
46405 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46407 /* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
46409 M32C_INSN_CMP32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "cmp.b", 32,
46410 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46412 /* cmp.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
46414 M32C_INSN_CMP32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "cmp.b", 32,
46415 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46417 /* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
46419 M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "cmp.b", 40,
46420 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46422 /* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
46424 M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "cmp.b", 40,
46425 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46427 /* cmp.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
46429 M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "cmp.b", 40,
46430 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46432 /* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16} */
46434 M32C_INSN_CMP32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "cmp.b", 40,
46435 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46437 /* cmp.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
46439 M32C_INSN_CMP32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "cmp32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "cmp.b", 48,
46440 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46442 /* cmp.b${G} #${Imm-40-QI},${Dsp-16-u24} */
46444 M32C_INSN_CMP32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "cmp32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "cmp.b", 48,
46445 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46447 /* cmp.w${G} #${Imm-16-HI},$Dst16RnHI */
46449 M32C_INSN_CMP16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "cmp16.w-imm-G-basic-dst16-Rn-direct-HI", "cmp.w", 32,
46450 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46452 /* cmp.w${G} #${Imm-16-HI},$Dst16AnHI */
46454 M32C_INSN_CMP16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "cmp16.w-imm-G-basic-dst16-An-direct-HI", "cmp.w", 32,
46455 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46457 /* cmp.w${G} #${Imm-16-HI},[$Dst16An] */
46459 M32C_INSN_CMP16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "cmp16.w-imm-G-basic-dst16-An-indirect-HI", "cmp.w", 32,
46460 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46462 /* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
46464 M32C_INSN_CMP16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "cmp16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "cmp.w", 40,
46465 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46467 /* cmp.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
46469 M32C_INSN_CMP16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "cmp16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "cmp.w", 40,
46470 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46472 /* cmp.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
46474 M32C_INSN_CMP16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "cmp16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "cmp.w", 40,
46475 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46477 /* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
46479 M32C_INSN_CMP16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "cmp16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "cmp.w", 48,
46480 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46482 /* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
46484 M32C_INSN_CMP16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "cmp16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "cmp.w", 48,
46485 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46487 /* cmp.w${G} #${Imm-32-HI},${Dsp-16-u16} */
46489 M32C_INSN_CMP16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "cmp16.w-imm-G-16-16-dst16-16-16-absolute-HI", "cmp.w", 48,
46490 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46492 /* cmp.b${G} #${Imm-16-QI},$Dst16RnQI */
46494 M32C_INSN_CMP16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "cmp16.b-imm-G-basic-dst16-Rn-direct-QI", "cmp.b", 24,
46495 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46497 /* cmp.b${G} #${Imm-16-QI},$Dst16AnQI */
46499 M32C_INSN_CMP16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "cmp16.b-imm-G-basic-dst16-An-direct-QI", "cmp.b", 24,
46500 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46502 /* cmp.b${G} #${Imm-16-QI},[$Dst16An] */
46504 M32C_INSN_CMP16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "cmp16.b-imm-G-basic-dst16-An-indirect-QI", "cmp.b", 24,
46505 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46507 /* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
46509 M32C_INSN_CMP16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "cmp16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "cmp.b", 32,
46510 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46512 /* cmp.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
46514 M32C_INSN_CMP16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "cmp16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "cmp.b", 32,
46515 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46517 /* cmp.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
46519 M32C_INSN_CMP16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "cmp16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "cmp.b", 32,
46520 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46522 /* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
46524 M32C_INSN_CMP16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "cmp16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "cmp.b", 40,
46525 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46527 /* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
46529 M32C_INSN_CMP16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "cmp16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "cmp.b", 40,
46530 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46532 /* cmp.b${G} #${Imm-32-QI},${Dsp-16-u16} */
46534 M32C_INSN_CMP16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "cmp16.b-imm-G-16-16-dst16-16-16-absolute-QI", "cmp.b", 40,
46535 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46537 /* cmp.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */
46539 M32C_INSN_CMP32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "cmp32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "cmp.l", 48,
46540 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46542 /* cmp.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */
46544 M32C_INSN_CMP32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "cmp32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "cmp.l", 48,
46545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46547 /* cmp.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */
46549 M32C_INSN_CMP32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "cmp32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "cmp.l", 48,
46550 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46552 /* cmp.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
46554 M32C_INSN_CMP32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "cmp.l", 56,
46555 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46557 /* cmp.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */
46559 M32C_INSN_CMP32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "cmp.l", 56,
46560 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46562 /* cmp.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */
46564 M32C_INSN_CMP32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "cmp.l", 56,
46565 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46567 /* cmp.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
46569 M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "cmp.l", 64,
46570 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46572 /* cmp.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */
46574 M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "cmp.l", 64,
46575 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46577 /* cmp.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */
46579 M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "cmp.l", 64,
46580 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46582 /* cmp.l${G} #${Imm-32-SI},${Dsp-16-u16} */
46584 M32C_INSN_CMP32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "cmp.l", 64,
46585 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46587 /* cmp.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
46589 M32C_INSN_CMP32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "cmp32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "cmp.l", 72,
46590 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46592 /* cmp.l${G} #${Imm-40-SI},${Dsp-16-u24} */
46594 M32C_INSN_CMP32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "cmp32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "cmp.l", 72,
46595 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46597 /* clip.w #${Imm-24-HI},#${Imm-40-HI},$Dst32RnPrefixedHI */
46599 M32C_INSN_CLIP32_W_IMM_24_HI_IMM_40_HI_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "clip32.w-Imm-24-HI-Imm-40-HI-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "clip.w", 56,
46600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46602 /* clip.w #${Imm-24-HI},#${Imm-40-HI},$Dst32AnPrefixedHI */
46604 M32C_INSN_CLIP32_W_IMM_24_HI_IMM_40_HI_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "clip32.w-Imm-24-HI-Imm-40-HI-basic-Prefixed-dst32-An-direct-Prefixed-HI", "clip.w", 56,
46605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46607 /* clip.w #${Imm-24-HI},#${Imm-40-HI},[$Dst32AnPrefixed] */
46609 M32C_INSN_CLIP32_W_IMM_24_HI_IMM_40_HI_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "clip32.w-Imm-24-HI-Imm-40-HI-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "clip.w", 56,
46610 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46612 /* clip.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
46614 M32C_INSN_CLIP32_W_IMM_32_HI_IMM_48_HI_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "clip32.w-Imm-32-HI-Imm-48-HI-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "clip.w", 64,
46615 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46617 /* clip.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-24-u8}[sb] */
46619 M32C_INSN_CLIP32_W_IMM_32_HI_IMM_48_HI_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "clip32.w-Imm-32-HI-Imm-48-HI-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "clip.w", 64,
46620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46622 /* clip.w #${Imm-32-HI},#${Imm-48-HI},${Dsp-24-s8}[fb] */
46624 M32C_INSN_CLIP32_W_IMM_32_HI_IMM_48_HI_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "clip32.w-Imm-32-HI-Imm-48-HI-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "clip.w", 64,
46625 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46627 /* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
46629 M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "clip32.w-Imm-40-HI-Imm-56-HI-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "clip.w", 72,
46630 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46632 /* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-u16}[sb] */
46634 M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "clip32.w-Imm-40-HI-Imm-56-HI-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "clip.w", 72,
46635 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46637 /* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-s16}[fb] */
46639 M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "clip32.w-Imm-40-HI-Imm-56-HI-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "clip.w", 72,
46640 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46642 /* clip.w #${Imm-40-HI},#${Imm-56-HI},${Dsp-24-u16} */
46644 M32C_INSN_CLIP32_W_IMM_40_HI_IMM_56_HI_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "clip32.w-Imm-40-HI-Imm-56-HI-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "clip.w", 72,
46645 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46647 /* clip.w #${Imm-48-HI},#${Imm-64-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
46649 M32C_INSN_CLIP32_W_IMM_48_HI_IMM_64_HI_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "clip32.w-Imm-48-HI-Imm-64-HI-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "clip.w", 80,
46650 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46652 /* clip.w #${Imm-48-HI},#${Imm-64-HI},${Dsp-24-u24} */
46654 M32C_INSN_CLIP32_W_IMM_48_HI_IMM_64_HI_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "clip32.w-Imm-48-HI-Imm-64-HI-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "clip.w", 80,
46655 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46657 /* clip.b #${Imm-24-QI},#${Imm-32-QI},$Dst32RnPrefixedQI */
46659 M32C_INSN_CLIP32_B_IMM_24_QI_IMM_32_QI_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "clip32.b-Imm-24-QI-Imm-32-QI-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "clip.b", 40,
46660 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46662 /* clip.b #${Imm-24-QI},#${Imm-32-QI},$Dst32AnPrefixedQI */
46664 M32C_INSN_CLIP32_B_IMM_24_QI_IMM_32_QI_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "clip32.b-Imm-24-QI-Imm-32-QI-basic-Prefixed-dst32-An-direct-Prefixed-QI", "clip.b", 40,
46665 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46667 /* clip.b #${Imm-24-QI},#${Imm-32-QI},[$Dst32AnPrefixed] */
46669 M32C_INSN_CLIP32_B_IMM_24_QI_IMM_32_QI_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "clip32.b-Imm-24-QI-Imm-32-QI-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "clip.b", 40,
46670 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46672 /* clip.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
46674 M32C_INSN_CLIP32_B_IMM_32_QI_IMM_40_QI_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "clip32.b-Imm-32-QI-Imm-40-QI-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "clip.b", 48,
46675 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46677 /* clip.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-24-u8}[sb] */
46679 M32C_INSN_CLIP32_B_IMM_32_QI_IMM_40_QI_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "clip32.b-Imm-32-QI-Imm-40-QI-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "clip.b", 48,
46680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46682 /* clip.b #${Imm-32-QI},#${Imm-40-QI},${Dsp-24-s8}[fb] */
46684 M32C_INSN_CLIP32_B_IMM_32_QI_IMM_40_QI_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "clip32.b-Imm-32-QI-Imm-40-QI-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "clip.b", 48,
46685 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46687 /* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
46689 M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "clip32.b-Imm-40-QI-Imm-48-QI-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "clip.b", 56,
46690 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46692 /* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-u16}[sb] */
46694 M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "clip32.b-Imm-40-QI-Imm-48-QI-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "clip.b", 56,
46695 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46697 /* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-s16}[fb] */
46699 M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "clip32.b-Imm-40-QI-Imm-48-QI-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "clip.b", 56,
46700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46702 /* clip.b #${Imm-40-QI},#${Imm-48-QI},${Dsp-24-u16} */
46704 M32C_INSN_CLIP32_B_IMM_40_QI_IMM_48_QI_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "clip32.b-Imm-40-QI-Imm-48-QI-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "clip.b", 56,
46705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46707 /* clip.b #${Imm-48-QI},#${Imm-56-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
46709 M32C_INSN_CLIP32_B_IMM_48_QI_IMM_56_QI_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "clip32.b-Imm-48-QI-Imm-56-QI-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "clip.b", 64,
46710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46712 /* clip.b #${Imm-48-QI},#${Imm-56-QI},${Dsp-24-u24} */
46714 M32C_INSN_CLIP32_B_IMM_48_QI_IMM_56_QI_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "clip32.b-Imm-48-QI-Imm-56-QI-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "clip.b", 64,
46715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46717 /* bxor${X} $Bitno32Prefixed,$Bit32RnPrefixed */
46719 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bxor", 24,
46720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46722 /* bxor${X} $Bitno32Prefixed,$Bit32AnPrefixed */
46724 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bxor", 24,
46725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46727 /* bxor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
46729 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bxor", 24,
46730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46732 /* bxor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
46734 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bxor", 32,
46735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46737 /* bxor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
46739 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bxor", 40,
46740 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46742 /* bxor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
46744 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bxor", 48,
46745 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46747 /* bxor${X} ${BitBase32-24-u11-Prefixed}[sb] */
46749 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bxor", 32,
46750 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46752 /* bxor${X} ${BitBase32-24-u19-Prefixed}[sb] */
46754 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bxor", 40,
46755 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46757 /* bxor${X} ${BitBase32-24-s11-Prefixed}[fb] */
46759 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bxor", 32,
46760 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46762 /* bxor${X} ${BitBase32-24-s19-Prefixed}[fb] */
46764 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bxor", 40,
46765 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46767 /* bxor${X} ${BitBase32-24-u19-Prefixed} */
46769 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bxor", 40,
46770 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46772 /* bxor${X} ${BitBase32-24-u27-Prefixed} */
46774 M32C_INSN_BXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bxor32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bxor", 48,
46775 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46777 /* bxor${X} $Bitno16R,$Bit16Rn */
46779 M32C_INSN_BXOR16_X_BIT16_16_BIT16_RN_DIRECT, "bxor16-X-bit16-16-bit16-Rn-direct", "bxor", 24,
46780 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46782 /* bxor${X} $Bitno16R,$Bit16An */
46784 M32C_INSN_BXOR16_X_BIT16_16_BIT16_AN_DIRECT, "bxor16-X-bit16-16-bit16-An-direct", "bxor", 24,
46785 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46787 /* bxor${X} [$Bit16An] */
46789 M32C_INSN_BXOR16_X_BIT16_16_BIT16_AN_INDIRECT, "bxor16-X-bit16-16-bit16-An-indirect", "bxor", 16,
46790 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46792 /* bxor${X} ${Dsp-16-u8}[$Bit16An] */
46794 M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bxor16-X-bit16-16-bit16-16-8-An-relative", "bxor", 24,
46795 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46797 /* bxor${X} ${Dsp-16-u16}[$Bit16An] */
46799 M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bxor16-X-bit16-16-bit16-16-16-An-relative", "bxor", 32,
46800 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46802 /* bxor${X} ${BitBase16-16-u8}[sb] */
46804 M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bxor16-X-bit16-16-bit16-16-8-SB-relative", "bxor", 24,
46805 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46807 /* bxor${X} ${BitBase16-16-u16}[sb] */
46809 M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bxor16-X-bit16-16-bit16-16-16-SB-relative", "bxor", 32,
46810 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46812 /* bxor${X} ${BitBase16-16-s8}[fb] */
46814 M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bxor16-X-bit16-16-bit16-16-8-FB-relative", "bxor", 24,
46815 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46817 /* bxor${X} ${BitBase16-16-u16} */
46819 M32C_INSN_BXOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bxor16-X-bit16-16-bit16-16-16-absolute", "bxor", 32,
46820 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46822 /* btsts${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
46824 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "btsts", 16,
46825 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46827 /* btsts${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
46829 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "btsts", 16,
46830 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46832 /* btsts${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
46834 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "btsts", 16,
46835 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46837 /* btsts${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
46839 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "btsts", 24,
46840 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46842 /* btsts${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
46844 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "btsts", 32,
46845 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46847 /* btsts${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
46849 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "btsts", 40,
46850 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46852 /* btsts${X} ${BitBase32-16-u11-Unprefixed}[sb] */
46854 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "btsts", 24,
46855 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46857 /* btsts${X} ${BitBase32-16-u19-Unprefixed}[sb] */
46859 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "btsts", 32,
46860 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46862 /* btsts${X} ${BitBase32-16-s11-Unprefixed}[fb] */
46864 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "btsts", 24,
46865 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46867 /* btsts${X} ${BitBase32-16-s19-Unprefixed}[fb] */
46869 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "btsts", 32,
46870 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46872 /* btsts${X} ${BitBase32-16-u19-Unprefixed} */
46874 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "btsts", 32,
46875 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46877 /* btsts${X} ${BitBase32-16-u27-Unprefixed} */
46879 M32C_INSN_BTSTS32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "btsts32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "btsts", 40,
46880 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46882 /* btsts${X} $Bitno16R,$Bit16Rn */
46884 M32C_INSN_BTSTS16_X_BIT16_16_BIT16_RN_DIRECT, "btsts16-X-bit16-16-bit16-Rn-direct", "btsts", 24,
46885 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46887 /* btsts${X} $Bitno16R,$Bit16An */
46889 M32C_INSN_BTSTS16_X_BIT16_16_BIT16_AN_DIRECT, "btsts16-X-bit16-16-bit16-An-direct", "btsts", 24,
46890 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46892 /* btsts${X} [$Bit16An] */
46894 M32C_INSN_BTSTS16_X_BIT16_16_BIT16_AN_INDIRECT, "btsts16-X-bit16-16-bit16-An-indirect", "btsts", 16,
46895 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46897 /* btsts${X} ${Dsp-16-u8}[$Bit16An] */
46899 M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "btsts16-X-bit16-16-bit16-16-8-An-relative", "btsts", 24,
46900 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46902 /* btsts${X} ${Dsp-16-u16}[$Bit16An] */
46904 M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "btsts16-X-bit16-16-bit16-16-16-An-relative", "btsts", 32,
46905 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46907 /* btsts${X} ${BitBase16-16-u8}[sb] */
46909 M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "btsts16-X-bit16-16-bit16-16-8-SB-relative", "btsts", 24,
46910 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46912 /* btsts${X} ${BitBase16-16-u16}[sb] */
46914 M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "btsts16-X-bit16-16-bit16-16-16-SB-relative", "btsts", 32,
46915 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46917 /* btsts${X} ${BitBase16-16-s8}[fb] */
46919 M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "btsts16-X-bit16-16-bit16-16-8-FB-relative", "btsts", 24,
46920 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46922 /* btsts${X} ${BitBase16-16-u16} */
46924 M32C_INSN_BTSTS16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "btsts16-X-bit16-16-bit16-16-16-absolute", "btsts", 32,
46925 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46927 /* btstc${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
46929 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "btstc", 16,
46930 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46932 /* btstc${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
46934 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "btstc", 16,
46935 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46937 /* btstc${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
46939 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "btstc", 16,
46940 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46942 /* btstc${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
46944 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "btstc", 24,
46945 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46947 /* btstc${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
46949 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "btstc", 32,
46950 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46952 /* btstc${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
46954 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "btstc", 40,
46955 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46957 /* btstc${X} ${BitBase32-16-u11-Unprefixed}[sb] */
46959 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "btstc", 24,
46960 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46962 /* btstc${X} ${BitBase32-16-u19-Unprefixed}[sb] */
46964 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "btstc", 32,
46965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46967 /* btstc${X} ${BitBase32-16-s11-Unprefixed}[fb] */
46969 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "btstc", 24,
46970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46972 /* btstc${X} ${BitBase32-16-s19-Unprefixed}[fb] */
46974 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "btstc", 32,
46975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46977 /* btstc${X} ${BitBase32-16-u19-Unprefixed} */
46979 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "btstc", 32,
46980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46982 /* btstc${X} ${BitBase32-16-u27-Unprefixed} */
46984 M32C_INSN_BTSTC32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "btstc32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "btstc", 40,
46985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
46987 /* btstc${X} $Bitno16R,$Bit16Rn */
46989 M32C_INSN_BTSTC16_X_BIT16_16_BIT16_RN_DIRECT, "btstc16-X-bit16-16-bit16-Rn-direct", "btstc", 24,
46990 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46992 /* btstc${X} $Bitno16R,$Bit16An */
46994 M32C_INSN_BTSTC16_X_BIT16_16_BIT16_AN_DIRECT, "btstc16-X-bit16-16-bit16-An-direct", "btstc", 24,
46995 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
46997 /* btstc${X} [$Bit16An] */
46999 M32C_INSN_BTSTC16_X_BIT16_16_BIT16_AN_INDIRECT, "btstc16-X-bit16-16-bit16-An-indirect", "btstc", 16,
47000 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47002 /* btstc${X} ${Dsp-16-u8}[$Bit16An] */
47004 M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "btstc16-X-bit16-16-bit16-16-8-An-relative", "btstc", 24,
47005 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47007 /* btstc${X} ${Dsp-16-u16}[$Bit16An] */
47009 M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "btstc16-X-bit16-16-bit16-16-16-An-relative", "btstc", 32,
47010 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47012 /* btstc${X} ${BitBase16-16-u8}[sb] */
47014 M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "btstc16-X-bit16-16-bit16-16-8-SB-relative", "btstc", 24,
47015 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47017 /* btstc${X} ${BitBase16-16-u16}[sb] */
47019 M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "btstc16-X-bit16-16-bit16-16-16-SB-relative", "btstc", 32,
47020 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47022 /* btstc${X} ${BitBase16-16-s8}[fb] */
47024 M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "btstc16-X-bit16-16-bit16-16-8-FB-relative", "btstc", 24,
47025 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47027 /* btstc${X} ${BitBase16-16-u16} */
47029 M32C_INSN_BTSTC16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "btstc16-X-bit16-16-bit16-16-16-absolute", "btstc", 32,
47030 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47032 /* btst${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
47034 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "btst", 16,
47035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47037 /* btst${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
47039 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "btst", 16,
47040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47042 /* btst${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
47044 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "btst", 16,
47045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47047 /* btst${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
47049 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "btst", 24,
47050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47052 /* btst${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
47054 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "btst", 32,
47055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47057 /* btst${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
47059 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "btst", 40,
47060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47062 /* btst${X} ${BitBase32-16-u11-Unprefixed}[sb] */
47064 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "btst", 24,
47065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47067 /* btst${X} ${BitBase32-16-u19-Unprefixed}[sb] */
47069 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "btst", 32,
47070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47072 /* btst${X} ${BitBase32-16-s11-Unprefixed}[fb] */
47074 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "btst", 24,
47075 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47077 /* btst${X} ${BitBase32-16-s19-Unprefixed}[fb] */
47079 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "btst", 32,
47080 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47082 /* btst${X} ${BitBase32-16-u19-Unprefixed} */
47084 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "btst", 32,
47085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47087 /* btst${X} ${BitBase32-16-u27-Unprefixed} */
47089 M32C_INSN_BTST32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "btst32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "btst", 40,
47090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47092 /* btst${G} $Bitno16R,$Bit16Rn */
47094 M32C_INSN_BTST16_G_BIT16_16_8_BIT16_RN_DIRECT, "btst16-G-bit16-16-8-bit16-Rn-direct", "btst", 24,
47095 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47097 /* btst${G} $Bitno16R,$Bit16An */
47099 M32C_INSN_BTST16_G_BIT16_16_8_BIT16_AN_DIRECT, "btst16-G-bit16-16-8-bit16-An-direct", "btst", 24,
47100 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47102 /* btst${G} ${Dsp-16-u8}[$Bit16An] */
47104 M32C_INSN_BTST16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE, "btst16-G-bit16-16-8-bit16-16-8-An-relative", "btst", 24,
47105 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47107 /* btst${G} ${BitBase16-16-u8}[sb] */
47109 M32C_INSN_BTST16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE, "btst16-G-bit16-16-8-bit16-16-8-SB-relative", "btst", 24,
47110 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47112 /* btst${G} ${BitBase16-16-s8}[fb] */
47114 M32C_INSN_BTST16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, "btst16-G-bit16-16-8-bit16-16-8-FB-relative", "btst", 24,
47115 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47117 /* btst${S} ${BitBase16-8-u11-S}[sb] */
47119 M32C_INSN_BTST16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S, "btst16-S-bit16-11-S-bit16-11-SB-relative-S", "btst", 16,
47120 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47122 /* btst${G} ${Dsp-16-u16}[$Bit16An] */
47124 M32C_INSN_BTST16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE, "btst16-G-bit16-16-16-bit16-16-16-An-relative", "btst", 32,
47125 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47127 /* btst${G} ${BitBase16-16-u16}[sb] */
47129 M32C_INSN_BTST16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE, "btst16-G-bit16-16-16-bit16-16-16-SB-relative", "btst", 32,
47130 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47132 /* btst${G} ${BitBase16-16-u16} */
47134 M32C_INSN_BTST16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, "btst16-G-bit16-16-16-bit16-16-16-absolute", "btst", 32,
47135 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47137 /* btst${G} [$Bit16An] */
47139 M32C_INSN_BTST16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT, "btst16-G-bit16-16-basic-bit16-An-indirect", "btst", 16,
47140 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47142 /* bset${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
47144 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "bset", 16,
47145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47147 /* bset${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
47149 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "bset", 16,
47150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47152 /* bset${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
47154 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "bset", 16,
47155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47157 /* bset${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
47159 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "bset", 24,
47160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47162 /* bset${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
47164 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "bset", 32,
47165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47167 /* bset${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
47169 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "bset", 40,
47170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47172 /* bset${X} ${BitBase32-16-u11-Unprefixed}[sb] */
47174 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "bset", 24,
47175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47177 /* bset${X} ${BitBase32-16-u19-Unprefixed}[sb] */
47179 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "bset", 32,
47180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47182 /* bset${X} ${BitBase32-16-s11-Unprefixed}[fb] */
47184 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "bset", 24,
47185 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47187 /* bset${X} ${BitBase32-16-s19-Unprefixed}[fb] */
47189 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "bset", 32,
47190 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47192 /* bset${X} ${BitBase32-16-u19-Unprefixed} */
47194 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "bset", 32,
47195 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47197 /* bset${X} ${BitBase32-16-u27-Unprefixed} */
47199 M32C_INSN_BSET32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "bset32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "bset", 40,
47200 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47202 /* bset${G} $Bitno16R,$Bit16Rn */
47204 M32C_INSN_BSET16_G_BIT16_16_8_BIT16_RN_DIRECT, "bset16-G-bit16-16-8-bit16-Rn-direct", "bset", 24,
47205 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47207 /* bset${G} $Bitno16R,$Bit16An */
47209 M32C_INSN_BSET16_G_BIT16_16_8_BIT16_AN_DIRECT, "bset16-G-bit16-16-8-bit16-An-direct", "bset", 24,
47210 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47212 /* bset${G} ${Dsp-16-u8}[$Bit16An] */
47214 M32C_INSN_BSET16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE, "bset16-G-bit16-16-8-bit16-16-8-An-relative", "bset", 24,
47215 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47217 /* bset${G} ${BitBase16-16-u8}[sb] */
47219 M32C_INSN_BSET16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE, "bset16-G-bit16-16-8-bit16-16-8-SB-relative", "bset", 24,
47220 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47222 /* bset${G} ${BitBase16-16-s8}[fb] */
47224 M32C_INSN_BSET16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, "bset16-G-bit16-16-8-bit16-16-8-FB-relative", "bset", 24,
47225 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47227 /* bset${S} ${BitBase16-8-u11-S}[sb] */
47229 M32C_INSN_BSET16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S, "bset16-S-bit16-11-S-bit16-11-SB-relative-S", "bset", 16,
47230 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47232 /* bset${G} ${Dsp-16-u16}[$Bit16An] */
47234 M32C_INSN_BSET16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE, "bset16-G-bit16-16-16-bit16-16-16-An-relative", "bset", 32,
47235 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47237 /* bset${G} ${BitBase16-16-u16}[sb] */
47239 M32C_INSN_BSET16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE, "bset16-G-bit16-16-16-bit16-16-16-SB-relative", "bset", 32,
47240 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47242 /* bset${G} ${BitBase16-16-u16} */
47244 M32C_INSN_BSET16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, "bset16-G-bit16-16-16-bit16-16-16-absolute", "bset", 32,
47245 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47247 /* bset${G} [$Bit16An] */
47249 M32C_INSN_BSET16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT, "bset16-G-bit16-16-basic-bit16-An-indirect", "bset", 16,
47250 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47252 /* bor${X} $Bitno32Prefixed,$Bit32RnPrefixed */
47254 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bor", 24,
47255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47257 /* bor${X} $Bitno32Prefixed,$Bit32AnPrefixed */
47259 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bor", 24,
47260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47262 /* bor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
47264 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bor", 24,
47265 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47267 /* bor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
47269 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bor", 32,
47270 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47272 /* bor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
47274 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bor", 40,
47275 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47277 /* bor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
47279 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bor", 48,
47280 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47282 /* bor${X} ${BitBase32-24-u11-Prefixed}[sb] */
47284 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bor", 32,
47285 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47287 /* bor${X} ${BitBase32-24-u19-Prefixed}[sb] */
47289 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bor", 40,
47290 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47292 /* bor${X} ${BitBase32-24-s11-Prefixed}[fb] */
47294 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bor", 32,
47295 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47297 /* bor${X} ${BitBase32-24-s19-Prefixed}[fb] */
47299 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bor", 40,
47300 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47302 /* bor${X} ${BitBase32-24-u19-Prefixed} */
47304 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bor", 40,
47305 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47307 /* bor${X} ${BitBase32-24-u27-Prefixed} */
47309 M32C_INSN_BOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bor32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bor", 48,
47310 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47312 /* bor${X} $Bitno16R,$Bit16Rn */
47314 M32C_INSN_BOR16_X_BIT16_16_BIT16_RN_DIRECT, "bor16-X-bit16-16-bit16-Rn-direct", "bor", 24,
47315 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47317 /* bor${X} $Bitno16R,$Bit16An */
47319 M32C_INSN_BOR16_X_BIT16_16_BIT16_AN_DIRECT, "bor16-X-bit16-16-bit16-An-direct", "bor", 24,
47320 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47322 /* bor${X} [$Bit16An] */
47324 M32C_INSN_BOR16_X_BIT16_16_BIT16_AN_INDIRECT, "bor16-X-bit16-16-bit16-An-indirect", "bor", 16,
47325 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47327 /* bor${X} ${Dsp-16-u8}[$Bit16An] */
47329 M32C_INSN_BOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bor16-X-bit16-16-bit16-16-8-An-relative", "bor", 24,
47330 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47332 /* bor${X} ${Dsp-16-u16}[$Bit16An] */
47334 M32C_INSN_BOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bor16-X-bit16-16-bit16-16-16-An-relative", "bor", 32,
47335 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47337 /* bor${X} ${BitBase16-16-u8}[sb] */
47339 M32C_INSN_BOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bor16-X-bit16-16-bit16-16-8-SB-relative", "bor", 24,
47340 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47342 /* bor${X} ${BitBase16-16-u16}[sb] */
47344 M32C_INSN_BOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bor16-X-bit16-16-bit16-16-16-SB-relative", "bor", 32,
47345 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47347 /* bor${X} ${BitBase16-16-s8}[fb] */
47349 M32C_INSN_BOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bor16-X-bit16-16-bit16-16-8-FB-relative", "bor", 24,
47350 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47352 /* bor${X} ${BitBase16-16-u16} */
47354 M32C_INSN_BOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bor16-X-bit16-16-bit16-16-16-absolute", "bor", 32,
47355 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47357 /* bnxor${X} $Bitno32Prefixed,$Bit32RnPrefixed */
47359 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bnxor", 24,
47360 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47362 /* bnxor${X} $Bitno32Prefixed,$Bit32AnPrefixed */
47364 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bnxor", 24,
47365 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47367 /* bnxor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
47369 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bnxor", 24,
47370 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47372 /* bnxor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
47374 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bnxor", 32,
47375 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47377 /* bnxor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
47379 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bnxor", 40,
47380 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47382 /* bnxor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
47384 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bnxor", 48,
47385 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47387 /* bnxor${X} ${BitBase32-24-u11-Prefixed}[sb] */
47389 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bnxor", 32,
47390 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47392 /* bnxor${X} ${BitBase32-24-u19-Prefixed}[sb] */
47394 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bnxor", 40,
47395 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47397 /* bnxor${X} ${BitBase32-24-s11-Prefixed}[fb] */
47399 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bnxor", 32,
47400 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47402 /* bnxor${X} ${BitBase32-24-s19-Prefixed}[fb] */
47404 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bnxor", 40,
47405 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47407 /* bnxor${X} ${BitBase32-24-u19-Prefixed} */
47409 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bnxor", 40,
47410 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47412 /* bnxor${X} ${BitBase32-24-u27-Prefixed} */
47414 M32C_INSN_BNXOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bnxor32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bnxor", 48,
47415 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47417 /* bnxor${X} $Bitno16R,$Bit16Rn */
47419 M32C_INSN_BNXOR16_X_BIT16_16_BIT16_RN_DIRECT, "bnxor16-X-bit16-16-bit16-Rn-direct", "bnxor", 24,
47420 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47422 /* bnxor${X} $Bitno16R,$Bit16An */
47424 M32C_INSN_BNXOR16_X_BIT16_16_BIT16_AN_DIRECT, "bnxor16-X-bit16-16-bit16-An-direct", "bnxor", 24,
47425 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47427 /* bnxor${X} [$Bit16An] */
47429 M32C_INSN_BNXOR16_X_BIT16_16_BIT16_AN_INDIRECT, "bnxor16-X-bit16-16-bit16-An-indirect", "bnxor", 16,
47430 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47432 /* bnxor${X} ${Dsp-16-u8}[$Bit16An] */
47434 M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bnxor16-X-bit16-16-bit16-16-8-An-relative", "bnxor", 24,
47435 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47437 /* bnxor${X} ${Dsp-16-u16}[$Bit16An] */
47439 M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bnxor16-X-bit16-16-bit16-16-16-An-relative", "bnxor", 32,
47440 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47442 /* bnxor${X} ${BitBase16-16-u8}[sb] */
47444 M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bnxor16-X-bit16-16-bit16-16-8-SB-relative", "bnxor", 24,
47445 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47447 /* bnxor${X} ${BitBase16-16-u16}[sb] */
47449 M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bnxor16-X-bit16-16-bit16-16-16-SB-relative", "bnxor", 32,
47450 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47452 /* bnxor${X} ${BitBase16-16-s8}[fb] */
47454 M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bnxor16-X-bit16-16-bit16-16-8-FB-relative", "bnxor", 24,
47455 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47457 /* bnxor${X} ${BitBase16-16-u16} */
47459 M32C_INSN_BNXOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bnxor16-X-bit16-16-bit16-16-16-absolute", "bnxor", 32,
47460 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47462 /* bntst${X} $Bitno32Prefixed,$Bit32RnPrefixed */
47464 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bntst", 24,
47465 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47467 /* bntst${X} $Bitno32Prefixed,$Bit32AnPrefixed */
47469 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bntst", 24,
47470 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47472 /* bntst${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
47474 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bntst", 24,
47475 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47477 /* bntst${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
47479 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bntst", 32,
47480 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47482 /* bntst${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
47484 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bntst", 40,
47485 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47487 /* bntst${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
47489 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bntst", 48,
47490 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47492 /* bntst${X} ${BitBase32-24-u11-Prefixed}[sb] */
47494 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bntst", 32,
47495 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47497 /* bntst${X} ${BitBase32-24-u19-Prefixed}[sb] */
47499 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bntst", 40,
47500 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47502 /* bntst${X} ${BitBase32-24-s11-Prefixed}[fb] */
47504 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bntst", 32,
47505 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47507 /* bntst${X} ${BitBase32-24-s19-Prefixed}[fb] */
47509 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bntst", 40,
47510 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47512 /* bntst${X} ${BitBase32-24-u19-Prefixed} */
47514 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bntst", 40,
47515 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47517 /* bntst${X} ${BitBase32-24-u27-Prefixed} */
47519 M32C_INSN_BNTST32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bntst32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bntst", 48,
47520 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47522 /* bntst${X} $Bitno16R,$Bit16Rn */
47524 M32C_INSN_BNTST16_X_BIT16_16_BIT16_RN_DIRECT, "bntst16-X-bit16-16-bit16-Rn-direct", "bntst", 24,
47525 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47527 /* bntst${X} $Bitno16R,$Bit16An */
47529 M32C_INSN_BNTST16_X_BIT16_16_BIT16_AN_DIRECT, "bntst16-X-bit16-16-bit16-An-direct", "bntst", 24,
47530 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47532 /* bntst${X} [$Bit16An] */
47534 M32C_INSN_BNTST16_X_BIT16_16_BIT16_AN_INDIRECT, "bntst16-X-bit16-16-bit16-An-indirect", "bntst", 16,
47535 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47537 /* bntst${X} ${Dsp-16-u8}[$Bit16An] */
47539 M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bntst16-X-bit16-16-bit16-16-8-An-relative", "bntst", 24,
47540 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47542 /* bntst${X} ${Dsp-16-u16}[$Bit16An] */
47544 M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bntst16-X-bit16-16-bit16-16-16-An-relative", "bntst", 32,
47545 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47547 /* bntst${X} ${BitBase16-16-u8}[sb] */
47549 M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bntst16-X-bit16-16-bit16-16-8-SB-relative", "bntst", 24,
47550 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47552 /* bntst${X} ${BitBase16-16-u16}[sb] */
47554 M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bntst16-X-bit16-16-bit16-16-16-SB-relative", "bntst", 32,
47555 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47557 /* bntst${X} ${BitBase16-16-s8}[fb] */
47559 M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bntst16-X-bit16-16-bit16-16-8-FB-relative", "bntst", 24,
47560 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47562 /* bntst${X} ${BitBase16-16-u16} */
47564 M32C_INSN_BNTST16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bntst16-X-bit16-16-bit16-16-16-absolute", "bntst", 32,
47565 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47567 /* bnot${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
47569 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "bnot", 16,
47570 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47572 /* bnot${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
47574 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "bnot", 16,
47575 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47577 /* bnot${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
47579 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "bnot", 16,
47580 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47582 /* bnot${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
47584 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "bnot", 24,
47585 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47587 /* bnot${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
47589 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "bnot", 32,
47590 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47592 /* bnot${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
47594 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "bnot", 40,
47595 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47597 /* bnot${X} ${BitBase32-16-u11-Unprefixed}[sb] */
47599 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "bnot", 24,
47600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47602 /* bnot${X} ${BitBase32-16-u19-Unprefixed}[sb] */
47604 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "bnot", 32,
47605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47607 /* bnot${X} ${BitBase32-16-s11-Unprefixed}[fb] */
47609 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "bnot", 24,
47610 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47612 /* bnot${X} ${BitBase32-16-s19-Unprefixed}[fb] */
47614 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "bnot", 32,
47615 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47617 /* bnot${X} ${BitBase32-16-u19-Unprefixed} */
47619 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "bnot", 32,
47620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47622 /* bnot${X} ${BitBase32-16-u27-Unprefixed} */
47624 M32C_INSN_BNOT32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "bnot32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "bnot", 40,
47625 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47627 /* bnot${G} $Bitno16R,$Bit16Rn */
47629 M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_RN_DIRECT, "bnot16-G-bit16-16-8-bit16-Rn-direct", "bnot", 24,
47630 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47632 /* bnot${G} $Bitno16R,$Bit16An */
47634 M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_AN_DIRECT, "bnot16-G-bit16-16-8-bit16-An-direct", "bnot", 24,
47635 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47637 /* bnot${G} ${Dsp-16-u8}[$Bit16An] */
47639 M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE, "bnot16-G-bit16-16-8-bit16-16-8-An-relative", "bnot", 24,
47640 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47642 /* bnot${G} ${BitBase16-16-u8}[sb] */
47644 M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE, "bnot16-G-bit16-16-8-bit16-16-8-SB-relative", "bnot", 24,
47645 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47647 /* bnot${G} ${BitBase16-16-s8}[fb] */
47649 M32C_INSN_BNOT16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, "bnot16-G-bit16-16-8-bit16-16-8-FB-relative", "bnot", 24,
47650 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47652 /* bnot${S} ${BitBase16-8-u11-S}[sb] */
47654 M32C_INSN_BNOT16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S, "bnot16-S-bit16-11-S-bit16-11-SB-relative-S", "bnot", 16,
47655 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47657 /* bnot${G} ${Dsp-16-u16}[$Bit16An] */
47659 M32C_INSN_BNOT16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE, "bnot16-G-bit16-16-16-bit16-16-16-An-relative", "bnot", 32,
47660 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47662 /* bnot${G} ${BitBase16-16-u16}[sb] */
47664 M32C_INSN_BNOT16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE, "bnot16-G-bit16-16-16-bit16-16-16-SB-relative", "bnot", 32,
47665 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47667 /* bnot${G} ${BitBase16-16-u16} */
47669 M32C_INSN_BNOT16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, "bnot16-G-bit16-16-16-bit16-16-16-absolute", "bnot", 32,
47670 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47672 /* bnot${G} [$Bit16An] */
47674 M32C_INSN_BNOT16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT, "bnot16-G-bit16-16-basic-bit16-An-indirect", "bnot", 16,
47675 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47677 /* bnor${X} $Bitno32Prefixed,$Bit32RnPrefixed */
47679 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bnor", 24,
47680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47682 /* bnor${X} $Bitno32Prefixed,$Bit32AnPrefixed */
47684 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bnor", 24,
47685 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47687 /* bnor${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
47689 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bnor", 24,
47690 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47692 /* bnor${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
47694 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bnor", 32,
47695 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47697 /* bnor${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
47699 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bnor", 40,
47700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47702 /* bnor${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
47704 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bnor", 48,
47705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47707 /* bnor${X} ${BitBase32-24-u11-Prefixed}[sb] */
47709 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bnor", 32,
47710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47712 /* bnor${X} ${BitBase32-24-u19-Prefixed}[sb] */
47714 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bnor", 40,
47715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47717 /* bnor${X} ${BitBase32-24-s11-Prefixed}[fb] */
47719 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bnor", 32,
47720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47722 /* bnor${X} ${BitBase32-24-s19-Prefixed}[fb] */
47724 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bnor", 40,
47725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47727 /* bnor${X} ${BitBase32-24-u19-Prefixed} */
47729 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bnor", 40,
47730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47732 /* bnor${X} ${BitBase32-24-u27-Prefixed} */
47734 M32C_INSN_BNOR32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bnor32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bnor", 48,
47735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47737 /* bnor${X} $Bitno16R,$Bit16Rn */
47739 M32C_INSN_BNOR16_X_BIT16_16_BIT16_RN_DIRECT, "bnor16-X-bit16-16-bit16-Rn-direct", "bnor", 24,
47740 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47742 /* bnor${X} $Bitno16R,$Bit16An */
47744 M32C_INSN_BNOR16_X_BIT16_16_BIT16_AN_DIRECT, "bnor16-X-bit16-16-bit16-An-direct", "bnor", 24,
47745 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47747 /* bnor${X} [$Bit16An] */
47749 M32C_INSN_BNOR16_X_BIT16_16_BIT16_AN_INDIRECT, "bnor16-X-bit16-16-bit16-An-indirect", "bnor", 16,
47750 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47752 /* bnor${X} ${Dsp-16-u8}[$Bit16An] */
47754 M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bnor16-X-bit16-16-bit16-16-8-An-relative", "bnor", 24,
47755 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47757 /* bnor${X} ${Dsp-16-u16}[$Bit16An] */
47759 M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bnor16-X-bit16-16-bit16-16-16-An-relative", "bnor", 32,
47760 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47762 /* bnor${X} ${BitBase16-16-u8}[sb] */
47764 M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bnor16-X-bit16-16-bit16-16-8-SB-relative", "bnor", 24,
47765 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47767 /* bnor${X} ${BitBase16-16-u16}[sb] */
47769 M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bnor16-X-bit16-16-bit16-16-16-SB-relative", "bnor", 32,
47770 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47772 /* bnor${X} ${BitBase16-16-s8}[fb] */
47774 M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bnor16-X-bit16-16-bit16-16-8-FB-relative", "bnor", 24,
47775 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47777 /* bnor${X} ${BitBase16-16-u16} */
47779 M32C_INSN_BNOR16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bnor16-X-bit16-16-bit16-16-16-absolute", "bnor", 32,
47780 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47782 /* bnand${X} $Bitno32Prefixed,$Bit32RnPrefixed */
47784 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "bnand", 24,
47785 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47787 /* bnand${X} $Bitno32Prefixed,$Bit32AnPrefixed */
47789 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "bnand", 24,
47790 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47792 /* bnand${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
47794 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "bnand", 24,
47795 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47797 /* bnand${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
47799 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "bnand", 32,
47800 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47802 /* bnand${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
47804 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "bnand", 40,
47805 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47807 /* bnand${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
47809 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "bnand", 48,
47810 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47812 /* bnand${X} ${BitBase32-24-u11-Prefixed}[sb] */
47814 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "bnand", 32,
47815 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47817 /* bnand${X} ${BitBase32-24-u19-Prefixed}[sb] */
47819 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "bnand", 40,
47820 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47822 /* bnand${X} ${BitBase32-24-s11-Prefixed}[fb] */
47824 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "bnand", 32,
47825 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47827 /* bnand${X} ${BitBase32-24-s19-Prefixed}[fb] */
47829 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "bnand", 40,
47830 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47832 /* bnand${X} ${BitBase32-24-u19-Prefixed} */
47834 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "bnand", 40,
47835 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47837 /* bnand${X} ${BitBase32-24-u27-Prefixed} */
47839 M32C_INSN_BNAND32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "bnand32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "bnand", 48,
47840 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47842 /* bnand${X} $Bitno16R,$Bit16Rn */
47844 M32C_INSN_BNAND16_X_BIT16_16_BIT16_RN_DIRECT, "bnand16-X-bit16-16-bit16-Rn-direct", "bnand", 24,
47845 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47847 /* bnand${X} $Bitno16R,$Bit16An */
47849 M32C_INSN_BNAND16_X_BIT16_16_BIT16_AN_DIRECT, "bnand16-X-bit16-16-bit16-An-direct", "bnand", 24,
47850 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47852 /* bnand${X} [$Bit16An] */
47854 M32C_INSN_BNAND16_X_BIT16_16_BIT16_AN_INDIRECT, "bnand16-X-bit16-16-bit16-An-indirect", "bnand", 16,
47855 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47857 /* bnand${X} ${Dsp-16-u8}[$Bit16An] */
47859 M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "bnand16-X-bit16-16-bit16-16-8-An-relative", "bnand", 24,
47860 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47862 /* bnand${X} ${Dsp-16-u16}[$Bit16An] */
47864 M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "bnand16-X-bit16-16-bit16-16-16-An-relative", "bnand", 32,
47865 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47867 /* bnand${X} ${BitBase16-16-u8}[sb] */
47869 M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "bnand16-X-bit16-16-bit16-16-8-SB-relative", "bnand", 24,
47870 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47872 /* bnand${X} ${BitBase16-16-u16}[sb] */
47874 M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "bnand16-X-bit16-16-bit16-16-16-SB-relative", "bnand", 32,
47875 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47877 /* bnand${X} ${BitBase16-16-s8}[fb] */
47879 M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "bnand16-X-bit16-16-bit16-16-8-FB-relative", "bnand", 24,
47880 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47882 /* bnand${X} ${BitBase16-16-u16} */
47884 M32C_INSN_BNAND16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "bnand16-X-bit16-16-bit16-16-16-absolute", "bnand", 32,
47885 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47887 /* bm${cond32-16} $Bitno32Unprefixed,$Bit32RnUnprefixed */
47889 M32C_INSN_BM32_BIT32_BASIC_UNPREFIXED_COND32_16_BIT32_RN_DIRECT_UNPREFIXED, "bm32-bit32-basic-Unprefixed-cond32-16-bit32-Rn-direct-Unprefixed", "bm", 24,
47890 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47892 /* bm${cond32-16} $Bitno32Unprefixed,$Bit32AnUnprefixed */
47894 M32C_INSN_BM32_BIT32_BASIC_UNPREFIXED_COND32_16_BIT32_AN_DIRECT_UNPREFIXED, "bm32-bit32-basic-Unprefixed-cond32-16-bit32-An-direct-Unprefixed", "bm", 24,
47895 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47897 /* bm${cond32-16} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
47899 M32C_INSN_BM32_BIT32_BASIC_UNPREFIXED_COND32_16_BIT32_AN_INDIRECT_UNPREFIXED, "bm32-bit32-basic-Unprefixed-cond32-16-bit32-An-indirect-Unprefixed", "bm", 24,
47900 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47902 /* bm${cond32-24} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
47904 M32C_INSN_BM32_BIT32_16_8_UNPREFIXED_COND32_24_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "bm32-bit32-16-8-Unprefixed-cond32-24-bit32-16-11-An-relative-Unprefixed", "bm", 32,
47905 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47907 /* bm${cond32-24} ${BitBase32-16-u11-Unprefixed}[sb] */
47909 M32C_INSN_BM32_BIT32_16_8_UNPREFIXED_COND32_24_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "bm32-bit32-16-8-Unprefixed-cond32-24-bit32-16-11-SB-relative-Unprefixed", "bm", 32,
47910 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47912 /* bm${cond32-24} ${BitBase32-16-s11-Unprefixed}[fb] */
47914 M32C_INSN_BM32_BIT32_16_8_UNPREFIXED_COND32_24_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "bm32-bit32-16-8-Unprefixed-cond32-24-bit32-16-11-FB-relative-Unprefixed", "bm", 32,
47915 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47917 /* bm${cond32-32} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
47919 M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "bm32-bit32-16-16-Unprefixed-cond32-32-bit32-16-19-An-relative-Unprefixed", "bm", 40,
47920 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47922 /* bm${cond32-32} ${BitBase32-16-u19-Unprefixed}[sb] */
47924 M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "bm32-bit32-16-16-Unprefixed-cond32-32-bit32-16-19-SB-relative-Unprefixed", "bm", 40,
47925 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47927 /* bm${cond32-32} ${BitBase32-16-s19-Unprefixed}[fb] */
47929 M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "bm32-bit32-16-16-Unprefixed-cond32-32-bit32-16-19-FB-relative-Unprefixed", "bm", 40,
47930 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47932 /* bm${cond32-32} ${BitBase32-16-u19-Unprefixed} */
47934 M32C_INSN_BM32_BIT32_16_16_UNPREFIXED_COND32_32_BIT32_16_19_ABSOLUTE_UNPREFIXED, "bm32-bit32-16-16-Unprefixed-cond32-32-bit32-16-19-absolute-Unprefixed", "bm", 40,
47935 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47937 /* bm${cond32-40} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
47939 M32C_INSN_BM32_BIT32_16_24_UNPREFIXED_COND32_40_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "bm32-bit32-16-24-Unprefixed-cond32-40-bit32-16-27-An-relative-Unprefixed", "bm", 48,
47940 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47942 /* bm${cond32-40} ${BitBase32-16-u27-Unprefixed} */
47944 M32C_INSN_BM32_BIT32_16_24_UNPREFIXED_COND32_40_BIT32_16_27_ABSOLUTE_UNPREFIXED, "bm32-bit32-16-24-Unprefixed-cond32-40-bit32-16-27-absolute-Unprefixed", "bm", 48,
47945 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47947 /* bm${cond16-24} $Bitno16R,$Bit16Rn */
47949 M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_RN_DIRECT, "bm16-bit16-16-8-cond16-24-bit16-Rn-direct", "bm", 32,
47950 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47952 /* bm${cond16-24} $Bitno16R,$Bit16An */
47954 M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_AN_DIRECT, "bm16-bit16-16-8-cond16-24-bit16-An-direct", "bm", 32,
47955 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47957 /* bm${cond16-24} ${Dsp-16-u8}[$Bit16An] */
47959 M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_16_8_AN_RELATIVE, "bm16-bit16-16-8-cond16-24-bit16-16-8-An-relative", "bm", 32,
47960 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47962 /* bm${cond16-24} ${BitBase16-16-u8}[sb] */
47964 M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_16_8_SB_RELATIVE, "bm16-bit16-16-8-cond16-24-bit16-16-8-SB-relative", "bm", 32,
47965 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47967 /* bm${cond16-24} ${BitBase16-16-s8}[fb] */
47969 M32C_INSN_BM16_BIT16_16_8_COND16_24_BIT16_16_8_FB_RELATIVE, "bm16-bit16-16-8-cond16-24-bit16-16-8-FB-relative", "bm", 32,
47970 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47972 /* bm${cond16-32} ${Dsp-16-u16}[$Bit16An] */
47974 M32C_INSN_BM16_BIT16_16_16_COND16_32_BIT16_16_16_AN_RELATIVE, "bm16-bit16-16-16-cond16-32-bit16-16-16-An-relative", "bm", 40,
47975 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47977 /* bm${cond16-32} ${BitBase16-16-u16}[sb] */
47979 M32C_INSN_BM16_BIT16_16_16_COND16_32_BIT16_16_16_SB_RELATIVE, "bm16-bit16-16-16-cond16-32-bit16-16-16-SB-relative", "bm", 40,
47980 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47982 /* bm${cond16-32} ${BitBase16-16-u16} */
47984 M32C_INSN_BM16_BIT16_16_16_COND16_32_BIT16_16_16_ABSOLUTE, "bm16-bit16-16-16-cond16-32-bit16-16-16-absolute", "bm", 40,
47985 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47987 /* bm${cond16-16} [$Bit16An] */
47989 M32C_INSN_BM16_BIT16_16_BASIC_COND16_16_BIT16_AN_INDIRECT, "bm16-bit16-16-basic-cond16-16-bit16-An-indirect", "bm", 24,
47990 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
47992 /* bitindex.w $Dst32RnUnprefixedHI */
47994 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "bitindex.w", 16,
47995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
47997 /* bitindex.w $Dst32AnUnprefixedHI */
47999 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "bitindex.w", 16,
48000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48002 /* bitindex.w [$Dst32AnUnprefixed] */
48004 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "bitindex.w", 16,
48005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48007 /* bitindex.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
48009 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "bitindex.w", 24,
48010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48012 /* bitindex.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
48014 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "bitindex.w", 32,
48015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48017 /* bitindex.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
48019 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "bitindex.w", 40,
48020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48022 /* bitindex.w ${Dsp-16-u8}[sb] */
48024 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "bitindex.w", 24,
48025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48027 /* bitindex.w ${Dsp-16-u16}[sb] */
48029 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "bitindex.w", 32,
48030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48032 /* bitindex.w ${Dsp-16-s8}[fb] */
48034 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "bitindex.w", 24,
48035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48037 /* bitindex.w ${Dsp-16-s16}[fb] */
48039 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "bitindex.w", 32,
48040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48042 /* bitindex.w ${Dsp-16-u16} */
48044 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "bitindex.w", 32,
48045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48047 /* bitindex.w ${Dsp-16-u24} */
48049 M32C_INSN_BITINDEX32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "bitindex32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "bitindex.w", 40,
48050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48052 /* bitindex.b $Dst32RnUnprefixedQI */
48054 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "bitindex.b", 16,
48055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48057 /* bitindex.b $Dst32AnUnprefixedQI */
48059 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "bitindex.b", 16,
48060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48062 /* bitindex.b [$Dst32AnUnprefixed] */
48064 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "bitindex.b", 16,
48065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48067 /* bitindex.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
48069 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "bitindex.b", 24,
48070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48072 /* bitindex.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
48074 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "bitindex.b", 32,
48075 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48077 /* bitindex.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
48079 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "bitindex.b", 40,
48080 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48082 /* bitindex.b ${Dsp-16-u8}[sb] */
48084 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "bitindex.b", 24,
48085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48087 /* bitindex.b ${Dsp-16-u16}[sb] */
48089 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "bitindex.b", 32,
48090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48092 /* bitindex.b ${Dsp-16-s8}[fb] */
48094 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "bitindex.b", 24,
48095 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48097 /* bitindex.b ${Dsp-16-s16}[fb] */
48099 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "bitindex.b", 32,
48100 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48102 /* bitindex.b ${Dsp-16-u16} */
48104 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "bitindex.b", 32,
48105 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48107 /* bitindex.b ${Dsp-16-u24} */
48109 M32C_INSN_BITINDEX32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "bitindex32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "bitindex.b", 40,
48110 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48112 /* bclr${X} $Bitno32Unprefixed,$Bit32RnUnprefixed */
48114 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_RN_DIRECT_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-Rn-direct-Unprefixed", "bclr", 16,
48115 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48117 /* bclr${X} $Bitno32Unprefixed,$Bit32AnUnprefixed */
48119 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_AN_DIRECT_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-An-direct-Unprefixed", "bclr", 16,
48120 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48122 /* bclr${X} $Bitno32Unprefixed,[$Bit32AnUnprefixed] */
48124 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_AN_INDIRECT_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-An-indirect-Unprefixed", "bclr", 16,
48125 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48127 /* bclr${X} ${BitBase32-16-u11-Unprefixed}[$Bit32AnUnprefixed] */
48129 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_11_AN_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-11-An-relative-Unprefixed", "bclr", 24,
48130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48132 /* bclr${X} ${BitBase32-16-u19-Unprefixed}[$Bit32AnUnprefixed] */
48134 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_AN_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-19-An-relative-Unprefixed", "bclr", 32,
48135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48137 /* bclr${X} ${BitBase32-16-u27-Unprefixed}[$Bit32AnUnprefixed] */
48139 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_27_AN_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-27-An-relative-Unprefixed", "bclr", 40,
48140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48142 /* bclr${X} ${BitBase32-16-u11-Unprefixed}[sb] */
48144 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_11_SB_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-11-SB-relative-Unprefixed", "bclr", 24,
48145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48147 /* bclr${X} ${BitBase32-16-u19-Unprefixed}[sb] */
48149 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_SB_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-19-SB-relative-Unprefixed", "bclr", 32,
48150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48152 /* bclr${X} ${BitBase32-16-s11-Unprefixed}[fb] */
48154 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_11_FB_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-11-FB-relative-Unprefixed", "bclr", 24,
48155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48157 /* bclr${X} ${BitBase32-16-s19-Unprefixed}[fb] */
48159 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_FB_RELATIVE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-19-FB-relative-Unprefixed", "bclr", 32,
48160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48162 /* bclr${X} ${BitBase32-16-u19-Unprefixed} */
48164 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_19_ABSOLUTE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-19-absolute-Unprefixed", "bclr", 32,
48165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48167 /* bclr${X} ${BitBase32-16-u27-Unprefixed} */
48169 M32C_INSN_BCLR32_X_BIT32_16_UNPREFIXED_BIT32_16_27_ABSOLUTE_UNPREFIXED, "bclr32-X-bit32-16-Unprefixed-bit32-16-27-absolute-Unprefixed", "bclr", 40,
48170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48172 /* bclr${G} $Bitno16R,$Bit16Rn */
48174 M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_RN_DIRECT, "bclr16-G-bit16-16-8-bit16-Rn-direct", "bclr", 24,
48175 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48177 /* bclr${G} $Bitno16R,$Bit16An */
48179 M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_AN_DIRECT, "bclr16-G-bit16-16-8-bit16-An-direct", "bclr", 24,
48180 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48182 /* bclr${G} ${Dsp-16-u8}[$Bit16An] */
48184 M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_16_8_AN_RELATIVE, "bclr16-G-bit16-16-8-bit16-16-8-An-relative", "bclr", 24,
48185 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48187 /* bclr${G} ${BitBase16-16-u8}[sb] */
48189 M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_16_8_SB_RELATIVE, "bclr16-G-bit16-16-8-bit16-16-8-SB-relative", "bclr", 24,
48190 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48192 /* bclr${G} ${BitBase16-16-s8}[fb] */
48194 M32C_INSN_BCLR16_G_BIT16_16_8_BIT16_16_8_FB_RELATIVE, "bclr16-G-bit16-16-8-bit16-16-8-FB-relative", "bclr", 24,
48195 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48197 /* bclr${S} ${BitBase16-8-u11-S}[sb] */
48199 M32C_INSN_BCLR16_S_BIT16_11_S_BIT16_11_SB_RELATIVE_S, "bclr16-S-bit16-11-S-bit16-11-SB-relative-S", "bclr", 16,
48200 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48202 /* bclr${G} ${Dsp-16-u16}[$Bit16An] */
48204 M32C_INSN_BCLR16_G_BIT16_16_16_BIT16_16_16_AN_RELATIVE, "bclr16-G-bit16-16-16-bit16-16-16-An-relative", "bclr", 32,
48205 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48207 /* bclr${G} ${BitBase16-16-u16}[sb] */
48209 M32C_INSN_BCLR16_G_BIT16_16_16_BIT16_16_16_SB_RELATIVE, "bclr16-G-bit16-16-16-bit16-16-16-SB-relative", "bclr", 32,
48210 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48212 /* bclr${G} ${BitBase16-16-u16} */
48214 M32C_INSN_BCLR16_G_BIT16_16_16_BIT16_16_16_ABSOLUTE, "bclr16-G-bit16-16-16-bit16-16-16-absolute", "bclr", 32,
48215 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48217 /* bclr${G} [$Bit16An] */
48219 M32C_INSN_BCLR16_G_BIT16_16_BASIC_BIT16_AN_INDIRECT, "bclr16-G-bit16-16-basic-bit16-An-indirect", "bclr", 16,
48220 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48222 /* band${X} $Bitno32Prefixed,$Bit32RnPrefixed */
48224 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_RN_DIRECT_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-Rn-direct-Prefixed", "band", 24,
48225 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48227 /* band${X} $Bitno32Prefixed,$Bit32AnPrefixed */
48229 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_AN_DIRECT_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-An-direct-Prefixed", "band", 24,
48230 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48232 /* band${X} $Bitno32Prefixed,[$Bit32AnPrefixed] */
48234 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_AN_INDIRECT_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-An-indirect-Prefixed", "band", 24,
48235 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48237 /* band${X} ${BitBase32-24-u11-Prefixed}[$Bit32AnPrefixed] */
48239 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_11_AN_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-11-An-relative-Prefixed", "band", 32,
48240 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48242 /* band${X} ${BitBase32-24-u19-Prefixed}[$Bit32AnPrefixed] */
48244 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_AN_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-19-An-relative-Prefixed", "band", 40,
48245 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48247 /* band${X} ${BitBase32-24-u27-Prefixed}[$Bit32AnPrefixed] */
48249 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_27_AN_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-27-An-relative-Prefixed", "band", 48,
48250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48252 /* band${X} ${BitBase32-24-u11-Prefixed}[sb] */
48254 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_11_SB_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-11-SB-relative-Prefixed", "band", 32,
48255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48257 /* band${X} ${BitBase32-24-u19-Prefixed}[sb] */
48259 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_SB_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-19-SB-relative-Prefixed", "band", 40,
48260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48262 /* band${X} ${BitBase32-24-s11-Prefixed}[fb] */
48264 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_11_FB_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-11-FB-relative-Prefixed", "band", 32,
48265 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48267 /* band${X} ${BitBase32-24-s19-Prefixed}[fb] */
48269 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_FB_RELATIVE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-19-FB-relative-Prefixed", "band", 40,
48270 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48272 /* band${X} ${BitBase32-24-u19-Prefixed} */
48274 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_19_ABSOLUTE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-19-absolute-Prefixed", "band", 40,
48275 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48277 /* band${X} ${BitBase32-24-u27-Prefixed} */
48279 M32C_INSN_BAND32_X_BIT32_24_PREFIXED_BIT32_24_27_ABSOLUTE_PREFIXED, "band32-X-bit32-24-Prefixed-bit32-24-27-absolute-Prefixed", "band", 48,
48280 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48282 /* band${X} $Bitno16R,$Bit16Rn */
48284 M32C_INSN_BAND16_X_BIT16_16_BIT16_RN_DIRECT, "band16-X-bit16-16-bit16-Rn-direct", "band", 24,
48285 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48287 /* band${X} $Bitno16R,$Bit16An */
48289 M32C_INSN_BAND16_X_BIT16_16_BIT16_AN_DIRECT, "band16-X-bit16-16-bit16-An-direct", "band", 24,
48290 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48292 /* band${X} [$Bit16An] */
48294 M32C_INSN_BAND16_X_BIT16_16_BIT16_AN_INDIRECT, "band16-X-bit16-16-bit16-An-indirect", "band", 16,
48295 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48297 /* band${X} ${Dsp-16-u8}[$Bit16An] */
48299 M32C_INSN_BAND16_X_BIT16_16_BIT16_16_8_AN_RELATIVE, "band16-X-bit16-16-bit16-16-8-An-relative", "band", 24,
48300 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48302 /* band${X} ${Dsp-16-u16}[$Bit16An] */
48304 M32C_INSN_BAND16_X_BIT16_16_BIT16_16_16_AN_RELATIVE, "band16-X-bit16-16-bit16-16-16-An-relative", "band", 32,
48305 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48307 /* band${X} ${BitBase16-16-u8}[sb] */
48309 M32C_INSN_BAND16_X_BIT16_16_BIT16_16_8_SB_RELATIVE, "band16-X-bit16-16-bit16-16-8-SB-relative", "band", 24,
48310 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48312 /* band${X} ${BitBase16-16-u16}[sb] */
48314 M32C_INSN_BAND16_X_BIT16_16_BIT16_16_16_SB_RELATIVE, "band16-X-bit16-16-bit16-16-16-SB-relative", "band", 32,
48315 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48317 /* band${X} ${BitBase16-16-s8}[fb] */
48319 M32C_INSN_BAND16_X_BIT16_16_BIT16_16_8_FB_RELATIVE, "band16-X-bit16-16-bit16-16-8-FB-relative", "band", 24,
48320 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48322 /* band${X} ${BitBase16-16-u16} */
48324 M32C_INSN_BAND16_X_BIT16_16_BIT16_16_16_ABSOLUTE, "band16-X-bit16-16-bit16-16-16-absolute", "band", 32,
48325 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48327 /* and.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
48329 M32C_INSN_AND32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "and32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "and.w", 32,
48330 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48332 /* and.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
48334 M32C_INSN_AND32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "and32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "and.w", 32,
48335 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48337 /* and.w${S} #${Imm-24-HI},${Dsp-8-u16} */
48339 M32C_INSN_AND32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "and32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "and.w", 40,
48340 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48342 /* and.w${S} #${Imm-8-HI},r0 */
48344 M32C_INSN_AND32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "and32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "and.w", 24,
48345 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48347 /* and.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
48349 M32C_INSN_AND32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "and32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "and.b", 24,
48350 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48352 /* and.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
48354 M32C_INSN_AND32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "and32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "and.b", 24,
48355 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48357 /* and.b${S} #${Imm-24-QI},${Dsp-8-u16} */
48359 M32C_INSN_AND32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "and32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "and.b", 32,
48360 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48362 /* and.b${S} #${Imm-8-QI},r0l */
48364 M32C_INSN_AND32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "and32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "and.b", 16,
48365 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48367 /* and.b${S} ${SrcDst16-r0l-r0h-S-normal} */
48369 M32C_INSN_AND16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, "and16.b.S-r0l-r0h-srcdst16-r0l-r0h-S-derived", "and.b", 8,
48370 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48372 /* and.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
48374 M32C_INSN_AND16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, "and16.b.S-src2-src16-2-S-8-SB-relative-QI", "and.b", 16,
48375 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48377 /* and.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
48379 M32C_INSN_AND16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, "and16.b.S-src2-src16-2-S-8-FB-relative-QI", "and.b", 16,
48380 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48382 /* and.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
48384 M32C_INSN_AND16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, "and16.b.S-src2-src16-2-S-16-absolute-QI", "and.b", 24,
48385 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
48387 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
48389 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 24,
48390 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48392 /* and.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
48394 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 24,
48395 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48397 /* and.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
48399 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 24,
48400 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48402 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
48404 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 24,
48405 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48407 /* and.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
48409 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 24,
48410 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48412 /* and.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
48414 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 24,
48415 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48417 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
48419 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 24,
48420 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48422 /* and.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
48424 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 24,
48425 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48427 /* and.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
48429 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 24,
48430 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48432 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
48434 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "and.w", 32,
48435 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48437 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
48439 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "and.w", 32,
48440 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48442 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
48444 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "and.w", 32,
48445 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48447 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
48449 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "and.w", 40,
48450 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48452 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
48454 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "and.w", 40,
48455 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48457 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
48459 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "and.w", 40,
48460 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48462 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
48464 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "and.w", 48,
48465 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48467 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
48469 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "and.w", 48,
48470 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48472 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
48474 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "and.w", 48,
48475 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48477 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
48479 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "and.w", 32,
48480 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48482 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
48484 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "and.w", 32,
48485 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48487 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
48489 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "and.w", 32,
48490 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48492 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
48494 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "and.w", 40,
48495 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48497 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
48499 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "and.w", 40,
48500 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48502 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
48504 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "and.w", 40,
48505 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48507 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
48509 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "and.w", 32,
48510 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48512 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
48514 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "and.w", 32,
48515 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48517 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
48519 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "and.w", 32,
48520 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48522 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
48524 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "and.w", 40,
48525 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48527 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
48529 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "and.w", 40,
48530 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48532 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
48534 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "and.w", 40,
48535 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48537 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
48539 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "and.w", 40,
48540 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48542 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
48544 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "and.w", 40,
48545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48547 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
48549 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "and.w", 40,
48550 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48552 /* and.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
48554 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "and.w", 48,
48555 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48557 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
48559 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "and.w", 48,
48560 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48562 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
48564 M32C_INSN_AND32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "and.w", 48,
48565 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48567 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
48569 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 32,
48570 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48572 /* and.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
48574 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 32,
48575 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48577 /* and.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
48579 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 32,
48580 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48582 /* and.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
48584 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 32,
48585 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48587 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
48589 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 32,
48590 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48592 /* and.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
48594 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 32,
48595 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48597 /* and.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
48599 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 32,
48600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48602 /* and.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
48604 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 32,
48605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48607 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
48609 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 32,
48610 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48612 /* and.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
48614 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 32,
48615 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48617 /* and.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
48619 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 32,
48620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48622 /* and.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
48624 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 32,
48625 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48627 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
48629 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "and.w", 40,
48630 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48632 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
48634 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "and.w", 40,
48635 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48637 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
48639 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "and.w", 40,
48640 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48642 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
48644 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "and.w", 40,
48645 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48647 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
48649 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "and.w", 48,
48650 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48652 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
48654 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "and.w", 48,
48655 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48657 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
48659 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "and.w", 48,
48660 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48662 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
48664 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "and.w", 48,
48665 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48667 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
48669 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "and.w", 56,
48670 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48672 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
48674 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "and.w", 56,
48675 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48677 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
48679 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "and.w", 56,
48680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48682 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
48684 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "and.w", 56,
48685 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48687 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
48689 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "and.w", 40,
48690 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48692 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
48694 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "and.w", 40,
48695 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48697 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
48699 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "and.w", 40,
48700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48702 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
48704 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "and.w", 40,
48705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48707 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
48709 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "and.w", 48,
48710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48712 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
48714 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "and.w", 48,
48715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48717 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
48719 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "and.w", 48,
48720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48722 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
48724 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "and.w", 48,
48725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48727 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
48729 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "and.w", 40,
48730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48732 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
48734 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "and.w", 40,
48735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48737 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
48739 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "and.w", 40,
48740 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48742 /* and.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
48744 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "and.w", 40,
48745 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48747 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
48749 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "and.w", 48,
48750 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48752 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
48754 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "and.w", 48,
48755 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48757 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
48759 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "and.w", 48,
48760 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48762 /* and.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
48764 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "and.w", 48,
48765 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48767 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
48769 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "and.w", 48,
48770 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48772 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
48774 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "and.w", 48,
48775 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48777 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
48779 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "and.w", 48,
48780 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48782 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
48784 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "and.w", 48,
48785 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48787 /* and.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
48789 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "and.w", 56,
48790 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48792 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
48794 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "and.w", 56,
48795 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48797 /* and.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
48799 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "and.w", 56,
48800 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48802 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
48804 M32C_INSN_AND32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "and.w", 56,
48805 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48807 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
48809 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 40,
48810 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48812 /* and.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
48814 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 40,
48815 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48817 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
48819 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 40,
48820 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48822 /* and.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
48824 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 40,
48825 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48827 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
48829 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 40,
48830 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48832 /* and.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
48834 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 40,
48835 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48837 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
48839 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "and.w", 48,
48840 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48842 /* and.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
48844 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "and.w", 48,
48845 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48847 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
48849 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "and.w", 56,
48850 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48852 /* and.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
48854 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "and.w", 56,
48855 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48857 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
48859 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "and.w", 64,
48860 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48862 /* and.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
48864 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "and.w", 64,
48865 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48867 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
48869 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "and.w", 48,
48870 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48872 /* and.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
48874 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "and.w", 48,
48875 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48877 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
48879 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "and.w", 56,
48880 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48882 /* and.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
48884 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "and.w", 56,
48885 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48887 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
48889 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "and.w", 48,
48890 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48892 /* and.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
48894 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "and.w", 48,
48895 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48897 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
48899 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "and.w", 56,
48900 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48902 /* and.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
48904 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "and.w", 56,
48905 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48907 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
48909 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "and.w", 56,
48910 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48912 /* and.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
48914 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "and.w", 56,
48915 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48917 /* and.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
48919 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "and.w", 64,
48920 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48922 /* and.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
48924 M32C_INSN_AND32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "and.w", 64,
48925 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48927 /* and.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
48929 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 16,
48930 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48932 /* and.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
48934 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 16,
48935 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48937 /* and.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
48939 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "and.w", 16,
48940 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48942 /* and.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
48944 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 16,
48945 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48947 /* and.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
48949 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 16,
48950 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48952 /* and.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
48954 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "and.w", 16,
48955 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48957 /* and.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
48959 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 16,
48960 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48962 /* and.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
48964 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 16,
48965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48967 /* and.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
48969 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "and.w", 16,
48970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48972 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
48974 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "and.w", 24,
48975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48977 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
48979 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "and.w", 24,
48980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48982 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
48984 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "and.w", 24,
48985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48987 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
48989 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "and.w", 32,
48990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48992 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
48994 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "and.w", 32,
48995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
48997 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
48999 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "and.w", 32,
49000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49002 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
49004 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "and.w", 40,
49005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49007 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
49009 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "and.w", 40,
49010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49012 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
49014 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "and.w", 40,
49015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49017 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
49019 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "and.w", 24,
49020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49022 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
49024 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "and.w", 24,
49025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49027 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
49029 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "and.w", 24,
49030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49032 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
49034 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "and.w", 32,
49035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49037 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
49039 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "and.w", 32,
49040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49042 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
49044 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "and.w", 32,
49045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49047 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
49049 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "and.w", 24,
49050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49052 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
49054 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "and.w", 24,
49055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49057 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
49059 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "and.w", 24,
49060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49062 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
49064 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "and.w", 32,
49065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49067 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
49069 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "and.w", 32,
49070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49072 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
49074 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "and.w", 32,
49075 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49077 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
49079 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "and.w", 32,
49080 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49082 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
49084 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "and.w", 32,
49085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49087 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
49089 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "and.w", 32,
49090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49092 /* and.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
49094 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "and.w", 40,
49095 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49097 /* and.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
49099 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "and.w", 40,
49100 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49102 /* and.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
49104 M32C_INSN_AND32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "and.w", 40,
49105 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49107 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
49109 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 24,
49110 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49112 /* and.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
49114 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 24,
49115 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49117 /* and.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
49119 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 24,
49120 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49122 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
49124 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 24,
49125 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49127 /* and.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
49129 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 24,
49130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49132 /* and.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
49134 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 24,
49135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49137 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
49139 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 24,
49140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49142 /* and.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
49144 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 24,
49145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49147 /* and.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
49149 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 24,
49150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49152 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
49154 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "and.b", 32,
49155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49157 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
49159 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "and.b", 32,
49160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49162 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
49164 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "and.b", 32,
49165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49167 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
49169 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "and.b", 40,
49170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49172 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
49174 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "and.b", 40,
49175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49177 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
49179 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "and.b", 40,
49180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49182 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
49184 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "and.b", 48,
49185 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49187 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
49189 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "and.b", 48,
49190 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49192 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
49194 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "and.b", 48,
49195 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49197 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
49199 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "and.b", 32,
49200 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49202 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
49204 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "and.b", 32,
49205 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49207 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
49209 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "and.b", 32,
49210 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49212 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
49214 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "and.b", 40,
49215 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49217 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
49219 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "and.b", 40,
49220 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49222 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
49224 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "and.b", 40,
49225 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49227 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
49229 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "and.b", 32,
49230 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49232 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
49234 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "and.b", 32,
49235 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49237 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
49239 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "and.b", 32,
49240 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49242 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
49244 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "and.b", 40,
49245 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49247 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
49249 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "and.b", 40,
49250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49252 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
49254 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "and.b", 40,
49255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49257 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
49259 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "and.b", 40,
49260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49262 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
49264 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "and.b", 40,
49265 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49267 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
49269 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "and.b", 40,
49270 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49272 /* and.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
49274 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "and.b", 48,
49275 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49277 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
49279 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "and.b", 48,
49280 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49282 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
49284 M32C_INSN_AND32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "and.b", 48,
49285 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49287 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
49289 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 32,
49290 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49292 /* and.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
49294 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 32,
49295 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49297 /* and.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
49299 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 32,
49300 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49302 /* and.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
49304 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 32,
49305 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49307 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
49309 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 32,
49310 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49312 /* and.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
49314 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 32,
49315 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49317 /* and.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
49319 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 32,
49320 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49322 /* and.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
49324 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 32,
49325 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49327 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
49329 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 32,
49330 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49332 /* and.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
49334 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 32,
49335 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49337 /* and.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
49339 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 32,
49340 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49342 /* and.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
49344 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 32,
49345 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49347 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
49349 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "and.b", 40,
49350 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49352 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
49354 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "and.b", 40,
49355 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49357 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
49359 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "and.b", 40,
49360 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49362 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
49364 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "and.b", 40,
49365 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49367 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
49369 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "and.b", 48,
49370 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49372 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
49374 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "and.b", 48,
49375 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49377 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
49379 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "and.b", 48,
49380 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49382 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
49384 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "and.b", 48,
49385 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49387 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
49389 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "and.b", 56,
49390 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49392 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
49394 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "and.b", 56,
49395 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49397 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
49399 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "and.b", 56,
49400 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49402 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
49404 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "and.b", 56,
49405 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49407 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
49409 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "and.b", 40,
49410 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49412 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
49414 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "and.b", 40,
49415 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49417 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
49419 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "and.b", 40,
49420 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49422 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
49424 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "and.b", 40,
49425 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49427 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
49429 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "and.b", 48,
49430 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49432 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
49434 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "and.b", 48,
49435 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49437 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
49439 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "and.b", 48,
49440 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49442 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
49444 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "and.b", 48,
49445 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49447 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
49449 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "and.b", 40,
49450 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49452 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
49454 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "and.b", 40,
49455 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49457 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
49459 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "and.b", 40,
49460 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49462 /* and.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
49464 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "and.b", 40,
49465 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49467 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
49469 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "and.b", 48,
49470 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49472 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
49474 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "and.b", 48,
49475 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49477 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
49479 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "and.b", 48,
49480 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49482 /* and.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
49484 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "and.b", 48,
49485 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49487 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
49489 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "and.b", 48,
49490 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49492 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
49494 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "and.b", 48,
49495 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49497 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
49499 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "and.b", 48,
49500 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49502 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
49504 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "and.b", 48,
49505 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49507 /* and.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
49509 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "and.b", 56,
49510 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49512 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
49514 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "and.b", 56,
49515 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49517 /* and.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
49519 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "and.b", 56,
49520 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49522 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
49524 M32C_INSN_AND32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "and.b", 56,
49525 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49527 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
49529 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 40,
49530 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49532 /* and.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
49534 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 40,
49535 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49537 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
49539 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 40,
49540 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49542 /* and.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
49544 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 40,
49545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49547 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
49549 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 40,
49550 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49552 /* and.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
49554 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 40,
49555 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49557 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
49559 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "and.b", 48,
49560 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49562 /* and.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
49564 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "and.b", 48,
49565 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49567 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
49569 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "and.b", 56,
49570 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49572 /* and.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
49574 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "and.b", 56,
49575 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49577 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
49579 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "and.b", 64,
49580 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49582 /* and.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
49584 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "and.b", 64,
49585 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49587 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
49589 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "and.b", 48,
49590 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49592 /* and.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
49594 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "and.b", 48,
49595 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49597 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
49599 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "and.b", 56,
49600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49602 /* and.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
49604 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "and.b", 56,
49605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49607 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
49609 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "and.b", 48,
49610 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49612 /* and.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
49614 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "and.b", 48,
49615 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49617 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
49619 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "and.b", 56,
49620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49622 /* and.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
49624 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "and.b", 56,
49625 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49627 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
49629 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "and.b", 56,
49630 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49632 /* and.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
49634 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "and.b", 56,
49635 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49637 /* and.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
49639 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "and.b", 64,
49640 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49642 /* and.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
49644 M32C_INSN_AND32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "and.b", 64,
49645 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49647 /* and.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
49649 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 16,
49650 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49652 /* and.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
49654 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 16,
49655 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49657 /* and.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
49659 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "and.b", 16,
49660 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49662 /* and.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
49664 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 16,
49665 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49667 /* and.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
49669 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 16,
49670 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49672 /* and.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
49674 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "and.b", 16,
49675 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49677 /* and.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
49679 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 16,
49680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49682 /* and.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
49684 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 16,
49685 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49687 /* and.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
49689 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "and.b", 16,
49690 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49692 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
49694 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "and.b", 24,
49695 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49697 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
49699 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "and.b", 24,
49700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49702 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
49704 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "and.b", 24,
49705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49707 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
49709 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "and.b", 32,
49710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49712 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
49714 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "and.b", 32,
49715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49717 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
49719 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "and.b", 32,
49720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49722 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
49724 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "and.b", 40,
49725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49727 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
49729 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "and.b", 40,
49730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49732 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
49734 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "and.b", 40,
49735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49737 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
49739 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "and.b", 24,
49740 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49742 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
49744 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "and.b", 24,
49745 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49747 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
49749 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "and.b", 24,
49750 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49752 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
49754 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "and.b", 32,
49755 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49757 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
49759 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "and.b", 32,
49760 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49762 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
49764 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "and.b", 32,
49765 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49767 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
49769 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "and.b", 24,
49770 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49772 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
49774 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "and.b", 24,
49775 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49777 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
49779 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "and.b", 24,
49780 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49782 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
49784 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "and.b", 32,
49785 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49787 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
49789 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "and.b", 32,
49790 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49792 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
49794 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "and.b", 32,
49795 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49797 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
49799 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "and.b", 32,
49800 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49802 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
49804 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "and.b", 32,
49805 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49807 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
49809 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "and.b", 32,
49810 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49812 /* and.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
49814 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "and.b", 40,
49815 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49817 /* and.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
49819 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "and.b", 40,
49820 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49822 /* and.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
49824 M32C_INSN_AND32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "and.b", 40,
49825 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
49827 /* and.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
49829 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "and.w", 24,
49830 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
49832 /* and.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
49834 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "and.w", 24,
49835 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
49837 /* and.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
49839 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "and.w", 24,
49840 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
49842 /* and.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
49844 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "and.w", 24,
49845 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
49847 /* and.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
49849 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "and.w", 24,
49850 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
49852 /* and.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
49854 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "and.w", 24,
49855 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
49857 /* and.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
49859 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "and.w", 24,
49860 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
49862 /* and.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
49864 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "and.w", 24,
49865 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
49867 /* and.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
49869 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "and.w", 24,
49870 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
49872 /* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
49874 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "and.w", 32,
49875 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
49877 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
49879 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "and.w", 32,
49880 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
49882 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
49884 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "and.w", 32,
49885 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
49887 /* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
49889 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "and.w", 40,
49890 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
49892 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
49894 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "and.w", 40,
49895 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
49897 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
49899 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "and.w", 40,
49900 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
49902 /* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
49904 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "and.w", 32,
49905 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
49907 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
49909 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "and.w", 32,
49910 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
49912 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
49914 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "and.w", 32,
49915 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
49917 /* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
49919 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "and.w", 40,
49920 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
49922 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
49924 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "and.w", 40,
49925 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
49927 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
49929 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "and.w", 40,
49930 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
49932 /* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
49934 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "and.w", 32,
49935 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
49937 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
49939 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "and.w", 32,
49940 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
49942 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
49944 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "and.w", 32,
49945 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
49947 /* and.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
49949 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "and16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "and.w", 40,
49950 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
49952 /* and.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
49954 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "and16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "and.w", 40,
49955 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
49957 /* and.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
49959 M32C_INSN_AND16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "and16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "and.w", 40,
49960 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
49962 /* and.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
49964 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "and.w", 32,
49965 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
49967 /* and.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
49969 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "and.w", 32,
49970 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
49972 /* and.w${G} ${Dsp-16-u16},$Dst16RnHI */
49974 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "and.w", 32,
49975 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
49977 /* and.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
49979 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "and.w", 32,
49980 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
49982 /* and.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
49984 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "and.w", 32,
49985 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
49987 /* and.w${G} ${Dsp-16-u16},$Dst16AnHI */
49989 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "and.w", 32,
49990 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
49992 /* and.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
49994 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "and.w", 32,
49995 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
49997 /* and.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
49999 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "and.w", 32,
50000 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50002 /* and.w${G} ${Dsp-16-u16},[$Dst16An] */
50004 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "and.w", 32,
50005 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50007 /* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
50009 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "and.w", 40,
50010 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50012 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
50014 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "and.w", 40,
50015 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50017 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
50019 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "and.w", 40,
50020 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50022 /* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
50024 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "and.w", 48,
50025 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50027 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
50029 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "and.w", 48,
50030 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50032 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
50034 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "and.w", 48,
50035 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50037 /* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
50039 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "and.w", 40,
50040 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50042 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
50044 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "and.w", 40,
50045 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50047 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
50049 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "and.w", 40,
50050 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50052 /* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
50054 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "and.w", 48,
50055 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50057 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
50059 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "and.w", 48,
50060 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50062 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
50064 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "and.w", 48,
50065 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50067 /* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
50069 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "and.w", 40,
50070 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50072 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
50074 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "and.w", 40,
50075 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50077 /* and.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
50079 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "and.w", 40,
50080 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50082 /* and.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
50084 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "and16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "and.w", 48,
50085 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50087 /* and.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
50089 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "and16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "and.w", 48,
50090 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50092 /* and.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
50094 M32C_INSN_AND16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "and16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "and.w", 48,
50095 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50097 /* and.w${G} $Src16RnHI,$Dst16RnHI */
50099 M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "and.w", 16,
50100 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50102 /* and.w${G} $Src16AnHI,$Dst16RnHI */
50104 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "and.w", 16,
50105 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50107 /* and.w${G} [$Src16An],$Dst16RnHI */
50109 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "and.w", 16,
50110 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50112 /* and.w${G} $Src16RnHI,$Dst16AnHI */
50114 M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "and.w", 16,
50115 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50117 /* and.w${G} $Src16AnHI,$Dst16AnHI */
50119 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "and.w", 16,
50120 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50122 /* and.w${G} [$Src16An],$Dst16AnHI */
50124 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "and.w", 16,
50125 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50127 /* and.w${G} $Src16RnHI,[$Dst16An] */
50129 M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "and.w", 16,
50130 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50132 /* and.w${G} $Src16AnHI,[$Dst16An] */
50134 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "and.w", 16,
50135 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50137 /* and.w${G} [$Src16An],[$Dst16An] */
50139 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "and.w", 16,
50140 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50142 /* and.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
50144 M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "and.w", 24,
50145 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50147 /* and.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
50149 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "and.w", 24,
50150 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50152 /* and.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
50154 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "and.w", 24,
50155 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50157 /* and.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
50159 M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "and.w", 32,
50160 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50162 /* and.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
50164 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "and.w", 32,
50165 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50167 /* and.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
50169 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "and.w", 32,
50170 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50172 /* and.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
50174 M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "and.w", 24,
50175 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50177 /* and.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
50179 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "and.w", 24,
50180 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50182 /* and.w${G} [$Src16An],${Dsp-16-u8}[sb] */
50184 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "and.w", 24,
50185 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50187 /* and.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
50189 M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "and.w", 32,
50190 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50192 /* and.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
50194 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "and.w", 32,
50195 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50197 /* and.w${G} [$Src16An],${Dsp-16-u16}[sb] */
50199 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "and.w", 32,
50200 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50202 /* and.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
50204 M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "and.w", 24,
50205 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50207 /* and.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
50209 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "and.w", 24,
50210 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50212 /* and.w${G} [$Src16An],${Dsp-16-s8}[fb] */
50214 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "and.w", 24,
50215 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50217 /* and.w${G} $Src16RnHI,${Dsp-16-u16} */
50219 M32C_INSN_AND16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "and16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "and.w", 32,
50220 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50222 /* and.w${G} $Src16AnHI,${Dsp-16-u16} */
50224 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "and16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "and.w", 32,
50225 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50227 /* and.w${G} [$Src16An],${Dsp-16-u16} */
50229 M32C_INSN_AND16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "and16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "and.w", 32,
50230 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50232 /* and.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
50234 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "and.b", 24,
50235 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50237 /* and.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
50239 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "and.b", 24,
50240 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50242 /* and.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
50244 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "and.b", 24,
50245 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50247 /* and.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
50249 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "and.b", 24,
50250 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50252 /* and.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
50254 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "and.b", 24,
50255 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50257 /* and.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
50259 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "and.b", 24,
50260 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50262 /* and.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
50264 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "and.b", 24,
50265 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50267 /* and.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
50269 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "and.b", 24,
50270 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50272 /* and.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
50274 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "and.b", 24,
50275 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50277 /* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
50279 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "and.b", 32,
50280 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50282 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
50284 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "and.b", 32,
50285 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50287 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
50289 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "and.b", 32,
50290 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50292 /* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
50294 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "and.b", 40,
50295 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50297 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
50299 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "and.b", 40,
50300 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50302 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
50304 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "and.b", 40,
50305 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50307 /* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
50309 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "and.b", 32,
50310 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50312 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
50314 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "and.b", 32,
50315 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50317 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
50319 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "and.b", 32,
50320 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50322 /* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
50324 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "and.b", 40,
50325 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50327 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
50329 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "and.b", 40,
50330 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50332 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
50334 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "and.b", 40,
50335 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50337 /* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
50339 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "and.b", 32,
50340 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50342 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
50344 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "and.b", 32,
50345 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50347 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
50349 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "and.b", 32,
50350 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50352 /* and.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
50354 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "and16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "and.b", 40,
50355 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50357 /* and.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
50359 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "and16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "and.b", 40,
50360 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50362 /* and.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
50364 M32C_INSN_AND16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "and16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "and.b", 40,
50365 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50367 /* and.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
50369 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "and.b", 32,
50370 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50372 /* and.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
50374 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "and.b", 32,
50375 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50377 /* and.b${G} ${Dsp-16-u16},$Dst16RnQI */
50379 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "and.b", 32,
50380 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50382 /* and.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
50384 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "and.b", 32,
50385 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50387 /* and.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
50389 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "and.b", 32,
50390 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50392 /* and.b${G} ${Dsp-16-u16},$Dst16AnQI */
50394 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "and.b", 32,
50395 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50397 /* and.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
50399 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "and.b", 32,
50400 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50402 /* and.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
50404 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "and.b", 32,
50405 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50407 /* and.b${G} ${Dsp-16-u16},[$Dst16An] */
50409 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "and.b", 32,
50410 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50412 /* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
50414 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "and.b", 40,
50415 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50417 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
50419 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "and.b", 40,
50420 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50422 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
50424 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "and.b", 40,
50425 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50427 /* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
50429 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "and.b", 48,
50430 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50432 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
50434 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "and.b", 48,
50435 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50437 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
50439 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "and.b", 48,
50440 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50442 /* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
50444 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "and.b", 40,
50445 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50447 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
50449 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "and.b", 40,
50450 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50452 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
50454 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "and.b", 40,
50455 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50457 /* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
50459 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "and.b", 48,
50460 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50462 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
50464 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "and.b", 48,
50465 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50467 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
50469 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "and.b", 48,
50470 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50472 /* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
50474 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "and.b", 40,
50475 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50477 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
50479 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "and.b", 40,
50480 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50482 /* and.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
50484 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "and.b", 40,
50485 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50487 /* and.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
50489 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "and16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "and.b", 48,
50490 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50492 /* and.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
50494 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "and16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "and.b", 48,
50495 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50497 /* and.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
50499 M32C_INSN_AND16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "and16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "and.b", 48,
50500 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50502 /* and.b${G} $Src16RnQI,$Dst16RnQI */
50504 M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "and.b", 16,
50505 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50507 /* and.b${G} $Src16AnQI,$Dst16RnQI */
50509 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "and.b", 16,
50510 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50512 /* and.b${G} [$Src16An],$Dst16RnQI */
50514 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "and.b", 16,
50515 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50517 /* and.b${G} $Src16RnQI,$Dst16AnQI */
50519 M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "and.b", 16,
50520 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50522 /* and.b${G} $Src16AnQI,$Dst16AnQI */
50524 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "and.b", 16,
50525 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50527 /* and.b${G} [$Src16An],$Dst16AnQI */
50529 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "and.b", 16,
50530 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50532 /* and.b${G} $Src16RnQI,[$Dst16An] */
50534 M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "and.b", 16,
50535 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50537 /* and.b${G} $Src16AnQI,[$Dst16An] */
50539 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "and.b", 16,
50540 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50542 /* and.b${G} [$Src16An],[$Dst16An] */
50544 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "and.b", 16,
50545 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50547 /* and.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
50549 M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "and.b", 24,
50550 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50552 /* and.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
50554 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "and.b", 24,
50555 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50557 /* and.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
50559 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "and.b", 24,
50560 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50562 /* and.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
50564 M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "and.b", 32,
50565 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50567 /* and.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
50569 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "and.b", 32,
50570 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50572 /* and.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
50574 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "and.b", 32,
50575 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50577 /* and.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
50579 M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "and.b", 24,
50580 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50582 /* and.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
50584 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "and.b", 24,
50585 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50587 /* and.b${G} [$Src16An],${Dsp-16-u8}[sb] */
50589 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "and.b", 24,
50590 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50592 /* and.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
50594 M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "and.b", 32,
50595 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50597 /* and.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
50599 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "and.b", 32,
50600 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50602 /* and.b${G} [$Src16An],${Dsp-16-u16}[sb] */
50604 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "and.b", 32,
50605 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50607 /* and.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
50609 M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "and.b", 24,
50610 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50612 /* and.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
50614 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "and.b", 24,
50615 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50617 /* and.b${G} [$Src16An],${Dsp-16-s8}[fb] */
50619 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "and.b", 24,
50620 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50622 /* and.b${G} $Src16RnQI,${Dsp-16-u16} */
50624 M32C_INSN_AND16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "and16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "and.b", 32,
50625 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50627 /* and.b${G} $Src16AnQI,${Dsp-16-u16} */
50629 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "and16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "and.b", 32,
50630 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50632 /* and.b${G} [$Src16An],${Dsp-16-u16} */
50634 M32C_INSN_AND16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "and16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "and.b", 32,
50635 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50637 /* and.b${S} #${Imm-8-QI},r0l */
50639 M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "and16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "and.b", 16,
50640 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50642 /* and.b${S} #${Imm-8-QI},r0h */
50644 M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "and16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "and.b", 16,
50645 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50647 /* and.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
50649 M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "and16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "and.b", 24,
50650 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50652 /* and.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
50654 M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "and16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "and.b", 24,
50655 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50657 /* and.b${S} #${Imm-8-QI},${Dsp-16-u16} */
50659 M32C_INSN_AND16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "and16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "and.b", 32,
50660 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50662 /* and.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
50664 M32C_INSN_AND32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "and32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "and.w", 32,
50665 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50667 /* and.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
50669 M32C_INSN_AND32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "and32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "and.w", 32,
50670 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50672 /* and.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
50674 M32C_INSN_AND32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "and32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "and.w", 32,
50675 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50677 /* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
50679 M32C_INSN_AND32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "and.w", 40,
50680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50682 /* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
50684 M32C_INSN_AND32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "and.w", 40,
50685 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50687 /* and.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
50689 M32C_INSN_AND32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "and.w", 40,
50690 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50692 /* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
50694 M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "and.w", 48,
50695 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50697 /* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
50699 M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "and.w", 48,
50700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50702 /* and.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
50704 M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "and.w", 48,
50705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50707 /* and.w${G} #${Imm-32-HI},${Dsp-16-u16} */
50709 M32C_INSN_AND32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "and32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "and.w", 48,
50710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50712 /* and.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
50714 M32C_INSN_AND32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "and32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "and.w", 56,
50715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50717 /* and.w${G} #${Imm-40-HI},${Dsp-16-u24} */
50719 M32C_INSN_AND32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "and32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "and.w", 56,
50720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50722 /* and.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
50724 M32C_INSN_AND32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "and32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "and.b", 24,
50725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50727 /* and.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
50729 M32C_INSN_AND32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "and32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "and.b", 24,
50730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50732 /* and.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
50734 M32C_INSN_AND32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "and32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "and.b", 24,
50735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50737 /* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
50739 M32C_INSN_AND32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "and.b", 32,
50740 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50742 /* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
50744 M32C_INSN_AND32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "and.b", 32,
50745 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50747 /* and.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
50749 M32C_INSN_AND32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "and.b", 32,
50750 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50752 /* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
50754 M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "and.b", 40,
50755 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50757 /* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
50759 M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "and.b", 40,
50760 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50762 /* and.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
50764 M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "and.b", 40,
50765 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50767 /* and.b${G} #${Imm-32-QI},${Dsp-16-u16} */
50769 M32C_INSN_AND32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "and32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "and.b", 40,
50770 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50772 /* and.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
50774 M32C_INSN_AND32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "and32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "and.b", 48,
50775 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50777 /* and.b${G} #${Imm-40-QI},${Dsp-16-u24} */
50779 M32C_INSN_AND32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "and32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "and.b", 48,
50780 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
50782 /* and.w${G} #${Imm-16-HI},$Dst16RnHI */
50784 M32C_INSN_AND16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "and16.w-imm-G-basic-dst16-Rn-direct-HI", "and.w", 32,
50785 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50787 /* and.w${G} #${Imm-16-HI},$Dst16AnHI */
50789 M32C_INSN_AND16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "and16.w-imm-G-basic-dst16-An-direct-HI", "and.w", 32,
50790 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50792 /* and.w${G} #${Imm-16-HI},[$Dst16An] */
50794 M32C_INSN_AND16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "and16.w-imm-G-basic-dst16-An-indirect-HI", "and.w", 32,
50795 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50797 /* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
50799 M32C_INSN_AND16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "and16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "and.w", 40,
50800 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50802 /* and.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
50804 M32C_INSN_AND16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "and16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "and.w", 40,
50805 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50807 /* and.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
50809 M32C_INSN_AND16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "and16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "and.w", 40,
50810 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50812 /* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
50814 M32C_INSN_AND16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "and16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "and.w", 48,
50815 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50817 /* and.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
50819 M32C_INSN_AND16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "and16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "and.w", 48,
50820 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50822 /* and.w${G} #${Imm-32-HI},${Dsp-16-u16} */
50824 M32C_INSN_AND16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "and16.w-imm-G-16-16-dst16-16-16-absolute-HI", "and.w", 48,
50825 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50827 /* and.b${G} #${Imm-16-QI},$Dst16RnQI */
50829 M32C_INSN_AND16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "and16.b-imm-G-basic-dst16-Rn-direct-QI", "and.b", 24,
50830 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50832 /* and.b${G} #${Imm-16-QI},$Dst16AnQI */
50834 M32C_INSN_AND16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "and16.b-imm-G-basic-dst16-An-direct-QI", "and.b", 24,
50835 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50837 /* and.b${G} #${Imm-16-QI},[$Dst16An] */
50839 M32C_INSN_AND16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "and16.b-imm-G-basic-dst16-An-indirect-QI", "and.b", 24,
50840 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50842 /* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
50844 M32C_INSN_AND16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "and16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "and.b", 32,
50845 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50847 /* and.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
50849 M32C_INSN_AND16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "and16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "and.b", 32,
50850 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50852 /* and.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
50854 M32C_INSN_AND16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "and16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "and.b", 32,
50855 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50857 /* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
50859 M32C_INSN_AND16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "and16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "and.b", 40,
50860 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50862 /* and.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
50864 M32C_INSN_AND16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "and16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "and.b", 40,
50865 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50867 /* and.b${G} #${Imm-32-QI},${Dsp-16-u16} */
50869 M32C_INSN_AND16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "and16.b-imm-G-16-16-dst16-16-16-absolute-QI", "and.b", 40,
50870 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
50872 /* adjnz.w #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
50874 M32C_INSN_ADJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "adjnz.w", 32,
50875 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
50877 /* adjnz.w #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
50879 M32C_INSN_ADJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "adjnz.w", 32,
50880 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
50882 /* adjnz.w #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
50884 M32C_INSN_ADJNZ32_W_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "adjnz.w", 32,
50885 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
50887 /* adjnz.w #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
50889 M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "adjnz.w", 40,
50890 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
50892 /* adjnz.w #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
50894 M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "adjnz.w", 40,
50895 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
50897 /* adjnz.w #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */
50899 M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "adjnz.w", 40,
50900 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
50902 /* adjnz.w #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */
50904 M32C_INSN_ADJNZ32_W_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "adjnz32.w-imm4-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "adjnz.w", 40,
50905 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
50907 /* adjnz.w #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
50909 M32C_INSN_ADJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "adjnz32.w-imm4-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "adjnz.w", 48,
50910 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
50912 /* adjnz.w #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */
50914 M32C_INSN_ADJNZ32_W_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "adjnz32.w-imm4-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "adjnz.w", 48,
50915 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
50917 /* adjnz.w #${Imm-12-s4},$Dst32RnUnprefixedHI,${Lab-16-8} */
50919 M32C_INSN_ADJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "adjnz32.w-imm4-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "adjnz.w", 24,
50920 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
50922 /* adjnz.w #${Imm-12-s4},$Dst32AnUnprefixedHI,${Lab-16-8} */
50924 M32C_INSN_ADJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "adjnz32.w-imm4-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "adjnz.w", 24,
50925 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
50927 /* adjnz.w #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */
50929 M32C_INSN_ADJNZ32_W_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "adjnz32.w-imm4-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "adjnz.w", 24,
50930 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
50932 /* adjnz.b #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed],${Lab-24-8} */
50934 M32C_INSN_ADJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "adjnz.b", 32,
50935 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
50937 /* adjnz.b #${Imm-12-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
50939 M32C_INSN_ADJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "adjnz.b", 32,
50940 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
50942 /* adjnz.b #${Imm-12-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
50944 M32C_INSN_ADJNZ32_B_IMM4_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "adjnz.b", 32,
50945 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
50947 /* adjnz.b #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed],${Lab-32-8} */
50949 M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "adjnz.b", 40,
50950 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
50952 /* adjnz.b #${Imm-12-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
50954 M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "adjnz.b", 40,
50955 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
50957 /* adjnz.b #${Imm-12-s4},${Dsp-16-s16}[fb],${Lab-32-8} */
50959 M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "adjnz.b", 40,
50960 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
50962 /* adjnz.b #${Imm-12-s4},${Dsp-16-u16},${Lab-32-8} */
50964 M32C_INSN_ADJNZ32_B_IMM4_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "adjnz32.b-imm4-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "adjnz.b", 40,
50965 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
50967 /* adjnz.b #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed],${Lab-40-8} */
50969 M32C_INSN_ADJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "adjnz32.b-imm4-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "adjnz.b", 48,
50970 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
50972 /* adjnz.b #${Imm-12-s4},${Dsp-16-u24},${Lab-40-8} */
50974 M32C_INSN_ADJNZ32_B_IMM4_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "adjnz32.b-imm4-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "adjnz.b", 48,
50975 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
50977 /* adjnz.b #${Imm-12-s4},$Dst32RnUnprefixedQI,${Lab-16-8} */
50979 M32C_INSN_ADJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "adjnz32.b-imm4-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "adjnz.b", 24,
50980 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
50982 /* adjnz.b #${Imm-12-s4},$Dst32AnUnprefixedQI,${Lab-16-8} */
50984 M32C_INSN_ADJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "adjnz32.b-imm4-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "adjnz.b", 24,
50985 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
50987 /* adjnz.b #${Imm-12-s4},[$Dst32AnUnprefixed],${Lab-16-8} */
50989 M32C_INSN_ADJNZ32_B_IMM4_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "adjnz32.b-imm4-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "adjnz.b", 24,
50990 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
50992 /* adjnz.w #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
50994 M32C_INSN_ADJNZ16_W_IMM4_16_8_DST16_16_8_AN_RELATIVE_HI, "adjnz16.w-imm4-16-8-dst16-16-8-An-relative-HI", "adjnz.w", 32,
50995 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
50997 /* adjnz.w #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
50999 M32C_INSN_ADJNZ16_W_IMM4_16_8_DST16_16_8_SB_RELATIVE_HI, "adjnz16.w-imm4-16-8-dst16-16-8-SB-relative-HI", "adjnz.w", 32,
51000 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51002 /* adjnz.w #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
51004 M32C_INSN_ADJNZ16_W_IMM4_16_8_DST16_16_8_FB_RELATIVE_HI, "adjnz16.w-imm4-16-8-dst16-16-8-FB-relative-HI", "adjnz.w", 32,
51005 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51007 /* adjnz.w #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
51009 M32C_INSN_ADJNZ16_W_IMM4_16_16_DST16_16_16_AN_RELATIVE_HI, "adjnz16.w-imm4-16-16-dst16-16-16-An-relative-HI", "adjnz.w", 40,
51010 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51012 /* adjnz.w #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
51014 M32C_INSN_ADJNZ16_W_IMM4_16_16_DST16_16_16_SB_RELATIVE_HI, "adjnz16.w-imm4-16-16-dst16-16-16-SB-relative-HI", "adjnz.w", 40,
51015 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51017 /* adjnz.w #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */
51019 M32C_INSN_ADJNZ16_W_IMM4_16_16_DST16_16_16_ABSOLUTE_HI, "adjnz16.w-imm4-16-16-dst16-16-16-absolute-HI", "adjnz.w", 40,
51020 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51022 /* adjnz.w #${Imm-8-s4},$Dst16RnHI,${Lab-16-8} */
51024 M32C_INSN_ADJNZ16_W_IMM4_BASIC_DST16_RN_DIRECT_HI, "adjnz16.w-imm4-basic-dst16-Rn-direct-HI", "adjnz.w", 24,
51025 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51027 /* adjnz.w #${Imm-8-s4},$Dst16AnHI,${Lab-16-8} */
51029 M32C_INSN_ADJNZ16_W_IMM4_BASIC_DST16_AN_DIRECT_HI, "adjnz16.w-imm4-basic-dst16-An-direct-HI", "adjnz.w", 24,
51030 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51032 /* adjnz.w #${Imm-8-s4},[$Dst16An],${Lab-16-8} */
51034 M32C_INSN_ADJNZ16_W_IMM4_BASIC_DST16_AN_INDIRECT_HI, "adjnz16.w-imm4-basic-dst16-An-indirect-HI", "adjnz.w", 24,
51035 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51037 /* adjnz.b #${Imm-8-s4},${Dsp-16-u8}[$Dst16An],${Lab-24-8} */
51039 M32C_INSN_ADJNZ16_B_IMM4_16_8_DST16_16_8_AN_RELATIVE_QI, "adjnz16.b-imm4-16-8-dst16-16-8-An-relative-QI", "adjnz.b", 32,
51040 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51042 /* adjnz.b #${Imm-8-s4},${Dsp-16-u8}[sb],${Lab-24-8} */
51044 M32C_INSN_ADJNZ16_B_IMM4_16_8_DST16_16_8_SB_RELATIVE_QI, "adjnz16.b-imm4-16-8-dst16-16-8-SB-relative-QI", "adjnz.b", 32,
51045 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51047 /* adjnz.b #${Imm-8-s4},${Dsp-16-s8}[fb],${Lab-24-8} */
51049 M32C_INSN_ADJNZ16_B_IMM4_16_8_DST16_16_8_FB_RELATIVE_QI, "adjnz16.b-imm4-16-8-dst16-16-8-FB-relative-QI", "adjnz.b", 32,
51050 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51052 /* adjnz.b #${Imm-8-s4},${Dsp-16-u16}[$Dst16An],${Lab-32-8} */
51054 M32C_INSN_ADJNZ16_B_IMM4_16_16_DST16_16_16_AN_RELATIVE_QI, "adjnz16.b-imm4-16-16-dst16-16-16-An-relative-QI", "adjnz.b", 40,
51055 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51057 /* adjnz.b #${Imm-8-s4},${Dsp-16-u16}[sb],${Lab-32-8} */
51059 M32C_INSN_ADJNZ16_B_IMM4_16_16_DST16_16_16_SB_RELATIVE_QI, "adjnz16.b-imm4-16-16-dst16-16-16-SB-relative-QI", "adjnz.b", 40,
51060 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51062 /* adjnz.b #${Imm-8-s4},${Dsp-16-u16},${Lab-32-8} */
51064 M32C_INSN_ADJNZ16_B_IMM4_16_16_DST16_16_16_ABSOLUTE_QI, "adjnz16.b-imm4-16-16-dst16-16-16-absolute-QI", "adjnz.b", 40,
51065 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51067 /* adjnz.b #${Imm-8-s4},$Dst16RnQI,${Lab-16-8} */
51069 M32C_INSN_ADJNZ16_B_IMM4_BASIC_DST16_RN_DIRECT_QI, "adjnz16.b-imm4-basic-dst16-Rn-direct-QI", "adjnz.b", 24,
51070 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51072 /* adjnz.b #${Imm-8-s4},$Dst16AnQI,${Lab-16-8} */
51074 M32C_INSN_ADJNZ16_B_IMM4_BASIC_DST16_AN_DIRECT_QI, "adjnz16.b-imm4-basic-dst16-An-direct-QI", "adjnz.b", 24,
51075 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51077 /* adjnz.b #${Imm-8-s4},[$Dst16An],${Lab-16-8} */
51079 M32C_INSN_ADJNZ16_B_IMM4_BASIC_DST16_AN_INDIRECT_QI, "adjnz16.b-imm4-basic-dst16-An-indirect-QI", "adjnz.b", 24,
51080 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
51082 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
51084 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 24,
51085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51087 /* addx${X} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
51089 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 24,
51090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51092 /* addx${X} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
51094 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 24,
51095 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51097 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
51099 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 24,
51100 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51102 /* addx${X} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
51104 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 24,
51105 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51107 /* addx${X} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
51109 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 24,
51110 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51112 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
51114 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 24,
51115 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51117 /* addx${X} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
51119 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 24,
51120 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51122 /* addx${X} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
51124 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 24,
51125 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51127 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
51129 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "addx", 32,
51130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51132 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
51134 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "addx", 32,
51135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51137 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
51139 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-SI", "addx", 32,
51140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51142 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
51144 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "addx", 40,
51145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51147 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
51149 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "addx", 40,
51150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51152 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
51154 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-SI", "addx", 40,
51155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51157 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
51159 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "addx", 48,
51160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51162 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
51164 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "addx", 48,
51165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51167 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
51169 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-SI", "addx", 48,
51170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51172 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
51174 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "addx", 32,
51175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51177 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
51179 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "addx", 32,
51180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51182 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
51184 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-SI", "addx", 32,
51185 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51187 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
51189 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "addx", 40,
51190 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51192 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
51194 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "addx", 40,
51195 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51197 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
51199 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-SI", "addx", 40,
51200 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51202 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
51204 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "addx", 32,
51205 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51207 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
51209 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "addx", 32,
51210 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51212 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
51214 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-SI", "addx", 32,
51215 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51217 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
51219 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "addx", 40,
51220 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51222 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
51224 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "addx", 40,
51225 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51227 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
51229 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-SI", "addx", 40,
51230 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51232 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
51234 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "addx", 40,
51235 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51237 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
51239 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "addx", 40,
51240 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51242 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
51244 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-SI", "addx", 40,
51245 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51247 /* addx${X} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
51249 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "addx", 48,
51250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51252 /* addx${X} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
51254 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "addx", 48,
51255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51257 /* addx${X} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
51259 M32C_INSN_ADDX32_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-SI", "addx", 48,
51260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51262 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
51264 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 32,
51265 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51267 /* addx${X} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
51269 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 32,
51270 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51272 /* addx${X} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
51274 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 32,
51275 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51277 /* addx${X} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
51279 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 32,
51280 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51282 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
51284 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 32,
51285 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51287 /* addx${X} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
51289 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 32,
51290 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51292 /* addx${X} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
51294 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 32,
51295 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51297 /* addx${X} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
51299 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 32,
51300 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51302 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
51304 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 32,
51305 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51307 /* addx${X} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
51309 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 32,
51310 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51312 /* addx${X} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
51314 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 32,
51315 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51317 /* addx${X} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
51319 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 32,
51320 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51322 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
51324 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "addx", 40,
51325 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51327 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
51329 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "addx", 40,
51330 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51332 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
51334 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "addx", 40,
51335 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51337 /* addx${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
51339 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-SI", "addx", 40,
51340 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51342 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
51344 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "addx", 48,
51345 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51347 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
51349 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "addx", 48,
51350 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51352 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
51354 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "addx", 48,
51355 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51357 /* addx${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
51359 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-SI", "addx", 48,
51360 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51362 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
51364 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "addx", 56,
51365 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51367 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
51369 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "addx", 56,
51370 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51372 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
51374 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "addx", 56,
51375 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51377 /* addx${X} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
51379 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-SI", "addx", 56,
51380 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51382 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
51384 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "addx", 40,
51385 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51387 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
51389 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "addx", 40,
51390 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51392 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
51394 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "addx", 40,
51395 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51397 /* addx${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
51399 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-SI", "addx", 40,
51400 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51402 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
51404 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "addx", 48,
51405 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51407 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
51409 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "addx", 48,
51410 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51412 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
51414 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "addx", 48,
51415 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51417 /* addx${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
51419 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-SI", "addx", 48,
51420 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51422 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
51424 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "addx", 40,
51425 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51427 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
51429 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "addx", 40,
51430 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51432 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
51434 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "addx", 40,
51435 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51437 /* addx${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
51439 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-SI", "addx", 40,
51440 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51442 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
51444 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "addx", 48,
51445 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51447 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
51449 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "addx", 48,
51450 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51452 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
51454 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "addx", 48,
51455 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51457 /* addx${X} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
51459 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-SI", "addx", 48,
51460 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51462 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
51464 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "addx", 48,
51465 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51467 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
51469 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "addx", 48,
51470 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51472 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
51474 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "addx", 48,
51475 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51477 /* addx${X} ${Dsp-16-u16},${Dsp-32-u16} */
51479 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-SI", "addx", 48,
51480 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51482 /* addx${X} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
51484 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "addx", 56,
51485 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51487 /* addx${X} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
51489 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "addx", 56,
51490 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51492 /* addx${X} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
51494 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "addx", 56,
51495 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51497 /* addx${X} ${Dsp-16-u16},${Dsp-32-u24} */
51499 M32C_INSN_ADDX32_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-SI", "addx", 56,
51500 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51502 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
51504 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 40,
51505 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51507 /* addx${X} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
51509 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 40,
51510 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51512 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
51514 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 40,
51515 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51517 /* addx${X} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
51519 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 40,
51520 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51522 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
51524 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 40,
51525 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51527 /* addx${X} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
51529 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 40,
51530 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51532 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
51534 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-SI", "addx", 48,
51535 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51537 /* addx${X} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
51539 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-SI", "addx", 48,
51540 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51542 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
51544 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-SI", "addx", 56,
51545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51547 /* addx${X} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
51549 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-SI", "addx", 56,
51550 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51552 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
51554 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-SI", "addx", 64,
51555 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51557 /* addx${X} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
51559 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-SI", "addx", 64,
51560 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51562 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
51564 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-SI", "addx", 48,
51565 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51567 /* addx${X} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
51569 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-SI", "addx", 48,
51570 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51572 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
51574 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-SI", "addx", 56,
51575 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51577 /* addx${X} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
51579 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-SI", "addx", 56,
51580 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51582 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
51584 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-SI", "addx", 48,
51585 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51587 /* addx${X} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
51589 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-SI", "addx", 48,
51590 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51592 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
51594 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-SI", "addx", 56,
51595 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51597 /* addx${X} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
51599 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-SI", "addx", 56,
51600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51602 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
51604 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-SI", "addx", 56,
51605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51607 /* addx${X} ${Dsp-16-u24},${Dsp-40-u16} */
51609 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-SI", "addx", 56,
51610 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51612 /* addx${X} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
51614 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-SI", "addx", 64,
51615 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51617 /* addx${X} ${Dsp-16-u24},${Dsp-40-u24} */
51619 M32C_INSN_ADDX32_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "addx32-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-SI", "addx", 64,
51620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51622 /* addx${X} $Src32RnUnprefixedQI,$Dst32RnUnprefixedSI */
51624 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 16,
51625 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51627 /* addx${X} $Src32AnUnprefixedQI,$Dst32RnUnprefixedSI */
51629 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 16,
51630 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51632 /* addx${X} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
51634 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-SI", "addx", 16,
51635 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51637 /* addx${X} $Src32RnUnprefixedQI,$Dst32AnUnprefixedSI */
51639 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 16,
51640 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51642 /* addx${X} $Src32AnUnprefixedQI,$Dst32AnUnprefixedSI */
51644 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 16,
51645 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51647 /* addx${X} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
51649 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-SI", "addx", 16,
51650 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51652 /* addx${X} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
51654 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 16,
51655 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51657 /* addx${X} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
51659 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 16,
51660 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51662 /* addx${X} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
51664 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-SI", "addx", 16,
51665 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51667 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
51669 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "addx", 24,
51670 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51672 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
51674 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "addx", 24,
51675 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51677 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
51679 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-SI", "addx", 24,
51680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51682 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
51684 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "addx", 32,
51685 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51687 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
51689 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "addx", 32,
51690 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51692 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
51694 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-SI", "addx", 32,
51695 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51697 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
51699 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "addx", 40,
51700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51702 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
51704 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "addx", 40,
51705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51707 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
51709 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-SI", "addx", 40,
51710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51712 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
51714 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "addx", 24,
51715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51717 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
51719 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "addx", 24,
51720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51722 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
51724 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-SI", "addx", 24,
51725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51727 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
51729 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "addx", 32,
51730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51732 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
51734 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "addx", 32,
51735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51737 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
51739 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-SI", "addx", 32,
51740 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51742 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
51744 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "addx", 24,
51745 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51747 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
51749 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "addx", 24,
51750 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51752 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
51754 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-SI", "addx", 24,
51755 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51757 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
51759 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "addx", 32,
51760 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51762 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
51764 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "addx", 32,
51765 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51767 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
51769 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-SI", "addx", 32,
51770 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51772 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u16} */
51774 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "addx", 32,
51775 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51777 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u16} */
51779 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "addx", 32,
51780 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51782 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-u16} */
51784 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-SI", "addx", 32,
51785 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51787 /* addx${X} $Src32RnUnprefixedQI,${Dsp-16-u24} */
51789 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "addx", 40,
51790 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51792 /* addx${X} $Src32AnUnprefixedQI,${Dsp-16-u24} */
51794 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "addx", 40,
51795 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51797 /* addx${X} [$Src32AnUnprefixed],${Dsp-16-u24} */
51799 M32C_INSN_ADDX32_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "addx32-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-SI", "addx", 40,
51800 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51802 /* addx${X} #${Imm-16-QI},$Dst32RnUnprefixedSI */
51804 M32C_INSN_ADDX32_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "addx32-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "addx", 24,
51805 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51807 /* addx${X} #${Imm-16-QI},$Dst32AnUnprefixedSI */
51809 M32C_INSN_ADDX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "addx32-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "addx", 24,
51810 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51812 /* addx${X} #${Imm-16-QI},[$Dst32AnUnprefixed] */
51814 M32C_INSN_ADDX32_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "addx32-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "addx", 24,
51815 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51817 /* addx${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
51819 M32C_INSN_ADDX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "addx", 32,
51820 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51822 /* addx${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
51824 M32C_INSN_ADDX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "addx", 32,
51825 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51827 /* addx${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
51829 M32C_INSN_ADDX32_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "addx", 32,
51830 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51832 /* addx${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
51834 M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "addx", 40,
51835 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51837 /* addx${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
51839 M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "addx", 40,
51840 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51842 /* addx${X} #${Imm-32-QI},${Dsp-16-s16}[fb] */
51844 M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "addx", 40,
51845 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51847 /* addx${X} #${Imm-32-QI},${Dsp-16-u16} */
51849 M32C_INSN_ADDX32_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "addx32-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "addx", 40,
51850 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51852 /* addx${X} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
51854 M32C_INSN_ADDX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "addx32-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "addx", 48,
51855 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51857 /* addx${X} #${Imm-40-QI},${Dsp-16-u24} */
51859 M32C_INSN_ADDX32_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "addx32-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "addx", 48,
51860 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51862 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
51864 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 32,
51865 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51867 /* dadd.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
51869 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 32,
51870 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51872 /* dadd.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
51874 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 32,
51875 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51877 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
51879 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 32,
51880 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51882 /* dadd.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
51884 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 32,
51885 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51887 /* dadd.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
51889 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 32,
51890 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51892 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
51894 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 32,
51895 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51897 /* dadd.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
51899 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 32,
51900 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51902 /* dadd.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
51904 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 32,
51905 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51907 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
51909 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadd.w", 40,
51910 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51912 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
51914 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadd.w", 40,
51915 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51917 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
51919 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadd.w", 40,
51920 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51922 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
51924 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadd.w", 48,
51925 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51927 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
51929 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadd.w", 48,
51930 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51932 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
51934 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadd.w", 48,
51935 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51937 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
51939 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadd.w", 56,
51940 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51942 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
51944 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadd.w", 56,
51945 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51947 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
51949 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadd.w", 56,
51950 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51952 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
51954 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadd.w", 40,
51955 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51957 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
51959 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadd.w", 40,
51960 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51962 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
51964 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadd.w", 40,
51965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51967 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
51969 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadd.w", 48,
51970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51972 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
51974 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadd.w", 48,
51975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51977 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
51979 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadd.w", 48,
51980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51982 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
51984 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadd.w", 40,
51985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51987 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
51989 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadd.w", 40,
51990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51992 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
51994 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadd.w", 40,
51995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
51997 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
51999 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadd.w", 48,
52000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52002 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
52004 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadd.w", 48,
52005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52007 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
52009 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadd.w", 48,
52010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52012 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
52014 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadd.w", 48,
52015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52017 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
52019 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadd.w", 48,
52020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52022 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
52024 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadd.w", 48,
52025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52027 /* dadd.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
52029 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadd.w", 56,
52030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52032 /* dadd.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
52034 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadd.w", 56,
52035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52037 /* dadd.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
52039 M32C_INSN_DADD32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadd.w", 56,
52040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52042 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
52044 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 40,
52045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52047 /* dadd.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
52049 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 40,
52050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52052 /* dadd.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
52054 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 40,
52055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52057 /* dadd.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
52059 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 40,
52060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52062 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
52064 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 40,
52065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52067 /* dadd.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
52069 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 40,
52070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52072 /* dadd.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
52074 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 40,
52075 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52077 /* dadd.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
52079 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 40,
52080 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52082 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
52084 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 40,
52085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52087 /* dadd.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
52089 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 40,
52090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52092 /* dadd.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
52094 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 40,
52095 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52097 /* dadd.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
52099 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 40,
52100 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52102 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
52104 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadd.w", 48,
52105 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52107 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
52109 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadd.w", 48,
52110 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52112 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
52114 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadd.w", 48,
52115 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52117 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
52119 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadd.w", 48,
52120 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52122 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
52124 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadd.w", 56,
52125 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52127 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
52129 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadd.w", 56,
52130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52132 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
52134 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadd.w", 56,
52135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52137 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
52139 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadd.w", 56,
52140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52142 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
52144 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadd.w", 64,
52145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52147 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
52149 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadd.w", 64,
52150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52152 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
52154 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadd.w", 64,
52155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52157 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
52159 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadd.w", 64,
52160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52162 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
52164 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadd.w", 48,
52165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52167 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
52169 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadd.w", 48,
52170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52172 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
52174 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadd.w", 48,
52175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52177 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
52179 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadd.w", 48,
52180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52182 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
52184 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadd.w", 56,
52185 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52187 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
52189 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadd.w", 56,
52190 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52192 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
52194 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadd.w", 56,
52195 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52197 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
52199 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadd.w", 56,
52200 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52202 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
52204 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadd.w", 48,
52205 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52207 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
52209 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadd.w", 48,
52210 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52212 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
52214 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadd.w", 48,
52215 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52217 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
52219 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadd.w", 48,
52220 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52222 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
52224 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadd.w", 56,
52225 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52227 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
52229 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadd.w", 56,
52230 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52232 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
52234 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadd.w", 56,
52235 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52237 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
52239 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadd.w", 56,
52240 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52242 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
52244 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadd.w", 56,
52245 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52247 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
52249 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadd.w", 56,
52250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52252 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
52254 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadd.w", 56,
52255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52257 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
52259 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadd.w", 56,
52260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52262 /* dadd.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
52264 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadd.w", 64,
52265 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52267 /* dadd.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
52269 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadd.w", 64,
52270 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52272 /* dadd.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
52274 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadd.w", 64,
52275 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52277 /* dadd.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
52279 M32C_INSN_DADD32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadd.w", 64,
52280 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52282 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
52284 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 48,
52285 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52287 /* dadd.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
52289 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 48,
52290 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52292 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
52294 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 48,
52295 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52297 /* dadd.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
52299 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 48,
52300 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52302 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
52304 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 48,
52305 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52307 /* dadd.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
52309 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 48,
52310 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52312 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
52314 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dadd.w", 56,
52315 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52317 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
52319 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dadd.w", 56,
52320 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52322 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
52324 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dadd.w", 64,
52325 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52327 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
52329 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dadd.w", 64,
52330 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52332 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
52334 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dadd.w", 72,
52335 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52337 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
52339 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dadd.w", 72,
52340 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52342 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
52344 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dadd.w", 56,
52345 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52347 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
52349 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dadd.w", 56,
52350 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52352 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
52354 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dadd.w", 64,
52355 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52357 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
52359 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dadd.w", 64,
52360 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52362 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
52364 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dadd.w", 56,
52365 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52367 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
52369 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dadd.w", 56,
52370 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52372 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
52374 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dadd.w", 64,
52375 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52377 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
52379 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dadd.w", 64,
52380 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52382 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
52384 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dadd.w", 64,
52385 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52387 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
52389 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dadd.w", 64,
52390 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52392 /* dadd.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
52394 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dadd.w", 72,
52395 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52397 /* dadd.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
52399 M32C_INSN_DADD32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dadd.w", 72,
52400 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52402 /* dadd.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
52404 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 24,
52405 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52407 /* dadd.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
52409 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 24,
52410 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52412 /* dadd.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
52414 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadd.w", 24,
52415 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52417 /* dadd.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
52419 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 24,
52420 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52422 /* dadd.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
52424 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 24,
52425 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52427 /* dadd.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
52429 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadd.w", 24,
52430 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52432 /* dadd.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
52434 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 24,
52435 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52437 /* dadd.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
52439 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 24,
52440 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52442 /* dadd.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
52444 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadd.w", 24,
52445 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52447 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
52449 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadd.w", 32,
52450 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52452 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
52454 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadd.w", 32,
52455 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52457 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
52459 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadd.w", 32,
52460 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52462 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
52464 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadd.w", 40,
52465 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52467 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
52469 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadd.w", 40,
52470 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52472 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
52474 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadd.w", 40,
52475 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52477 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
52479 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadd.w", 48,
52480 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52482 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
52484 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadd.w", 48,
52485 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52487 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
52489 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadd.w", 48,
52490 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52492 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
52494 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadd.w", 32,
52495 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52497 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
52499 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadd.w", 32,
52500 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52502 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
52504 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadd.w", 32,
52505 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52507 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
52509 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadd.w", 40,
52510 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52512 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
52514 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadd.w", 40,
52515 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52517 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
52519 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadd.w", 40,
52520 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52522 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
52524 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadd.w", 32,
52525 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52527 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
52529 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadd.w", 32,
52530 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52532 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
52534 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadd.w", 32,
52535 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52537 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
52539 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadd.w", 40,
52540 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52542 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
52544 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadd.w", 40,
52545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52547 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
52549 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadd.w", 40,
52550 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52552 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
52554 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadd.w", 40,
52555 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52557 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
52559 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadd.w", 40,
52560 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52562 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
52564 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadd.w", 40,
52565 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52567 /* dadd.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
52569 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadd.w", 48,
52570 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52572 /* dadd.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
52574 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadd.w", 48,
52575 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52577 /* dadd.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
52579 M32C_INSN_DADD32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadd.w", 48,
52580 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52582 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
52584 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 32,
52585 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52587 /* dadd.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
52589 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 32,
52590 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52592 /* dadd.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
52594 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 32,
52595 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52597 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
52599 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 32,
52600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52602 /* dadd.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
52604 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 32,
52605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52607 /* dadd.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
52609 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 32,
52610 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52612 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
52614 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 32,
52615 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52617 /* dadd.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
52619 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 32,
52620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52622 /* dadd.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
52624 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 32,
52625 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52627 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
52629 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadd.b", 40,
52630 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52632 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
52634 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadd.b", 40,
52635 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52637 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
52639 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadd.b", 40,
52640 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52642 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
52644 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadd.b", 48,
52645 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52647 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
52649 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadd.b", 48,
52650 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52652 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
52654 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadd.b", 48,
52655 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52657 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
52659 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadd.b", 56,
52660 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52662 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
52664 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadd.b", 56,
52665 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52667 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
52669 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadd.b", 56,
52670 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52672 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
52674 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadd.b", 40,
52675 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52677 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
52679 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadd.b", 40,
52680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52682 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
52684 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadd.b", 40,
52685 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52687 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
52689 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadd.b", 48,
52690 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52692 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
52694 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadd.b", 48,
52695 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52697 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
52699 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadd.b", 48,
52700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52702 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
52704 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadd.b", 40,
52705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52707 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
52709 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadd.b", 40,
52710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52712 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
52714 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadd.b", 40,
52715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52717 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
52719 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadd.b", 48,
52720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52722 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
52724 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadd.b", 48,
52725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52727 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
52729 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadd.b", 48,
52730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52732 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
52734 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadd.b", 48,
52735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52737 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
52739 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadd.b", 48,
52740 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52742 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
52744 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadd.b", 48,
52745 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52747 /* dadd.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
52749 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadd.b", 56,
52750 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52752 /* dadd.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
52754 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadd.b", 56,
52755 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52757 /* dadd.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
52759 M32C_INSN_DADD32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadd.b", 56,
52760 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52762 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
52764 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 40,
52765 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52767 /* dadd.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
52769 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 40,
52770 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52772 /* dadd.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
52774 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 40,
52775 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52777 /* dadd.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
52779 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 40,
52780 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52782 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
52784 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 40,
52785 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52787 /* dadd.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
52789 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 40,
52790 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52792 /* dadd.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
52794 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 40,
52795 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52797 /* dadd.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
52799 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 40,
52800 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52802 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
52804 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 40,
52805 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52807 /* dadd.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
52809 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 40,
52810 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52812 /* dadd.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
52814 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 40,
52815 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52817 /* dadd.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
52819 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 40,
52820 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52822 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
52824 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadd.b", 48,
52825 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52827 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
52829 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadd.b", 48,
52830 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52832 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
52834 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadd.b", 48,
52835 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52837 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
52839 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadd.b", 48,
52840 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52842 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
52844 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadd.b", 56,
52845 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52847 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
52849 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadd.b", 56,
52850 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52852 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
52854 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadd.b", 56,
52855 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52857 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
52859 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadd.b", 56,
52860 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52862 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
52864 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadd.b", 64,
52865 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52867 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
52869 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadd.b", 64,
52870 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52872 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
52874 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadd.b", 64,
52875 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52877 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
52879 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadd.b", 64,
52880 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52882 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
52884 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadd.b", 48,
52885 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52887 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
52889 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadd.b", 48,
52890 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52892 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
52894 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadd.b", 48,
52895 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52897 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
52899 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadd.b", 48,
52900 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52902 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
52904 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadd.b", 56,
52905 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52907 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
52909 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadd.b", 56,
52910 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52912 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
52914 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadd.b", 56,
52915 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52917 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
52919 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadd.b", 56,
52920 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52922 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
52924 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadd.b", 48,
52925 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52927 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
52929 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadd.b", 48,
52930 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52932 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
52934 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadd.b", 48,
52935 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52937 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
52939 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadd.b", 48,
52940 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52942 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
52944 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadd.b", 56,
52945 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52947 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
52949 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadd.b", 56,
52950 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52952 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
52954 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadd.b", 56,
52955 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52957 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
52959 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadd.b", 56,
52960 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52962 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
52964 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadd.b", 56,
52965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52967 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
52969 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadd.b", 56,
52970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52972 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
52974 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadd.b", 56,
52975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52977 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
52979 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadd.b", 56,
52980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52982 /* dadd.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
52984 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadd.b", 64,
52985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52987 /* dadd.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
52989 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadd.b", 64,
52990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52992 /* dadd.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
52994 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadd.b", 64,
52995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
52997 /* dadd.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
52999 M32C_INSN_DADD32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadd.b", 64,
53000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53002 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
53004 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 48,
53005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53007 /* dadd.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
53009 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 48,
53010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53012 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
53014 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 48,
53015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53017 /* dadd.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
53019 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 48,
53020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53022 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
53024 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 48,
53025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53027 /* dadd.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
53029 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 48,
53030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53032 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
53034 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dadd.b", 56,
53035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53037 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
53039 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dadd.b", 56,
53040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53042 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
53044 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dadd.b", 64,
53045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53047 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
53049 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dadd.b", 64,
53050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53052 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
53054 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dadd.b", 72,
53055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53057 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
53059 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dadd.b", 72,
53060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53062 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
53064 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dadd.b", 56,
53065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53067 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
53069 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dadd.b", 56,
53070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53072 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
53074 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dadd.b", 64,
53075 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53077 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
53079 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dadd.b", 64,
53080 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53082 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
53084 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dadd.b", 56,
53085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53087 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
53089 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dadd.b", 56,
53090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53092 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
53094 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dadd.b", 64,
53095 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53097 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
53099 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dadd.b", 64,
53100 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53102 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
53104 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dadd.b", 64,
53105 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53107 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
53109 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dadd.b", 64,
53110 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53112 /* dadd.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
53114 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dadd.b", 72,
53115 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53117 /* dadd.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
53119 M32C_INSN_DADD32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dadd.b", 72,
53120 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53122 /* dadd.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
53124 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 24,
53125 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53127 /* dadd.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
53129 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 24,
53130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53132 /* dadd.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
53134 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadd.b", 24,
53135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53137 /* dadd.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
53139 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 24,
53140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53142 /* dadd.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
53144 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 24,
53145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53147 /* dadd.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
53149 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadd.b", 24,
53150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53152 /* dadd.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
53154 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 24,
53155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53157 /* dadd.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
53159 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 24,
53160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53162 /* dadd.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
53164 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadd.b", 24,
53165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53167 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
53169 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadd.b", 32,
53170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53172 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
53174 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadd.b", 32,
53175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53177 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
53179 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadd.b", 32,
53180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53182 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
53184 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadd.b", 40,
53185 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53187 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
53189 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadd.b", 40,
53190 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53192 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
53194 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadd.b", 40,
53195 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53197 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
53199 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadd.b", 48,
53200 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53202 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
53204 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadd.b", 48,
53205 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53207 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
53209 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadd.b", 48,
53210 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53212 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
53214 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadd.b", 32,
53215 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53217 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
53219 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadd.b", 32,
53220 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53222 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
53224 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadd.b", 32,
53225 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53227 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
53229 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadd.b", 40,
53230 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53232 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
53234 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadd.b", 40,
53235 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53237 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
53239 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadd.b", 40,
53240 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53242 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
53244 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadd.b", 32,
53245 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53247 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
53249 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadd.b", 32,
53250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53252 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
53254 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadd.b", 32,
53255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53257 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
53259 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadd.b", 40,
53260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53262 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
53264 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadd.b", 40,
53265 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53267 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
53269 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadd.b", 40,
53270 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53272 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
53274 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadd.b", 40,
53275 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53277 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
53279 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadd.b", 40,
53280 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53282 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
53284 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadd.b", 40,
53285 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53287 /* dadd.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
53289 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadd.b", 48,
53290 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53292 /* dadd.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
53294 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadd.b", 48,
53295 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53297 /* dadd.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
53299 M32C_INSN_DADD32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadd.b", 48,
53300 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53302 /* dadd.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
53304 M32C_INSN_DADD32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "dadd32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "dadd.w", 40,
53305 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53307 /* dadd.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
53309 M32C_INSN_DADD32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "dadd32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "dadd.w", 40,
53310 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53312 /* dadd.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
53314 M32C_INSN_DADD32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "dadd32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "dadd.w", 40,
53315 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53317 /* dadd.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
53319 M32C_INSN_DADD32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "dadd.w", 48,
53320 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53322 /* dadd.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
53324 M32C_INSN_DADD32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "dadd.w", 48,
53325 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53327 /* dadd.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
53329 M32C_INSN_DADD32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "dadd.w", 48,
53330 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53332 /* dadd.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
53334 M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "dadd.w", 56,
53335 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53337 /* dadd.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
53339 M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "dadd.w", 56,
53340 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53342 /* dadd.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
53344 M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "dadd.w", 56,
53345 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53347 /* dadd.w${X} #${Imm-40-HI},${Dsp-24-u16} */
53349 M32C_INSN_DADD32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadd32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "dadd.w", 56,
53350 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53352 /* dadd.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
53354 M32C_INSN_DADD32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadd32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "dadd.w", 64,
53355 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53357 /* dadd.w${X} #${Imm-48-HI},${Dsp-24-u24} */
53359 M32C_INSN_DADD32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadd32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "dadd.w", 64,
53360 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53362 /* dadd.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
53364 M32C_INSN_DADD32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "dadd32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "dadd.b", 32,
53365 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53367 /* dadd.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
53369 M32C_INSN_DADD32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "dadd32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "dadd.b", 32,
53370 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53372 /* dadd.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
53374 M32C_INSN_DADD32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "dadd32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "dadd.b", 32,
53375 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53377 /* dadd.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
53379 M32C_INSN_DADD32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "dadd.b", 40,
53380 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53382 /* dadd.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
53384 M32C_INSN_DADD32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "dadd.b", 40,
53385 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53387 /* dadd.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
53389 M32C_INSN_DADD32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "dadd.b", 40,
53390 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53392 /* dadd.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
53394 M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "dadd.b", 48,
53395 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53397 /* dadd.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
53399 M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "dadd.b", 48,
53400 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53402 /* dadd.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
53404 M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "dadd.b", 48,
53405 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53407 /* dadd.b${X} #${Imm-40-QI},${Dsp-24-u16} */
53409 M32C_INSN_DADD32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadd32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "dadd.b", 48,
53410 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53412 /* dadd.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
53414 M32C_INSN_DADD32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadd32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "dadd.b", 56,
53415 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53417 /* dadd.b${X} #${Imm-48-QI},${Dsp-24-u24} */
53419 M32C_INSN_DADD32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadd32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "dadd.b", 56,
53420 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53422 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
53424 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 32,
53425 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53427 /* dadc.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
53429 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 32,
53430 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53432 /* dadc.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
53434 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 32,
53435 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53437 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
53439 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 32,
53440 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53442 /* dadc.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
53444 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 32,
53445 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53447 /* dadc.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
53449 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 32,
53450 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53452 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
53454 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 32,
53455 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53457 /* dadc.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
53459 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 32,
53460 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53462 /* dadc.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
53464 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 32,
53465 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53467 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
53469 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadc.w", 40,
53470 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53472 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
53474 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadc.w", 40,
53475 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53477 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
53479 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "dadc.w", 40,
53480 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53482 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
53484 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadc.w", 48,
53485 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53487 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
53489 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadc.w", 48,
53490 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53492 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
53494 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "dadc.w", 48,
53495 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53497 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
53499 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadc.w", 56,
53500 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53502 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
53504 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadc.w", 56,
53505 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53507 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
53509 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "dadc.w", 56,
53510 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53512 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
53514 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadc.w", 40,
53515 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53517 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
53519 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadc.w", 40,
53520 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53522 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
53524 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "dadc.w", 40,
53525 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53527 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
53529 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadc.w", 48,
53530 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53532 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
53534 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadc.w", 48,
53535 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53537 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
53539 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "dadc.w", 48,
53540 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53542 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
53544 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadc.w", 40,
53545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53547 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
53549 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadc.w", 40,
53550 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53552 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
53554 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "dadc.w", 40,
53555 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53557 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
53559 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadc.w", 48,
53560 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53562 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
53564 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadc.w", 48,
53565 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53567 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
53569 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "dadc.w", 48,
53570 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53572 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
53574 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadc.w", 48,
53575 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53577 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
53579 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadc.w", 48,
53580 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53582 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
53584 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "dadc.w", 48,
53585 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53587 /* dadc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
53589 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadc.w", 56,
53590 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53592 /* dadc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
53594 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadc.w", 56,
53595 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53597 /* dadc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
53599 M32C_INSN_DADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "dadc.w", 56,
53600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53602 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
53604 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 40,
53605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53607 /* dadc.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
53609 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 40,
53610 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53612 /* dadc.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
53614 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 40,
53615 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53617 /* dadc.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
53619 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 40,
53620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53622 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
53624 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 40,
53625 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53627 /* dadc.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
53629 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 40,
53630 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53632 /* dadc.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
53634 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 40,
53635 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53637 /* dadc.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
53639 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 40,
53640 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53642 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
53644 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 40,
53645 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53647 /* dadc.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
53649 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 40,
53650 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53652 /* dadc.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
53654 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 40,
53655 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53657 /* dadc.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
53659 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 40,
53660 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53662 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
53664 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadc.w", 48,
53665 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53667 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
53669 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadc.w", 48,
53670 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53672 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
53674 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadc.w", 48,
53675 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53677 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
53679 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "dadc.w", 48,
53680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53682 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
53684 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadc.w", 56,
53685 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53687 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
53689 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadc.w", 56,
53690 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53692 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
53694 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadc.w", 56,
53695 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53697 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
53699 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "dadc.w", 56,
53700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53702 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
53704 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadc.w", 64,
53705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53707 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
53709 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadc.w", 64,
53710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53712 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
53714 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadc.w", 64,
53715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53717 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
53719 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "dadc.w", 64,
53720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53722 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
53724 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadc.w", 48,
53725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53727 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
53729 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadc.w", 48,
53730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53732 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
53734 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadc.w", 48,
53735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53737 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
53739 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "dadc.w", 48,
53740 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53742 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
53744 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadc.w", 56,
53745 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53747 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
53749 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadc.w", 56,
53750 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53752 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
53754 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadc.w", 56,
53755 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53757 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
53759 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "dadc.w", 56,
53760 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53762 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
53764 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadc.w", 48,
53765 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53767 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
53769 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadc.w", 48,
53770 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53772 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
53774 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadc.w", 48,
53775 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53777 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
53779 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "dadc.w", 48,
53780 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53782 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
53784 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadc.w", 56,
53785 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53787 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
53789 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadc.w", 56,
53790 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53792 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
53794 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadc.w", 56,
53795 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53797 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
53799 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "dadc.w", 56,
53800 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53802 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
53804 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadc.w", 56,
53805 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53807 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
53809 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadc.w", 56,
53810 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53812 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
53814 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadc.w", 56,
53815 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53817 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
53819 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "dadc.w", 56,
53820 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53822 /* dadc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
53824 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadc.w", 64,
53825 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53827 /* dadc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
53829 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadc.w", 64,
53830 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53832 /* dadc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
53834 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadc.w", 64,
53835 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53837 /* dadc.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
53839 M32C_INSN_DADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "dadc.w", 64,
53840 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53842 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
53844 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 48,
53845 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53847 /* dadc.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
53849 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 48,
53850 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53852 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
53854 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 48,
53855 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53857 /* dadc.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
53859 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 48,
53860 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53862 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
53864 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 48,
53865 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53867 /* dadc.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
53869 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 48,
53870 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53872 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
53874 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dadc.w", 56,
53875 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53877 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
53879 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "dadc.w", 56,
53880 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53882 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
53884 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dadc.w", 64,
53885 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53887 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
53889 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "dadc.w", 64,
53890 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53892 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
53894 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dadc.w", 72,
53895 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53897 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
53899 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "dadc.w", 72,
53900 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53902 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
53904 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dadc.w", 56,
53905 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53907 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
53909 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "dadc.w", 56,
53910 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53912 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
53914 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dadc.w", 64,
53915 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53917 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
53919 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "dadc.w", 64,
53920 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53922 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
53924 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dadc.w", 56,
53925 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53927 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
53929 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "dadc.w", 56,
53930 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53932 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
53934 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dadc.w", 64,
53935 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53937 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
53939 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "dadc.w", 64,
53940 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53942 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
53944 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dadc.w", 64,
53945 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53947 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
53949 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "dadc.w", 64,
53950 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53952 /* dadc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
53954 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dadc.w", 72,
53955 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53957 /* dadc.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
53959 M32C_INSN_DADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "dadc.w", 72,
53960 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53962 /* dadc.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
53964 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 24,
53965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53967 /* dadc.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
53969 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 24,
53970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53972 /* dadc.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
53974 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "dadc.w", 24,
53975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53977 /* dadc.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
53979 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 24,
53980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53982 /* dadc.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
53984 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 24,
53985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53987 /* dadc.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
53989 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "dadc.w", 24,
53990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53992 /* dadc.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
53994 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 24,
53995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
53997 /* dadc.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
53999 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 24,
54000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54002 /* dadc.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
54004 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "dadc.w", 24,
54005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54007 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
54009 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadc.w", 32,
54010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54012 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
54014 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadc.w", 32,
54015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54017 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
54019 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "dadc.w", 32,
54020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54022 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
54024 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadc.w", 40,
54025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54027 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
54029 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadc.w", 40,
54030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54032 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
54034 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "dadc.w", 40,
54035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54037 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
54039 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadc.w", 48,
54040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54042 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
54044 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadc.w", 48,
54045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54047 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
54049 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "dadc.w", 48,
54050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54052 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
54054 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadc.w", 32,
54055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54057 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
54059 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadc.w", 32,
54060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54062 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
54064 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "dadc.w", 32,
54065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54067 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
54069 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadc.w", 40,
54070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54072 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
54074 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadc.w", 40,
54075 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54077 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
54079 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "dadc.w", 40,
54080 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54082 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
54084 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadc.w", 32,
54085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54087 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
54089 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadc.w", 32,
54090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54092 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
54094 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "dadc.w", 32,
54095 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54097 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
54099 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadc.w", 40,
54100 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54102 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
54104 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadc.w", 40,
54105 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54107 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
54109 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "dadc.w", 40,
54110 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54112 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
54114 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadc.w", 40,
54115 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54117 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
54119 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadc.w", 40,
54120 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54122 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
54124 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "dadc.w", 40,
54125 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54127 /* dadc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
54129 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadc.w", 48,
54130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54132 /* dadc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
54134 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadc.w", 48,
54135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54137 /* dadc.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
54139 M32C_INSN_DADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "dadc.w", 48,
54140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54142 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
54144 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 32,
54145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54147 /* dadc.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
54149 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 32,
54150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54152 /* dadc.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
54154 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 32,
54155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54157 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
54159 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 32,
54160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54162 /* dadc.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
54164 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 32,
54165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54167 /* dadc.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
54169 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 32,
54170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54172 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
54174 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 32,
54175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54177 /* dadc.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
54179 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 32,
54180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54182 /* dadc.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
54184 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 32,
54185 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54187 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
54189 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadc.b", 40,
54190 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54192 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
54194 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadc.b", 40,
54195 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54197 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
54199 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "dadc.b", 40,
54200 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54202 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
54204 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadc.b", 48,
54205 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54207 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
54209 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadc.b", 48,
54210 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54212 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
54214 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "dadc.b", 48,
54215 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54217 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
54219 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadc.b", 56,
54220 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54222 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
54224 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadc.b", 56,
54225 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54227 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
54229 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "dadc.b", 56,
54230 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54232 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
54234 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadc.b", 40,
54235 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54237 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
54239 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadc.b", 40,
54240 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54242 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
54244 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "dadc.b", 40,
54245 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54247 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
54249 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadc.b", 48,
54250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54252 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
54254 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadc.b", 48,
54255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54257 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
54259 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "dadc.b", 48,
54260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54262 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
54264 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadc.b", 40,
54265 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54267 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
54269 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadc.b", 40,
54270 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54272 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
54274 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "dadc.b", 40,
54275 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54277 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
54279 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadc.b", 48,
54280 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54282 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
54284 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadc.b", 48,
54285 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54287 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
54289 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "dadc.b", 48,
54290 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54292 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
54294 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadc.b", 48,
54295 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54297 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
54299 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadc.b", 48,
54300 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54302 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
54304 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "dadc.b", 48,
54305 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54307 /* dadc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
54309 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadc.b", 56,
54310 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54312 /* dadc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
54314 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadc.b", 56,
54315 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54317 /* dadc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
54319 M32C_INSN_DADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "dadc.b", 56,
54320 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54322 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
54324 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 40,
54325 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54327 /* dadc.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
54329 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 40,
54330 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54332 /* dadc.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
54334 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 40,
54335 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54337 /* dadc.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
54339 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 40,
54340 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54342 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
54344 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 40,
54345 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54347 /* dadc.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
54349 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 40,
54350 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54352 /* dadc.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
54354 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 40,
54355 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54357 /* dadc.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
54359 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 40,
54360 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54362 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
54364 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 40,
54365 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54367 /* dadc.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
54369 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 40,
54370 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54372 /* dadc.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
54374 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 40,
54375 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54377 /* dadc.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
54379 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 40,
54380 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54382 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
54384 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadc.b", 48,
54385 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54387 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
54389 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadc.b", 48,
54390 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54392 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
54394 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadc.b", 48,
54395 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54397 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
54399 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "dadc.b", 48,
54400 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54402 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
54404 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadc.b", 56,
54405 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54407 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
54409 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadc.b", 56,
54410 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54412 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
54414 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadc.b", 56,
54415 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54417 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
54419 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "dadc.b", 56,
54420 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54422 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
54424 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadc.b", 64,
54425 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54427 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
54429 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadc.b", 64,
54430 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54432 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
54434 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadc.b", 64,
54435 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54437 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
54439 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "dadc.b", 64,
54440 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54442 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
54444 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadc.b", 48,
54445 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54447 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
54449 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadc.b", 48,
54450 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54452 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
54454 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadc.b", 48,
54455 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54457 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
54459 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "dadc.b", 48,
54460 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54462 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
54464 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadc.b", 56,
54465 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54467 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
54469 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadc.b", 56,
54470 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54472 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
54474 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadc.b", 56,
54475 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54477 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
54479 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "dadc.b", 56,
54480 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54482 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
54484 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadc.b", 48,
54485 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54487 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
54489 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadc.b", 48,
54490 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54492 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
54494 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadc.b", 48,
54495 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54497 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
54499 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "dadc.b", 48,
54500 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54502 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
54504 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadc.b", 56,
54505 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54507 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
54509 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadc.b", 56,
54510 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54512 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
54514 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadc.b", 56,
54515 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54517 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
54519 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "dadc.b", 56,
54520 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54522 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
54524 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadc.b", 56,
54525 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54527 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
54529 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadc.b", 56,
54530 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54532 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
54534 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadc.b", 56,
54535 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54537 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
54539 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "dadc.b", 56,
54540 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54542 /* dadc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
54544 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadc.b", 64,
54545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54547 /* dadc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
54549 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadc.b", 64,
54550 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54552 /* dadc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
54554 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadc.b", 64,
54555 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54557 /* dadc.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
54559 M32C_INSN_DADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "dadc.b", 64,
54560 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54562 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
54564 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 48,
54565 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54567 /* dadc.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
54569 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 48,
54570 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54572 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
54574 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 48,
54575 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54577 /* dadc.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
54579 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 48,
54580 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54582 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
54584 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 48,
54585 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54587 /* dadc.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
54589 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 48,
54590 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54592 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
54594 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dadc.b", 56,
54595 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54597 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
54599 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "dadc.b", 56,
54600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54602 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
54604 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dadc.b", 64,
54605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54607 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
54609 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "dadc.b", 64,
54610 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54612 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
54614 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dadc.b", 72,
54615 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54617 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
54619 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "dadc.b", 72,
54620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54622 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
54624 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dadc.b", 56,
54625 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54627 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
54629 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "dadc.b", 56,
54630 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54632 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
54634 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dadc.b", 64,
54635 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54637 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
54639 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "dadc.b", 64,
54640 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54642 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
54644 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dadc.b", 56,
54645 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54647 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
54649 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "dadc.b", 56,
54650 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54652 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
54654 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dadc.b", 64,
54655 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54657 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
54659 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "dadc.b", 64,
54660 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54662 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
54664 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dadc.b", 64,
54665 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54667 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
54669 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "dadc.b", 64,
54670 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54672 /* dadc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
54674 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dadc.b", 72,
54675 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54677 /* dadc.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
54679 M32C_INSN_DADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "dadc.b", 72,
54680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54682 /* dadc.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
54684 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 24,
54685 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54687 /* dadc.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
54689 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 24,
54690 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54692 /* dadc.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
54694 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "dadc.b", 24,
54695 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54697 /* dadc.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
54699 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 24,
54700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54702 /* dadc.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
54704 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 24,
54705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54707 /* dadc.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
54709 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "dadc.b", 24,
54710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54712 /* dadc.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
54714 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 24,
54715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54717 /* dadc.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
54719 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 24,
54720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54722 /* dadc.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
54724 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "dadc.b", 24,
54725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54727 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
54729 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadc.b", 32,
54730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54732 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
54734 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadc.b", 32,
54735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54737 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
54739 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "dadc.b", 32,
54740 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54742 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
54744 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadc.b", 40,
54745 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54747 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
54749 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadc.b", 40,
54750 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54752 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
54754 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "dadc.b", 40,
54755 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54757 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
54759 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadc.b", 48,
54760 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54762 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
54764 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadc.b", 48,
54765 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54767 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
54769 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "dadc.b", 48,
54770 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54772 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
54774 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadc.b", 32,
54775 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54777 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
54779 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadc.b", 32,
54780 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54782 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
54784 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "dadc.b", 32,
54785 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54787 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
54789 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadc.b", 40,
54790 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54792 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
54794 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadc.b", 40,
54795 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54797 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
54799 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "dadc.b", 40,
54800 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54802 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
54804 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadc.b", 32,
54805 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54807 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
54809 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadc.b", 32,
54810 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54812 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
54814 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "dadc.b", 32,
54815 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54817 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
54819 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadc.b", 40,
54820 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54822 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
54824 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadc.b", 40,
54825 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54827 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
54829 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "dadc.b", 40,
54830 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54832 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
54834 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadc.b", 40,
54835 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54837 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
54839 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadc.b", 40,
54840 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54842 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
54844 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "dadc.b", 40,
54845 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54847 /* dadc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
54849 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadc.b", 48,
54850 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54852 /* dadc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
54854 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadc.b", 48,
54855 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54857 /* dadc.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
54859 M32C_INSN_DADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "dadc.b", 48,
54860 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54862 /* dadc.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
54864 M32C_INSN_DADC32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "dadc32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "dadc.w", 40,
54865 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54867 /* dadc.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
54869 M32C_INSN_DADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "dadc32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "dadc.w", 40,
54870 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54872 /* dadc.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
54874 M32C_INSN_DADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "dadc32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "dadc.w", 40,
54875 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54877 /* dadc.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
54879 M32C_INSN_DADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "dadc.w", 48,
54880 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54882 /* dadc.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
54884 M32C_INSN_DADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "dadc.w", 48,
54885 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54887 /* dadc.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
54889 M32C_INSN_DADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "dadc.w", 48,
54890 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54892 /* dadc.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
54894 M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "dadc.w", 56,
54895 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54897 /* dadc.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
54899 M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "dadc.w", 56,
54900 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54902 /* dadc.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
54904 M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "dadc.w", 56,
54905 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54907 /* dadc.w${X} #${Imm-40-HI},${Dsp-24-u16} */
54909 M32C_INSN_DADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "dadc32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "dadc.w", 56,
54910 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54912 /* dadc.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
54914 M32C_INSN_DADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "dadc32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "dadc.w", 64,
54915 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54917 /* dadc.w${X} #${Imm-48-HI},${Dsp-24-u24} */
54919 M32C_INSN_DADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "dadc32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "dadc.w", 64,
54920 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54922 /* dadc.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
54924 M32C_INSN_DADC32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "dadc32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "dadc.b", 32,
54925 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54927 /* dadc.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
54929 M32C_INSN_DADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "dadc32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "dadc.b", 32,
54930 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54932 /* dadc.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
54934 M32C_INSN_DADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "dadc32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "dadc.b", 32,
54935 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54937 /* dadc.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
54939 M32C_INSN_DADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "dadc.b", 40,
54940 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54942 /* dadc.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
54944 M32C_INSN_DADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "dadc.b", 40,
54945 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54947 /* dadc.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
54949 M32C_INSN_DADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "dadc.b", 40,
54950 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54952 /* dadc.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
54954 M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "dadc.b", 48,
54955 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54957 /* dadc.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
54959 M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "dadc.b", 48,
54960 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54962 /* dadc.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
54964 M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "dadc.b", 48,
54965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54967 /* dadc.b${X} #${Imm-40-QI},${Dsp-24-u16} */
54969 M32C_INSN_DADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "dadc32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "dadc.b", 48,
54970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54972 /* dadc.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
54974 M32C_INSN_DADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "dadc32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "dadc.b", 56,
54975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54977 /* dadc.b${X} #${Imm-48-QI},${Dsp-24-u24} */
54979 M32C_INSN_DADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "dadc32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "dadc.b", 56,
54980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54982 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
54984 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 32,
54985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54987 /* adc.w${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedHI */
54989 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 32,
54990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54992 /* adc.w${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedHI */
54994 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 32,
54995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
54997 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
54999 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 32,
55000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55002 /* adc.w${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedHI */
55004 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 32,
55005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55007 /* adc.w${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedHI */
55009 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 32,
55010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55012 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
55014 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 32,
55015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55017 /* adc.w${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
55019 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 32,
55020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55022 /* adc.w${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
55024 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 32,
55025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55027 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
55029 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "adc.w", 40,
55030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55032 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
55034 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "adc.w", 40,
55035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55037 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
55039 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-An-relative-Prefixed-HI", "adc.w", 40,
55040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55042 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
55044 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "adc.w", 48,
55045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55047 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
55049 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "adc.w", 48,
55050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55052 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
55054 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-An-relative-Prefixed-HI", "adc.w", 48,
55055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55057 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
55059 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "adc.w", 56,
55060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55062 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
55064 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "adc.w", 56,
55065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55067 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
55069 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-An-relative-Prefixed-HI", "adc.w", 56,
55070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55072 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
55074 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "adc.w", 40,
55075 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55077 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
55079 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "adc.w", 40,
55080 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55082 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
55084 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-SB-relative-Prefixed-HI", "adc.w", 40,
55085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55087 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
55089 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "adc.w", 48,
55090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55092 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
55094 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "adc.w", 48,
55095 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55097 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
55099 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-SB-relative-Prefixed-HI", "adc.w", 48,
55100 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55102 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
55104 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "adc.w", 40,
55105 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55107 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
55109 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "adc.w", 40,
55110 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55112 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
55114 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-8-FB-relative-Prefixed-HI", "adc.w", 40,
55115 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55117 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
55119 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "adc.w", 48,
55120 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55122 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
55124 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "adc.w", 48,
55125 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55127 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
55129 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-FB-relative-Prefixed-HI", "adc.w", 48,
55130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55132 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
55134 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "adc.w", 48,
55135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55137 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
55139 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "adc.w", 48,
55140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55142 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
55144 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-16-absolute-Prefixed-HI", "adc.w", 48,
55145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55147 /* adc.w${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
55149 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "adc.w", 56,
55150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55152 /* adc.w${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
55154 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "adc.w", 56,
55155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55157 /* adc.w${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
55159 M32C_INSN_ADC32_W_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_HI_DST32_32_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-HI-dst32-32-24-absolute-Prefixed-HI", "adc.w", 56,
55160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55162 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
55164 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 40,
55165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55167 /* adc.w${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedHI */
55169 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 40,
55170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55172 /* adc.w${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedHI */
55174 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 40,
55175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55177 /* adc.w${X} ${Dsp-24-u16},$Dst32RnPrefixedHI */
55179 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 40,
55180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55182 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
55184 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 40,
55185 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55187 /* adc.w${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedHI */
55189 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 40,
55190 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55192 /* adc.w${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedHI */
55194 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 40,
55195 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55197 /* adc.w${X} ${Dsp-24-u16},$Dst32AnPrefixedHI */
55199 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 40,
55200 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55202 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
55204 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 40,
55205 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55207 /* adc.w${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
55209 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 40,
55210 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55212 /* adc.w${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
55214 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 40,
55215 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55217 /* adc.w${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
55219 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 40,
55220 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55222 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
55224 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "adc.w", 48,
55225 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55227 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
55229 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "adc.w", 48,
55230 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55232 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
55234 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "adc.w", 48,
55235 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55237 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
55239 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-An-relative-Prefixed-HI", "adc.w", 48,
55240 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55242 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
55244 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "adc.w", 56,
55245 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55247 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
55249 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "adc.w", 56,
55250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55252 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
55254 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "adc.w", 56,
55255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55257 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
55259 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-An-relative-Prefixed-HI", "adc.w", 56,
55260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55262 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
55264 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "adc.w", 64,
55265 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55267 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
55269 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "adc.w", 64,
55270 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55272 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
55274 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "adc.w", 64,
55275 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55277 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
55279 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-An-relative-Prefixed-HI", "adc.w", 64,
55280 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55282 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
55284 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "adc.w", 48,
55285 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55287 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
55289 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "adc.w", 48,
55290 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55292 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
55294 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "adc.w", 48,
55295 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55297 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
55299 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-SB-relative-Prefixed-HI", "adc.w", 48,
55300 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55302 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
55304 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "adc.w", 56,
55305 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55307 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
55309 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "adc.w", 56,
55310 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55312 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
55314 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "adc.w", 56,
55315 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55317 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
55319 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-SB-relative-Prefixed-HI", "adc.w", 56,
55320 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55322 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
55324 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "adc.w", 48,
55325 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55327 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
55329 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "adc.w", 48,
55330 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55332 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
55334 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "adc.w", 48,
55335 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55337 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
55339 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-8-FB-relative-Prefixed-HI", "adc.w", 48,
55340 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55342 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
55344 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "adc.w", 56,
55345 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55347 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
55349 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "adc.w", 56,
55350 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55352 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
55354 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "adc.w", 56,
55355 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55357 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
55359 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-FB-relative-Prefixed-HI", "adc.w", 56,
55360 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55362 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
55364 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "adc.w", 56,
55365 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55367 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
55369 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "adc.w", 56,
55370 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55372 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
55374 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "adc.w", 56,
55375 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55377 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-u16} */
55379 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-16-absolute-Prefixed-HI", "adc.w", 56,
55380 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55382 /* adc.w${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
55384 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "adc.w", 64,
55385 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55387 /* adc.w${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
55389 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "adc.w", 64,
55390 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55392 /* adc.w${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
55394 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "adc.w", 64,
55395 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55397 /* adc.w${X} ${Dsp-24-u16},${Dsp-40-u24} */
55399 M32C_INSN_ADC32_W_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_HI_DST32_40_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-HI-dst32-40-24-absolute-Prefixed-HI", "adc.w", 64,
55400 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55402 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedHI */
55404 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 48,
55405 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55407 /* adc.w${X} ${Dsp-24-u24},$Dst32RnPrefixedHI */
55409 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 48,
55410 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55412 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedHI */
55414 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 48,
55415 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55417 /* adc.w${X} ${Dsp-24-u24},$Dst32AnPrefixedHI */
55419 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 48,
55420 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55422 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
55424 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 48,
55425 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55427 /* adc.w${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
55429 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 48,
55430 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55432 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
55434 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "adc.w", 56,
55435 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55437 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
55439 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-An-relative-Prefixed-HI", "adc.w", 56,
55440 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55442 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
55444 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "adc.w", 64,
55445 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55447 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
55449 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-An-relative-Prefixed-HI", "adc.w", 64,
55450 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55452 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
55454 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "adc.w", 72,
55455 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55457 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
55459 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-An-relative-Prefixed-HI", "adc.w", 72,
55460 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55462 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
55464 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "adc.w", 56,
55465 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55467 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
55469 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-SB-relative-Prefixed-HI", "adc.w", 56,
55470 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55472 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
55474 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "adc.w", 64,
55475 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55477 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
55479 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-SB-relative-Prefixed-HI", "adc.w", 64,
55480 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55482 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
55484 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "adc.w", 56,
55485 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55487 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
55489 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-8-FB-relative-Prefixed-HI", "adc.w", 56,
55490 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55492 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
55494 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "adc.w", 64,
55495 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55497 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
55499 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-FB-relative-Prefixed-HI", "adc.w", 64,
55500 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55502 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
55504 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "adc.w", 64,
55505 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55507 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-u16} */
55509 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_16_ABSOLUTE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-16-absolute-Prefixed-HI", "adc.w", 64,
55510 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55512 /* adc.w${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
55514 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "adc.w", 72,
55515 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55517 /* adc.w${X} ${Dsp-24-u24},${Dsp-48-u24} */
55519 M32C_INSN_ADC32_W_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_HI_DST32_48_24_ABSOLUTE_PREFIXED_HI, "adc32.w-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-HI-dst32-48-24-absolute-Prefixed-HI", "adc.w", 72,
55520 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55522 /* adc.w${X} $Src32RnPrefixedHI,$Dst32RnPrefixedHI */
55524 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 24,
55525 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55527 /* adc.w${X} $Src32AnPrefixedHI,$Dst32RnPrefixedHI */
55529 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 24,
55530 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55532 /* adc.w${X} [$Src32AnPrefixed],$Dst32RnPrefixedHI */
55534 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-Rn-direct-Prefixed-HI", "adc.w", 24,
55535 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55537 /* adc.w${X} $Src32RnPrefixedHI,$Dst32AnPrefixedHI */
55539 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 24,
55540 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55542 /* adc.w${X} $Src32AnPrefixedHI,$Dst32AnPrefixedHI */
55544 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 24,
55545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55547 /* adc.w${X} [$Src32AnPrefixed],$Dst32AnPrefixedHI */
55549 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-direct-Prefixed-HI", "adc.w", 24,
55550 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55552 /* adc.w${X} $Src32RnPrefixedHI,[$Dst32AnPrefixed] */
55554 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 24,
55555 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55557 /* adc.w${X} $Src32AnPrefixedHI,[$Dst32AnPrefixed] */
55559 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 24,
55560 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55562 /* adc.w${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
55564 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-An-indirect-Prefixed-HI", "adc.w", 24,
55565 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55567 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
55569 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "adc.w", 32,
55570 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55572 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[$Dst32AnPrefixed] */
55574 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "adc.w", 32,
55575 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55577 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
55579 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-An-relative-Prefixed-HI", "adc.w", 32,
55580 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55582 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
55584 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "adc.w", 40,
55585 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55587 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[$Dst32AnPrefixed] */
55589 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "adc.w", 40,
55590 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55592 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
55594 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-An-relative-Prefixed-HI", "adc.w", 40,
55595 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55597 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
55599 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "adc.w", 48,
55600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55602 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24}[$Dst32AnPrefixed] */
55604 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "adc.w", 48,
55605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55607 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
55609 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-An-relative-Prefixed-HI", "adc.w", 48,
55610 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55612 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u8}[sb] */
55614 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "adc.w", 32,
55615 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55617 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u8}[sb] */
55619 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "adc.w", 32,
55620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55622 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
55624 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-SB-relative-Prefixed-HI", "adc.w", 32,
55625 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55627 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16}[sb] */
55629 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "adc.w", 40,
55630 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55632 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16}[sb] */
55634 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "adc.w", 40,
55635 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55637 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
55639 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-SB-relative-Prefixed-HI", "adc.w", 40,
55640 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55642 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-s8}[fb] */
55644 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "adc.w", 32,
55645 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55647 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-s8}[fb] */
55649 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "adc.w", 32,
55650 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55652 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
55654 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-8-FB-relative-Prefixed-HI", "adc.w", 32,
55655 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55657 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-s16}[fb] */
55659 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "adc.w", 40,
55660 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55662 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-s16}[fb] */
55664 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "adc.w", 40,
55665 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55667 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
55669 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-FB-relative-Prefixed-HI", "adc.w", 40,
55670 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55672 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u16} */
55674 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "adc.w", 40,
55675 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55677 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u16} */
55679 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "adc.w", 40,
55680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55682 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u16} */
55684 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_16_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-16-absolute-Prefixed-HI", "adc.w", 40,
55685 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55687 /* adc.w${X} $Src32RnPrefixedHI,${Dsp-24-u24} */
55689 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "adc.w", 48,
55690 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55692 /* adc.w${X} $Src32AnPrefixedHI,${Dsp-24-u24} */
55694 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "adc.w", 48,
55695 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55697 /* adc.w${X} [$Src32AnPrefixed],${Dsp-24-u24} */
55699 M32C_INSN_ADC32_W_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_HI_DST32_24_24_ABSOLUTE_PREFIXED_HI, "adc32.w-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-HI-dst32-24-24-absolute-Prefixed-HI", "adc.w", 48,
55700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55702 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
55704 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 32,
55705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55707 /* adc.b${X} ${Dsp-24-u8}[sb],$Dst32RnPrefixedQI */
55709 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 32,
55710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55712 /* adc.b${X} ${Dsp-24-s8}[fb],$Dst32RnPrefixedQI */
55714 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 32,
55715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55717 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
55719 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 32,
55720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55722 /* adc.b${X} ${Dsp-24-u8}[sb],$Dst32AnPrefixedQI */
55724 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 32,
55725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55727 /* adc.b${X} ${Dsp-24-s8}[fb],$Dst32AnPrefixedQI */
55729 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 32,
55730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55732 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
55734 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 32,
55735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55737 /* adc.b${X} ${Dsp-24-u8}[sb],[$Dst32AnPrefixed] */
55739 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 32,
55740 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55742 /* adc.b${X} ${Dsp-24-s8}[fb],[$Dst32AnPrefixed] */
55744 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 32,
55745 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55747 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[$Dst32AnPrefixed] */
55749 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "adc.b", 40,
55750 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55752 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[$Dst32AnPrefixed] */
55754 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "adc.b", 40,
55755 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55757 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[$Dst32AnPrefixed] */
55759 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-An-relative-Prefixed-QI", "adc.b", 40,
55760 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55762 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[$Dst32AnPrefixed] */
55764 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "adc.b", 48,
55765 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55767 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[$Dst32AnPrefixed] */
55769 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "adc.b", 48,
55770 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55772 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[$Dst32AnPrefixed] */
55774 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-An-relative-Prefixed-QI", "adc.b", 48,
55775 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55777 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24}[$Dst32AnPrefixed] */
55779 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "adc.b", 56,
55780 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55782 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24}[$Dst32AnPrefixed] */
55784 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "adc.b", 56,
55785 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55787 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24}[$Dst32AnPrefixed] */
55789 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-An-relative-Prefixed-QI", "adc.b", 56,
55790 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55792 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u8}[sb] */
55794 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "adc.b", 40,
55795 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55797 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u8}[sb] */
55799 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "adc.b", 40,
55800 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55802 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u8}[sb] */
55804 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-SB-relative-Prefixed-QI", "adc.b", 40,
55805 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55807 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16}[sb] */
55809 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "adc.b", 48,
55810 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55812 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16}[sb] */
55814 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "adc.b", 48,
55815 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55817 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16}[sb] */
55819 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-SB-relative-Prefixed-QI", "adc.b", 48,
55820 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55822 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s8}[fb] */
55824 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "adc.b", 40,
55825 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55827 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s8}[fb] */
55829 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "adc.b", 40,
55830 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55832 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s8}[fb] */
55834 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-8-FB-relative-Prefixed-QI", "adc.b", 40,
55835 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55837 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-s16}[fb] */
55839 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "adc.b", 48,
55840 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55842 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-s16}[fb] */
55844 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "adc.b", 48,
55845 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55847 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-s16}[fb] */
55849 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-FB-relative-Prefixed-QI", "adc.b", 48,
55850 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55852 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u16} */
55854 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "adc.b", 48,
55855 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55857 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u16} */
55859 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "adc.b", 48,
55860 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55862 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u16} */
55864 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-16-absolute-Prefixed-QI", "adc.b", 48,
55865 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55867 /* adc.b${X} ${Dsp-24-u8}[$Src32AnPrefixed],${Dsp-32-u24} */
55869 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_AN_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-An-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "adc.b", 56,
55870 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55872 /* adc.b${X} ${Dsp-24-u8}[sb],${Dsp-32-u24} */
55874 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_SB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-SB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "adc.b", 56,
55875 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55877 /* adc.b${X} ${Dsp-24-s8}[fb],${Dsp-32-u24} */
55879 M32C_INSN_ADC32_B_24_8_PREFIXED_32_PREFIXED_SRC32_24_8_FB_RELATIVE_PREFIXED_QI_DST32_32_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-8-Prefixed-32-Prefixed-src32-24-8-FB-relative-Prefixed-QI-dst32-32-24-absolute-Prefixed-QI", "adc.b", 56,
55880 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55882 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
55884 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 40,
55885 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55887 /* adc.b${X} ${Dsp-24-u16}[sb],$Dst32RnPrefixedQI */
55889 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 40,
55890 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55892 /* adc.b${X} ${Dsp-24-s16}[fb],$Dst32RnPrefixedQI */
55894 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 40,
55895 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55897 /* adc.b${X} ${Dsp-24-u16},$Dst32RnPrefixedQI */
55899 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 40,
55900 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55902 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
55904 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 40,
55905 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55907 /* adc.b${X} ${Dsp-24-u16}[sb],$Dst32AnPrefixedQI */
55909 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 40,
55910 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55912 /* adc.b${X} ${Dsp-24-s16}[fb],$Dst32AnPrefixedQI */
55914 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 40,
55915 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55917 /* adc.b${X} ${Dsp-24-u16},$Dst32AnPrefixedQI */
55919 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 40,
55920 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55922 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
55924 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 40,
55925 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55927 /* adc.b${X} ${Dsp-24-u16}[sb],[$Dst32AnPrefixed] */
55929 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 40,
55930 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55932 /* adc.b${X} ${Dsp-24-s16}[fb],[$Dst32AnPrefixed] */
55934 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 40,
55935 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55937 /* adc.b${X} ${Dsp-24-u16},[$Dst32AnPrefixed] */
55939 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 40,
55940 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55942 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[$Dst32AnPrefixed] */
55944 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "adc.b", 48,
55945 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55947 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[$Dst32AnPrefixed] */
55949 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "adc.b", 48,
55950 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55952 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[$Dst32AnPrefixed] */
55954 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "adc.b", 48,
55955 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55957 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[$Dst32AnPrefixed] */
55959 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-An-relative-Prefixed-QI", "adc.b", 48,
55960 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55962 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[$Dst32AnPrefixed] */
55964 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "adc.b", 56,
55965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55967 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[$Dst32AnPrefixed] */
55969 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "adc.b", 56,
55970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55972 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[$Dst32AnPrefixed] */
55974 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "adc.b", 56,
55975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55977 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[$Dst32AnPrefixed] */
55979 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-An-relative-Prefixed-QI", "adc.b", 56,
55980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55982 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24}[$Dst32AnPrefixed] */
55984 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "adc.b", 64,
55985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55987 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24}[$Dst32AnPrefixed] */
55989 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "adc.b", 64,
55990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55992 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24}[$Dst32AnPrefixed] */
55994 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "adc.b", 64,
55995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
55997 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-u24}[$Dst32AnPrefixed] */
55999 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-An-relative-Prefixed-QI", "adc.b", 64,
56000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56002 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u8}[sb] */
56004 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "adc.b", 48,
56005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56007 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u8}[sb] */
56009 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "adc.b", 48,
56010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56012 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u8}[sb] */
56014 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "adc.b", 48,
56015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56017 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-u8}[sb] */
56019 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-SB-relative-Prefixed-QI", "adc.b", 48,
56020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56022 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16}[sb] */
56024 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "adc.b", 56,
56025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56027 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16}[sb] */
56029 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "adc.b", 56,
56030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56032 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16}[sb] */
56034 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "adc.b", 56,
56035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56037 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-u16}[sb] */
56039 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-SB-relative-Prefixed-QI", "adc.b", 56,
56040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56042 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s8}[fb] */
56044 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "adc.b", 48,
56045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56047 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s8}[fb] */
56049 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "adc.b", 48,
56050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56052 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s8}[fb] */
56054 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "adc.b", 48,
56055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56057 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-s8}[fb] */
56059 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-8-FB-relative-Prefixed-QI", "adc.b", 48,
56060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56062 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-s16}[fb] */
56064 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "adc.b", 56,
56065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56067 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-s16}[fb] */
56069 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "adc.b", 56,
56070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56072 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-s16}[fb] */
56074 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "adc.b", 56,
56075 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56077 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-s16}[fb] */
56079 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-FB-relative-Prefixed-QI", "adc.b", 56,
56080 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56082 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u16} */
56084 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "adc.b", 56,
56085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56087 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u16} */
56089 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "adc.b", 56,
56090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56092 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u16} */
56094 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "adc.b", 56,
56095 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56097 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-u16} */
56099 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-16-absolute-Prefixed-QI", "adc.b", 56,
56100 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56102 /* adc.b${X} ${Dsp-24-u16}[$Src32AnPrefixed],${Dsp-40-u24} */
56104 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_AN_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-An-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "adc.b", 64,
56105 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56107 /* adc.b${X} ${Dsp-24-u16}[sb],${Dsp-40-u24} */
56109 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_SB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-SB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "adc.b", 64,
56110 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56112 /* adc.b${X} ${Dsp-24-s16}[fb],${Dsp-40-u24} */
56114 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_FB_RELATIVE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-FB-relative-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "adc.b", 64,
56115 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56117 /* adc.b${X} ${Dsp-24-u16},${Dsp-40-u24} */
56119 M32C_INSN_ADC32_B_24_16_PREFIXED_40_PREFIXED_SRC32_24_16_ABSOLUTE_PREFIXED_QI_DST32_40_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-16-Prefixed-40-Prefixed-src32-24-16-absolute-Prefixed-QI-dst32-40-24-absolute-Prefixed-QI", "adc.b", 64,
56120 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56122 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32RnPrefixedQI */
56124 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 48,
56125 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56127 /* adc.b${X} ${Dsp-24-u24},$Dst32RnPrefixedQI */
56129 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 48,
56130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56132 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],$Dst32AnPrefixedQI */
56134 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 48,
56135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56137 /* adc.b${X} ${Dsp-24-u24},$Dst32AnPrefixedQI */
56139 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 48,
56140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56142 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],[$Dst32AnPrefixed] */
56144 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 48,
56145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56147 /* adc.b${X} ${Dsp-24-u24},[$Dst32AnPrefixed] */
56149 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 48,
56150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56152 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[$Dst32AnPrefixed] */
56154 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "adc.b", 56,
56155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56157 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[$Dst32AnPrefixed] */
56159 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-An-relative-Prefixed-QI", "adc.b", 56,
56160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56162 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[$Dst32AnPrefixed] */
56164 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "adc.b", 64,
56165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56167 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[$Dst32AnPrefixed] */
56169 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-An-relative-Prefixed-QI", "adc.b", 64,
56170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56172 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24}[$Dst32AnPrefixed] */
56174 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "adc.b", 72,
56175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56177 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-u24}[$Dst32AnPrefixed] */
56179 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-An-relative-Prefixed-QI", "adc.b", 72,
56180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56182 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u8}[sb] */
56184 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "adc.b", 56,
56185 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56187 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-u8}[sb] */
56189 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-SB-relative-Prefixed-QI", "adc.b", 56,
56190 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56192 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16}[sb] */
56194 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "adc.b", 64,
56195 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56197 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-u16}[sb] */
56199 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-SB-relative-Prefixed-QI", "adc.b", 64,
56200 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56202 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s8}[fb] */
56204 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "adc.b", 56,
56205 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56207 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-s8}[fb] */
56209 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-8-FB-relative-Prefixed-QI", "adc.b", 56,
56210 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56212 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-s16}[fb] */
56214 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "adc.b", 64,
56215 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56217 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-s16}[fb] */
56219 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-FB-relative-Prefixed-QI", "adc.b", 64,
56220 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56222 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u16} */
56224 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "adc.b", 64,
56225 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56227 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-u16} */
56229 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_16_ABSOLUTE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-16-absolute-Prefixed-QI", "adc.b", 64,
56230 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56232 /* adc.b${X} ${Dsp-24-u24}[$Src32AnPrefixed],${Dsp-48-u24} */
56234 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_AN_RELATIVE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-An-relative-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "adc.b", 72,
56235 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56237 /* adc.b${X} ${Dsp-24-u24},${Dsp-48-u24} */
56239 M32C_INSN_ADC32_B_24_24_PREFIXED_48_PREFIXED_SRC32_24_24_ABSOLUTE_PREFIXED_QI_DST32_48_24_ABSOLUTE_PREFIXED_QI, "adc32.b-24-24-Prefixed-48-Prefixed-src32-24-24-absolute-Prefixed-QI-dst32-48-24-absolute-Prefixed-QI", "adc.b", 72,
56240 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56242 /* adc.b${X} $Src32RnPrefixedQI,$Dst32RnPrefixedQI */
56244 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 24,
56245 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56247 /* adc.b${X} $Src32AnPrefixedQI,$Dst32RnPrefixedQI */
56249 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 24,
56250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56252 /* adc.b${X} [$Src32AnPrefixed],$Dst32RnPrefixedQI */
56254 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-Rn-direct-Prefixed-QI", "adc.b", 24,
56255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56257 /* adc.b${X} $Src32RnPrefixedQI,$Dst32AnPrefixedQI */
56259 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 24,
56260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56262 /* adc.b${X} $Src32AnPrefixedQI,$Dst32AnPrefixedQI */
56264 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 24,
56265 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56267 /* adc.b${X} [$Src32AnPrefixed],$Dst32AnPrefixedQI */
56269 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-direct-Prefixed-QI", "adc.b", 24,
56270 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56272 /* adc.b${X} $Src32RnPrefixedQI,[$Dst32AnPrefixed] */
56274 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 24,
56275 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56277 /* adc.b${X} $Src32AnPrefixedQI,[$Dst32AnPrefixed] */
56279 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 24,
56280 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56282 /* adc.b${X} [$Src32AnPrefixed],[$Dst32AnPrefixed] */
56284 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-An-indirect-Prefixed-QI", "adc.b", 24,
56285 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56287 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
56289 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "adc.b", 32,
56290 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56292 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[$Dst32AnPrefixed] */
56294 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "adc.b", 32,
56295 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56297 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[$Dst32AnPrefixed] */
56299 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-An-relative-Prefixed-QI", "adc.b", 32,
56300 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56302 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
56304 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "adc.b", 40,
56305 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56307 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[$Dst32AnPrefixed] */
56309 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "adc.b", 40,
56310 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56312 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[$Dst32AnPrefixed] */
56314 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-An-relative-Prefixed-QI", "adc.b", 40,
56315 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56317 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
56319 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "adc.b", 48,
56320 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56322 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24}[$Dst32AnPrefixed] */
56324 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "adc.b", 48,
56325 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56327 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u24}[$Dst32AnPrefixed] */
56329 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-An-relative-Prefixed-QI", "adc.b", 48,
56330 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56332 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u8}[sb] */
56334 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "adc.b", 32,
56335 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56337 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u8}[sb] */
56339 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "adc.b", 32,
56340 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56342 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u8}[sb] */
56344 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-SB-relative-Prefixed-QI", "adc.b", 32,
56345 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56347 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16}[sb] */
56349 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "adc.b", 40,
56350 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56352 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16}[sb] */
56354 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "adc.b", 40,
56355 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56357 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u16}[sb] */
56359 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-SB-relative-Prefixed-QI", "adc.b", 40,
56360 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56362 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-s8}[fb] */
56364 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "adc.b", 32,
56365 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56367 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-s8}[fb] */
56369 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "adc.b", 32,
56370 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56372 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-s8}[fb] */
56374 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-8-FB-relative-Prefixed-QI", "adc.b", 32,
56375 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56377 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-s16}[fb] */
56379 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "adc.b", 40,
56380 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56382 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-s16}[fb] */
56384 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "adc.b", 40,
56385 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56387 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-s16}[fb] */
56389 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-FB-relative-Prefixed-QI", "adc.b", 40,
56390 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56392 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u16} */
56394 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "adc.b", 40,
56395 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56397 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u16} */
56399 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "adc.b", 40,
56400 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56402 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u16} */
56404 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_16_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-16-absolute-Prefixed-QI", "adc.b", 40,
56405 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56407 /* adc.b${X} $Src32RnPrefixedQI,${Dsp-24-u24} */
56409 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_RN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-Rn-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "adc.b", 48,
56410 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56412 /* adc.b${X} $Src32AnPrefixedQI,${Dsp-24-u24} */
56414 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_DIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-direct-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "adc.b", 48,
56415 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56417 /* adc.b${X} [$Src32AnPrefixed],${Dsp-24-u24} */
56419 M32C_INSN_ADC32_B_BASIC_PREFIXED_24_PREFIXED_SRC32_AN_INDIRECT_PREFIXED_QI_DST32_24_24_ABSOLUTE_PREFIXED_QI, "adc32.b-basic-Prefixed-24-Prefixed-src32-An-indirect-Prefixed-QI-dst32-24-24-absolute-Prefixed-QI", "adc.b", 48,
56420 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
56422 /* adc.w${X} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
56424 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "adc.w", 24,
56425 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56427 /* adc.w${X} ${Dsp-16-u8}[sb],$Dst16RnHI */
56429 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "adc.w", 24,
56430 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56432 /* adc.w${X} ${Dsp-16-s8}[fb],$Dst16RnHI */
56434 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "adc.w", 24,
56435 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56437 /* adc.w${X} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
56439 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "adc.w", 24,
56440 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56442 /* adc.w${X} ${Dsp-16-u8}[sb],$Dst16AnHI */
56444 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "adc.w", 24,
56445 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56447 /* adc.w${X} ${Dsp-16-s8}[fb],$Dst16AnHI */
56449 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "adc.w", 24,
56450 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56452 /* adc.w${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
56454 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "adc.w", 24,
56455 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56457 /* adc.w${X} ${Dsp-16-u8}[sb],[$Dst16An] */
56459 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "adc.w", 24,
56460 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56462 /* adc.w${X} ${Dsp-16-s8}[fb],[$Dst16An] */
56464 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "adc.w", 24,
56465 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56467 /* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
56469 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "adc.w", 32,
56470 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56472 /* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
56474 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "adc.w", 32,
56475 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56477 /* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
56479 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "adc.w", 32,
56480 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56482 /* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
56484 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "adc.w", 40,
56485 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56487 /* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
56489 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "adc.w", 40,
56490 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56492 /* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
56494 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "adc.w", 40,
56495 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56497 /* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
56499 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "adc.w", 32,
56500 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56502 /* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
56504 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "adc.w", 32,
56505 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56507 /* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
56509 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "adc.w", 32,
56510 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56512 /* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
56514 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "adc.w", 40,
56515 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56517 /* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
56519 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "adc.w", 40,
56520 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56522 /* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
56524 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "adc.w", 40,
56525 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56527 /* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
56529 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "adc.w", 32,
56530 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56532 /* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
56534 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "adc.w", 32,
56535 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56537 /* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
56539 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "adc.w", 32,
56540 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56542 /* adc.w${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
56544 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "adc16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "adc.w", 40,
56545 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56547 /* adc.w${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
56549 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "adc16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "adc.w", 40,
56550 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56552 /* adc.w${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
56554 M32C_INSN_ADC16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "adc16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "adc.w", 40,
56555 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56557 /* adc.w${X} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
56559 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "adc.w", 32,
56560 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56562 /* adc.w${X} ${Dsp-16-u16}[sb],$Dst16RnHI */
56564 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "adc.w", 32,
56565 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56567 /* adc.w${X} ${Dsp-16-u16},$Dst16RnHI */
56569 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "adc.w", 32,
56570 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56572 /* adc.w${X} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
56574 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "adc.w", 32,
56575 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56577 /* adc.w${X} ${Dsp-16-u16}[sb],$Dst16AnHI */
56579 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "adc.w", 32,
56580 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56582 /* adc.w${X} ${Dsp-16-u16},$Dst16AnHI */
56584 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "adc.w", 32,
56585 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56587 /* adc.w${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
56589 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "adc.w", 32,
56590 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56592 /* adc.w${X} ${Dsp-16-u16}[sb],[$Dst16An] */
56594 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "adc.w", 32,
56595 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56597 /* adc.w${X} ${Dsp-16-u16},[$Dst16An] */
56599 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "adc.w", 32,
56600 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56602 /* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
56604 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "adc.w", 40,
56605 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56607 /* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
56609 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "adc.w", 40,
56610 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56612 /* adc.w${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
56614 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "adc.w", 40,
56615 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56617 /* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
56619 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "adc.w", 48,
56620 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56622 /* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
56624 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "adc.w", 48,
56625 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56627 /* adc.w${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
56629 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "adc.w", 48,
56630 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56632 /* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
56634 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "adc.w", 40,
56635 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56637 /* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
56639 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "adc.w", 40,
56640 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56642 /* adc.w${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
56644 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "adc.w", 40,
56645 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56647 /* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
56649 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "adc.w", 48,
56650 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56652 /* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
56654 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "adc.w", 48,
56655 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56657 /* adc.w${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
56659 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "adc.w", 48,
56660 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56662 /* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
56664 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "adc.w", 40,
56665 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56667 /* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
56669 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "adc.w", 40,
56670 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56672 /* adc.w${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
56674 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "adc.w", 40,
56675 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56677 /* adc.w${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
56679 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "adc16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "adc.w", 48,
56680 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56682 /* adc.w${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
56684 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "adc16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "adc.w", 48,
56685 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56687 /* adc.w${X} ${Dsp-16-u16},${Dsp-32-u16} */
56689 M32C_INSN_ADC16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "adc16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "adc.w", 48,
56690 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56692 /* adc.w${X} $Src16RnHI,$Dst16RnHI */
56694 M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "adc.w", 16,
56695 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56697 /* adc.w${X} $Src16AnHI,$Dst16RnHI */
56699 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "adc.w", 16,
56700 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56702 /* adc.w${X} [$Src16An],$Dst16RnHI */
56704 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "adc.w", 16,
56705 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56707 /* adc.w${X} $Src16RnHI,$Dst16AnHI */
56709 M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "adc.w", 16,
56710 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56712 /* adc.w${X} $Src16AnHI,$Dst16AnHI */
56714 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "adc.w", 16,
56715 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56717 /* adc.w${X} [$Src16An],$Dst16AnHI */
56719 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "adc.w", 16,
56720 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56722 /* adc.w${X} $Src16RnHI,[$Dst16An] */
56724 M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "adc.w", 16,
56725 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56727 /* adc.w${X} $Src16AnHI,[$Dst16An] */
56729 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "adc.w", 16,
56730 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56732 /* adc.w${X} [$Src16An],[$Dst16An] */
56734 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "adc.w", 16,
56735 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56737 /* adc.w${X} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
56739 M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "adc.w", 24,
56740 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56742 /* adc.w${X} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
56744 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "adc.w", 24,
56745 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56747 /* adc.w${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
56749 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "adc.w", 24,
56750 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56752 /* adc.w${X} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
56754 M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "adc.w", 32,
56755 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56757 /* adc.w${X} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
56759 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "adc.w", 32,
56760 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56762 /* adc.w${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
56764 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "adc.w", 32,
56765 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56767 /* adc.w${X} $Src16RnHI,${Dsp-16-u8}[sb] */
56769 M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "adc.w", 24,
56770 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56772 /* adc.w${X} $Src16AnHI,${Dsp-16-u8}[sb] */
56774 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "adc.w", 24,
56775 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56777 /* adc.w${X} [$Src16An],${Dsp-16-u8}[sb] */
56779 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "adc.w", 24,
56780 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56782 /* adc.w${X} $Src16RnHI,${Dsp-16-u16}[sb] */
56784 M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "adc.w", 32,
56785 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56787 /* adc.w${X} $Src16AnHI,${Dsp-16-u16}[sb] */
56789 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "adc.w", 32,
56790 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56792 /* adc.w${X} [$Src16An],${Dsp-16-u16}[sb] */
56794 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "adc.w", 32,
56795 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56797 /* adc.w${X} $Src16RnHI,${Dsp-16-s8}[fb] */
56799 M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "adc.w", 24,
56800 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56802 /* adc.w${X} $Src16AnHI,${Dsp-16-s8}[fb] */
56804 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "adc.w", 24,
56805 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56807 /* adc.w${X} [$Src16An],${Dsp-16-s8}[fb] */
56809 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "adc.w", 24,
56810 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56812 /* adc.w${X} $Src16RnHI,${Dsp-16-u16} */
56814 M32C_INSN_ADC16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "adc16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "adc.w", 32,
56815 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56817 /* adc.w${X} $Src16AnHI,${Dsp-16-u16} */
56819 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "adc16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "adc.w", 32,
56820 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56822 /* adc.w${X} [$Src16An],${Dsp-16-u16} */
56824 M32C_INSN_ADC16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "adc16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "adc.w", 32,
56825 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56827 /* adc.b${X} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
56829 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "adc.b", 24,
56830 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56832 /* adc.b${X} ${Dsp-16-u8}[sb],$Dst16RnQI */
56834 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "adc.b", 24,
56835 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56837 /* adc.b${X} ${Dsp-16-s8}[fb],$Dst16RnQI */
56839 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "adc.b", 24,
56840 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56842 /* adc.b${X} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
56844 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "adc.b", 24,
56845 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56847 /* adc.b${X} ${Dsp-16-u8}[sb],$Dst16AnQI */
56849 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "adc.b", 24,
56850 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56852 /* adc.b${X} ${Dsp-16-s8}[fb],$Dst16AnQI */
56854 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "adc.b", 24,
56855 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56857 /* adc.b${X} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
56859 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "adc.b", 24,
56860 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56862 /* adc.b${X} ${Dsp-16-u8}[sb],[$Dst16An] */
56864 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "adc.b", 24,
56865 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56867 /* adc.b${X} ${Dsp-16-s8}[fb],[$Dst16An] */
56869 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "adc.b", 24,
56870 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56872 /* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
56874 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "adc.b", 32,
56875 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56877 /* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
56879 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "adc.b", 32,
56880 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56882 /* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
56884 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "adc.b", 32,
56885 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56887 /* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
56889 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "adc.b", 40,
56890 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56892 /* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
56894 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "adc.b", 40,
56895 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56897 /* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
56899 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "adc.b", 40,
56900 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56902 /* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
56904 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "adc.b", 32,
56905 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56907 /* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
56909 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "adc.b", 32,
56910 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56912 /* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
56914 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "adc.b", 32,
56915 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56917 /* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
56919 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "adc.b", 40,
56920 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56922 /* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
56924 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "adc.b", 40,
56925 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56927 /* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
56929 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "adc.b", 40,
56930 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56932 /* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
56934 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "adc.b", 32,
56935 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56937 /* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
56939 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "adc.b", 32,
56940 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56942 /* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
56944 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "adc.b", 32,
56945 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56947 /* adc.b${X} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
56949 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "adc16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "adc.b", 40,
56950 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56952 /* adc.b${X} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
56954 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "adc16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "adc.b", 40,
56955 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56957 /* adc.b${X} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
56959 M32C_INSN_ADC16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "adc16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "adc.b", 40,
56960 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56962 /* adc.b${X} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
56964 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "adc.b", 32,
56965 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56967 /* adc.b${X} ${Dsp-16-u16}[sb],$Dst16RnQI */
56969 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "adc.b", 32,
56970 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56972 /* adc.b${X} ${Dsp-16-u16},$Dst16RnQI */
56974 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "adc.b", 32,
56975 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56977 /* adc.b${X} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
56979 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "adc.b", 32,
56980 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56982 /* adc.b${X} ${Dsp-16-u16}[sb],$Dst16AnQI */
56984 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "adc.b", 32,
56985 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56987 /* adc.b${X} ${Dsp-16-u16},$Dst16AnQI */
56989 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "adc.b", 32,
56990 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56992 /* adc.b${X} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
56994 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "adc.b", 32,
56995 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
56997 /* adc.b${X} ${Dsp-16-u16}[sb],[$Dst16An] */
56999 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "adc.b", 32,
57000 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57002 /* adc.b${X} ${Dsp-16-u16},[$Dst16An] */
57004 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "adc.b", 32,
57005 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57007 /* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
57009 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "adc.b", 40,
57010 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57012 /* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
57014 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "adc.b", 40,
57015 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57017 /* adc.b${X} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
57019 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "adc.b", 40,
57020 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57022 /* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
57024 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "adc.b", 48,
57025 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57027 /* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
57029 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "adc.b", 48,
57030 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57032 /* adc.b${X} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
57034 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "adc.b", 48,
57035 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57037 /* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
57039 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "adc.b", 40,
57040 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57042 /* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
57044 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "adc.b", 40,
57045 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57047 /* adc.b${X} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
57049 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "adc.b", 40,
57050 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57052 /* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
57054 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "adc.b", 48,
57055 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57057 /* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
57059 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "adc.b", 48,
57060 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57062 /* adc.b${X} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
57064 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "adc.b", 48,
57065 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57067 /* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
57069 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "adc.b", 40,
57070 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57072 /* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
57074 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "adc.b", 40,
57075 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57077 /* adc.b${X} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
57079 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "adc.b", 40,
57080 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57082 /* adc.b${X} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
57084 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "adc16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "adc.b", 48,
57085 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57087 /* adc.b${X} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
57089 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "adc16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "adc.b", 48,
57090 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57092 /* adc.b${X} ${Dsp-16-u16},${Dsp-32-u16} */
57094 M32C_INSN_ADC16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "adc16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "adc.b", 48,
57095 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57097 /* adc.b${X} $Src16RnQI,$Dst16RnQI */
57099 M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "adc.b", 16,
57100 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57102 /* adc.b${X} $Src16AnQI,$Dst16RnQI */
57104 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "adc.b", 16,
57105 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57107 /* adc.b${X} [$Src16An],$Dst16RnQI */
57109 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "adc.b", 16,
57110 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57112 /* adc.b${X} $Src16RnQI,$Dst16AnQI */
57114 M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "adc.b", 16,
57115 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57117 /* adc.b${X} $Src16AnQI,$Dst16AnQI */
57119 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "adc.b", 16,
57120 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57122 /* adc.b${X} [$Src16An],$Dst16AnQI */
57124 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "adc.b", 16,
57125 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57127 /* adc.b${X} $Src16RnQI,[$Dst16An] */
57129 M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "adc.b", 16,
57130 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57132 /* adc.b${X} $Src16AnQI,[$Dst16An] */
57134 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "adc.b", 16,
57135 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57137 /* adc.b${X} [$Src16An],[$Dst16An] */
57139 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "adc.b", 16,
57140 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57142 /* adc.b${X} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
57144 M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "adc.b", 24,
57145 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57147 /* adc.b${X} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
57149 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "adc.b", 24,
57150 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57152 /* adc.b${X} [$Src16An],${Dsp-16-u8}[$Dst16An] */
57154 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "adc.b", 24,
57155 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57157 /* adc.b${X} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
57159 M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "adc.b", 32,
57160 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57162 /* adc.b${X} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
57164 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "adc.b", 32,
57165 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57167 /* adc.b${X} [$Src16An],${Dsp-16-u16}[$Dst16An] */
57169 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "adc.b", 32,
57170 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57172 /* adc.b${X} $Src16RnQI,${Dsp-16-u8}[sb] */
57174 M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "adc.b", 24,
57175 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57177 /* adc.b${X} $Src16AnQI,${Dsp-16-u8}[sb] */
57179 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "adc.b", 24,
57180 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57182 /* adc.b${X} [$Src16An],${Dsp-16-u8}[sb] */
57184 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "adc.b", 24,
57185 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57187 /* adc.b${X} $Src16RnQI,${Dsp-16-u16}[sb] */
57189 M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "adc.b", 32,
57190 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57192 /* adc.b${X} $Src16AnQI,${Dsp-16-u16}[sb] */
57194 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "adc.b", 32,
57195 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57197 /* adc.b${X} [$Src16An],${Dsp-16-u16}[sb] */
57199 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "adc.b", 32,
57200 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57202 /* adc.b${X} $Src16RnQI,${Dsp-16-s8}[fb] */
57204 M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "adc.b", 24,
57205 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57207 /* adc.b${X} $Src16AnQI,${Dsp-16-s8}[fb] */
57209 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "adc.b", 24,
57210 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57212 /* adc.b${X} [$Src16An],${Dsp-16-s8}[fb] */
57214 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "adc.b", 24,
57215 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57217 /* adc.b${X} $Src16RnQI,${Dsp-16-u16} */
57219 M32C_INSN_ADC16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "adc16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "adc.b", 32,
57220 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57222 /* adc.b${X} $Src16AnQI,${Dsp-16-u16} */
57224 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "adc16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "adc.b", 32,
57225 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57227 /* adc.b${X} [$Src16An],${Dsp-16-u16} */
57229 M32C_INSN_ADC16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "adc16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "adc.b", 32,
57230 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57232 /* adc.w${X} #${Imm-24-HI},$Dst32RnPrefixedHI */
57234 M32C_INSN_ADC32_W_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_HI, "adc32.w-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-HI", "adc.w", 40,
57235 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57237 /* adc.w${X} #${Imm-24-HI},$Dst32AnPrefixedHI */
57239 M32C_INSN_ADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_HI, "adc32.w-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-HI", "adc.w", 40,
57240 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57242 /* adc.w${X} #${Imm-24-HI},[$Dst32AnPrefixed] */
57244 M32C_INSN_ADC32_W_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_HI, "adc32.w-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-HI", "adc.w", 40,
57245 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57247 /* adc.w${X} #${Imm-32-HI},${Dsp-24-u8}[$Dst32AnPrefixed] */
57249 M32C_INSN_ADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-HI", "adc.w", 48,
57250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57252 /* adc.w${X} #${Imm-32-HI},${Dsp-24-u8}[sb] */
57254 M32C_INSN_ADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-HI", "adc.w", 48,
57255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57257 /* adc.w${X} #${Imm-32-HI},${Dsp-24-s8}[fb] */
57259 M32C_INSN_ADC32_W_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-HI", "adc.w", 48,
57260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57262 /* adc.w${X} #${Imm-40-HI},${Dsp-24-u16}[$Dst32AnPrefixed] */
57264 M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-HI", "adc.w", 56,
57265 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57267 /* adc.w${X} #${Imm-40-HI},${Dsp-24-u16}[sb] */
57269 M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-HI", "adc.w", 56,
57270 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57272 /* adc.w${X} #${Imm-40-HI},${Dsp-24-s16}[fb] */
57274 M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-HI", "adc.w", 56,
57275 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57277 /* adc.w${X} #${Imm-40-HI},${Dsp-24-u16} */
57279 M32C_INSN_ADC32_W_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_HI, "adc32.w-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-HI", "adc.w", 56,
57280 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57282 /* adc.w${X} #${Imm-48-HI},${Dsp-24-u24}[$Dst32AnPrefixed] */
57284 M32C_INSN_ADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_HI, "adc32.w-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-HI", "adc.w", 64,
57285 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57287 /* adc.w${X} #${Imm-48-HI},${Dsp-24-u24} */
57289 M32C_INSN_ADC32_W_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_HI, "adc32.w-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-HI", "adc.w", 64,
57290 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57292 /* adc.b${X} #${Imm-24-QI},$Dst32RnPrefixedQI */
57294 M32C_INSN_ADC32_B_IMM_G_BASIC_PREFIXED_DST32_RN_DIRECT_PREFIXED_QI, "adc32.b-imm-G-basic-Prefixed-dst32-Rn-direct-Prefixed-QI", "adc.b", 32,
57295 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57297 /* adc.b${X} #${Imm-24-QI},$Dst32AnPrefixedQI */
57299 M32C_INSN_ADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_DIRECT_PREFIXED_QI, "adc32.b-imm-G-basic-Prefixed-dst32-An-direct-Prefixed-QI", "adc.b", 32,
57300 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57302 /* adc.b${X} #${Imm-24-QI},[$Dst32AnPrefixed] */
57304 M32C_INSN_ADC32_B_IMM_G_BASIC_PREFIXED_DST32_AN_INDIRECT_PREFIXED_QI, "adc32.b-imm-G-basic-Prefixed-dst32-An-indirect-Prefixed-QI", "adc.b", 32,
57305 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57307 /* adc.b${X} #${Imm-32-QI},${Dsp-24-u8}[$Dst32AnPrefixed] */
57309 M32C_INSN_ADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_AN_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-8-Prefixed-dst32-24-8-An-relative-Prefixed-QI", "adc.b", 40,
57310 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57312 /* adc.b${X} #${Imm-32-QI},${Dsp-24-u8}[sb] */
57314 M32C_INSN_ADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_SB_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-8-Prefixed-dst32-24-8-SB-relative-Prefixed-QI", "adc.b", 40,
57315 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57317 /* adc.b${X} #${Imm-32-QI},${Dsp-24-s8}[fb] */
57319 M32C_INSN_ADC32_B_IMM_G_24_8_PREFIXED_DST32_24_8_FB_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-8-Prefixed-dst32-24-8-FB-relative-Prefixed-QI", "adc.b", 40,
57320 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57322 /* adc.b${X} #${Imm-40-QI},${Dsp-24-u16}[$Dst32AnPrefixed] */
57324 M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_AN_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-16-Prefixed-dst32-24-16-An-relative-Prefixed-QI", "adc.b", 48,
57325 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57327 /* adc.b${X} #${Imm-40-QI},${Dsp-24-u16}[sb] */
57329 M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_SB_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-16-Prefixed-dst32-24-16-SB-relative-Prefixed-QI", "adc.b", 48,
57330 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57332 /* adc.b${X} #${Imm-40-QI},${Dsp-24-s16}[fb] */
57334 M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_FB_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-16-Prefixed-dst32-24-16-FB-relative-Prefixed-QI", "adc.b", 48,
57335 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57337 /* adc.b${X} #${Imm-40-QI},${Dsp-24-u16} */
57339 M32C_INSN_ADC32_B_IMM_G_24_16_PREFIXED_DST32_24_16_ABSOLUTE_PREFIXED_QI, "adc32.b-imm-G-24-16-Prefixed-dst32-24-16-absolute-Prefixed-QI", "adc.b", 48,
57340 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57342 /* adc.b${X} #${Imm-48-QI},${Dsp-24-u24}[$Dst32AnPrefixed] */
57344 M32C_INSN_ADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_AN_RELATIVE_PREFIXED_QI, "adc32.b-imm-G-24-24-Prefixed-dst32-24-24-An-relative-Prefixed-QI", "adc.b", 56,
57345 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57347 /* adc.b${X} #${Imm-48-QI},${Dsp-24-u24} */
57349 M32C_INSN_ADC32_B_IMM_G_24_24_PREFIXED_DST32_24_24_ABSOLUTE_PREFIXED_QI, "adc32.b-imm-G-24-24-Prefixed-dst32-24-24-absolute-Prefixed-QI", "adc.b", 56,
57350 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57352 /* adc.w${X} #${Imm-16-HI},$Dst16RnHI */
57354 M32C_INSN_ADC16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "adc16.w-imm-G-basic-dst16-Rn-direct-HI", "adc.w", 32,
57355 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57357 /* adc.w${X} #${Imm-16-HI},$Dst16AnHI */
57359 M32C_INSN_ADC16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "adc16.w-imm-G-basic-dst16-An-direct-HI", "adc.w", 32,
57360 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57362 /* adc.w${X} #${Imm-16-HI},[$Dst16An] */
57364 M32C_INSN_ADC16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "adc16.w-imm-G-basic-dst16-An-indirect-HI", "adc.w", 32,
57365 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57367 /* adc.w${X} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
57369 M32C_INSN_ADC16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "adc16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "adc.w", 40,
57370 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57372 /* adc.w${X} #${Imm-24-HI},${Dsp-16-u8}[sb] */
57374 M32C_INSN_ADC16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "adc16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "adc.w", 40,
57375 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57377 /* adc.w${X} #${Imm-24-HI},${Dsp-16-s8}[fb] */
57379 M32C_INSN_ADC16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "adc16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "adc.w", 40,
57380 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57382 /* adc.w${X} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
57384 M32C_INSN_ADC16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "adc16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "adc.w", 48,
57385 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57387 /* adc.w${X} #${Imm-32-HI},${Dsp-16-u16}[sb] */
57389 M32C_INSN_ADC16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "adc16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "adc.w", 48,
57390 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57392 /* adc.w${X} #${Imm-32-HI},${Dsp-16-u16} */
57394 M32C_INSN_ADC16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "adc16.w-imm-G-16-16-dst16-16-16-absolute-HI", "adc.w", 48,
57395 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57397 /* adc.b${X} #${Imm-16-QI},$Dst16RnQI */
57399 M32C_INSN_ADC16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "adc16.b-imm-G-basic-dst16-Rn-direct-QI", "adc.b", 24,
57400 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57402 /* adc.b${X} #${Imm-16-QI},$Dst16AnQI */
57404 M32C_INSN_ADC16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "adc16.b-imm-G-basic-dst16-An-direct-QI", "adc.b", 24,
57405 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57407 /* adc.b${X} #${Imm-16-QI},[$Dst16An] */
57409 M32C_INSN_ADC16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "adc16.b-imm-G-basic-dst16-An-indirect-QI", "adc.b", 24,
57410 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57412 /* adc.b${X} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
57414 M32C_INSN_ADC16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "adc16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "adc.b", 32,
57415 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57417 /* adc.b${X} #${Imm-24-QI},${Dsp-16-u8}[sb] */
57419 M32C_INSN_ADC16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "adc16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "adc.b", 32,
57420 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57422 /* adc.b${X} #${Imm-24-QI},${Dsp-16-s8}[fb] */
57424 M32C_INSN_ADC16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "adc16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "adc.b", 32,
57425 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57427 /* adc.b${X} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
57429 M32C_INSN_ADC16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "adc16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "adc.b", 40,
57430 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57432 /* adc.b${X} #${Imm-32-QI},${Dsp-16-u16}[sb] */
57434 M32C_INSN_ADC16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "adc16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "adc.b", 40,
57435 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57437 /* adc.b${X} #${Imm-32-QI},${Dsp-16-u16} */
57439 M32C_INSN_ADC16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "adc16.b-imm-G-16-16-dst16-16-16-absolute-QI", "adc.b", 40,
57440 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
57442 /* add.w${S} #${Imm-16-HI},${Dsp-8-u8}[sb] */
57444 M32C_INSN_ADD32_W_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_HI, "add32.w-imm-S-2-S-8-dst32-2-S-8-SB-relative-HI", "add.w", 32,
57445 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57447 /* add.w${S} #${Imm-16-HI},${Dsp-8-s8}[fb] */
57449 M32C_INSN_ADD32_W_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_HI, "add32.w-imm-S-2-S-8-dst32-2-S-8-FB-relative-HI", "add.w", 32,
57450 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57452 /* add.w${S} #${Imm-24-HI},${Dsp-8-u16} */
57454 M32C_INSN_ADD32_W_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_HI, "add32.w-imm-S-2-S-16-dst32-2-S-16-absolute-HI", "add.w", 40,
57455 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57457 /* add.w${S} #${Imm-8-HI},r0 */
57459 M32C_INSN_ADD32_W_IMM_S_2_S_BASIC_DST32_2_S_R0_DIRECT_HI, "add32.w-imm-S-2-S-basic-dst32-2-S-R0-direct-HI", "add.w", 24,
57460 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57462 /* add.b${S} #${Imm-16-QI},${Dsp-8-u8}[sb] */
57464 M32C_INSN_ADD32_B_IMM_S_2_S_8_DST32_2_S_8_SB_RELATIVE_QI, "add32.b-imm-S-2-S-8-dst32-2-S-8-SB-relative-QI", "add.b", 24,
57465 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57467 /* add.b${S} #${Imm-16-QI},${Dsp-8-s8}[fb] */
57469 M32C_INSN_ADD32_B_IMM_S_2_S_8_DST32_2_S_8_FB_RELATIVE_QI, "add32.b-imm-S-2-S-8-dst32-2-S-8-FB-relative-QI", "add.b", 24,
57470 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57472 /* add.b${S} #${Imm-24-QI},${Dsp-8-u16} */
57474 M32C_INSN_ADD32_B_IMM_S_2_S_16_DST32_2_S_16_ABSOLUTE_QI, "add32.b-imm-S-2-S-16-dst32-2-S-16-absolute-QI", "add.b", 32,
57475 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57477 /* add.b${S} #${Imm-8-QI},r0l */
57479 M32C_INSN_ADD32_B_IMM_S_2_S_BASIC_DST32_2_S_R0L_DIRECT_QI, "add32.b-imm-S-2-S-basic-dst32-2-S-R0l-direct-QI", "add.b", 16,
57480 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57482 /* add.l${S} #${Imm1-S},a0 */
57484 M32C_INSN_ADD32_L_S_IMM1_S_AN_DST32_1_S_A0_DIRECT_HI, "add32.l-s-imm1-S-an-dst32-1-S-A0-direct-HI", "add.l", 8,
57485 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57487 /* add.l${S} #${Imm1-S},a1 */
57489 M32C_INSN_ADD32_L_S_IMM1_S_AN_DST32_1_S_A1_DIRECT_HI, "add32.l-s-imm1-S-an-dst32-1-S-A1-direct-HI", "add.l", 8,
57490 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57492 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
57494 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 24,
57495 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57497 /* add.l${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedSI */
57499 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 24,
57500 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57502 /* add.l${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedSI */
57504 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 24,
57505 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57507 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
57509 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 24,
57510 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57512 /* add.l${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedSI */
57514 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 24,
57515 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57517 /* add.l${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedSI */
57519 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 24,
57520 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57522 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
57524 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 24,
57525 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57527 /* add.l${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
57529 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 24,
57530 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57532 /* add.l${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
57534 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 24,
57535 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57537 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
57539 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "add.l", 32,
57540 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57542 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
57544 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "add.l", 32,
57545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57547 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
57549 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-An-relative-Unprefixed-SI", "add.l", 32,
57550 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57552 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
57554 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "add.l", 40,
57555 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57557 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
57559 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "add.l", 40,
57560 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57562 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
57564 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-An-relative-Unprefixed-SI", "add.l", 40,
57565 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57567 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
57569 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "add.l", 48,
57570 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57572 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
57574 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "add.l", 48,
57575 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57577 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
57579 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-An-relative-Unprefixed-SI", "add.l", 48,
57580 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57582 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
57584 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "add.l", 32,
57585 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57587 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
57589 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "add.l", 32,
57590 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57592 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
57594 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-SB-relative-Unprefixed-SI", "add.l", 32,
57595 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57597 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
57599 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "add.l", 40,
57600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57602 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
57604 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "add.l", 40,
57605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57607 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
57609 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-SB-relative-Unprefixed-SI", "add.l", 40,
57610 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57612 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
57614 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "add.l", 32,
57615 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57617 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
57619 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "add.l", 32,
57620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57622 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
57624 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-8-FB-relative-Unprefixed-SI", "add.l", 32,
57625 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57627 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
57629 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "add.l", 40,
57630 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57632 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
57634 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "add.l", 40,
57635 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57637 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
57639 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-FB-relative-Unprefixed-SI", "add.l", 40,
57640 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57642 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
57644 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "add.l", 40,
57645 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57647 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
57649 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "add.l", 40,
57650 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57652 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
57654 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-16-absolute-Unprefixed-SI", "add.l", 40,
57655 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57657 /* add.l${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
57659 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "add.l", 48,
57660 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57662 /* add.l${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
57664 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "add.l", 48,
57665 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57667 /* add.l${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
57669 M32C_INSN_ADD32_L_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-SI-dst32-24-24-absolute-Unprefixed-SI", "add.l", 48,
57670 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57672 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
57674 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 32,
57675 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57677 /* add.l${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedSI */
57679 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 32,
57680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57682 /* add.l${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedSI */
57684 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 32,
57685 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57687 /* add.l${G} ${Dsp-16-u16},$Dst32RnUnprefixedSI */
57689 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 32,
57690 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57692 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
57694 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 32,
57695 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57697 /* add.l${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedSI */
57699 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 32,
57700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57702 /* add.l${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedSI */
57704 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 32,
57705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57707 /* add.l${G} ${Dsp-16-u16},$Dst32AnUnprefixedSI */
57709 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 32,
57710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57712 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
57714 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 32,
57715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57717 /* add.l${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
57719 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 32,
57720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57722 /* add.l${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
57724 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 32,
57725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57727 /* add.l${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
57729 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 32,
57730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57732 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
57734 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "add.l", 40,
57735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57737 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
57739 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "add.l", 40,
57740 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57742 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
57744 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "add.l", 40,
57745 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57747 /* add.l${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
57749 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-An-relative-Unprefixed-SI", "add.l", 40,
57750 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57752 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
57754 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "add.l", 48,
57755 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57757 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
57759 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "add.l", 48,
57760 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57762 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
57764 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "add.l", 48,
57765 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57767 /* add.l${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
57769 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-An-relative-Unprefixed-SI", "add.l", 48,
57770 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57772 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
57774 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "add.l", 56,
57775 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57777 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
57779 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "add.l", 56,
57780 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57782 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
57784 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "add.l", 56,
57785 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57787 /* add.l${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
57789 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-An-relative-Unprefixed-SI", "add.l", 56,
57790 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57792 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
57794 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "add.l", 40,
57795 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57797 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
57799 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "add.l", 40,
57800 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57802 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
57804 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "add.l", 40,
57805 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57807 /* add.l${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
57809 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-SB-relative-Unprefixed-SI", "add.l", 40,
57810 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57812 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
57814 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "add.l", 48,
57815 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57817 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
57819 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "add.l", 48,
57820 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57822 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
57824 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "add.l", 48,
57825 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57827 /* add.l${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
57829 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-SB-relative-Unprefixed-SI", "add.l", 48,
57830 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57832 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
57834 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "add.l", 40,
57835 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57837 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
57839 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "add.l", 40,
57840 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57842 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
57844 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "add.l", 40,
57845 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57847 /* add.l${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
57849 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-8-FB-relative-Unprefixed-SI", "add.l", 40,
57850 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57852 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
57854 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "add.l", 48,
57855 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57857 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
57859 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "add.l", 48,
57860 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57862 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
57864 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "add.l", 48,
57865 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57867 /* add.l${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
57869 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-FB-relative-Unprefixed-SI", "add.l", 48,
57870 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57872 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
57874 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "add.l", 48,
57875 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57877 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
57879 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "add.l", 48,
57880 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57882 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
57884 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "add.l", 48,
57885 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57887 /* add.l${G} ${Dsp-16-u16},${Dsp-32-u16} */
57889 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-16-absolute-Unprefixed-SI", "add.l", 48,
57890 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57892 /* add.l${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
57894 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "add.l", 56,
57895 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57897 /* add.l${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
57899 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "add.l", 56,
57900 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57902 /* add.l${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
57904 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "add.l", 56,
57905 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57907 /* add.l${G} ${Dsp-16-u16},${Dsp-32-u24} */
57909 M32C_INSN_ADD32_L_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-SI-dst32-32-24-absolute-Unprefixed-SI", "add.l", 56,
57910 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57912 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
57914 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 40,
57915 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57917 /* add.l${G} ${Dsp-16-u24},$Dst32RnUnprefixedSI */
57919 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 40,
57920 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57922 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
57924 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 40,
57925 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57927 /* add.l${G} ${Dsp-16-u24},$Dst32AnUnprefixedSI */
57929 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 40,
57930 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57932 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
57934 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 40,
57935 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57937 /* add.l${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
57939 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 40,
57940 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57942 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
57944 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "add.l", 48,
57945 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57947 /* add.l${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
57949 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-An-relative-Unprefixed-SI", "add.l", 48,
57950 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57952 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
57954 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "add.l", 56,
57955 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57957 /* add.l${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
57959 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-An-relative-Unprefixed-SI", "add.l", 56,
57960 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57962 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
57964 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "add.l", 64,
57965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57967 /* add.l${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
57969 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-An-relative-Unprefixed-SI", "add.l", 64,
57970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57972 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
57974 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "add.l", 48,
57975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57977 /* add.l${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
57979 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-SB-relative-Unprefixed-SI", "add.l", 48,
57980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57982 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
57984 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "add.l", 56,
57985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57987 /* add.l${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
57989 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-SB-relative-Unprefixed-SI", "add.l", 56,
57990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57992 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
57994 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "add.l", 48,
57995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
57997 /* add.l${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
57999 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-8-FB-relative-Unprefixed-SI", "add.l", 48,
58000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58002 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
58004 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "add.l", 56,
58005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58007 /* add.l${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
58009 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-FB-relative-Unprefixed-SI", "add.l", 56,
58010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58012 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
58014 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "add.l", 56,
58015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58017 /* add.l${G} ${Dsp-16-u24},${Dsp-40-u16} */
58019 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-16-absolute-Unprefixed-SI", "add.l", 56,
58020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58022 /* add.l${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
58024 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "add.l", 64,
58025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58027 /* add.l${G} ${Dsp-16-u24},${Dsp-40-u24} */
58029 M32C_INSN_ADD32_L_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-SI-dst32-40-24-absolute-Unprefixed-SI", "add.l", 64,
58030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58032 /* add.l${G} $Src32RnUnprefixedSI,$Dst32RnUnprefixedSI */
58034 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 16,
58035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58037 /* add.l${G} $Src32AnUnprefixedSI,$Dst32RnUnprefixedSI */
58039 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 16,
58040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58042 /* add.l${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedSI */
58044 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-Rn-direct-Unprefixed-SI", "add.l", 16,
58045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58047 /* add.l${G} $Src32RnUnprefixedSI,$Dst32AnUnprefixedSI */
58049 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 16,
58050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58052 /* add.l${G} $Src32AnUnprefixedSI,$Dst32AnUnprefixedSI */
58054 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 16,
58055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58057 /* add.l${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedSI */
58059 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-direct-Unprefixed-SI", "add.l", 16,
58060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58062 /* add.l${G} $Src32RnUnprefixedSI,[$Dst32AnUnprefixed] */
58064 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 16,
58065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58067 /* add.l${G} $Src32AnUnprefixedSI,[$Dst32AnUnprefixed] */
58069 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 16,
58070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58072 /* add.l${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
58074 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-An-indirect-Unprefixed-SI", "add.l", 16,
58075 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58077 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
58079 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "add.l", 24,
58080 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58082 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
58084 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "add.l", 24,
58085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58087 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
58089 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-An-relative-Unprefixed-SI", "add.l", 24,
58090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58092 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
58094 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "add.l", 32,
58095 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58097 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
58099 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "add.l", 32,
58100 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58102 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
58104 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-An-relative-Unprefixed-SI", "add.l", 32,
58105 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58107 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
58109 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "add.l", 40,
58110 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58112 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
58114 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "add.l", 40,
58115 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58117 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
58119 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-An-relative-Unprefixed-SI", "add.l", 40,
58120 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58122 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u8}[sb] */
58124 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "add.l", 24,
58125 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58127 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u8}[sb] */
58129 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "add.l", 24,
58130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58132 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
58134 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-SB-relative-Unprefixed-SI", "add.l", 24,
58135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58137 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16}[sb] */
58139 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "add.l", 32,
58140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58142 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16}[sb] */
58144 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "add.l", 32,
58145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58147 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
58149 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-SB-relative-Unprefixed-SI", "add.l", 32,
58150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58152 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-s8}[fb] */
58154 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "add.l", 24,
58155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58157 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-s8}[fb] */
58159 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "add.l", 24,
58160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58162 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
58164 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-8-FB-relative-Unprefixed-SI", "add.l", 24,
58165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58167 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-s16}[fb] */
58169 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "add.l", 32,
58170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58172 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-s16}[fb] */
58174 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "add.l", 32,
58175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58177 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
58179 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-FB-relative-Unprefixed-SI", "add.l", 32,
58180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58182 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u16} */
58184 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "add.l", 32,
58185 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58187 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u16} */
58189 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "add.l", 32,
58190 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58192 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
58194 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-16-absolute-Unprefixed-SI", "add.l", 32,
58195 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58197 /* add.l${G} $Src32RnUnprefixedSI,${Dsp-16-u24} */
58199 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "add.l", 40,
58200 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58202 /* add.l${G} $Src32AnUnprefixedSI,${Dsp-16-u24} */
58204 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "add.l", 40,
58205 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58207 /* add.l${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
58209 M32C_INSN_ADD32_L_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_SI_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-SI-dst32-16-24-absolute-Unprefixed-SI", "add.l", 40,
58210 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58212 /* add.b${S} ${SrcDst16-r0l-r0h-S-normal} */
58214 M32C_INSN_ADD16_B_S_R0L_R0H_SRCDST16_R0L_R0H_S_DERIVED, "add16.b.S-r0l-r0h-srcdst16-r0l-r0h-S-derived", "add.b", 8,
58215 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
58217 /* add.b${S} ${Dsp-8-u8}[sb],${Dst16RnQI-S} */
58219 M32C_INSN_ADD16_B_S_SRC2_SRC16_2_S_8_SB_RELATIVE_QI, "add16.b.S-src2-src16-2-S-8-SB-relative-QI", "add.b", 16,
58220 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
58222 /* add.b${S} ${Dsp-8-s8}[fb],${Dst16RnQI-S} */
58224 M32C_INSN_ADD16_B_S_SRC2_SRC16_2_S_8_FB_RELATIVE_QI, "add16.b.S-src2-src16-2-S-8-FB-relative-QI", "add.b", 16,
58225 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
58227 /* add.b${S} ${Dsp-8-u16},${Dst16RnQI-S} */
58229 M32C_INSN_ADD16_B_S_SRC2_SRC16_2_S_16_ABSOLUTE_QI, "add16.b.S-src2-src16-2-S-16-absolute-QI", "add.b", 24,
58230 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
58232 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
58234 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 24,
58235 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58237 /* add.w${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedHI */
58239 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 24,
58240 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58242 /* add.w${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedHI */
58244 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 24,
58245 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58247 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
58249 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 24,
58250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58252 /* add.w${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedHI */
58254 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 24,
58255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58257 /* add.w${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedHI */
58259 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 24,
58260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58262 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
58264 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 24,
58265 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58267 /* add.w${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
58269 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 24,
58270 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58272 /* add.w${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
58274 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 24,
58275 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58277 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
58279 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "add.w", 32,
58280 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58282 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
58284 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "add.w", 32,
58285 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58287 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
58289 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-An-relative-Unprefixed-HI", "add.w", 32,
58290 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58292 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
58294 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "add.w", 40,
58295 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58297 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
58299 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "add.w", 40,
58300 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58302 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
58304 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-An-relative-Unprefixed-HI", "add.w", 40,
58305 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58307 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
58309 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "add.w", 48,
58310 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58312 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
58314 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "add.w", 48,
58315 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58317 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
58319 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-An-relative-Unprefixed-HI", "add.w", 48,
58320 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58322 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
58324 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "add.w", 32,
58325 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58327 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
58329 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "add.w", 32,
58330 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58332 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
58334 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-SB-relative-Unprefixed-HI", "add.w", 32,
58335 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58337 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
58339 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "add.w", 40,
58340 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58342 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
58344 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "add.w", 40,
58345 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58347 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
58349 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-SB-relative-Unprefixed-HI", "add.w", 40,
58350 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58352 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
58354 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "add.w", 32,
58355 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58357 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
58359 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "add.w", 32,
58360 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58362 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
58364 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-8-FB-relative-Unprefixed-HI", "add.w", 32,
58365 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58367 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
58369 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "add.w", 40,
58370 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58372 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
58374 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "add.w", 40,
58375 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58377 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
58379 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-FB-relative-Unprefixed-HI", "add.w", 40,
58380 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58382 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
58384 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "add.w", 40,
58385 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58387 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
58389 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "add.w", 40,
58390 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58392 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
58394 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-16-absolute-Unprefixed-HI", "add.w", 40,
58395 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58397 /* add.w${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
58399 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "add.w", 48,
58400 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58402 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
58404 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "add.w", 48,
58405 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58407 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
58409 M32C_INSN_ADD32_W_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-HI-dst32-24-24-absolute-Unprefixed-HI", "add.w", 48,
58410 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58412 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
58414 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 32,
58415 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58417 /* add.w${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedHI */
58419 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 32,
58420 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58422 /* add.w${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedHI */
58424 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 32,
58425 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58427 /* add.w${G} ${Dsp-16-u16},$Dst32RnUnprefixedHI */
58429 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 32,
58430 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58432 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
58434 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 32,
58435 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58437 /* add.w${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedHI */
58439 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 32,
58440 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58442 /* add.w${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedHI */
58444 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 32,
58445 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58447 /* add.w${G} ${Dsp-16-u16},$Dst32AnUnprefixedHI */
58449 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 32,
58450 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58452 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
58454 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 32,
58455 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58457 /* add.w${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
58459 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 32,
58460 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58462 /* add.w${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
58464 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 32,
58465 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58467 /* add.w${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
58469 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 32,
58470 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58472 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
58474 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "add.w", 40,
58475 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58477 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
58479 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "add.w", 40,
58480 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58482 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
58484 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "add.w", 40,
58485 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58487 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
58489 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-An-relative-Unprefixed-HI", "add.w", 40,
58490 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58492 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
58494 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "add.w", 48,
58495 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58497 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
58499 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "add.w", 48,
58500 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58502 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
58504 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "add.w", 48,
58505 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58507 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
58509 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-An-relative-Unprefixed-HI", "add.w", 48,
58510 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58512 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
58514 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "add.w", 56,
58515 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58517 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
58519 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "add.w", 56,
58520 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58522 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
58524 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "add.w", 56,
58525 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58527 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
58529 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-An-relative-Unprefixed-HI", "add.w", 56,
58530 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58532 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
58534 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "add.w", 40,
58535 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58537 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
58539 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "add.w", 40,
58540 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58542 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
58544 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "add.w", 40,
58545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58547 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
58549 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-SB-relative-Unprefixed-HI", "add.w", 40,
58550 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58552 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
58554 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "add.w", 48,
58555 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58557 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
58559 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "add.w", 48,
58560 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58562 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
58564 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "add.w", 48,
58565 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58567 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
58569 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-SB-relative-Unprefixed-HI", "add.w", 48,
58570 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58572 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
58574 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "add.w", 40,
58575 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58577 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
58579 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "add.w", 40,
58580 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58582 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
58584 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "add.w", 40,
58585 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58587 /* add.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
58589 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-8-FB-relative-Unprefixed-HI", "add.w", 40,
58590 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58592 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
58594 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "add.w", 48,
58595 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58597 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
58599 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "add.w", 48,
58600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58602 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
58604 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "add.w", 48,
58605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58607 /* add.w${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
58609 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-FB-relative-Unprefixed-HI", "add.w", 48,
58610 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58612 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
58614 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "add.w", 48,
58615 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58617 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
58619 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "add.w", 48,
58620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58622 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
58624 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "add.w", 48,
58625 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58627 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
58629 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-16-absolute-Unprefixed-HI", "add.w", 48,
58630 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58632 /* add.w${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
58634 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "add.w", 56,
58635 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58637 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
58639 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "add.w", 56,
58640 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58642 /* add.w${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
58644 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "add.w", 56,
58645 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58647 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u24} */
58649 M32C_INSN_ADD32_W_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-HI-dst32-32-24-absolute-Unprefixed-HI", "add.w", 56,
58650 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58652 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
58654 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 40,
58655 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58657 /* add.w${G} ${Dsp-16-u24},$Dst32RnUnprefixedHI */
58659 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 40,
58660 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58662 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
58664 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 40,
58665 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58667 /* add.w${G} ${Dsp-16-u24},$Dst32AnUnprefixedHI */
58669 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 40,
58670 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58672 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
58674 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 40,
58675 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58677 /* add.w${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
58679 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 40,
58680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58682 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
58684 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "add.w", 48,
58685 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58687 /* add.w${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
58689 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-An-relative-Unprefixed-HI", "add.w", 48,
58690 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58692 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
58694 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "add.w", 56,
58695 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58697 /* add.w${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
58699 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-An-relative-Unprefixed-HI", "add.w", 56,
58700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58702 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
58704 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "add.w", 64,
58705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58707 /* add.w${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
58709 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-An-relative-Unprefixed-HI", "add.w", 64,
58710 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58712 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
58714 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "add.w", 48,
58715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58717 /* add.w${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
58719 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-SB-relative-Unprefixed-HI", "add.w", 48,
58720 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58722 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
58724 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "add.w", 56,
58725 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58727 /* add.w${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
58729 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-SB-relative-Unprefixed-HI", "add.w", 56,
58730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58732 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
58734 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "add.w", 48,
58735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58737 /* add.w${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
58739 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-8-FB-relative-Unprefixed-HI", "add.w", 48,
58740 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58742 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
58744 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "add.w", 56,
58745 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58747 /* add.w${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
58749 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-FB-relative-Unprefixed-HI", "add.w", 56,
58750 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58752 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
58754 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "add.w", 56,
58755 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58757 /* add.w${G} ${Dsp-16-u24},${Dsp-40-u16} */
58759 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-16-absolute-Unprefixed-HI", "add.w", 56,
58760 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58762 /* add.w${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
58764 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "add.w", 64,
58765 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58767 /* add.w${G} ${Dsp-16-u24},${Dsp-40-u24} */
58769 M32C_INSN_ADD32_W_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-HI-dst32-40-24-absolute-Unprefixed-HI", "add.w", 64,
58770 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58772 /* add.w${G} $Src32RnUnprefixedHI,$Dst32RnUnprefixedHI */
58774 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 16,
58775 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58777 /* add.w${G} $Src32AnUnprefixedHI,$Dst32RnUnprefixedHI */
58779 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 16,
58780 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58782 /* add.w${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedHI */
58784 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-Rn-direct-Unprefixed-HI", "add.w", 16,
58785 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58787 /* add.w${G} $Src32RnUnprefixedHI,$Dst32AnUnprefixedHI */
58789 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 16,
58790 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58792 /* add.w${G} $Src32AnUnprefixedHI,$Dst32AnUnprefixedHI */
58794 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 16,
58795 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58797 /* add.w${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedHI */
58799 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-direct-Unprefixed-HI", "add.w", 16,
58800 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58802 /* add.w${G} $Src32RnUnprefixedHI,[$Dst32AnUnprefixed] */
58804 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 16,
58805 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58807 /* add.w${G} $Src32AnUnprefixedHI,[$Dst32AnUnprefixed] */
58809 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 16,
58810 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58812 /* add.w${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
58814 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-An-indirect-Unprefixed-HI", "add.w", 16,
58815 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58817 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
58819 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "add.w", 24,
58820 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58822 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
58824 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "add.w", 24,
58825 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58827 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
58829 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-An-relative-Unprefixed-HI", "add.w", 24,
58830 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58832 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
58834 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "add.w", 32,
58835 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58837 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
58839 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "add.w", 32,
58840 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58842 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
58844 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-An-relative-Unprefixed-HI", "add.w", 32,
58845 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58847 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
58849 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "add.w", 40,
58850 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58852 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
58854 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "add.w", 40,
58855 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58857 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
58859 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-An-relative-Unprefixed-HI", "add.w", 40,
58860 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58862 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u8}[sb] */
58864 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "add.w", 24,
58865 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58867 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u8}[sb] */
58869 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "add.w", 24,
58870 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58872 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
58874 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-SB-relative-Unprefixed-HI", "add.w", 24,
58875 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58877 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16}[sb] */
58879 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "add.w", 32,
58880 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58882 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16}[sb] */
58884 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "add.w", 32,
58885 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58887 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
58889 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-SB-relative-Unprefixed-HI", "add.w", 32,
58890 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58892 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-s8}[fb] */
58894 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "add.w", 24,
58895 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58897 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-s8}[fb] */
58899 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "add.w", 24,
58900 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58902 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
58904 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-8-FB-relative-Unprefixed-HI", "add.w", 24,
58905 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58907 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-s16}[fb] */
58909 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "add.w", 32,
58910 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58912 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-s16}[fb] */
58914 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "add.w", 32,
58915 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58917 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
58919 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-FB-relative-Unprefixed-HI", "add.w", 32,
58920 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58922 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u16} */
58924 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "add.w", 32,
58925 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58927 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u16} */
58929 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "add.w", 32,
58930 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58932 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
58934 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-16-absolute-Unprefixed-HI", "add.w", 32,
58935 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58937 /* add.w${G} $Src32RnUnprefixedHI,${Dsp-16-u24} */
58939 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "add.w", 40,
58940 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58942 /* add.w${G} $Src32AnUnprefixedHI,${Dsp-16-u24} */
58944 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "add.w", 40,
58945 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58947 /* add.w${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
58949 M32C_INSN_ADD32_W_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_HI_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-HI-dst32-16-24-absolute-Unprefixed-HI", "add.w", 40,
58950 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58952 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
58954 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 24,
58955 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58957 /* add.b${G} ${Dsp-16-u8}[sb],$Dst32RnUnprefixedQI */
58959 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 24,
58960 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58962 /* add.b${G} ${Dsp-16-s8}[fb],$Dst32RnUnprefixedQI */
58964 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 24,
58965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58967 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
58969 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 24,
58970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58972 /* add.b${G} ${Dsp-16-u8}[sb],$Dst32AnUnprefixedQI */
58974 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 24,
58975 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58977 /* add.b${G} ${Dsp-16-s8}[fb],$Dst32AnUnprefixedQI */
58979 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 24,
58980 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58982 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
58984 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 24,
58985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58987 /* add.b${G} ${Dsp-16-u8}[sb],[$Dst32AnUnprefixed] */
58989 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 24,
58990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58992 /* add.b${G} ${Dsp-16-s8}[fb],[$Dst32AnUnprefixed] */
58994 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 24,
58995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
58997 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[$Dst32AnUnprefixed] */
58999 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "add.b", 32,
59000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59002 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
59004 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "add.b", 32,
59005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59007 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst32AnUnprefixed] */
59009 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-An-relative-Unprefixed-QI", "add.b", 32,
59010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59012 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[$Dst32AnUnprefixed] */
59014 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "add.b", 40,
59015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59017 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
59019 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "add.b", 40,
59020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59022 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst32AnUnprefixed] */
59024 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-An-relative-Unprefixed-QI", "add.b", 40,
59025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59027 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24}[$Dst32AnUnprefixed] */
59029 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "add.b", 48,
59030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59032 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
59034 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "add.b", 48,
59035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59037 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24}[$Dst32AnUnprefixed] */
59039 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-An-relative-Unprefixed-QI", "add.b", 48,
59040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59042 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u8}[sb] */
59044 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "add.b", 32,
59045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59047 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
59049 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "add.b", 32,
59050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59052 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
59054 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-SB-relative-Unprefixed-QI", "add.b", 32,
59055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59057 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16}[sb] */
59059 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "add.b", 40,
59060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59062 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
59064 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "add.b", 40,
59065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59067 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
59069 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-SB-relative-Unprefixed-QI", "add.b", 40,
59070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59072 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s8}[fb] */
59074 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "add.b", 32,
59075 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59077 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
59079 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "add.b", 32,
59080 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59082 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
59084 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-8-FB-relative-Unprefixed-QI", "add.b", 32,
59085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59087 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-s16}[fb] */
59089 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "add.b", 40,
59090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59092 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s16}[fb] */
59094 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "add.b", 40,
59095 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59097 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s16}[fb] */
59099 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-FB-relative-Unprefixed-QI", "add.b", 40,
59100 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59102 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u16} */
59104 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "add.b", 40,
59105 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59107 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
59109 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "add.b", 40,
59110 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59112 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
59114 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-16-absolute-Unprefixed-QI", "add.b", 40,
59115 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59117 /* add.b${G} ${Dsp-16-u8}[$Src32AnUnprefixed],${Dsp-24-u24} */
59119 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-An-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "add.b", 48,
59120 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59122 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u24} */
59124 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-SB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "add.b", 48,
59125 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59127 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u24} */
59129 M32C_INSN_ADD32_B_16_8_UNPREFIXED_24_UNPREFIXED_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-8-Unprefixed-24-Unprefixed-src32-16-8-FB-relative-Unprefixed-QI-dst32-24-24-absolute-Unprefixed-QI", "add.b", 48,
59130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59132 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
59134 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 32,
59135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59137 /* add.b${G} ${Dsp-16-u16}[sb],$Dst32RnUnprefixedQI */
59139 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 32,
59140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59142 /* add.b${G} ${Dsp-16-s16}[fb],$Dst32RnUnprefixedQI */
59144 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 32,
59145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59147 /* add.b${G} ${Dsp-16-u16},$Dst32RnUnprefixedQI */
59149 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 32,
59150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59152 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
59154 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 32,
59155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59157 /* add.b${G} ${Dsp-16-u16}[sb],$Dst32AnUnprefixedQI */
59159 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 32,
59160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59162 /* add.b${G} ${Dsp-16-s16}[fb],$Dst32AnUnprefixedQI */
59164 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 32,
59165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59167 /* add.b${G} ${Dsp-16-u16},$Dst32AnUnprefixedQI */
59169 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 32,
59170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59172 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
59174 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 32,
59175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59177 /* add.b${G} ${Dsp-16-u16}[sb],[$Dst32AnUnprefixed] */
59179 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 32,
59180 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59182 /* add.b${G} ${Dsp-16-s16}[fb],[$Dst32AnUnprefixed] */
59184 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 32,
59185 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59187 /* add.b${G} ${Dsp-16-u16},[$Dst32AnUnprefixed] */
59189 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 32,
59190 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59192 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[$Dst32AnUnprefixed] */
59194 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "add.b", 40,
59195 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59197 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
59199 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "add.b", 40,
59200 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59202 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[$Dst32AnUnprefixed] */
59204 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "add.b", 40,
59205 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59207 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst32AnUnprefixed] */
59209 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-An-relative-Unprefixed-QI", "add.b", 40,
59210 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59212 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[$Dst32AnUnprefixed] */
59214 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "add.b", 48,
59215 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59217 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
59219 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "add.b", 48,
59220 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59222 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[$Dst32AnUnprefixed] */
59224 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "add.b", 48,
59225 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59227 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst32AnUnprefixed] */
59229 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-An-relative-Unprefixed-QI", "add.b", 48,
59230 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59232 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24}[$Dst32AnUnprefixed] */
59234 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "add.b", 56,
59235 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59237 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
59239 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "add.b", 56,
59240 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59242 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24}[$Dst32AnUnprefixed] */
59244 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "add.b", 56,
59245 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59247 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u24}[$Dst32AnUnprefixed] */
59249 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-An-relative-Unprefixed-QI", "add.b", 56,
59250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59252 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u8}[sb] */
59254 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "add.b", 40,
59255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59257 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
59259 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "add.b", 40,
59260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59262 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u8}[sb] */
59264 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "add.b", 40,
59265 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59267 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
59269 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-SB-relative-Unprefixed-QI", "add.b", 40,
59270 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59272 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16}[sb] */
59274 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "add.b", 48,
59275 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59277 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
59279 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "add.b", 48,
59280 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59282 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16}[sb] */
59284 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "add.b", 48,
59285 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59287 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
59289 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-SB-relative-Unprefixed-QI", "add.b", 48,
59290 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59292 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s8}[fb] */
59294 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "add.b", 40,
59295 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59297 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
59299 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "add.b", 40,
59300 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59302 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s8}[fb] */
59304 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "add.b", 40,
59305 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59307 /* add.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
59309 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-8-FB-relative-Unprefixed-QI", "add.b", 40,
59310 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59312 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-s16}[fb] */
59314 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "add.b", 48,
59315 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59317 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s16}[fb] */
59319 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "add.b", 48,
59320 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59322 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-s16}[fb] */
59324 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "add.b", 48,
59325 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59327 /* add.b${G} ${Dsp-16-u16},${Dsp-32-s16}[fb] */
59329 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-FB-relative-Unprefixed-QI", "add.b", 48,
59330 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59332 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u16} */
59334 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "add.b", 48,
59335 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59337 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
59339 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "add.b", 48,
59340 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59342 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u16} */
59344 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "add.b", 48,
59345 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59347 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
59349 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-16-absolute-Unprefixed-QI", "add.b", 48,
59350 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59352 /* add.b${G} ${Dsp-16-u16}[$Src32AnUnprefixed],${Dsp-32-u24} */
59354 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-An-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "add.b", 56,
59355 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59357 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u24} */
59359 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-SB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "add.b", 56,
59360 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59362 /* add.b${G} ${Dsp-16-s16}[fb],${Dsp-32-u24} */
59364 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-FB-relative-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "add.b", 56,
59365 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59367 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u24} */
59369 M32C_INSN_ADD32_B_16_16_UNPREFIXED_32_UNPREFIXED_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-16-Unprefixed-32-Unprefixed-src32-16-16-absolute-Unprefixed-QI-dst32-32-24-absolute-Unprefixed-QI", "add.b", 56,
59370 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59372 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
59374 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 40,
59375 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59377 /* add.b${G} ${Dsp-16-u24},$Dst32RnUnprefixedQI */
59379 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 40,
59380 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59382 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
59384 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 40,
59385 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59387 /* add.b${G} ${Dsp-16-u24},$Dst32AnUnprefixedQI */
59389 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 40,
59390 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59392 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
59394 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 40,
59395 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59397 /* add.b${G} ${Dsp-16-u24},[$Dst32AnUnprefixed] */
59399 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 40,
59400 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59402 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[$Dst32AnUnprefixed] */
59404 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "add.b", 48,
59405 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59407 /* add.b${G} ${Dsp-16-u24},${Dsp-40-u8}[$Dst32AnUnprefixed] */
59409 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-An-relative-Unprefixed-QI", "add.b", 48,
59410 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59412 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[$Dst32AnUnprefixed] */
59414 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "add.b", 56,
59415 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59417 /* add.b${G} ${Dsp-16-u24},${Dsp-40-u16}[$Dst32AnUnprefixed] */
59419 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-An-relative-Unprefixed-QI", "add.b", 56,
59420 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59422 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24}[$Dst32AnUnprefixed] */
59424 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "add.b", 64,
59425 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59427 /* add.b${G} ${Dsp-16-u24},${Dsp-40-u24}[$Dst32AnUnprefixed] */
59429 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-An-relative-Unprefixed-QI", "add.b", 64,
59430 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59432 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u8}[sb] */
59434 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "add.b", 48,
59435 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59437 /* add.b${G} ${Dsp-16-u24},${Dsp-40-u8}[sb] */
59439 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-SB-relative-Unprefixed-QI", "add.b", 48,
59440 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59442 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16}[sb] */
59444 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "add.b", 56,
59445 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59447 /* add.b${G} ${Dsp-16-u24},${Dsp-40-u16}[sb] */
59449 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-SB-relative-Unprefixed-QI", "add.b", 56,
59450 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59452 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s8}[fb] */
59454 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "add.b", 48,
59455 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59457 /* add.b${G} ${Dsp-16-u24},${Dsp-40-s8}[fb] */
59459 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-8-FB-relative-Unprefixed-QI", "add.b", 48,
59460 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59462 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-s16}[fb] */
59464 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "add.b", 56,
59465 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59467 /* add.b${G} ${Dsp-16-u24},${Dsp-40-s16}[fb] */
59469 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-FB-relative-Unprefixed-QI", "add.b", 56,
59470 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59472 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u16} */
59474 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "add.b", 56,
59475 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59477 /* add.b${G} ${Dsp-16-u24},${Dsp-40-u16} */
59479 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-16-absolute-Unprefixed-QI", "add.b", 56,
59480 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59482 /* add.b${G} ${Dsp-16-u24}[$Src32AnUnprefixed],${Dsp-40-u24} */
59484 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-An-relative-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "add.b", 64,
59485 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59487 /* add.b${G} ${Dsp-16-u24},${Dsp-40-u24} */
59489 M32C_INSN_ADD32_B_16_24_UNPREFIXED_40_UNPREFIXED_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-16-24-Unprefixed-40-Unprefixed-src32-16-24-absolute-Unprefixed-QI-dst32-40-24-absolute-Unprefixed-QI", "add.b", 64,
59490 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59492 /* add.b${G} $Src32RnUnprefixedQI,$Dst32RnUnprefixedQI */
59494 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 16,
59495 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59497 /* add.b${G} $Src32AnUnprefixedQI,$Dst32RnUnprefixedQI */
59499 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 16,
59500 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59502 /* add.b${G} [$Src32AnUnprefixed],$Dst32RnUnprefixedQI */
59504 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-Rn-direct-Unprefixed-QI", "add.b", 16,
59505 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59507 /* add.b${G} $Src32RnUnprefixedQI,$Dst32AnUnprefixedQI */
59509 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 16,
59510 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59512 /* add.b${G} $Src32AnUnprefixedQI,$Dst32AnUnprefixedQI */
59514 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 16,
59515 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59517 /* add.b${G} [$Src32AnUnprefixed],$Dst32AnUnprefixedQI */
59519 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-direct-Unprefixed-QI", "add.b", 16,
59520 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59522 /* add.b${G} $Src32RnUnprefixedQI,[$Dst32AnUnprefixed] */
59524 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 16,
59525 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59527 /* add.b${G} $Src32AnUnprefixedQI,[$Dst32AnUnprefixed] */
59529 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 16,
59530 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59532 /* add.b${G} [$Src32AnUnprefixed],[$Dst32AnUnprefixed] */
59534 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-An-indirect-Unprefixed-QI", "add.b", 16,
59535 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59537 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
59539 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "add.b", 24,
59540 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59542 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[$Dst32AnUnprefixed] */
59544 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "add.b", 24,
59545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59547 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[$Dst32AnUnprefixed] */
59549 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-An-relative-Unprefixed-QI", "add.b", 24,
59550 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59552 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
59554 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "add.b", 32,
59555 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59557 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[$Dst32AnUnprefixed] */
59559 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "add.b", 32,
59560 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59562 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[$Dst32AnUnprefixed] */
59564 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-An-relative-Unprefixed-QI", "add.b", 32,
59565 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59567 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
59569 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "add.b", 40,
59570 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59572 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24}[$Dst32AnUnprefixed] */
59574 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "add.b", 40,
59575 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59577 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u24}[$Dst32AnUnprefixed] */
59579 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-An-relative-Unprefixed-QI", "add.b", 40,
59580 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59582 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u8}[sb] */
59584 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "add.b", 24,
59585 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59587 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u8}[sb] */
59589 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "add.b", 24,
59590 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59592 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u8}[sb] */
59594 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-SB-relative-Unprefixed-QI", "add.b", 24,
59595 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59597 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16}[sb] */
59599 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "add.b", 32,
59600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59602 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16}[sb] */
59604 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "add.b", 32,
59605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59607 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u16}[sb] */
59609 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-SB-relative-Unprefixed-QI", "add.b", 32,
59610 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59612 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-s8}[fb] */
59614 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "add.b", 24,
59615 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59617 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-s8}[fb] */
59619 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "add.b", 24,
59620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59622 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-s8}[fb] */
59624 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-8-FB-relative-Unprefixed-QI", "add.b", 24,
59625 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59627 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-s16}[fb] */
59629 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "add.b", 32,
59630 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59632 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-s16}[fb] */
59634 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "add.b", 32,
59635 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59637 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-s16}[fb] */
59639 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-FB-relative-Unprefixed-QI", "add.b", 32,
59640 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59642 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u16} */
59644 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "add.b", 32,
59645 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59647 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u16} */
59649 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "add.b", 32,
59650 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59652 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u16} */
59654 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-16-absolute-Unprefixed-QI", "add.b", 32,
59655 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59657 /* add.b${G} $Src32RnUnprefixedQI,${Dsp-16-u24} */
59659 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_RN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-Rn-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "add.b", 40,
59660 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59662 /* add.b${G} $Src32AnUnprefixedQI,${Dsp-16-u24} */
59664 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_DIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-direct-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "add.b", 40,
59665 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59667 /* add.b${G} [$Src32AnUnprefixed],${Dsp-16-u24} */
59669 M32C_INSN_ADD32_B_BASIC_UNPREFIXED_16_UNPREFIXED_SRC32_AN_INDIRECT_UNPREFIXED_QI_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-basic-Unprefixed-16-Unprefixed-src32-An-indirect-Unprefixed-QI-dst32-16-24-absolute-Unprefixed-QI", "add.b", 40,
59670 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
59672 /* add.w${G} ${Dsp-16-u8}[$Src16An],$Dst16RnHI */
59674 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-Rn-direct-HI", "add.w", 24,
59675 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59677 /* add.w${G} ${Dsp-16-u8}[sb],$Dst16RnHI */
59679 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-Rn-direct-HI", "add.w", 24,
59680 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59682 /* add.w${G} ${Dsp-16-s8}[fb],$Dst16RnHI */
59684 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_RN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-Rn-direct-HI", "add.w", 24,
59685 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59687 /* add.w${G} ${Dsp-16-u8}[$Src16An],$Dst16AnHI */
59689 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-direct-HI", "add.w", 24,
59690 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59692 /* add.w${G} ${Dsp-16-u8}[sb],$Dst16AnHI */
59694 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-direct-HI", "add.w", 24,
59695 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59697 /* add.w${G} ${Dsp-16-s8}[fb],$Dst16AnHI */
59699 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_DIRECT_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-direct-HI", "add.w", 24,
59700 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59702 /* add.w${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
59704 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-An-indirect-HI", "add.w", 24,
59705 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59707 /* add.w${G} ${Dsp-16-u8}[sb],[$Dst16An] */
59709 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-An-indirect-HI", "add.w", 24,
59710 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59712 /* add.w${G} ${Dsp-16-s8}[fb],[$Dst16An] */
59714 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-An-indirect-HI", "add.w", 24,
59715 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59717 /* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
59719 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-An-relative-HI", "add.w", 32,
59720 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59722 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
59724 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-An-relative-HI", "add.w", 32,
59725 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59727 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
59729 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-An-relative-HI", "add.w", 32,
59730 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59732 /* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
59734 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-An-relative-HI", "add.w", 40,
59735 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59737 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
59739 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-An-relative-HI", "add.w", 40,
59740 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59742 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
59744 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_AN_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-An-relative-HI", "add.w", 40,
59745 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59747 /* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
59749 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-SB-relative-HI", "add.w", 32,
59750 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59752 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
59754 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-SB-relative-HI", "add.w", 32,
59755 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59757 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
59759 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-SB-relative-HI", "add.w", 32,
59760 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59762 /* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
59764 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-SB-relative-HI", "add.w", 40,
59765 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59767 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
59769 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-SB-relative-HI", "add.w", 40,
59770 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59772 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
59774 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_SB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-SB-relative-HI", "add.w", 40,
59775 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59777 /* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
59779 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-8-FB-relative-HI", "add.w", 32,
59780 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59782 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
59784 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-8-FB-relative-HI", "add.w", 32,
59785 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59787 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
59789 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_8_FB_RELATIVE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-8-FB-relative-HI", "add.w", 32,
59790 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59792 /* add.w${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
59794 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_AN_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "add16.w-16-8-24-src16-16-8-An-relative-HI-dst16-24-16-absolute-HI", "add.w", 40,
59795 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59797 /* add.w${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
59799 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_SB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "add16.w-16-8-24-src16-16-8-SB-relative-HI-dst16-24-16-absolute-HI", "add.w", 40,
59800 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59802 /* add.w${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
59804 M32C_INSN_ADD16_W_16_8_24_SRC16_16_8_FB_RELATIVE_HI_DST16_24_16_ABSOLUTE_HI, "add16.w-16-8-24-src16-16-8-FB-relative-HI-dst16-24-16-absolute-HI", "add.w", 40,
59805 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59807 /* add.w${G} ${Dsp-16-u16}[$Src16An],$Dst16RnHI */
59809 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_RN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-Rn-direct-HI", "add.w", 32,
59810 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59812 /* add.w${G} ${Dsp-16-u16}[sb],$Dst16RnHI */
59814 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_RN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-Rn-direct-HI", "add.w", 32,
59815 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59817 /* add.w${G} ${Dsp-16-u16},$Dst16RnHI */
59819 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_RN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-Rn-direct-HI", "add.w", 32,
59820 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59822 /* add.w${G} ${Dsp-16-u16}[$Src16An],$Dst16AnHI */
59824 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-direct-HI", "add.w", 32,
59825 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59827 /* add.w${G} ${Dsp-16-u16}[sb],$Dst16AnHI */
59829 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-direct-HI", "add.w", 32,
59830 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59832 /* add.w${G} ${Dsp-16-u16},$Dst16AnHI */
59834 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_DIRECT_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-direct-HI", "add.w", 32,
59835 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59837 /* add.w${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
59839 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-An-indirect-HI", "add.w", 32,
59840 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59842 /* add.w${G} ${Dsp-16-u16}[sb],[$Dst16An] */
59844 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-An-indirect-HI", "add.w", 32,
59845 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59847 /* add.w${G} ${Dsp-16-u16},[$Dst16An] */
59849 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_AN_INDIRECT_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-An-indirect-HI", "add.w", 32,
59850 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59852 /* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
59854 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-An-relative-HI", "add.w", 40,
59855 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59857 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
59859 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-An-relative-HI", "add.w", 40,
59860 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59862 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
59864 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-An-relative-HI", "add.w", 40,
59865 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59867 /* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
59869 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-An-relative-HI", "add.w", 48,
59870 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59872 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
59874 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-An-relative-HI", "add.w", 48,
59875 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59877 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
59879 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_AN_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-An-relative-HI", "add.w", 48,
59880 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59882 /* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
59884 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-SB-relative-HI", "add.w", 40,
59885 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59887 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
59889 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-SB-relative-HI", "add.w", 40,
59890 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59892 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
59894 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-SB-relative-HI", "add.w", 40,
59895 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59897 /* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
59899 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-SB-relative-HI", "add.w", 48,
59900 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59902 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
59904 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-SB-relative-HI", "add.w", 48,
59905 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59907 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
59909 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_SB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-SB-relative-HI", "add.w", 48,
59910 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59912 /* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
59914 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-8-FB-relative-HI", "add.w", 40,
59915 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59917 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
59919 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_8_FB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-8-FB-relative-HI", "add.w", 40,
59920 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59922 /* add.w${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
59924 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_8_FB_RELATIVE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-8-FB-relative-HI", "add.w", 40,
59925 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59927 /* add.w${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
59929 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_AN_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "add16.w-16-16-32-src16-16-16-An-relative-HI-dst16-32-16-absolute-HI", "add.w", 48,
59930 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59932 /* add.w${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
59934 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_SB_RELATIVE_HI_DST16_32_16_ABSOLUTE_HI, "add16.w-16-16-32-src16-16-16-SB-relative-HI-dst16-32-16-absolute-HI", "add.w", 48,
59935 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59937 /* add.w${G} ${Dsp-16-u16},${Dsp-32-u16} */
59939 M32C_INSN_ADD16_W_16_16_32_SRC16_16_16_ABSOLUTE_HI_DST16_32_16_ABSOLUTE_HI, "add16.w-16-16-32-src16-16-16-absolute-HI-dst16-32-16-absolute-HI", "add.w", 48,
59940 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59942 /* add.w${G} $Src16RnHI,$Dst16RnHI */
59944 M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_RN_DIRECT_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-Rn-direct-HI", "add.w", 16,
59945 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59947 /* add.w${G} $Src16AnHI,$Dst16RnHI */
59949 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_RN_DIRECT_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-Rn-direct-HI", "add.w", 16,
59950 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59952 /* add.w${G} [$Src16An],$Dst16RnHI */
59954 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_RN_DIRECT_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-Rn-direct-HI", "add.w", 16,
59955 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59957 /* add.w${G} $Src16RnHI,$Dst16AnHI */
59959 M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_DIRECT_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-An-direct-HI", "add.w", 16,
59960 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59962 /* add.w${G} $Src16AnHI,$Dst16AnHI */
59964 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_DIRECT_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-An-direct-HI", "add.w", 16,
59965 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59967 /* add.w${G} [$Src16An],$Dst16AnHI */
59969 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_DIRECT_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-An-direct-HI", "add.w", 16,
59970 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59972 /* add.w${G} $Src16RnHI,[$Dst16An] */
59974 M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_AN_INDIRECT_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-An-indirect-HI", "add.w", 16,
59975 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59977 /* add.w${G} $Src16AnHI,[$Dst16An] */
59979 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_AN_INDIRECT_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-An-indirect-HI", "add.w", 16,
59980 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59982 /* add.w${G} [$Src16An],[$Dst16An] */
59984 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_AN_INDIRECT_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-An-indirect-HI", "add.w", 16,
59985 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59987 /* add.w${G} $Src16RnHI,${Dsp-16-u8}[$Dst16An] */
59989 M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-An-relative-HI", "add.w", 24,
59990 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59992 /* add.w${G} $Src16AnHI,${Dsp-16-u8}[$Dst16An] */
59994 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-8-An-relative-HI", "add.w", 24,
59995 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
59997 /* add.w${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
59999 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_AN_RELATIVE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-8-An-relative-HI", "add.w", 24,
60000 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60002 /* add.w${G} $Src16RnHI,${Dsp-16-u16}[$Dst16An] */
60004 M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-An-relative-HI", "add.w", 32,
60005 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60007 /* add.w${G} $Src16AnHI,${Dsp-16-u16}[$Dst16An] */
60009 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-16-An-relative-HI", "add.w", 32,
60010 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60012 /* add.w${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
60014 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_AN_RELATIVE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-16-An-relative-HI", "add.w", 32,
60015 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60017 /* add.w${G} $Src16RnHI,${Dsp-16-u8}[sb] */
60019 M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-SB-relative-HI", "add.w", 24,
60020 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60022 /* add.w${G} $Src16AnHI,${Dsp-16-u8}[sb] */
60024 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-8-SB-relative-HI", "add.w", 24,
60025 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60027 /* add.w${G} [$Src16An],${Dsp-16-u8}[sb] */
60029 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_SB_RELATIVE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-8-SB-relative-HI", "add.w", 24,
60030 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60032 /* add.w${G} $Src16RnHI,${Dsp-16-u16}[sb] */
60034 M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-SB-relative-HI", "add.w", 32,
60035 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60037 /* add.w${G} $Src16AnHI,${Dsp-16-u16}[sb] */
60039 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-16-SB-relative-HI", "add.w", 32,
60040 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60042 /* add.w${G} [$Src16An],${Dsp-16-u16}[sb] */
60044 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_SB_RELATIVE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-16-SB-relative-HI", "add.w", 32,
60045 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60047 /* add.w${G} $Src16RnHI,${Dsp-16-s8}[fb] */
60049 M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-8-FB-relative-HI", "add.w", 24,
60050 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60052 /* add.w${G} $Src16AnHI,${Dsp-16-s8}[fb] */
60054 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-8-FB-relative-HI", "add.w", 24,
60055 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60057 /* add.w${G} [$Src16An],${Dsp-16-s8}[fb] */
60059 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_8_FB_RELATIVE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-8-FB-relative-HI", "add.w", 24,
60060 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60062 /* add.w${G} $Src16RnHI,${Dsp-16-u16} */
60064 M32C_INSN_ADD16_W_BASIC_16_SRC16_RN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "add16.w-basic-16-src16-Rn-direct-HI-dst16-16-16-absolute-HI", "add.w", 32,
60065 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60067 /* add.w${G} $Src16AnHI,${Dsp-16-u16} */
60069 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_DIRECT_HI_DST16_16_16_ABSOLUTE_HI, "add16.w-basic-16-src16-An-direct-HI-dst16-16-16-absolute-HI", "add.w", 32,
60070 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60072 /* add.w${G} [$Src16An],${Dsp-16-u16} */
60074 M32C_INSN_ADD16_W_BASIC_16_SRC16_AN_INDIRECT_HI_DST16_16_16_ABSOLUTE_HI, "add16.w-basic-16-src16-An-indirect-HI-dst16-16-16-absolute-HI", "add.w", 32,
60075 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60077 /* add.b${G} ${Dsp-16-u8}[$Src16An],$Dst16RnQI */
60079 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-Rn-direct-QI", "add.b", 24,
60080 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60082 /* add.b${G} ${Dsp-16-u8}[sb],$Dst16RnQI */
60084 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-Rn-direct-QI", "add.b", 24,
60085 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60087 /* add.b${G} ${Dsp-16-s8}[fb],$Dst16RnQI */
60089 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_RN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-Rn-direct-QI", "add.b", 24,
60090 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60092 /* add.b${G} ${Dsp-16-u8}[$Src16An],$Dst16AnQI */
60094 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-direct-QI", "add.b", 24,
60095 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60097 /* add.b${G} ${Dsp-16-u8}[sb],$Dst16AnQI */
60099 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-direct-QI", "add.b", 24,
60100 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60102 /* add.b${G} ${Dsp-16-s8}[fb],$Dst16AnQI */
60104 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_DIRECT_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-direct-QI", "add.b", 24,
60105 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60107 /* add.b${G} ${Dsp-16-u8}[$Src16An],[$Dst16An] */
60109 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-An-indirect-QI", "add.b", 24,
60110 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60112 /* add.b${G} ${Dsp-16-u8}[sb],[$Dst16An] */
60114 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-An-indirect-QI", "add.b", 24,
60115 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60117 /* add.b${G} ${Dsp-16-s8}[fb],[$Dst16An] */
60119 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-An-indirect-QI", "add.b", 24,
60120 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60122 /* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[$Dst16An] */
60124 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-An-relative-QI", "add.b", 32,
60125 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60127 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[$Dst16An] */
60129 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-An-relative-QI", "add.b", 32,
60130 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60132 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[$Dst16An] */
60134 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-An-relative-QI", "add.b", 32,
60135 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60137 /* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[$Dst16An] */
60139 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-An-relative-QI", "add.b", 40,
60140 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60142 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[$Dst16An] */
60144 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-An-relative-QI", "add.b", 40,
60145 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60147 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[$Dst16An] */
60149 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_AN_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-An-relative-QI", "add.b", 40,
60150 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60152 /* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u8}[sb] */
60154 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-SB-relative-QI", "add.b", 32,
60155 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60157 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u8}[sb] */
60159 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-SB-relative-QI", "add.b", 32,
60160 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60162 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u8}[sb] */
60164 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-SB-relative-QI", "add.b", 32,
60165 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60167 /* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16}[sb] */
60169 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-SB-relative-QI", "add.b", 40,
60170 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60172 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16}[sb] */
60174 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-SB-relative-QI", "add.b", 40,
60175 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60177 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16}[sb] */
60179 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_SB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-SB-relative-QI", "add.b", 40,
60180 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60182 /* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-s8}[fb] */
60184 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-8-FB-relative-QI", "add.b", 32,
60185 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60187 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-s8}[fb] */
60189 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-8-FB-relative-QI", "add.b", 32,
60190 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60192 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-s8}[fb] */
60194 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_8_FB_RELATIVE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-8-FB-relative-QI", "add.b", 32,
60195 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60197 /* add.b${G} ${Dsp-16-u8}[$Src16An],${Dsp-24-u16} */
60199 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_AN_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "add16.b-16-8-24-src16-16-8-An-relative-QI-dst16-24-16-absolute-QI", "add.b", 40,
60200 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60202 /* add.b${G} ${Dsp-16-u8}[sb],${Dsp-24-u16} */
60204 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_SB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "add16.b-16-8-24-src16-16-8-SB-relative-QI-dst16-24-16-absolute-QI", "add.b", 40,
60205 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60207 /* add.b${G} ${Dsp-16-s8}[fb],${Dsp-24-u16} */
60209 M32C_INSN_ADD16_B_16_8_24_SRC16_16_8_FB_RELATIVE_QI_DST16_24_16_ABSOLUTE_QI, "add16.b-16-8-24-src16-16-8-FB-relative-QI-dst16-24-16-absolute-QI", "add.b", 40,
60210 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60212 /* add.b${G} ${Dsp-16-u16}[$Src16An],$Dst16RnQI */
60214 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_RN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-Rn-direct-QI", "add.b", 32,
60215 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60217 /* add.b${G} ${Dsp-16-u16}[sb],$Dst16RnQI */
60219 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_RN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-Rn-direct-QI", "add.b", 32,
60220 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60222 /* add.b${G} ${Dsp-16-u16},$Dst16RnQI */
60224 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_RN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-Rn-direct-QI", "add.b", 32,
60225 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60227 /* add.b${G} ${Dsp-16-u16}[$Src16An],$Dst16AnQI */
60229 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-direct-QI", "add.b", 32,
60230 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60232 /* add.b${G} ${Dsp-16-u16}[sb],$Dst16AnQI */
60234 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-direct-QI", "add.b", 32,
60235 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60237 /* add.b${G} ${Dsp-16-u16},$Dst16AnQI */
60239 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_DIRECT_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-direct-QI", "add.b", 32,
60240 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60242 /* add.b${G} ${Dsp-16-u16}[$Src16An],[$Dst16An] */
60244 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-An-indirect-QI", "add.b", 32,
60245 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60247 /* add.b${G} ${Dsp-16-u16}[sb],[$Dst16An] */
60249 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-An-indirect-QI", "add.b", 32,
60250 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60252 /* add.b${G} ${Dsp-16-u16},[$Dst16An] */
60254 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_AN_INDIRECT_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-An-indirect-QI", "add.b", 32,
60255 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60257 /* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[$Dst16An] */
60259 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-An-relative-QI", "add.b", 40,
60260 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60262 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[$Dst16An] */
60264 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-An-relative-QI", "add.b", 40,
60265 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60267 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[$Dst16An] */
60269 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-An-relative-QI", "add.b", 40,
60270 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60272 /* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[$Dst16An] */
60274 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-An-relative-QI", "add.b", 48,
60275 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60277 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[$Dst16An] */
60279 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-An-relative-QI", "add.b", 48,
60280 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60282 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[$Dst16An] */
60284 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_AN_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-An-relative-QI", "add.b", 48,
60285 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60287 /* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u8}[sb] */
60289 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-SB-relative-QI", "add.b", 40,
60290 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60292 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u8}[sb] */
60294 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-SB-relative-QI", "add.b", 40,
60295 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60297 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u8}[sb] */
60299 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-SB-relative-QI", "add.b", 40,
60300 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60302 /* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16}[sb] */
60304 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-SB-relative-QI", "add.b", 48,
60305 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60307 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16}[sb] */
60309 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-SB-relative-QI", "add.b", 48,
60310 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60312 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u16}[sb] */
60314 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_SB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-SB-relative-QI", "add.b", 48,
60315 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60317 /* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-s8}[fb] */
60319 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-8-FB-relative-QI", "add.b", 40,
60320 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60322 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-s8}[fb] */
60324 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_8_FB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-8-FB-relative-QI", "add.b", 40,
60325 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60327 /* add.b${G} ${Dsp-16-u16},${Dsp-32-s8}[fb] */
60329 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_8_FB_RELATIVE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-8-FB-relative-QI", "add.b", 40,
60330 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60332 /* add.b${G} ${Dsp-16-u16}[$Src16An],${Dsp-32-u16} */
60334 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_AN_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "add16.b-16-16-32-src16-16-16-An-relative-QI-dst16-32-16-absolute-QI", "add.b", 48,
60335 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60337 /* add.b${G} ${Dsp-16-u16}[sb],${Dsp-32-u16} */
60339 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_SB_RELATIVE_QI_DST16_32_16_ABSOLUTE_QI, "add16.b-16-16-32-src16-16-16-SB-relative-QI-dst16-32-16-absolute-QI", "add.b", 48,
60340 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60342 /* add.b${G} ${Dsp-16-u16},${Dsp-32-u16} */
60344 M32C_INSN_ADD16_B_16_16_32_SRC16_16_16_ABSOLUTE_QI_DST16_32_16_ABSOLUTE_QI, "add16.b-16-16-32-src16-16-16-absolute-QI-dst16-32-16-absolute-QI", "add.b", 48,
60345 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60347 /* add.b${G} $Src16RnQI,$Dst16RnQI */
60349 M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_RN_DIRECT_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-Rn-direct-QI", "add.b", 16,
60350 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60352 /* add.b${G} $Src16AnQI,$Dst16RnQI */
60354 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_RN_DIRECT_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-Rn-direct-QI", "add.b", 16,
60355 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60357 /* add.b${G} [$Src16An],$Dst16RnQI */
60359 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_RN_DIRECT_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-Rn-direct-QI", "add.b", 16,
60360 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60362 /* add.b${G} $Src16RnQI,$Dst16AnQI */
60364 M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_DIRECT_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-An-direct-QI", "add.b", 16,
60365 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60367 /* add.b${G} $Src16AnQI,$Dst16AnQI */
60369 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_DIRECT_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-An-direct-QI", "add.b", 16,
60370 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60372 /* add.b${G} [$Src16An],$Dst16AnQI */
60374 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_DIRECT_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-An-direct-QI", "add.b", 16,
60375 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60377 /* add.b${G} $Src16RnQI,[$Dst16An] */
60379 M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_AN_INDIRECT_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-An-indirect-QI", "add.b", 16,
60380 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60382 /* add.b${G} $Src16AnQI,[$Dst16An] */
60384 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_AN_INDIRECT_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-An-indirect-QI", "add.b", 16,
60385 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60387 /* add.b${G} [$Src16An],[$Dst16An] */
60389 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_AN_INDIRECT_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-An-indirect-QI", "add.b", 16,
60390 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60392 /* add.b${G} $Src16RnQI,${Dsp-16-u8}[$Dst16An] */
60394 M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-An-relative-QI", "add.b", 24,
60395 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60397 /* add.b${G} $Src16AnQI,${Dsp-16-u8}[$Dst16An] */
60399 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-8-An-relative-QI", "add.b", 24,
60400 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60402 /* add.b${G} [$Src16An],${Dsp-16-u8}[$Dst16An] */
60404 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_AN_RELATIVE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-8-An-relative-QI", "add.b", 24,
60405 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60407 /* add.b${G} $Src16RnQI,${Dsp-16-u16}[$Dst16An] */
60409 M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-An-relative-QI", "add.b", 32,
60410 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60412 /* add.b${G} $Src16AnQI,${Dsp-16-u16}[$Dst16An] */
60414 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-16-An-relative-QI", "add.b", 32,
60415 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60417 /* add.b${G} [$Src16An],${Dsp-16-u16}[$Dst16An] */
60419 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_AN_RELATIVE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-16-An-relative-QI", "add.b", 32,
60420 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60422 /* add.b${G} $Src16RnQI,${Dsp-16-u8}[sb] */
60424 M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-SB-relative-QI", "add.b", 24,
60425 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60427 /* add.b${G} $Src16AnQI,${Dsp-16-u8}[sb] */
60429 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-8-SB-relative-QI", "add.b", 24,
60430 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60432 /* add.b${G} [$Src16An],${Dsp-16-u8}[sb] */
60434 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_SB_RELATIVE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-8-SB-relative-QI", "add.b", 24,
60435 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60437 /* add.b${G} $Src16RnQI,${Dsp-16-u16}[sb] */
60439 M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-SB-relative-QI", "add.b", 32,
60440 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60442 /* add.b${G} $Src16AnQI,${Dsp-16-u16}[sb] */
60444 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-16-SB-relative-QI", "add.b", 32,
60445 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60447 /* add.b${G} [$Src16An],${Dsp-16-u16}[sb] */
60449 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_SB_RELATIVE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-16-SB-relative-QI", "add.b", 32,
60450 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60452 /* add.b${G} $Src16RnQI,${Dsp-16-s8}[fb] */
60454 M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-8-FB-relative-QI", "add.b", 24,
60455 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60457 /* add.b${G} $Src16AnQI,${Dsp-16-s8}[fb] */
60459 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-8-FB-relative-QI", "add.b", 24,
60460 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60462 /* add.b${G} [$Src16An],${Dsp-16-s8}[fb] */
60464 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_8_FB_RELATIVE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-8-FB-relative-QI", "add.b", 24,
60465 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60467 /* add.b${G} $Src16RnQI,${Dsp-16-u16} */
60469 M32C_INSN_ADD16_B_BASIC_16_SRC16_RN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "add16.b-basic-16-src16-Rn-direct-QI-dst16-16-16-absolute-QI", "add.b", 32,
60470 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60472 /* add.b${G} $Src16AnQI,${Dsp-16-u16} */
60474 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_DIRECT_QI_DST16_16_16_ABSOLUTE_QI, "add16.b-basic-16-src16-An-direct-QI-dst16-16-16-absolute-QI", "add.b", 32,
60475 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60477 /* add.b${G} [$Src16An],${Dsp-16-u16} */
60479 M32C_INSN_ADD16_B_BASIC_16_SRC16_AN_INDIRECT_QI_DST16_16_16_ABSOLUTE_QI, "add16.b-basic-16-src16-An-indirect-QI-dst16-16-16-absolute-QI", "add.b", 32,
60480 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60482 /* add.b${S} #${Imm-8-QI},r0l */
60484 M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_R0L_DIRECT_QI, "add16.b.S-imm8-dst3-dst16-3-S-R0l-direct-QI", "add.b", 16,
60485 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60487 /* add.b${S} #${Imm-8-QI},r0h */
60489 M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_R0H_DIRECT_QI, "add16.b.S-imm8-dst3-dst16-3-S-R0h-direct-QI", "add.b", 16,
60490 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60492 /* add.b${S} #${Imm-8-QI},${Dsp-16-u8}[sb] */
60494 M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_16_8_SB_RELATIVE_QI, "add16.b.S-imm8-dst3-dst16-3-S-16-8-SB-relative-QI", "add.b", 24,
60495 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60497 /* add.b${S} #${Imm-8-QI},${Dsp-16-s8}[fb] */
60499 M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_16_8_FB_RELATIVE_QI, "add16.b.S-imm8-dst3-dst16-3-S-16-8-FB-relative-QI", "add.b", 24,
60500 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60502 /* add.b${S} #${Imm-8-QI},${Dsp-16-u16} */
60504 M32C_INSN_ADD16_B_S_IMM8_DST3_DST16_3_S_16_16_ABSOLUTE_QI, "add16.b.S-imm8-dst3-dst16-3-S-16-16-absolute-QI", "add.b", 32,
60505 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60507 /* add.l${Q} #${Imm-12-s4},$Dst32RnUnprefixedSI */
60509 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "add.l", 16,
60510 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60512 /* add.l${Q} #${Imm-12-s4},$Dst32AnUnprefixedSI */
60514 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-SI", "add.l", 16,
60515 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60517 /* add.l${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
60519 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-SI", "add.l", 16,
60520 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60522 /* add.l${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
60524 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "add.l", 24,
60525 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60527 /* add.l${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
60529 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "add.l", 32,
60530 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60532 /* add.l${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
60534 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "add.l", 40,
60535 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60537 /* add.l${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
60539 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "add.l", 24,
60540 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60542 /* add.l${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
60544 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "add.l", 32,
60545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60547 /* add.l${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
60549 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "add.l", 24,
60550 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60552 /* add.l${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
60554 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "add.l", 32,
60555 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60557 /* add.l${Q} #${Imm-12-s4},${Dsp-16-u16} */
60559 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "add.l", 32,
60560 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60562 /* add.l${Q} #${Imm-12-s4},${Dsp-16-u24} */
60564 M32C_INSN_ADD32_L_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "add.l", 40,
60565 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60567 /* add.w${Q} #${Imm-12-s4},$Dst32RnUnprefixedHI */
60569 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "add.w", 16,
60570 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60572 /* add.w${Q} #${Imm-12-s4},$Dst32AnUnprefixedHI */
60574 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "add.w", 16,
60575 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60577 /* add.w${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
60579 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "add.w", 16,
60580 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60582 /* add.w${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
60584 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "add.w", 24,
60585 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60587 /* add.w${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
60589 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "add.w", 32,
60590 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60592 /* add.w${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
60594 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "add.w", 40,
60595 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60597 /* add.w${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
60599 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "add.w", 24,
60600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60602 /* add.w${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
60604 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "add.w", 32,
60605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60607 /* add.w${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
60609 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "add.w", 24,
60610 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60612 /* add.w${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
60614 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "add.w", 32,
60615 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60617 /* add.w${Q} #${Imm-12-s4},${Dsp-16-u16} */
60619 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "add.w", 32,
60620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60622 /* add.w${Q} #${Imm-12-s4},${Dsp-16-u24} */
60624 M32C_INSN_ADD32_W_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "add.w", 40,
60625 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60627 /* add.b${Q} #${Imm-12-s4},$Dst32RnUnprefixedQI */
60629 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "add.b", 16,
60630 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60632 /* add.b${Q} #${Imm-12-s4},$Dst32AnUnprefixedQI */
60634 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "add.b", 16,
60635 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60637 /* add.b${Q} #${Imm-12-s4},[$Dst32AnUnprefixed] */
60639 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "add.b", 16,
60640 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60642 /* add.b${Q} #${Imm-12-s4},${Dsp-16-u8}[$Dst32AnUnprefixed] */
60644 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "add.b", 24,
60645 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60647 /* add.b${Q} #${Imm-12-s4},${Dsp-16-u16}[$Dst32AnUnprefixed] */
60649 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "add.b", 32,
60650 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60652 /* add.b${Q} #${Imm-12-s4},${Dsp-16-u24}[$Dst32AnUnprefixed] */
60654 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "add.b", 40,
60655 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60657 /* add.b${Q} #${Imm-12-s4},${Dsp-16-u8}[sb] */
60659 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "add.b", 24,
60660 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60662 /* add.b${Q} #${Imm-12-s4},${Dsp-16-u16}[sb] */
60664 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "add.b", 32,
60665 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60667 /* add.b${Q} #${Imm-12-s4},${Dsp-16-s8}[fb] */
60669 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "add.b", 24,
60670 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60672 /* add.b${Q} #${Imm-12-s4},${Dsp-16-s16}[fb] */
60674 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "add.b", 32,
60675 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60677 /* add.b${Q} #${Imm-12-s4},${Dsp-16-u16} */
60679 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "add.b", 32,
60680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60682 /* add.b${Q} #${Imm-12-s4},${Dsp-16-u24} */
60684 M32C_INSN_ADD32_B_IMM4_Q_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-imm4-Q-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "add.b", 40,
60685 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60687 /* add.w${Q} #${Imm-8-s4},$Dst16RnHI */
60689 M32C_INSN_ADD16_W_IMM4_Q_16_DST16_RN_DIRECT_HI, "add16.w-imm4-Q-16-dst16-Rn-direct-HI", "add.w", 16,
60690 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60692 /* add.w${Q} #${Imm-8-s4},$Dst16AnHI */
60694 M32C_INSN_ADD16_W_IMM4_Q_16_DST16_AN_DIRECT_HI, "add16.w-imm4-Q-16-dst16-An-direct-HI", "add.w", 16,
60695 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60697 /* add.w${Q} #${Imm-8-s4},[$Dst16An] */
60699 M32C_INSN_ADD16_W_IMM4_Q_16_DST16_AN_INDIRECT_HI, "add16.w-imm4-Q-16-dst16-An-indirect-HI", "add.w", 16,
60700 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60702 /* add.w${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
60704 M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_8_AN_RELATIVE_HI, "add16.w-imm4-Q-16-dst16-16-8-An-relative-HI", "add.w", 24,
60705 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60707 /* add.w${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
60709 M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_16_AN_RELATIVE_HI, "add16.w-imm4-Q-16-dst16-16-16-An-relative-HI", "add.w", 32,
60710 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60712 /* add.w${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
60714 M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_8_SB_RELATIVE_HI, "add16.w-imm4-Q-16-dst16-16-8-SB-relative-HI", "add.w", 24,
60715 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60717 /* add.w${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
60719 M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_16_SB_RELATIVE_HI, "add16.w-imm4-Q-16-dst16-16-16-SB-relative-HI", "add.w", 32,
60720 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60722 /* add.w${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
60724 M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_8_FB_RELATIVE_HI, "add16.w-imm4-Q-16-dst16-16-8-FB-relative-HI", "add.w", 24,
60725 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60727 /* add.w${Q} #${Imm-8-s4},${Dsp-16-u16} */
60729 M32C_INSN_ADD16_W_IMM4_Q_16_DST16_16_16_ABSOLUTE_HI, "add16.w-imm4-Q-16-dst16-16-16-absolute-HI", "add.w", 32,
60730 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60732 /* add.b${Q} #${Imm-8-s4},$Dst16RnQI */
60734 M32C_INSN_ADD16_B_IMM4_Q_16_DST16_RN_DIRECT_QI, "add16.b-imm4-Q-16-dst16-Rn-direct-QI", "add.b", 16,
60735 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60737 /* add.b${Q} #${Imm-8-s4},$Dst16AnQI */
60739 M32C_INSN_ADD16_B_IMM4_Q_16_DST16_AN_DIRECT_QI, "add16.b-imm4-Q-16-dst16-An-direct-QI", "add.b", 16,
60740 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60742 /* add.b${Q} #${Imm-8-s4},[$Dst16An] */
60744 M32C_INSN_ADD16_B_IMM4_Q_16_DST16_AN_INDIRECT_QI, "add16.b-imm4-Q-16-dst16-An-indirect-QI", "add.b", 16,
60745 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60747 /* add.b${Q} #${Imm-8-s4},${Dsp-16-u8}[$Dst16An] */
60749 M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_8_AN_RELATIVE_QI, "add16.b-imm4-Q-16-dst16-16-8-An-relative-QI", "add.b", 24,
60750 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60752 /* add.b${Q} #${Imm-8-s4},${Dsp-16-u16}[$Dst16An] */
60754 M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_16_AN_RELATIVE_QI, "add16.b-imm4-Q-16-dst16-16-16-An-relative-QI", "add.b", 32,
60755 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60757 /* add.b${Q} #${Imm-8-s4},${Dsp-16-u8}[sb] */
60759 M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_8_SB_RELATIVE_QI, "add16.b-imm4-Q-16-dst16-16-8-SB-relative-QI", "add.b", 24,
60760 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60762 /* add.b${Q} #${Imm-8-s4},${Dsp-16-u16}[sb] */
60764 M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_16_SB_RELATIVE_QI, "add16.b-imm4-Q-16-dst16-16-16-SB-relative-QI", "add.b", 32,
60765 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60767 /* add.b${Q} #${Imm-8-s4},${Dsp-16-s8}[fb] */
60769 M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_8_FB_RELATIVE_QI, "add16.b-imm4-Q-16-dst16-16-8-FB-relative-QI", "add.b", 24,
60770 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60772 /* add.b${Q} #${Imm-8-s4},${Dsp-16-u16} */
60774 M32C_INSN_ADD16_B_IMM4_Q_16_DST16_16_16_ABSOLUTE_QI, "add16.b-imm4-Q-16-dst16-16-16-absolute-QI", "add.b", 32,
60775 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60777 /* add.w${G} #${Imm-16-HI},$Dst32RnUnprefixedHI */
60779 M32C_INSN_ADD32_W_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "add32.w-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "add.w", 32,
60780 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60782 /* add.w${G} #${Imm-16-HI},$Dst32AnUnprefixedHI */
60784 M32C_INSN_ADD32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "add32.w-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-HI", "add.w", 32,
60785 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60787 /* add.w${G} #${Imm-16-HI},[$Dst32AnUnprefixed] */
60789 M32C_INSN_ADD32_W_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "add32.w-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-HI", "add.w", 32,
60790 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60792 /* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
60794 M32C_INSN_ADD32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "add.w", 40,
60795 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60797 /* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
60799 M32C_INSN_ADD32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "add.w", 40,
60800 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60802 /* add.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
60804 M32C_INSN_ADD32_W_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "add.w", 40,
60805 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60807 /* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
60809 M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "add.w", 48,
60810 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60812 /* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
60814 M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "add.w", 48,
60815 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60817 /* add.w${G} #${Imm-32-HI},${Dsp-16-s16}[fb] */
60819 M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "add.w", 48,
60820 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60822 /* add.w${G} #${Imm-32-HI},${Dsp-16-u16} */
60824 M32C_INSN_ADD32_W_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "add32.w-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "add.w", 48,
60825 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60827 /* add.w${G} #${Imm-40-HI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
60829 M32C_INSN_ADD32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "add32.w-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "add.w", 56,
60830 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60832 /* add.w${G} #${Imm-40-HI},${Dsp-16-u24} */
60834 M32C_INSN_ADD32_W_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "add32.w-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "add.w", 56,
60835 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60837 /* add.b${G} #${Imm-16-QI},$Dst32RnUnprefixedQI */
60839 M32C_INSN_ADD32_B_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "add32.b-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "add.b", 24,
60840 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60842 /* add.b${G} #${Imm-16-QI},$Dst32AnUnprefixedQI */
60844 M32C_INSN_ADD32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "add32.b-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-QI", "add.b", 24,
60845 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60847 /* add.b${G} #${Imm-16-QI},[$Dst32AnUnprefixed] */
60849 M32C_INSN_ADD32_B_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "add32.b-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-QI", "add.b", 24,
60850 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60852 /* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
60854 M32C_INSN_ADD32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "add.b", 32,
60855 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60857 /* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
60859 M32C_INSN_ADD32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "add.b", 32,
60860 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60862 /* add.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
60864 M32C_INSN_ADD32_B_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "add.b", 32,
60865 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60867 /* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
60869 M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "add.b", 40,
60870 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60872 /* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
60874 M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "add.b", 40,
60875 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60877 /* add.b${G} #${Imm-32-QI},${Dsp-16-s16}[fb] */
60879 M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "add.b", 40,
60880 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60882 /* add.b${G} #${Imm-32-QI},${Dsp-16-u16} */
60884 M32C_INSN_ADD32_B_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "add32.b-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "add.b", 40,
60885 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60887 /* add.b${G} #${Imm-40-QI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
60889 M32C_INSN_ADD32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "add32.b-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "add.b", 48,
60890 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60892 /* add.b${G} #${Imm-40-QI},${Dsp-16-u24} */
60894 M32C_INSN_ADD32_B_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "add32.b-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "add.b", 48,
60895 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60897 /* add.w${G} #${Imm-16-HI},$Dst16RnHI */
60899 M32C_INSN_ADD16_W_IMM_G_BASIC_DST16_RN_DIRECT_HI, "add16.w-imm-G-basic-dst16-Rn-direct-HI", "add.w", 32,
60900 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60902 /* add.w${G} #${Imm-16-HI},$Dst16AnHI */
60904 M32C_INSN_ADD16_W_IMM_G_BASIC_DST16_AN_DIRECT_HI, "add16.w-imm-G-basic-dst16-An-direct-HI", "add.w", 32,
60905 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60907 /* add.w${G} #${Imm-16-HI},[$Dst16An] */
60909 M32C_INSN_ADD16_W_IMM_G_BASIC_DST16_AN_INDIRECT_HI, "add16.w-imm-G-basic-dst16-An-indirect-HI", "add.w", 32,
60910 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60912 /* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[$Dst16An] */
60914 M32C_INSN_ADD16_W_IMM_G_16_8_DST16_16_8_AN_RELATIVE_HI, "add16.w-imm-G-16-8-dst16-16-8-An-relative-HI", "add.w", 40,
60915 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60917 /* add.w${G} #${Imm-24-HI},${Dsp-16-u8}[sb] */
60919 M32C_INSN_ADD16_W_IMM_G_16_8_DST16_16_8_SB_RELATIVE_HI, "add16.w-imm-G-16-8-dst16-16-8-SB-relative-HI", "add.w", 40,
60920 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60922 /* add.w${G} #${Imm-24-HI},${Dsp-16-s8}[fb] */
60924 M32C_INSN_ADD16_W_IMM_G_16_8_DST16_16_8_FB_RELATIVE_HI, "add16.w-imm-G-16-8-dst16-16-8-FB-relative-HI", "add.w", 40,
60925 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60927 /* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[$Dst16An] */
60929 M32C_INSN_ADD16_W_IMM_G_16_16_DST16_16_16_AN_RELATIVE_HI, "add16.w-imm-G-16-16-dst16-16-16-An-relative-HI", "add.w", 48,
60930 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60932 /* add.w${G} #${Imm-32-HI},${Dsp-16-u16}[sb] */
60934 M32C_INSN_ADD16_W_IMM_G_16_16_DST16_16_16_SB_RELATIVE_HI, "add16.w-imm-G-16-16-dst16-16-16-SB-relative-HI", "add.w", 48,
60935 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60937 /* add.w${G} #${Imm-32-HI},${Dsp-16-u16} */
60939 M32C_INSN_ADD16_W_IMM_G_16_16_DST16_16_16_ABSOLUTE_HI, "add16.w-imm-G-16-16-dst16-16-16-absolute-HI", "add.w", 48,
60940 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60942 /* add.b${G} #${Imm-16-QI},$Dst16RnQI */
60944 M32C_INSN_ADD16_B_IMM_G_BASIC_DST16_RN_DIRECT_QI, "add16.b-imm-G-basic-dst16-Rn-direct-QI", "add.b", 24,
60945 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60947 /* add.b${G} #${Imm-16-QI},$Dst16AnQI */
60949 M32C_INSN_ADD16_B_IMM_G_BASIC_DST16_AN_DIRECT_QI, "add16.b-imm-G-basic-dst16-An-direct-QI", "add.b", 24,
60950 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60952 /* add.b${G} #${Imm-16-QI},[$Dst16An] */
60954 M32C_INSN_ADD16_B_IMM_G_BASIC_DST16_AN_INDIRECT_QI, "add16.b-imm-G-basic-dst16-An-indirect-QI", "add.b", 24,
60955 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60957 /* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[$Dst16An] */
60959 M32C_INSN_ADD16_B_IMM_G_16_8_DST16_16_8_AN_RELATIVE_QI, "add16.b-imm-G-16-8-dst16-16-8-An-relative-QI", "add.b", 32,
60960 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60962 /* add.b${G} #${Imm-24-QI},${Dsp-16-u8}[sb] */
60964 M32C_INSN_ADD16_B_IMM_G_16_8_DST16_16_8_SB_RELATIVE_QI, "add16.b-imm-G-16-8-dst16-16-8-SB-relative-QI", "add.b", 32,
60965 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60967 /* add.b${G} #${Imm-24-QI},${Dsp-16-s8}[fb] */
60969 M32C_INSN_ADD16_B_IMM_G_16_8_DST16_16_8_FB_RELATIVE_QI, "add16.b-imm-G-16-8-dst16-16-8-FB-relative-QI", "add.b", 32,
60970 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60972 /* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[$Dst16An] */
60974 M32C_INSN_ADD16_B_IMM_G_16_16_DST16_16_16_AN_RELATIVE_QI, "add16.b-imm-G-16-16-dst16-16-16-An-relative-QI", "add.b", 40,
60975 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60977 /* add.b${G} #${Imm-32-QI},${Dsp-16-u16}[sb] */
60979 M32C_INSN_ADD16_B_IMM_G_16_16_DST16_16_16_SB_RELATIVE_QI, "add16.b-imm-G-16-16-dst16-16-16-SB-relative-QI", "add.b", 40,
60980 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60982 /* add.b${G} #${Imm-32-QI},${Dsp-16-u16} */
60984 M32C_INSN_ADD16_B_IMM_G_16_16_DST16_16_16_ABSOLUTE_QI, "add16.b-imm-G-16-16-dst16-16-16-absolute-QI", "add.b", 40,
60985 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
60987 /* add.l${G} #${Imm-16-SI},$Dst32RnUnprefixedSI */
60989 M32C_INSN_ADD32_L_IMM_G_BASIC_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_SI, "add32.l-imm-G-basic-Unprefixed-dst32-Rn-direct-Unprefixed-SI", "add.l", 48,
60990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60992 /* add.l${G} #${Imm-16-SI},$Dst32AnUnprefixedSI */
60994 M32C_INSN_ADD32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_SI, "add32.l-imm-G-basic-Unprefixed-dst32-An-direct-Unprefixed-SI", "add.l", 48,
60995 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
60997 /* add.l${G} #${Imm-16-SI},[$Dst32AnUnprefixed] */
60999 M32C_INSN_ADD32_L_IMM_G_BASIC_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_SI, "add32.l-imm-G-basic-Unprefixed-dst32-An-indirect-Unprefixed-SI", "add.l", 48,
61000 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61002 /* add.l${G} #${Imm-24-SI},${Dsp-16-u8}[$Dst32AnUnprefixed] */
61004 M32C_INSN_ADD32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-8-Unprefixed-dst32-16-8-An-relative-Unprefixed-SI", "add.l", 56,
61005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61007 /* add.l${G} #${Imm-24-SI},${Dsp-16-u8}[sb] */
61009 M32C_INSN_ADD32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-8-Unprefixed-dst32-16-8-SB-relative-Unprefixed-SI", "add.l", 56,
61010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61012 /* add.l${G} #${Imm-24-SI},${Dsp-16-s8}[fb] */
61014 M32C_INSN_ADD32_L_IMM_G_16_8_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-8-Unprefixed-dst32-16-8-FB-relative-Unprefixed-SI", "add.l", 56,
61015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61017 /* add.l${G} #${Imm-32-SI},${Dsp-16-u16}[$Dst32AnUnprefixed] */
61019 M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-SI", "add.l", 64,
61020 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61022 /* add.l${G} #${Imm-32-SI},${Dsp-16-u16}[sb] */
61024 M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-SI", "add.l", 64,
61025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61027 /* add.l${G} #${Imm-32-SI},${Dsp-16-s16}[fb] */
61029 M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-SI", "add.l", 64,
61030 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61032 /* add.l${G} #${Imm-32-SI},${Dsp-16-u16} */
61034 M32C_INSN_ADD32_L_IMM_G_16_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, "add32.l-imm-G-16-16-Unprefixed-dst32-16-16-absolute-Unprefixed-SI", "add.l", 64,
61035 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61037 /* add.l${G} #${Imm-40-SI},${Dsp-16-u24}[$Dst32AnUnprefixed] */
61039 M32C_INSN_ADD32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, "add32.l-imm-G-16-24-Unprefixed-dst32-16-24-An-relative-Unprefixed-SI", "add.l", 72,
61040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61042 /* add.l${G} #${Imm-40-SI},${Dsp-16-u24} */
61044 M32C_INSN_ADD32_L_IMM_G_16_24_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, "add32.l-imm-G-16-24-Unprefixed-dst32-16-24-absolute-Unprefixed-SI", "add.l", 72,
61045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61047 /* adcf.w $Dst32RnUnprefixedHI */
61049 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "adcf.w", 16,
61050 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61052 /* adcf.w $Dst32AnUnprefixedHI */
61054 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "adcf.w", 16,
61055 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61057 /* adcf.w [$Dst32AnUnprefixed] */
61059 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "adcf.w", 16,
61060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61062 /* adcf.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
61064 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "adcf.w", 24,
61065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61067 /* adcf.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
61069 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "adcf.w", 32,
61070 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61072 /* adcf.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
61074 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "adcf.w", 40,
61075 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61077 /* adcf.w ${Dsp-16-u8}[sb] */
61079 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "adcf.w", 24,
61080 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61082 /* adcf.w ${Dsp-16-u16}[sb] */
61084 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "adcf.w", 32,
61085 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61087 /* adcf.w ${Dsp-16-s8}[fb] */
61089 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "adcf.w", 24,
61090 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61092 /* adcf.w ${Dsp-16-s16}[fb] */
61094 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "adcf.w", 32,
61095 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61097 /* adcf.w ${Dsp-16-u16} */
61099 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "adcf.w", 32,
61100 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61102 /* adcf.w ${Dsp-16-u24} */
61104 M32C_INSN_ADCF32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "adcf32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "adcf.w", 40,
61105 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61107 /* adcf.b $Dst32RnUnprefixedQI */
61109 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "adcf.b", 16,
61110 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61112 /* adcf.b $Dst32AnUnprefixedQI */
61114 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "adcf.b", 16,
61115 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61117 /* adcf.b [$Dst32AnUnprefixed] */
61119 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "adcf.b", 16,
61120 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61122 /* adcf.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
61124 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "adcf.b", 24,
61125 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61127 /* adcf.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
61129 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "adcf.b", 32,
61130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61132 /* adcf.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
61134 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "adcf.b", 40,
61135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61137 /* adcf.b ${Dsp-16-u8}[sb] */
61139 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "adcf.b", 24,
61140 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61142 /* adcf.b ${Dsp-16-u16}[sb] */
61144 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "adcf.b", 32,
61145 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61147 /* adcf.b ${Dsp-16-s8}[fb] */
61149 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "adcf.b", 24,
61150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61152 /* adcf.b ${Dsp-16-s16}[fb] */
61154 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "adcf.b", 32,
61155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61157 /* adcf.b ${Dsp-16-u16} */
61159 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "adcf.b", 32,
61160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61162 /* adcf.b ${Dsp-16-u24} */
61164 M32C_INSN_ADCF32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "adcf32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "adcf.b", 40,
61165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61167 /* adcf.w $Dst16RnHI */
61169 M32C_INSN_ADCF16_W_16_DST16_RN_DIRECT_HI, "adcf16.w-16-dst16-Rn-direct-HI", "adcf.w", 16,
61170 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61172 /* adcf.w $Dst16AnHI */
61174 M32C_INSN_ADCF16_W_16_DST16_AN_DIRECT_HI, "adcf16.w-16-dst16-An-direct-HI", "adcf.w", 16,
61175 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61177 /* adcf.w [$Dst16An] */
61179 M32C_INSN_ADCF16_W_16_DST16_AN_INDIRECT_HI, "adcf16.w-16-dst16-An-indirect-HI", "adcf.w", 16,
61180 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61182 /* adcf.w ${Dsp-16-u8}[$Dst16An] */
61184 M32C_INSN_ADCF16_W_16_DST16_16_8_AN_RELATIVE_HI, "adcf16.w-16-dst16-16-8-An-relative-HI", "adcf.w", 24,
61185 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61187 /* adcf.w ${Dsp-16-u16}[$Dst16An] */
61189 M32C_INSN_ADCF16_W_16_DST16_16_16_AN_RELATIVE_HI, "adcf16.w-16-dst16-16-16-An-relative-HI", "adcf.w", 32,
61190 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61192 /* adcf.w ${Dsp-16-u8}[sb] */
61194 M32C_INSN_ADCF16_W_16_DST16_16_8_SB_RELATIVE_HI, "adcf16.w-16-dst16-16-8-SB-relative-HI", "adcf.w", 24,
61195 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61197 /* adcf.w ${Dsp-16-u16}[sb] */
61199 M32C_INSN_ADCF16_W_16_DST16_16_16_SB_RELATIVE_HI, "adcf16.w-16-dst16-16-16-SB-relative-HI", "adcf.w", 32,
61200 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61202 /* adcf.w ${Dsp-16-s8}[fb] */
61204 M32C_INSN_ADCF16_W_16_DST16_16_8_FB_RELATIVE_HI, "adcf16.w-16-dst16-16-8-FB-relative-HI", "adcf.w", 24,
61205 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61207 /* adcf.w ${Dsp-16-u16} */
61209 M32C_INSN_ADCF16_W_16_DST16_16_16_ABSOLUTE_HI, "adcf16.w-16-dst16-16-16-absolute-HI", "adcf.w", 32,
61210 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61212 /* adcf.b $Dst16RnQI */
61214 M32C_INSN_ADCF16_B_16_DST16_RN_DIRECT_QI, "adcf16.b-16-dst16-Rn-direct-QI", "adcf.b", 16,
61215 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61217 /* adcf.b $Dst16AnQI */
61219 M32C_INSN_ADCF16_B_16_DST16_AN_DIRECT_QI, "adcf16.b-16-dst16-An-direct-QI", "adcf.b", 16,
61220 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61222 /* adcf.b [$Dst16An] */
61224 M32C_INSN_ADCF16_B_16_DST16_AN_INDIRECT_QI, "adcf16.b-16-dst16-An-indirect-QI", "adcf.b", 16,
61225 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61227 /* adcf.b ${Dsp-16-u8}[$Dst16An] */
61229 M32C_INSN_ADCF16_B_16_DST16_16_8_AN_RELATIVE_QI, "adcf16.b-16-dst16-16-8-An-relative-QI", "adcf.b", 24,
61230 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61232 /* adcf.b ${Dsp-16-u16}[$Dst16An] */
61234 M32C_INSN_ADCF16_B_16_DST16_16_16_AN_RELATIVE_QI, "adcf16.b-16-dst16-16-16-An-relative-QI", "adcf.b", 32,
61235 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61237 /* adcf.b ${Dsp-16-u8}[sb] */
61239 M32C_INSN_ADCF16_B_16_DST16_16_8_SB_RELATIVE_QI, "adcf16.b-16-dst16-16-8-SB-relative-QI", "adcf.b", 24,
61240 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61242 /* adcf.b ${Dsp-16-u16}[sb] */
61244 M32C_INSN_ADCF16_B_16_DST16_16_16_SB_RELATIVE_QI, "adcf16.b-16-dst16-16-16-SB-relative-QI", "adcf.b", 32,
61245 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61247 /* adcf.b ${Dsp-16-s8}[fb] */
61249 M32C_INSN_ADCF16_B_16_DST16_16_8_FB_RELATIVE_QI, "adcf16.b-16-dst16-16-8-FB-relative-QI", "adcf.b", 24,
61250 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61252 /* adcf.b ${Dsp-16-u16} */
61254 M32C_INSN_ADCF16_B_16_DST16_16_16_ABSOLUTE_QI, "adcf16.b-16-dst16-16-16-absolute-QI", "adcf.b", 32,
61255 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61257 /* abs.w $Dst32RnUnprefixedHI */
61259 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-Rn-direct-Unprefixed-HI", "abs.w", 16,
61260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61262 /* abs.w $Dst32AnUnprefixedHI */
61264 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-An-direct-Unprefixed-HI", "abs.w", 16,
61265 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61267 /* abs.w [$Dst32AnUnprefixed] */
61269 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-An-indirect-Unprefixed-HI", "abs.w", 16,
61270 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61272 /* abs.w ${Dsp-16-u8}[$Dst32AnUnprefixed] */
61274 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-HI", "abs.w", 24,
61275 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61277 /* abs.w ${Dsp-16-u16}[$Dst32AnUnprefixed] */
61279 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-HI", "abs.w", 32,
61280 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61282 /* abs.w ${Dsp-16-u24}[$Dst32AnUnprefixed] */
61284 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-HI", "abs.w", 40,
61285 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61287 /* abs.w ${Dsp-16-u8}[sb] */
61289 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-HI", "abs.w", 24,
61290 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61292 /* abs.w ${Dsp-16-u16}[sb] */
61294 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-HI", "abs.w", 32,
61295 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61297 /* abs.w ${Dsp-16-s8}[fb] */
61299 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-HI", "abs.w", 24,
61300 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61302 /* abs.w ${Dsp-16-s16}[fb] */
61304 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-HI", "abs.w", 32,
61305 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61307 /* abs.w ${Dsp-16-u16} */
61309 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-16-absolute-Unprefixed-HI", "abs.w", 32,
61310 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61312 /* abs.w ${Dsp-16-u24} */
61314 M32C_INSN_ABS32_W_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, "abs32.w-16-Unprefixed-dst32-16-24-absolute-Unprefixed-HI", "abs.w", 40,
61315 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61317 /* abs.b $Dst32RnUnprefixedQI */
61319 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_RN_DIRECT_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-Rn-direct-Unprefixed-QI", "abs.b", 16,
61320 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61322 /* abs.b $Dst32AnUnprefixedQI */
61324 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_AN_DIRECT_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-An-direct-Unprefixed-QI", "abs.b", 16,
61325 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61327 /* abs.b [$Dst32AnUnprefixed] */
61329 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_AN_INDIRECT_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-An-indirect-Unprefixed-QI", "abs.b", 16,
61330 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61332 /* abs.b ${Dsp-16-u8}[$Dst32AnUnprefixed] */
61334 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-8-An-relative-Unprefixed-QI", "abs.b", 24,
61335 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61337 /* abs.b ${Dsp-16-u16}[$Dst32AnUnprefixed] */
61339 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-16-An-relative-Unprefixed-QI", "abs.b", 32,
61340 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61342 /* abs.b ${Dsp-16-u24}[$Dst32AnUnprefixed] */
61344 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-24-An-relative-Unprefixed-QI", "abs.b", 40,
61345 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61347 /* abs.b ${Dsp-16-u8}[sb] */
61349 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-8-SB-relative-Unprefixed-QI", "abs.b", 24,
61350 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61352 /* abs.b ${Dsp-16-u16}[sb] */
61354 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-16-SB-relative-Unprefixed-QI", "abs.b", 32,
61355 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61357 /* abs.b ${Dsp-16-s8}[fb] */
61359 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-8-FB-relative-Unprefixed-QI", "abs.b", 24,
61360 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61362 /* abs.b ${Dsp-16-s16}[fb] */
61364 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-16-FB-relative-Unprefixed-QI", "abs.b", 32,
61365 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61367 /* abs.b ${Dsp-16-u16} */
61369 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-16-absolute-Unprefixed-QI", "abs.b", 32,
61370 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61372 /* abs.b ${Dsp-16-u24} */
61374 M32C_INSN_ABS32_B_16_UNPREFIXED_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, "abs32.b-16-Unprefixed-dst32-16-24-absolute-Unprefixed-QI", "abs.b", 40,
61375 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61377 /* abs.w $Dst16RnHI */
61379 M32C_INSN_ABS16_W_16_DST16_RN_DIRECT_HI, "abs16.w-16-dst16-Rn-direct-HI", "abs.w", 16,
61380 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61382 /* abs.w $Dst16AnHI */
61384 M32C_INSN_ABS16_W_16_DST16_AN_DIRECT_HI, "abs16.w-16-dst16-An-direct-HI", "abs.w", 16,
61385 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61387 /* abs.w [$Dst16An] */
61389 M32C_INSN_ABS16_W_16_DST16_AN_INDIRECT_HI, "abs16.w-16-dst16-An-indirect-HI", "abs.w", 16,
61390 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61392 /* abs.w ${Dsp-16-u8}[$Dst16An] */
61394 M32C_INSN_ABS16_W_16_DST16_16_8_AN_RELATIVE_HI, "abs16.w-16-dst16-16-8-An-relative-HI", "abs.w", 24,
61395 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61397 /* abs.w ${Dsp-16-u16}[$Dst16An] */
61399 M32C_INSN_ABS16_W_16_DST16_16_16_AN_RELATIVE_HI, "abs16.w-16-dst16-16-16-An-relative-HI", "abs.w", 32,
61400 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61402 /* abs.w ${Dsp-16-u8}[sb] */
61404 M32C_INSN_ABS16_W_16_DST16_16_8_SB_RELATIVE_HI, "abs16.w-16-dst16-16-8-SB-relative-HI", "abs.w", 24,
61405 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61407 /* abs.w ${Dsp-16-u16}[sb] */
61409 M32C_INSN_ABS16_W_16_DST16_16_16_SB_RELATIVE_HI, "abs16.w-16-dst16-16-16-SB-relative-HI", "abs.w", 32,
61410 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61412 /* abs.w ${Dsp-16-s8}[fb] */
61414 M32C_INSN_ABS16_W_16_DST16_16_8_FB_RELATIVE_HI, "abs16.w-16-dst16-16-8-FB-relative-HI", "abs.w", 24,
61415 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61417 /* abs.w ${Dsp-16-u16} */
61419 M32C_INSN_ABS16_W_16_DST16_16_16_ABSOLUTE_HI, "abs16.w-16-dst16-16-16-absolute-HI", "abs.w", 32,
61420 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61422 /* abs.b $Dst16RnQI */
61424 M32C_INSN_ABS16_B_16_DST16_RN_DIRECT_QI, "abs16.b-16-dst16-Rn-direct-QI", "abs.b", 16,
61425 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61427 /* abs.b $Dst16AnQI */
61429 M32C_INSN_ABS16_B_16_DST16_AN_DIRECT_QI, "abs16.b-16-dst16-An-direct-QI", "abs.b", 16,
61430 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61432 /* abs.b [$Dst16An] */
61434 M32C_INSN_ABS16_B_16_DST16_AN_INDIRECT_QI, "abs16.b-16-dst16-An-indirect-QI", "abs.b", 16,
61435 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61437 /* abs.b ${Dsp-16-u8}[$Dst16An] */
61439 M32C_INSN_ABS16_B_16_DST16_16_8_AN_RELATIVE_QI, "abs16.b-16-dst16-16-8-An-relative-QI", "abs.b", 24,
61440 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61442 /* abs.b ${Dsp-16-u16}[$Dst16An] */
61444 M32C_INSN_ABS16_B_16_DST16_16_16_AN_RELATIVE_QI, "abs16.b-16-dst16-16-16-An-relative-QI", "abs.b", 32,
61445 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61447 /* abs.b ${Dsp-16-u8}[sb] */
61449 M32C_INSN_ABS16_B_16_DST16_16_8_SB_RELATIVE_QI, "abs16.b-16-dst16-16-8-SB-relative-QI", "abs.b", 24,
61450 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61452 /* abs.b ${Dsp-16-u16}[sb] */
61454 M32C_INSN_ABS16_B_16_DST16_16_16_SB_RELATIVE_QI, "abs16.b-16-dst16-16-16-SB-relative-QI", "abs.b", 32,
61455 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61457 /* abs.b ${Dsp-16-s8}[fb] */
61459 M32C_INSN_ABS16_B_16_DST16_16_8_FB_RELATIVE_QI, "abs16.b-16-dst16-16-8-FB-relative-QI", "abs.b", 24,
61460 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61462 /* abs.b ${Dsp-16-u16} */
61464 M32C_INSN_ABS16_B_16_DST16_16_16_ABSOLUTE_QI, "abs16.b-16-dst16-16-16-absolute-QI", "abs.b", 32,
61465 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61467 /* add${size}$Q #${Imm-12-s4},sp */
61469 M32C_INSN_ADD16_Q_SP, "add16-Q-sp", "add", 16,
61470 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61472 /* add.b$G #${Imm-16-QI},sp */
61474 M32C_INSN_ADD16_B_G_SP, "add16.b-G-sp", "add.b", 24,
61475 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61477 /* add.w$G #${Imm-16-HI},sp */
61479 M32C_INSN_ADD16_W_G_SP, "add16.w-G-sp", "add.w", 32,
61480 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61482 /* add.l$Q #${Imm3-S},sp */
61484 M32C_INSN_ADD32_L_IMM3_Q, "add32.l-imm3-Q", "add.l", 8,
61485 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61487 /* add.l$S #${Imm-16-QI},sp */
61489 M32C_INSN_ADD32_L_IMM8_S, "add32.l-imm8-S", "add.l", 24,
61490 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61492 /* add.l$G #${Imm-16-HI},sp */
61494 M32C_INSN_ADD32_L_IMM16_G, "add32.l-imm16-G", "add.l", 32,
61495 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61497 /* dadc.b #${Imm-16-QI} */
61499 M32C_INSN_DADC16_B_IMM8, "dadc16.b-imm8", "dadc.b", 24,
61500 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61502 /* dadc.w #${Imm-16-HI} */
61504 M32C_INSN_DADC16_W_IMM16, "dadc16.w-imm16", "dadc.w", 32,
61505 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61507 /* dadc.b r0h,r0l */
61509 M32C_INSN_DADC16_B_R0H_R0L, "dadc16.b-r0h-r0l", "dadc.b", 16,
61510 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61514 M32C_INSN_DADC16_W_R1_R0, "dadc16.w-r1-r0", "dadc.w", 16,
61515 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61517 /* dadd.b #${Imm-16-QI} */
61519 M32C_INSN_DADD16_B_IMM8, "dadd16.b-imm8", "dadd.b", 24,
61520 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61522 /* dadd.w #${Imm-16-HI} */
61524 M32C_INSN_DADD16_W_IMM16, "dadd16.w-imm16", "dadd.w", 32,
61525 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61527 /* dadd.b r0h,r0l */
61529 M32C_INSN_DADD16_B_R0H_R0L, "dadd16.b-r0h-r0l", "dadd.b", 16,
61530 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61534 M32C_INSN_DADD16_W_R1_R0, "dadd16.w-r1-r0", "dadd.w", 16,
61535 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61539 M32C_INSN_BM16_C, "bm16-c", "bm", 16,
61540 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61544 M32C_INSN_BM32_C, "bm32-c", "bm", 16,
61545 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61549 M32C_INSN_BRK16, "brk16", "brk", 8,
61550 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61554 M32C_INSN_BRK32, "brk32", "brk", 8,
61555 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61559 M32C_INSN_BRK232, "brk232", "brk2", 8,
61560 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61562 /* dec.w ${Dst16An-S} */
61564 M32C_INSN_DEC16_W, "dec16.w", "dec.w", 8,
61565 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61567 /* div.b #${Imm-16-QI} */
61569 M32C_INSN_DIV16_B_IMM_16_QI, "div16.b-Imm-16-QI", "div.b", 24,
61570 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61572 /* div.w #${Imm-16-HI} */
61574 M32C_INSN_DIV16_W_IMM_16_HI, "div16.w-Imm-16-HI", "div.w", 32,
61575 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61577 /* div.b #${Imm-16-QI} */
61579 M32C_INSN_DIV32_B_IMM_16_QI, "div32.b-Imm-16-QI", "div.b", 24,
61580 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61582 /* div.w #${Imm-16-HI} */
61584 M32C_INSN_DIV32_W_IMM_16_HI, "div32.w-Imm-16-HI", "div.w", 32,
61585 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61587 /* divu.b #${Imm-16-QI} */
61589 M32C_INSN_DIVU16_B_IMM_16_QI, "divu16.b-Imm-16-QI", "divu.b", 24,
61590 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61592 /* divu.w #${Imm-16-HI} */
61594 M32C_INSN_DIVU16_W_IMM_16_HI, "divu16.w-Imm-16-HI", "divu.w", 32,
61595 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61597 /* divu.b #${Imm-16-QI} */
61599 M32C_INSN_DIVU32_B_IMM_16_QI, "divu32.b-Imm-16-QI", "divu.b", 24,
61600 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61602 /* divu.w #${Imm-16-HI} */
61604 M32C_INSN_DIVU32_W_IMM_16_HI, "divu32.w-Imm-16-HI", "divu.w", 32,
61605 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61607 /* divx.b #${Imm-16-QI} */
61609 M32C_INSN_DIVX16_B_IMM_16_QI, "divx16.b-Imm-16-QI", "divx.b", 24,
61610 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61612 /* divx.w #${Imm-16-HI} */
61614 M32C_INSN_DIVX16_W_IMM_16_HI, "divx16.w-Imm-16-HI", "divx.w", 32,
61615 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61617 /* divx.b #${Imm-16-QI} */
61619 M32C_INSN_DIVX32_B_IMM_16_QI, "divx32.b-Imm-16-QI", "divx.b", 24,
61620 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61622 /* divx.w #${Imm-16-HI} */
61624 M32C_INSN_DIVX32_W_IMM_16_HI, "divx32.w-Imm-16-HI", "divx.w", 32,
61625 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61627 /* dsbb.b #${Imm-16-QI} */
61629 M32C_INSN_DSBB16_B_IMM8, "dsbb16.b-imm8", "dsbb.b", 24,
61630 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61632 /* dsbb.w #${Imm-16-HI} */
61634 M32C_INSN_DSBB16_W_IMM16, "dsbb16.w-imm16", "dsbb.w", 32,
61635 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61637 /* dsbb.b r0h,r0l */
61639 M32C_INSN_DSBB16_B_R0H_R0L, "dsbb16.b-r0h-r0l", "dsbb.b", 16,
61640 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61644 M32C_INSN_DSBB16_W_R1_R0, "dsbb16.w-r1-r0", "dsbb.w", 16,
61645 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61647 /* dsub.b #${Imm-16-QI} */
61649 M32C_INSN_DSUB16_B_IMM8, "dsub16.b-imm8", "dsub.b", 24,
61650 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61652 /* dsub.w #${Imm-16-HI} */
61654 M32C_INSN_DSUB16_W_IMM16, "dsub16.w-imm16", "dsub.w", 32,
61655 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61657 /* dsub.b r0h,r0l */
61659 M32C_INSN_DSUB16_B_R0H_R0L, "dsub16.b-r0h-r0l", "dsub.b", 16,
61660 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61664 M32C_INSN_DSUB16_W_R1_R0, "dsub16.w-r1-r0", "dsub.w", 16,
61665 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61667 /* enter #${Dsp-16-u8} */
61669 M32C_INSN_ENTER16, "enter16", "enter", 24,
61670 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61674 M32C_INSN_EXITD16, "exitd16", "exitd", 16,
61675 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
61677 /* enter #${Dsp-8-u8} */
61679 M32C_INSN_ENTER32, "enter32", "enter", 16,
61680 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61684 M32C_INSN_EXITD32, "exitd32", "exitd", 8,
61685 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
61687 /* fclr ${flags16} */
61689 M32C_INSN_FCLR16, "fclr16", "fclr", 16,
61690 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61692 /* fset ${flags16} */
61694 M32C_INSN_FSET16, "fset16", "fset", 16,
61695 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61697 /* fclr ${flags32} */
61699 M32C_INSN_FCLR, "fclr", "fclr", 16,
61700 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61702 /* fset ${flags32} */
61704 M32C_INSN_FSET, "fset", "fset", 16,
61705 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61707 /* inc.w ${Dst16An-S} */
61709 M32C_INSN_INC16_W, "inc16.w", "inc.w", 8,
61710 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61714 M32C_INSN_FREIT32, "freit32", "freit", 8,
61715 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61717 /* int #${Dsp-10-u6} */
61719 M32C_INSN_INT16, "int16", "int", 16,
61720 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61724 M32C_INSN_INTO16, "into16", "into", 8,
61725 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61727 /* int #${Dsp-8-u6} */
61729 M32C_INSN_INT32, "int32", "int", 16,
61730 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61734 M32C_INSN_INTO32, "into32", "into", 8,
61735 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61737 /* j$cond16j5 ${Lab-8-8} */
61739 M32C_INSN_JCND16_5, "jcnd16-5", "j", 16,
61740 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
61742 /* j$cond16j ${Lab-16-8} */
61744 M32C_INSN_JCND16, "jcnd16", "j", 24,
61745 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
61747 /* j$cond32j ${Lab-8-8} */
61749 M32C_INSN_JCND32, "jcnd32", "j", 16,
61750 { 0|A(COND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
61752 /* jmp.s ${Lab-5-3} */
61754 M32C_INSN_JMP16_S, "jmp16.s", "jmp.s", 8,
61755 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
61757 /* jmp.b ${Lab-8-8} */
61759 M32C_INSN_JMP16_B, "jmp16.b", "jmp.b", 16,
61760 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
61762 /* jmp.w ${Lab-8-16} */
61764 M32C_INSN_JMP16_W, "jmp16.w", "jmp.w", 24,
61765 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
61767 /* jmp.a ${Lab-8-24} */
61769 M32C_INSN_JMP16_A, "jmp16.a", "jmp.a", 32,
61770 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
61772 /* jmps #${Imm-8-QI} */
61774 M32C_INSN_JMPS16, "jmps16", "jmps", 16,
61775 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
61777 /* jmp.s ${Lab32-jmp-s} */
61779 M32C_INSN_JMP32_S, "jmp32.s", "jmp.s", 8,
61780 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
61782 /* jmp.b ${Lab-8-8} */
61784 M32C_INSN_JMP32_B, "jmp32.b", "jmp.b", 16,
61785 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
61787 /* jmp.w ${Lab-8-16} */
61789 M32C_INSN_JMP32_W, "jmp32.w", "jmp.w", 24,
61790 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
61792 /* jmp.a ${Lab-8-24} */
61794 M32C_INSN_JMP32_A, "jmp32.a", "jmp.a", 32,
61795 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
61797 /* jmps #${Imm-8-QI} */
61799 M32C_INSN_JMPS32, "jmps32", "jmps", 16,
61800 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
61802 /* jsr.w ${Lab-8-16} */
61804 M32C_INSN_JSR16_W, "jsr16.w", "jsr.w", 24,
61805 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
61807 /* jsr.a ${Lab-8-24} */
61809 M32C_INSN_JSR16_A, "jsr16.a", "jsr.a", 32,
61810 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
61812 /* jsr.w ${Lab-8-16} */
61814 M32C_INSN_JSR32_W, "jsr32.w", "jsr.w", 24,
61815 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
61817 /* jsr.a ${Lab-8-24} */
61819 M32C_INSN_JSR32_A, "jsr32.a", "jsr.a", 32,
61820 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
61822 /* jsrs #${Imm-8-QI} */
61824 M32C_INSN_JSRS16, "jsrs16", "jsrs", 16,
61825 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
61827 /* jsrs #${Imm-8-QI} */
61829 M32C_INSN_JSRS, "jsrs", "jsrs", 16,
61830 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
61832 /* ldc #${Imm-16-HI},${cr16} */
61834 M32C_INSN_LDC16_IMM16, "ldc16.imm16", "ldc", 32,
61835 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61837 /* ldc #${Imm-16-HI},${cr1-Unprefixed-32} */
61839 M32C_INSN_LDC32_IMM16_CR1, "ldc32.imm16-cr1", "ldc", 32,
61840 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61842 /* ldc #${Dsp-16-u24},${cr2-32} */
61844 M32C_INSN_LDC32_IMM16_CR2, "ldc32.imm16-cr2", "ldc", 40,
61845 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61847 /* ldc #${Dsp-16-u24},${cr3-Unprefixed-32} */
61849 M32C_INSN_LDC32_IMM16_CR3, "ldc32.imm16-cr3", "ldc", 40,
61850 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61852 /* ldctx ${Dsp-16-u16},${Dsp-32-u24} */
61854 M32C_INSN_LDCTX16, "ldctx16", "ldctx", 56,
61855 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61857 /* ldctx ${Dsp-16-u16},${Dsp-32-u24} */
61859 M32C_INSN_LDCTX32, "ldctx32", "ldctx", 56,
61860 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61862 /* stctx ${Dsp-16-u16},${Dsp-32-u24} */
61864 M32C_INSN_STCTX16, "stctx16", "stctx", 56,
61865 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61867 /* stctx ${Dsp-16-u16},${Dsp-32-u24} */
61869 M32C_INSN_STCTX32, "stctx32", "stctx", 56,
61870 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61872 /* ldipl #${Imm-13-u3} */
61874 M32C_INSN_LDIPL16_IMM, "ldipl16.imm", "ldipl", 16,
61875 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61877 /* ldipl #${Imm-13-u3} */
61879 M32C_INSN_LDIPL32_IMM, "ldipl32.imm", "ldipl", 16,
61880 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61882 /* mov.b$S #${Imm-8-QI},a0 */
61884 M32C_INSN_MOV16_B_S_IMM_A0, "mov16.b.S-imm-a0", "mov.b", 16,
61885 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61887 /* mov.b$S #${Imm-8-QI},a1 */
61889 M32C_INSN_MOV16_B_S_IMM_A1, "mov16.b.S-imm-a1", "mov.b", 16,
61890 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61892 /* mov.w$S #${Imm-8-HI},a0 */
61894 M32C_INSN_MOV16_W_S_IMM_A0, "mov16.w.S-imm-a0", "mov.w", 24,
61895 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61897 /* mov.w$S #${Imm-8-HI},a1 */
61899 M32C_INSN_MOV16_W_S_IMM_A1, "mov16.w.S-imm-a1", "mov.w", 24,
61900 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61902 /* mov.w$S #${Imm-8-HI},a0 */
61904 M32C_INSN_MOV32_W_A0, "mov32-w-a0", "mov.w", 24,
61905 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61907 /* mov.w$S #${Imm-8-HI},a1 */
61909 M32C_INSN_MOV32_W_A1, "mov32-w-a1", "mov.w", 24,
61910 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61912 /* mov.l$S #${Dsp-16-u24},a0 */
61914 M32C_INSN_MOV32_L_A0, "mov32-l-a0", "mov.l", 32,
61915 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61917 /* mov.l$S #${Dsp-16-u24},a1 */
61919 M32C_INSN_MOV32_L_A1, "mov32-l-a1", "mov.l", 32,
61920 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61922 /* mov.b$S r0l,a1 */
61924 M32C_INSN_MOV16_B_S_R0L_A1, "mov16.b.S-r0l-a1", "mov.b", 8,
61925 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61927 /* mov.b$S r0h,a0 */
61929 M32C_INSN_MOV16_B_S_R0H_A0, "mov16.b.S-r0h-a0", "mov.b", 8,
61930 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61934 M32C_INSN_NOP16, "nop16", "nop", 8,
61935 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61939 M32C_INSN_NOP32, "nop32", "nop", 8,
61940 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61944 M32C_INSN_POPC16_IMM16, "popc16.imm16", "popc", 16,
61945 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61947 /* popc ${cr1-Unprefixed-32} */
61949 M32C_INSN_POPC32_IMM16_CR1, "popc32.imm16-cr1", "popc", 16,
61950 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61952 /* popc ${cr2-32} */
61954 M32C_INSN_POPC32_IMM16_CR2, "popc32.imm16-cr2", "popc", 16,
61955 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61957 /* pushc ${cr16} */
61959 M32C_INSN_PUSHC16_IMM16, "pushc16.imm16", "pushc", 16,
61960 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61962 /* pushc ${cr1-Unprefixed-32} */
61964 M32C_INSN_PUSHC32_IMM16_CR1, "pushc32.imm16-cr1", "pushc", 16,
61965 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61967 /* pushc ${cr2-32} */
61969 M32C_INSN_PUSHC32_IMM16_CR2, "pushc32.imm16-cr2", "pushc", 16,
61970 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61972 /* popm ${Regsetpop} */
61974 M32C_INSN_POPM16, "popm16", "popm", 16,
61975 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61977 /* pushm ${Regsetpush} */
61979 M32C_INSN_PUSHM16, "pushm16", "pushm", 16,
61980 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61982 /* popm ${Regsetpop} */
61984 M32C_INSN_POPM, "popm", "popm", 16,
61985 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61987 /* pushm ${Regsetpush} */
61989 M32C_INSN_PUSHM, "pushm", "pushm", 16,
61990 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
61992 /* push.b$G #${Imm-16-QI} */
61994 M32C_INSN_PUSH16_B_G_IMM, "push16.b.G-imm", "push.b", 24,
61995 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
61997 /* push.w$G #${Imm-16-HI} */
61999 M32C_INSN_PUSH16_W_G_IMM, "push16.w.G-imm", "push.w", 32,
62000 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62002 /* push.b #Imm-8-QI */
62004 M32C_INSN_PUSH32_B_IMM, "push32.b.imm", "push.b", 16,
62005 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62007 /* push.w #${Imm-8-HI} */
62009 M32C_INSN_PUSH32_W_IMM, "push32.w.imm", "push.w", 24,
62010 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62012 /* push.l #${Imm-16-SI} */
62014 M32C_INSN_PUSH32_L_IMM, "push32.l.imm", "push.l", 48,
62015 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62019 M32C_INSN_REIT16, "reit16", "reit", 8,
62020 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62024 M32C_INSN_REIT32, "reit32", "reit", 8,
62025 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62029 M32C_INSN_RMPA16_B, "rmpa16.b", "rmpa.b", 16,
62030 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62034 M32C_INSN_RMPA16_W, "rmpa16.w", "rmpa.w", 16,
62035 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62039 M32C_INSN_RMPA32_B, "rmpa32.b", "rmpa.b", 16,
62040 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62044 M32C_INSN_RMPA32_W, "rmpa32.w", "rmpa.w", 16,
62045 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62049 M32C_INSN_RTS16, "rts16", "rts", 8,
62050 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M16C) } }
62054 M32C_INSN_RTS32, "rts32", "rts", 8,
62055 { 0|A(UNCOND_CTI), { (1<<MACH_BASE), (1<<ISA_M32C) } }
62059 M32C_INSN_SCMPU_B, "scmpu.b", "scmpu.b", 16,
62060 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62064 M32C_INSN_SCMPU_W, "scmpu.w", "scmpu.w", 16,
62065 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62067 /* sha.l #${Imm-sh-12-s4},r2r0 */
62069 M32C_INSN_SHA16_L_IMM_R2R0, "sha16-L-imm-r2r0", "sha.l", 16,
62070 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62072 /* sha.l #${Imm-sh-12-s4},r3r1 */
62074 M32C_INSN_SHA16_L_IMM_R3R1, "sha16-L-imm-r3r1", "sha.l", 16,
62075 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62077 /* sha.l r1h,r2r0 */
62079 M32C_INSN_SHA16_L_R1H_R2R0, "sha16-L-r1h-r2r0", "sha.l", 16,
62080 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62082 /* sha.l r1h,r3r1 */
62084 M32C_INSN_SHA16_L_R1H_R3R1, "sha16-L-r1h-r3r1", "sha.l", 16,
62085 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62087 /* shl.l #${Imm-sh-12-s4},r2r0 */
62089 M32C_INSN_SHL16_L_IMM_R2R0, "shl16-L-imm-r2r0", "shl.l", 16,
62090 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62092 /* shl.l #${Imm-sh-12-s4},r3r1 */
62094 M32C_INSN_SHL16_L_IMM_R3R1, "shl16-L-imm-r3r1", "shl.l", 16,
62095 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62097 /* shl.l r1h,r2r0 */
62099 M32C_INSN_SHL16_L_R1H_R2R0, "shl16-L-r1h-r2r0", "shl.l", 16,
62100 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62102 /* shl.l r1h,r3r1 */
62104 M32C_INSN_SHL16_L_R1H_R3R1, "shl16-L-r1h-r3r1", "shl.l", 16,
62105 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62109 M32C_INSN_SIN32_B, "sin32.b", "sin.b", 16,
62110 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62114 M32C_INSN_SIN32_W, "sin32.w", "sin.w", 16,
62115 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62119 M32C_INSN_SMOVB16_B, "smovb16.b", "smovb.b", 16,
62120 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62124 M32C_INSN_SMOVB16_W, "smovb16.w", "smovb.w", 16,
62125 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62129 M32C_INSN_SMOVB32_B, "smovb32.b", "smovb.b", 16,
62130 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62134 M32C_INSN_SMOVB32_W, "smovb32.w", "smovb.w", 16,
62135 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62139 M32C_INSN_SMOVF16_B, "smovf16.b", "smovf.b", 16,
62140 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62144 M32C_INSN_SMOVF16_W, "smovf16.w", "smovf.w", 16,
62145 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62149 M32C_INSN_SMOVF32_B, "smovf32.b", "smovf.b", 16,
62150 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62154 M32C_INSN_SMOVF32_W, "smovf32.w", "smovf.w", 16,
62155 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62159 M32C_INSN_SMOVU_B, "smovu.b", "smovu.b", 16,
62160 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62164 M32C_INSN_SMOVU_W, "smovu.w", "smovu.w", 16,
62165 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62169 M32C_INSN_SOUT_B, "sout.b", "sout.b", 16,
62170 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62174 M32C_INSN_SOUT_W, "sout.w", "sout.w", 16,
62175 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62179 M32C_INSN_SSTR16_B, "sstr16.b", "sstr.b", 16,
62180 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62184 M32C_INSN_SSTR16_W, "sstr16.w", "sstr.w", 16,
62185 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62189 M32C_INSN_SSTR_B, "sstr.b", "sstr.b", 16,
62190 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62194 M32C_INSN_SSTR_W, "sstr.w", "sstr.w", 16,
62195 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62197 /* stzx #${Imm-8-QI},#${Imm-16-QI},r0h */
62199 M32C_INSN_STZX16_IMM8_IMM8_R0H, "stzx16-imm8-imm8-r0h", "stzx", 24,
62200 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62202 /* stzx #${Imm-8-QI},#${Imm-16-QI},r0l */
62204 M32C_INSN_STZX16_IMM8_IMM8_R0L, "stzx16-imm8-imm8-r0l", "stzx", 24,
62205 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62207 /* stzx #${Imm-8-QI},#${Imm-16-QI},Dsp-24-u8[sb] */
62209 M32C_INSN_STZX16_IMM8_IMM8_DSP8SB, "stzx16-imm8-imm8-dsp8sb", "stzx", 32,
62210 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62212 /* stzx #${Imm-8-QI},#${Imm-16-QI},Dsp-24-u8[fb] */
62214 M32C_INSN_STZX16_IMM8_IMM8_DSP8FB, "stzx16-imm8-imm8-dsp8fb", "stzx", 32,
62215 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62217 /* stzx #${Imm-8-QI},#${Imm-16-QI},Dsp-24-u16 */
62219 M32C_INSN_STZX16_IMM8_IMM8_ABS16, "stzx16-imm8-imm8-abs16", "stzx", 40,
62220 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62224 M32C_INSN_UND16, "und16", "und", 8,
62225 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62229 M32C_INSN_UND32, "und32", "und", 8,
62230 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62234 M32C_INSN_WAIT16, "wait16", "wait", 16,
62235 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62239 M32C_INSN_WAIT, "wait", "wait", 16,
62240 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62244 M32C_INSN_EXTS16_W_R0, "exts16.w-r0", "exts.w", 16,
62245 { 0, { (1<<MACH_BASE), (1<<ISA_M16C) } }
62249 M32C_INSN_SRCIND, "srcind", "src-indirect", 8,
62250 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62252 /* dest-indirect */
62254 M32C_INSN_DESTIND, "destind", "dest-indirect", 8,
62255 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62257 /* src-dest-indirect */
62259 M32C_INSN_SRCDESTIND, "srcdestind", "src-dest-indirect", 8,
62260 { 0, { (1<<MACH_BASE), (1<<ISA_M32C) } }
62267 /* Initialize anything needed to be done once, before any cpu_open call. */
62268 static void init_tables PARAMS ((void));
62275 static const CGEN_MACH * lookup_mach_via_bfd_name
62276 PARAMS ((const CGEN_MACH *, const char *));
62277 static void build_hw_table PARAMS ((CGEN_CPU_TABLE *));
62278 static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *));
62279 static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
62280 static void build_insn_table PARAMS ((CGEN_CPU_TABLE *));
62281 static void m32c_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
62283 /* Subroutine of m32c_cgen_cpu_open to look up a mach via its bfd name. */
62285 static const CGEN_MACH *
62286 lookup_mach_via_bfd_name (table, name)
62287 const CGEN_MACH *table;
62290 while (table->name)
62292 if (strcmp (name, table->bfd_name) == 0)
62299 /* Subroutine of m32c_cgen_cpu_open to build the hardware table. */
62302 build_hw_table (cd)
62303 CGEN_CPU_TABLE *cd;
62306 int machs = cd->machs;
62307 const CGEN_HW_ENTRY *init = & m32c_cgen_hw_table[0];
62308 /* MAX_HW is only an upper bound on the number of selected entries.
62309 However each entry is indexed by it's enum so there can be holes in
62311 const CGEN_HW_ENTRY **selected =
62312 (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
62314 cd->hw_table.init_entries = init;
62315 cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
62316 memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
62317 /* ??? For now we just use machs to determine which ones we want. */
62318 for (i = 0; init[i].name != NULL; ++i)
62319 if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
62321 selected[init[i].type] = &init[i];
62322 cd->hw_table.entries = selected;
62323 cd->hw_table.num_entries = MAX_HW;
62326 /* Subroutine of m32c_cgen_cpu_open to build the hardware table. */
62329 build_ifield_table (cd)
62330 CGEN_CPU_TABLE *cd;
62332 cd->ifld_table = & m32c_cgen_ifld_table[0];
62335 /* Subroutine of m32c_cgen_cpu_open to build the hardware table. */
62338 build_operand_table (cd)
62339 CGEN_CPU_TABLE *cd;
62342 int machs = cd->machs;
62343 const CGEN_OPERAND *init = & m32c_cgen_operand_table[0];
62344 /* MAX_OPERANDS is only an upper bound on the number of selected entries.
62345 However each entry is indexed by it's enum so there can be holes in
62347 const CGEN_OPERAND **selected =
62348 (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
62350 cd->operand_table.init_entries = init;
62351 cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
62352 memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
62353 /* ??? For now we just use mach to determine which ones we want. */
62354 for (i = 0; init[i].name != NULL; ++i)
62355 if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
62357 selected[init[i].type] = &init[i];
62358 cd->operand_table.entries = selected;
62359 cd->operand_table.num_entries = MAX_OPERANDS;
62362 /* Subroutine of m32c_cgen_cpu_open to build the hardware table.
62363 ??? This could leave out insns not supported by the specified mach/isa,
62364 but that would cause errors like "foo only supported by bar" to become
62365 "unknown insn", so for now we include all insns and require the app to
62366 do the checking later.
62367 ??? On the other hand, parsing of such insns may require their hardware or
62368 operand elements to be in the table [which they mightn't be]. */
62371 build_insn_table (cd)
62372 CGEN_CPU_TABLE *cd;
62375 const CGEN_IBASE *ib = & m32c_cgen_insn_table[0];
62376 CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
62378 memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
62379 for (i = 0; i < MAX_INSNS; ++i)
62380 insns[i].base = &ib[i];
62381 cd->insn_table.init_entries = insns;
62382 cd->insn_table.entry_size = sizeof (CGEN_IBASE);
62383 cd->insn_table.num_init_entries = MAX_INSNS;
62386 /* Subroutine of m32c_cgen_cpu_open to rebuild the tables. */
62389 m32c_cgen_rebuild_tables (cd)
62390 CGEN_CPU_TABLE *cd;
62393 unsigned int isas = cd->isas;
62394 unsigned int machs = cd->machs;
62396 cd->int_insn_p = CGEN_INT_INSN_P;
62398 /* Data derived from the isa spec. */
62399 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
62400 cd->default_insn_bitsize = UNSET;
62401 cd->base_insn_bitsize = UNSET;
62402 cd->min_insn_bitsize = 65535; /* some ridiculously big number */
62403 cd->max_insn_bitsize = 0;
62404 for (i = 0; i < MAX_ISAS; ++i)
62405 if (((1 << i) & isas) != 0)
62407 const CGEN_ISA *isa = & m32c_cgen_isa_table[i];
62409 /* Default insn sizes of all selected isas must be
62410 equal or we set the result to 0, meaning "unknown". */
62411 if (cd->default_insn_bitsize == UNSET)
62412 cd->default_insn_bitsize = isa->default_insn_bitsize;
62413 else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
62416 cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
62418 /* Base insn sizes of all selected isas must be equal
62419 or we set the result to 0, meaning "unknown". */
62420 if (cd->base_insn_bitsize == UNSET)
62421 cd->base_insn_bitsize = isa->base_insn_bitsize;
62422 else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
62425 cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
62427 /* Set min,max insn sizes. */
62428 if (isa->min_insn_bitsize < cd->min_insn_bitsize)
62429 cd->min_insn_bitsize = isa->min_insn_bitsize;
62430 if (isa->max_insn_bitsize > cd->max_insn_bitsize)
62431 cd->max_insn_bitsize = isa->max_insn_bitsize;
62434 /* Data derived from the mach spec. */
62435 for (i = 0; i < MAX_MACHS; ++i)
62436 if (((1 << i) & machs) != 0)
62438 const CGEN_MACH *mach = & m32c_cgen_mach_table[i];
62440 if (mach->insn_chunk_bitsize != 0)
62442 if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
62444 fprintf (stderr, "m32c_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
62445 cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
62449 cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
62453 /* Determine which hw elements are used by MACH. */
62454 build_hw_table (cd);
62456 /* Build the ifield table. */
62457 build_ifield_table (cd);
62459 /* Determine which operands are used by MACH/ISA. */
62460 build_operand_table (cd);
62462 /* Build the instruction table. */
62463 build_insn_table (cd);
62466 /* Initialize a cpu table and return a descriptor.
62467 It's much like opening a file, and must be the first function called.
62468 The arguments are a set of (type/value) pairs, terminated with
62471 Currently supported values:
62472 CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
62473 CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
62474 CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
62475 CGEN_CPU_OPEN_ENDIAN: specify endian choice
62476 CGEN_CPU_OPEN_END: terminates arguments
62478 ??? Simultaneous multiple isas might not make sense, but it's not (yet)
62481 ??? We only support ISO C stdargs here, not K&R.
62482 Laziness, plus experiment to see if anything requires K&R - eventually
62483 K&R will no longer be supported - e.g. GDB is currently trying this. */
62486 m32c_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
62488 CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
62490 unsigned int isas = 0; /* 0 = "unspecified" */
62491 unsigned int machs = 0; /* 0 = "unspecified" */
62492 enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
62501 memset (cd, 0, sizeof (*cd));
62503 va_start (ap, arg_type);
62504 while (arg_type != CGEN_CPU_OPEN_END)
62508 case CGEN_CPU_OPEN_ISAS :
62509 isas = va_arg (ap, unsigned int);
62511 case CGEN_CPU_OPEN_MACHS :
62512 machs = va_arg (ap, unsigned int);
62514 case CGEN_CPU_OPEN_BFDMACH :
62516 const char *name = va_arg (ap, const char *);
62517 const CGEN_MACH *mach =
62518 lookup_mach_via_bfd_name (m32c_cgen_mach_table, name);
62520 machs |= 1 << mach->num;
62523 case CGEN_CPU_OPEN_ENDIAN :
62524 endian = va_arg (ap, enum cgen_endian);
62527 fprintf (stderr, "m32c_cgen_cpu_open: unsupported argument `%d'\n",
62529 abort (); /* ??? return NULL? */
62531 arg_type = va_arg (ap, enum cgen_cpu_open_arg);
62535 /* mach unspecified means "all" */
62537 machs = (1 << MAX_MACHS) - 1;
62538 /* base mach is always selected */
62540 /* isa unspecified means "all" */
62542 isas = (1 << MAX_ISAS) - 1;
62543 if (endian == CGEN_ENDIAN_UNKNOWN)
62545 /* ??? If target has only one, could have a default. */
62546 fprintf (stderr, "m32c_cgen_cpu_open: no endianness specified\n");
62552 cd->endian = endian;
62553 /* FIXME: for the sparc case we can determine insn-endianness statically.
62554 The worry here is where both data and insn endian can be independently
62555 chosen, in which case this function will need another argument.
62556 Actually, will want to allow for more arguments in the future anyway. */
62557 cd->insn_endian = endian;
62559 /* Table (re)builder. */
62560 cd->rebuild_tables = m32c_cgen_rebuild_tables;
62561 m32c_cgen_rebuild_tables (cd);
62563 /* Default to not allowing signed overflow. */
62564 cd->signed_overflow_ok_p = 0;
62566 return (CGEN_CPU_DESC) cd;
62569 /* Cover fn to m32c_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
62570 MACH_NAME is the bfd name of the mach. */
62573 m32c_cgen_cpu_open_1 (mach_name, endian)
62574 const char *mach_name;
62575 enum cgen_endian endian;
62577 return m32c_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
62578 CGEN_CPU_OPEN_ENDIAN, endian,
62579 CGEN_CPU_OPEN_END);
62582 /* Close a cpu table.
62583 ??? This can live in a machine independent file, but there's currently
62584 no place to put this file (there's no libcgen). libopcodes is the wrong
62585 place as some simulator ports use this but they don't use libopcodes. */
62588 m32c_cgen_cpu_close (cd)
62592 const CGEN_INSN *insns;
62594 if (cd->macro_insn_table.init_entries)
62596 insns = cd->macro_insn_table.init_entries;
62597 for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
62599 if (CGEN_INSN_RX ((insns)))
62600 regfree (CGEN_INSN_RX (insns));
62604 if (cd->insn_table.init_entries)
62606 insns = cd->insn_table.init_entries;
62607 for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
62609 if (CGEN_INSN_RX (insns))
62610 regfree (CGEN_INSN_RX (insns));
62616 if (cd->macro_insn_table.init_entries)
62617 free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
62619 if (cd->insn_table.init_entries)
62620 free ((CGEN_INSN *) cd->insn_table.init_entries);
62622 if (cd->hw_table.entries)
62623 free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
62625 if (cd->operand_table.entries)
62626 free ((CGEN_HW_ENTRY *) cd->operand_table.entries);