* mn10300-opc.c (IMM32_HIGH8_MEM): New operand type.
[platform/upstream/binutils.git] / opcodes / m10300-opc.c
1 /* Assemble Matsushita MN10300 instructions.
2    Copyright (C) 1996, 1997 Free Software Foundation, Inc.
3
4 This program is free software; you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation; either version 2 of the License, or
7 (at your option) any later version.
8
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12 GNU General Public License for more details.
13
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
17
18 #include "ansidecl.h"
19 #include "opcode/mn10300.h"
20
21 \f
22 const struct mn10300_operand mn10300_operands[] = {
23 #define UNUSED  0
24   {0, 0, 0}, 
25
26 /* dn register in the first register operand position.  */
27 #define DN0      (UNUSED+1)
28   {2, 0, MN10300_OPERAND_DREG},
29
30 /* dn register in the second register operand position.  */
31 #define DN1      (DN0+1)
32   {2, 2, MN10300_OPERAND_DREG},
33
34 /* dn register in the third register operand position.  */
35 #define DN2      (DN1+1)
36   {2, 4, MN10300_OPERAND_DREG},
37
38 /* dm register in the first register operand position.  */
39 #define DM0      (DN2+1)
40   {2, 0, MN10300_OPERAND_DREG},
41
42 /* dm register in the second register operand position.  */
43 #define DM1      (DM0+1)
44   {2, 2, MN10300_OPERAND_DREG},
45
46 /* dm register in the third register operand position.  */
47 #define DM2      (DM1+1)
48   {2, 4, MN10300_OPERAND_DREG},
49
50 /* an register in the first register operand position.  */
51 #define AN0      (DM2+1)
52   {2, 0, MN10300_OPERAND_AREG},
53
54 /* an register in the second register operand position.  */
55 #define AN1      (AN0+1)
56   {2, 2, MN10300_OPERAND_AREG},
57
58 /* an register in the third register operand position.  */
59 #define AN2      (AN1+1)
60   {2, 4, MN10300_OPERAND_AREG},
61
62 /* am register in the first register operand position.  */
63 #define AM0      (AN2+1)
64   {2, 0, MN10300_OPERAND_AREG},
65
66 /* am register in the second register operand position.  */
67 #define AM1      (AM0+1)
68   {2, 2, MN10300_OPERAND_AREG},
69
70 /* am register in the third register operand position.  */
71 #define AM2      (AM1+1)
72   {2, 4, MN10300_OPERAND_AREG},
73
74 /* 8 bit unsigned immediate which may promote to a 16bit
75    unsigned immediate.  */
76 #define IMM8    (AM2+1)
77   {8, 0, MN10300_OPERAND_PROMOTE},
78
79 /* 16 bit unsigned immediate which may promote to a 32bit
80    unsigned immediate.  */
81 #define IMM16    (IMM8+1)
82   {16, 0, MN10300_OPERAND_PROMOTE},
83
84 /* 16 bit pc-relative immediate which may promote to a 16bit
85    pc-relative immediate.  */
86 #define IMM16_PCREL    (IMM16+1)
87   {16, 0, MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX | MN10300_OPERAND_SIGNED},
88
89 /* 16bit unsigned dispacement in a memory operation which
90    may promote to a 32bit displacement.  */
91 #define IMM16_MEM    (IMM16_PCREL+1)
92   {16, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
93
94 /* 32bit immediate, high 16 bits in the main instruction
95    word, 16bits in the extension word. 
96
97    The "bits" field indicates how many bits are in the
98    main instruction word for MN10300_OPERAND_SPLIT!  */
99 #define IMM32    (IMM16_MEM+1)
100   {16, 0, MN10300_OPERAND_SPLIT},
101
102 /* 32bit pc-relative offset.  */
103 #define IMM32_PCREL    (IMM32+1)
104   {16, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL},
105
106 /* 32bit memory offset.  */
107 #define IMM32_MEM    (IMM32_PCREL+1)
108   {16, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR},
109
110 /* 32bit immediate, high 16 bits in the main instruction
111    word, 16bits in the extension word, low 16bits are left
112    shifted 8 places. 
113
114    The "bits" field indicates how many bits are in the
115    main instruction word for MN10300_OPERAND_SPLIT!  */
116 #define IMM32_LOWSHIFT8    (IMM32_MEM+1)
117   {16, 8, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR},
118
119 /* 32bit immediate, high 24 bits in the main instruction
120    word, 8 in the extension word.
121
122    The "bits" field indicates how many bits are in the
123    main instruction word for MN10300_OPERAND_SPLIT!  */
124 #define IMM32_HIGH24    (IMM32_LOWSHIFT8+1)
125   {24, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL},
126
127 /* 32bit immediate, high 24 bits in the main instruction
128    word, 8 in the extension word, low 8 bits are left
129    shifted 16 places. 
130
131    The "bits" field indicates how many bits are in the
132    main instruction word for MN10300_OPERAND_SPLIT!  */
133 #define IMM32_HIGH24_LOWSHIFT16    (IMM32_HIGH24+1)
134   {24, 16, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL},
135
136 /* Stack pointer.  */
137 #define SP    (IMM32_HIGH24_LOWSHIFT16+1)
138   {8, 0, MN10300_OPERAND_SP},
139
140 /* Processor status word.  */
141 #define PSW    (SP+1)
142   {0, 0, MN10300_OPERAND_PSW},
143
144 /* MDR register.  */
145 #define MDR    (PSW+1)
146   {0, 0, MN10300_OPERAND_MDR},
147
148 /* Index register.  */
149 #define DI (MDR+1)
150   {2, 2, MN10300_OPERAND_DREG},
151
152 /* 8 bit signed displacement, may promote to 16bit signed dispacement.  */
153 #define SD8    (DI+1)
154   {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
155
156 /* 16 bit signed displacement, may promote to 32bit dispacement.  */
157 #define SD16    (SD8+1)
158   {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
159
160 /* 8 bit signed displacement that can not promote.  */
161 #define SD8N    (SD16+1)
162   {8, 0, MN10300_OPERAND_SIGNED},
163
164 /* 8 bit pc-relative displacement.  */
165 #define SD8N_PCREL    (SD8N+1)
166   {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX},
167
168 /* 8 bit signed displacement shifted left 8 bits in the instruction.  */
169 #define SD8N_SHIFT8    (SD8N_PCREL+1)
170   {8, 8, MN10300_OPERAND_SIGNED},
171
172 /* 8 bit signed immediate which may promote to 16bit signed immediate.  */
173 #define SIMM8    (SD8N_SHIFT8+1)
174   {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
175
176 /* 16 bit signed immediate which may promote to 32bit  immediate.  */
177 #define SIMM16    (SIMM8+1)
178   {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
179
180 /* Either an open paren or close paren.  */
181 #define PAREN   (SIMM16+1)
182   {0, 0, MN10300_OPERAND_PAREN}, 
183
184 /* dn register that appears in the first and second register positions.  */
185 #define DN01     (PAREN+1)
186   {2, 0, MN10300_OPERAND_DREG | MN10300_OPERAND_REPEATED},
187
188 /* an register that appears in the first and second register positions.  */
189 #define AN01     (DN01+1)
190   {2, 0, MN10300_OPERAND_AREG | MN10300_OPERAND_REPEATED},
191
192 /* 16bit pc-relative displacement which may promote to 32bit pc-relative
193    displacement.  */
194 #define D16_SHIFT (AN01+1)
195   {16, 8, MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX | MN10300_OPERAND_SIGNED},
196
197 /* 8 bit immediate found in the extension word.  */
198 #define IMM8E    (D16_SHIFT+1)
199   {8, 0, MN10300_OPERAND_EXTENDED},
200
201 /* Register list found in the extension word shifted 8 bits left.  */
202 #define REGSE_SHIFT8    (IMM8E+1)
203   {8, 8, MN10300_OPERAND_EXTENDED | MN10300_OPERAND_REG_LIST},
204
205 /* Register list shifted 8 bits left.  */
206 #define REGS_SHIFT8 (REGSE_SHIFT8 + 1)
207   {8, 8, MN10300_OPERAND_REG_LIST},
208
209 /* Reigster list.  */
210 #define REGS    (REGS_SHIFT8+1)
211   {8, 0, MN10300_OPERAND_REG_LIST},
212
213 /* start-sanitize-am33 */
214 /* UStack pointer.  */
215 #define USP    (REGS+1)
216   {0, 0, MN10300_OPERAND_USP},
217
218 /* SStack pointer.  */
219 #define SSP    (USP+1)
220   {0, 0, MN10300_OPERAND_SSP},
221
222 /* MStack pointer.  */
223 #define MSP    (SSP+1)
224   {0, 0, MN10300_OPERAND_MSP},
225
226 /* PC .  */
227 #define PC    (MSP+1)
228   {0, 0, MN10300_OPERAND_PC},
229
230 /* 4 bit immediate for syscall.  */
231 #define IMM4    (PC+1)
232   {4, 0, 0},
233
234 /* Processor status word.  */
235 #define EPSW    (IMM4+1)
236   {0, 0, MN10300_OPERAND_EPSW},
237
238 /* rn register in the first register operand position.  */
239 #define RN0      (EPSW+1)
240   {4, 0, MN10300_OPERAND_RREG},
241
242 /* rn register in the fourth register operand position.  */
243 #define RN2      (RN0+1)
244   {4, 4, MN10300_OPERAND_RREG},
245
246 /* rm register in the first register operand position.  */
247 #define RM0      (RN2+1)
248   {4, 0, MN10300_OPERAND_RREG},
249
250 /* rm register in the second register operand position.  */
251 #define RM1      (RM0+1)
252   {4, 2, MN10300_OPERAND_RREG},
253
254 /* rm register in the third register operand position.  */
255 #define RM2      (RM1+1)
256   {4, 4, MN10300_OPERAND_RREG},
257
258 #define RN02      (RM2+1)
259   {4, 0, MN10300_OPERAND_RREG | MN10300_OPERAND_REPEATED},
260
261 #define XRN0      (RN02+1)
262   {4, 0, MN10300_OPERAND_XRREG},
263
264 #define XRM2      (XRN0+1)
265   {4, 4, MN10300_OPERAND_XRREG},
266
267 /* + for autoincrement */
268 #define PLUS    (XRM2+1)
269   {0, 0, MN10300_OPERAND_PLUS}, 
270
271 #define XRN02      (PLUS+1)
272   {4, 0, MN10300_OPERAND_XRREG | MN10300_OPERAND_REPEATED},
273
274 /* Ick */
275 #define RD0      (XRN02+1)
276   {4, -8, MN10300_OPERAND_RREG},
277
278 #define RD2      (RD0+1)
279   {4, -4, MN10300_OPERAND_RREG},
280
281 /* 8 unsigned dispacement in a memory operation which
282    may promote to a 32bit displacement.  */
283 #define IMM8_MEM    (RD2+1)
284   {8, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
285
286 /* Index register.  */
287 #define RI (IMM8_MEM+1)
288   {4, 4, MN10300_OPERAND_RREG},
289
290 /* 24 bit signed displacement, may promote to 32bit dispacement.  */
291 #define SD24    (RI+1)
292   {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
293
294 /* 24 bit unsigned immediate which may promote to a 32bit
295    unsigned immediate.  */
296 #define IMM24    (SD24+1)
297   {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE},
298
299 /* 24 bit signed immediate which may promote to a 32bit
300    signed immediate.  */
301 #define SIMM24    (IMM24+1)
302   {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE | MN10300_OPERAND_SIGNED},
303
304 /* 16bit unsigned dispacement in a memory operation which
305    may promote to a 32bit displacement.  */
306 #define IMM24_MEM    (SIMM24+1)
307   {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
308 /* 32bit immediate, high 24 bits in the main instruction
309    word, 8 in the extension word.
310
311    The "bits" field indicates how many bits are in the
312    main instruction word for MN10300_OPERAND_SPLIT!  */
313 #define IMM32_HIGH8    (IMM24_MEM+1)
314   {8, 0, MN10300_OPERAND_SPLIT},
315
316 /* Similarly, but a memory address.  */
317 #define IMM32_HIGH8_MEM  (IMM32_HIGH8+1)
318   {8, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR},
319
320 /* rm register in the seventh register operand position.  */
321 #define RM6      (IMM32_HIGH8_MEM+1)
322   {4, 12, MN10300_OPERAND_RREG},
323
324 /* rm register in the fifth register operand position.  */
325 #define RN4      (RM6+1)
326   {4, 8, MN10300_OPERAND_RREG},
327
328 /* 4 bit immediate for dsp instructions.  */
329 #define IMM4_2    (RN4+1)
330   {4, 4, 0},
331
332 /* 4 bit immediate for dsp instructions.  */
333 #define SIMM4_2    (IMM4_2+1)
334   {4, 4, MN10300_OPERAND_SIGNED},
335
336 /* 4 bit immediate for dsp instructions.  */
337 #define SIMM4_6    (SIMM4_2+1)
338   {4, 12, MN10300_OPERAND_SIGNED},
339 /* end-sanitize-am33 */
340
341 } ; 
342
343 #define MEM(ADDR) PAREN, ADDR, PAREN 
344 #define MEMINC(ADDR) PAREN, ADDR, PLUS, PAREN 
345 #define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN 
346 \f
347 /* The opcode table.
348
349    The format of the opcode table is:
350
351    NAME         OPCODE          MASK            { OPERANDS }
352
353    NAME is the name of the instruction.
354    OPCODE is the instruction opcode.
355    MASK is the opcode mask; this is used to tell the disassembler
356      which bits in the actual opcode must match OPCODE.
357    OPERANDS is the list of operands.
358
359    The disassembler reads the table in order and prints the first
360    instruction which matches, so this table is sorted to put more
361    specific instructions before more general instructions.  It is also
362    sorted by major opcode.  */
363
364 const struct mn10300_opcode mn10300_opcodes[] = {
365 { "mov",        0x8000,         0xf000,         FMT_S1, {SIMM8, DN01}},
366 { "mov",        0x80,           0xf0,           FMT_S0, {DM1, DN0}},
367 { "mov",        0xf1e0,         0xfff0,         FMT_D0, {DM1, AN0}},
368 { "mov",        0xf1d0,         0xfff0,         FMT_D0, {AM1, DN0}},
369 { "mov",        0x9000,         0xf000,         FMT_S1, {IMM8, AN01}},
370 { "mov",        0x90,           0xf0,           FMT_S0, {AM1, AN0}},
371 { "mov",        0x3c,           0xfc,           FMT_S0, {SP, AN0}},
372 { "mov",        0xf2f0,         0xfff3,         FMT_D0, {AM1, SP}},
373 { "mov",        0xf2e4,         0xfffc,         FMT_D0, {PSW, DN0}},
374 { "mov",        0xf2f3,         0xfff3,         FMT_D0, {DM1, PSW}},
375 { "mov",        0xf2e0,         0xfffc,         FMT_D0, {MDR, DN0}},
376 { "mov",        0xf2f2,         0xfff3,         FMT_D0, {DM1, MDR}},
377 { "mov",        0x70,           0xf0,           FMT_S0, {MEM(AM0), DN1}},
378 { "mov",        0x5800,         0xfcff,         FMT_S1, {MEM(SP), DN0}},
379 { "mov",        0x300000,       0xfc0000,       FMT_S2, {MEM(IMM16_MEM), DN0}},
380 { "mov",        0xfca40000,     0xfffc0000,     FMT_D4, {MEM(IMM32_MEM), DN0}},
381 { "mov",        0xf000,         0xfff0,         FMT_D0, {MEM(AM0), AN1}},
382 { "mov",        0x5c00,         0xfcff,         FMT_S1, {MEM(SP), AN0}},
383 { "mov",        0xfaa00000,     0xfffc0000,     FMT_D2, {MEM(IMM16_MEM), AN0}},
384 { "mov",        0xfca00000,     0xfffc0000,     FMT_D4, {MEM(IMM32_MEM), AN0}},
385 { "mov",        0x60,           0xf0,           FMT_S0, {DM1, MEM(AN0)}},
386 { "mov",        0x4200,         0xf3ff,         FMT_S1, {DM1, MEM(SP)}},
387 { "mov",        0x010000,       0xf30000,       FMT_S2, {DM1, MEM(IMM16_MEM)}},
388 { "mov",        0xfc810000,     0xfff30000,     FMT_D4, {DM1, MEM(IMM32_MEM)}},
389 { "mov",        0xf010,         0xfff0,         FMT_D0, {AM1, MEM(AN0)}},
390 { "mov",        0x4300,         0xf3ff,         FMT_S1, {AM1, MEM(SP)}},
391 { "mov",        0xfa800000,     0xfff30000,     FMT_D2, {AM1, MEM(IMM16_MEM)}},
392 { "mov",        0xfc800000,     0xfff30000,     FMT_D4, {AM1, MEM(IMM32_MEM)}},
393 { "mov",        0x5c00,         0xfc00,         FMT_S1, {MEM2(IMM8, SP), AN0}},
394 { "mov",        0xf80000,       0xfff000,       FMT_D1, {MEM2(SD8, AM0), DN1}},
395 { "mov",        0xfa000000,     0xfff00000,     FMT_D2, {MEM2(SD16, AM0), DN1}},
396 { "mov",        0xfc000000,     0xfff00000,     FMT_D4, {MEM2(IMM32,AM0), DN1}},
397 { "mov",        0x5800,         0xfc00,         FMT_S1, {MEM2(IMM8, SP), DN0}},
398 { "mov",        0xfab40000,     0xfffc0000,     FMT_D2, {MEM2(IMM16, SP), DN0}},
399 { "mov",        0xfcb40000,     0xfffc0000,     FMT_D4, {MEM2(IMM32, SP), DN0}},
400 { "mov",        0xf300,         0xffc0,         FMT_D0, {MEM2(DI, AM0), DN2}},
401 { "mov",        0xf82000,       0xfff000,       FMT_D1, {MEM2(SD8,AM0), AN1}},
402 { "mov",        0xfa200000,     0xfff00000,     FMT_D2, {MEM2(SD16, AM0), AN1}},
403 { "mov",        0xfc200000,     0xfff00000,     FMT_D4, {MEM2(IMM32,AM0), AN1}},
404 { "mov",        0xfab00000,     0xfffc0000,     FMT_D2, {MEM2(IMM16, SP), AN0}},
405 { "mov",        0xfcb00000,     0xfffc0000,     FMT_D4, {MEM2(IMM32, SP), AN0}},
406 { "mov",        0xf380,         0xffc0,         FMT_D0, {MEM2(DI, AM0), AN2}},
407 { "mov",        0x4300,         0xf300,         FMT_S1, {AM1, MEM2(IMM8, SP)}},
408 { "mov",        0xf81000,       0xfff000,       FMT_D1, {DM1, MEM2(SD8, AN0)}},
409 { "mov",        0xfa100000,     0xfff00000,     FMT_D2, {DM1, MEM2(SD16, AN0)}},
410 { "mov",        0xfc100000,     0xfff00000,     FMT_D4, {DM1, MEM2(IMM32,AN0)}},
411 { "mov",        0x4200,         0xf300,         FMT_S1, {DM1, MEM2(IMM8, SP)}},
412 { "mov",        0xfa910000,     0xfff30000,     FMT_D2, {DM1, MEM2(IMM16, SP)}},
413 { "mov",        0xfc910000,     0xfff30000,     FMT_D4, {DM1, MEM2(IMM32, SP)}},
414 { "mov",        0xf340,         0xffc0,         FMT_D0, {DM2, MEM2(DI, AN0)}},
415 { "mov",        0xf83000,       0xfff000,       FMT_D1, {AM1, MEM2(SD8, AN0)}},
416 { "mov",        0xfa300000,     0xfff00000,     FMT_D2, {AM1, MEM2(SD16, AN0)}},
417 { "mov",        0xfc300000,     0xfff00000,     FMT_D4, {AM1, MEM2(IMM32,AN0)}},
418 { "mov",        0xfa900000,     0xfff30000,     FMT_D2, {AM1, MEM2(IMM16, SP)}},
419 { "mov",        0xfc900000,     0xfff30000,     FMT_D4, {AM1, MEM2(IMM32, SP)}},
420 { "mov",        0xf3c0,         0xffc0,         FMT_D0, {AM2, MEM2(DI, AN0)}},
421
422 /* start-sanitize-am33 */
423 { "mov",        0xf020,         0xfffc,         FMT_D0, {USP, AN0}},
424 { "mov",        0xf024,         0xfffc,         FMT_D0, {SSP, AN0}},
425 { "mov",        0xf028,         0xfffc,         FMT_D0, {MSP, AN0}},
426 { "mov",        0xf02c,         0xfffc,         FMT_D0, {PC, AN0}},
427 { "mov",        0xf030,         0xfff3,         FMT_D0, {AN1, USP}},
428 { "mov",        0xf031,         0xfff3,         FMT_D0, {AN1, SSP}},
429 { "mov",        0xf032,         0xfff3,         FMT_D0, {AN1, MSP}},
430 { "mov",        0xf2ec,         0xfffc,         FMT_D0, {EPSW, DN0}},
431 { "mov",        0xf2f1,         0xfff3,         FMT_D0, {DM1, EPSW}},
432 { "mov",        0xf500,         0xffc0,         FMT_D0, {AM2, RN0}},
433 { "mov",        0xf540,         0xffc0,         FMT_D0, {DM2, RN0}},
434 { "mov",        0xf580,         0xffc0,         FMT_D0, {RM1, AN0}},
435 { "mov",        0xf5c0,         0xffc0,         FMT_D0, {RM1, DN0}},
436 { "mov",        0xf90800,       0xffff00,       FMT_D6, {RM2, RN0}},
437 { "mov",        0xf9e800,       0xffff00,       FMT_D6, {XRM2, RN0}},
438 { "mov",        0xf9f800,       0xffff00,       FMT_D6, {RM2, XRN0}},
439 { "mov",        0xf90a00,       0xffff00,       FMT_D6, {MEM(RM0), RN2}},
440 { "mov",        0xf98a00,       0xffff0f,       FMT_D6, {MEM(SP), RN2}},
441 { "mov",        0xf96a00,       0xffff00,       FMT_D6, {MEMINC(RM0), RN2}},
442 { "mov",        0xfb0e0000,     0xffff0f00,     FMT_D7, {MEM(IMM8_MEM), RN2}},
443 { "mov",        0xfd0e0000,     0xffff0f00,     FMT_D8, {MEM(IMM24_MEM), RN2}},
444 { "mov",        0xfe0e0000,     0xffff0f00,     FMT_D9, {MEM(IMM32_HIGH8_MEM),
445                                                          RN2}},
446 { "mov",        0xf91a00,       0xffff00,       FMT_D6, {RM2, MEM(RN0)}},
447 { "mov",        0xf99a00,       0xffff0f,       FMT_D6, {RM2, MEM(SP)}},
448 { "mov",        0xf97a00,       0xffff00,       FMT_D6, {RM2, MEMINC(RN0)}},
449 { "mov",        0xfb1e0000,     0xffff0f00,     FMT_D7, {RM2, MEM(IMM8_MEM)}},
450 { "mov",        0xfd1e0000,     0xffff0f00,     FMT_D8, {RM2, MEM(IMM24_MEM)}},
451 { "mov",        0xfe1e0000,     0xffff0f00,     FMT_D9, {RM2,
452                                                          MEM(IMM32_HIGH8_MEM)}},
453 { "mov",        0xfb0a0000,     0xffff0000,     FMT_D7, {MEM2(SD8, RM0), RN2}},
454 { "mov",        0xfd0a0000,     0xffff0000,     FMT_D8, {MEM2(SD24, RM0), RN2}},
455 { "mov",        0xfe0a0000,     0xffff0000,     FMT_D9, {MEM2(IMM32_HIGH8,RM0), RN2}},
456 { "mov",        0xfb8e0000,     0xffff000f,     FMT_D7, {MEM2(RI, RM0), RD2}},
457 { "mov",        0xfb1a0000,     0xffff0000,     FMT_D7, {RM2, MEM2(SD8, RN0)}},
458 { "mov",        0xfd1a0000,     0xffff0000,     FMT_D8, {RM2, MEM2(SD24, RN0)}},
459 { "mov",        0xfe1a0000,     0xffff0000,     FMT_D9, {RM2, MEM2(IMM32_HIGH8,RN0)}},
460 { "mov",        0xfb8a0000,     0xffff0f00,     FMT_D7, {MEM2(SD8, SP), RN2}},
461 { "mov",        0xfd8a0000,     0xffff0f00,     FMT_D8, {MEM2(SD24, SP), RN2}},
462 { "mov",        0xfe8a0000,     0xffff0f00,     FMT_D9, {MEM2(IMM32_HIGH8, SP), RN2}},
463 { "mov",        0xfb9a0000,     0xffff0f00,     FMT_D7, {RM2, MEM2(SD8, SP)}},
464 { "mov",        0xfd9a0000,     0xffff0f00,     FMT_D8, {RM2, MEM2(SD24, SP)}},
465 { "mov",        0xfe9a0000,     0xffff0f00,     FMT_D9, {RM2, MEM2(IMM32_HIGH8, SP)}},
466 { "mov",        0xfb9e0000,     0xffff000f,     FMT_D7, {RD2, MEM2(RI, RN0)}},
467 /* end-sanitize-am33 */
468 /* These must come after most of the other move instructions to avoid matching
469    a symbolic name with IMMxx operands.  Ugh.  */
470 { "mov",        0x2c0000,       0xfc0000,       FMT_S2, {SIMM16, DN0}},
471 { "mov",        0xfccc0000,     0xfffc0000,     FMT_D4, {IMM32, DN0}},
472 { "mov",        0x240000,       0xfc0000,       FMT_S2, {IMM16, AN0}},
473 { "mov",        0xfcdc0000,     0xfffc0000,     FMT_D4, {IMM32, AN0}},
474 /* These non-promoting variants need to come after all the other memory
475    moves.  */
476 { "mov",        0xf8f000,       0xfffc00,       FMT_D1, {MEM2(SD8N, AM0), SP}},
477 { "mov",        0xf8f400,       0xfffc00,       FMT_D1, {SP, MEM2(SD8N, AN0)}},
478 /* start-sanitize-am33 */
479 /* These must come last so that we favor shorter move instructions for
480    loading immediates into d0-d3/a0-a3.  */
481 { "mov",        0xfb080000,     0xffff0000,     FMT_D7, {SIMM8, RN02}},
482 { "mov",        0xfd080000,     0xffff0000,     FMT_D8, {SIMM24, RN02}},
483 { "mov",        0xfe080000,     0xffff0000,     FMT_D9, {IMM32_HIGH8, RN02}},
484 { "mov",        0xfbf80000,     0xffff0000,     FMT_D7, {SIMM8, XRN02}},
485 { "mov",        0xfdf80000,     0xffff0000,     FMT_D8, {SIMM24, XRN02}},
486 { "mov",        0xfef80000,     0xffff0000,     FMT_D9, {IMM32_HIGH8, XRN02}},
487 /* end-sanitize-am33 */
488
489 /* start-sanitize-am33 */
490 { "movu",       0xfb180000,     0xffff0000,     FMT_D7, {IMM8, RN02}},
491 { "movu",       0xfd180000,     0xffff0000,     FMT_D8, {IMM24, RN02}},
492 { "movu",       0xfe180000,     0xffff0000,     FMT_D9, {IMM32_HIGH8, RN02}},
493 /* end-sanitize-am33 */
494
495 /* start-sanitize-am33 */
496 { "mcst9",      0xf630,         0xfff0,         FMT_D0, {DN01}},
497 { "mcst48",     0xf660,         0xfff0,         FMT_D0, {DN01}},
498 { "swap",       0xf680,         0xfff0,         FMT_D0, {DM1, DN0}},
499 { "swap",       0xf9cb00,       0xffff00,       FMT_D6, {RM2, RN0}},
500 { "swaph",      0xf690,         0xfff0,         FMT_D0, {DM1, DN0}},
501 { "swaph",      0xf9db00,       0xffff00,       FMT_D6, {RM2, RN0}},
502 { "getchx",     0xf6c0,         0xfff0,         FMT_D0, {DN01}},
503 { "getclx",     0xf6d0,         0xfff0,         FMT_D0, {DN01}},
504 { "mac",        0xfb0f0000,     0xffff0000,     FMT_D7, {RM2, RN0, RD2, RD0}},
505 { "mac",        0xf90b00,       0xffff00,       FMT_D6, {RM2, RN0}},
506 { "mac",        0xfb0b0000,     0xffff0000,     FMT_D7, {SIMM8, RN02}},
507 { "mac",        0xfd0b0000,     0xffff0000,     FMT_D8, {SIMM24, RN02}},
508 { "mac",        0xfe0b0000,     0xffff0000,     FMT_D9, {IMM32_HIGH8, RN02}},
509 { "macu",       0xfb1f0000,     0xffff0000,     FMT_D7, {RM2, RN0, RD2, RD0}},
510 { "macu",       0xf91b00,       0xffff00,       FMT_D6, {RM2, RN0}},
511 { "macu",       0xfb1b0000,     0xffff0000,     FMT_D7, {IMM8, RN02}},
512 { "macu",       0xfd1b0000,     0xffff0000,     FMT_D8, {IMM24, RN02}},
513 { "macu",       0xfe1b0000,     0xffff0000,     FMT_D9, {IMM32_HIGH8, RN02}},
514 { "macb",       0xfb2f0000,     0xffff000f,     FMT_D7, {RM2, RN0, RD2}},
515 { "macb",       0xf92b00,       0xffff00,       FMT_D6, {RM2, RN0}},
516 { "macb",       0xfb2b0000,     0xffff0000,     FMT_D7, {SIMM8, RN02}},
517 { "macb",       0xfd2b0000,     0xffff0000,     FMT_D8, {SIMM24, RN02}},
518 { "macb",       0xfe2b0000,     0xffff0000,     FMT_D9, {IMM32_HIGH8, RN02}},
519 { "macbu",      0xfb3f0000,     0xffff000f,     FMT_D7, {RM2, RN0, RD2}},
520 { "macbu",      0xf93b00,       0xffff00,       FMT_D6, {RM2, RN0}},
521 { "macbu",      0xfb3b0000,     0xffff0000,     FMT_D7, {IMM8, RN02}},
522 { "macbu",      0xfd3b0000,     0xffff0000,     FMT_D8, {IMM24, RN02}},
523 { "macbu",      0xfe3b0000,     0xffff0000,     FMT_D9, {IMM32_HIGH8, RN02}},
524 { "mach",       0xfb4f0000,     0xffff0000,     FMT_D7, {RM2, RN0, RD2, RD0}},
525 { "mach",       0xf94b00,       0xffff00,       FMT_D6, {RM2, RN0}},
526 { "mach",       0xfb4b0000,     0xffff0000,     FMT_D7, {SIMM8, RN02}},
527 { "mach",       0xfd4b0000,     0xffff0000,     FMT_D8, {SIMM24, RN02}},
528 { "mach",       0xfe4b0000,     0xffff0000,     FMT_D9, {IMM32_HIGH8, RN02}},
529 { "machu",      0xfb5f0000,     0xffff0000,     FMT_D7, {RM2, RN0, RD2, RD0}},
530 { "machu",      0xf95b00,       0xffff00,       FMT_D6, {RM2, RN0}},
531 { "machu",      0xfb5b0000,     0xffff0000,     FMT_D7, {IMM8, RN02}},
532 { "machu",      0xfd5b0000,     0xffff0000,     FMT_D8, {IMM24, RN02}},
533 { "machu",      0xfe5b0000,     0xffff0000,     FMT_D9, {IMM32_HIGH8, RN02}},
534 { "dmach",      0xfb6f0000,     0xffff000f,     FMT_D7, {RM2, RN0, RD2}},
535 { "dmach",      0xf96b00,       0xffff00,       FMT_D6, {RM2, RN0}},
536 { "dmach",      0xfe6b0000,     0xffff0000,     FMT_D9, {IMM32_HIGH8, RN02}},
537 { "dmachu",     0xfb7f0000,     0xffff000f,     FMT_D7, {RM2, RN0, RD2}},
538 { "dmachu",     0xf97b00,       0xffff00,       FMT_D6, {RM2, RN0}},
539 { "dmachu",     0xfe7b0000,     0xffff0000,     FMT_D9, {IMM32_HIGH8, RN02}},
540 { "dmulh",      0xfb8f0000,     0xffff0000,     FMT_D7, {RM2, RN0, RD2, RD0}},
541 { "dmulh",      0xf98b00,       0xffff00,       FMT_D6, {RM2, RN0}},
542 { "dmulh",      0xfe8b0000,     0xffff0000,     FMT_D9, {IMM32_HIGH8, RN02}},
543 { "dmulhu",     0xfb9f0000,     0xffff0000,     FMT_D7, {RM2, RN0, RD2, RD0}},
544 { "dmulhu",     0xf99b00,       0xffff00,       FMT_D6, {RM2, RN0}},
545 { "dmulhu",     0xfe9b0000,     0xffff0000,     FMT_D9, {IMM32_HIGH8, RN02}},
546 { "mcste",      0xf9bb00,       0xffff00,       FMT_D6, {RM2, RN0}},
547 { "mcste",      0xfbbb0000,     0xffff0000,     FMT_D7, {IMM8, RN02}},
548 { "swhw",       0xf9eb00,       0xffff00,       FMT_D6, {RM2, RN0}},
549 /* end-sanitize-am33 */
550
551 { "movbu",      0xf040,         0xfff0,         FMT_D0, {MEM(AM0), DN1}},
552 { "movbu",      0xf84000,       0xfff000,       FMT_D1, {MEM2(SD8, AM0), DN1}},
553 { "movbu",      0xfa400000,     0xfff00000,     FMT_D2, {MEM2(SD16, AM0), DN1}},
554 { "movbu",      0xfc400000,     0xfff00000,     FMT_D4, {MEM2(IMM32,AM0), DN1}},
555 { "movbu",      0xf8b800,       0xfffcff,       FMT_D1, {MEM(SP), DN0}},
556 { "movbu",      0xf8b800,       0xfffc00,       FMT_D1, {MEM2(IMM8, SP), DN0}},
557 { "movbu",      0xfab80000,     0xfffc0000,     FMT_D2, {MEM2(IMM16, SP), DN0}},
558 { "movbu",      0xfcb80000,     0xfffc0000,     FMT_D4, {MEM2(IMM32, SP), DN0}},
559 { "movbu",      0xf400,         0xffc0,         FMT_D0, {MEM2(DI, AM0), DN2}},
560 { "movbu",      0x340000,       0xfc0000,       FMT_S2, {MEM(IMM16_MEM), DN0}},
561 { "movbu",      0xfca80000,     0xfffc0000,     FMT_D4, {MEM(IMM32_MEM), DN0}},
562 { "movbu",      0xf050,         0xfff0,         FMT_D0, {DM1, MEM(AN0)}},
563 { "movbu",      0xf85000,       0xfff000,       FMT_D1, {DM1, MEM2(SD8, AN0)}},
564 { "movbu",      0xfa500000,     0xfff00000,     FMT_D2, {DM1, MEM2(SD16, AN0)}},
565 { "movbu",      0xfc500000,     0xfff00000,     FMT_D4, {DM1, MEM2(IMM32,AN0)}},
566 { "movbu",      0xf89200,       0xfff3ff,       FMT_D1, {DM1, MEM(SP)}},
567 { "movbu",      0xf89200,       0xfff300,       FMT_D1, {DM1, MEM2(IMM8, SP)}},
568 { "movbu",      0xfa920000,     0xfff30000,     FMT_D2, {DM1, MEM2(IMM16, SP)}},
569 { "movbu",      0xfc920000,     0xfff30000,     FMT_D4, {DM1, MEM2(IMM32, SP)}},
570 { "movbu",      0xf440,         0xffc0,         FMT_D0, {DM2, MEM2(DI, AN0)}},
571 { "movbu",      0x020000,       0xf30000,       FMT_S2, {DM1, MEM(IMM16_MEM)}},
572 { "movbu",      0xfc820000,     0xfff30000,     FMT_D4, {DM1, MEM(IMM32_MEM)}},
573 /* start-sanitize-am33 */
574 { "movbu",      0xf92a00,       0xffff00,       FMT_D6, {MEM(RM0), RN2}},
575 { "movbu",      0xf93a00,       0xffff00,       FMT_D6, {RM2, MEM(RN0)}},
576 { "movbu",      0xf9aa00,       0xffff0f,       FMT_D6, {MEM(SP), RN2}},
577 { "movbu",      0xf9ba00,       0xffff0f,       FMT_D6, {RM2, MEM(SP)}},
578 { "movbu",      0xfb2a0000,     0xffff0000,     FMT_D7, {MEM2(SD8, RM0), RN2}},
579 { "movbu",      0xfd2a0000,     0xffff0000,     FMT_D8, {MEM2(SD24, RM0), RN2}},
580 { "movbu",      0xfe2a0000,     0xffff0000,     FMT_D9, {MEM2(IMM32_HIGH8,RM0), RN2}},
581 { "movbu",      0xfb3a0000,     0xffff0000,     FMT_D7, {RM2, MEM2(SD8, RN0)}},
582 { "movbu",      0xfd3a0000,     0xffff0000,     FMT_D8, {RM2, MEM2(SD24, RN0)}},
583 { "movbu",      0xfe3a0000,     0xffff0000,     FMT_D9, {RM2, MEM2(IMM32_HIGH8,RN0)}},
584 { "movbu",      0xfbaa0000,     0xffff0f00,     FMT_D7, {MEM2(SD8, SP), RN2}},
585 { "movbu",      0xfdaa0000,     0xffff0f00,     FMT_D8, {MEM2(SD24, SP), RN2}},
586 { "movbu",      0xfeaa0000,     0xffff0f00,     FMT_D9, {MEM2(IMM32_HIGH8,SP), RN2}},
587 { "movbu",      0xfbba0000,     0xffff0f00,     FMT_D7, {RM2, MEM2(SD8, SP)}},
588 { "movbu",      0xfdba0000,     0xffff0f00,     FMT_D8, {RM2, MEM2(SD24, SP)}},
589 { "movbu",      0xfeba0000,     0xffff0f00,     FMT_D9, {RM2, MEM2(IMM32_HIGH8, SP)}},
590 { "movbu",      0xfb2e0000,     0xffff0f00,     FMT_D7, {MEM(IMM8_MEM), RN2}},
591 { "movbu",      0xfd2e0000,     0xffff0f00,     FMT_D8, {MEM(IMM24_MEM), RN2}},
592 { "movbu",      0xfe2e0000,     0xffff0f00,     FMT_D9, {MEM(IMM32_HIGH8_MEM),
593                                                          RN2}},
594 { "movbu",      0xfb3e0000,     0xffff0f00,     FMT_D7, {RM2, MEM(IMM8_MEM)}},
595 { "movbu",      0xfd3e0000,     0xffff0f00,     FMT_D8, {RM2, MEM(IMM24_MEM)}},
596 { "movbu",      0xfe3e0000,     0xffff0f00,     FMT_D9, {RM2,
597                                                          MEM(IMM32_HIGH8_MEM)}},
598 { "movbu",      0xfbae0000,     0xffff000f,     FMT_D7, {MEM2(RI, RM0), RD2}},
599 { "movbu",      0xfbbe0000,     0xffff000f,     FMT_D7, {RD2, MEM2(RI, RN0)}},
600 /* end-sanitize-am33 */
601
602 { "movhu",      0xf060,         0xfff0,         FMT_D0, {MEM(AM0), DN1}},
603 { "movhu",      0xf86000,       0xfff000,       FMT_D1, {MEM2(SD8, AM0), DN1}},
604 { "movhu",      0xfa600000,     0xfff00000,     FMT_D2, {MEM2(SD16, AM0), DN1}},
605 { "movhu",      0xfc600000,     0xfff00000,     FMT_D4, {MEM2(IMM32,AM0), DN1}},
606 { "movhu",      0xf8bc00,       0xfffcff,       FMT_D1, {MEM(SP), DN0}},
607 { "movhu",      0xf8bc00,       0xfffc00,       FMT_D1, {MEM2(IMM8, SP), DN0}},
608 { "movhu",      0xfabc0000,     0xfffc0000,     FMT_D2, {MEM2(IMM16, SP), DN0}},
609 { "movhu",      0xfcbc0000,     0xfffc0000,     FMT_D4, {MEM2(IMM32, SP), DN0}},
610 { "movhu",      0xf480,         0xffc0,         FMT_D0, {MEM2(DI, AM0), DN2}},
611 { "movhu",      0x380000,       0xfc0000,       FMT_S2, {MEM(IMM16_MEM), DN0}},
612 { "movhu",      0xfcac0000,     0xfffc0000,     FMT_D4, {MEM(IMM32_MEM), DN0}},
613 { "movhu",      0xf070,         0xfff0,         FMT_D0, {DM1, MEM(AN0)}},
614 { "movhu",      0xf87000,       0xfff000,       FMT_D1, {DM1, MEM2(SD8, AN0)}},
615 { "movhu",      0xfa700000,     0xfff00000,     FMT_D2, {DM1, MEM2(SD16, AN0)}},
616 { "movhu",      0xfc700000,     0xfff00000,     FMT_D4, {DM1, MEM2(IMM32,AN0)}},
617 { "movhu",      0xf89300,       0xfff3ff,       FMT_D1, {DM1, MEM(SP)}},
618 { "movhu",      0xf89300,       0xfff300,       FMT_D1, {DM1, MEM2(IMM8, SP)}},
619 { "movhu",      0xfa930000,     0xfff30000,     FMT_D2, {DM1, MEM2(IMM16, SP)}},
620 { "movhu",      0xfc930000,     0xfff30000,     FMT_D4, {DM1, MEM2(IMM32, SP)}},
621 { "movhu",      0xf4c0,         0xffc0,         FMT_D0, {DM2, MEM2(DI, AN0)}},
622 { "movhu",      0x030000,       0xf30000,       FMT_S2, {DM1, MEM(IMM16_MEM)}},
623 { "movhu",      0xfc830000,     0xfff30000,     FMT_D4, {DM1, MEM(IMM32_MEM)}},
624 /* start-sanitize-am33 */
625 { "movhu",      0xf94a00,       0xffff00,       FMT_D6, {MEM(RM0), RN2}},
626 { "movhu",      0xf95a00,       0xffff00,       FMT_D6, {RM2, MEM(RN0)}},
627 { "movhu",      0xf9ca00,       0xffff0f,       FMT_D6, {MEM(SP), RN2}},
628 { "movhu",      0xf9da00,       0xffff0f,       FMT_D6, {RM2, MEM(SP)}},
629 { "movhu",      0xf9ea00,       0xffff00,       FMT_D6, {MEMINC(RM0), RN2}},
630 { "movhu",      0xf9fa00,       0xffff00,       FMT_D6, {RM2, MEMINC(RN0)}},
631 { "movhu",      0xfb4a0000,     0xffff0000,     FMT_D7, {MEM2(SD8, RM0), RN2}},
632 { "movhu",      0xfd4a0000,     0xffff0000,     FMT_D8, {MEM2(SD24, RM0), RN2}},
633 { "movhu",      0xfe4a0000,     0xffff0000,     FMT_D9, {MEM2(IMM32_HIGH8,RM0), RN2}},
634 { "movhu",      0xfb5a0000,     0xffff0000,     FMT_D7, {RM2, MEM2(SD8, RN0)}},
635 { "movhu",      0xfd5a0000,     0xffff0000,     FMT_D8, {RM2, MEM2(SD24, RN0)}},
636 { "movhu",      0xfe5a0000,     0xffff0000,     FMT_D9, {RM2, MEM2(IMM32_HIGH8,RN0)}},
637 { "movhu",      0xfbca0000,     0xffff0f00,     FMT_D7, {MEM2(SD8, SP), RN2}},
638 { "movhu",      0xfdca0000,     0xffff0f00,     FMT_D8, {MEM2(SD24, SP), RN2}},
639 { "movhu",      0xfeca0000,     0xffff0f00,     FMT_D9, {MEM2(IMM32_HIGH8, SP), RN2}},
640 { "movhu",      0xfbda0000,     0xffff0f00,     FMT_D7, {RM2, MEM2(SD8, SP)}},
641 { "movhu",      0xfdda0000,     0xffff0f00,     FMT_D8, {RM2, MEM2(SD24, SP)}},
642 { "movhu",      0xfeda0000,     0xffff0f00,     FMT_D9, {RM2, MEM2(IMM32_HIGH8, SP)}},
643 { "movhu",      0xfb4e0000,     0xffff0f00,     FMT_D7, {MEM(IMM8_MEM), RN2}},
644 { "movhu",      0xfd4e0000,     0xffff0f00,     FMT_D8, {MEM(IMM24_MEM), RN2}},
645 { "movhu",      0xfe4e0000,     0xffff0f00,     FMT_D9, {MEM(IMM32_HIGH8_MEM),
646                                                          RN2}},
647 { "movhu",      0xfb5e0000,     0xffff0f00,     FMT_D7, {RM2, MEM(IMM8_MEM)}},
648 { "movhu",      0xfd5e0000,     0xffff0f00,     FMT_D8, {RM2, MEM(IMM24_MEM)}},
649 { "movhu",      0xfe5e0000,     0xffff0f00,     FMT_D9, {RM2,
650                                                          MEM(IMM32_HIGH8_MEM)}},
651 { "movhu",      0xfbce0000,     0xffff000f,     FMT_D7, {MEM2(RI, RM0), RD2}},
652 { "movhu",      0xfbde0000,     0xffff000f,     FMT_D7, {RD2, MEM2(RI, RN0)}},
653 /* end-sanitize-am33 */
654
655 { "ext",        0xf2d0,         0xfffc,         FMT_D0, {DN0}},
656 /* start-sanitize-am33 */
657 { "ext",        0xf91800,       0xffff00,       FMT_D6, {RN02}},
658 /* end-sanitize-am33 */
659
660 /* start-sanitize-am33 */
661 { "extb",       0xf92800,       0xffff00,       FMT_D6, {RM2, RN0}},
662 /* end-sanitize-am33 */
663 { "extb",       0x10,           0xfc,           FMT_S0, {DN0}},
664 /* start-sanitize-am33 */
665 { "extb",       0xf92800,       0xffff00,       FMT_D6, {RN02}},
666 /* end-sanitize-am33 */
667
668 /* start-sanitize-am33 */
669 { "extbu",      0xf93800,       0xffff00,       FMT_D6, {RM2, RN0}},
670 /* end-sanitize-am33 */
671 { "extbu",      0x14,           0xfc,           FMT_S0, {DN0}},
672 /* start-sanitize-am33 */
673 { "extbu",      0xf93800,       0xffff00,       FMT_D6, {RN02}},
674 /* end-sanitize-am33 */
675
676 /* start-sanitize-am33 */
677 { "exth",       0xf94800,       0xffff00,       FMT_D6, {RM2, RN0}},
678 /* end-sanitize-am33 */
679 { "exth",       0x18,           0xfc,           FMT_S0, {DN0}},
680 /* start-sanitize-am33 */
681 { "exth",       0xf94800,       0xffff00,       FMT_D6, {RN02}},
682 /* end-sanitize-am33 */
683
684 /* start-sanitize-am33 */
685 { "exthu",      0xf95800,       0xffff00,       FMT_D6, {RM2, RN0}},
686 /* end-sanitize-am33 */
687 { "exthu",      0x1c,           0xfc,           FMT_S0, {DN0}},
688 /* start-sanitize-am33 */
689 { "exthu",      0xf95800,       0xffff00,       FMT_D6, {RN02}},
690 /* end-sanitize-am33 */
691
692 { "movm",       0xce00,         0xff00,         FMT_S1, {MEM(SP), REGS}},
693 { "movm",       0xcf00,         0xff00,         FMT_S1, {REGS, MEM(SP)}},
694 /* start-sanitize-am33 */
695 { "movm",       0xf8ce00,       0xffff00,       FMT_D1, {MEM(USP), REGS}},
696 { "movm",       0xf8cf00,       0xffff00,       FMT_D1, {REGS, MEM(USP)}},
697 /* end-sanitize-am33 */
698
699 { "clr",        0x00,           0xf3,           FMT_S0, {DN1}},
700 /* start-sanitize-am33 */
701 { "clr",        0xf96800,       0xffff00,       FMT_D6, {RN02}},
702 /* end-sanitize-am33 */
703
704 /* start-sanitize-am33 */
705 { "add",        0xfb7c0000,     0xffff000f,     FMT_D7, {RM2, RN0, RD2}},
706 /* end-sanitize-am33 */
707 { "add",        0xe0,           0xf0,           FMT_S0, {DM1, DN0}},
708 { "add",        0xf160,         0xfff0,         FMT_D0, {DM1, AN0}},
709 { "add",        0xf150,         0xfff0,         FMT_D0, {AM1, DN0}},
710 { "add",        0xf170,         0xfff0,         FMT_D0, {AM1, AN0}},
711 { "add",        0x2800,         0xfc00,         FMT_S1, {SIMM8, DN0}},
712 { "add",        0xfac00000,     0xfffc0000,     FMT_D2, {SIMM16, DN0}},
713 { "add",        0xfcc00000,     0xfffc0000,     FMT_D4, {IMM32, DN0}},
714 { "add",        0x2000,         0xfc00,         FMT_S1, {SIMM8, AN0}},
715 { "add",        0xfad00000,     0xfffc0000,     FMT_D2, {SIMM16, AN0}},
716 { "add",        0xfcd00000,     0xfffc0000,     FMT_D4, {IMM32, AN0}},
717 { "add",        0xf8fe00,       0xffff00,       FMT_D1, {SIMM8, SP}},
718 { "add",        0xfafe0000,     0xffff0000,     FMT_D2, {SIMM16, SP}},
719 { "add",        0xfcfe0000,     0xffff0000,     FMT_D4, {IMM32, SP}},
720 /* start-sanitize-am33 */
721 { "add",        0xf97800,       0xffff00,       FMT_D6, {RM2, RN0}},
722 { "add",        0xfb780000,     0xffff0000,     FMT_D7, {SIMM8, RN02}},
723 { "add",        0xfd780000,     0xffff0000,     FMT_D8, {SIMM24, RN02}},
724 { "add",        0xfe780000,     0xffff0000,     FMT_D9, {IMM32_HIGH8, RN02}},
725 /* end-sanitize-am33 */
726
727 /* start-sanitize-am33 */
728 { "addc",       0xfb8c0000,     0xffff000f,     FMT_D7, {RM2, RN0, RD0}},
729 /* end-sanitize-am33 */
730 { "addc",       0xf140,         0xfff0,         FMT_D0, {DM1, DN0}},
731 /* start-sanitize-am33 */
732 { "addc",       0xf98800,       0xffff00,       FMT_D6, {RM2, RN0}},
733 { "addc",       0xfb880000,     0xffff0000,     FMT_D7, {SIMM8, RN02}},
734 { "addc",       0xfd880000,     0xffff0000,     FMT_D8, {SIMM24, RN02}},
735 { "addc",       0xfe880000,     0xffff0000,     FMT_D9, {IMM32_HIGH8, RN02}},
736 /* end-sanitize-am33 */
737
738 /* start-sanitize-am33 */
739 { "sub",        0xfb9c0000,     0xffff000f,     FMT_D7, {RM2, RN0, RD0}},
740 /* end-sanitize-am33 */
741 { "sub",        0xf100,         0xfff0,         FMT_D0, {DM1, DN0}},
742 { "sub",        0xf120,         0xfff0,         FMT_D0, {DM1, AN0}},
743 { "sub",        0xf110,         0xfff0,         FMT_D0, {AM1, DN0}},
744 { "sub",        0xf130,         0xfff0,         FMT_D0, {AM1, AN0}},
745 { "sub",        0xfcc40000,     0xfffc0000,     FMT_D4, {IMM32, DN0}},
746 { "sub",        0xfcd40000,     0xfffc0000,     FMT_D4, {IMM32, AN0}},
747 /* start-sanitize-am33 */
748 { "sub",        0xf99800,       0xffff00,       FMT_D6, {RM2, RN0}},
749 { "sub",        0xfb980000,     0xffff0000,     FMT_D7, {SIMM8, RN02}},
750 { "sub",        0xfd980000,     0xffff0000,     FMT_D8, {SIMM24, RN02}},
751 { "sub",        0xfe980000,     0xffff0000,     FMT_D9, {IMM32_HIGH8, RN02}},
752 /* end-sanitize-am33 */
753
754 /* start-sanitize-am33 */
755 { "subc",       0xfa8c0000,     0xffff000f,     FMT_D7, {RM2, RN0, RD0}},
756 /* end-sanitize-am33 */
757 { "subc",       0xf180,         0xfff0,         FMT_D0, {DM1, DN0}},
758 /* start-sanitize-am33 */
759 { "subc",       0xf9a800,       0xffff00,       FMT_D6, {RM2, RN0}},
760 { "subc",       0xfba80000,     0xffff0000,     FMT_D7, {SIMM8, RN02}},
761 { "subc",       0xfda80000,     0xffff0000,     FMT_D8, {SIMM24, RN02}},
762 { "subc",       0xfea80000,     0xffff0000,     FMT_D9, {IMM32_HIGH8, RN02}},
763 /* end-sanitize-am33 */
764
765 /* start-sanitize-am33 */
766 { "mul",        0xfbab0000,     0xffff0000,     FMT_D7, {RM2, RN0, RD2, RD0}},
767 /* end-sanitize-am33 */
768 { "mul",        0xf240,         0xfff0,         FMT_D0, {DM1, DN0}},
769 /* start-sanitize-am33 */
770 { "mul",        0xf9a900,       0xffff00,       FMT_D6, {RM2, RN0}},
771 { "mul",        0xfba90000,     0xffff0000,     FMT_D7, {SIMM8, RN02}},
772 { "mul",        0xfda90000,     0xffff0000,     FMT_D8, {SIMM24, RN02}},
773 { "mul",        0xfea90000,     0xffff0000,     FMT_D9, {IMM32_HIGH8, RN02}},
774 /* end-sanitize-am33 */
775
776 /* start-sanitize-am33 */
777 { "mulu",       0xfbbb0000,     0xffff0000,     FMT_D7, {RM2, RN0, RD2, RD0}},
778 /* end-sanitize-am33 */
779 { "mulu",       0xf250,         0xfff0,         FMT_D0, {DM1, DN0}},
780 /* start-sanitize-am33 */
781 { "mulu",       0xf9b900,       0xffff00,       FMT_D6, {RM2, RN0}},
782 { "mulu",       0xfbb90000,     0xffff0000,     FMT_D7, {IMM8, RN02}},
783 { "mulu",       0xfdb90000,     0xffff0000,     FMT_D8, {IMM24, RN02}},
784 { "mulu",       0xfeb90000,     0xffff0000,     FMT_D9, {IMM32_HIGH8, RN02}},
785 /* end-sanitize-am33 */
786
787 { "div",        0xf260,         0xfff0,         FMT_D0, {DM1, DN0}},
788 /* start-sanitize-am33 */
789 { "div",        0xf9c900,       0xffff00,       FMT_D6, {RM2, RN0}},
790 /* end-sanitize-am33 */
791
792 { "divu",       0xf270,         0xfff0,         FMT_D0, {DM1, DN0}},
793 /* start-sanitize-am33 */
794 { "divu",       0xf9d900,       0xffff00,       FMT_D6, {RM2, RN0}},
795 /* end-sanitize-am33 */
796
797 { "inc",        0x40,           0xf3,           FMT_S0, {DN1}},
798 { "inc",        0x41,           0xf3,           FMT_S0, {AN1}},
799 /* start-sanitize-am33 */
800 { "inc",        0xf9b800,       0xffff00,       FMT_D6, {RN02}},
801 /* end-sanitize-am33 */
802
803 { "inc4",       0x50,           0xfc,           FMT_S0, {AN0}},
804 /* start-sanitize-am33 */
805 { "inc4",       0xf9c800,       0xffff00,       FMT_D6, {RN02}},
806 /* end-sanitize-am33 */
807
808 { "cmp",        0xa000,         0xf000,         FMT_S1, {SIMM8, DN01}},
809 { "cmp",        0xa0,           0xf0,           FMT_S0, {DM1, DN0}},
810 { "cmp",        0xf1a0,         0xfff0,         FMT_D0, {DM1, AN0}},
811 { "cmp",        0xf190,         0xfff0,         FMT_D0, {AM1, DN0}},
812 { "cmp",        0xb000,         0xf000,         FMT_S1, {IMM8, AN01}},
813 { "cmp",        0xb0,           0xf0,           FMT_S0, {AM1, AN0}},
814 { "cmp",        0xfac80000,     0xfffc0000,     FMT_D2, {SIMM16, DN0}},
815 { "cmp",        0xfcc80000,     0xfffc0000,     FMT_D4, {IMM32, DN0}},
816 { "cmp",        0xfad80000,     0xfffc0000,     FMT_D2, {IMM16, AN0}},
817 { "cmp",        0xfcd80000,     0xfffc0000,     FMT_D4, {IMM32, AN0}},
818 /* start-sanitize-am33 */
819 { "cmp",        0xf9d800,       0xffff00,       FMT_D6, {RM2, RN0}},
820 { "cmp",        0xfbd80000,     0xffff0000,     FMT_D7, {SIMM8, RN02}},
821 { "cmp",        0xfdd80000,     0xffff0000,     FMT_D8, {SIMM24, RN02}},
822 { "cmp",        0xfed80000,     0xffff0000,     FMT_D9, {IMM32_HIGH8, RN02}},
823 /* end-sanitize-am33 */
824
825 /* start-sanitize-am33 */
826 { "and",        0xfb0d0000,     0xffff000f,     FMT_D7, {RM2, RN0, RD0}},
827 /* end-sanitize-am33 */
828 { "and",        0xf200,         0xfff0,         FMT_D0, {DM1, DN0}},
829 { "and",        0xf8e000,       0xfffc00,       FMT_D1, {IMM8, DN0}},
830 { "and",        0xfae00000,     0xfffc0000,     FMT_D2, {IMM16, DN0}},
831 { "and",        0xfce00000,     0xfffc0000,     FMT_D4, {IMM32, DN0}},
832 { "and",        0xfafc0000,     0xffff0000,     FMT_D2, {IMM16, PSW}},
833 /* start-sanitize-am33 */
834 { "and",        0xfcfc0000,     0xffff0000,     FMT_D4, {IMM32, EPSW}},
835 { "and",        0xf90900,       0xffff00,       FMT_D6, {RM2, RN0}},
836 { "and",        0xfb090000,     0xffff0000,     FMT_D7, {IMM8, RN02}},
837 { "and",        0xfd090000,     0xffff0000,     FMT_D8, {IMM24, RN02}},
838 { "and",        0xfe090000,     0xffff0000,     FMT_D9, {IMM32_HIGH8, RN02}},
839 /* end-sanitize-am33 */
840
841 /* start-sanitize-am33 */
842 { "or",         0xfb1d0000,     0xffff000f,     FMT_D7, {RM2, RN0, RD0}},
843 /* end-sanitize-am33 */
844 { "or",         0xf210,         0xfff0,         FMT_D0, {DM1, DN0}},
845 { "or",         0xf8e400,       0xfffc00,       FMT_D1, {IMM8, DN0}},
846 { "or",         0xfae40000,     0xfffc0000,     FMT_D2, {IMM16, DN0}},
847 { "or",         0xfce40000,     0xfffc0000,     FMT_D4, {IMM32, DN0}},
848 { "or",         0xfafd0000,     0xffff0000,     FMT_D2, {IMM16, PSW}},
849 /* start-sanitize-am33 */
850 { "or",         0xfcfd0000,     0xffff0000,     FMT_D4, {IMM32, EPSW}},
851 { "or",         0xf91900,       0xffff00,       FMT_D6, {RM2, RN0}},
852 { "or",         0xfb190000,     0xffff0000,     FMT_D7, {IMM8, RN02}},
853 { "or",         0xfd190000,     0xffff0000,     FMT_D8, {IMM24, RN02}},
854 { "or",         0xfe190000,     0xffff0000,     FMT_D9, {IMM32_HIGH8, RN02}},
855 /* end-sanitize-am33 */
856
857 /* start-sanitize-am33 */
858 { "xor",        0xfb2d0000,     0xffff000f,     FMT_D7, {RM2, RN0, RD0}},
859 /* end-sanitize-am33 */
860 { "xor",        0xf220,         0xfff0,         FMT_D0, {DM1, DN0}},
861 { "xor",        0xfae80000,     0xfffc0000,     FMT_D2, {IMM16, DN0}},
862 { "xor",        0xfce80000,     0xfffc0000,     FMT_D4, {IMM32, DN0}},
863 /* start-sanitize-am33 */
864 { "xor",        0xf92900,       0xffff00,       FMT_D6, {RM2, RN0}},
865 { "xor",        0xfb290000,     0xffff0000,     FMT_D7, {IMM8, RN02}},
866 { "xor",        0xfd290000,     0xffff0000,     FMT_D8, {IMM24, RN02}},
867 { "xor",        0xfe290000,     0xffff0000,     FMT_D9, {IMM32_HIGH8, RN02}},
868 /* end-sanitize-am33 */
869 { "not",        0xf230,         0xfffc,         FMT_D0, {DN0}},
870 /* start-sanitize-am33 */
871 { "not",        0xf93900,       0xffff00,       FMT_D6, {RN02}},
872 /* end-sanitize-am33 */
873
874 { "btst",       0xf8ec00,       0xfffc00,       FMT_D1, {IMM8, DN0}},
875 { "btst",       0xfaec0000,     0xfffc0000,     FMT_D2, {IMM16, DN0}},
876 { "btst",       0xfcec0000,     0xfffc0000,     FMT_D4, {IMM32, DN0}},
877 /* start-sanitize-am33 */
878 /* Place these before the ones with IMM8E and SD8N_SHIFT8 since we want the
879    them to match last since they do not promote.  */
880 { "btst",       0xfbe90000,     0xffff0000,     FMT_D7, {IMM8, RN02}},
881 { "btst",       0xfde90000,     0xffff0000,     FMT_D8, {IMM24, RN02}},
882 { "btst",       0xfee90000,     0xffff0000,     FMT_D9, {IMM32_HIGH8, RN02}},
883 /* end-sanitize-am33 */
884 { "btst",       0xfe020000,     0xffff0000,     FMT_D5, {IMM8E,
885                                                          MEM(IMM32_LOWSHIFT8)}},
886 { "btst",       0xfaf80000,     0xfffc0000,     FMT_D2,
887                                         {IMM8, MEM2(SD8N_SHIFT8,AN0)}},
888
889 { "bset",       0xf080,         0xfff0,         FMT_D0, {DM1, MEM(AN0)}},
890 { "bset",       0xfe000000,     0xffff0000,     FMT_D5, {IMM8E,
891                                                          MEM(IMM32_LOWSHIFT8)}},
892 { "bset",       0xfaf00000,     0xfffc0000,     FMT_D2,
893                                         {IMM8, MEM2(SD8N_SHIFT8,AN0)}},
894
895 { "bclr",       0xf090,         0xfff0,         FMT_D0, {DM1, MEM(AN0)}},
896 { "bclr",       0xfe010000,     0xffff0000,     FMT_D5, {IMM8E,
897                                                          MEM(IMM32_LOWSHIFT8)}},
898 { "bclr",       0xfaf40000,     0xfffc0000,     FMT_D2, {IMM8,
899                                                 MEM2(SD8N_SHIFT8,AN0)}},
900
901 /* start-sanitize-am33 */
902 { "asr",        0xfb4d0000,     0xffff000f,     FMT_D7, {RM2, RN0, RD0}},
903 /* end-sanitize-am33 */
904 { "asr",        0xf2b0,         0xfff0,         FMT_D0, {DM1, DN0}},
905 { "asr",        0xf8c800,       0xfffc00,       FMT_D1, {IMM8, DN0}},
906 /* start-sanitize-am33 */
907 { "asr",        0xf94900,       0xffff00,       FMT_D6, {RM2, RN0}},
908 { "asr",        0xfb490000,     0xffff0000,     FMT_D7, {IMM8, RN02}},
909 { "asr",        0xfd490000,     0xfffc0000,     FMT_D8, {IMM24, RN02}},
910 { "asr",        0xfe490000,     0xffff0000,     FMT_D9, {IMM32_HIGH8, RN02}},
911 /* end-sanitize-am33 */
912 { "asr",        0xf8c801,       0xfffcff,       FMT_D1, {DN0}},
913 /* start-sanitize-am33 */
914 { "asr",        0xfb490000,     0xffff00ff,     FMT_D7, {RN02}},
915 /* end-sanitize-am33 */
916
917 /* start-sanitize-am33 */
918 { "lsr",        0xfb5d0000,     0xffff000f,     FMT_D7, {RM2, RN0, RD0}},
919 /* end-sanitize-am33 */
920 { "lsr",        0xf2a0,         0xfff0,         FMT_D0, {DM1, DN0}},
921 { "lsr",        0xf8c400,       0xfffc00,       FMT_D1, {IMM8, DN0}},
922 /* start-sanitize-am33 */
923 { "lsr",        0xf95900,       0xffff00,       FMT_D6, {RM2, RN0}},
924 { "lsr",        0xfb590000,     0xffff0000,     FMT_D7, {IMM8, RN02}},
925 { "lsr",        0xfd590000,     0xfffc0000,     FMT_D8, {IMM24, RN02}},
926 { "lsr",        0xfe590000,     0xffff0000,     FMT_D9, {IMM32_HIGH8, RN02}},
927 /* end-sanitize-am33 */
928 { "lsr",        0xf8c401,       0xfffcff,       FMT_D1, {DN0}},
929 /* start-sanitize-am33 */
930 { "lsr",        0xfb590000,     0xffff00ff,     FMT_D7, {RN02}},
931 /* end-sanitize-am33 */
932
933 /* start-sanitize-am33 */
934 { "asl",        0xfb6d0000,     0xffff000f,     FMT_D7, {RM2, RN0, RD0}},
935 /* end-sanitize-am33 */
936 { "asl",        0xf290,         0xfff0,         FMT_D0, {DM1, DN0}},
937 { "asl",        0xf8c000,       0xfffc00,       FMT_D1, {IMM8, DN0}},
938 /* start-sanitize-am33 */
939 { "asl",        0xf96900,       0xffff00,       FMT_D6, {RM2, RN0}},
940 { "asl",        0xfb690000,     0xffff0000,     FMT_D7, {SIMM8, RN02}},
941 { "asl",        0xfd690000,     0xfffc0000,     FMT_D8, {IMM24, RN02}},
942 { "asl",        0xfe690000,     0xffff0000,     FMT_D9, {IMM32_HIGH8, RN02}},
943 /* end-sanitize-am33 */
944 { "asl",        0xf8c001,       0xfffcff,       FMT_D1, {DN0}},
945 /* start-sanitize-am33 */
946 { "asl",        0xfb690000,     0xffff00ff,     FMT_D7, {RN02}},
947 /* end-sanitize-am33 */
948
949 { "asl2",       0x54,           0xfc,           FMT_S0, {DN0}},
950 /* start-sanitize-am33 */
951 { "asl2",       0xf97900,       0xffff00,       FMT_D6, {RN02}},
952 /* end-sanitize-am33 */
953
954 { "ror",        0xf284,         0xfffc,         FMT_D0, {DN0}},
955 /* start-sanitize-am33 */
956 { "ror",        0xf98900,       0xffff00,       FMT_D6, {RN02}},
957 /* end-sanitize-am33 */
958
959 { "rol",        0xf280,         0xfffc,         FMT_D0, {DN0}},
960 /* start-sanitize-am33 */
961 { "rol",        0xf99900,       0xffff00,       FMT_D6, {RN02}},
962 /* end-sanitize-am33 */
963
964 { "beq",        0xc800,         0xff00,         FMT_S1, {SD8N_PCREL}},
965 { "bne",        0xc900,         0xff00,         FMT_S1, {SD8N_PCREL}},
966 { "bgt",        0xc100,         0xff00,         FMT_S1, {SD8N_PCREL}},
967 { "bge",        0xc200,         0xff00,         FMT_S1, {SD8N_PCREL}},
968 { "ble",        0xc300,         0xff00,         FMT_S1, {SD8N_PCREL}},
969 { "blt",        0xc000,         0xff00,         FMT_S1, {SD8N_PCREL}},
970 { "bhi",        0xc500,         0xff00,         FMT_S1, {SD8N_PCREL}},
971 { "bcc",        0xc600,         0xff00,         FMT_S1, {SD8N_PCREL}},
972 { "bls",        0xc700,         0xff00,         FMT_S1, {SD8N_PCREL}},
973 { "bcs",        0xc400,         0xff00,         FMT_S1, {SD8N_PCREL}},
974 { "bvc",        0xf8e800,       0xffff00,       FMT_D1, {SD8N_PCREL}},
975 { "bvs",        0xf8e900,       0xffff00,       FMT_D1, {SD8N_PCREL}},
976 { "bnc",        0xf8ea00,       0xffff00,       FMT_D1, {SD8N_PCREL}},
977 { "bns",        0xf8eb00,       0xffff00,       FMT_D1, {SD8N_PCREL}},
978 { "bra",        0xca00,         0xff00,         FMT_S1, {SD8N_PCREL}},
979
980 { "leq",        0xd8,           0xff,           FMT_S0, {UNUSED}},
981 { "lne",        0xd9,           0xff,           FMT_S0, {UNUSED}},
982 { "lgt",        0xd1,           0xff,           FMT_S0, {UNUSED}},
983 { "lge",        0xd2,           0xff,           FMT_S0, {UNUSED}},
984 { "lle",        0xd3,           0xff,           FMT_S0, {UNUSED}},
985 { "llt",        0xd0,           0xff,           FMT_S0, {UNUSED}},
986 { "lhi",        0xd5,           0xff,           FMT_S0, {UNUSED}},
987 { "lcc",        0xd6,           0xff,           FMT_S0, {UNUSED}},
988 { "lls",        0xd7,           0xff,           FMT_S0, {UNUSED}},
989 { "lcs",        0xd4,           0xff,           FMT_S0, {UNUSED}},
990 { "lra",        0xda,           0xff,           FMT_S0, {UNUSED}},
991 { "setlb",      0xdb,           0xff,           FMT_S0, {UNUSED}},
992
993 { "jmp",        0xf0f4,         0xfffc,         FMT_D0, {PAREN,AN0,PAREN}},
994 { "jmp",        0xcc0000,       0xff0000,       FMT_S2, {IMM16_PCREL}},
995 { "jmp",        0xdc000000,     0xff000000,     FMT_S4, {IMM32_HIGH24}},
996 { "call",       0xcd000000,     0xff000000,     FMT_S4, {D16_SHIFT,REGS,IMM8E}},
997 { "call",       0xdd000000,     0xff000000,     FMT_S6,
998                                         {IMM32_HIGH24_LOWSHIFT16,REGSE_SHIFT8,IMM8E}},
999 { "calls",      0xf0f0,         0xfffc,         FMT_D0, {PAREN,AN0,PAREN}},
1000 { "calls",      0xfaff0000,     0xffff0000,     FMT_D2, {IMM16_PCREL}},
1001 { "calls",      0xfcff0000,     0xffff0000,     FMT_D4, {IMM32_PCREL}},
1002
1003 { "ret",        0xdf0000,       0xff0000,       FMT_S2, {REGS_SHIFT8, IMM8}},
1004 { "retf",       0xde0000,       0xff0000,       FMT_S2, {REGS_SHIFT8, IMM8}},
1005 { "rets",       0xf0fc,         0xffff,         FMT_D0, {UNUSED}},
1006 { "rti",        0xf0fd,         0xffff,         FMT_D0, {UNUSED}},
1007 { "trap",       0xf0fe,         0xffff,         FMT_D0, {UNUSED}},
1008 { "rtm",        0xf0ff,         0xffff,         FMT_D0, {UNUSED}},
1009 { "nop",        0xcb,           0xff,           FMT_S0, {UNUSED}},
1010 /* { "udf", 0, 0, {0}},  */
1011
1012 { "putx",       0xf500,         0xfff0,         FMT_D0, {DN01}},
1013 { "getx",       0xf6f0,         0xfff0,         FMT_D0, {DN01}},
1014 { "mulq",       0xf600,         0xfff0,         FMT_D0, {DM1, DN0}},
1015 { "mulq",       0xf90000,       0xfffc00,       FMT_D1, {SIMM8, DN0}},
1016 { "mulq",       0xfb000000,     0xfffc0000,     FMT_D2, {SIMM16, DN0}},
1017 { "mulq",       0xfd000000,     0xfffc0000,     FMT_D4, {IMM32, DN0}},
1018 { "mulqu",      0xf610,         0xfff0,         FMT_D0, {DM1, DN0}},
1019 { "mulqu",      0xf91400,       0xfffc00,       FMT_D1, {SIMM8, DN0}},
1020 { "mulqu",      0xfb140000,     0xfffc0000,     FMT_D2, {SIMM16, DN0}},
1021 { "mulqu",      0xfd140000,     0xfffc0000,     FMT_D4, {IMM32, DN0}},
1022 { "sat16",      0xf640,         0xfff0,         FMT_D0, {DM1, DN0}},
1023 /* start-sanitize-am33 */
1024 { "sat16",      0xf9ab00,       0xffff00,       FMT_D6, {RM2, RN0}},
1025 /* end-sanitize-am33 */
1026
1027 { "sat24",      0xf650,         0xfff0,         FMT_D0, {DM1, DN0}},
1028 /* start-sanitize-am33 */
1029 { "sat24",      0xfbaf0000,     0xffff00ff,     FMT_D7, {RM2, RN0}},
1030 /* end-sanitize-am33 */
1031
1032 /* start-sanitize-am33 */
1033 { "bsch",       0xfbff0000,     0xffff000f,     FMT_D7, {RM2, RN0, RD0}},
1034 /* end-sanitize-am33 */
1035 { "bsch",       0xf670,         0xfff0,         FMT_D0, {DM1, DN0}},
1036 /* start-sanitize-am33 */
1037 { "bsch",       0xf9fb00,       0xffff00,       FMT_D6, {RM2, RN0}},
1038 /* end-sanitize-am33 */
1039
1040 /* Extension.  We need some instruction to trigger "emulated syscalls"
1041    for our simulator.  */
1042 /* start-sanitize-am33 */
1043 { "syscall",    0xf0e0,         0xfff0,         FMT_D0, {IMM4}},
1044 /* end-sanitize-am33 */
1045 { "syscall",    0xf0c0,         0xffff,         FMT_D0, {UNUSED}},
1046
1047 /* Extension.  When talking to the simulator, gdb requires some instruction
1048    that will trigger a "breakpoint" (really just an instruction that isn't
1049    otherwise used by the tools.  This instruction must be the same size
1050    as the smallest instruction on the target machine.  In the case of the
1051    mn10x00 the "break" instruction must be one byte.  0xff is available on
1052    both mn10x00 architectures.  */
1053 { "break",      0xff,           0xff,           FMT_S0, {UNUSED}},
1054
1055 /* start-sanitize-am33 */
1056 { "add_add",    0xf7000000,     0xffff0000,     FMT_D10, {RM6, RN4, RM2, RN0}},
1057 { "add_add",    0xf7100000,     0xffff0000,     FMT_D10, {RM6, RN4,
1058                                                           SIMM4_2, RN0}},
1059 { "add_add",    0xf7040000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1060                                                           RM2, RN0}},
1061 { "add_add",    0xf7140000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1062                                                           SIMM4_2, RN0}},
1063 { "add_sub",    0xf7200000,     0xffff0000,     FMT_D10, {RM6, RN4, RM2, RN0}},
1064 { "add_sub",    0xf7300000,     0xffff0000,     FMT_D10, {RM6, RN4,
1065                                                           SIMM4_2, RN0}},
1066 { "add_sub",    0xf7240000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1067                                                           RM2, RN0}},
1068 { "add_sub",    0xf7340000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1069                                                           SIMM4_2, RN0}},
1070 { "add_cmp",    0xf7400000,     0xffff0000,     FMT_D10, {RM6, RN4, RM2, RN0}},
1071 { "add_cmp",    0xf7500000,     0xffff0000,     FMT_D10, {RM6, RN4,
1072                                                           SIMM4_2, RN0}},
1073 { "add_cmp",    0xf7440000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1074                                                           RM2, RN0}},
1075 { "add_cmp",    0xf7540000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1076                                                           SIMM4_2, RN0}},
1077 { "add_mov",    0xf7600000,     0xffff0000,     FMT_D10, {RM6, RN4, RM2, RN0}},
1078 { "add_mov",    0xf7700000,     0xffff0000,     FMT_D10, {RM6, RN4,
1079                                                           SIMM4_2, RN0}},
1080 { "add_mov",    0xf7640000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1081                                                           RM2, RN0}},
1082 { "add_mov",    0xf7740000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1083                                                           SIMM4_2, RN0}},
1084 { "add_asr",    0xf7800000,     0xffff0000,     FMT_D10, {RM6, RN4, RM2, RN0}},
1085 { "add_asr",    0xf7900000,     0xffff0000,     FMT_D10, {RM6, RN4,
1086                                                           IMM4_2, RN0}},
1087 { "add_asr",    0xf7840000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1088                                                           RM2, RN0}},
1089 { "add_asr",    0xf7940000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1090                                                           IMM4_2, RN0}},
1091 { "add_lsr",    0xf7a00000,     0xffff0000,     FMT_D10, {RM6, RN4, RM2, RN0}},
1092 { "add_lsr",    0xf7b00000,     0xffff0000,     FMT_D10, {RM6, RN4,
1093                                                           IMM4_2, RN0}},
1094 { "add_lsr",    0xf7a40000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1095                                                           RM2, RN0}},
1096 { "add_lsr",    0xf7b40000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1097                                                           IMM4_2, RN0}},
1098 { "add_asl",    0xf7c00000,     0xffff0000,     FMT_D10, {RM6, RN4, RM2, RN0}},
1099 { "add_asl",    0xf7d00000,     0xffff0000,     FMT_D10, {RM6, RN4,
1100                                                           IMM4_2, RN0}},
1101 { "add_asl",    0xf7c40000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1102                                                           RM2, RN0}},
1103 { "add_asl",    0xf7d40000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1104                                                           IMM4_2, RN0}},
1105 { "cmp_add",    0xf7010000,     0xffff0000,     FMT_D10, {RM6, RN4, RM2, RN0}},
1106 { "cmp_add",    0xf7110000,     0xffff0000,     FMT_D10, {RM6, RN4,
1107                                                           SIMM4_2, RN0}},
1108 { "cmp_add",    0xf7050000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1109                                                           RM2, RN0}},
1110 { "cmp_add",    0xf7150000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1111                                                           SIMM4_2, RN0}},
1112 { "cmp_sub",    0xf7210000,     0xffff0000,     FMT_D10, {RM6, RN4, RM2, RN0}},
1113 { "cmp_sub",    0xf7310000,     0xffff0000,     FMT_D10, {RM6, RN4,
1114                                                           SIMM4_2, RN0}},
1115 { "cmp_sub",    0xf7250000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1116                                                           RM2, RN0}},
1117 { "cmp_sub",    0xf7350000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1118                                                           SIMM4_2, RN0}},
1119 { "cmp_mov",    0xf7610000,     0xffff0000,     FMT_D10, {RM6, RN4, RM2, RN0}},
1120 { "cmp_mov",    0xf7710000,     0xffff0000,     FMT_D10, {RM6, RN4,
1121                                                           SIMM4_2, RN0}},
1122 { "cmp_mov",    0xf7650000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1123                                                           RM2, RN0}},
1124 { "cmp_mov",    0xf7750000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1125                                                           SIMM4_2, RN0}},
1126 { "cmp_asr",    0xf7810000,     0xffff0000,     FMT_D10, {RM6, RN4, RM2, RN0}},
1127 { "cmp_asr",    0xf7910000,     0xffff0000,     FMT_D10, {RM6, RN4,
1128                                                           IMM4_2, RN0}},
1129 { "cmp_asr",    0xf7850000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1130                                                           RM2, RN0}},
1131 { "cmp_asr",    0xf7950000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1132                                                           IMM4_2, RN0}},
1133 { "cmp_lsr",    0xf7a10000,     0xffff0000,     FMT_D10, {RM6, RN4, RM2, RN0}},
1134 { "cmp_lsr",    0xf7b10000,     0xffff0000,     FMT_D10, {RM6, RN4,
1135                                                           IMM4_2, RN0}},
1136 { "cmp_lsr",    0xf7a50000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1137                                                           RM2, RN0}},
1138 { "cmp_lsr",    0xf7b50000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1139                                                           IMM4_2, RN0}},
1140 { "cmp_asl",    0xf7c10000,     0xffff0000,     FMT_D10, {RM6, RN4, RM2, RN0}},
1141 { "cmp_asl",    0xf7d10000,     0xffff0000,     FMT_D10, {RM6, RN4, IMM4_2, RN0}},
1142 { "cmp_asl",    0xf7c50000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1143                                                           RM2, RN0}},
1144 { "cmp_asl",    0xf7d50000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1145                                                           IMM4_2, RN0}},
1146 { "sub_add",    0xf7020000,     0xffff0000,     FMT_D10, {RM6, RN4, RM2, RN0}},
1147 { "sub_add",    0xf7120000,     0xffff0000,     FMT_D10, {RM6, RN4,
1148                                                           SIMM4_2, RN0}},
1149 { "sub_add",    0xf7060000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1150                                                           RM2, RN0}},
1151 { "sub_add",    0xf7160000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1152                                                           SIMM4_2, RN0}},
1153 { "sub_sub",    0xf7220000,     0xffff0000,     FMT_D10, {RM6, RN4, RM2, RN0}},
1154 { "sub_sub",    0xf7320000,     0xffff0000,     FMT_D10, {RM6, RN4,
1155                                                           SIMM4_2, RN0}},
1156 { "sub_sub",    0xf7260000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1157                                                           RM2, RN0}},
1158 { "sub_sub",    0xf7360000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1159                                                           SIMM4_2, RN0}},
1160 { "sub_cmp",    0xf7420000,     0xffff0000,     FMT_D10, {RM6, RN4, RM2, RN0}},
1161 { "sub_cmp",    0xf7520000,     0xffff0000,     FMT_D10, {RM6, RN4,
1162                                                           SIMM4_2, RN0}},
1163 { "sub_cmp",    0xf7460000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1164                                                           RM2, RN0}},
1165 { "sub_cmp",    0xf7560000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1166                                                           SIMM4_2, RN0}},
1167 { "sub_mov",    0xf7620000,     0xffff0000,     FMT_D10, {RM6, RN4, RM2, RN0}},
1168 { "sub_mov",    0xf7720000,     0xffff0000,     FMT_D10, {RM6, RN4,
1169                                                           SIMM4_2, RN0}},
1170 { "sub_mov",    0xf7660000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1171                                                           RM2, RN0}},
1172 { "sub_mov",    0xf7760000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1173                                                           SIMM4_2, RN0}},
1174 { "sub_asr",    0xf7820000,     0xffff0000,     FMT_D10, {RM6, RN4, RM2, RN0}},
1175 { "sub_asr",    0xf7920000,     0xffff0000,     FMT_D10, {RM6, RN4,
1176                                                           IMM4_2, RN0}},
1177 { "sub_asr",    0xf7860000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1178                                                           RM2, RN0}},
1179 { "sub_asr",    0xf7960000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1180                                                           IMM4_2, RN0}},
1181 { "sub_lsr",    0xf7a20000,     0xffff0000,     FMT_D10, {RM6, RN4, RM2, RN0}},
1182 { "sub_lsr",    0xf7b20000,     0xffff0000,     FMT_D10, {RM6, RN4,
1183                                                           IMM4_2, RN0}},
1184 { "sub_lsr",    0xf7a60000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1185                                                           RM2, RN0}},
1186 { "sub_lsr",    0xf7b60000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1187                                                           IMM4_2, RN0}},
1188 { "sub_asl",    0xf7c20000,     0xffff0000,     FMT_D10, {RM6, RN4, RM2, RN0}},
1189 { "sub_asl",    0xf7d20000,     0xffff0000,     FMT_D10, {RM6, RN4,
1190                                                           IMM4_2, RN0}},
1191 { "sub_asl",    0xf7c60000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1192                                                           RM2, RN0}},
1193 { "sub_asl",    0xf7d60000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1194                                                           IMM4_2, RN0}},
1195 { "mov_add",    0xf7030000,     0xffff0000,     FMT_D10, {RM6, RN4, RM2, RN0}},
1196 { "mov_add",    0xf7130000,     0xffff0000,     FMT_D10, {RM6, RN4,
1197                                                           SIMM4_2, RN0}},
1198 { "mov_add",    0xf7070000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1199                                                           RM2, RN0}},
1200 { "mov_add",    0xf7170000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1201                                                           SIMM4_2, RN0}},
1202 { "mov_sub",    0xf7230000,     0xffff0000,     FMT_D10, {RM6, RN4, RM2, RN0}},
1203 { "mov_sub",    0xf7330000,     0xffff0000,     FMT_D10, {RM6, RN4,
1204                                                           SIMM4_2, RN0}},
1205 { "mov_sub",    0xf7270000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1206                                                           RM2, RN0}},
1207 { "mov_sub",    0xf7370000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1208                                                           SIMM4_2, RN0}},
1209 { "mov_cmp",    0xf7430000,     0xffff0000,     FMT_D10, {RM6, RN4, RM2, RN0}},
1210 { "mov_cmp",    0xf7530000,     0xffff0000,     FMT_D10, {RM6, RN4,
1211                                                           SIMM4_2, RN0}},
1212 { "mov_cmp",    0xf7470000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1213                                                           RM2, RN0}},
1214 { "mov_cmp",    0xf7570000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1215                                                           SIMM4_2, RN0}},
1216 { "mov_mov",    0xf7630000,     0xffff0000,     FMT_D10, {RM6, RN4, RM2, RN0}},
1217 { "mov_mov",    0xf7730000,     0xffff0000,     FMT_D10, {RM6, RN4,
1218                                                           SIMM4_2, RN0}},
1219 { "mov_mov",    0xf7670000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1220                                                           RM2, RN0}},
1221 { "mov_mov",    0xf7770000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1222                                                           SIMM4_2, RN0}},
1223 { "mov_asr",    0xf7830000,     0xffff0000,     FMT_D10, {RM6, RN4, RM2, RN0}},
1224 { "mov_asr",    0xf7930000,     0xffff0000,     FMT_D10, {RM6, RN4,
1225                                                           IMM4_2, RN0}},
1226 { "mov_asr",    0xf7870000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1227                                                           RM2, RN0}},
1228 { "mov_asr",    0xf7970000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1229                                                           IMM4_2, RN0}},
1230 { "mov_lsr",    0xf7a30000,     0xffff0000,     FMT_D10, {RM6, RN4, RM2, RN0}},
1231 { "mov_lsr",    0xf7b30000,     0xffff0000,     FMT_D10, {RM6, RN4,
1232                                                           IMM4_2, RN0}},
1233 { "mov_lsr",    0xf7a70000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1234                                                           RM2, RN0}},
1235 { "mov_lsr",    0xf7b70000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1236                                                           IMM4_2, RN0}},
1237 { "mov_asl",    0xf7c30000,     0xffff0000,     FMT_D10, {RM6, RN4, RM2, RN0}},
1238 { "mov_asl",    0xf7d30000,     0xffff0000,     FMT_D10, {RM6, RN4,
1239                                                           IMM4_2, RN0}},
1240 { "mov_asl",    0xf7c70000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1241                                                           RM2, RN0}},
1242 { "mov_asl",    0xf7d70000,     0xffff0000,     FMT_D10, {SIMM4_6, RN4,
1243                                                           IMM4_2, RN0}},
1244 { "and_add",    0xf7080000,     0xffff0000,     FMT_D10, {RM6, RN4,
1245                                                           RM2, RN0}},
1246 { "and_add",    0xf7180000,     0xffff0000,     FMT_D10, {RM6, RN4,
1247                                                           SIMM4_2, RN0}},
1248 { "and_sub",    0xf7280000,     0xffff0000,     FMT_D10, {RM6, RN4,
1249                                                           RM2, RN0}},
1250 { "and_sub",    0xf7380000,     0xffff0000,     FMT_D10, {RM6, RN4,
1251                                                           SIMM4_2, RN0}},
1252 { "and_cmp",    0xf7480000,     0xffff0000,     FMT_D10, {RM6, RN4,
1253                                                           RM2, RN0}},
1254 { "and_cmp",    0xf7580000,     0xffff0000,     FMT_D10, {RM6, RN4,
1255                                                           SIMM4_2, RN0}},
1256 { "and_mov",    0xf7680000,     0xffff0000,     FMT_D10, {RM6, RN4,
1257                                                           RM2, RN0}},
1258 { "and_mov",    0xf7780000,     0xffff0000,     FMT_D10, {RM6, RN4,
1259                                                           SIMM4_2, RN0}},
1260 { "and_asr",    0xf7880000,     0xffff0000,     FMT_D10, {RM6, RN4,
1261                                                           RM2, RN0}},
1262 { "and_asr",    0xf7980000,     0xffff0000,     FMT_D10, {RM6, RN4,
1263                                                           IMM4_2, RN0}},
1264 { "and_lsr",    0xf7a80000,     0xffff0000,     FMT_D10, {RM6, RN4,
1265                                                           RM2, RN0}},
1266 { "and_lsr",    0xf7b80000,     0xffff0000,     FMT_D10, {RM6, RN4,
1267                                                           IMM4_2, RN0}},
1268 { "and_asl",    0xf7c80000,     0xffff0000,     FMT_D10, {RM6, RN4,
1269                                                           RM2, RN0}},
1270 { "and_asl",    0xf7d80000,     0xffff0000,     FMT_D10, {RM6, RN4,
1271                                                           IMM4_2, RN0}},
1272 { "dmach_add",  0xf7090000,     0xffff0000,     FMT_D10, {RM6, RN4,
1273                                                           RM2, RN0}},
1274 { "dmach_add",  0xf7190000,     0xffff0000,     FMT_D10, {RM6, RN4,
1275                                                           SIMM4_2, RN0}},
1276 { "dmach_sub",  0xf7290000,     0xffff0000,     FMT_D10, {RM6, RN4,
1277                                                           RM2, RN0}},
1278 { "dmach_sub",  0xf7390000,     0xffff0000,     FMT_D10, {RM6, RN4,
1279                                                           SIMM4_2, RN0}},
1280 { "dmach_cmp",  0xf7490000,     0xffff0000,     FMT_D10, {RM6, RN4,
1281                                                           RM2, RN0}},
1282 { "dmach_cmp",  0xf7590000,     0xffff0000,     FMT_D10, {RM6, RN4,
1283                                                           SIMM4_2, RN0}},
1284 { "dmach_mov",  0xf7690000,     0xffff0000,     FMT_D10, {RM6, RN4,
1285                                                           RM2, RN0}},
1286 { "dmach_mov",  0xf7790000,     0xffff0000,     FMT_D10, {RM6, RN4,
1287                                                           SIMM4_2, RN0}},
1288 { "dmach_asr",  0xf7890000,     0xffff0000,     FMT_D10, {RM6, RN4,
1289                                                           RM2, RN0}},
1290 { "dmach_asr",  0xf7990000,     0xffff0000,     FMT_D10, {RM6, RN4,
1291                                                           IMM4_2, RN0}},
1292 { "dmach_lsr",  0xf7a90000,     0xffff0000,     FMT_D10, {RM6, RN4,
1293                                                           RM2, RN0}},
1294 { "dmach_lsr",  0xf7b90000,     0xffff0000,     FMT_D10, {RM6, RN4,
1295                                                           IMM4_2, RN0}},
1296 { "dmach_asl",  0xf7c90000,     0xffff0000,     FMT_D10, {RM6, RN4,
1297                                                           RM2, RN0}},
1298 { "dmach_asl",  0xf7d90000,     0xffff0000,     FMT_D10, {RM6, RN4,
1299                                                           IMM4_2, RN0}},
1300 { "xor_add",    0xf70a0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1301                                                           RM2, RN0}},
1302 { "xor_add",    0xf71a0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1303                                                           SIMM4_2, RN0}},
1304 { "xor_sub",    0xf72a0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1305                                                           RM2, RN0}},
1306 { "xor_sub",    0xf73a0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1307                                                           SIMM4_2, RN0}},
1308 { "xor_cmp",    0xf74a0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1309                                                           RM2, RN0}},
1310 { "xor_cmp",    0xf75a0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1311                                                           SIMM4_2, RN0}},
1312 { "xor_mov",    0xf76a0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1313                                                           RM2, RN0}},
1314 { "xor_mov",    0xf77a0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1315                                                           SIMM4_2, RN0}},
1316 { "xor_asr",    0xf78a0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1317                                                           RM2, RN0}},
1318 { "xor_asr",    0xf79a0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1319                                                           IMM4_2, RN0}},
1320 { "xor_lsr",    0xf7aa0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1321                                                           RM2, RN0}},
1322 { "xor_lsr",    0xf7ba0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1323                                                           IMM4_2, RN0}},
1324 { "xor_asl",    0xf7ca0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1325                                                           RM2, RN0}},
1326 { "xor_asl",    0xf7da0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1327                                                           IMM4_2, RN0}},
1328 { "swhw_add",   0xf70b0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1329                                                           RM2, RN0}},
1330 { "swhw_add",   0xf71b0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1331                                                           SIMM4_2, RN0}},
1332 { "swhw_sub",   0xf72b0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1333                                                           RM2, RN0}},
1334 { "swhw_sub",   0xf73b0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1335                                                           SIMM4_2, RN0}},
1336 { "swhw_cmp",   0xf74b0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1337                                                           RM2, RN0}},
1338 { "swhw_cmp",   0xf75b0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1339                                                           SIMM4_2, RN0}},
1340 { "swhw_mov",   0xf76b0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1341                                                           RM2, RN0}},
1342 { "swhw_mov",   0xf77b0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1343                                                           SIMM4_2, RN0}},
1344 { "swhw_asr",   0xf78b0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1345                                                           RM2, RN0}},
1346 { "swhw_asr",   0xf79b0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1347                                                           IMM4_2, RN0}},
1348 { "swhw_lsr",   0xf7ab0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1349                                                           RM2, RN0}},
1350 { "swhw_lsr",   0xf7bb0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1351                                                           IMM4_2, RN0}},
1352 { "swhw_asl",   0xf7cb0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1353                                                           RM2, RN0}},
1354 { "swhw_asl",   0xf7db0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1355                                                           IMM4_2, RN0}},
1356 { "or_add",     0xf70c0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1357                                                           RM2, RN0}},
1358 { "or_add",     0xf71c0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1359                                                           SIMM4_2, RN0}},
1360 { "or_sub",     0xf72c0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1361                                                           RM2, RN0}},
1362 { "or_sub",     0xf73c0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1363                                                           SIMM4_2, RN0}},
1364 { "or_cmp",     0xf74c0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1365                                                           RM2, RN0}},
1366 { "or_cmp",     0xf75c0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1367                                                           SIMM4_2, RN0}},
1368 { "or_mov",     0xf76c0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1369                                                           RM2, RN0}},
1370 { "or_mov",     0xf77c0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1371                                                           SIMM4_2, RN0}},
1372 { "or_asr",     0xf78c0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1373                                                           RM2, RN0}},
1374 { "or_asr",     0xf79c0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1375                                                           IMM4_2, RN0}},
1376 { "or_lsr",     0xf7ac0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1377                                                           RM2, RN0}},
1378 { "or_lsr",     0xf7bc0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1379                                                           IMM4_2, RN0}},
1380 { "or_asl",     0xf7cc0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1381                                                           RM2, RN0}},
1382 { "or_asl",     0xf7dc0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1383                                                           IMM4_2, RN0}},
1384 { "sat16_add",  0xf70d0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1385                                                           RM2, RN0}},
1386 { "sat16_add",  0xf71d0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1387                                                           SIMM4_2, RN0}},
1388 { "sat16_sub",  0xf72d0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1389                                                           RM2, RN0}},
1390 { "sat16_sub",  0xf73d0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1391                                                           SIMM4_2, RN0}},
1392 { "sat16_cmp",  0xf74d0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1393                                                           RM2, RN0}},
1394 { "sat16_cmp",  0xf75d0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1395                                                           SIMM4_2, RN0}},
1396 { "sat16_mov",  0xf76d0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1397                                                           RM2, RN0}},
1398 { "sat16_mov",  0xf77d0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1399                                                           SIMM4_2, RN0}},
1400 { "sat16_asr",  0xf78d0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1401                                                           RM2, RN0}},
1402 { "sat16_asr",  0xf79d0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1403                                                           IMM4_2, RN0}},
1404 { "sat16_lsr",  0xf7ad0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1405                                                           RM2, RN0}},
1406 { "sat16_lsr",  0xf7bd0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1407                                                           IMM4_2, RN0}},
1408 { "sat16_asl",  0xf7cd0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1409                                                           RM2, RN0}},
1410 { "sat16_asl",  0xf7dd0000,     0xffff0000,     FMT_D10, {RM6, RN4,
1411                                                           IMM4_2, RN0}},
1412 /* end-sanitize-am33 */
1413
1414 { 0, 0, 0, 0, {0}},
1415
1416 } ;
1417
1418 const int mn10300_num_opcodes =
1419   sizeof (mn10300_opcodes) / sizeof (mn10300_opcodes[0]);
1420
1421 \f