opcodes/m10300-opc.c

   1 /* Assemble Matsushita MN10300 instructions.
   2    Copyright (C) 1996, 1997 Free Software Foundation, Inc.
   3
   4 This program is free software; you can redistribute it and/or modify
   5 it under the terms of the GNU General Public License as published by
   6 the Free Software Foundation; either version 2 of the License, or
   7 (at your option) any later version.
   8
   9 This program is distributed in the hope that it will be useful,
  10 but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 GNU General Public License for more details.
  13
  14 You should have received a copy of the GNU General Public License
  15 along with this program; if not, write to the Free Software
  16 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  17
  18 #include "ansidecl.h"
  19 #include "opcode/mn10300.h"
  20
  21 \f
  22 const struct mn10300_operand mn10300_operands[] = {
  23 #define UNUSED  0
  24   {0, 0, 0},
  25
  26 /* dn register in the first register operand position.  */
  27 #define DN0      (UNUSED+1)
  28   {2, 0, MN10300_OPERAND_DREG},
  29
  30 /* dn register in the second register operand position.  */
  31 #define DN1      (DN0+1)
  32   {2, 2, MN10300_OPERAND_DREG},
  33
  34 /* dn register in the third register operand position.  */
  35 #define DN2      (DN1+1)
  36   {2, 4, MN10300_OPERAND_DREG},
  37
  38 /* dm register in the first register operand position.  */
  39 #define DM0      (DN2+1)
  40   {2, 0, MN10300_OPERAND_DREG},
  41
  42 /* dm register in the second register operand position.  */
  43 #define DM1      (DM0+1)
  44   {2, 2, MN10300_OPERAND_DREG},
  45
  46 /* dm register in the third register operand position.  */
  47 #define DM2      (DM1+1)
  48   {2, 4, MN10300_OPERAND_DREG},
  49
  50 /* an register in the first register operand position.  */
  51 #define AN0      (DM2+1)
  52   {2, 0, MN10300_OPERAND_AREG},
  53
  54 /* an register in the second register operand position.  */
  55 #define AN1      (AN0+1)
  56   {2, 2, MN10300_OPERAND_AREG},
  57
  58 /* an register in the third register operand position.  */
  59 #define AN2      (AN1+1)
  60   {2, 4, MN10300_OPERAND_AREG},
  61
  62 /* am register in the first register operand position.  */
  63 #define AM0      (AN2+1)
  64   {2, 0, MN10300_OPERAND_AREG},
  65
  66 /* am register in the second register operand position.  */
  67 #define AM1      (AM0+1)
  68   {2, 2, MN10300_OPERAND_AREG},
  69
  70 /* am register in the third register operand position.  */
  71 #define AM2      (AM1+1)
  72   {2, 4, MN10300_OPERAND_AREG},
  73
  74 /* 8 bit unsigned immediate which may promote to a 16bit
  75    unsigned immediate.  */
  76 #define IMM8    (AM2+1)
  77   {8, 0, MN10300_OPERAND_PROMOTE},
  78
  79 /* 16 bit unsigned immediate which may promote to a 32bit
  80    unsigned immediate.  */
  81 #define IMM16    (IMM8+1)
  82   {16, 0, MN10300_OPERAND_PROMOTE},
  83
  84 /* 16 bit pc-relative immediate which may promote to a 16bit
  85    pc-relative immediate.  */
  86 #define IMM16_PCREL    (IMM16+1)
  87   {16, 0, MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX | MN10300_OPERAND_SIGNED},
  88
  89 /* 16bit unsigned dispacement in a memory operation which
  90    may promote to a 32bit displacement.  */
  91 #define IMM16_MEM    (IMM16_PCREL+1)
  92   {16, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
  93
  94 /* 32bit immediate, high 16 bits in the main instruction
  95    word, 16bits in the extension word.
  96
  97    The "bits" field indicates how many bits are in the
  98    main instruction word for MN10300_OPERAND_SPLIT!  */
  99 #define IMM32    (IMM16_MEM+1)
 100   {16, 0, MN10300_OPERAND_SPLIT},
 101
 102 /* 32bit pc-relative offset.  */
 103 #define IMM32_PCREL    (IMM32+1)
 104   {16, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL},
 105
 106 /* 32bit memory offset.  */
 107 #define IMM32_MEM    (IMM32_PCREL+1)
 108   {16, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR},
 109
 110 /* 32bit immediate, high 16 bits in the main instruction
 111    word, 16bits in the extension word, low 16bits are left
 112    shifted 8 places.
 113
 114    The "bits" field indicates how many bits are in the
 115    main instruction word for MN10300_OPERAND_SPLIT!  */
 116 #define IMM32_LOWSHIFT8    (IMM32_MEM+1)
 117   {16, 8, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR},
 118
 119 /* 32bit immediate, high 24 bits in the main instruction
 120    word, 8 in the extension word.
 121
 122    The "bits" field indicates how many bits are in the
 123    main instruction word for MN10300_OPERAND_SPLIT!  */
 124 #define IMM32_HIGH24    (IMM32_LOWSHIFT8+1)
 125   {24, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL},
 126
 127 /* 32bit immediate, high 24 bits in the main instruction
 128    word, 8 in the extension word, low 8 bits are left
 129    shifted 16 places.
 130
 131    The "bits" field indicates how many bits are in the
 132    main instruction word for MN10300_OPERAND_SPLIT!  */
 133 #define IMM32_HIGH24_LOWSHIFT16    (IMM32_HIGH24+1)
 134   {24, 16, MN10300_OPERAND_SPLIT | MN10300_OPERAND_PCREL},
 135
 136 /* Stack pointer.  */
 137 #define SP    (IMM32_HIGH24_LOWSHIFT16+1)
 138   {8, 0, MN10300_OPERAND_SP},
 139
 140 /* Processor status word.  */
 141 #define PSW    (SP+1)
 142   {0, 0, MN10300_OPERAND_PSW},
 143
 144 /* MDR register.  */
 145 #define MDR    (PSW+1)
 146   {0, 0, MN10300_OPERAND_MDR},
 147
 148 /* Index register.  */
 149 #define DI (MDR+1)
 150   {2, 2, MN10300_OPERAND_DREG},
 151
 152 /* 8 bit signed displacement, may promote to 16bit signed dispacement.  */
 153 #define SD8    (DI+1)
 154   {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
 155
 156 /* 16 bit signed displacement, may promote to 32bit dispacement.  */
 157 #define SD16    (SD8+1)
 158   {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
 159
 160 /* 8 bit signed displacement that can not promote.  */
 161 #define SD8N    (SD16+1)
 162   {8, 0, MN10300_OPERAND_SIGNED},
 163
 164 /* 8 bit pc-relative displacement.  */
 165 #define SD8N_PCREL    (SD8N+1)
 166   {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX},
 167
 168 /* 8 bit signed displacement shifted left 8 bits in the instruction.  */
 169 #define SD8N_SHIFT8    (SD8N_PCREL+1)
 170   {8, 8, MN10300_OPERAND_SIGNED},
 171
 172 /* 8 bit signed immediate which may promote to 16bit signed immediate.  */
 173 #define SIMM8    (SD8N_SHIFT8+1)
 174   {8, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
 175
 176 /* 16 bit signed immediate which may promote to 32bit  immediate.  */
 177 #define SIMM16    (SIMM8+1)
 178   {16, 0, MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
 179
 180 /* Either an open paren or close paren.  */
 181 #define PAREN   (SIMM16+1)
 182   {0, 0, MN10300_OPERAND_PAREN},
 183
 184 /* dn register that appears in the first and second register positions.  */
 185 #define DN01     (PAREN+1)
 186   {2, 0, MN10300_OPERAND_DREG | MN10300_OPERAND_REPEATED},
 187
 188 /* an register that appears in the first and second register positions.  */
 189 #define AN01     (DN01+1)
 190   {2, 0, MN10300_OPERAND_AREG | MN10300_OPERAND_REPEATED},
 191
 192 /* 16bit pc-relative displacement which may promote to 32bit pc-relative
 193    displacement.  */
 194 #define D16_SHIFT (AN01+1)
 195   {16, 8, MN10300_OPERAND_PCREL | MN10300_OPERAND_RELAX | MN10300_OPERAND_SIGNED},
 196
 197 /* 8 bit immediate found in the extension word.  */
 198 #define IMM8E    (D16_SHIFT+1)
 199   {8, 0, MN10300_OPERAND_EXTENDED},
 200
 201 /* Register list found in the extension word shifted 8 bits left.  */
 202 #define REGSE_SHIFT8    (IMM8E+1)
 203   {8, 8, MN10300_OPERAND_EXTENDED | MN10300_OPERAND_REG_LIST},
 204
 205 /* Register list shifted 8 bits left.  */
 206 #define REGS_SHIFT8 (REGSE_SHIFT8 + 1)
 207   {8, 8, MN10300_OPERAND_REG_LIST},
 208
 209 /* Reigster list.  */
 210 #define REGS    (REGS_SHIFT8+1)
 211   {8, 0, MN10300_OPERAND_REG_LIST},
 212
 213 /* start-sanitize-am33 */
 214 /* UStack pointer.  */
 215 #define USP    (REGS+1)
 216   {0, 0, MN10300_OPERAND_USP},
 217
 218 /* SStack pointer.  */
 219 #define SSP    (USP+1)
 220   {0, 0, MN10300_OPERAND_SSP},
 221
 222 /* MStack pointer.  */
 223 #define MSP    (SSP+1)
 224   {0, 0, MN10300_OPERAND_MSP},
 225
 226 /* PC .  */
 227 #define PC    (MSP+1)
 228   {0, 0, MN10300_OPERAND_PC},
 229
 230 /* 4 bit immediate for syscall.  */
 231 #define IMM4    (PC+1)
 232   {4, 0, 0},
 233
 234 /* Processor status word.  */
 235 #define EPSW    (IMM4+1)
 236   {0, 0, MN10300_OPERAND_EPSW},
 237
 238 /* rn register in the first register operand position.  */
 239 #define RN0      (EPSW+1)
 240   {4, 0, MN10300_OPERAND_RREG},
 241
 242 /* rn register in the fourth register operand position.  */
 243 #define RN2      (RN0+1)
 244   {4, 4, MN10300_OPERAND_RREG},
 245
 246 /* rm register in the first register operand position.  */
 247 #define RM0      (RN2+1)
 248   {4, 0, MN10300_OPERAND_RREG},
 249
 250 /* rm register in the second register operand position.  */
 251 #define RM1      (RM0+1)
 252   {4, 2, MN10300_OPERAND_RREG},
 253
 254 /* rm register in the third register operand position.  */
 255 #define RM2      (RM1+1)
 256   {4, 4, MN10300_OPERAND_RREG},
 257
 258 #define RN02      (RM2+1)
 259   {4, 0, MN10300_OPERAND_RREG | MN10300_OPERAND_REPEATED},
 260
 261 #define XRN0      (RN02+1)
 262   {4, 0, MN10300_OPERAND_XRREG},
 263
 264 #define XRM2      (XRN0+1)
 265   {4, 4, MN10300_OPERAND_XRREG},
 266
 267 /* + for autoincrement */
 268 #define PLUS    (XRM2+1)
 269   {0, 0, MN10300_OPERAND_PLUS},
 270
 271 #define XRN02      (PLUS+1)
 272   {4, 0, MN10300_OPERAND_XRREG | MN10300_OPERAND_REPEATED},
 273
 274 /* Ick */
 275 #define RD0      (XRN02+1)
 276   {4, -8, MN10300_OPERAND_RREG},
 277
 278 #define RD2      (RD0+1)
 279   {4, -4, MN10300_OPERAND_RREG},
 280
 281 /* 8 unsigned dispacement in a memory operation which
 282    may promote to a 32bit displacement.  */
 283 #define IMM8_MEM    (RD2+1)
 284   {8, 0, MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
 285
 286 /* Index register.  */
 287 #define RI (IMM8_MEM+1)
 288   {4, 4, MN10300_OPERAND_RREG},
 289
 290 /* 24 bit signed displacement, may promote to 32bit dispacement.  */
 291 #define SD24    (RI+1)
 292   {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_SIGNED | MN10300_OPERAND_PROMOTE},
 293
 294 /* 24 bit unsigned immediate which may promote to a 32bit
 295    unsigned immediate.  */
 296 #define IMM24    (SD24+1)
 297   {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE},
 298
 299 /* 24 bit signed immediate which may promote to a 32bit
 300    signed immediate.  */
 301 #define SIMM24    (IMM24+1)
 302   {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE | MN10300_OPERAND_SIGNED},
 303
 304 /* 16bit unsigned dispacement in a memory operation which
 305    may promote to a 32bit displacement.  */
 306 #define IMM24_MEM    (SIMM24+1)
 307   {8, 0, MN10300_OPERAND_24BIT | MN10300_OPERAND_PROMOTE | MN10300_OPERAND_MEMADDR},
 308 /* 32bit immediate, high 24 bits in the main instruction
 309    word, 8 in the extension word.
 310
 311    The "bits" field indicates how many bits are in the
 312    main instruction word for MN10300_OPERAND_SPLIT!  */
 313 #define IMM32_HIGH8    (IMM24_MEM+1)
 314   {8, 0, MN10300_OPERAND_SPLIT},
 315
 316 /* Similarly, but a memory address.  */
 317 #define IMM32_HIGH8_MEM  (IMM32_HIGH8+1)
 318   {8, 0, MN10300_OPERAND_SPLIT | MN10300_OPERAND_MEMADDR},
 319
 320 /* rm register in the seventh register operand position.  */
 321 #define RM6      (IMM32_HIGH8_MEM+1)
 322   {4, 12, MN10300_OPERAND_RREG},
 323
 324 /* rm register in the fifth register operand position.  */
 325 #define RN4      (RM6+1)
 326   {4, 8, MN10300_OPERAND_RREG},
 327
 328 /* 4 bit immediate for dsp instructions.  */
 329 #define IMM4_2    (RN4+1)
 330   {4, 4, 0},
 331
 332 /* 4 bit immediate for dsp instructions.  */
 333 #define SIMM4_2    (IMM4_2+1)
 334   {4, 4, MN10300_OPERAND_SIGNED},
 335
 336 /* 4 bit immediate for dsp instructions.  */
 337 #define SIMM4_6    (SIMM4_2+1)
 338   {4, 12, MN10300_OPERAND_SIGNED},
 339 /* end-sanitize-am33 */
 340
 341 } ;
 342
 343 #define MEM(ADDR) PAREN, ADDR, PAREN
 344 #define MEMINC(ADDR) PAREN, ADDR, PLUS, PAREN
 345 #define MEMINC2(ADDR,INC) PAREN, ADDR, PLUS, INC, PAREN
 346 #define MEM2(ADDR1,ADDR2) PAREN, ADDR1, ADDR2, PAREN
 347 \f
 348 /* The opcode table.
 349
 350    The format of the opcode table is:
 351
 352    NAME         OPCODE          MASK            { OPERANDS }
 353
 354    NAME is the name of the instruction.
 355    OPCODE is the instruction opcode.
 356    MASK is the opcode mask; this is used to tell the disassembler
 357      which bits in the actual opcode must match OPCODE.
 358    OPERANDS is the list of operands.
 359
 360    The disassembler reads the table in order and prints the first
 361    instruction which matches, so this table is sorted to put more
 362    specific instructions before more general instructions.  It is also
 363    sorted by major opcode.  */
 364
 365 const struct mn10300_opcode mn10300_opcodes[] = {
 366 { "mov",        0x8000,      0xf000,      FMT_S1, 0,    {SIMM8, DN01}},
 367 { "mov",        0x80,        0xf0,        FMT_S0, 0,    {DM1, DN0}},
 368 { "mov",        0xf1e0,      0xfff0,      FMT_D0, 0,    {DM1, AN0}},
 369 { "mov",        0xf1d0,      0xfff0,      FMT_D0, 0,    {AM1, DN0}},
 370 { "mov",        0x9000,      0xf000,      FMT_S1, 0,    {IMM8, AN01}},
 371 { "mov",        0x90,        0xf0,        FMT_S0, 0,    {AM1, AN0}},
 372 { "mov",        0x3c,        0xfc,        FMT_S0, 0,    {SP, AN0}},
 373 { "mov",        0xf2f0,      0xfff3,      FMT_D0, 0,    {AM1, SP}},
 374 { "mov",        0xf2e4,      0xfffc,      FMT_D0, 0,    {PSW, DN0}},
 375 { "mov",        0xf2f3,      0xfff3,      FMT_D0, 0,    {DM1, PSW}},
 376 { "mov",        0xf2e0,      0xfffc,      FMT_D0, 0,    {MDR, DN0}},
 377 { "mov",        0xf2f2,      0xfff3,      FMT_D0, 0,    {DM1, MDR}},
 378 { "mov",        0x70,        0xf0,        FMT_S0, 0,    {MEM(AM0), DN1}},
 379 { "mov",        0x5800,      0xfcff,      FMT_S1, 0,    {MEM(SP), DN0}},
 380 { "mov",        0x300000,    0xfc0000,    FMT_S2, 0,    {MEM(IMM16_MEM), DN0}},
 381 { "mov",        0xf000,      0xfff0,      FMT_D0, 0,    {MEM(AM0), AN1}},
 382 { "mov",        0x5c00,      0xfcff,      FMT_S1, 0,    {MEM(SP), AN0}},
 383 { "mov",        0xfaa00000,  0xfffc0000,  FMT_D2, 0,    {MEM(IMM16_MEM), AN0}},
 384 { "mov",        0x60,        0xf0,        FMT_S0, 0,    {DM1, MEM(AN0)}},
 385 { "mov",        0x4200,      0xf3ff,      FMT_S1, 0,    {DM1, MEM(SP)}},
 386 { "mov",        0x010000,    0xf30000,    FMT_S2, 0,    {DM1, MEM(IMM16_MEM)}},
 387 { "mov",        0xf010,      0xfff0,      FMT_D0, 0,    {AM1, MEM(AN0)}},
 388 { "mov",        0x4300,      0xf3ff,      FMT_S1, 0,    {AM1, MEM(SP)}},
 389 { "mov",        0xfa800000,  0xfff30000,  FMT_D2, 0,    {AM1, MEM(IMM16_MEM)}},
 390 { "mov",        0x5c00,      0xfc00,      FMT_S1, 0,    {MEM2(IMM8, SP), AN0}},
 391 { "mov",        0xf80000,    0xfff000,    FMT_D1, 0,    {MEM2(SD8, AM0), DN1}},
 392 { "mov",        0xfa000000,  0xfff00000,  FMT_D2, 0,    {MEM2(SD16, AM0), DN1}},
 393 { "mov",        0x5800,      0xfc00,      FMT_S1, 0,    {MEM2(IMM8, SP), DN0}},
 394 { "mov",        0xfab40000,  0xfffc0000,  FMT_D2, 0,    {MEM2(IMM16, SP), DN0}},
 395 { "mov",        0xf300,      0xffc0,      FMT_D0, 0,    {MEM2(DI, AM0), DN2}},
 396 { "mov",        0xf82000,    0xfff000,    FMT_D1, 0,    {MEM2(SD8,AM0), AN1}},
 397 { "mov",        0xfa200000,  0xfff00000,  FMT_D2, 0,    {MEM2(SD16, AM0), AN1}},
 398 { "mov",        0xfab00000,  0xfffc0000,  FMT_D2, 0,    {MEM2(IMM16, SP), AN0}},
 399 { "mov",        0xf380,      0xffc0,      FMT_D0, 0,    {MEM2(DI, AM0), AN2}},
 400 { "mov",        0x4300,      0xf300,      FMT_S1, 0,    {AM1, MEM2(IMM8, SP)}},
 401 { "mov",        0xf81000,    0xfff000,    FMT_D1, 0,    {DM1, MEM2(SD8, AN0)}},
 402 { "mov",        0xfa100000,  0xfff00000,  FMT_D2, 0,    {DM1, MEM2(SD16, AN0)}},
 403 { "mov",        0x4200,      0xf300,      FMT_S1, 0,    {DM1, MEM2(IMM8, SP)}},
 404 { "mov",        0xfa910000,  0xfff30000,  FMT_D2, 0,    {DM1, MEM2(IMM16, SP)}},
 405 { "mov",        0xf340,      0xffc0,      FMT_D0, 0,    {DM2, MEM2(DI, AN0)}},
 406 { "mov",        0xf83000,    0xfff000,    FMT_D1, 0,    {AM1, MEM2(SD8, AN0)}},
 407 { "mov",        0xfa300000,  0xfff00000,  FMT_D2, 0,    {AM1, MEM2(SD16, AN0)}},
 408 { "mov",        0xfa900000,  0xfff30000,  FMT_D2, 0,    {AM1, MEM2(IMM16, SP)}},
 409 { "mov",        0xf3c0,      0xffc0,      FMT_D0, 0,    {AM2, MEM2(DI, AN0)}},
 410
 411 /* start-sanitize-am33 */
 412 { "mov",        0xf020,      0xfffc,      FMT_D0, AM33, {USP, AN0}},
 413 { "mov",        0xf024,      0xfffc,      FMT_D0, AM33, {SSP, AN0}},
 414 { "mov",        0xf028,      0xfffc,      FMT_D0, AM33, {MSP, AN0}},
 415 { "mov",        0xf02c,      0xfffc,      FMT_D0, AM33, {PC, AN0}},
 416 { "mov",        0xf030,      0xfff3,      FMT_D0, AM33, {AN1, USP}},
 417 { "mov",        0xf031,      0xfff3,      FMT_D0, AM33, {AN1, SSP}},
 418 { "mov",        0xf032,      0xfff3,      FMT_D0, AM33, {AN1, MSP}},
 419 { "mov",        0xf2ec,      0xfffc,      FMT_D0, AM33, {EPSW, DN0}},
 420 { "mov",        0xf2f1,      0xfff3,      FMT_D0, AM33, {DM1, EPSW}},
 421 { "mov",        0xf500,      0xffc0,      FMT_D0, AM33, {AM2, RN0}},
 422 { "mov",        0xf540,      0xffc0,      FMT_D0, AM33, {DM2, RN0}},
 423 { "mov",        0xf580,      0xffc0,      FMT_D0, AM33, {RM1, AN0}},
 424 { "mov",        0xf5c0,      0xffc0,      FMT_D0, AM33, {RM1, DN0}},
 425 { "mov",        0xf90800,    0xffff00,    FMT_D6, AM33, {RM2, RN0}},
 426 { "mov",        0xf9e800,    0xffff00,    FMT_D6, AM33, {XRM2, RN0}},
 427 { "mov",        0xf9f800,    0xffff00,    FMT_D6, AM33, {RM2, XRN0}},
 428 { "mov",        0xf90a00,    0xffff00,    FMT_D6, AM33, {MEM(RM0), RN2}},
 429 { "mov",        0xf98a00,    0xffff0f,    FMT_D6, AM33, {MEM(SP), RN2}},
 430 { "mov",        0xf96a00,    0xffff00,    FMT_D6, AM33, {MEMINC(RM0), RN2}},
 431 { "mov",        0xfb0e0000,  0xffff0f00,  FMT_D7, AM33, {MEM(IMM8_MEM), RN2}},
 432 { "mov",        0xfd0e0000,  0xffff0f00,  FMT_D8, AM33, {MEM(IMM24_MEM), RN2}},
 433 { "mov",        0xf91a00,    0xffff00,    FMT_D6, AM33, {RM2, MEM(RN0)}},
 434 { "mov",        0xf99a00,    0xffff0f,    FMT_D6, AM33, {RM2, MEM(SP)}},
 435 { "mov",        0xf97a00,    0xffff00,    FMT_D6, AM33, {RM2, MEMINC(RN0)}},
 436 { "mov",        0xfb1e0000,  0xffff0f00,  FMT_D7, AM33, {RM2, MEM(IMM8_MEM)}},
 437 { "mov",        0xfd1e0000,  0xffff0f00,  FMT_D8, AM33, {RM2, MEM(IMM24_MEM)}},
 438 { "mov",        0xfb0a0000,  0xffff0000,  FMT_D7, AM33, {MEM2(SD8, RM0), RN2}},
 439 { "mov",        0xfd0a0000,  0xffff0000,  FMT_D8, AM33, {MEM2(SD24, RM0), RN2}},
 440 { "mov",        0xfb8e0000,  0xffff000f,  FMT_D7, AM33, {MEM2(RI, RM0), RD2}},
 441 { "mov",        0xfb1a0000,  0xffff0000,  FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}},
 442 { "mov",        0xfd1a0000,  0xffff0000,  FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}},
 443 { "mov",        0xfb8a0000,  0xffff0f00,  FMT_D7, AM33, {MEM2(SD8, SP), RN2}},
 444 { "mov",        0xfd8a0000,  0xffff0f00,  FMT_D8, AM33, {MEM2(SD24, SP), RN2}},
 445 { "mov",        0xfb9a0000,  0xffff0f00,  FMT_D7, AM33, {RM2, MEM2(SD8, SP)}},
 446 { "mov",        0xfd9a0000,  0xffff0f00,  FMT_D8, AM33, {RM2, MEM2(SD24, SP)}},
 447 { "mov",        0xfb9e0000,  0xffff000f,  FMT_D7, AM33, {RD2, MEM2(RI, RN0)}},
 448 { "mov",        0xfb6a0000,  0xffff0000,  FMT_D7, AM33, {MEMINC2 (RM0, SIMM8),
 449                                                          RN2}},
 450 { "mov",        0xfb7a0000,  0xffff0000,  FMT_D7, AM33, {RM2,
 451                                                          MEMINC2 (RN0, SIMM8)}},
 452 { "mov",        0xfd6a0000,  0xffff0000,  FMT_D8, AM33, {MEMINC2 (RM0, IMM24),
 453                                                          RN2}},
 454 { "mov",        0xfd7a0000,  0xffff0000,  FMT_D8, AM33, {RM2,
 455                                                          MEMINC2 (RN0, IMM24)}},
 456 { "mov",        0xfe6a0000,  0xffff0000,  FMT_D9, AM33, {
 457                                                  MEMINC2 (RM0, IMM32_HIGH8),
 458                                                  RN2}},
 459 { "mov",        0xfe7a0000,  0xffff0000,  FMT_D9, AM33, {RN2,
 460                                                  MEMINC2 (RM0, IMM32_HIGH8)}},
 461 /* end-sanitize-am33 */
 462 /* These must come after most of the other move instructions to avoid matching
 463    a symbolic name with IMMxx operands.  Ugh.  */
 464 { "mov",        0x2c0000,    0xfc0000,    FMT_S2, 0,    {SIMM16, DN0}},
 465 { "mov",        0xfccc0000,  0xfffc0000,  FMT_D4, 0,    {IMM32, DN0}},
 466 { "mov",        0x240000,    0xfc0000,    FMT_S2, 0,    {IMM16, AN0}},
 467 { "mov",        0xfcdc0000,  0xfffc0000,  FMT_D4, 0,    {IMM32, AN0}},
 468 { "mov",        0xfca40000,  0xfffc0000,  FMT_D4, 0,    {MEM(IMM32_MEM), DN0}},
 469 { "mov",        0xfca00000,  0xfffc0000,  FMT_D4, 0,    {MEM(IMM32_MEM), AN0}},
 470 { "mov",        0xfc810000,  0xfff30000,  FMT_D4, 0,    {DM1, MEM(IMM32_MEM)}},
 471 { "mov",        0xfc800000,  0xfff30000,  FMT_D4, 0,    {AM1, MEM(IMM32_MEM)}},
 472 { "mov",        0xfc000000,  0xfff00000,  FMT_D4, 0,    {MEM2(IMM32,AM0), DN1}},
 473 { "mov",        0xfcb40000,  0xfffc0000,  FMT_D4, 0,    {MEM2(IMM32, SP), DN0}},
 474 { "mov",        0xfc200000,  0xfff00000,  FMT_D4, 0,    {MEM2(IMM32,AM0), AN1}},
 475 { "mov",        0xfcb00000,  0xfffc0000,  FMT_D4, 0,    {MEM2(IMM32, SP), AN0}},
 476 { "mov",        0xfc100000,  0xfff00000,  FMT_D4, 0,    {DM1, MEM2(IMM32,AN0)}},
 477 { "mov",        0xfc910000,  0xfff30000,  FMT_D4, 0,    {DM1, MEM2(IMM32, SP)}},
 478 { "mov",        0xfc300000,  0xfff00000,  FMT_D4, 0,    {AM1, MEM2(IMM32,AN0)}},
 479 { "mov",        0xfc900000,  0xfff30000,  FMT_D4, 0,    {AM1, MEM2(IMM32, SP)}},
 480 /* These non-promoting variants need to come after all the other memory
 481    moves.  */
 482 { "mov",        0xf8f000,    0xfffc00,    FMT_D1, AM30, {MEM2(SD8N, AM0), SP}},
 483 { "mov",        0xf8f400,    0xfffc00,    FMT_D1, AM30, {SP, MEM2(SD8N, AN0)}},
 484 /* start-sanitize-am33 */
 485 /* These are the same as the previous non-promoting versions.  The am33
 486    does not have restrictions on the offsets used to load/store the stack
 487    pointer.  */
 488 { "mov",        0xf8f000,    0xfffc00,    FMT_D1, AM33, {MEM2(SD8, AM0), SP}},
 489 { "mov",        0xf8f400,    0xfffc00,    FMT_D1, AM33, {SP, MEM2(SD8, AN0)}},
 490 /* These must come last so that we favor shorter move instructions for
 491    loading immediates into d0-d3/a0-a3.  */
 492 { "mov",        0xfb080000,  0xffff0000, FMT_D7, AM33,  {SIMM8, RN02}},
 493 { "mov",        0xfd080000,  0xffff0000, FMT_D8, AM33,  {SIMM24, RN02}},
 494 { "mov",        0xfe080000,  0xffff0000, FMT_D9, AM33,  {IMM32_HIGH8, RN02}},
 495 { "mov",        0xfbf80000,  0xffff0000, FMT_D7, AM33,  {SIMM8, XRN02}},
 496 { "mov",        0xfdf80000,  0xffff0000, FMT_D8, AM33,  {SIMM24, XRN02}},
 497 { "mov",        0xfef80000,  0xffff0000, FMT_D9, AM33,  {IMM32_HIGH8, XRN02}},
 498 { "mov",        0xfe0e0000,  0xffff0f00,  FMT_D9, AM33, {MEM(IMM32_HIGH8_MEM),
 499                                                          RN2}},
 500 { "mov",        0xfe1e0000,  0xffff0f00,  FMT_D9, AM33, {RM2,
 501                                                          MEM(IMM32_HIGH8_MEM)}},
 502 { "mov",        0xfe0a0000,  0xffff0000,  FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0),
 503                                                          RN2}},
 504 { "mov",        0xfe1a0000,  0xffff0000,  FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8,
 505                                                                    RN0)}},
 506 { "mov",        0xfe8a0000,  0xffff0f00,  FMT_D9, AM33, {MEM2(IMM32_HIGH8, SP),
 507                                                          RN2}},
 508 { "mov",        0xfe9a0000,  0xffff0f00,  FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8,
 509                                                                    SP)}},
 510 /* end-sanitize-am33 */
 511
 512 /* start-sanitize-am33 */
 513 { "movu",       0xfb180000,  0xffff0000, FMT_D7, AM33,  {IMM8, RN02}},
 514 { "movu",       0xfd180000,  0xffff0000, FMT_D8, AM33,  {IMM24, RN02}},
 515 { "movu",       0xfe180000,  0xffff0000, FMT_D9, AM33,  {IMM32_HIGH8, RN02}},
 516 /* end-sanitize-am33 */
 517
 518 /* start-sanitize-am33 */
 519 { "mcst9",      0xf630,      0xfff0,     FMT_D0, AM33,  {DN01}},
 520 { "mcst48",     0xf660,      0xfff0,     FMT_D0, AM33,  {DN01}},
 521 { "swap",       0xf680,      0xfff0,     FMT_D0, AM33,  {DM1, DN0}},
 522 { "swap",       0xf9cb00,    0xffff00,   FMT_D6, AM33,  {RM2, RN0}},
 523 { "swaph",      0xf690,      0xfff0,     FMT_D0, AM33,  {DM1, DN0}},
 524 { "swaph",      0xf9db00,    0xffff00,   FMT_D6, AM33,  {RM2, RN0}},
 525 { "getchx",     0xf6c0,      0xfff0,     FMT_D0, AM33,  {DN01}},
 526 { "getclx",     0xf6d0,      0xfff0,     FMT_D0, AM33,  {DN01}},
 527 { "mac",        0xfb0f0000,  0xffff0000, FMT_D7, AM33,  {RM2, RN0, RD2, RD0}},
 528 { "mac",        0xf90b00,    0xffff00,   FMT_D6, AM33,  {RM2, RN0}},
 529 { "mac",        0xfb0b0000,  0xffff0000, FMT_D7, AM33,  {SIMM8, RN02}},
 530 { "mac",        0xfd0b0000,  0xffff0000, FMT_D8, AM33,  {SIMM24, RN02}},
 531 { "mac",        0xfe0b0000,  0xffff0000, FMT_D9, AM33,  {IMM32_HIGH8, RN02}},
 532 { "macu",       0xfb1f0000,  0xffff0000, FMT_D7, AM33,  {RM2, RN0, RD2, RD0}},
 533 { "macu",       0xf91b00,    0xffff00,   FMT_D6, AM33,  {RM2, RN0}},
 534 { "macu",       0xfb1b0000,  0xffff0000, FMT_D7, AM33,  {IMM8, RN02}},
 535 { "macu",       0xfd1b0000,  0xffff0000, FMT_D8, AM33,  {IMM24, RN02}},
 536 { "macu",       0xfe1b0000,  0xffff0000, FMT_D9, AM33,  {IMM32_HIGH8, RN02}},
 537 { "macb",       0xfb2f0000,  0xffff000f, FMT_D7, AM33,  {RM2, RN0, RD2}},
 538 { "macb",       0xf92b00,    0xffff00,   FMT_D6, AM33,  {RM2, RN0}},
 539 { "macb",       0xfb2b0000,  0xffff0000, FMT_D7, AM33,  {SIMM8, RN02}},
 540 { "macb",       0xfd2b0000,  0xffff0000, FMT_D8, AM33,  {SIMM24, RN02}},
 541 { "macb",       0xfe2b0000,  0xffff0000, FMT_D9, AM33,  {IMM32_HIGH8, RN02}},
 542 { "macbu",      0xfb3f0000,  0xffff000f, FMT_D7, AM33,  {RM2, RN0, RD2}},
 543 { "macbu",      0xf93b00,    0xffff00,   FMT_D6, AM33,  {RM2, RN0}},
 544 { "macbu",      0xfb3b0000,  0xffff0000, FMT_D7, AM33,  {IMM8, RN02}},
 545 { "macbu",      0xfd3b0000,  0xffff0000, FMT_D8, AM33,  {IMM24, RN02}},
 546 { "macbu",      0xfe3b0000,  0xffff0000, FMT_D9, AM33,  {IMM32_HIGH8, RN02}},
 547 { "mach",       0xfb4f0000,  0xffff0000, FMT_D7, AM33,  {RM2, RN0, RD2, RD0}},
 548 { "mach",       0xf94b00,    0xffff00,   FMT_D6, AM33,  {RM2, RN0}},
 549 { "mach",       0xfb4b0000,  0xffff0000, FMT_D7, AM33,  {SIMM8, RN02}},
 550 { "mach",       0xfd4b0000,  0xffff0000, FMT_D8, AM33,  {SIMM24, RN02}},
 551 { "mach",       0xfe4b0000,  0xffff0000, FMT_D9, AM33,  {IMM32_HIGH8, RN02}},
 552 { "machu",      0xfb5f0000,  0xffff0000, FMT_D7, AM33,  {RM2, RN0, RD2, RD0}},
 553 { "machu",      0xf95b00,    0xffff00,   FMT_D6, AM33,  {RM2, RN0}},
 554 { "machu",      0xfb5b0000,  0xffff0000, FMT_D7, AM33,  {IMM8, RN02}},
 555 { "machu",      0xfd5b0000,  0xffff0000, FMT_D8, AM33,  {IMM24, RN02}},
 556 { "machu",      0xfe5b0000,  0xffff0000, FMT_D9, AM33,  {IMM32_HIGH8, RN02}},
 557 { "dmach",      0xfb6f0000,  0xffff000f, FMT_D7, AM33,  {RM2, RN0, RD2}},
 558 { "dmach",      0xf96b00,    0xffff00,   FMT_D6, AM33,  {RM2, RN0}},
 559 { "dmach",      0xfe6b0000,  0xffff0000, FMT_D9, AM33,  {IMM32_HIGH8, RN02}},
 560 { "dmachu",     0xfb7f0000,  0xffff000f, FMT_D7, AM33,  {RM2, RN0, RD2}},
 561 { "dmachu",     0xf97b00,    0xffff00,   FMT_D6, AM33,  {RM2, RN0}},
 562 { "dmachu",     0xfe7b0000,  0xffff0000, FMT_D9, AM33,  {IMM32_HIGH8, RN02}},
 563 { "dmulh",      0xfb8f0000,  0xffff0000, FMT_D7, AM33,  {RM2, RN0, RD2, RD0}},
 564 { "dmulh",      0xf98b00,    0xffff00,   FMT_D6, AM33,  {RM2, RN0}},
 565 { "dmulh",      0xfe8b0000,  0xffff0000, FMT_D9, AM33,  {IMM32_HIGH8, RN02}},
 566 { "dmulhu",     0xfb9f0000,  0xffff0000, FMT_D7, AM33,  {RM2, RN0, RD2, RD0}},
 567 { "dmulhu",     0xf99b00,    0xffff00,   FMT_D6, AM33,  {RM2, RN0}},
 568 { "dmulhu",     0xfe9b0000,  0xffff0000, FMT_D9, AM33,  {IMM32_HIGH8, RN02}},
 569 { "mcste",      0xf9bb00,    0xffff00,   FMT_D6, AM33,  {RM2, RN0}},
 570 { "mcste",      0xfbbb0000,  0xffff0000, FMT_D7, AM33,  {IMM8, RN02}},
 571 { "swhw",       0xf9eb00,    0xffff00,   FMT_D6, AM33,  {RM2, RN0}},
 572 /* end-sanitize-am33 */
 573
 574 { "movbu",      0xf040,      0xfff0,     FMT_D0, 0,     {MEM(AM0), DN1}},
 575 { "movbu",      0xf84000,    0xfff000,   FMT_D1, 0,     {MEM2(SD8, AM0), DN1}},
 576 { "movbu",      0xfa400000,  0xfff00000, FMT_D2, 0,     {MEM2(SD16, AM0), DN1}},
 577 { "movbu",      0xf8b800,    0xfffcff,   FMT_D1, 0,     {MEM(SP), DN0}},
 578 { "movbu",      0xf8b800,    0xfffc00,   FMT_D1, 0,     {MEM2(IMM8, SP), DN0}},
 579 { "movbu",      0xfab80000,  0xfffc0000, FMT_D2, 0,     {MEM2(IMM16, SP), DN0}},
 580 { "movbu",      0xf400,      0xffc0,     FMT_D0, 0,     {MEM2(DI, AM0), DN2}},
 581 { "movbu",      0x340000,    0xfc0000,   FMT_S2, 0,     {MEM(IMM16_MEM), DN0}},
 582 { "movbu",      0xf050,      0xfff0,     FMT_D0, 0,     {DM1, MEM(AN0)}},
 583 { "movbu",      0xf85000,    0xfff000,   FMT_D1, 0,     {DM1, MEM2(SD8, AN0)}},
 584 { "movbu",      0xfa500000,  0xfff00000, FMT_D2, 0,     {DM1, MEM2(SD16, AN0)}},
 585 { "movbu",      0xf89200,    0xfff3ff,   FMT_D1, 0,     {DM1, MEM(SP)}},
 586 { "movbu",      0xf89200,    0xfff300,   FMT_D1, 0,     {DM1, MEM2(IMM8, SP)}},
 587 { "movbu",      0xfa920000,  0xfff30000, FMT_D2, 0,     {DM1, MEM2(IMM16, SP)}},
 588 { "movbu",      0xf440,      0xffc0,     FMT_D0, 0,     {DM2, MEM2(DI, AN0)}},
 589 { "movbu",      0x020000,    0xf30000,   FMT_S2, 0,     {DM1, MEM(IMM16_MEM)}},
 590 /* start-sanitize-am33 */
 591 { "movbu",      0xf92a00,    0xffff00,   FMT_D6, AM33,  {MEM(RM0), RN2}},
 592 { "movbu",      0xf93a00,    0xffff00,   FMT_D6, AM33,  {RM2, MEM(RN0)}},
 593 { "movbu",      0xf9aa00,    0xffff0f,   FMT_D6, AM33,  {MEM(SP), RN2}},
 594 { "movbu",      0xf9ba00,    0xffff0f,   FMT_D6, AM33,  {RM2, MEM(SP)}},
 595 { "movbu",      0xfb2a0000,  0xffff0000, FMT_D7, AM33,  {MEM2(SD8, RM0), RN2}},
 596 { "movbu",      0xfd2a0000,  0xffff0000, FMT_D8, AM33,  {MEM2(SD24, RM0), RN2}},
 597 { "movbu",      0xfb3a0000,  0xffff0000, FMT_D7, AM33,  {RM2, MEM2(SD8, RN0)}},
 598 { "movbu",      0xfd3a0000,  0xffff0000, FMT_D8, AM33,  {RM2, MEM2(SD24, RN0)}},
 599 { "movbu",      0xfbaa0000,  0xffff0f00, FMT_D7, AM33,  {MEM2(SD8, SP), RN2}},
 600 { "movbu",      0xfdaa0000,  0xffff0f00, FMT_D8, AM33,  {MEM2(SD24, SP), RN2}},
 601 { "movbu",      0xfbba0000,  0xffff0f00, FMT_D7, AM33,  {RM2, MEM2(SD8, SP)}},
 602 { "movbu",      0xfdba0000,  0xffff0f00, FMT_D8, AM33,  {RM2, MEM2(SD24, SP)}},
 603 { "movbu",      0xfb2e0000,  0xffff0f00, FMT_D7, AM33,  {MEM(IMM8_MEM), RN2}},
 604 { "movbu",      0xfd2e0000,  0xffff0f00, FMT_D8, AM33,  {MEM(IMM24_MEM), RN2}},
 605 { "movbu",      0xfb3e0000,  0xffff0f00, FMT_D7, AM33,  {RM2, MEM(IMM8_MEM)}},
 606 { "movbu",      0xfd3e0000,  0xffff0f00, FMT_D8, AM33,  {RM2, MEM(IMM24_MEM)}},
 607 { "movbu",      0xfbae0000,  0xffff000f, FMT_D7, AM33,  {MEM2(RI, RM0), RD2}},
 608 { "movbu",      0xfbbe0000,  0xffff000f, FMT_D7, AM33,  {RD2, MEM2(RI, RN0)}},
 609 /* end-sanitize-am33 */
 610 { "movbu",      0xfc400000,  0xfff00000, FMT_D4, 0,     {MEM2(IMM32,AM0), DN1}},
 611 { "movbu",      0xfcb80000,  0xfffc0000, FMT_D4, 0,     {MEM2(IMM32, SP), DN0}},
 612 { "movbu",      0xfca80000,  0xfffc0000, FMT_D4, 0,     {MEM(IMM32_MEM), DN0}},
 613 { "movbu",      0xfc500000,  0xfff00000, FMT_D4, 0,     {DM1, MEM2(IMM32,AN0)}},
 614 { "movbu",      0xfc920000,  0xfff30000, FMT_D4, 0,     {DM1, MEM2(IMM32, SP)}},
 615 { "movbu",      0xfc820000,  0xfff30000, FMT_D4, 0,     {DM1, MEM(IMM32_MEM)}},
 616 /* start-sanitize-am33 */
 617 { "movbu",      0xfe2a0000,  0xffff0000, FMT_D9, AM33,  {MEM2(IMM32_HIGH8,RM0),
 618                                                          RN2}},
 619 { "movbu",      0xfe3a0000,  0xffff0000, FMT_D9, AM33,  {RM2, MEM2(IMM32_HIGH8,
 620                                                                    RN0)}},
 621 { "movbu",      0xfeaa0000,  0xffff0f00, FMT_D9, AM33,  {MEM2(IMM32_HIGH8,SP),
 622                                                          RN2}},
 623 { "movbu",      0xfeba0000,  0xffff0f00, FMT_D9, AM33,  {RM2, MEM2(IMM32_HIGH8,
 624                                                                    SP)}},
 625 { "movbu",      0xfe2e0000,  0xffff0f00, FMT_D9, AM33,  {MEM(IMM32_HIGH8_MEM),
 626                                                          RN2}},
 627 { "movbu",      0xfe3e0000,  0xffff0f00, FMT_D9, AM33,  {RM2,
 628                                                          MEM(IMM32_HIGH8_MEM)}},
 629 /* end-sanitize-am33 */
 630
 631 { "movhu",      0xf060,      0xfff0,     FMT_D0, 0,     {MEM(AM0), DN1}},
 632 { "movhu",      0xf86000,    0xfff000,   FMT_D1, 0,     {MEM2(SD8, AM0), DN1}},
 633 { "movhu",      0xfa600000,  0xfff00000, FMT_D2, 0,     {MEM2(SD16, AM0), DN1}},
 634 { "movhu",      0xf8bc00,    0xfffcff,   FMT_D1, 0,     {MEM(SP), DN0}},
 635 { "movhu",      0xf8bc00,    0xfffc00,   FMT_D1, 0,     {MEM2(IMM8, SP), DN0}},
 636 { "movhu",      0xfabc0000,  0xfffc0000, FMT_D2, 0,     {MEM2(IMM16, SP), DN0}},
 637 { "movhu",      0xf480,      0xffc0,     FMT_D0, 0,     {MEM2(DI, AM0), DN2}},
 638 { "movhu",      0x380000,    0xfc0000,   FMT_S2, 0,     {MEM(IMM16_MEM), DN0}},
 639 { "movhu",      0xf070,      0xfff0,     FMT_D0, 0,     {DM1, MEM(AN0)}},
 640 { "movhu",      0xf87000,    0xfff000,   FMT_D1, 0,     {DM1, MEM2(SD8, AN0)}},
 641 { "movhu",      0xfa700000,  0xfff00000, FMT_D2, 0,     {DM1, MEM2(SD16, AN0)}},
 642 { "movhu",      0xf89300,    0xfff3ff,   FMT_D1, 0,     {DM1, MEM(SP)}},
 643 { "movhu",      0xf89300,    0xfff300,   FMT_D1, 0,     {DM1, MEM2(IMM8, SP)}},
 644 { "movhu",      0xfa930000,  0xfff30000, FMT_D2, 0,     {DM1, MEM2(IMM16, SP)}},
 645 { "movhu",      0xf4c0,      0xffc0,     FMT_D0, 0,     {DM2, MEM2(DI, AN0)}},
 646 { "movhu",      0x030000,    0xf30000,   FMT_S2, 0,     {DM1, MEM(IMM16_MEM)}},
 647 /* start-sanitize-am33 */
 648 { "movhu",      0xf94a00,    0xffff00,   FMT_D6, AM33,  {MEM(RM0), RN2}},
 649 { "movhu",      0xf95a00,    0xffff00,   FMT_D6, AM33,  {RM2, MEM(RN0)}},
 650 { "movhu",      0xf9ca00,    0xffff0f,   FMT_D6, AM33,  {MEM(SP), RN2}},
 651 { "movhu",      0xf9da00,    0xffff0f,   FMT_D6, AM33,  {RM2, MEM(SP)}},
 652 { "movhu",      0xf9ea00,    0xffff00,   FMT_D6, AM33,  {MEMINC(RM0), RN2}},
 653 { "movhu",      0xf9fa00,    0xffff00,   FMT_D6, AM33,  {RM2, MEMINC(RN0)}},
 654 { "movhu",      0xfb4a0000,  0xffff0000, FMT_D7, AM33,  {MEM2(SD8, RM0), RN2}},
 655 { "movhu",      0xfd4a0000,  0xffff0000, FMT_D8, AM33,  {MEM2(SD24, RM0), RN2}},
 656 { "movhu",      0xfb5a0000,  0xffff0000, FMT_D7, AM33,  {RM2, MEM2(SD8, RN0)}},
 657 { "movhu",      0xfd5a0000,  0xffff0000, FMT_D8, AM33,  {RM2, MEM2(SD24, RN0)}},
 658 { "movhu",      0xfbca0000,  0xffff0f00, FMT_D7, AM33,  {MEM2(SD8, SP), RN2}},
 659 { "movhu",      0xfdca0000,  0xffff0f00, FMT_D8, AM33,  {MEM2(SD24, SP), RN2}},
 660 { "movhu",      0xfbda0000,  0xffff0f00, FMT_D7, AM33,  {RM2, MEM2(SD8, SP)}},
 661 { "movhu",      0xfdda0000,  0xffff0f00, FMT_D8, AM33,  {RM2, MEM2(SD24, SP)}},
 662 { "movhu",      0xfb4e0000,  0xffff0f00, FMT_D7, AM33,  {MEM(IMM8_MEM), RN2}},
 663 { "movhu",      0xfd4e0000,  0xffff0f00, FMT_D8, AM33,  {MEM(IMM24_MEM), RN2}},
 664 { "movhu",      0xfbce0000,  0xffff000f, FMT_D7, AM33,  {MEM2(RI, RM0), RD2}},
 665 { "movhu",      0xfbde0000,  0xffff000f, FMT_D7, AM33,  {RD2, MEM2(RI, RN0)}},
 666 /* end-sanitize-am33 */
 667 { "movhu",      0xfc600000,  0xfff00000, FMT_D4, 0,     {MEM2(IMM32,AM0), DN1}},
 668 { "movhu",      0xfcbc0000,  0xfffc0000, FMT_D4, 0,     {MEM2(IMM32, SP), DN0}},
 669 { "movhu",      0xfcac0000,  0xfffc0000, FMT_D4, 0,     {MEM(IMM32_MEM), DN0}},
 670 { "movhu",      0xfc700000,  0xfff00000, FMT_D4, 0,     {DM1, MEM2(IMM32,AN0)}},
 671 { "movhu",      0xfc930000,  0xfff30000, FMT_D4, 0,     {DM1, MEM2(IMM32, SP)}},
 672 { "movhu",      0xfc830000,  0xfff30000, FMT_D4, 0,     {DM1, MEM(IMM32_MEM)}},
 673 /* start-sanitize-am33 */
 674 { "movhu",      0xfe4a0000,  0xffff0000, FMT_D9, AM33,  {MEM2(IMM32_HIGH8,RM0),
 675                                                          RN2}},
 676 { "movhu",      0xfe5a0000,  0xffff0000, FMT_D9, AM33,  {RM2, MEM2(IMM32_HIGH8,
 677                                                                    RN0)}},
 678 { "movhu",      0xfeca0000,  0xffff0f00, FMT_D9, AM33,  {MEM2(IMM32_HIGH8, SP),
 679                                                          RN2}},
 680 { "movhu",      0xfeda0000,  0xffff0f00, FMT_D9, AM33,  {RM2, MEM2(IMM32_HIGH8,
 681                                                                    SP)}},
 682 { "movhu",      0xfe4e0000,  0xffff0f00, FMT_D9, AM33,  {MEM(IMM32_HIGH8_MEM),
 683                                                          RN2}},
 684 { "movhu",      0xfb5e0000,  0xffff0f00, FMT_D7, AM33,  {RM2, MEM(IMM8_MEM)}},
 685 { "movhu",      0xfd5e0000,  0xffff0f00, FMT_D8, AM33,  {RM2, MEM(IMM24_MEM)}},
 686 { "movhu",      0xfe5e0000,  0xffff0f00, FMT_D9, AM33,  {RM2,
 687                                                          MEM(IMM32_HIGH8_MEM)}},
 688 { "movhu",      0xfbea0000,  0xffff0000,  FMT_D7, AM33, {MEMINC2 (RM0, SIMM8),
 689                                                          RN2}},
 690 { "movhu",      0xfbfa0000,  0xffff0000,  FMT_D7, AM33, {RM2,
 691                                                          MEMINC2 (RN0, SIMM8)}},
 692 { "movhu",      0xfdea0000,  0xffff0000,  FMT_D8, AM33, {MEMINC2 (RM0, IMM24),
 693                                                          RN2}},
 694 { "movhu",      0xfdfa0000,  0xffff0000,  FMT_D8, AM33, {RM2,
 695                                                          MEMINC2 (RN0, IMM24)}},
 696 { "movhu",      0xfeea0000,  0xffff0000,  FMT_D9, AM33, {
 697                                                  MEMINC2 (RM0, IMM32_HIGH8),
 698                                                  RN2}},
 699 { "movhu",      0xfefa0000,  0xffff0000,  FMT_D9, AM33, {RN2,
 700                                                  MEMINC2 (RM0, IMM32_HIGH8)}},
 701 /* end-sanitize-am33 */
 702
 703 { "ext",        0xf2d0,      0xfffc,     FMT_D0, 0,     {DN0}},
 704 /* start-sanitize-am33 */
 705 { "ext",        0xf91800,    0xffff00,   FMT_D6, AM33,  {RN02}},
 706 /* end-sanitize-am33 */
 707
 708 /* start-sanitize-am33 */
 709 { "extb",       0xf92800,    0xffff00,   FMT_D6, AM33,  {RM2, RN0}},
 710 /* end-sanitize-am33 */
 711 { "extb",       0x10,        0xfc,       FMT_S0, 0,     {DN0}},
 712 /* start-sanitize-am33 */
 713 { "extb",       0xf92800,    0xffff00,   FMT_D6, AM33,  {RN02}},
 714 /* end-sanitize-am33 */
 715
 716 /* start-sanitize-am33 */
 717 { "extbu",      0xf93800,    0xffff00,   FMT_D6, AM33,  {RM2, RN0}},
 718 /* end-sanitize-am33 */
 719 { "extbu",      0x14,        0xfc,       FMT_S0, 0,     {DN0}},
 720 /* start-sanitize-am33 */
 721 { "extbu",      0xf93800,    0xffff00,   FMT_D6, AM33,  {RN02}},
 722 /* end-sanitize-am33 */
 723
 724 /* start-sanitize-am33 */
 725 { "exth",       0xf94800,    0xffff00,   FMT_D6, AM33,  {RM2, RN0}},
 726 /* end-sanitize-am33 */
 727 { "exth",       0x18,        0xfc,       FMT_S0, 0,     {DN0}},
 728 /* start-sanitize-am33 */
 729 { "exth",       0xf94800,    0xffff00,   FMT_D6, AM33,  {RN02}},
 730 /* end-sanitize-am33 */
 731
 732 /* start-sanitize-am33 */
 733 { "exthu",      0xf95800,    0xffff00,   FMT_D6, AM33,  {RM2, RN0}},
 734 /* end-sanitize-am33 */
 735 { "exthu",      0x1c,        0xfc,       FMT_S0, 0,     {DN0}},
 736 /* start-sanitize-am33 */
 737 { "exthu",      0xf95800,    0xffff00,   FMT_D6, AM33,  {RN02}},
 738 /* end-sanitize-am33 */
 739
 740 { "movm",       0xce00,      0xff00,     FMT_S1, 0,     {MEM(SP), REGS}},
 741 { "movm",       0xcf00,      0xff00,     FMT_S1, 0,     {REGS, MEM(SP)}},
 742 /* start-sanitize-am33 */
 743 { "movm",       0xf8ce00,    0xffff00,   FMT_D1, AM33,  {MEM(USP), REGS}},
 744 { "movm",       0xf8cf00,    0xffff00,   FMT_D1, AM33,  {REGS, MEM(USP)}},
 745 /* end-sanitize-am33 */
 746
 747 { "clr",        0x00,        0xf3,       FMT_S0, 0,     {DN1}},
 748 /* start-sanitize-am33 */
 749 { "clr",        0xf96800,    0xffff00,   FMT_D6, AM33,  {RN02}},
 750 /* end-sanitize-am33 */
 751
 752 /* start-sanitize-am33 */
 753 { "add",        0xfb7c0000,  0xffff000f, FMT_D7, AM33,  {RM2, RN0, RD2}},
 754 /* end-sanitize-am33 */
 755 { "add",        0xe0,        0xf0,       FMT_S0, 0,     {DM1, DN0}},
 756 { "add",        0xf160,      0xfff0,     FMT_D0, 0,     {DM1, AN0}},
 757 { "add",        0xf150,      0xfff0,     FMT_D0, 0,     {AM1, DN0}},
 758 { "add",        0xf170,      0xfff0,     FMT_D0, 0,     {AM1, AN0}},
 759 { "add",        0x2800,      0xfc00,     FMT_S1, 0,     {SIMM8, DN0}},
 760 { "add",        0xfac00000,  0xfffc0000, FMT_D2, 0,     {SIMM16, DN0}},
 761 { "add",        0x2000,      0xfc00,     FMT_S1, 0,     {SIMM8, AN0}},
 762 { "add",        0xfad00000,  0xfffc0000, FMT_D2, 0,     {SIMM16, AN0}},
 763 { "add",        0xf8fe00,    0xffff00,   FMT_D1, 0,     {SIMM8, SP}},
 764 { "add",        0xfafe0000,  0xffff0000, FMT_D2, 0,     {SIMM16, SP}},
 765 /* start-sanitize-am33 */
 766 { "add",        0xf97800,    0xffff00,   FMT_D6, AM33,  {RM2, RN0}},
 767 /* end-sanitize-am33 */
 768 { "add",        0xfcc00000,  0xfffc0000, FMT_D4, 0,     {IMM32, DN0}},
 769 { "add",        0xfcd00000,  0xfffc0000, FMT_D4, 0,     {IMM32, AN0}},
 770 { "add",        0xfcfe0000,  0xffff0000, FMT_D4, 0,     {IMM32, SP}},
 771 /* start-sanitize-am33 */
 772 { "add",        0xfb780000,  0xffff0000, FMT_D7, AM33,  {SIMM8, RN02}},
 773 { "add",        0xfd780000,  0xffff0000, FMT_D8, AM33,  {SIMM24, RN02}},
 774 { "add",        0xfe780000,  0xffff0000, FMT_D9, AM33,  {IMM32_HIGH8, RN02}},
 775 /* end-sanitize-am33 */
 776
 777 /* start-sanitize-am33 */
 778 { "addc",       0xfb8c0000,  0xffff000f, FMT_D7, AM33,  {RM2, RN0, RD2}},
 779 /* end-sanitize-am33 */
 780 { "addc",       0xf140,      0xfff0,     FMT_D0, 0,     {DM1, DN0}},
 781 /* start-sanitize-am33 */
 782 { "addc",       0xf98800,    0xffff00,   FMT_D6, AM33,  {RM2, RN0}},
 783 { "addc",       0xfb880000,  0xffff0000, FMT_D7, AM33,  {SIMM8, RN02}},
 784 { "addc",       0xfd880000,  0xffff0000, FMT_D8, AM33,  {SIMM24, RN02}},
 785 { "addc",       0xfe880000,  0xffff0000, FMT_D9, AM33,  {IMM32_HIGH8, RN02}},
 786 /* end-sanitize-am33 */
 787
 788 /* start-sanitize-am33 */
 789 { "sub",        0xfb9c0000,  0xffff000f, FMT_D7, AM33,  {RM2, RN0, RD2}},
 790 /* end-sanitize-am33 */
 791 { "sub",        0xf100,      0xfff0,     FMT_D0, 0,     {DM1, DN0}},
 792 { "sub",        0xf120,      0xfff0,     FMT_D0, 0,     {DM1, AN0}},
 793 { "sub",        0xf110,      0xfff0,     FMT_D0, 0,     {AM1, DN0}},
 794 { "sub",        0xf130,      0xfff0,     FMT_D0, 0,     {AM1, AN0}},
 795 /* start-sanitize-am33 */
 796 { "sub",        0xf99800,    0xffff00,   FMT_D6, AM33,  {RM2, RN0}},
 797 /* end-sanitize-am33 */
 798 { "sub",        0xfcc40000,  0xfffc0000, FMT_D4, 0,     {IMM32, DN0}},
 799 { "sub",        0xfcd40000,  0xfffc0000, FMT_D4, 0,     {IMM32, AN0}},
 800 /* start-sanitize-am33 */
 801 { "sub",        0xfb980000,  0xffff0000, FMT_D7, AM33,  {SIMM8, RN02}},
 802 { "sub",        0xfd980000,  0xffff0000, FMT_D8, AM33,  {SIMM24, RN02}},
 803 { "sub",        0xfe980000,  0xffff0000, FMT_D9, AM33,  {IMM32_HIGH8, RN02}},
 804 /* end-sanitize-am33 */
 805
 806 /* start-sanitize-am33 */
 807 { "subc",       0xfa8c0000,  0xffff000f, FMT_D7, AM33,  {RM2, RN0, RD2}},
 808 /* end-sanitize-am33 */
 809 { "subc",       0xf180,      0xfff0,     FMT_D0, 0,     {DM1, DN0}},
 810 /* start-sanitize-am33 */
 811 { "subc",       0xf9a800,    0xffff00,   FMT_D6, AM33,  {RM2, RN0}},
 812 { "subc",       0xfba80000,  0xffff0000, FMT_D7, AM33,  {SIMM8, RN02}},
 813 { "subc",       0xfda80000,  0xffff0000, FMT_D8, AM33,  {SIMM24, RN02}},
 814 { "subc",       0xfea80000,  0xffff0000, FMT_D9, AM33,  {IMM32_HIGH8, RN02}},
 815 /* end-sanitize-am33 */
 816
 817 /* start-sanitize-am33 */
 818 { "mul",        0xfbad0000,  0xffff0000, FMT_D7, AM33,  {RM2, RN0, RD2, RD0}},
 819 /* end-sanitize-am33 */
 820 { "mul",        0xf240,      0xfff0,     FMT_D0, 0,     {DM1, DN0}},
 821 /* start-sanitize-am33 */
 822 { "mul",        0xf9a900,    0xffff00,   FMT_D6, AM33,  {RM2, RN0}},
 823 { "mul",        0xfba90000,  0xffff0000, FMT_D7, AM33,  {SIMM8, RN02}},
 824 { "mul",        0xfda90000,  0xffff0000, FMT_D8, AM33,  {SIMM24, RN02}},
 825 { "mul",        0xfea90000,  0xffff0000, FMT_D9, AM33,  {IMM32_HIGH8, RN02}},
 826 /* end-sanitize-am33 */
 827
 828 /* start-sanitize-am33 */
 829 { "mulu",       0xfbbd0000,  0xffff0000, FMT_D7, AM33,  {RM2, RN0, RD2, RD0}},
 830 /* end-sanitize-am33 */
 831 { "mulu",       0xf250,      0xfff0,     FMT_D0, 0,     {DM1, DN0}},
 832 /* start-sanitize-am33 */
 833 { "mulu",       0xf9b900,    0xffff00,   FMT_D6, AM33,  {RM2, RN0}},
 834 { "mulu",       0xfbb90000,  0xffff0000, FMT_D7, AM33,  {IMM8, RN02}},
 835 { "mulu",       0xfdb90000,  0xffff0000, FMT_D8, AM33,  {IMM24, RN02}},
 836 { "mulu",       0xfeb90000,  0xffff0000, FMT_D9, AM33,  {IMM32_HIGH8, RN02}},
 837 /* end-sanitize-am33 */
 838
 839 { "div",        0xf260,      0xfff0,     FMT_D0, 0,     {DM1, DN0}},
 840 /* start-sanitize-am33 */
 841 { "div",        0xf9c900,    0xffff00,   FMT_D6, AM33,  {RM2, RN0}},
 842 /* end-sanitize-am33 */
 843
 844 { "divu",       0xf270,      0xfff0,     FMT_D0, 0,     {DM1, DN0}},
 845 /* start-sanitize-am33 */
 846 { "divu",       0xf9d900,    0xffff00,   FMT_D6, AM33,  {RM2, RN0}},
 847 /* end-sanitize-am33 */
 848
 849 { "inc",        0x40,        0xf3,       FMT_S0, 0,     {DN1}},
 850 { "inc",        0x41,        0xf3,       FMT_S0, 0,     {AN1}},
 851 /* start-sanitize-am33 */
 852 { "inc",        0xf9b800,    0xffff00,   FMT_D6, AM33,  {RN02}},
 853 /* end-sanitize-am33 */
 854
 855 { "inc4",       0x50,        0xfc,       FMT_S0, 0,     {AN0}},
 856 /* start-sanitize-am33 */
 857 { "inc4",       0xf9c800,    0xffff00,   FMT_D6, AM33,  {RN02}},
 858 /* end-sanitize-am33 */
 859
 860 { "cmp",        0xa000,      0xf000,     FMT_S1, 0,     {SIMM8, DN01}},
 861 { "cmp",        0xa0,        0xf0,       FMT_S0, 0,     {DM1, DN0}},
 862 { "cmp",        0xf1a0,      0xfff0,     FMT_D0, 0,     {DM1, AN0}},
 863 { "cmp",        0xf190,      0xfff0,     FMT_D0, 0,     {AM1, DN0}},
 864 { "cmp",        0xb000,      0xf000,     FMT_S1, 0,     {IMM8, AN01}},
 865 { "cmp",        0xb0,        0xf0,       FMT_S0, 0,     {AM1, AN0}},
 866 { "cmp",        0xfac80000,  0xfffc0000, FMT_D2, 0,     {SIMM16, DN0}},
 867 { "cmp",        0xfad80000,  0xfffc0000, FMT_D2, 0,     {IMM16, AN0}},
 868 /* start-sanitize-am33 */
 869 { "cmp",        0xf9d800,    0xffff00,   FMT_D6, AM33,  {RM2, RN0}},
 870 /* end-sanitize-am33 */
 871 { "cmp",        0xfcc80000,  0xfffc0000, FMT_D4, 0,     {IMM32, DN0}},
 872 { "cmp",        0xfcd80000,  0xfffc0000, FMT_D4, 0,     {IMM32, AN0}},
 873 /* start-sanitize-am33 */
 874 { "cmp",        0xfbd80000,  0xffff0000, FMT_D7, AM33,  {SIMM8, RN02}},
 875 { "cmp",        0xfdd80000,  0xffff0000, FMT_D8, AM33,  {SIMM24, RN02}},
 876 { "cmp",        0xfed80000,  0xffff0000, FMT_D9, AM33,  {IMM32_HIGH8, RN02}},
 877 /* end-sanitize-am33 */
 878
 879 /* start-sanitize-am33 */
 880 { "and",        0xfb0d0000,  0xffff000f, FMT_D7, AM33,  {RM2, RN0, RD2}},
 881 /* end-sanitize-am33 */
 882 { "and",        0xf200,      0xfff0,     FMT_D0, 0,     {DM1, DN0}},
 883 { "and",        0xf8e000,    0xfffc00,   FMT_D1, 0,     {IMM8, DN0}},
 884 { "and",        0xfae00000,  0xfffc0000, FMT_D2, 0,     {IMM16, DN0}},
 885 { "and",        0xfafc0000,  0xffff0000, FMT_D2, 0,     {IMM16, PSW}},
 886 /* start-sanitize-am33 */
 887 { "and",        0xfcfc0000,  0xffff0000, FMT_D4, AM33,  {IMM32, EPSW}},
 888 { "and",        0xf90900,    0xffff00,   FMT_D6, AM33,  {RM2, RN0}},
 889 /* end-sanitize-am33 */
 890 { "and",        0xfce00000,  0xfffc0000, FMT_D4, 0,     {IMM32, DN0}},
 891 /* start-sanitize-am33 */
 892 { "and",        0xfb090000,  0xffff0000, FMT_D7, AM33,  {IMM8, RN02}},
 893 { "and",        0xfd090000,  0xffff0000, FMT_D8, AM33,  {IMM24, RN02}},
 894 { "and",        0xfe090000,  0xffff0000, FMT_D9, AM33,  {IMM32_HIGH8, RN02}},
 895 /* end-sanitize-am33 */
 896
 897 /* start-sanitize-am33 */
 898 { "or",         0xfb1d0000,  0xffff000f, FMT_D7, AM33,  {RM2, RN0, RD2}},
 899 /* end-sanitize-am33 */
 900 { "or",         0xf210,      0xfff0,     FMT_D0, 0,     {DM1, DN0}},
 901 { "or",         0xf8e400,    0xfffc00,   FMT_D1, 0,     {IMM8, DN0}},
 902 { "or",         0xfae40000,  0xfffc0000, FMT_D2, 0,     {IMM16, DN0}},
 903 { "or",         0xfafd0000,  0xffff0000, FMT_D2, 0,     {IMM16, PSW}},
 904 /* start-sanitize-am33 */
 905 { "or",         0xfcfd0000,  0xffff0000, FMT_D4, AM33,  {IMM32, EPSW}},
 906 { "or",         0xf91900,    0xffff00,   FMT_D6, AM33,  {RM2, RN0}},
 907 /* end-sanitize-am33 */
 908 { "or",         0xfce40000,  0xfffc0000, FMT_D4, 0,     {IMM32, DN0}},
 909 /* start-sanitize-am33 */
 910 { "or",         0xfb190000,  0xffff0000, FMT_D7, AM33,  {IMM8, RN02}},
 911 { "or",         0xfd190000,  0xffff0000, FMT_D8, AM33,  {IMM24, RN02}},
 912 { "or",         0xfe190000,  0xffff0000, FMT_D9, AM33,  {IMM32_HIGH8, RN02}},
 913 /* end-sanitize-am33 */
 914
 915 /* start-sanitize-am33 */
 916 { "xor",        0xfb2d0000,  0xffff000f, FMT_D7, AM33,  {RM2, RN0, RD2}},
 917 /* end-sanitize-am33 */
 918 { "xor",        0xf220,      0xfff0,     FMT_D0, 0,     {DM1, DN0}},
 919 { "xor",        0xfae80000,  0xfffc0000, FMT_D2, 0,     {IMM16, DN0}},
 920 /* start-sanitize-am33 */
 921 { "xor",        0xf92900,    0xffff00,   FMT_D6, AM33,  {RM2, RN0}},
 922 /* end-sanitize-am33 */
 923 { "xor",        0xfce80000,  0xfffc0000, FMT_D4, 0,     {IMM32, DN0}},
 924 /* start-sanitize-am33 */
 925 { "xor",        0xfb290000,  0xffff0000, FMT_D7, AM33,  {IMM8, RN02}},
 926 { "xor",        0xfd290000,  0xffff0000, FMT_D8, AM33,  {IMM24, RN02}},
 927 { "xor",        0xfe290000,  0xffff0000, FMT_D9, AM33,  {IMM32_HIGH8, RN02}},
 928 /* end-sanitize-am33 */
 929
 930 { "not",        0xf230,      0xfffc,     FMT_D0, 0,     {DN0}},
 931 /* start-sanitize-am33 */
 932 { "not",        0xf93900,    0xffff00,   FMT_D6, AM33,  {RN02}},
 933 /* end-sanitize-am33 */
 934
 935 { "btst",       0xf8ec00,    0xfffc00,   FMT_D1, 0,     {IMM8, DN0}},
 936 { "btst",       0xfaec0000,  0xfffc0000, FMT_D2, 0,     {IMM16, DN0}},
 937 { "btst",       0xfcec0000,  0xfffc0000, FMT_D4, 0,     {IMM32, DN0}},
 938 /* start-sanitize-am33 */
 939 /* Place these before the ones with IMM8E and SD8N_SHIFT8 since we want the
 940    them to match last since they do not promote.  */
 941 { "btst",       0xfbe90000,  0xffff0000, FMT_D7, AM33,  {IMM8, RN02}},
 942 { "btst",       0xfde90000,  0xffff0000, FMT_D8, AM33,  {IMM24, RN02}},
 943 { "btst",       0xfee90000,  0xffff0000, FMT_D9, AM33,  {IMM32_HIGH8, RN02}},
 944 /* end-sanitize-am33 */
 945 { "btst",       0xfe020000,  0xffff0000, FMT_D5, 0,     {IMM8E,
 946                                                          MEM(IMM32_LOWSHIFT8)}},
 947 { "btst",       0xfaf80000,  0xfffc0000, FMT_D2, 0,     {IMM8, MEM2(SD8N_SHIFT8,
 948                                                                     AN0)}},
 949
 950 { "bset",       0xf080,      0xfff0,     FMT_D0, 0,     {DM1, MEM(AN0)}},
 951 { "bset",       0xfe000000,  0xffff0000, FMT_D5, 0,     {IMM8E,
 952                                                          MEM(IMM32_LOWSHIFT8)}},
 953 { "bset",       0xfaf00000,  0xfffc0000, FMT_D2, 0,     {IMM8, MEM2(SD8N_SHIFT8,
 954                                                                     AN0)}},
 955
 956 { "bclr",       0xf090,      0xfff0,     FMT_D0, 0,     {DM1, MEM(AN0)}},
 957 { "bclr",       0xfe010000,  0xffff0000, FMT_D5, 0,     {IMM8E,
 958                                                          MEM(IMM32_LOWSHIFT8)}},
 959 { "bclr",       0xfaf40000,  0xfffc0000, FMT_D2, 0,     {IMM8,
 960                                                          MEM2(SD8N_SHIFT8,AN0)}},
 961
 962 /* start-sanitize-am33 */
 963 { "asr",        0xfb4d0000,  0xffff000f, FMT_D7, AM33,  {RM2, RN0, RD2}},
 964 /* end-sanitize-am33 */
 965 { "asr",        0xf2b0,      0xfff0,     FMT_D0, 0,     {DM1, DN0}},
 966 { "asr",        0xf8c800,    0xfffc00,   FMT_D1, 0,     {IMM8, DN0}},
 967 /* start-sanitize-am33 */
 968 { "asr",        0xf94900,    0xffff00,   FMT_D6, AM33,  {RM2, RN0}},
 969 { "asr",        0xfb490000,  0xffff0000, FMT_D7, AM33,  {IMM8, RN02}},
 970 { "asr",        0xfd490000,  0xffff0000, FMT_D8, AM33,  {IMM24, RN02}},
 971 { "asr",        0xfe490000,  0xffff0000, FMT_D9, AM33,  {IMM32_HIGH8, RN02}},
 972 /* end-sanitize-am33 */
 973 { "asr",        0xf8c801,    0xfffcff,   FMT_D1, 0,     {DN0}},
 974 /* start-sanitize-am33 */
 975 { "asr",        0xfb490000,  0xffff00ff, FMT_D7, AM33,  {RN02}},
 976 /* end-sanitize-am33 */
 977
 978 /* start-sanitize-am33 */
 979 { "lsr",        0xfb5d0000,  0xffff000f, FMT_D7, AM33,  {RM2, RN0, RD2}},
 980 /* end-sanitize-am33 */
 981 { "lsr",        0xf2a0,      0xfff0,     FMT_D0, 0,     {DM1, DN0}},
 982 { "lsr",        0xf8c400,    0xfffc00,   FMT_D1, 0,     {IMM8, DN0}},
 983 /* start-sanitize-am33 */
 984 { "lsr",        0xf95900,    0xffff00,   FMT_D6, AM33,  {RM2, RN0}},
 985 { "lsr",        0xfb590000,  0xffff0000, FMT_D7, AM33,  {IMM8, RN02}},
 986 { "lsr",        0xfd590000,  0xffff0000, FMT_D8, AM33,  {IMM24, RN02}},
 987 { "lsr",        0xfe590000,  0xffff0000, FMT_D9, AM33,  {IMM32_HIGH8, RN02}},
 988 /* end-sanitize-am33 */
 989 { "lsr",        0xf8c401,    0xfffcff,   FMT_D1, 0,     {DN0}},
 990 /* start-sanitize-am33 */
 991 { "lsr",        0xfb590000,  0xffff00ff, FMT_D7, AM33,  {RN02}},
 992 /* end-sanitize-am33 */
 993
 994 /* start-sanitize-am33 */
 995 { "asl",        0xfb6d0000,  0xffff000f, FMT_D7, AM33,  {RM2, RN0, RD2}},
 996 /* end-sanitize-am33 */
 997 { "asl",        0xf290,      0xfff0,     FMT_D0, 0,     {DM1, DN0}},
 998 { "asl",        0xf8c000,    0xfffc00,   FMT_D1, 0,     {IMM8, DN0}},
 999 /* start-sanitize-am33 */
1000 { "asl",        0xf96900,    0xffff00,   FMT_D6, AM33,  {RM2, RN0}},
1001 { "asl",        0xfb690000,  0xffff0000, FMT_D7, AM33,  {SIMM8, RN02}},
1002 { "asl",        0xfd690000,  0xffff0000, FMT_D8, AM33,  {IMM24, RN02}},
1003 { "asl",        0xfe690000,  0xffff0000, FMT_D9, AM33,  {IMM32_HIGH8, RN02}},
1004 /* end-sanitize-am33 */
1005 { "asl",        0xf8c001,    0xfffcff,   FMT_D1, 0,     {DN0}},
1006 /* start-sanitize-am33 */
1007 { "asl",        0xfb690000,  0xffff00ff, FMT_D7, AM33,  {RN02}},
1008 /* end-sanitize-am33 */
1009
1010 { "asl2",       0x54,        0xfc,       FMT_S0, 0,     {DN0}},
1011 /* start-sanitize-am33 */
1012 { "asl2",       0xf97900,    0xffff00,   FMT_D6, AM33,  {RN02}},
1013 /* end-sanitize-am33 */
1014
1015 { "ror",        0xf284,      0xfffc,     FMT_D0, 0,     {DN0}},
1016 /* start-sanitize-am33 */
1017 { "ror",        0xf98900,    0xffff00,   FMT_D6, AM33,  {RN02}},
1018 /* end-sanitize-am33 */
1019
1020 { "rol",        0xf280,      0xfffc,     FMT_D0, 0,     {DN0}},
1021 /* start-sanitize-am33 */
1022 { "rol",        0xf99900,    0xffff00,   FMT_D6, AM33,  {RN02}},
1023 /* end-sanitize-am33 */
1024
1025 { "beq",        0xc800,      0xff00,     FMT_S1, 0,     {SD8N_PCREL}},
1026 { "bne",        0xc900,      0xff00,     FMT_S1, 0,     {SD8N_PCREL}},
1027 { "bgt",        0xc100,      0xff00,     FMT_S1, 0,     {SD8N_PCREL}},
1028 { "bge",        0xc200,      0xff00,     FMT_S1, 0,     {SD8N_PCREL}},
1029 { "ble",        0xc300,      0xff00,     FMT_S1, 0,     {SD8N_PCREL}},
1030 { "blt",        0xc000,      0xff00,     FMT_S1, 0,     {SD8N_PCREL}},
1031 { "bhi",        0xc500,      0xff00,     FMT_S1, 0,     {SD8N_PCREL}},
1032 { "bcc",        0xc600,      0xff00,     FMT_S1, 0,     {SD8N_PCREL}},
1033 { "bls",        0xc700,      0xff00,     FMT_S1, 0,     {SD8N_PCREL}},
1034 { "bcs",        0xc400,      0xff00,     FMT_S1, 0,     {SD8N_PCREL}},
1035 { "bvc",        0xf8e800,    0xffff00,   FMT_D1, 0,     {SD8N_PCREL}},
1036 { "bvs",        0xf8e900,    0xffff00,   FMT_D1, 0,     {SD8N_PCREL}},
1037 { "bnc",        0xf8ea00,    0xffff00,   FMT_D1, 0,     {SD8N_PCREL}},
1038 { "bns",        0xf8eb00,    0xffff00,   FMT_D1, 0,     {SD8N_PCREL}},
1039 { "bra",        0xca00,      0xff00,     FMT_S1, 0,     {SD8N_PCREL}},
1040
1041 { "leq",        0xd8,        0xff,       FMT_S0, 0,     {UNUSED}},
1042 { "lne",        0xd9,        0xff,       FMT_S0, 0,     {UNUSED}},
1043 { "lgt",        0xd1,        0xff,       FMT_S0, 0,     {UNUSED}},
1044 { "lge",        0xd2,        0xff,       FMT_S0, 0,     {UNUSED}},
1045 { "lle",        0xd3,        0xff,       FMT_S0, 0,     {UNUSED}},
1046 { "llt",        0xd0,        0xff,       FMT_S0, 0,     {UNUSED}},
1047 { "lhi",        0xd5,        0xff,       FMT_S0, 0,     {UNUSED}},
1048 { "lcc",        0xd6,        0xff,       FMT_S0, 0,     {UNUSED}},
1049 { "lls",        0xd7,        0xff,       FMT_S0, 0,     {UNUSED}},
1050 { "lcs",        0xd4,        0xff,       FMT_S0, 0,     {UNUSED}},
1051 { "lra",        0xda,        0xff,       FMT_S0, 0,     {UNUSED}},
1052 { "setlb",      0xdb,        0xff,       FMT_S0, 0,     {UNUSED}},
1053
1054 { "jmp",        0xf0f4,      0xfffc,     FMT_D0, 0,     {PAREN,AN0,PAREN}},
1055 { "jmp",        0xcc0000,    0xff0000,   FMT_S2, 0,     {IMM16_PCREL}},
1056 { "jmp",        0xdc000000,  0xff000000, FMT_S4, 0,     {IMM32_HIGH24}},
1057 { "call",       0xcd000000,  0xff000000, FMT_S4, 0,     {D16_SHIFT,REGS,IMM8E}},
1058 { "call",       0xdd000000,  0xff000000, FMT_S6, 0,
1059                                         {IMM32_HIGH24_LOWSHIFT16,
1060                                          REGSE_SHIFT8,IMM8E}},
1061 { "calls",      0xf0f0,      0xfffc,     FMT_D0, 0,     {PAREN,AN0,PAREN}},
1062 { "calls",      0xfaff0000,  0xffff0000, FMT_D2, 0,     {IMM16_PCREL}},
1063 { "calls",      0xfcff0000,  0xffff0000, FMT_D4, 0,     {IMM32_PCREL}},
1064
1065 { "ret",        0xdf0000,    0xff0000,   FMT_S2, 0,     {REGS_SHIFT8, IMM8}},
1066 { "retf",       0xde0000,    0xff0000,   FMT_S2, 0,     {REGS_SHIFT8, IMM8}},
1067 { "rets",       0xf0fc,      0xffff,     FMT_D0, 0,     {UNUSED}},
1068 { "rti",        0xf0fd,      0xffff,     FMT_D0, 0,     {UNUSED}},
1069 { "trap",       0xf0fe,      0xffff,     FMT_D0, 0,     {UNUSED}},
1070 { "rtm",        0xf0ff,      0xffff,     FMT_D0, 0,     {UNUSED}},
1071 { "nop",        0xcb,        0xff,       FMT_S0, 0,     {UNUSED}},
1072 /* { "udf", 0, 0, {0}},  */
1073
1074 { "putx",       0xf500,      0xfff0,     FMT_D0, AM30,  {DN01}},
1075 { "getx",       0xf6f0,      0xfff0,     FMT_D0, AM30,  {DN01}},
1076 { "mulq",       0xf600,      0xfff0,     FMT_D0, AM30,  {DM1, DN0}},
1077 { "mulq",       0xf90000,    0xfffc00,   FMT_D1, AM30,  {SIMM8, DN0}},
1078 { "mulq",       0xfb000000,  0xfffc0000, FMT_D2, AM30,  {SIMM16, DN0}},
1079 { "mulq",       0xfd000000,  0xfffc0000, FMT_D4, AM30,  {IMM32, DN0}},
1080 { "mulqu",      0xf610,      0xfff0,     FMT_D0, AM30,  {DM1, DN0}},
1081 { "mulqu",      0xf91400,    0xfffc00,   FMT_D1, AM30,  {SIMM8, DN0}},
1082 { "mulqu",      0xfb140000,  0xfffc0000, FMT_D2, AM30,  {SIMM16, DN0}},
1083 { "mulqu",      0xfd140000,  0xfffc0000, FMT_D4, AM30,  {IMM32, DN0}},
1084 { "sat16",      0xf640,      0xfff0,     FMT_D0, AM30,  {DM1, DN0}},
1085 /* start-sanitize-am33 */
1086 { "sat16",      0xf9ab00,    0xffff00,   FMT_D6, AM33,  {RM2, RN0}},
1087 /* end-sanitize-am33 */
1088
1089 { "sat24",      0xf650,      0xfff0,     FMT_D0, AM30,  {DM1, DN0}},
1090 /* start-sanitize-am33 */
1091 { "sat24",      0xfbaf0000,  0xffff00ff, FMT_D7, AM33,  {RM2, RN0}},
1092 /* end-sanitize-am33 */
1093
1094 /* start-sanitize-am33 */
1095 { "bsch",       0xfbff0000,  0xffff000f, FMT_D7, AM33,  {RM2, RN0, RD2}},
1096 /* end-sanitize-am33 */
1097 { "bsch",       0xf670,      0xfff0,     FMT_D0, AM30,  {DM1, DN0}},
1098 /* start-sanitize-am33 */
1099 { "bsch",       0xf9fb00,    0xffff00,   FMT_D6, AM33,  {RM2, RN0}},
1100 /* end-sanitize-am33 */
1101
1102 /* Extension.  We need some instruction to trigger "emulated syscalls"
1103    for our simulator.  */
1104 /* start-sanitize-am33 */
1105 { "syscall",    0xf0e0,      0xfff0,     FMT_D0, AM33,  {IMM4}},
1106 /* end-sanitize-am33 */
1107 { "syscall",    0xf0c0,      0xffff,     FMT_D0, 0,     {UNUSED}},
1108
1109 /* Extension.  When talking to the simulator, gdb requires some instruction
1110    that will trigger a "breakpoint" (really just an instruction that isn't
1111    otherwise used by the tools.  This instruction must be the same size
1112    as the smallest instruction on the target machine.  In the case of the
1113    mn10x00 the "break" instruction must be one byte.  0xff is available on
1114    both mn10x00 architectures.  */
1115 { "break",      0xff,        0xff,       FMT_S0, 0,     {UNUSED}},
1116
1117 /* start-sanitize-am33 */
1118 { "add_add",    0xf7000000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4, RM2, RN0}},
1119 { "add_add",    0xf7100000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1120                                                           SIMM4_2, RN0}},
1121 { "add_add",    0xf7040000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1122                                                           RM2, RN0}},
1123 { "add_add",    0xf7140000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1124                                                           SIMM4_2, RN0}},
1125 { "add_sub",    0xf7200000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4, RM2, RN0}},
1126 { "add_sub",    0xf7300000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1127                                                           SIMM4_2, RN0}},
1128 { "add_sub",    0xf7240000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1129                                                           RM2, RN0}},
1130 { "add_sub",    0xf7340000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1131                                                           SIMM4_2, RN0}},
1132 { "add_cmp",    0xf7400000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4, RM2, RN0}},
1133 { "add_cmp",    0xf7500000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1134                                                           SIMM4_2, RN0}},
1135 { "add_cmp",    0xf7440000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1136                                                           RM2, RN0}},
1137 { "add_cmp",    0xf7540000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1138                                                           SIMM4_2, RN0}},
1139 { "add_mov",    0xf7600000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4, RM2, RN0}},
1140 { "add_mov",    0xf7700000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1141                                                           SIMM4_2, RN0}},
1142 { "add_mov",    0xf7640000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1143                                                           RM2, RN0}},
1144 { "add_mov",    0xf7740000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1145                                                           SIMM4_2, RN0}},
1146 { "add_asr",    0xf7800000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4, RM2, RN0}},
1147 { "add_asr",    0xf7900000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1148                                                           IMM4_2, RN0}},
1149 { "add_asr",    0xf7840000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1150                                                           RM2, RN0}},
1151 { "add_asr",    0xf7940000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1152                                                           IMM4_2, RN0}},
1153 { "add_lsr",    0xf7a00000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4, RM2, RN0}},
1154 { "add_lsr",    0xf7b00000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1155                                                           IMM4_2, RN0}},
1156 { "add_lsr",    0xf7a40000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1157                                                           RM2, RN0}},
1158 { "add_lsr",    0xf7b40000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1159                                                           IMM4_2, RN0}},
1160 { "add_asl",    0xf7c00000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4, RM2, RN0}},
1161 { "add_asl",    0xf7d00000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1162                                                           IMM4_2, RN0}},
1163 { "add_asl",    0xf7c40000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1164                                                           RM2, RN0}},
1165 { "add_asl",    0xf7d40000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1166                                                           IMM4_2, RN0}},
1167 { "cmp_add",    0xf7010000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4, RM2, RN0}},
1168 { "cmp_add",    0xf7110000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1169                                                           SIMM4_2, RN0}},
1170 { "cmp_add",    0xf7050000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1171                                                           RM2, RN0}},
1172 { "cmp_add",    0xf7150000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1173                                                           SIMM4_2, RN0}},
1174 { "cmp_sub",    0xf7210000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4, RM2, RN0}},
1175 { "cmp_sub",    0xf7310000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1176                                                           SIMM4_2, RN0}},
1177 { "cmp_sub",    0xf7250000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1178                                                           RM2, RN0}},
1179 { "cmp_sub",    0xf7350000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1180                                                           SIMM4_2, RN0}},
1181 { "cmp_mov",    0xf7610000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4, RM2, RN0}},
1182 { "cmp_mov",    0xf7710000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1183                                                           SIMM4_2, RN0}},
1184 { "cmp_mov",    0xf7650000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1185                                                           RM2, RN0}},
1186 { "cmp_mov",    0xf7750000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1187                                                           SIMM4_2, RN0}},
1188 { "cmp_asr",    0xf7810000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4, RM2, RN0}},
1189 { "cmp_asr",    0xf7910000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1190                                                           IMM4_2, RN0}},
1191 { "cmp_asr",    0xf7850000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1192                                                           RM2, RN0}},
1193 { "cmp_asr",    0xf7950000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1194                                                           IMM4_2, RN0}},
1195 { "cmp_lsr",    0xf7a10000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4, RM2, RN0}},
1196 { "cmp_lsr",    0xf7b10000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1197                                                           IMM4_2, RN0}},
1198 { "cmp_lsr",    0xf7a50000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1199                                                           RM2, RN0}},
1200 { "cmp_lsr",    0xf7b50000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1201                                                           IMM4_2, RN0}},
1202 { "cmp_asl",    0xf7c10000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4, RM2, RN0}},
1203 { "cmp_asl",    0xf7d10000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4, IMM4_2, RN0}},
1204 { "cmp_asl",    0xf7c50000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1205                                                           RM2, RN0}},
1206 { "cmp_asl",    0xf7d50000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1207                                                           IMM4_2, RN0}},
1208 { "sub_add",    0xf7020000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4, RM2, RN0}},
1209 { "sub_add",    0xf7120000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1210                                                           SIMM4_2, RN0}},
1211 { "sub_add",    0xf7060000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1212                                                           RM2, RN0}},
1213 { "sub_add",    0xf7160000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1214                                                           SIMM4_2, RN0}},
1215 { "sub_sub",    0xf7220000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4, RM2, RN0}},
1216 { "sub_sub",    0xf7320000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1217                                                           SIMM4_2, RN0}},
1218 { "sub_sub",    0xf7260000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1219                                                           RM2, RN0}},
1220 { "sub_sub",    0xf7360000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1221                                                           SIMM4_2, RN0}},
1222 { "sub_cmp",    0xf7420000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4, RM2, RN0}},
1223 { "sub_cmp",    0xf7520000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1224                                                           SIMM4_2, RN0}},
1225 { "sub_cmp",    0xf7460000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1226                                                           RM2, RN0}},
1227 { "sub_cmp",    0xf7560000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1228                                                           SIMM4_2, RN0}},
1229 { "sub_mov",    0xf7620000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4, RM2, RN0}},
1230 { "sub_mov",    0xf7720000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1231                                                           SIMM4_2, RN0}},
1232 { "sub_mov",    0xf7660000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1233                                                           RM2, RN0}},
1234 { "sub_mov",    0xf7760000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1235                                                           SIMM4_2, RN0}},
1236 { "sub_asr",    0xf7820000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4, RM2, RN0}},
1237 { "sub_asr",    0xf7920000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1238                                                           IMM4_2, RN0}},
1239 { "sub_asr",    0xf7860000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1240                                                           RM2, RN0}},
1241 { "sub_asr",    0xf7960000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1242                                                           IMM4_2, RN0}},
1243 { "sub_lsr",    0xf7a20000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4, RM2, RN0}},
1244 { "sub_lsr",    0xf7b20000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1245                                                           IMM4_2, RN0}},
1246 { "sub_lsr",    0xf7a60000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1247                                                           RM2, RN0}},
1248 { "sub_lsr",    0xf7b60000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1249                                                           IMM4_2, RN0}},
1250 { "sub_asl",    0xf7c20000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4, RM2, RN0}},
1251 { "sub_asl",    0xf7d20000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1252                                                           IMM4_2, RN0}},
1253 { "sub_asl",    0xf7c60000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1254                                                           RM2, RN0}},
1255 { "sub_asl",    0xf7d60000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1256                                                           IMM4_2, RN0}},
1257 { "mov_add",    0xf7030000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4, RM2, RN0}},
1258 { "mov_add",    0xf7130000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1259                                                           SIMM4_2, RN0}},
1260 { "mov_add",    0xf7070000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1261                                                           RM2, RN0}},
1262 { "mov_add",    0xf7170000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1263                                                           SIMM4_2, RN0}},
1264 { "mov_sub",    0xf7230000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4, RM2, RN0}},
1265 { "mov_sub",    0xf7330000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1266                                                           SIMM4_2, RN0}},
1267 { "mov_sub",    0xf7270000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1268                                                           RM2, RN0}},
1269 { "mov_sub",    0xf7370000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1270                                                           SIMM4_2, RN0}},
1271 { "mov_cmp",    0xf7430000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4, RM2, RN0}},
1272 { "mov_cmp",    0xf7530000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1273                                                           SIMM4_2, RN0}},
1274 { "mov_cmp",    0xf7470000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1275                                                           RM2, RN0}},
1276 { "mov_cmp",    0xf7570000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1277                                                           SIMM4_2, RN0}},
1278 { "mov_mov",    0xf7630000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4, RM2, RN0}},
1279 { "mov_mov",    0xf7730000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1280                                                           SIMM4_2, RN0}},
1281 { "mov_mov",    0xf7670000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1282                                                           RM2, RN0}},
1283 { "mov_mov",    0xf7770000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1284                                                           SIMM4_2, RN0}},
1285 { "mov_asr",    0xf7830000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4, RM2, RN0}},
1286 { "mov_asr",    0xf7930000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1287                                                           IMM4_2, RN0}},
1288 { "mov_asr",    0xf7870000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1289                                                           RM2, RN0}},
1290 { "mov_asr",    0xf7970000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1291                                                           IMM4_2, RN0}},
1292 { "mov_lsr",    0xf7a30000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4, RM2, RN0}},
1293 { "mov_lsr",    0xf7b30000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1294                                                           IMM4_2, RN0}},
1295 { "mov_lsr",    0xf7a70000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1296                                                           RM2, RN0}},
1297 { "mov_lsr",    0xf7b70000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1298                                                           IMM4_2, RN0}},
1299 { "mov_asl",    0xf7c30000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4, RM2, RN0}},
1300 { "mov_asl",    0xf7d30000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1301                                                           IMM4_2, RN0}},
1302 { "mov_asl",    0xf7c70000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1303                                                           RM2, RN0}},
1304 { "mov_asl",    0xf7d70000,  0xffff0000, FMT_D10, AM33,  {SIMM4_6, RN4,
1305                                                           IMM4_2, RN0}},
1306 { "and_add",    0xf7080000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1307                                                           RM2, RN0}},
1308 { "and_add",    0xf7180000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1309                                                           SIMM4_2, RN0}},
1310 { "and_sub",    0xf7280000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1311                                                           RM2, RN0}},
1312 { "and_sub",    0xf7380000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1313                                                           SIMM4_2, RN0}},
1314 { "and_cmp",    0xf7480000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1315                                                           RM2, RN0}},
1316 { "and_cmp",    0xf7580000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1317                                                           SIMM4_2, RN0}},
1318 { "and_mov",    0xf7680000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1319                                                           RM2, RN0}},
1320 { "and_mov",    0xf7780000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1321                                                           SIMM4_2, RN0}},
1322 { "and_asr",    0xf7880000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1323                                                           RM2, RN0}},
1324 { "and_asr",    0xf7980000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1325                                                           IMM4_2, RN0}},
1326 { "and_lsr",    0xf7a80000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1327                                                           RM2, RN0}},
1328 { "and_lsr",    0xf7b80000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1329                                                           IMM4_2, RN0}},
1330 { "and_asl",    0xf7c80000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1331                                                           RM2, RN0}},
1332 { "and_asl",    0xf7d80000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1333                                                           IMM4_2, RN0}},
1334 { "dmach_add",  0xf7090000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1335                                                           RM2, RN0}},
1336 { "dmach_add",  0xf7190000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1337                                                           SIMM4_2, RN0}},
1338 { "dmach_sub",  0xf7290000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1339                                                           RM2, RN0}},
1340 { "dmach_sub",  0xf7390000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1341                                                           SIMM4_2, RN0}},
1342 { "dmach_cmp",  0xf7490000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1343                                                           RM2, RN0}},
1344 { "dmach_cmp",  0xf7590000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1345                                                           SIMM4_2, RN0}},
1346 { "dmach_mov",  0xf7690000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1347                                                           RM2, RN0}},
1348 { "dmach_mov",  0xf7790000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1349                                                           SIMM4_2, RN0}},
1350 { "dmach_asr",  0xf7890000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1351                                                           RM2, RN0}},
1352 { "dmach_asr",  0xf7990000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1353                                                           IMM4_2, RN0}},
1354 { "dmach_lsr",  0xf7a90000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1355                                                           RM2, RN0}},
1356 { "dmach_lsr",  0xf7b90000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1357                                                           IMM4_2, RN0}},
1358 { "dmach_asl",  0xf7c90000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1359                                                           RM2, RN0}},
1360 { "dmach_asl",  0xf7d90000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1361                                                           IMM4_2, RN0}},
1362 { "xor_add",    0xf70a0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1363                                                           RM2, RN0}},
1364 { "xor_add",    0xf71a0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1365                                                           SIMM4_2, RN0}},
1366 { "xor_sub",    0xf72a0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1367                                                           RM2, RN0}},
1368 { "xor_sub",    0xf73a0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1369                                                           SIMM4_2, RN0}},
1370 { "xor_cmp",    0xf74a0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1371                                                           RM2, RN0}},
1372 { "xor_cmp",    0xf75a0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1373                                                           SIMM4_2, RN0}},
1374 { "xor_mov",    0xf76a0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1375                                                           RM2, RN0}},
1376 { "xor_mov",    0xf77a0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1377                                                           SIMM4_2, RN0}},
1378 { "xor_asr",    0xf78a0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1379                                                           RM2, RN0}},
1380 { "xor_asr",    0xf79a0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1381                                                           IMM4_2, RN0}},
1382 { "xor_lsr",    0xf7aa0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1383                                                           RM2, RN0}},
1384 { "xor_lsr",    0xf7ba0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1385                                                           IMM4_2, RN0}},
1386 { "xor_asl",    0xf7ca0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1387                                                           RM2, RN0}},
1388 { "xor_asl",    0xf7da0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1389                                                           IMM4_2, RN0}},
1390 { "swhw_add",   0xf70b0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1391                                                           RM2, RN0}},
1392 { "swhw_add",   0xf71b0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1393                                                           SIMM4_2, RN0}},
1394 { "swhw_sub",   0xf72b0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1395                                                           RM2, RN0}},
1396 { "swhw_sub",   0xf73b0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1397                                                           SIMM4_2, RN0}},
1398 { "swhw_cmp",   0xf74b0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1399                                                           RM2, RN0}},
1400 { "swhw_cmp",   0xf75b0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1401                                                           SIMM4_2, RN0}},
1402 { "swhw_mov",   0xf76b0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1403                                                           RM2, RN0}},
1404 { "swhw_mov",   0xf77b0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1405                                                           SIMM4_2, RN0}},
1406 { "swhw_asr",   0xf78b0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1407                                                           RM2, RN0}},
1408 { "swhw_asr",   0xf79b0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1409                                                           IMM4_2, RN0}},
1410 { "swhw_lsr",   0xf7ab0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1411                                                           RM2, RN0}},
1412 { "swhw_lsr",   0xf7bb0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1413                                                           IMM4_2, RN0}},
1414 { "swhw_asl",   0xf7cb0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1415                                                           RM2, RN0}},
1416 { "swhw_asl",   0xf7db0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1417                                                           IMM4_2, RN0}},
1418 { "or_add",     0xf70c0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1419                                                           RM2, RN0}},
1420 { "or_add",     0xf71c0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1421                                                           SIMM4_2, RN0}},
1422 { "or_sub",     0xf72c0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1423                                                           RM2, RN0}},
1424 { "or_sub",     0xf73c0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1425                                                           SIMM4_2, RN0}},
1426 { "or_cmp",     0xf74c0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1427                                                           RM2, RN0}},
1428 { "or_cmp",     0xf75c0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1429                                                           SIMM4_2, RN0}},
1430 { "or_mov",     0xf76c0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1431                                                           RM2, RN0}},
1432 { "or_mov",     0xf77c0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1433                                                           SIMM4_2, RN0}},
1434 { "or_asr",     0xf78c0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1435                                                           RM2, RN0}},
1436 { "or_asr",     0xf79c0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1437                                                           IMM4_2, RN0}},
1438 { "or_lsr",     0xf7ac0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1439                                                           RM2, RN0}},
1440 { "or_lsr",     0xf7bc0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1441                                                           IMM4_2, RN0}},
1442 { "or_asl",     0xf7cc0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1443                                                           RM2, RN0}},
1444 { "or_asl",     0xf7dc0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1445                                                           IMM4_2, RN0}},
1446 { "sat16_add",  0xf70d0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1447                                                           RM2, RN0}},
1448 { "sat16_add",  0xf71d0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1449                                                           SIMM4_2, RN0}},
1450 { "sat16_sub",  0xf72d0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1451                                                           RM2, RN0}},
1452 { "sat16_sub",  0xf73d0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1453                                                           SIMM4_2, RN0}},
1454 { "sat16_cmp",  0xf74d0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1455                                                           RM2, RN0}},
1456 { "sat16_cmp",  0xf75d0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1457                                                           SIMM4_2, RN0}},
1458 { "sat16_mov",  0xf76d0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1459                                                           RM2, RN0}},
1460 { "sat16_mov",  0xf77d0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1461                                                           SIMM4_2, RN0}},
1462 { "sat16_asr",  0xf78d0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1463                                                           RM2, RN0}},
1464 { "sat16_asr",  0xf79d0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1465                                                           IMM4_2, RN0}},
1466 { "sat16_lsr",  0xf7ad0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1467                                                           RM2, RN0}},
1468 { "sat16_lsr",  0xf7bd0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1469                                                           IMM4_2, RN0}},
1470 { "sat16_asl",  0xf7cd0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1471                                                           RM2, RN0}},
1472 { "sat16_asl",  0xf7dd0000,  0xffff0000, FMT_D10, AM33,  {RM6, RN4,
1473                                                           IMM4_2, RN0}},
1474 /* Ugh.  Synthetic instructions.  */
1475 { "add_and",    0xf7080000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1476                                                           RM6, RN4}},
1477 { "add_and",    0xf7180000,  0xffff0000, FMT_D10, AM33,  {SIMM4_2, RN0,
1478                                                           RM6, RN4}},
1479 { "add_dmach",  0xf7090000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1480                                                           RM6, RN4}},
1481 { "add_dmach",  0xf7190000,  0xffff0000, FMT_D10, AM33,  {SIMM4_2, RN0,
1482                                                           RM6, RN4}},
1483 { "add_or",     0xf70c0000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1484                                                           RM6, RN4}},
1485 { "add_or",     0xf71c0000,  0xffff0000, FMT_D10, AM33,  {SIMM4_2, RN0,
1486                                                           RM6, RN4}},
1487 { "add_sat16",  0xf70d0000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1488                                                           RM6, RN4}},
1489 { "add_sat16",  0xf71d0000,  0xffff0000, FMT_D10, AM33,  {SIMM4_2, RN0,
1490                                                           RM6, RN4}},
1491 { "add_swhw",   0xf70b0000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1492                                                           RM6, RN4}},
1493 { "add_swhw",   0xf71b0000,  0xffff0000, FMT_D10, AM33,  {SIMM4_2, RN0,
1494                                                           RM6, RN4}},
1495 { "add_xor",    0xf70a0000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1496                                                           RM6, RN4}},
1497 { "add_xor",    0xf71a0000,  0xffff0000, FMT_D10, AM33,  {SIMM4_2, RN0,
1498                                                           RM6, RN4}},
1499 { "asl_add",    0xf7c00000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0, RM6, RN4}},
1500 { "asl_add",    0xf7d00000,  0xffff0000, FMT_D10, AM33,  {IMM4_2, RN0,
1501                                                           RM6, RN4}},
1502 { "asl_add",    0xf7c40000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1503                                                           SIMM4_6, RN4}},
1504 { "asl_add",    0xf7d40000,  0xffff0000, FMT_D10, AM33,  {IMM4_2, RN0,
1505                                                           SIMM4_6, RN4}},
1506 { "asl_and",    0xf7c80000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1507                                                           RM6, RN4}},
1508 { "asl_and",    0xf7d80000,  0xffff0000, FMT_D10, AM33,  {IMM4_2, RN0,
1509                                                           RM6, RN4}},
1510 { "asl_cmp",    0xf7c10000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0, RM6, RN4}},
1511 { "asl_cmp",    0xf7d10000,  0xffff0000, FMT_D10, AM33,  {IMM4_2, RN0,
1512                                                           RM6, RN4, }},
1513 { "asl_cmp",    0xf7c50000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1514                                                           SIMM4_6, RN4}},
1515 { "asl_cmp",    0xf7d50000,  0xffff0000, FMT_D10, AM33,  {IMM4_2, RN0,
1516                                                           SIMM4_6, RN4}},
1517 { "asl_dmach",  0xf7c90000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1518                                                           RM6, RN4}},
1519 { "asl_dmach",  0xf7d90000,  0xffff0000, FMT_D10, AM33,  {IMM4_2, RN0,
1520                                                           RM6, RN4}},
1521 { "asl_mov",    0xf7c30000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0, RM6, RN4}},
1522 { "asl_mov",    0xf7d30000,  0xffff0000, FMT_D10, AM33,  {IMM4_2, RN0,
1523                                                           RM6, RN4}},
1524 { "asl_mov",    0xf7c70000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1525                                                           SIMM4_6, RN4}},
1526 { "asl_mov",    0xf7d70000,  0xffff0000, FMT_D10, AM33,  {IMM4_2, RN0,
1527                                                           SIMM4_6, RN4}},
1528 { "asl_or",     0xf7cc0000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1529                                                           RM6, RN4}},
1530 { "asl_or",     0xf7dc0000,  0xffff0000, FMT_D10, AM33,  {IMM4_2, RN0,
1531                                                           RM6, RN4}},
1532 { "asl_sat16",  0xf7cd0000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1533                                                           RM6, RN4}},
1534 { "asl_sat16",  0xf7dd0000,  0xffff0000, FMT_D10, AM33,  {IMM4_2, RN0,
1535                                                           RM6, RN4}},
1536 { "asl_sub",    0xf7c20000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0, RM6, RN4}},
1537 { "asl_sub",    0xf7d20000,  0xffff0000, FMT_D10, AM33,  {IMM4_2, RN0,
1538                                                           RM6, RN4}},
1539 { "asl_sub",    0xf7c60000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1540                                                           SIMM4_6, RN4}},
1541 { "asl_sub",    0xf7d60000,  0xffff0000, FMT_D10, AM33,  {IMM4_2, RN0,
1542                                                           SIMM4_6, RN4}},
1543 { "asl_swhw",   0xf7cb0000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1544                                                           RM6, RN4}},
1545 { "asl_swhw",   0xf7db0000,  0xffff0000, FMT_D10, AM33,  {IMM4_2, RN0,
1546                                                           RM6, RN4}},
1547 { "asl_xor",    0xf7ca0000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1548                                                           RM6, RN4}},
1549 { "asl_xor",    0xf7da0000,  0xffff0000, FMT_D10, AM33,  {IMM4_2, RN0,
1550                                                           RM6, RN4}},
1551 { "asr_add",    0xf7800000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0, RM6, RN4}},
1552 { "asr_add",    0xf7900000,  0xffff0000, FMT_D10, AM33,  {IMM4_2, RN0,
1553                                                           RM6, RN4}},
1554 { "asr_add",    0xf7840000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1555                                                           SIMM4_6, RN4}},
1556 { "asr_add",    0xf7940000,  0xffff0000, FMT_D10, AM33,  {IMM4_2, RN0,
1557                                                           SIMM4_6, RN4}},
1558 { "asr_and",    0xf7880000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1559                                                           RM6, RN4}},
1560 { "asr_and",    0xf7980000,  0xffff0000, FMT_D10, AM33,  {IMM4_2, RN0,
1561                                                           RM6, RN4}},
1562 { "asr_cmp",    0xf7810000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0, RM6, RN4}},
1563 { "asr_cmp",    0xf7910000,  0xffff0000, FMT_D10, AM33,  {IMM4_2, RN0,
1564                                                           RM6, RN4, }},
1565 { "asr_cmp",    0xf7850000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1566                                                           SIMM4_6, RN4}},
1567 { "asr_cmp",    0xf7950000,  0xffff0000, FMT_D10, AM33,  {IMM4_2, RN0,
1568                                                           SIMM4_6, RN4}},
1569 { "asr_dmach",  0xf7890000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1570                                                           RM6, RN4}},
1571 { "asr_dmach",  0xf7990000,  0xffff0000, FMT_D10, AM33,  {IMM4_2, RN0,
1572                                                           RM6, RN4}},
1573 { "asr_mov",    0xf7830000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0, RM6, RN4}},
1574 { "asr_mov",    0xf7930000,  0xffff0000, FMT_D10, AM33,  {IMM4_2, RN0,
1575                                                           RM6, RN4}},
1576 { "asr_mov",    0xf7870000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1577                                                           SIMM4_6, RN4}},
1578 { "asr_mov",    0xf7970000,  0xffff0000, FMT_D10, AM33,  {IMM4_2, RN0,
1579                                                           SIMM4_6, RN4}},
1580 { "asr_or",     0xf78c0000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1581                                                           RM6, RN4}},
1582 { "asr_or",     0xf79c0000,  0xffff0000, FMT_D10, AM33,  {IMM4_2, RN0,
1583                                                           RM6, RN4}},
1584 { "asr_sat16",  0xf78d0000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1585                                                           RM6, RN4}},
1586 { "asr_sat16",  0xf79d0000,  0xffff0000, FMT_D10, AM33,  {IMM4_2, RN0,
1587                                                           RM6, RN4}},
1588 { "asr_sub",    0xf7820000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0, RM6, RN4}},
1589 { "asr_sub",    0xf7920000,  0xffff0000, FMT_D10, AM33,  {IMM4_2, RN0,
1590                                                           RM6, RN4}},
1591 { "asr_sub",    0xf7860000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1592                                                           SIMM4_6, RN4}},
1593 { "asr_sub",    0xf7960000,  0xffff0000, FMT_D10, AM33,  {IMM4_2, RN0,
1594                                                           SIMM4_6, RN4}},
1595 { "asr_swhw",   0xf78b0000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1596                                                           RM6, RN4}},
1597 { "asr_swhw",   0xf79b0000,  0xffff0000, FMT_D10, AM33,  {IMM4_2, RN0,
1598                                                           RM6, RN4}},
1599 { "asr_xor",    0xf78a0000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1600                                                           RM6, RN4}},
1601 { "asr_xor",    0xf79a0000,  0xffff0000, FMT_D10, AM33,  {IMM4_2, RN0,
1602                                                           RM6, RN4}},
1603 { "cmp_and",    0xf7480000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1604                                                           RM6, RN4}},
1605 { "cmp_and",    0xf7580000,  0xffff0000, FMT_D10, AM33,  {SIMM4_2, RN0,
1606                                                           RM6, RN4}},
1607 { "cmp_dmach",  0xf7490000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1608                                                           RM6, RN4}},
1609 { "cmp_dmach",  0xf7590000,  0xffff0000, FMT_D10, AM33,  {SIMM4_2, RN0,
1610                                                           RM6, RN4}},
1611 { "cmp_or",     0xf74c0000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1612                                                           RM6, RN4}},
1613 { "cmp_or",     0xf75c0000,  0xffff0000, FMT_D10, AM33,  {SIMM4_2, RN0,
1614                                                           RM6, RN4}},
1615 { "cmp_sat16",  0xf74d0000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1616                                                           RM6, RN4}},
1617 { "cmp_sat16",  0xf75d0000,  0xffff0000, FMT_D10, AM33,  {SIMM4_2, RN0,
1618                                                           RM6, RN4}},
1619 { "cmp_swhw",   0xf74b0000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1620                                                           RM6, RN4}},
1621 { "cmp_swhw",   0xf75b0000,  0xffff0000, FMT_D10, AM33,  {SIMM4_2, RN0,
1622                                                           RM6, RN4}},
1623 { "cmp_xor",    0xf74a0000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1624                                                           RM6, RN4}},
1625 { "cmp_xor",    0xf75a0000,  0xffff0000, FMT_D10, AM33,  {SIMM4_2, RN0,
1626                                                           RM6, RN4}},
1627 { "lsr_add",    0xf7a00000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0, RM6, RN4}},
1628 { "lsr_add",    0xf7900000,  0xffff0000, FMT_D10, AM33,  {IMM4_2, RN0,
1629                                                           RM6, RN4}},
1630 { "lsr_add",    0xf7a40000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1631                                                           SIMM4_6, RN4}},
1632 { "lsr_add",    0xf7b40000,  0xffff0000, FMT_D10, AM33,  {IMM4_2, RN0,
1633                                                           SIMM4_6, RN4}},
1634 { "lsr_and",    0xf7a80000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1635                                                           RM6, RN4}},
1636 { "lsr_and",    0xf7b80000,  0xffff0000, FMT_D10, AM33,  {IMM4_2, RN0,
1637                                                           RM6, RN4}},
1638 { "lsr_cmp",    0xf7a10000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0, RM6, RN4}},
1639 { "lsr_cmp",    0xf7b10000,  0xffff0000, FMT_D10, AM33,  {IMM4_2, RN0,
1640                                                           RM6, RN4, }},
1641 { "lsr_cmp",    0xf7a50000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1642                                                           SIMM4_6, RN4}},
1643 { "lsr_cmp",    0xf7b50000,  0xffff0000, FMT_D10, AM33,  {IMM4_2, RN0,
1644                                                           SIMM4_6, RN4}},
1645 { "lsr_dmach",  0xf7a90000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1646                                                           RM6, RN4}},
1647 { "lsr_dmach",  0xf7b90000,  0xffff0000, FMT_D10, AM33,  {IMM4_2, RN0,
1648                                                           RM6, RN4}},
1649 { "lsr_mov",    0xf7a30000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0, RM6, RN4}},
1650 { "lsr_mov",    0xf7b30000,  0xffff0000, FMT_D10, AM33,  {IMM4_2, RN0,
1651                                                           RM6, RN4}},
1652 { "lsr_mov",    0xf7a70000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1653                                                           SIMM4_6, RN4}},
1654 { "lsr_mov",    0xf7b70000,  0xffff0000, FMT_D10, AM33,  {IMM4_2, RN0,
1655                                                           SIMM4_6, RN4}},
1656 { "lsr_or",     0xf7ac0000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1657                                                           RM6, RN4}},
1658 { "lsr_or",     0xf7bc0000,  0xffff0000, FMT_D10, AM33,  {IMM4_2, RN0,
1659                                                           RM6, RN4}},
1660 { "lsr_sat16",  0xf7ad0000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1661                                                           RM6, RN4}},
1662 { "lsr_sat16",  0xf7bd0000,  0xffff0000, FMT_D10, AM33,  {IMM4_2, RN0,
1663                                                           RM6, RN4}},
1664 { "lsr_sub",    0xf7a20000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0, RM6, RN4}},
1665 { "lsr_sub",    0xf7b20000,  0xffff0000, FMT_D10, AM33,  {IMM4_2, RN0,
1666                                                           RM6, RN4}},
1667 { "lsr_sub",    0xf7a60000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1668                                                           SIMM4_6, RN4}},
1669 { "lsr_sub",    0xf7b60000,  0xffff0000, FMT_D10, AM33,  {IMM4_2, RN0,
1670                                                           SIMM4_6, RN4}},
1671 { "lsr_swhw",   0xf7ab0000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1672                                                           RM6, RN4}},
1673 { "lsr_swhw",   0xf7bb0000,  0xffff0000, FMT_D10, AM33,  {IMM4_2, RN0,
1674                                                           RM6, RN4}},
1675 { "lsr_xor",    0xf7aa0000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1676                                                           RM6, RN4}},
1677 { "lsr_xor",    0xf7ba0000,  0xffff0000, FMT_D10, AM33,  {IMM4_2, RN0,
1678                                                           RM6, RN4}},
1679 { "mov_and",    0xf7680000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1680                                                           RM6, RN4}},
1681 { "mov_and",    0xf7780000,  0xffff0000, FMT_D10, AM33,  {SIMM4_2, RN0,
1682                                                           RM6, RN4}},
1683 { "mov_dmach",  0xf7690000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1684                                                           RM6, RN4}},
1685 { "mov_dmach",  0xf7790000,  0xffff0000, FMT_D10, AM33,  {SIMM4_2, RN0,
1686                                                           RM6, RN4}},
1687 { "mov_or",     0xf76c0000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1688                                                           RM6, RN4}},
1689 { "mov_or",     0xf77c0000,  0xffff0000, FMT_D10, AM33,  {SIMM4_2, RN0,
1690                                                           RM6, RN4}},
1691 { "mov_sat16",  0xf76d0000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1692                                                           RM6, RN4}},
1693 { "mov_sat16",  0xf77d0000,  0xffff0000, FMT_D10, AM33,  {SIMM4_2, RN0,
1694                                                           RM6, RN4}},
1695 { "mov_swhw",   0xf76b0000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1696                                                           RM6, RN4}},
1697 { "mov_swhw",   0xf77b0000,  0xffff0000, FMT_D10, AM33,  {SIMM4_2, RN0,
1698                                                           RM6, RN4}},
1699 { "mov_xor",    0xf76a0000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1700                                                           RM6, RN4}},
1701 { "mov_xor",    0xf77a0000,  0xffff0000, FMT_D10, AM33,  {SIMM4_2, RN0,
1702                                                           RM6, RN4}},
1703 { "sub_and",    0xf7280000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1704                                                           RM6, RN4}},
1705 { "sub_and",    0xf7380000,  0xffff0000, FMT_D10, AM33,  {SIMM4_2, RN0,
1706                                                           RM6, RN4}},
1707 { "sub_dmach",  0xf7290000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1708                                                           RM6, RN4}},
1709 { "sub_dmach",  0xf7390000,  0xffff0000, FMT_D10, AM33,  {SIMM4_2, RN0,
1710                                                           RM6, RN4}},
1711 { "sub_or",     0xf72c0000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1712                                                           RM6, RN4}},
1713 { "sub_or",     0xf73c0000,  0xffff0000, FMT_D10, AM33,  {SIMM4_2, RN0,
1714                                                           RM6, RN4}},
1715 { "sub_sat16",  0xf72d0000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1716                                                           RM6, RN4}},
1717 { "sub_sat16",  0xf73d0000,  0xffff0000, FMT_D10, AM33,  {SIMM4_2, RN0,
1718                                                           RM6, RN4}},
1719 { "sub_swhw",   0xf72b0000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1720                                                           RM6, RN4}},
1721 { "sub_swhw",   0xf73b0000,  0xffff0000, FMT_D10, AM33,  {SIMM4_2, RN0,
1722                                                           RM6, RN4}},
1723 { "sub_xor",    0xf72a0000,  0xffff0000, FMT_D10, AM33,  {RM2, RN0,
1724                                                           RM6, RN4}},
1725 { "sub_xor",    0xf73a0000,  0xffff0000, FMT_D10, AM33,  {SIMM4_2, RN0,
1726                                                           RM6, RN4}},
1727 { "mov_llt",    0xf7e00000,  0xffff000f, FMT_D10, AM33,  {MEMINC2 (RN4,SIMM4_2),
1728                                                           RM6}},
1729 { "mov_lgt",    0xf7e00001,  0xffff000f, FMT_D10, AM33,  {MEMINC2 (RN4,SIMM4_2),
1730                                                           RM6}},
1731 { "mov_lge",    0xf7e00002,  0xffff000f, FMT_D10, AM33,  {MEMINC2 (RN4,SIMM4_2),
1732                                                           RM6}},
1733 { "mov_lle",    0xf7e00003,  0xffff000f, FMT_D10, AM33,  {MEMINC2 (RN4,SIMM4_2),
1734                                                           RM6}},
1735 { "mov_lcs",    0xf7e00004,  0xffff000f, FMT_D10, AM33,  {MEMINC2 (RN4,SIMM4_2),
1736                                                           RM6}},
1737 { "mov_lhi",    0xf7e00005,  0xffff000f, FMT_D10, AM33,  {MEMINC2 (RN4,SIMM4_2),
1738                                                           RM6}},
1739 { "mov_lcc",    0xf7e00006,  0xffff000f, FMT_D10, AM33,  {MEMINC2 (RN4,SIMM4_2),
1740                                                           RM6}},
1741 { "mov_lls",    0xf7e00007,  0xffff000f, FMT_D10, AM33,  {MEMINC2 (RN4,SIMM4_2),
1742                                                           RM6}},
1743 { "mov_leq",    0xf7e00008,  0xffff000f, FMT_D10, AM33,  {MEMINC2 (RN4,SIMM4_2),
1744                                                           RM6}},
1745 { "mov_lne",    0xf7e00009,  0xffff000f, FMT_D10, AM33,  {MEMINC2 (RN4,SIMM4_2),
1746                                                           RM6}},
1747 { "mov_lra",    0xf7e0000a,  0xffff000f, FMT_D10, AM33,  {MEMINC2 (RN4,SIMM4_2),
1748                                                           RM6}},
1749 { "llt_mov",    0xf7e00000,  0xffff000f, FMT_D10, AM33,  {MEMINC2 (RN4,SIMM4_2),
1750                                                           RM6}},
1751 { "lgt_mov",    0xf7e00001,  0xffff000f, FMT_D10, AM33,  {MEMINC2 (RN4,SIMM4_2),
1752                                                           RM6}},
1753 { "lge_mov",    0xf7e00002,  0xffff000f, FMT_D10, AM33,  {MEMINC2 (RN4,SIMM4_2),
1754                                                           RM6}},
1755 { "lle_mov",    0xf7e00003,  0xffff000f, FMT_D10, AM33,  {MEMINC2 (RN4,SIMM4_2),
1756                                                           RM6}},
1757 { "lcs_mov",    0xf7e00004,  0xffff000f, FMT_D10, AM33,  {MEMINC2 (RN4,SIMM4_2),
1758                                                           RM6}},
1759 { "lhi_mov",    0xf7e00005,  0xffff000f, FMT_D10, AM33,  {MEMINC2 (RN4,SIMM4_2),
1760                                                           RM6}},
1761 { "lcc_mov",    0xf7e00006,  0xffff000f, FMT_D10, AM33,  {MEMINC2 (RN4,SIMM4_2),
1762                                                           RM6}},
1763 { "lls_mov",    0xf7e00007,  0xffff000f, FMT_D10, AM33,  {MEMINC2 (RN4,SIMM4_2),
1764                                                           RM6}},
1765 { "leq_mov",    0xf7e00008,  0xffff000f, FMT_D10, AM33,  {MEMINC2 (RN4,SIMM4_2),
1766                                                           RM6}},
1767 { "lne_mov",    0xf7e00009,  0xffff000f, FMT_D10, AM33,  {MEMINC2 (RN4,SIMM4_2),
1768                                                           RM6}},
1769 { "lra_mov",    0xf7e0000a,  0xffff000f, FMT_D10, AM33,  {MEMINC2 (RN4,SIMM4_2),
1770                                                           RM6}},
1771 /* end-sanitize-am33 */
1772
1773 { 0, 0, 0, 0, 0, {0}},
1774
1775 } ;
1776
1777 const int mn10300_num_opcodes =
1778   sizeof (mn10300_opcodes) / sizeof (mn10300_opcodes[0]);
1779
1780 \f