1 /* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
4 THIS FILE IS MACHINE GENERATED WITH CGEN.
6 Copyright (C) 1996-2018 Free Software Foundation, Inc.
8 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
10 This file is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 It is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License along
21 with this program; if not, write to the Free Software Foundation, Inc.,
22 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
32 #include "lm32-desc.h"
35 #include "libiberty.h"
40 static const CGEN_ATTR_ENTRY bool_attr[] =
47 static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
49 { "base", MACH_BASE },
50 { "lm32", MACH_LM32 },
55 static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
62 const CGEN_ATTR_TABLE lm32_cgen_ifield_attr_table[] =
64 { "MACH", & MACH_attr[0], & MACH_attr[0] },
65 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
66 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
67 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
68 { "RESERVED", &bool_attr[0], &bool_attr[0] },
69 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
70 { "SIGNED", &bool_attr[0], &bool_attr[0] },
74 const CGEN_ATTR_TABLE lm32_cgen_hardware_attr_table[] =
76 { "MACH", & MACH_attr[0], & MACH_attr[0] },
77 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
78 { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
79 { "PC", &bool_attr[0], &bool_attr[0] },
80 { "PROFILE", &bool_attr[0], &bool_attr[0] },
84 const CGEN_ATTR_TABLE lm32_cgen_operand_attr_table[] =
86 { "MACH", & MACH_attr[0], & MACH_attr[0] },
87 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
88 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
89 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
90 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
91 { "SIGNED", &bool_attr[0], &bool_attr[0] },
92 { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
93 { "RELAX", &bool_attr[0], &bool_attr[0] },
94 { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
98 const CGEN_ATTR_TABLE lm32_cgen_insn_attr_table[] =
100 { "MACH", & MACH_attr[0], & MACH_attr[0] },
101 { "ALIAS", &bool_attr[0], &bool_attr[0] },
102 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
103 { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
104 { "COND-CTI", &bool_attr[0], &bool_attr[0] },
105 { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
106 { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
107 { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
108 { "RELAXED", &bool_attr[0], &bool_attr[0] },
109 { "NO-DIS", &bool_attr[0], &bool_attr[0] },
110 { "PBB", &bool_attr[0], &bool_attr[0] },
114 /* Instruction set variants. */
116 static const CGEN_ISA lm32_cgen_isa_table[] = {
117 { "lm32", 32, 32, 32, 32 },
121 /* Machine variants. */
123 static const CGEN_MACH lm32_cgen_mach_table[] = {
124 { "lm32", "lm32", MACH_LM32, 0 },
128 static CGEN_KEYWORD_ENTRY lm32_cgen_opval_h_gr_entries[] =
130 { "gp", 26, {0, {{{0, 0}}}}, 0, 0 },
131 { "fp", 27, {0, {{{0, 0}}}}, 0, 0 },
132 { "sp", 28, {0, {{{0, 0}}}}, 0, 0 },
133 { "ra", 29, {0, {{{0, 0}}}}, 0, 0 },
134 { "ea", 30, {0, {{{0, 0}}}}, 0, 0 },
135 { "ba", 31, {0, {{{0, 0}}}}, 0, 0 },
136 { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
137 { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
138 { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
139 { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
140 { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
141 { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
142 { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
143 { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
144 { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
145 { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
146 { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
147 { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
148 { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
149 { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
150 { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
151 { "r15", 15, {0, {{{0, 0}}}}, 0, 0 },
152 { "r16", 16, {0, {{{0, 0}}}}, 0, 0 },
153 { "r17", 17, {0, {{{0, 0}}}}, 0, 0 },
154 { "r18", 18, {0, {{{0, 0}}}}, 0, 0 },
155 { "r19", 19, {0, {{{0, 0}}}}, 0, 0 },
156 { "r20", 20, {0, {{{0, 0}}}}, 0, 0 },
157 { "r21", 21, {0, {{{0, 0}}}}, 0, 0 },
158 { "r22", 22, {0, {{{0, 0}}}}, 0, 0 },
159 { "r23", 23, {0, {{{0, 0}}}}, 0, 0 },
160 { "r24", 24, {0, {{{0, 0}}}}, 0, 0 },
161 { "r25", 25, {0, {{{0, 0}}}}, 0, 0 },
162 { "r26", 26, {0, {{{0, 0}}}}, 0, 0 },
163 { "r27", 27, {0, {{{0, 0}}}}, 0, 0 },
164 { "r28", 28, {0, {{{0, 0}}}}, 0, 0 },
165 { "r29", 29, {0, {{{0, 0}}}}, 0, 0 },
166 { "r30", 30, {0, {{{0, 0}}}}, 0, 0 },
167 { "r31", 31, {0, {{{0, 0}}}}, 0, 0 }
170 CGEN_KEYWORD lm32_cgen_opval_h_gr =
172 & lm32_cgen_opval_h_gr_entries[0],
177 static CGEN_KEYWORD_ENTRY lm32_cgen_opval_h_csr_entries[] =
179 { "IE", 0, {0, {{{0, 0}}}}, 0, 0 },
180 { "IM", 1, {0, {{{0, 0}}}}, 0, 0 },
181 { "IP", 2, {0, {{{0, 0}}}}, 0, 0 },
182 { "ICC", 3, {0, {{{0, 0}}}}, 0, 0 },
183 { "DCC", 4, {0, {{{0, 0}}}}, 0, 0 },
184 { "CC", 5, {0, {{{0, 0}}}}, 0, 0 },
185 { "CFG", 6, {0, {{{0, 0}}}}, 0, 0 },
186 { "EBA", 7, {0, {{{0, 0}}}}, 0, 0 },
187 { "DC", 8, {0, {{{0, 0}}}}, 0, 0 },
188 { "DEBA", 9, {0, {{{0, 0}}}}, 0, 0 },
189 { "CFG2", 10, {0, {{{0, 0}}}}, 0, 0 },
190 { "JTX", 14, {0, {{{0, 0}}}}, 0, 0 },
191 { "JRX", 15, {0, {{{0, 0}}}}, 0, 0 },
192 { "BP0", 16, {0, {{{0, 0}}}}, 0, 0 },
193 { "BP1", 17, {0, {{{0, 0}}}}, 0, 0 },
194 { "BP2", 18, {0, {{{0, 0}}}}, 0, 0 },
195 { "BP3", 19, {0, {{{0, 0}}}}, 0, 0 },
196 { "WP0", 24, {0, {{{0, 0}}}}, 0, 0 },
197 { "WP1", 25, {0, {{{0, 0}}}}, 0, 0 },
198 { "WP2", 26, {0, {{{0, 0}}}}, 0, 0 },
199 { "WP3", 27, {0, {{{0, 0}}}}, 0, 0 },
200 { "PSW", 29, {0, {{{0, 0}}}}, 0, 0 },
201 { "TLBVADDR", 30, {0, {{{0, 0}}}}, 0, 0 },
202 { "TLBPADDR", 31, {0, {{{0, 0}}}}, 0, 0 },
203 { "TLBBADVADDR", 31, {0, {{{0, 0}}}}, 0, 0 }
206 CGEN_KEYWORD lm32_cgen_opval_h_csr =
208 & lm32_cgen_opval_h_csr_entries[0],
214 /* The hardware table. */
216 #define A(a) (1 << CGEN_HW_##a)
218 const CGEN_HW_ENTRY lm32_cgen_hw_table[] =
220 { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
221 { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
222 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
223 { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
224 { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
225 { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
226 { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & lm32_cgen_opval_h_gr, { 0, { { { (1<<MACH_BASE), 0 } } } } },
227 { "h-csr", HW_H_CSR, CGEN_ASM_KEYWORD, (PTR) & lm32_cgen_opval_h_csr, { 0, { { { (1<<MACH_BASE), 0 } } } } },
228 { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
234 /* The instruction field table. */
236 #define A(a) (1 << CGEN_IFLD_##a)
238 const CGEN_IFLD lm32_cgen_ifld_table[] =
240 { LM32_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
241 { LM32_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
242 { LM32_F_OPCODE, "f-opcode", 0, 32, 31, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } },
243 { LM32_F_R0, "f-r0", 0, 32, 25, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } },
244 { LM32_F_R1, "f-r1", 0, 32, 20, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } },
245 { LM32_F_R2, "f-r2", 0, 32, 15, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } },
246 { LM32_F_RESV0, "f-resv0", 0, 32, 10, 11, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
247 { LM32_F_SHIFT, "f-shift", 0, 32, 4, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } },
248 { LM32_F_IMM, "f-imm", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
249 { LM32_F_UIMM, "f-uimm", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
250 { LM32_F_CSR, "f-csr", 0, 32, 25, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } },
251 { LM32_F_USER, "f-user", 0, 32, 10, 11, { 0, { { { (1<<MACH_BASE), 0 } } } } },
252 { LM32_F_EXCEPTION, "f-exception", 0, 32, 25, 26, { 0, { { { (1<<MACH_BASE), 0 } } } } },
253 { LM32_F_BRANCH, "f-branch", 0, 32, 15, 16, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
254 { LM32_F_CALL, "f-call", 0, 32, 25, 26, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
255 { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
262 /* multi ifield declarations */
266 /* multi ifield definitions */
269 /* The operand table. */
271 #define A(a) (1 << CGEN_OPERAND_##a)
272 #define OPERAND(op) LM32_OPERAND_##op
274 const CGEN_OPERAND lm32_cgen_operand_table[] =
276 /* pc: program counter */
277 { "pc", LM32_OPERAND_PC, HW_H_PC, 0, 0,
278 { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_NIL] } },
279 { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
281 { "r0", LM32_OPERAND_R0, HW_H_GR, 25, 5,
282 { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_R0] } },
283 { 0, { { { (1<<MACH_BASE), 0 } } } } },
285 { "r1", LM32_OPERAND_R1, HW_H_GR, 20, 5,
286 { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_R1] } },
287 { 0, { { { (1<<MACH_BASE), 0 } } } } },
289 { "r2", LM32_OPERAND_R2, HW_H_GR, 15, 5,
290 { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_R2] } },
291 { 0, { { { (1<<MACH_BASE), 0 } } } } },
292 /* shift: shift amout */
293 { "shift", LM32_OPERAND_SHIFT, HW_H_UINT, 4, 5,
294 { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_SHIFT] } },
295 { 0, { { { (1<<MACH_BASE), 0 } } } } },
296 /* imm: signed immediate */
297 { "imm", LM32_OPERAND_IMM, HW_H_SINT, 15, 16,
298 { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } },
299 { 0, { { { (1<<MACH_BASE), 0 } } } } },
300 /* uimm: unsigned immediate */
301 { "uimm", LM32_OPERAND_UIMM, HW_H_UINT, 15, 16,
302 { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_UIMM] } },
303 { 0, { { { (1<<MACH_BASE), 0 } } } } },
304 /* branch: branch offset */
305 { "branch", LM32_OPERAND_BRANCH, HW_H_IADDR, 15, 16,
306 { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_BRANCH] } },
307 { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
308 /* call: call offset */
309 { "call", LM32_OPERAND_CALL, HW_H_IADDR, 25, 26,
310 { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_CALL] } },
311 { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
313 { "csr", LM32_OPERAND_CSR, HW_H_CSR, 25, 5,
314 { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_CSR] } },
315 { 0, { { { (1<<MACH_BASE), 0 } } } } },
317 { "user", LM32_OPERAND_USER, HW_H_UINT, 10, 11,
318 { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_USER] } },
319 { 0, { { { (1<<MACH_BASE), 0 } } } } },
320 /* exception: exception */
321 { "exception", LM32_OPERAND_EXCEPTION, HW_H_UINT, 25, 26,
322 { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_EXCEPTION] } },
323 { 0, { { { (1<<MACH_BASE), 0 } } } } },
324 /* hi16: high 16-bit immediate */
325 { "hi16", LM32_OPERAND_HI16, HW_H_UINT, 15, 16,
326 { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_UIMM] } },
327 { 0, { { { (1<<MACH_BASE), 0 } } } } },
328 /* lo16: low 16-bit immediate */
329 { "lo16", LM32_OPERAND_LO16, HW_H_UINT, 15, 16,
330 { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_UIMM] } },
331 { 0, { { { (1<<MACH_BASE), 0 } } } } },
332 /* gp16: gp relative 16-bit immediate */
333 { "gp16", LM32_OPERAND_GP16, HW_H_SINT, 15, 16,
334 { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } },
335 { 0, { { { (1<<MACH_BASE), 0 } } } } },
336 /* got16: got 16-bit immediate */
337 { "got16", LM32_OPERAND_GOT16, HW_H_SINT, 15, 16,
338 { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } },
339 { 0, { { { (1<<MACH_BASE), 0 } } } } },
340 /* gotoffhi16: got offset high 16-bit immediate */
341 { "gotoffhi16", LM32_OPERAND_GOTOFFHI16, HW_H_SINT, 15, 16,
342 { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } },
343 { 0, { { { (1<<MACH_BASE), 0 } } } } },
344 /* gotofflo16: got offset low 16-bit immediate */
345 { "gotofflo16", LM32_OPERAND_GOTOFFLO16, HW_H_SINT, 15, 16,
346 { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } },
347 { 0, { { { (1<<MACH_BASE), 0 } } } } },
350 { 0, { (const PTR) 0 } },
351 { 0, { { { (1<<MACH_BASE), 0 } } } } }
357 /* The instruction table. */
359 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
360 #define A(a) (1 << CGEN_INSN_##a)
362 static const CGEN_IBASE lm32_cgen_insn_table[MAX_INSNS] =
364 /* Special null first entry.
365 A `num' value of zero is thus invalid.
366 Also, the special `invalid' insn resides here. */
367 { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
368 /* add $r2,$r0,$r1 */
370 LM32_INSN_ADD, "add", "add", 32,
371 { 0, { { { (1<<MACH_BASE), 0 } } } }
373 /* addi $r1,$r0,$imm */
375 LM32_INSN_ADDI, "addi", "addi", 32,
376 { 0, { { { (1<<MACH_BASE), 0 } } } }
378 /* and $r2,$r0,$r1 */
380 LM32_INSN_AND, "and", "and", 32,
381 { 0, { { { (1<<MACH_BASE), 0 } } } }
383 /* andi $r1,$r0,$uimm */
385 LM32_INSN_ANDI, "andi", "andi", 32,
386 { 0, { { { (1<<MACH_BASE), 0 } } } }
388 /* andhi $r1,$r0,$hi16 */
390 LM32_INSN_ANDHII, "andhii", "andhi", 32,
391 { 0, { { { (1<<MACH_BASE), 0 } } } }
395 LM32_INSN_B, "b", "b", 32,
396 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
400 LM32_INSN_BI, "bi", "bi", 32,
401 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
403 /* be $r0,$r1,$branch */
405 LM32_INSN_BE, "be", "be", 32,
406 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
408 /* bg $r0,$r1,$branch */
410 LM32_INSN_BG, "bg", "bg", 32,
411 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
413 /* bge $r0,$r1,$branch */
415 LM32_INSN_BGE, "bge", "bge", 32,
416 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
418 /* bgeu $r0,$r1,$branch */
420 LM32_INSN_BGEU, "bgeu", "bgeu", 32,
421 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
423 /* bgu $r0,$r1,$branch */
425 LM32_INSN_BGU, "bgu", "bgu", 32,
426 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
428 /* bne $r0,$r1,$branch */
430 LM32_INSN_BNE, "bne", "bne", 32,
431 { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
435 LM32_INSN_CALL, "call", "call", 32,
436 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
440 LM32_INSN_CALLI, "calli", "calli", 32,
441 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
443 /* cmpe $r2,$r0,$r1 */
445 LM32_INSN_CMPE, "cmpe", "cmpe", 32,
446 { 0, { { { (1<<MACH_BASE), 0 } } } }
448 /* cmpei $r1,$r0,$imm */
450 LM32_INSN_CMPEI, "cmpei", "cmpei", 32,
451 { 0, { { { (1<<MACH_BASE), 0 } } } }
453 /* cmpg $r2,$r0,$r1 */
455 LM32_INSN_CMPG, "cmpg", "cmpg", 32,
456 { 0, { { { (1<<MACH_BASE), 0 } } } }
458 /* cmpgi $r1,$r0,$imm */
460 LM32_INSN_CMPGI, "cmpgi", "cmpgi", 32,
461 { 0, { { { (1<<MACH_BASE), 0 } } } }
463 /* cmpge $r2,$r0,$r1 */
465 LM32_INSN_CMPGE, "cmpge", "cmpge", 32,
466 { 0, { { { (1<<MACH_BASE), 0 } } } }
468 /* cmpgei $r1,$r0,$imm */
470 LM32_INSN_CMPGEI, "cmpgei", "cmpgei", 32,
471 { 0, { { { (1<<MACH_BASE), 0 } } } }
473 /* cmpgeu $r2,$r0,$r1 */
475 LM32_INSN_CMPGEU, "cmpgeu", "cmpgeu", 32,
476 { 0, { { { (1<<MACH_BASE), 0 } } } }
478 /* cmpgeui $r1,$r0,$uimm */
480 LM32_INSN_CMPGEUI, "cmpgeui", "cmpgeui", 32,
481 { 0, { { { (1<<MACH_BASE), 0 } } } }
483 /* cmpgu $r2,$r0,$r1 */
485 LM32_INSN_CMPGU, "cmpgu", "cmpgu", 32,
486 { 0, { { { (1<<MACH_BASE), 0 } } } }
488 /* cmpgui $r1,$r0,$uimm */
490 LM32_INSN_CMPGUI, "cmpgui", "cmpgui", 32,
491 { 0, { { { (1<<MACH_BASE), 0 } } } }
493 /* cmpne $r2,$r0,$r1 */
495 LM32_INSN_CMPNE, "cmpne", "cmpne", 32,
496 { 0, { { { (1<<MACH_BASE), 0 } } } }
498 /* cmpnei $r1,$r0,$imm */
500 LM32_INSN_CMPNEI, "cmpnei", "cmpnei", 32,
501 { 0, { { { (1<<MACH_BASE), 0 } } } }
503 /* divu $r2,$r0,$r1 */
505 LM32_INSN_DIVU, "divu", "divu", 32,
506 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
508 /* lb $r1,($r0+$imm) */
510 LM32_INSN_LB, "lb", "lb", 32,
511 { 0, { { { (1<<MACH_BASE), 0 } } } }
513 /* lbu $r1,($r0+$imm) */
515 LM32_INSN_LBU, "lbu", "lbu", 32,
516 { 0, { { { (1<<MACH_BASE), 0 } } } }
518 /* lh $r1,($r0+$imm) */
520 LM32_INSN_LH, "lh", "lh", 32,
521 { 0, { { { (1<<MACH_BASE), 0 } } } }
523 /* lhu $r1,($r0+$imm) */
525 LM32_INSN_LHU, "lhu", "lhu", 32,
526 { 0, { { { (1<<MACH_BASE), 0 } } } }
528 /* lw $r1,($r0+$imm) */
530 LM32_INSN_LW, "lw", "lw", 32,
531 { 0, { { { (1<<MACH_BASE), 0 } } } }
533 /* modu $r2,$r0,$r1 */
535 LM32_INSN_MODU, "modu", "modu", 32,
536 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
538 /* mul $r2,$r0,$r1 */
540 LM32_INSN_MUL, "mul", "mul", 32,
541 { 0, { { { (1<<MACH_BASE), 0 } } } }
543 /* muli $r1,$r0,$imm */
545 LM32_INSN_MULI, "muli", "muli", 32,
546 { 0, { { { (1<<MACH_BASE), 0 } } } }
548 /* nor $r2,$r0,$r1 */
550 LM32_INSN_NOR, "nor", "nor", 32,
551 { 0, { { { (1<<MACH_BASE), 0 } } } }
553 /* nori $r1,$r0,$uimm */
555 LM32_INSN_NORI, "nori", "nori", 32,
556 { 0, { { { (1<<MACH_BASE), 0 } } } }
560 LM32_INSN_OR, "or", "or", 32,
561 { 0, { { { (1<<MACH_BASE), 0 } } } }
563 /* ori $r1,$r0,$lo16 */
565 LM32_INSN_ORI, "ori", "ori", 32,
566 { 0, { { { (1<<MACH_BASE), 0 } } } }
568 /* orhi $r1,$r0,$hi16 */
570 LM32_INSN_ORHII, "orhii", "orhi", 32,
571 { 0, { { { (1<<MACH_BASE), 0 } } } }
575 LM32_INSN_RCSR, "rcsr", "rcsr", 32,
576 { 0, { { { (1<<MACH_BASE), 0 } } } }
578 /* sb ($r0+$imm),$r1 */
580 LM32_INSN_SB, "sb", "sb", 32,
581 { 0, { { { (1<<MACH_BASE), 0 } } } }
585 LM32_INSN_SEXTB, "sextb", "sextb", 32,
586 { 0, { { { (1<<MACH_BASE), 0 } } } }
590 LM32_INSN_SEXTH, "sexth", "sexth", 32,
591 { 0, { { { (1<<MACH_BASE), 0 } } } }
593 /* sh ($r0+$imm),$r1 */
595 LM32_INSN_SH, "sh", "sh", 32,
596 { 0, { { { (1<<MACH_BASE), 0 } } } }
600 LM32_INSN_SL, "sl", "sl", 32,
601 { 0, { { { (1<<MACH_BASE), 0 } } } }
603 /* sli $r1,$r0,$imm */
605 LM32_INSN_SLI, "sli", "sli", 32,
606 { 0, { { { (1<<MACH_BASE), 0 } } } }
610 LM32_INSN_SR, "sr", "sr", 32,
611 { 0, { { { (1<<MACH_BASE), 0 } } } }
613 /* sri $r1,$r0,$imm */
615 LM32_INSN_SRI, "sri", "sri", 32,
616 { 0, { { { (1<<MACH_BASE), 0 } } } }
618 /* sru $r2,$r0,$r1 */
620 LM32_INSN_SRU, "sru", "sru", 32,
621 { 0, { { { (1<<MACH_BASE), 0 } } } }
623 /* srui $r1,$r0,$imm */
625 LM32_INSN_SRUI, "srui", "srui", 32,
626 { 0, { { { (1<<MACH_BASE), 0 } } } }
628 /* sub $r2,$r0,$r1 */
630 LM32_INSN_SUB, "sub", "sub", 32,
631 { 0, { { { (1<<MACH_BASE), 0 } } } }
633 /* sw ($r0+$imm),$r1 */
635 LM32_INSN_SW, "sw", "sw", 32,
636 { 0, { { { (1<<MACH_BASE), 0 } } } }
638 /* user $r2,$r0,$r1,$user */
640 LM32_INSN_USER, "user", "user", 32,
641 { 0, { { { (1<<MACH_BASE), 0 } } } }
645 LM32_INSN_WCSR, "wcsr", "wcsr", 32,
646 { 0, { { { (1<<MACH_BASE), 0 } } } }
648 /* xor $r2,$r0,$r1 */
650 LM32_INSN_XOR, "xor", "xor", 32,
651 { 0, { { { (1<<MACH_BASE), 0 } } } }
653 /* xori $r1,$r0,$uimm */
655 LM32_INSN_XORI, "xori", "xori", 32,
656 { 0, { { { (1<<MACH_BASE), 0 } } } }
658 /* xnor $r2,$r0,$r1 */
660 LM32_INSN_XNOR, "xnor", "xnor", 32,
661 { 0, { { { (1<<MACH_BASE), 0 } } } }
663 /* xnori $r1,$r0,$uimm */
665 LM32_INSN_XNORI, "xnori", "xnori", 32,
666 { 0, { { { (1<<MACH_BASE), 0 } } } }
670 LM32_INSN_BREAK, "break", "break", 32,
671 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
675 LM32_INSN_SCALL, "scall", "scall", 32,
676 { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
680 -1, "bret", "bret", 32,
681 { 0|A(ALIAS)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
685 -1, "eret", "eret", 32,
686 { 0|A(ALIAS)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
690 -1, "ret", "ret", 32,
691 { 0|A(ALIAS)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
696 { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
700 -1, "mvi", "mvi", 32,
701 { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
705 -1, "mvui", "mvu", 32,
706 { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
710 -1, "mvhi", "mvhi", 32,
711 { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
715 -1, "mva", "mva", 32,
716 { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
720 -1, "not", "not", 32,
721 { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
725 -1, "nop", "nop", 32,
726 { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
730 -1, "lbgprel", "lb", 32,
731 { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
735 -1, "lbugprel", "lbu", 32,
736 { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
740 -1, "lhgprel", "lh", 32,
741 { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
745 -1, "lhugprel", "lhu", 32,
746 { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
750 -1, "lwgprel", "lw", 32,
751 { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
755 -1, "sbgprel", "sb", 32,
756 { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
760 -1, "shgprel", "sh", 32,
761 { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
765 -1, "swgprel", "sw", 32,
766 { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
768 /* lw $r1,(gp+$got16) */
770 -1, "lwgotrel", "lw", 32,
771 { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
773 /* orhi $r1,$r0,$gotoffhi16 */
775 -1, "orhigotoffi", "orhi", 32,
776 { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
778 /* addi $r1,$r0,$gotofflo16 */
780 -1, "addgotoff", "addi", 32,
781 { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
783 /* sw ($r0+$gotofflo16),$r1 */
785 -1, "swgotoff", "sw", 32,
786 { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
788 /* lw $r1,($r0+$gotofflo16) */
790 -1, "lwgotoff", "lw", 32,
791 { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
793 /* sh ($r0+$gotofflo16),$r1 */
795 -1, "shgotoff", "sh", 32,
796 { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
798 /* lh $r1,($r0+$gotofflo16) */
800 -1, "lhgotoff", "lh", 32,
801 { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
803 /* lhu $r1,($r0+$gotofflo16) */
805 -1, "lhugotoff", "lhu", 32,
806 { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
808 /* sb ($r0+$gotofflo16),$r1 */
810 -1, "sbgotoff", "sb", 32,
811 { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
813 /* lb $r1,($r0+$gotofflo16) */
815 -1, "lbgotoff", "lb", 32,
816 { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
818 /* lbu $r1,($r0+$gotofflo16) */
820 -1, "lbugotoff", "lbu", 32,
821 { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
828 /* Initialize anything needed to be done once, before any cpu_open call. */
835 static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
836 static void build_hw_table (CGEN_CPU_TABLE *);
837 static void build_ifield_table (CGEN_CPU_TABLE *);
838 static void build_operand_table (CGEN_CPU_TABLE *);
839 static void build_insn_table (CGEN_CPU_TABLE *);
840 static void lm32_cgen_rebuild_tables (CGEN_CPU_TABLE *);
842 /* Subroutine of lm32_cgen_cpu_open to look up a mach via its bfd name. */
844 static const CGEN_MACH *
845 lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
849 if (strcmp (name, table->bfd_name) == 0)
856 /* Subroutine of lm32_cgen_cpu_open to build the hardware table. */
859 build_hw_table (CGEN_CPU_TABLE *cd)
862 int machs = cd->machs;
863 const CGEN_HW_ENTRY *init = & lm32_cgen_hw_table[0];
864 /* MAX_HW is only an upper bound on the number of selected entries.
865 However each entry is indexed by it's enum so there can be holes in
867 const CGEN_HW_ENTRY **selected =
868 (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
870 cd->hw_table.init_entries = init;
871 cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
872 memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
873 /* ??? For now we just use machs to determine which ones we want. */
874 for (i = 0; init[i].name != NULL; ++i)
875 if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
877 selected[init[i].type] = &init[i];
878 cd->hw_table.entries = selected;
879 cd->hw_table.num_entries = MAX_HW;
882 /* Subroutine of lm32_cgen_cpu_open to build the hardware table. */
885 build_ifield_table (CGEN_CPU_TABLE *cd)
887 cd->ifld_table = & lm32_cgen_ifld_table[0];
890 /* Subroutine of lm32_cgen_cpu_open to build the hardware table. */
893 build_operand_table (CGEN_CPU_TABLE *cd)
896 int machs = cd->machs;
897 const CGEN_OPERAND *init = & lm32_cgen_operand_table[0];
898 /* MAX_OPERANDS is only an upper bound on the number of selected entries.
899 However each entry is indexed by it's enum so there can be holes in
901 const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
903 cd->operand_table.init_entries = init;
904 cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
905 memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
906 /* ??? For now we just use mach to determine which ones we want. */
907 for (i = 0; init[i].name != NULL; ++i)
908 if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
910 selected[init[i].type] = &init[i];
911 cd->operand_table.entries = selected;
912 cd->operand_table.num_entries = MAX_OPERANDS;
915 /* Subroutine of lm32_cgen_cpu_open to build the hardware table.
916 ??? This could leave out insns not supported by the specified mach/isa,
917 but that would cause errors like "foo only supported by bar" to become
918 "unknown insn", so for now we include all insns and require the app to
919 do the checking later.
920 ??? On the other hand, parsing of such insns may require their hardware or
921 operand elements to be in the table [which they mightn't be]. */
924 build_insn_table (CGEN_CPU_TABLE *cd)
927 const CGEN_IBASE *ib = & lm32_cgen_insn_table[0];
928 CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
930 memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
931 for (i = 0; i < MAX_INSNS; ++i)
932 insns[i].base = &ib[i];
933 cd->insn_table.init_entries = insns;
934 cd->insn_table.entry_size = sizeof (CGEN_IBASE);
935 cd->insn_table.num_init_entries = MAX_INSNS;
938 /* Subroutine of lm32_cgen_cpu_open to rebuild the tables. */
941 lm32_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
944 CGEN_BITSET *isas = cd->isas;
945 unsigned int machs = cd->machs;
947 cd->int_insn_p = CGEN_INT_INSN_P;
949 /* Data derived from the isa spec. */
950 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
951 cd->default_insn_bitsize = UNSET;
952 cd->base_insn_bitsize = UNSET;
953 cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */
954 cd->max_insn_bitsize = 0;
955 for (i = 0; i < MAX_ISAS; ++i)
956 if (cgen_bitset_contains (isas, i))
958 const CGEN_ISA *isa = & lm32_cgen_isa_table[i];
960 /* Default insn sizes of all selected isas must be
961 equal or we set the result to 0, meaning "unknown". */
962 if (cd->default_insn_bitsize == UNSET)
963 cd->default_insn_bitsize = isa->default_insn_bitsize;
964 else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
967 cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
969 /* Base insn sizes of all selected isas must be equal
970 or we set the result to 0, meaning "unknown". */
971 if (cd->base_insn_bitsize == UNSET)
972 cd->base_insn_bitsize = isa->base_insn_bitsize;
973 else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
976 cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
978 /* Set min,max insn sizes. */
979 if (isa->min_insn_bitsize < cd->min_insn_bitsize)
980 cd->min_insn_bitsize = isa->min_insn_bitsize;
981 if (isa->max_insn_bitsize > cd->max_insn_bitsize)
982 cd->max_insn_bitsize = isa->max_insn_bitsize;
985 /* Data derived from the mach spec. */
986 for (i = 0; i < MAX_MACHS; ++i)
987 if (((1 << i) & machs) != 0)
989 const CGEN_MACH *mach = & lm32_cgen_mach_table[i];
991 if (mach->insn_chunk_bitsize != 0)
993 if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
995 fprintf (stderr, "lm32_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
996 cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
1000 cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
1004 /* Determine which hw elements are used by MACH. */
1005 build_hw_table (cd);
1007 /* Build the ifield table. */
1008 build_ifield_table (cd);
1010 /* Determine which operands are used by MACH/ISA. */
1011 build_operand_table (cd);
1013 /* Build the instruction table. */
1014 build_insn_table (cd);
1017 /* Initialize a cpu table and return a descriptor.
1018 It's much like opening a file, and must be the first function called.
1019 The arguments are a set of (type/value) pairs, terminated with
1022 Currently supported values:
1023 CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
1024 CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
1025 CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
1026 CGEN_CPU_OPEN_ENDIAN: specify endian choice
1027 CGEN_CPU_OPEN_END: terminates arguments
1029 ??? Simultaneous multiple isas might not make sense, but it's not (yet)
1033 lm32_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
1035 CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
1037 CGEN_BITSET *isas = 0; /* 0 = "unspecified" */
1038 unsigned int machs = 0; /* 0 = "unspecified" */
1039 enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
1048 memset (cd, 0, sizeof (*cd));
1050 va_start (ap, arg_type);
1051 while (arg_type != CGEN_CPU_OPEN_END)
1055 case CGEN_CPU_OPEN_ISAS :
1056 isas = va_arg (ap, CGEN_BITSET *);
1058 case CGEN_CPU_OPEN_MACHS :
1059 machs = va_arg (ap, unsigned int);
1061 case CGEN_CPU_OPEN_BFDMACH :
1063 const char *name = va_arg (ap, const char *);
1064 const CGEN_MACH *mach =
1065 lookup_mach_via_bfd_name (lm32_cgen_mach_table, name);
1068 machs |= 1 << mach->num;
1071 case CGEN_CPU_OPEN_ENDIAN :
1072 endian = va_arg (ap, enum cgen_endian);
1075 fprintf (stderr, "lm32_cgen_cpu_open: unsupported argument `%d'\n",
1077 abort (); /* ??? return NULL? */
1079 arg_type = va_arg (ap, enum cgen_cpu_open_arg);
1083 /* Mach unspecified means "all". */
1085 machs = (1 << MAX_MACHS) - 1;
1086 /* Base mach is always selected. */
1088 if (endian == CGEN_ENDIAN_UNKNOWN)
1090 /* ??? If target has only one, could have a default. */
1091 fprintf (stderr, "lm32_cgen_cpu_open: no endianness specified\n");
1095 cd->isas = cgen_bitset_copy (isas);
1097 cd->endian = endian;
1098 /* FIXME: for the sparc case we can determine insn-endianness statically.
1099 The worry here is where both data and insn endian can be independently
1100 chosen, in which case this function will need another argument.
1101 Actually, will want to allow for more arguments in the future anyway. */
1102 cd->insn_endian = endian;
1104 /* Table (re)builder. */
1105 cd->rebuild_tables = lm32_cgen_rebuild_tables;
1106 lm32_cgen_rebuild_tables (cd);
1108 /* Default to not allowing signed overflow. */
1109 cd->signed_overflow_ok_p = 0;
1111 return (CGEN_CPU_DESC) cd;
1114 /* Cover fn to lm32_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
1115 MACH_NAME is the bfd name of the mach. */
1118 lm32_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
1120 return lm32_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
1121 CGEN_CPU_OPEN_ENDIAN, endian,
1125 /* Close a cpu table.
1126 ??? This can live in a machine independent file, but there's currently
1127 no place to put this file (there's no libcgen). libopcodes is the wrong
1128 place as some simulator ports use this but they don't use libopcodes. */
1131 lm32_cgen_cpu_close (CGEN_CPU_DESC cd)
1134 const CGEN_INSN *insns;
1136 if (cd->macro_insn_table.init_entries)
1138 insns = cd->macro_insn_table.init_entries;
1139 for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
1140 if (CGEN_INSN_RX ((insns)))
1141 regfree (CGEN_INSN_RX (insns));
1144 if (cd->insn_table.init_entries)
1146 insns = cd->insn_table.init_entries;
1147 for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
1148 if (CGEN_INSN_RX (insns))
1149 regfree (CGEN_INSN_RX (insns));
1152 if (cd->macro_insn_table.init_entries)
1153 free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
1155 if (cd->insn_table.init_entries)
1156 free ((CGEN_INSN *) cd->insn_table.init_entries);
1158 if (cd->hw_table.entries)
1159 free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
1161 if (cd->operand_table.entries)
1162 free ((CGEN_HW_ENTRY *) cd->operand_table.entries);