1 /* Declarations for Intel 80386 opcode table
2 Copyright (C) 2007-2014 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 #include "opcode/i386.h"
30 /* Position of cpu flags bitfiled. */
34 /* i186 or better required */
36 /* i286 or better required */
38 /* i386 or better required */
40 /* i486 or better required */
42 /* i585 or better required */
44 /* i686 or better required */
46 /* CLFLUSH Instruction support required */
48 /* NOP Instruction support required */
50 /* SYSCALL Instructions support required */
52 /* Floating point support required */
54 /* i287 support required */
56 /* i387 support required */
58 /* i686 and floating point support required */
60 /* SSE3 and floating point support required */
62 /* MMX support required */
64 /* SSE support required */
66 /* SSE2 support required */
68 /* 3dnow! support required */
70 /* 3dnow! Extensions support required */
72 /* SSE3 support required */
74 /* VIA PadLock required */
76 /* AMD Secure Virtual Machine Ext-s required */
78 /* VMX Instructions required */
80 /* SMX Instructions required */
82 /* SSSE3 support required */
84 /* SSE4a support required */
86 /* ABM New Instructions required */
88 /* SSE4.1 support required */
90 /* SSE4.2 support required */
92 /* AVX support required */
94 /* AVX2 support required */
96 /* Intel AVX-512 Foundation Instructions support required */
98 /* Intel AVX-512 Conflict Detection Instructions support required */
100 /* Intel AVX-512 Exponential and Reciprocal Instructions support
103 /* Intel AVX-512 Prefetch Instructions support required */
105 /* Intel AVX-512 VL Instructions support required. */
107 /* Intel AVX-512 DQ Instructions support required. */
109 /* Intel AVX-512 BW Instructions support required. */
111 /* Intel L1OM support required */
113 /* Intel K1OM support required */
115 /* Xsave/xrstor New Instructions support required */
117 /* Xsaveopt New Instructions support required */
119 /* AES support required */
121 /* PCLMUL support required */
123 /* FMA support required */
125 /* FMA4 support required */
127 /* XOP support required */
129 /* LWP support required */
131 /* BMI support required */
133 /* TBM support required */
135 /* MOVBE Instruction support required */
137 /* CMPXCHG16B instruction support required. */
139 /* EPT Instructions required */
141 /* RDTSCP Instruction support required */
143 /* FSGSBASE Instructions required */
145 /* RDRND Instructions required */
147 /* F16C Instructions required */
149 /* Intel BMI2 support required */
151 /* LZCNT support required */
153 /* HLE support required */
155 /* RTM support required */
157 /* INVPCID Instructions required */
159 /* VMFUNC Instruction required */
161 /* Intel MPX Instructions required */
163 /* 64bit support available, used by -march= in assembler. */
165 /* RDRSEED instruction required. */
167 /* Multi-presisionn add-carry instructions are required. */
169 /* Supports prefetchw and prefetch instructions. */
171 /* SMAP instructions required. */
173 /* SHA instructions required. */
175 /* VREX support required */
177 /* CLFLUSHOPT instruction required */
179 /* XSAVES/XRSTORS instruction required */
181 /* XSAVEC instruction required */
183 /* PREFETCHWT1 instruction required */
185 /* SE1 instruction required */
187 /* CLWB instruction required */
189 /* 64bit support required */
191 /* Not supported in the 64bit mode */
193 /* The last bitfield in i386_cpu_flags. */
197 #define CpuNumOfUints \
198 (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
199 #define CpuNumOfBits \
200 (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
202 /* If you get a compiler error for zero width of the unused field,
204 #define CpuUnused (CpuMax + 1)
206 /* We can check if an instruction is available with array instead
208 typedef union i386_cpu_flags
212 unsigned int cpui186:1;
213 unsigned int cpui286:1;
214 unsigned int cpui386:1;
215 unsigned int cpui486:1;
216 unsigned int cpui586:1;
217 unsigned int cpui686:1;
218 unsigned int cpuclflush:1;
219 unsigned int cpunop:1;
220 unsigned int cpusyscall:1;
221 unsigned int cpu8087:1;
222 unsigned int cpu287:1;
223 unsigned int cpu387:1;
224 unsigned int cpu687:1;
225 unsigned int cpufisttp:1;
226 unsigned int cpummx:1;
227 unsigned int cpusse:1;
228 unsigned int cpusse2:1;
229 unsigned int cpua3dnow:1;
230 unsigned int cpua3dnowa:1;
231 unsigned int cpusse3:1;
232 unsigned int cpupadlock:1;
233 unsigned int cpusvme:1;
234 unsigned int cpuvmx:1;
235 unsigned int cpusmx:1;
236 unsigned int cpussse3:1;
237 unsigned int cpusse4a:1;
238 unsigned int cpuabm:1;
239 unsigned int cpusse4_1:1;
240 unsigned int cpusse4_2:1;
241 unsigned int cpuavx:1;
242 unsigned int cpuavx2:1;
243 unsigned int cpuavx512f:1;
244 unsigned int cpuavx512cd:1;
245 unsigned int cpuavx512er:1;
246 unsigned int cpuavx512pf:1;
247 unsigned int cpuavx512vl:1;
248 unsigned int cpuavx512dq:1;
249 unsigned int cpuavx512bw:1;
250 unsigned int cpul1om:1;
251 unsigned int cpuk1om:1;
252 unsigned int cpuxsave:1;
253 unsigned int cpuxsaveopt:1;
254 unsigned int cpuaes:1;
255 unsigned int cpupclmul:1;
256 unsigned int cpufma:1;
257 unsigned int cpufma4:1;
258 unsigned int cpuxop:1;
259 unsigned int cpulwp:1;
260 unsigned int cpubmi:1;
261 unsigned int cputbm:1;
262 unsigned int cpumovbe:1;
263 unsigned int cpucx16:1;
264 unsigned int cpuept:1;
265 unsigned int cpurdtscp:1;
266 unsigned int cpufsgsbase:1;
267 unsigned int cpurdrnd:1;
268 unsigned int cpuf16c:1;
269 unsigned int cpubmi2:1;
270 unsigned int cpulzcnt:1;
271 unsigned int cpuhle:1;
272 unsigned int cpurtm:1;
273 unsigned int cpuinvpcid:1;
274 unsigned int cpuvmfunc:1;
275 unsigned int cpumpx:1;
276 unsigned int cpulm:1;
277 unsigned int cpurdseed:1;
278 unsigned int cpuadx:1;
279 unsigned int cpuprfchw:1;
280 unsigned int cpusmap:1;
281 unsigned int cpusha:1;
282 unsigned int cpuvrex:1;
283 unsigned int cpuclflushopt:1;
284 unsigned int cpuxsaves:1;
285 unsigned int cpuxsavec:1;
286 unsigned int cpuprefetchwt1:1;
287 unsigned int cpuse1:1;
288 unsigned int cpuclwb:1;
289 unsigned int cpu64:1;
290 unsigned int cpuno64:1;
292 unsigned int unused:(CpuNumOfBits - CpuUnused);
295 unsigned int array[CpuNumOfUints];
298 /* Position of opcode_modifier bits. */
302 /* has direction bit. */
304 /* set if operands can be words or dwords encoded the canonical way */
306 /* Skip the current insn and use the next insn in i386-opc.tbl to swap
307 operand in encoding. */
309 /* insn has a modrm byte. */
311 /* register is in low 3 bits of opcode */
313 /* special case for jump insns. */
319 /* special case for intersegment leaps/calls */
321 /* FP insn memory format bit, sized by 0x4 */
323 /* src/dest swap for floats. */
325 /* has float insn direction bit. */
327 /* needs size prefix if in 32-bit mode */
329 /* needs size prefix if in 16-bit mode */
331 /* needs size prefix if in 64-bit mode */
333 /* check register size. */
335 /* instruction ignores operand size prefix and in Intel mode ignores
336 mnemonic size suffix check. */
338 /* default insn size depends on mode */
340 /* b suffix on instruction illegal */
342 /* w suffix on instruction illegal */
344 /* l suffix on instruction illegal */
346 /* s suffix on instruction illegal */
348 /* q suffix on instruction illegal */
350 /* long double suffix on instruction illegal */
352 /* instruction needs FWAIT */
354 /* quick test for string instructions */
356 /* quick test if branch instruction is MPX supported */
358 /* quick test for lockable instructions */
360 /* fake an extra reg operand for clr, imul and special register
361 processing for some instructions. */
363 /* The first operand must be xmm0 */
365 /* An implicit xmm0 as the first operand */
367 /* The HLE prefix is OK:
368 1. With a LOCK prefix.
369 2. With or without a LOCK prefix.
370 3. With a RELEASE (0xf3) prefix.
372 #define HLEPrefixNone 0
373 #define HLEPrefixLock 1
374 #define HLEPrefixAny 2
375 #define HLEPrefixRelease 3
377 /* An instruction on which a "rep" prefix is acceptable. */
379 /* Convert to DWORD */
381 /* Convert to QWORD */
383 /* Address prefix changes operand 0 */
385 /* opcode is a prefix */
387 /* instruction has extension in 8 bit imm */
389 /* instruction don't need Rex64 prefix. */
391 /* instruction require Rex64 prefix. */
393 /* deprecated fp insn, gets a warning */
395 /* insn has VEX prefix:
396 1: 128bit VEX prefix.
397 2: 256bit VEX prefix.
398 3: Scalar VEX prefix.
404 /* How to encode VEX.vvvv:
405 0: VEX.vvvv must be 1111b.
406 1: VEX.NDS. Register-only source is encoded in VEX.vvvv where
407 the content of source registers will be preserved.
408 VEX.DDS. The second register operand is encoded in VEX.vvvv
409 where the content of first source register will be overwritten
411 VEX.NDD2. The second destination register operand is encoded in
412 VEX.vvvv for instructions with 2 destination register operands.
413 For assembler, there are no difference between VEX.NDS, VEX.DDS
415 2. VEX.NDD. Register destination is encoded in VEX.vvvv for
416 instructions with 1 destination register operand.
417 3. VEX.LWP. Register destination is encoded in VEX.vvvv and one
418 of the operands can access a memory location.
424 /* How the VEX.W bit is used:
425 0: Set by the REX.W bit.
426 1: VEX.W0. Should always be 0.
427 2: VEX.W1. Should always be 1.
432 /* VEX opcode prefix:
433 0: VEX 0x0F opcode prefix.
434 1: VEX 0x0F38 opcode prefix.
435 2: VEX 0x0F3A opcode prefix
436 3: XOP 0x08 opcode prefix.
437 4: XOP 0x09 opcode prefix
438 5: XOP 0x0A opcode prefix.
447 /* number of VEX source operands:
448 0: <= 2 source operands.
449 1: 2 XOP source operands.
450 2: 3 source operands.
452 #define XOP2SOURCES 1
453 #define VEX3SOURCES 2
455 /* instruction has VEX 8 bit imm */
457 /* Instruction with vector SIB byte:
458 1: 128bit vector register.
459 2: 256bit vector register.
460 3: 512bit vector register.
466 /* SSE to AVX support required */
468 /* No AVX equivalent */
471 /* insn has EVEX prefix:
472 1: 512bit EVEX prefix.
473 2: 128bit EVEX prefix.
474 3: 256bit EVEX prefix.
475 4: Length-ignored (LIG) EVEX prefix.
483 /* AVX512 masking support:
486 3: Both zeroing and merging masking.
488 #define ZEROING_MASKING 1
489 #define MERGING_MASKING 2
490 #define BOTH_MASKING 3
493 /* Input element size of vector insn:
504 #define NO_BROADCAST 0
505 #define BROADCAST_1TO16 1
506 #define BROADCAST_1TO8 2
507 #define BROADCAST_1TO4 3
508 #define BROADCAST_1TO2 4
511 /* Static rounding control is supported. */
514 /* Supress All Exceptions is supported. */
517 /* Copressed Disp8*N attribute. */
520 /* Default mask isn't allowed. */
523 /* Compatible with old (<= 2.8.1) versions of gcc */
531 /* The last bitfield in i386_opcode_modifier. */
535 typedef struct i386_opcode_modifier
540 unsigned int modrm:1;
541 unsigned int shortform:1;
543 unsigned int jumpdword:1;
544 unsigned int jumpbyte:1;
545 unsigned int jumpintersegment:1;
546 unsigned int floatmf:1;
547 unsigned int floatr:1;
548 unsigned int floatd:1;
549 unsigned int size16:1;
550 unsigned int size32:1;
551 unsigned int size64:1;
552 unsigned int checkregsize:1;
553 unsigned int ignoresize:1;
554 unsigned int defaultsize:1;
555 unsigned int no_bsuf:1;
556 unsigned int no_wsuf:1;
557 unsigned int no_lsuf:1;
558 unsigned int no_ssuf:1;
559 unsigned int no_qsuf:1;
560 unsigned int no_ldsuf:1;
561 unsigned int fwait:1;
562 unsigned int isstring:1;
563 unsigned int bndprefixok:1;
564 unsigned int islockable:1;
565 unsigned int regkludge:1;
566 unsigned int firstxmm0:1;
567 unsigned int implicit1stxmm0:1;
568 unsigned int hleprefixok:2;
569 unsigned int repprefixok:1;
570 unsigned int todword:1;
571 unsigned int toqword:1;
572 unsigned int addrprefixop0:1;
573 unsigned int isprefix:1;
574 unsigned int immext:1;
575 unsigned int norex64:1;
576 unsigned int rex64:1;
579 unsigned int vexvvvv:2;
581 unsigned int vexopcode:3;
582 unsigned int vexsources:2;
583 unsigned int veximmext:1;
584 unsigned int vecsib:2;
585 unsigned int sse2avx:1;
586 unsigned int noavx:1;
588 unsigned int masking:2;
589 unsigned int vecesize:1;
590 unsigned int broadcast:3;
591 unsigned int staticrounding:1;
593 unsigned int disp8memshift:3;
594 unsigned int nodefmask:1;
595 unsigned int oldgcc:1;
596 unsigned int attmnemonic:1;
597 unsigned int attsyntax:1;
598 unsigned int intelsyntax:1;
599 } i386_opcode_modifier;
601 /* Position of operand_type bits. */
613 /* Floating pointer stack register */
621 /* AVX512 registers */
623 /* Vector Mask registers */
625 /* Control register */
631 /* 2 bit segment register */
633 /* 3 bit segment register */
635 /* 1 bit immediate */
637 /* 8 bit immediate */
639 /* 8 bit immediate sign extended */
641 /* 16 bit immediate */
643 /* 32 bit immediate */
645 /* 32 bit immediate sign extended */
647 /* 64 bit immediate */
649 /* 8bit/16bit/32bit displacements are used in different ways,
650 depending on the instruction. For jumps, they specify the
651 size of the PC relative displacement, for instructions with
652 memory operand, they specify the size of the offset relative
653 to the base register, and for instructions with memory offset
654 such as `mov 1234,%al' they specify the size of the offset
655 relative to the segment base. */
656 /* 8 bit displacement */
658 /* 16 bit displacement */
660 /* 32 bit displacement */
662 /* 32 bit signed displacement */
664 /* 64 bit displacement */
666 /* Accumulator %al/%ax/%eax/%rax */
668 /* Floating pointer top stack register %st(0) */
670 /* Register which can be used for base or index in memory operand. */
672 /* Register to hold in/out port addr = dx */
674 /* Register to hold shift count = cl */
676 /* Absolute address for jump. */
678 /* String insn operand with fixed es segment */
680 /* RegMem is for instructions with a modrm byte where the register
681 destination operand should be encoded in the mod and regmem fields.
682 Normally, it will be encoded in the reg field. We add a RegMem
683 flag to the destination register operand to indicate that it should
684 be encoded in the regmem field. */
690 /* WORD memory. 2 byte */
692 /* DWORD memory. 4 byte */
694 /* FWORD memory. 6 byte */
696 /* QWORD memory. 8 byte */
698 /* TBYTE memory. 10 byte */
700 /* XMMWORD memory. */
702 /* YMMWORD memory. */
704 /* ZMMWORD memory. */
706 /* Unspecified memory size. */
708 /* Any memory size. */
711 /* Vector 4 bit immediate. */
714 /* Bound register. */
717 /* Vector 8bit displacement */
720 /* The last bitfield in i386_operand_type. */
724 #define OTNumOfUints \
725 (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
726 #define OTNumOfBits \
727 (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
729 /* If you get a compiler error for zero width of the unused field,
731 #define OTUnused (OTMax + 1)
733 typedef union i386_operand_type
738 unsigned int reg16:1;
739 unsigned int reg32:1;
740 unsigned int reg64:1;
741 unsigned int floatreg:1;
742 unsigned int regmmx:1;
743 unsigned int regxmm:1;
744 unsigned int regymm:1;
745 unsigned int regzmm:1;
746 unsigned int regmask:1;
747 unsigned int control:1;
748 unsigned int debug:1;
750 unsigned int sreg2:1;
751 unsigned int sreg3:1;
754 unsigned int imm8s:1;
755 unsigned int imm16:1;
756 unsigned int imm32:1;
757 unsigned int imm32s:1;
758 unsigned int imm64:1;
759 unsigned int disp8:1;
760 unsigned int disp16:1;
761 unsigned int disp32:1;
762 unsigned int disp32s:1;
763 unsigned int disp64:1;
765 unsigned int floatacc:1;
766 unsigned int baseindex:1;
767 unsigned int inoutportreg:1;
768 unsigned int shiftcount:1;
769 unsigned int jumpabsolute:1;
770 unsigned int esseg:1;
771 unsigned int regmem:1;
775 unsigned int dword:1;
776 unsigned int fword:1;
777 unsigned int qword:1;
778 unsigned int tbyte:1;
779 unsigned int xmmword:1;
780 unsigned int ymmword:1;
781 unsigned int zmmword:1;
782 unsigned int unspecified:1;
783 unsigned int anysize:1;
784 unsigned int vec_imm4:1;
785 unsigned int regbnd:1;
786 unsigned int vec_disp8:1;
788 unsigned int unused:(OTNumOfBits - OTUnused);
791 unsigned int array[OTNumOfUints];
794 typedef struct insn_template
796 /* instruction name sans width suffix ("mov" for movl insns) */
799 /* how many operands */
800 unsigned int operands;
802 /* base_opcode is the fundamental opcode byte without optional
804 unsigned int base_opcode;
805 #define Opcode_D 0x2 /* Direction bit:
806 set if Reg --> Regmem;
807 unset if Regmem --> Reg. */
808 #define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */
809 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
811 /* extension_opcode is the 3 bit extension for group <n> insns.
812 This field is also used to store the 8-bit opcode suffix for the
813 AMD 3DNow! instructions.
814 If this template has no extension opcode (the usual case) use None
816 unsigned int extension_opcode;
817 #define None 0xffff /* If no extension_opcode is possible. */
820 unsigned char opcode_length;
822 /* cpu feature flags */
823 i386_cpu_flags cpu_flags;
825 /* the bits in opcode_modifier are used to generate the final opcode from
826 the base_opcode. These bits also are used to detect alternate forms of
827 the same instruction */
828 i386_opcode_modifier opcode_modifier;
830 /* operand_types[i] describes the type of operand i. This is made
831 by OR'ing together all of the possible type masks. (e.g.
832 'operand_types[i] = Reg|Imm' specifies that operand i can be
833 either a register or an immediate operand. */
834 i386_operand_type operand_types[MAX_OPERANDS];
838 extern const insn_template i386_optab[];
840 /* these are for register name --> number & type hash lookup */
844 i386_operand_type reg_type;
845 unsigned char reg_flags;
846 #define RegRex 0x1 /* Extended register. */
847 #define RegRex64 0x2 /* Extended 8 bit register. */
848 #define RegVRex 0x4 /* Extended vector register. */
849 unsigned char reg_num;
850 #define RegRip ((unsigned char ) ~0)
851 #define RegEip (RegRip - 1)
852 /* EIZ and RIZ are fake index registers. */
853 #define RegEiz (RegEip - 1)
854 #define RegRiz (RegEiz - 1)
855 /* FLAT is a fake segment register (Intel mode). */
856 #define RegFlat ((unsigned char) ~0)
857 signed char dw2_regnum[2];
858 #define Dw2Inval (-1)
862 /* Entries in i386_regtab. */
865 #define REGNAM_EAX 41
867 extern const reg_entry i386_regtab[];
868 extern const unsigned int i386_regtab_size;
873 unsigned int seg_prefix;
877 extern const seg_entry cs;
878 extern const seg_entry ds;
879 extern const seg_entry ss;
880 extern const seg_entry es;
881 extern const seg_entry fs;
882 extern const seg_entry gs;