1 /* Declarations for Intel 80386 opcode table
2 Copyright (C) 2007-2018 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 #include "opcode/i386.h"
30 /* Position of cpu flags bitfiled. */
34 /* i186 or better required */
36 /* i286 or better required */
38 /* i386 or better required */
40 /* i486 or better required */
42 /* i585 or better required */
44 /* i686 or better required */
46 /* CLFLUSH Instruction support required */
48 /* NOP Instruction support required */
50 /* SYSCALL Instructions support required */
52 /* Floating point support required */
54 /* i287 support required */
56 /* i387 support required */
58 /* i686 and floating point support required */
60 /* SSE3 and floating point support required */
62 /* MMX support required */
64 /* SSE support required */
66 /* SSE2 support required */
68 /* 3dnow! support required */
70 /* 3dnow! Extensions support required */
72 /* SSE3 support required */
74 /* VIA PadLock required */
76 /* AMD Secure Virtual Machine Ext-s required */
78 /* VMX Instructions required */
80 /* SMX Instructions required */
82 /* SSSE3 support required */
84 /* SSE4a support required */
86 /* ABM New Instructions required */
88 /* SSE4.1 support required */
90 /* SSE4.2 support required */
92 /* AVX support required */
94 /* AVX2 support required */
96 /* Intel AVX-512 Foundation Instructions support required */
98 /* Intel AVX-512 Conflict Detection Instructions support required */
100 /* Intel AVX-512 Exponential and Reciprocal Instructions support
103 /* Intel AVX-512 Prefetch Instructions support required */
105 /* Intel AVX-512 VL Instructions support required. */
107 /* Intel AVX-512 DQ Instructions support required. */
109 /* Intel AVX-512 BW Instructions support required. */
111 /* Intel L1OM support required */
113 /* Intel K1OM support required */
115 /* Intel IAMCU support required */
117 /* Xsave/xrstor New Instructions support required */
119 /* Xsaveopt New Instructions support required */
121 /* AES support required */
123 /* PCLMUL support required */
125 /* FMA support required */
127 /* FMA4 support required */
129 /* XOP support required */
131 /* LWP support required */
133 /* BMI support required */
135 /* TBM support required */
137 /* MOVBE Instruction support required */
139 /* CMPXCHG16B instruction support required. */
141 /* EPT Instructions required */
143 /* RDTSCP Instruction support required */
145 /* FSGSBASE Instructions required */
147 /* RDRND Instructions required */
149 /* F16C Instructions required */
151 /* Intel BMI2 support required */
153 /* LZCNT support required */
155 /* HLE support required */
157 /* RTM support required */
159 /* INVPCID Instructions required */
161 /* VMFUNC Instruction required */
163 /* Intel MPX Instructions required */
165 /* 64bit support available, used by -march= in assembler. */
167 /* RDRSEED instruction required. */
169 /* Multi-presisionn add-carry instructions are required. */
171 /* Supports prefetchw and prefetch instructions. */
173 /* SMAP instructions required. */
175 /* SHA instructions required. */
177 /* VREX support required */
179 /* CLFLUSHOPT instruction required */
181 /* XSAVES/XRSTORS instruction required */
183 /* XSAVEC instruction required */
185 /* PREFETCHWT1 instruction required */
187 /* SE1 instruction required */
189 /* CLWB instruction required */
191 /* Intel AVX-512 IFMA Instructions support required. */
193 /* Intel AVX-512 VBMI Instructions support required. */
195 /* Intel AVX-512 4FMAPS Instructions support required. */
197 /* Intel AVX-512 4VNNIW Instructions support required. */
199 /* Intel AVX-512 VPOPCNTDQ Instructions support required. */
201 /* Intel AVX-512 VBMI2 Instructions support required. */
203 /* Intel AVX-512 VNNI Instructions support required. */
205 /* Intel AVX-512 BITALG Instructions support required. */
207 /* mwaitx instruction required */
209 /* Clzero instruction required */
211 /* OSPKE instruction required */
213 /* RDPID instruction required */
215 /* PTWRITE instruction required */
217 /* CET instructions support required */
220 /* GFNI instructions required */
222 /* VAES instructions required */
224 /* VPCLMULQDQ instructions required */
226 /* WBNOINVD instructions required */
228 /* PCONFIG instructions required */
230 /* WAITPKG instructions required */
232 /* CLDEMOTE instruction required */
234 /* MOVDIRI instruction support required */
236 /* MOVDIRR64B instruction required */
238 /* 64bit support required */
240 /* Not supported in the 64bit mode */
242 /* The last bitfield in i386_cpu_flags. */
246 #define CpuNumOfUints \
247 (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
248 #define CpuNumOfBits \
249 (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
251 /* If you get a compiler error for zero width of the unused field,
253 #define CpuUnused (CpuMax + 1)
255 /* We can check if an instruction is available with array instead
257 typedef union i386_cpu_flags
261 unsigned int cpui186:1;
262 unsigned int cpui286:1;
263 unsigned int cpui386:1;
264 unsigned int cpui486:1;
265 unsigned int cpui586:1;
266 unsigned int cpui686:1;
267 unsigned int cpuclflush:1;
268 unsigned int cpunop:1;
269 unsigned int cpusyscall:1;
270 unsigned int cpu8087:1;
271 unsigned int cpu287:1;
272 unsigned int cpu387:1;
273 unsigned int cpu687:1;
274 unsigned int cpufisttp:1;
275 unsigned int cpummx:1;
276 unsigned int cpusse:1;
277 unsigned int cpusse2:1;
278 unsigned int cpua3dnow:1;
279 unsigned int cpua3dnowa:1;
280 unsigned int cpusse3:1;
281 unsigned int cpupadlock:1;
282 unsigned int cpusvme:1;
283 unsigned int cpuvmx:1;
284 unsigned int cpusmx:1;
285 unsigned int cpussse3:1;
286 unsigned int cpusse4a:1;
287 unsigned int cpuabm:1;
288 unsigned int cpusse4_1:1;
289 unsigned int cpusse4_2:1;
290 unsigned int cpuavx:1;
291 unsigned int cpuavx2:1;
292 unsigned int cpuavx512f:1;
293 unsigned int cpuavx512cd:1;
294 unsigned int cpuavx512er:1;
295 unsigned int cpuavx512pf:1;
296 unsigned int cpuavx512vl:1;
297 unsigned int cpuavx512dq:1;
298 unsigned int cpuavx512bw:1;
299 unsigned int cpul1om:1;
300 unsigned int cpuk1om:1;
301 unsigned int cpuiamcu:1;
302 unsigned int cpuxsave:1;
303 unsigned int cpuxsaveopt:1;
304 unsigned int cpuaes:1;
305 unsigned int cpupclmul:1;
306 unsigned int cpufma:1;
307 unsigned int cpufma4:1;
308 unsigned int cpuxop:1;
309 unsigned int cpulwp:1;
310 unsigned int cpubmi:1;
311 unsigned int cputbm:1;
312 unsigned int cpumovbe:1;
313 unsigned int cpucx16:1;
314 unsigned int cpuept:1;
315 unsigned int cpurdtscp:1;
316 unsigned int cpufsgsbase:1;
317 unsigned int cpurdrnd:1;
318 unsigned int cpuf16c:1;
319 unsigned int cpubmi2:1;
320 unsigned int cpulzcnt:1;
321 unsigned int cpuhle:1;
322 unsigned int cpurtm:1;
323 unsigned int cpuinvpcid:1;
324 unsigned int cpuvmfunc:1;
325 unsigned int cpumpx:1;
326 unsigned int cpulm:1;
327 unsigned int cpurdseed:1;
328 unsigned int cpuadx:1;
329 unsigned int cpuprfchw:1;
330 unsigned int cpusmap:1;
331 unsigned int cpusha:1;
332 unsigned int cpuvrex:1;
333 unsigned int cpuclflushopt:1;
334 unsigned int cpuxsaves:1;
335 unsigned int cpuxsavec:1;
336 unsigned int cpuprefetchwt1:1;
337 unsigned int cpuse1:1;
338 unsigned int cpuclwb:1;
339 unsigned int cpuavx512ifma:1;
340 unsigned int cpuavx512vbmi:1;
341 unsigned int cpuavx512_4fmaps:1;
342 unsigned int cpuavx512_4vnniw:1;
343 unsigned int cpuavx512_vpopcntdq:1;
344 unsigned int cpuavx512_vbmi2:1;
345 unsigned int cpuavx512_vnni:1;
346 unsigned int cpuavx512_bitalg:1;
347 unsigned int cpumwaitx:1;
348 unsigned int cpuclzero:1;
349 unsigned int cpuospke:1;
350 unsigned int cpurdpid:1;
351 unsigned int cpuptwrite:1;
352 unsigned int cpuibt:1;
353 unsigned int cpushstk:1;
354 unsigned int cpugfni:1;
355 unsigned int cpuvaes:1;
356 unsigned int cpuvpclmulqdq:1;
357 unsigned int cpuwbnoinvd:1;
358 unsigned int cpupconfig:1;
359 unsigned int cpuwaitpkg:1;
360 unsigned int cpucldemote:1;
361 unsigned int cpumovdiri:1;
362 unsigned int cpumovdir64b:1;
363 unsigned int cpu64:1;
364 unsigned int cpuno64:1;
366 unsigned int unused:(CpuNumOfBits - CpuUnused);
369 unsigned int array[CpuNumOfUints];
372 /* Position of opcode_modifier bits. */
376 /* has direction bit. */
378 /* set if operands can be words or dwords encoded the canonical way */
380 /* load form instruction. Must be placed before store form. */
382 /* insn has a modrm byte. */
384 /* register is in low 3 bits of opcode */
386 /* special case for jump insns. */
392 /* special case for intersegment leaps/calls */
394 /* FP insn memory format bit, sized by 0x4 */
396 /* src/dest swap for floats. */
398 /* needs size prefix if in 32-bit mode */
400 /* needs size prefix if in 16-bit mode */
402 /* needs size prefix if in 64-bit mode */
404 /* check register size. */
406 /* instruction ignores operand size prefix and in Intel mode ignores
407 mnemonic size suffix check. */
409 /* default insn size depends on mode */
411 /* b suffix on instruction illegal */
413 /* w suffix on instruction illegal */
415 /* l suffix on instruction illegal */
417 /* s suffix on instruction illegal */
419 /* q suffix on instruction illegal */
421 /* long double suffix on instruction illegal */
423 /* instruction needs FWAIT */
425 /* quick test for string instructions */
427 /* quick test if branch instruction is MPX supported */
429 /* quick test if NOTRACK prefix is supported */
431 /* quick test for lockable instructions */
433 /* fake an extra reg operand for clr, imul and special register
434 processing for some instructions. */
436 /* An implicit xmm0 as the first operand */
438 /* The HLE prefix is OK:
439 1. With a LOCK prefix.
440 2. With or without a LOCK prefix.
441 3. With a RELEASE (0xf3) prefix.
443 #define HLEPrefixNone 0
444 #define HLEPrefixLock 1
445 #define HLEPrefixAny 2
446 #define HLEPrefixRelease 3
448 /* An instruction on which a "rep" prefix is acceptable. */
450 /* Convert to DWORD */
452 /* Convert to QWORD */
454 /* Address prefix changes register operand */
456 /* opcode is a prefix */
458 /* instruction has extension in 8 bit imm */
460 /* instruction don't need Rex64 prefix. */
462 /* instruction require Rex64 prefix. */
464 /* deprecated fp insn, gets a warning */
466 /* insn has VEX prefix:
467 1: 128bit VEX prefix (or operand dependent).
468 2: 256bit VEX prefix.
469 3: Scalar VEX prefix.
475 /* How to encode VEX.vvvv:
476 0: VEX.vvvv must be 1111b.
477 1: VEX.NDS. Register-only source is encoded in VEX.vvvv where
478 the content of source registers will be preserved.
479 VEX.DDS. The second register operand is encoded in VEX.vvvv
480 where the content of first source register will be overwritten
482 VEX.NDD2. The second destination register operand is encoded in
483 VEX.vvvv for instructions with 2 destination register operands.
484 For assembler, there are no difference between VEX.NDS, VEX.DDS
486 2. VEX.NDD. Register destination is encoded in VEX.vvvv for
487 instructions with 1 destination register operand.
488 3. VEX.LWP. Register destination is encoded in VEX.vvvv and one
489 of the operands can access a memory location.
495 /* How the VEX.W bit is used:
496 0: Set by the REX.W bit.
497 1: VEX.W0. Should always be 0.
498 2: VEX.W1. Should always be 1.
503 /* VEX opcode prefix:
504 0: VEX 0x0F opcode prefix.
505 1: VEX 0x0F38 opcode prefix.
506 2: VEX 0x0F3A opcode prefix
507 3: XOP 0x08 opcode prefix.
508 4: XOP 0x09 opcode prefix
509 5: XOP 0x0A opcode prefix.
518 /* number of VEX source operands:
519 0: <= 2 source operands.
520 1: 2 XOP source operands.
521 2: 3 source operands.
523 #define XOP2SOURCES 1
524 #define VEX3SOURCES 2
526 /* Instruction with vector SIB byte:
527 1: 128bit vector register.
528 2: 256bit vector register.
529 3: 512bit vector register.
535 /* SSE to AVX support required */
537 /* No AVX equivalent */
540 /* insn has EVEX prefix:
541 1: 512bit EVEX prefix.
542 2: 128bit EVEX prefix.
543 3: 256bit EVEX prefix.
544 4: Length-ignored (LIG) EVEX prefix.
545 5: Length determined from actual operands.
554 /* AVX512 masking support:
557 3: Both zeroing and merging masking.
559 #define ZEROING_MASKING 1
560 #define MERGING_MASKING 2
561 #define BOTH_MASKING 3
566 /* Static rounding control is supported. */
569 /* Supress All Exceptions is supported. */
572 /* Compressed Disp8*N attribute. */
573 #define DISP8_SHIFT_VL 7
576 /* Default mask isn't allowed. */
579 /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
580 It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
584 /* Support encoding optimization. */
597 /* The last bitfield in i386_opcode_modifier. */
601 typedef struct i386_opcode_modifier
606 unsigned int modrm:1;
607 unsigned int shortform:1;
609 unsigned int jumpdword:1;
610 unsigned int jumpbyte:1;
611 unsigned int jumpintersegment:1;
612 unsigned int floatmf:1;
613 unsigned int floatr:1;
614 unsigned int size16:1;
615 unsigned int size32:1;
616 unsigned int size64:1;
617 unsigned int checkregsize:1;
618 unsigned int ignoresize:1;
619 unsigned int defaultsize:1;
620 unsigned int no_bsuf:1;
621 unsigned int no_wsuf:1;
622 unsigned int no_lsuf:1;
623 unsigned int no_ssuf:1;
624 unsigned int no_qsuf:1;
625 unsigned int no_ldsuf:1;
626 unsigned int fwait:1;
627 unsigned int isstring:1;
628 unsigned int bndprefixok:1;
629 unsigned int notrackprefixok:1;
630 unsigned int islockable:1;
631 unsigned int regkludge:1;
632 unsigned int implicit1stxmm0:1;
633 unsigned int hleprefixok:2;
634 unsigned int repprefixok:1;
635 unsigned int todword:1;
636 unsigned int toqword:1;
637 unsigned int addrprefixopreg:1;
638 unsigned int isprefix:1;
639 unsigned int immext:1;
640 unsigned int norex64:1;
641 unsigned int rex64:1;
644 unsigned int vexvvvv:2;
646 unsigned int vexopcode:3;
647 unsigned int vexsources:2;
648 unsigned int vecsib:2;
649 unsigned int sse2avx:1;
650 unsigned int noavx:1;
652 unsigned int masking:2;
653 unsigned int broadcast:1;
654 unsigned int staticrounding:1;
656 unsigned int disp8memshift:3;
657 unsigned int nodefmask:1;
658 unsigned int implicitquadgroup:1;
659 unsigned int optimize:1;
660 unsigned int attmnemonic:1;
661 unsigned int attsyntax:1;
662 unsigned int intelsyntax:1;
663 unsigned int amd64:1;
664 unsigned int intel64:1;
665 } i386_opcode_modifier;
667 /* Position of operand_type bits. */
671 /* Register (qualified by Byte, Word, etc) */
675 /* Vector registers */
677 /* Vector Mask registers */
679 /* Control register */
685 /* 2 bit segment register */
687 /* 3 bit segment register */
689 /* 1 bit immediate */
691 /* 8 bit immediate */
693 /* 8 bit immediate sign extended */
695 /* 16 bit immediate */
697 /* 32 bit immediate */
699 /* 32 bit immediate sign extended */
701 /* 64 bit immediate */
703 /* 8bit/16bit/32bit displacements are used in different ways,
704 depending on the instruction. For jumps, they specify the
705 size of the PC relative displacement, for instructions with
706 memory operand, they specify the size of the offset relative
707 to the base register, and for instructions with memory offset
708 such as `mov 1234,%al' they specify the size of the offset
709 relative to the segment base. */
710 /* 8 bit displacement */
712 /* 16 bit displacement */
714 /* 32 bit displacement */
716 /* 32 bit signed displacement */
718 /* 64 bit displacement */
720 /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
722 /* Register which can be used for base or index in memory operand. */
724 /* Register to hold in/out port addr = dx */
726 /* Register to hold shift count = cl */
728 /* Absolute address for jump. */
730 /* String insn operand with fixed es segment */
732 /* RegMem is for instructions with a modrm byte where the register
733 destination operand should be encoded in the mod and regmem fields.
734 Normally, it will be encoded in the reg field. We add a RegMem
735 flag to the destination register operand to indicate that it should
736 be encoded in the regmem field. */
742 /* WORD size. 2 byte */
744 /* DWORD size. 4 byte */
746 /* FWORD size. 6 byte */
748 /* QWORD size. 8 byte */
750 /* TBYTE size. 10 byte */
758 /* Unspecified memory size. */
760 /* Any memory size. */
763 /* Vector 4 bit immediate. */
766 /* Bound register. */
769 /* The number of bitfields in i386_operand_type. */
773 #define OTNumOfUints \
774 ((OTNum - 1) / sizeof (unsigned int) / CHAR_BIT + 1)
775 #define OTNumOfBits \
776 (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
778 /* If you get a compiler error for zero width of the unused field,
780 #define OTUnused OTNum
782 typedef union i386_operand_type
787 unsigned int regmmx:1;
788 unsigned int regsimd:1;
789 unsigned int regmask:1;
790 unsigned int control:1;
791 unsigned int debug:1;
793 unsigned int sreg2:1;
794 unsigned int sreg3:1;
797 unsigned int imm8s:1;
798 unsigned int imm16:1;
799 unsigned int imm32:1;
800 unsigned int imm32s:1;
801 unsigned int imm64:1;
802 unsigned int disp8:1;
803 unsigned int disp16:1;
804 unsigned int disp32:1;
805 unsigned int disp32s:1;
806 unsigned int disp64:1;
808 unsigned int baseindex:1;
809 unsigned int inoutportreg:1;
810 unsigned int shiftcount:1;
811 unsigned int jumpabsolute:1;
812 unsigned int esseg:1;
813 unsigned int regmem:1;
817 unsigned int dword:1;
818 unsigned int fword:1;
819 unsigned int qword:1;
820 unsigned int tbyte:1;
821 unsigned int xmmword:1;
822 unsigned int ymmword:1;
823 unsigned int zmmword:1;
824 unsigned int unspecified:1;
825 unsigned int anysize:1;
826 unsigned int vec_imm4:1;
827 unsigned int regbnd:1;
829 unsigned int unused:(OTNumOfBits - OTUnused);
832 unsigned int array[OTNumOfUints];
835 typedef struct insn_template
837 /* instruction name sans width suffix ("mov" for movl insns) */
840 /* how many operands */
841 unsigned int operands;
843 /* base_opcode is the fundamental opcode byte without optional
845 unsigned int base_opcode;
846 #define Opcode_D 0x2 /* Direction bit:
847 set if Reg --> Regmem;
848 unset if Regmem --> Reg. */
849 #define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */
850 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
852 /* extension_opcode is the 3 bit extension for group <n> insns.
853 This field is also used to store the 8-bit opcode suffix for the
854 AMD 3DNow! instructions.
855 If this template has no extension opcode (the usual case) use None
857 unsigned int extension_opcode;
858 #define None 0xffff /* If no extension_opcode is possible. */
861 unsigned char opcode_length;
863 /* cpu feature flags */
864 i386_cpu_flags cpu_flags;
866 /* the bits in opcode_modifier are used to generate the final opcode from
867 the base_opcode. These bits also are used to detect alternate forms of
868 the same instruction */
869 i386_opcode_modifier opcode_modifier;
871 /* operand_types[i] describes the type of operand i. This is made
872 by OR'ing together all of the possible type masks. (e.g.
873 'operand_types[i] = Reg|Imm' specifies that operand i can be
874 either a register or an immediate operand. */
875 i386_operand_type operand_types[MAX_OPERANDS];
879 extern const insn_template i386_optab[];
881 /* these are for register name --> number & type hash lookup */
885 i386_operand_type reg_type;
886 unsigned char reg_flags;
887 #define RegRex 0x1 /* Extended register. */
888 #define RegRex64 0x2 /* Extended 8 bit register. */
889 #define RegVRex 0x4 /* Extended vector register. */
890 unsigned char reg_num;
891 #define RegRip ((unsigned char ) ~0)
892 #define RegEip (RegRip - 1)
893 /* EIZ and RIZ are fake index registers. */
894 #define RegEiz (RegEip - 1)
895 #define RegRiz (RegEiz - 1)
896 /* FLAT is a fake segment register (Intel mode). */
897 #define RegFlat ((unsigned char) ~0)
898 signed char dw2_regnum[2];
899 #define Dw2Inval (-1)
903 /* Entries in i386_regtab. */
906 #define REGNAM_EAX 41
908 extern const reg_entry i386_regtab[];
909 extern const unsigned int i386_regtab_size;
914 unsigned int seg_prefix;
918 extern const seg_entry cs;
919 extern const seg_entry ds;
920 extern const seg_entry ss;
921 extern const seg_entry es;
922 extern const seg_entry fs;
923 extern const seg_entry gs;