1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
6 This file is part of the GNU opcodes library.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
26 modified by John Hassey (hassey@dg-rtp.dg.com)
27 x86-64 support added by Jan Hubicka (jh@suse.cz)
28 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
30 /* The main tables describing the instructions is essentially a copy
31 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
32 Programmers Manual. Usually, there is a capital letter, followed
33 by a small letter. The capital letter tell the addressing mode,
34 and the small letter tells about the operand size. Refer to
35 the Intel manual for details. */
40 #include "opcode/i386.h"
41 #include "libiberty.h"
45 static int print_insn (bfd_vma, disassemble_info *);
46 static void dofloat (int);
47 static void OP_ST (int, int);
48 static void OP_STi (int, int);
49 static int putop (const char *, int);
50 static void oappend (const char *);
51 static void append_seg (void);
52 static void OP_indirE (int, int);
53 static void print_operand_value (char *, int, bfd_vma);
54 static void OP_E_register (int, int);
55 static void OP_E_memory (int, int);
56 static void print_displacement (char *, bfd_vma);
57 static void OP_E (int, int);
58 static void OP_G (int, int);
59 static bfd_vma get64 (void);
60 static bfd_signed_vma get32 (void);
61 static bfd_signed_vma get32s (void);
62 static int get16 (void);
63 static void set_op (bfd_vma, int);
64 static void OP_Skip_MODRM (int, int);
65 static void OP_REG (int, int);
66 static void OP_IMREG (int, int);
67 static void OP_I (int, int);
68 static void OP_I64 (int, int);
69 static void OP_sI (int, int);
70 static void OP_J (int, int);
71 static void OP_SEG (int, int);
72 static void OP_DIR (int, int);
73 static void OP_OFF (int, int);
74 static void OP_OFF64 (int, int);
75 static void ptr_reg (int, int);
76 static void OP_ESreg (int, int);
77 static void OP_DSreg (int, int);
78 static void OP_C (int, int);
79 static void OP_D (int, int);
80 static void OP_T (int, int);
81 static void OP_R (int, int);
82 static void OP_MMX (int, int);
83 static void OP_XMM (int, int);
84 static void OP_EM (int, int);
85 static void OP_EX (int, int);
86 static void OP_EMC (int,int);
87 static void OP_MXC (int,int);
88 static void OP_MS (int, int);
89 static void OP_XS (int, int);
90 static void OP_M (int, int);
91 static void OP_VEX (int, int);
92 static void OP_EX_Vex (int, int);
93 static void OP_EX_VexW (int, int);
94 static void OP_EX_VexImmW (int, int);
95 static void OP_XMM_Vex (int, int);
96 static void OP_XMM_VexW (int, int);
97 static void OP_REG_VexI4 (int, int);
98 static void PCLMUL_Fixup (int, int);
99 static void VEXI4_Fixup (int, int);
100 static void VZERO_Fixup (int, int);
101 static void VCMP_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void NOP_Fixup1 (int, int);
106 static void NOP_Fixup2 (int, int);
107 static void OP_3DNowSuffix (int, int);
108 static void CMP_Fixup (int, int);
109 static void BadOp (void);
110 static void REP_Fixup (int, int);
111 static void HLE_Fixup1 (int, int);
112 static void HLE_Fixup2 (int, int);
113 static void HLE_Fixup3 (int, int);
114 static void CMPXCHG8B_Fixup (int, int);
115 static void XMM_Fixup (int, int);
116 static void CRC32_Fixup (int, int);
117 static void FXSAVE_Fixup (int, int);
118 static void OP_LWPCB_E (int, int);
119 static void OP_LWP_E (int, int);
120 static void OP_Vex_2src_1 (int, int);
121 static void OP_Vex_2src_2 (int, int);
123 static void MOVBE_Fixup (int, int);
126 /* Points to first byte not fetched. */
127 bfd_byte *max_fetched;
128 bfd_byte the_buffer[MAX_MNEM_SIZE];
141 enum address_mode address_mode;
143 /* Flags for the prefixes for the current instruction. See below. */
146 /* REX prefix the current instruction. See below. */
148 /* Bits of REX we've already used. */
150 /* REX bits in original REX prefix ignored. */
151 static int rex_ignored;
152 /* Mark parts used in the REX prefix. When we are testing for
153 empty prefix (for 8bit register REX extension), just mask it
154 out. Otherwise test for REX bit is excuse for existence of REX
155 only in case value is nonzero. */
156 #define USED_REX(value) \
161 rex_used |= (value) | REX_OPCODE; \
164 rex_used |= REX_OPCODE; \
167 /* Flags for prefixes which we somehow handled when printing the
168 current instruction. */
169 static int used_prefixes;
171 /* Flags stored in PREFIXES. */
172 #define PREFIX_REPZ 1
173 #define PREFIX_REPNZ 2
174 #define PREFIX_LOCK 4
176 #define PREFIX_SS 0x10
177 #define PREFIX_DS 0x20
178 #define PREFIX_ES 0x40
179 #define PREFIX_FS 0x80
180 #define PREFIX_GS 0x100
181 #define PREFIX_DATA 0x200
182 #define PREFIX_ADDR 0x400
183 #define PREFIX_FWAIT 0x800
185 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
186 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
188 #define FETCH_DATA(info, addr) \
189 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
190 ? 1 : fetch_data ((info), (addr)))
193 fetch_data (struct disassemble_info *info, bfd_byte *addr)
196 struct dis_private *priv = (struct dis_private *) info->private_data;
197 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
199 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
200 status = (*info->read_memory_func) (start,
202 addr - priv->max_fetched,
208 /* If we did manage to read at least one byte, then
209 print_insn_i386 will do something sensible. Otherwise, print
210 an error. We do that here because this is where we know
212 if (priv->max_fetched == priv->the_buffer)
213 (*info->memory_error_func) (status, start, info);
214 longjmp (priv->bailout, 1);
217 priv->max_fetched = addr;
221 #define XX { NULL, 0 }
222 #define Bad_Opcode NULL, { { NULL, 0 } }
224 #define Eb { OP_E, b_mode }
225 #define EbS { OP_E, b_swap_mode }
226 #define Ev { OP_E, v_mode }
227 #define EvS { OP_E, v_swap_mode }
228 #define Ed { OP_E, d_mode }
229 #define Edq { OP_E, dq_mode }
230 #define Edqw { OP_E, dqw_mode }
231 #define Edqb { OP_E, dqb_mode }
232 #define Edqd { OP_E, dqd_mode }
233 #define Eq { OP_E, q_mode }
234 #define indirEv { OP_indirE, stack_v_mode }
235 #define indirEp { OP_indirE, f_mode }
236 #define stackEv { OP_E, stack_v_mode }
237 #define Em { OP_E, m_mode }
238 #define Ew { OP_E, w_mode }
239 #define M { OP_M, 0 } /* lea, lgdt, etc. */
240 #define Ma { OP_M, a_mode }
241 #define Mb { OP_M, b_mode }
242 #define Md { OP_M, d_mode }
243 #define Mo { OP_M, o_mode }
244 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
245 #define Mq { OP_M, q_mode }
246 #define Mx { OP_M, x_mode }
247 #define Mxmm { OP_M, xmm_mode }
248 #define Gb { OP_G, b_mode }
249 #define Gv { OP_G, v_mode }
250 #define Gd { OP_G, d_mode }
251 #define Gdq { OP_G, dq_mode }
252 #define Gm { OP_G, m_mode }
253 #define Gw { OP_G, w_mode }
254 #define Rd { OP_R, d_mode }
255 #define Rm { OP_R, m_mode }
256 #define Ib { OP_I, b_mode }
257 #define sIb { OP_sI, b_mode } /* sign extened byte */
258 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
259 #define Iv { OP_I, v_mode }
260 #define sIv { OP_sI, v_mode }
261 #define Iq { OP_I, q_mode }
262 #define Iv64 { OP_I64, v_mode }
263 #define Iw { OP_I, w_mode }
264 #define I1 { OP_I, const_1_mode }
265 #define Jb { OP_J, b_mode }
266 #define Jv { OP_J, v_mode }
267 #define Cm { OP_C, m_mode }
268 #define Dm { OP_D, m_mode }
269 #define Td { OP_T, d_mode }
270 #define Skip_MODRM { OP_Skip_MODRM, 0 }
272 #define RMeAX { OP_REG, eAX_reg }
273 #define RMeBX { OP_REG, eBX_reg }
274 #define RMeCX { OP_REG, eCX_reg }
275 #define RMeDX { OP_REG, eDX_reg }
276 #define RMeSP { OP_REG, eSP_reg }
277 #define RMeBP { OP_REG, eBP_reg }
278 #define RMeSI { OP_REG, eSI_reg }
279 #define RMeDI { OP_REG, eDI_reg }
280 #define RMrAX { OP_REG, rAX_reg }
281 #define RMrBX { OP_REG, rBX_reg }
282 #define RMrCX { OP_REG, rCX_reg }
283 #define RMrDX { OP_REG, rDX_reg }
284 #define RMrSP { OP_REG, rSP_reg }
285 #define RMrBP { OP_REG, rBP_reg }
286 #define RMrSI { OP_REG, rSI_reg }
287 #define RMrDI { OP_REG, rDI_reg }
288 #define RMAL { OP_REG, al_reg }
289 #define RMCL { OP_REG, cl_reg }
290 #define RMDL { OP_REG, dl_reg }
291 #define RMBL { OP_REG, bl_reg }
292 #define RMAH { OP_REG, ah_reg }
293 #define RMCH { OP_REG, ch_reg }
294 #define RMDH { OP_REG, dh_reg }
295 #define RMBH { OP_REG, bh_reg }
296 #define RMAX { OP_REG, ax_reg }
297 #define RMDX { OP_REG, dx_reg }
299 #define eAX { OP_IMREG, eAX_reg }
300 #define eBX { OP_IMREG, eBX_reg }
301 #define eCX { OP_IMREG, eCX_reg }
302 #define eDX { OP_IMREG, eDX_reg }
303 #define eSP { OP_IMREG, eSP_reg }
304 #define eBP { OP_IMREG, eBP_reg }
305 #define eSI { OP_IMREG, eSI_reg }
306 #define eDI { OP_IMREG, eDI_reg }
307 #define AL { OP_IMREG, al_reg }
308 #define CL { OP_IMREG, cl_reg }
309 #define DL { OP_IMREG, dl_reg }
310 #define BL { OP_IMREG, bl_reg }
311 #define AH { OP_IMREG, ah_reg }
312 #define CH { OP_IMREG, ch_reg }
313 #define DH { OP_IMREG, dh_reg }
314 #define BH { OP_IMREG, bh_reg }
315 #define AX { OP_IMREG, ax_reg }
316 #define DX { OP_IMREG, dx_reg }
317 #define zAX { OP_IMREG, z_mode_ax_reg }
318 #define indirDX { OP_IMREG, indir_dx_reg }
320 #define Sw { OP_SEG, w_mode }
321 #define Sv { OP_SEG, v_mode }
322 #define Ap { OP_DIR, 0 }
323 #define Ob { OP_OFF64, b_mode }
324 #define Ov { OP_OFF64, v_mode }
325 #define Xb { OP_DSreg, eSI_reg }
326 #define Xv { OP_DSreg, eSI_reg }
327 #define Xz { OP_DSreg, eSI_reg }
328 #define Yb { OP_ESreg, eDI_reg }
329 #define Yv { OP_ESreg, eDI_reg }
330 #define DSBX { OP_DSreg, eBX_reg }
332 #define es { OP_REG, es_reg }
333 #define ss { OP_REG, ss_reg }
334 #define cs { OP_REG, cs_reg }
335 #define ds { OP_REG, ds_reg }
336 #define fs { OP_REG, fs_reg }
337 #define gs { OP_REG, gs_reg }
339 #define MX { OP_MMX, 0 }
340 #define XM { OP_XMM, 0 }
341 #define XMScalar { OP_XMM, scalar_mode }
342 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
343 #define XMM { OP_XMM, xmm_mode }
344 #define EM { OP_EM, v_mode }
345 #define EMS { OP_EM, v_swap_mode }
346 #define EMd { OP_EM, d_mode }
347 #define EMx { OP_EM, x_mode }
348 #define EXw { OP_EX, w_mode }
349 #define EXd { OP_EX, d_mode }
350 #define EXdScalar { OP_EX, d_scalar_mode }
351 #define EXdS { OP_EX, d_swap_mode }
352 #define EXq { OP_EX, q_mode }
353 #define EXqScalar { OP_EX, q_scalar_mode }
354 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
355 #define EXqS { OP_EX, q_swap_mode }
356 #define EXx { OP_EX, x_mode }
357 #define EXxS { OP_EX, x_swap_mode }
358 #define EXxmm { OP_EX, xmm_mode }
359 #define EXxmmq { OP_EX, xmmq_mode }
360 #define EXxmm_mb { OP_EX, xmm_mb_mode }
361 #define EXxmm_mw { OP_EX, xmm_mw_mode }
362 #define EXxmm_md { OP_EX, xmm_md_mode }
363 #define EXxmm_mq { OP_EX, xmm_mq_mode }
364 #define EXxmmdw { OP_EX, xmmdw_mode }
365 #define EXxmmqd { OP_EX, xmmqd_mode }
366 #define EXymmq { OP_EX, ymmq_mode }
367 #define EXVexWdq { OP_EX, vex_w_dq_mode }
368 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
369 #define MS { OP_MS, v_mode }
370 #define XS { OP_XS, v_mode }
371 #define EMCq { OP_EMC, q_mode }
372 #define MXC { OP_MXC, 0 }
373 #define OPSUF { OP_3DNowSuffix, 0 }
374 #define CMP { CMP_Fixup, 0 }
375 #define XMM0 { XMM_Fixup, 0 }
376 #define FXSAVE { FXSAVE_Fixup, 0 }
377 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
378 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
380 #define Vex { OP_VEX, vex_mode }
381 #define VexScalar { OP_VEX, vex_scalar_mode }
382 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
383 #define Vex128 { OP_VEX, vex128_mode }
384 #define Vex256 { OP_VEX, vex256_mode }
385 #define VexGdq { OP_VEX, dq_mode }
386 #define VexI4 { VEXI4_Fixup, 0}
387 #define EXdVex { OP_EX_Vex, d_mode }
388 #define EXdVexS { OP_EX_Vex, d_swap_mode }
389 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
390 #define EXqVex { OP_EX_Vex, q_mode }
391 #define EXqVexS { OP_EX_Vex, q_swap_mode }
392 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
393 #define EXVexW { OP_EX_VexW, x_mode }
394 #define EXdVexW { OP_EX_VexW, d_mode }
395 #define EXqVexW { OP_EX_VexW, q_mode }
396 #define EXVexImmW { OP_EX_VexImmW, x_mode }
397 #define XMVex { OP_XMM_Vex, 0 }
398 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
399 #define XMVexW { OP_XMM_VexW, 0 }
400 #define XMVexI4 { OP_REG_VexI4, x_mode }
401 #define PCLMUL { PCLMUL_Fixup, 0 }
402 #define VZERO { VZERO_Fixup, 0 }
403 #define VCMP { VCMP_Fixup, 0 }
405 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
406 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
408 /* Used handle "rep" prefix for string instructions. */
409 #define Xbr { REP_Fixup, eSI_reg }
410 #define Xvr { REP_Fixup, eSI_reg }
411 #define Ybr { REP_Fixup, eDI_reg }
412 #define Yvr { REP_Fixup, eDI_reg }
413 #define Yzr { REP_Fixup, eDI_reg }
414 #define indirDXr { REP_Fixup, indir_dx_reg }
415 #define ALr { REP_Fixup, al_reg }
416 #define eAXr { REP_Fixup, eAX_reg }
418 /* Used handle HLE prefix for lockable instructions. */
419 #define Ebh1 { HLE_Fixup1, b_mode }
420 #define Evh1 { HLE_Fixup1, v_mode }
421 #define Ebh2 { HLE_Fixup2, b_mode }
422 #define Evh2 { HLE_Fixup2, v_mode }
423 #define Ebh3 { HLE_Fixup3, b_mode }
424 #define Evh3 { HLE_Fixup3, v_mode }
426 #define cond_jump_flag { NULL, cond_jump_mode }
427 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
429 /* bits in sizeflag */
430 #define SUFFIX_ALWAYS 4
438 /* byte operand with operand swapped */
440 /* byte operand, sign extend like 'T' suffix */
442 /* operand size depends on prefixes */
444 /* operand size depends on prefixes with operand swapped */
448 /* double word operand */
450 /* double word operand with operand swapped */
452 /* quad word operand */
454 /* quad word operand with operand swapped */
456 /* ten-byte operand */
458 /* 16-byte XMM or 32-byte YMM operand */
460 /* 16-byte XMM or 32-byte YMM operand with operand swapped */
462 /* 16-byte XMM operand */
464 /* 16-byte XMM or quad word operand */
466 /* XMM register or byte memory operand */
468 /* XMM register or word memory operand */
470 /* XMM register or double word memory operand */
472 /* XMM register or quad word memory operand */
474 /* 16-byte XMM, word or double word operand */
476 /* 16-byte XMM, double word or quad word operand */
478 /* 32-byte YMM or quad word operand */
480 /* 32-byte YMM or 16-byte word operand */
482 /* d_mode in 32bit, q_mode in 64bit mode. */
484 /* pair of v_mode operands */
488 /* operand size depends on REX prefixes. */
490 /* registers like dq_mode, memory like w_mode. */
492 /* 4- or 6-byte pointer operand */
495 /* v_mode for stack-related opcodes. */
497 /* non-quad operand size depends on prefixes */
499 /* 16-byte operand */
501 /* registers like dq_mode, memory like b_mode. */
503 /* registers like dq_mode, memory like d_mode. */
505 /* normal vex mode */
507 /* 128bit vex mode */
509 /* 256bit vex mode */
511 /* operand size depends on the VEX.W bit. */
514 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
515 vex_vsib_d_w_dq_mode,
516 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
517 vex_vsib_q_w_dq_mode,
519 /* scalar, ignore vector length. */
521 /* like d_mode, ignore vector length. */
523 /* like d_swap_mode, ignore vector length. */
525 /* like q_mode, ignore vector length. */
527 /* like q_swap_mode, ignore vector length. */
529 /* like vex_mode, ignore vector length. */
531 /* like vex_w_dq_mode, ignore vector length. */
532 vex_scalar_w_dq_mode,
597 #define FLOAT NULL, { { NULL, FLOATCODE } }
599 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
600 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
601 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
602 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
603 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
604 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
605 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
606 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
607 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
608 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
609 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
610 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
712 MOD_VEX_0F12_PREFIX_0,
714 MOD_VEX_0F16_PREFIX_0,
730 MOD_VEX_0FD7_PREFIX_2,
731 MOD_VEX_0FE7_PREFIX_2,
732 MOD_VEX_0FF0_PREFIX_3,
733 MOD_VEX_0F381A_PREFIX_2,
734 MOD_VEX_0F382A_PREFIX_2,
735 MOD_VEX_0F382C_PREFIX_2,
736 MOD_VEX_0F382D_PREFIX_2,
737 MOD_VEX_0F382E_PREFIX_2,
738 MOD_VEX_0F382F_PREFIX_2,
739 MOD_VEX_0F385A_PREFIX_2,
740 MOD_VEX_0F388C_PREFIX_2,
741 MOD_VEX_0F388E_PREFIX_2,
915 PREFIX_VEX_0F71_REG_2,
916 PREFIX_VEX_0F71_REG_4,
917 PREFIX_VEX_0F71_REG_6,
918 PREFIX_VEX_0F72_REG_2,
919 PREFIX_VEX_0F72_REG_4,
920 PREFIX_VEX_0F72_REG_6,
921 PREFIX_VEX_0F73_REG_2,
922 PREFIX_VEX_0F73_REG_3,
923 PREFIX_VEX_0F73_REG_6,
924 PREFIX_VEX_0F73_REG_7,
1090 PREFIX_VEX_0F38F3_REG_1,
1091 PREFIX_VEX_0F38F3_REG_2,
1092 PREFIX_VEX_0F38F3_REG_3,
1194 THREE_BYTE_0F38 = 0,
1215 VEX_LEN_0F10_P_1 = 0,
1219 VEX_LEN_0F12_P_0_M_0,
1220 VEX_LEN_0F12_P_0_M_1,
1223 VEX_LEN_0F16_P_0_M_0,
1224 VEX_LEN_0F16_P_0_M_1,
1258 VEX_LEN_0FAE_R_2_M_0,
1259 VEX_LEN_0FAE_R_3_M_0,
1268 VEX_LEN_0F381A_P_2_M_0,
1271 VEX_LEN_0F385A_P_2_M_0,
1278 VEX_LEN_0F38F3_R_1_P_0,
1279 VEX_LEN_0F38F3_R_2_P_0,
1280 VEX_LEN_0F38F3_R_3_P_0,
1322 VEX_LEN_0FXOP_08_CC,
1323 VEX_LEN_0FXOP_08_CD,
1324 VEX_LEN_0FXOP_08_CE,
1325 VEX_LEN_0FXOP_08_CF,
1326 VEX_LEN_0FXOP_08_EC,
1327 VEX_LEN_0FXOP_08_ED,
1328 VEX_LEN_0FXOP_08_EE,
1329 VEX_LEN_0FXOP_08_EF,
1330 VEX_LEN_0FXOP_09_80,
1521 VEX_W_0F381A_P_2_M_0,
1533 VEX_W_0F382A_P_2_M_0,
1535 VEX_W_0F382C_P_2_M_0,
1536 VEX_W_0F382D_P_2_M_0,
1537 VEX_W_0F382E_P_2_M_0,
1538 VEX_W_0F382F_P_2_M_0,
1560 VEX_W_0F385A_P_2_M_0,
1607 typedef void (*op_rtn) (int bytemode, int sizeflag);
1618 /* Upper case letters in the instruction names here are macros.
1619 'A' => print 'b' if no register operands or suffix_always is true
1620 'B' => print 'b' if suffix_always is true
1621 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1623 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1624 suffix_always is true
1625 'E' => print 'e' if 32-bit form of jcxz
1626 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1627 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1628 'H' => print ",pt" or ",pn" branch hint
1629 'I' => honor following macro letter even in Intel mode (implemented only
1630 for some of the macro letters)
1632 'K' => print 'd' or 'q' if rex prefix is present.
1633 'L' => print 'l' if suffix_always is true
1634 'M' => print 'r' if intel_mnemonic is false.
1635 'N' => print 'n' if instruction has no wait "prefix"
1636 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1637 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1638 or suffix_always is true. print 'q' if rex prefix is present.
1639 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1641 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1642 'S' => print 'w', 'l' or 'q' if suffix_always is true
1643 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1644 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1645 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1646 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1647 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1648 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1649 suffix_always is true.
1650 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1651 '!' => change condition from true to false or from false to true.
1652 '%' => add 1 upper case letter to the macro.
1654 2 upper case letter macros:
1655 "XY" => print 'x' or 'y' if no register operands or suffix_always
1657 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1658 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
1659 or suffix_always is true
1660 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1661 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1662 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1663 "LW" => print 'd', 'q' depending on the VEX.W bit
1665 Many of the above letters print nothing in Intel mode. See "putop"
1668 Braces '{' and '}', and vertical bars '|', indicate alternative
1669 mnemonic strings for AT&T and Intel. */
1671 static const struct dis386 dis386[] = {
1673 { "addB", { Ebh1, Gb } },
1674 { "addS", { Evh1, Gv } },
1675 { "addB", { Gb, EbS } },
1676 { "addS", { Gv, EvS } },
1677 { "addB", { AL, Ib } },
1678 { "addS", { eAX, Iv } },
1679 { X86_64_TABLE (X86_64_06) },
1680 { X86_64_TABLE (X86_64_07) },
1682 { "orB", { Ebh1, Gb } },
1683 { "orS", { Evh1, Gv } },
1684 { "orB", { Gb, EbS } },
1685 { "orS", { Gv, EvS } },
1686 { "orB", { AL, Ib } },
1687 { "orS", { eAX, Iv } },
1688 { X86_64_TABLE (X86_64_0D) },
1689 { Bad_Opcode }, /* 0x0f extended opcode escape */
1691 { "adcB", { Ebh1, Gb } },
1692 { "adcS", { Evh1, Gv } },
1693 { "adcB", { Gb, EbS } },
1694 { "adcS", { Gv, EvS } },
1695 { "adcB", { AL, Ib } },
1696 { "adcS", { eAX, Iv } },
1697 { X86_64_TABLE (X86_64_16) },
1698 { X86_64_TABLE (X86_64_17) },
1700 { "sbbB", { Ebh1, Gb } },
1701 { "sbbS", { Evh1, Gv } },
1702 { "sbbB", { Gb, EbS } },
1703 { "sbbS", { Gv, EvS } },
1704 { "sbbB", { AL, Ib } },
1705 { "sbbS", { eAX, Iv } },
1706 { X86_64_TABLE (X86_64_1E) },
1707 { X86_64_TABLE (X86_64_1F) },
1709 { "andB", { Ebh1, Gb } },
1710 { "andS", { Evh1, Gv } },
1711 { "andB", { Gb, EbS } },
1712 { "andS", { Gv, EvS } },
1713 { "andB", { AL, Ib } },
1714 { "andS", { eAX, Iv } },
1715 { Bad_Opcode }, /* SEG ES prefix */
1716 { X86_64_TABLE (X86_64_27) },
1718 { "subB", { Ebh1, Gb } },
1719 { "subS", { Evh1, Gv } },
1720 { "subB", { Gb, EbS } },
1721 { "subS", { Gv, EvS } },
1722 { "subB", { AL, Ib } },
1723 { "subS", { eAX, Iv } },
1724 { Bad_Opcode }, /* SEG CS prefix */
1725 { X86_64_TABLE (X86_64_2F) },
1727 { "xorB", { Ebh1, Gb } },
1728 { "xorS", { Evh1, Gv } },
1729 { "xorB", { Gb, EbS } },
1730 { "xorS", { Gv, EvS } },
1731 { "xorB", { AL, Ib } },
1732 { "xorS", { eAX, Iv } },
1733 { Bad_Opcode }, /* SEG SS prefix */
1734 { X86_64_TABLE (X86_64_37) },
1736 { "cmpB", { Eb, Gb } },
1737 { "cmpS", { Ev, Gv } },
1738 { "cmpB", { Gb, EbS } },
1739 { "cmpS", { Gv, EvS } },
1740 { "cmpB", { AL, Ib } },
1741 { "cmpS", { eAX, Iv } },
1742 { Bad_Opcode }, /* SEG DS prefix */
1743 { X86_64_TABLE (X86_64_3F) },
1745 { "inc{S|}", { RMeAX } },
1746 { "inc{S|}", { RMeCX } },
1747 { "inc{S|}", { RMeDX } },
1748 { "inc{S|}", { RMeBX } },
1749 { "inc{S|}", { RMeSP } },
1750 { "inc{S|}", { RMeBP } },
1751 { "inc{S|}", { RMeSI } },
1752 { "inc{S|}", { RMeDI } },
1754 { "dec{S|}", { RMeAX } },
1755 { "dec{S|}", { RMeCX } },
1756 { "dec{S|}", { RMeDX } },
1757 { "dec{S|}", { RMeBX } },
1758 { "dec{S|}", { RMeSP } },
1759 { "dec{S|}", { RMeBP } },
1760 { "dec{S|}", { RMeSI } },
1761 { "dec{S|}", { RMeDI } },
1763 { "pushV", { RMrAX } },
1764 { "pushV", { RMrCX } },
1765 { "pushV", { RMrDX } },
1766 { "pushV", { RMrBX } },
1767 { "pushV", { RMrSP } },
1768 { "pushV", { RMrBP } },
1769 { "pushV", { RMrSI } },
1770 { "pushV", { RMrDI } },
1772 { "popV", { RMrAX } },
1773 { "popV", { RMrCX } },
1774 { "popV", { RMrDX } },
1775 { "popV", { RMrBX } },
1776 { "popV", { RMrSP } },
1777 { "popV", { RMrBP } },
1778 { "popV", { RMrSI } },
1779 { "popV", { RMrDI } },
1781 { X86_64_TABLE (X86_64_60) },
1782 { X86_64_TABLE (X86_64_61) },
1783 { X86_64_TABLE (X86_64_62) },
1784 { X86_64_TABLE (X86_64_63) },
1785 { Bad_Opcode }, /* seg fs */
1786 { Bad_Opcode }, /* seg gs */
1787 { Bad_Opcode }, /* op size prefix */
1788 { Bad_Opcode }, /* adr size prefix */
1790 { "pushT", { sIv } },
1791 { "imulS", { Gv, Ev, Iv } },
1792 { "pushT", { sIbT } },
1793 { "imulS", { Gv, Ev, sIb } },
1794 { "ins{b|}", { Ybr, indirDX } },
1795 { X86_64_TABLE (X86_64_6D) },
1796 { "outs{b|}", { indirDXr, Xb } },
1797 { X86_64_TABLE (X86_64_6F) },
1799 { "joH", { Jb, XX, cond_jump_flag } },
1800 { "jnoH", { Jb, XX, cond_jump_flag } },
1801 { "jbH", { Jb, XX, cond_jump_flag } },
1802 { "jaeH", { Jb, XX, cond_jump_flag } },
1803 { "jeH", { Jb, XX, cond_jump_flag } },
1804 { "jneH", { Jb, XX, cond_jump_flag } },
1805 { "jbeH", { Jb, XX, cond_jump_flag } },
1806 { "jaH", { Jb, XX, cond_jump_flag } },
1808 { "jsH", { Jb, XX, cond_jump_flag } },
1809 { "jnsH", { Jb, XX, cond_jump_flag } },
1810 { "jpH", { Jb, XX, cond_jump_flag } },
1811 { "jnpH", { Jb, XX, cond_jump_flag } },
1812 { "jlH", { Jb, XX, cond_jump_flag } },
1813 { "jgeH", { Jb, XX, cond_jump_flag } },
1814 { "jleH", { Jb, XX, cond_jump_flag } },
1815 { "jgH", { Jb, XX, cond_jump_flag } },
1817 { REG_TABLE (REG_80) },
1818 { REG_TABLE (REG_81) },
1820 { REG_TABLE (REG_82) },
1821 { "testB", { Eb, Gb } },
1822 { "testS", { Ev, Gv } },
1823 { "xchgB", { Ebh2, Gb } },
1824 { "xchgS", { Evh2, Gv } },
1826 { "movB", { Ebh3, Gb } },
1827 { "movS", { Evh3, Gv } },
1828 { "movB", { Gb, EbS } },
1829 { "movS", { Gv, EvS } },
1830 { "movD", { Sv, Sw } },
1831 { MOD_TABLE (MOD_8D) },
1832 { "movD", { Sw, Sv } },
1833 { REG_TABLE (REG_8F) },
1835 { PREFIX_TABLE (PREFIX_90) },
1836 { "xchgS", { RMeCX, eAX } },
1837 { "xchgS", { RMeDX, eAX } },
1838 { "xchgS", { RMeBX, eAX } },
1839 { "xchgS", { RMeSP, eAX } },
1840 { "xchgS", { RMeBP, eAX } },
1841 { "xchgS", { RMeSI, eAX } },
1842 { "xchgS", { RMeDI, eAX } },
1844 { "cW{t|}R", { XX } },
1845 { "cR{t|}O", { XX } },
1846 { X86_64_TABLE (X86_64_9A) },
1847 { Bad_Opcode }, /* fwait */
1848 { "pushfT", { XX } },
1849 { "popfT", { XX } },
1853 { "mov%LB", { AL, Ob } },
1854 { "mov%LS", { eAX, Ov } },
1855 { "mov%LB", { Ob, AL } },
1856 { "mov%LS", { Ov, eAX } },
1857 { "movs{b|}", { Ybr, Xb } },
1858 { "movs{R|}", { Yvr, Xv } },
1859 { "cmps{b|}", { Xb, Yb } },
1860 { "cmps{R|}", { Xv, Yv } },
1862 { "testB", { AL, Ib } },
1863 { "testS", { eAX, Iv } },
1864 { "stosB", { Ybr, AL } },
1865 { "stosS", { Yvr, eAX } },
1866 { "lodsB", { ALr, Xb } },
1867 { "lodsS", { eAXr, Xv } },
1868 { "scasB", { AL, Yb } },
1869 { "scasS", { eAX, Yv } },
1871 { "movB", { RMAL, Ib } },
1872 { "movB", { RMCL, Ib } },
1873 { "movB", { RMDL, Ib } },
1874 { "movB", { RMBL, Ib } },
1875 { "movB", { RMAH, Ib } },
1876 { "movB", { RMCH, Ib } },
1877 { "movB", { RMDH, Ib } },
1878 { "movB", { RMBH, Ib } },
1880 { "mov%LV", { RMeAX, Iv64 } },
1881 { "mov%LV", { RMeCX, Iv64 } },
1882 { "mov%LV", { RMeDX, Iv64 } },
1883 { "mov%LV", { RMeBX, Iv64 } },
1884 { "mov%LV", { RMeSP, Iv64 } },
1885 { "mov%LV", { RMeBP, Iv64 } },
1886 { "mov%LV", { RMeSI, Iv64 } },
1887 { "mov%LV", { RMeDI, Iv64 } },
1889 { REG_TABLE (REG_C0) },
1890 { REG_TABLE (REG_C1) },
1893 { X86_64_TABLE (X86_64_C4) },
1894 { X86_64_TABLE (X86_64_C5) },
1895 { REG_TABLE (REG_C6) },
1896 { REG_TABLE (REG_C7) },
1898 { "enterT", { Iw, Ib } },
1899 { "leaveT", { XX } },
1900 { "Jret{|f}P", { Iw } },
1901 { "Jret{|f}P", { XX } },
1904 { X86_64_TABLE (X86_64_CE) },
1905 { "iretP", { XX } },
1907 { REG_TABLE (REG_D0) },
1908 { REG_TABLE (REG_D1) },
1909 { REG_TABLE (REG_D2) },
1910 { REG_TABLE (REG_D3) },
1911 { X86_64_TABLE (X86_64_D4) },
1912 { X86_64_TABLE (X86_64_D5) },
1914 { "xlat", { DSBX } },
1925 { "loopneFH", { Jb, XX, loop_jcxz_flag } },
1926 { "loopeFH", { Jb, XX, loop_jcxz_flag } },
1927 { "loopFH", { Jb, XX, loop_jcxz_flag } },
1928 { "jEcxzH", { Jb, XX, loop_jcxz_flag } },
1929 { "inB", { AL, Ib } },
1930 { "inG", { zAX, Ib } },
1931 { "outB", { Ib, AL } },
1932 { "outG", { Ib, zAX } },
1934 { "callT", { Jv } },
1936 { X86_64_TABLE (X86_64_EA) },
1938 { "inB", { AL, indirDX } },
1939 { "inG", { zAX, indirDX } },
1940 { "outB", { indirDX, AL } },
1941 { "outG", { indirDX, zAX } },
1943 { Bad_Opcode }, /* lock prefix */
1944 { "icebp", { XX } },
1945 { Bad_Opcode }, /* repne */
1946 { Bad_Opcode }, /* repz */
1949 { REG_TABLE (REG_F6) },
1950 { REG_TABLE (REG_F7) },
1958 { REG_TABLE (REG_FE) },
1959 { REG_TABLE (REG_FF) },
1962 static const struct dis386 dis386_twobyte[] = {
1964 { REG_TABLE (REG_0F00 ) },
1965 { REG_TABLE (REG_0F01 ) },
1966 { "larS", { Gv, Ew } },
1967 { "lslS", { Gv, Ew } },
1969 { "syscall", { XX } },
1971 { "sysretP", { XX } },
1974 { "wbinvd", { XX } },
1978 { REG_TABLE (REG_0F0D) },
1979 { "femms", { XX } },
1980 { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */
1982 { PREFIX_TABLE (PREFIX_0F10) },
1983 { PREFIX_TABLE (PREFIX_0F11) },
1984 { PREFIX_TABLE (PREFIX_0F12) },
1985 { MOD_TABLE (MOD_0F13) },
1986 { "unpcklpX", { XM, EXx } },
1987 { "unpckhpX", { XM, EXx } },
1988 { PREFIX_TABLE (PREFIX_0F16) },
1989 { MOD_TABLE (MOD_0F17) },
1991 { REG_TABLE (REG_0F18) },
2000 { MOD_TABLE (MOD_0F20) },
2001 { MOD_TABLE (MOD_0F21) },
2002 { MOD_TABLE (MOD_0F22) },
2003 { MOD_TABLE (MOD_0F23) },
2004 { MOD_TABLE (MOD_0F24) },
2006 { MOD_TABLE (MOD_0F26) },
2009 { "movapX", { XM, EXx } },
2010 { "movapX", { EXxS, XM } },
2011 { PREFIX_TABLE (PREFIX_0F2A) },
2012 { PREFIX_TABLE (PREFIX_0F2B) },
2013 { PREFIX_TABLE (PREFIX_0F2C) },
2014 { PREFIX_TABLE (PREFIX_0F2D) },
2015 { PREFIX_TABLE (PREFIX_0F2E) },
2016 { PREFIX_TABLE (PREFIX_0F2F) },
2018 { "wrmsr", { XX } },
2019 { "rdtsc", { XX } },
2020 { "rdmsr", { XX } },
2021 { "rdpmc", { XX } },
2022 { "sysenter", { XX } },
2023 { "sysexit", { XX } },
2025 { "getsec", { XX } },
2027 { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2029 { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2036 { "cmovoS", { Gv, Ev } },
2037 { "cmovnoS", { Gv, Ev } },
2038 { "cmovbS", { Gv, Ev } },
2039 { "cmovaeS", { Gv, Ev } },
2040 { "cmoveS", { Gv, Ev } },
2041 { "cmovneS", { Gv, Ev } },
2042 { "cmovbeS", { Gv, Ev } },
2043 { "cmovaS", { Gv, Ev } },
2045 { "cmovsS", { Gv, Ev } },
2046 { "cmovnsS", { Gv, Ev } },
2047 { "cmovpS", { Gv, Ev } },
2048 { "cmovnpS", { Gv, Ev } },
2049 { "cmovlS", { Gv, Ev } },
2050 { "cmovgeS", { Gv, Ev } },
2051 { "cmovleS", { Gv, Ev } },
2052 { "cmovgS", { Gv, Ev } },
2054 { MOD_TABLE (MOD_0F51) },
2055 { PREFIX_TABLE (PREFIX_0F51) },
2056 { PREFIX_TABLE (PREFIX_0F52) },
2057 { PREFIX_TABLE (PREFIX_0F53) },
2058 { "andpX", { XM, EXx } },
2059 { "andnpX", { XM, EXx } },
2060 { "orpX", { XM, EXx } },
2061 { "xorpX", { XM, EXx } },
2063 { PREFIX_TABLE (PREFIX_0F58) },
2064 { PREFIX_TABLE (PREFIX_0F59) },
2065 { PREFIX_TABLE (PREFIX_0F5A) },
2066 { PREFIX_TABLE (PREFIX_0F5B) },
2067 { PREFIX_TABLE (PREFIX_0F5C) },
2068 { PREFIX_TABLE (PREFIX_0F5D) },
2069 { PREFIX_TABLE (PREFIX_0F5E) },
2070 { PREFIX_TABLE (PREFIX_0F5F) },
2072 { PREFIX_TABLE (PREFIX_0F60) },
2073 { PREFIX_TABLE (PREFIX_0F61) },
2074 { PREFIX_TABLE (PREFIX_0F62) },
2075 { "packsswb", { MX, EM } },
2076 { "pcmpgtb", { MX, EM } },
2077 { "pcmpgtw", { MX, EM } },
2078 { "pcmpgtd", { MX, EM } },
2079 { "packuswb", { MX, EM } },
2081 { "punpckhbw", { MX, EM } },
2082 { "punpckhwd", { MX, EM } },
2083 { "punpckhdq", { MX, EM } },
2084 { "packssdw", { MX, EM } },
2085 { PREFIX_TABLE (PREFIX_0F6C) },
2086 { PREFIX_TABLE (PREFIX_0F6D) },
2087 { "movK", { MX, Edq } },
2088 { PREFIX_TABLE (PREFIX_0F6F) },
2090 { PREFIX_TABLE (PREFIX_0F70) },
2091 { REG_TABLE (REG_0F71) },
2092 { REG_TABLE (REG_0F72) },
2093 { REG_TABLE (REG_0F73) },
2094 { "pcmpeqb", { MX, EM } },
2095 { "pcmpeqw", { MX, EM } },
2096 { "pcmpeqd", { MX, EM } },
2099 { PREFIX_TABLE (PREFIX_0F78) },
2100 { PREFIX_TABLE (PREFIX_0F79) },
2101 { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2103 { PREFIX_TABLE (PREFIX_0F7C) },
2104 { PREFIX_TABLE (PREFIX_0F7D) },
2105 { PREFIX_TABLE (PREFIX_0F7E) },
2106 { PREFIX_TABLE (PREFIX_0F7F) },
2108 { "joH", { Jv, XX, cond_jump_flag } },
2109 { "jnoH", { Jv, XX, cond_jump_flag } },
2110 { "jbH", { Jv, XX, cond_jump_flag } },
2111 { "jaeH", { Jv, XX, cond_jump_flag } },
2112 { "jeH", { Jv, XX, cond_jump_flag } },
2113 { "jneH", { Jv, XX, cond_jump_flag } },
2114 { "jbeH", { Jv, XX, cond_jump_flag } },
2115 { "jaH", { Jv, XX, cond_jump_flag } },
2117 { "jsH", { Jv, XX, cond_jump_flag } },
2118 { "jnsH", { Jv, XX, cond_jump_flag } },
2119 { "jpH", { Jv, XX, cond_jump_flag } },
2120 { "jnpH", { Jv, XX, cond_jump_flag } },
2121 { "jlH", { Jv, XX, cond_jump_flag } },
2122 { "jgeH", { Jv, XX, cond_jump_flag } },
2123 { "jleH", { Jv, XX, cond_jump_flag } },
2124 { "jgH", { Jv, XX, cond_jump_flag } },
2127 { "setno", { Eb } },
2129 { "setae", { Eb } },
2131 { "setne", { Eb } },
2132 { "setbe", { Eb } },
2136 { "setns", { Eb } },
2138 { "setnp", { Eb } },
2140 { "setge", { Eb } },
2141 { "setle", { Eb } },
2144 { "pushT", { fs } },
2146 { "cpuid", { XX } },
2147 { "btS", { Ev, Gv } },
2148 { "shldS", { Ev, Gv, Ib } },
2149 { "shldS", { Ev, Gv, CL } },
2150 { REG_TABLE (REG_0FA6) },
2151 { REG_TABLE (REG_0FA7) },
2153 { "pushT", { gs } },
2156 { "btsS", { Evh1, Gv } },
2157 { "shrdS", { Ev, Gv, Ib } },
2158 { "shrdS", { Ev, Gv, CL } },
2159 { REG_TABLE (REG_0FAE) },
2160 { "imulS", { Gv, Ev } },
2162 { "cmpxchgB", { Ebh1, Gb } },
2163 { "cmpxchgS", { Evh1, Gv } },
2164 { MOD_TABLE (MOD_0FB2) },
2165 { "btrS", { Evh1, Gv } },
2166 { MOD_TABLE (MOD_0FB4) },
2167 { MOD_TABLE (MOD_0FB5) },
2168 { "movz{bR|x}", { Gv, Eb } },
2169 { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */
2171 { PREFIX_TABLE (PREFIX_0FB8) },
2173 { REG_TABLE (REG_0FBA) },
2174 { "btcS", { Evh1, Gv } },
2175 { PREFIX_TABLE (PREFIX_0FBC) },
2176 { PREFIX_TABLE (PREFIX_0FBD) },
2177 { "movs{bR|x}", { Gv, Eb } },
2178 { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */
2180 { "xaddB", { Ebh1, Gb } },
2181 { "xaddS", { Evh1, Gv } },
2182 { PREFIX_TABLE (PREFIX_0FC2) },
2183 { PREFIX_TABLE (PREFIX_0FC3) },
2184 { "pinsrw", { MX, Edqw, Ib } },
2185 { "pextrw", { Gdq, MS, Ib } },
2186 { "shufpX", { XM, EXx, Ib } },
2187 { REG_TABLE (REG_0FC7) },
2189 { "bswap", { RMeAX } },
2190 { "bswap", { RMeCX } },
2191 { "bswap", { RMeDX } },
2192 { "bswap", { RMeBX } },
2193 { "bswap", { RMeSP } },
2194 { "bswap", { RMeBP } },
2195 { "bswap", { RMeSI } },
2196 { "bswap", { RMeDI } },
2198 { PREFIX_TABLE (PREFIX_0FD0) },
2199 { "psrlw", { MX, EM } },
2200 { "psrld", { MX, EM } },
2201 { "psrlq", { MX, EM } },
2202 { "paddq", { MX, EM } },
2203 { "pmullw", { MX, EM } },
2204 { PREFIX_TABLE (PREFIX_0FD6) },
2205 { MOD_TABLE (MOD_0FD7) },
2207 { "psubusb", { MX, EM } },
2208 { "psubusw", { MX, EM } },
2209 { "pminub", { MX, EM } },
2210 { "pand", { MX, EM } },
2211 { "paddusb", { MX, EM } },
2212 { "paddusw", { MX, EM } },
2213 { "pmaxub", { MX, EM } },
2214 { "pandn", { MX, EM } },
2216 { "pavgb", { MX, EM } },
2217 { "psraw", { MX, EM } },
2218 { "psrad", { MX, EM } },
2219 { "pavgw", { MX, EM } },
2220 { "pmulhuw", { MX, EM } },
2221 { "pmulhw", { MX, EM } },
2222 { PREFIX_TABLE (PREFIX_0FE6) },
2223 { PREFIX_TABLE (PREFIX_0FE7) },
2225 { "psubsb", { MX, EM } },
2226 { "psubsw", { MX, EM } },
2227 { "pminsw", { MX, EM } },
2228 { "por", { MX, EM } },
2229 { "paddsb", { MX, EM } },
2230 { "paddsw", { MX, EM } },
2231 { "pmaxsw", { MX, EM } },
2232 { "pxor", { MX, EM } },
2234 { PREFIX_TABLE (PREFIX_0FF0) },
2235 { "psllw", { MX, EM } },
2236 { "pslld", { MX, EM } },
2237 { "psllq", { MX, EM } },
2238 { "pmuludq", { MX, EM } },
2239 { "pmaddwd", { MX, EM } },
2240 { "psadbw", { MX, EM } },
2241 { PREFIX_TABLE (PREFIX_0FF7) },
2243 { "psubb", { MX, EM } },
2244 { "psubw", { MX, EM } },
2245 { "psubd", { MX, EM } },
2246 { "psubq", { MX, EM } },
2247 { "paddb", { MX, EM } },
2248 { "paddw", { MX, EM } },
2249 { "paddd", { MX, EM } },
2253 static const unsigned char onebyte_has_modrm[256] = {
2254 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2255 /* ------------------------------- */
2256 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2257 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2258 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2259 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2260 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2261 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2262 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2263 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2264 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2265 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2266 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2267 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2268 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2269 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2270 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2271 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2272 /* ------------------------------- */
2273 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2276 static const unsigned char twobyte_has_modrm[256] = {
2277 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2278 /* ------------------------------- */
2279 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2280 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2281 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2282 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2283 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2284 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2285 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2286 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2287 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2288 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2289 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2290 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2291 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2292 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2293 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2294 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
2295 /* ------------------------------- */
2296 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2299 static char obuf[100];
2301 static char *mnemonicendp;
2302 static char scratchbuf[100];
2303 static unsigned char *start_codep;
2304 static unsigned char *insn_codep;
2305 static unsigned char *codep;
2306 static int last_lock_prefix;
2307 static int last_repz_prefix;
2308 static int last_repnz_prefix;
2309 static int last_data_prefix;
2310 static int last_addr_prefix;
2311 static int last_rex_prefix;
2312 static int last_seg_prefix;
2313 #define MAX_CODE_LENGTH 15
2314 /* We can up to 14 prefixes since the maximum instruction length is
2316 static int all_prefixes[MAX_CODE_LENGTH - 1];
2317 static disassemble_info *the_info;
2325 static unsigned char need_modrm;
2335 int register_specifier;
2341 static unsigned char need_vex;
2342 static unsigned char need_vex_reg;
2343 static unsigned char vex_w_done;
2351 /* If we are accessing mod/rm/reg without need_modrm set, then the
2352 values are stale. Hitting this abort likely indicates that you
2353 need to update onebyte_has_modrm or twobyte_has_modrm. */
2354 #define MODRM_CHECK if (!need_modrm) abort ()
2356 static const char **names64;
2357 static const char **names32;
2358 static const char **names16;
2359 static const char **names8;
2360 static const char **names8rex;
2361 static const char **names_seg;
2362 static const char *index64;
2363 static const char *index32;
2364 static const char **index16;
2366 static const char *intel_names64[] = {
2367 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2368 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2370 static const char *intel_names32[] = {
2371 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2372 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2374 static const char *intel_names16[] = {
2375 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2376 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2378 static const char *intel_names8[] = {
2379 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2381 static const char *intel_names8rex[] = {
2382 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2383 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2385 static const char *intel_names_seg[] = {
2386 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2388 static const char *intel_index64 = "riz";
2389 static const char *intel_index32 = "eiz";
2390 static const char *intel_index16[] = {
2391 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2394 static const char *att_names64[] = {
2395 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2396 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2398 static const char *att_names32[] = {
2399 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2400 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2402 static const char *att_names16[] = {
2403 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2404 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2406 static const char *att_names8[] = {
2407 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2409 static const char *att_names8rex[] = {
2410 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2411 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2413 static const char *att_names_seg[] = {
2414 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2416 static const char *att_index64 = "%riz";
2417 static const char *att_index32 = "%eiz";
2418 static const char *att_index16[] = {
2419 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2422 static const char **names_mm;
2423 static const char *intel_names_mm[] = {
2424 "mm0", "mm1", "mm2", "mm3",
2425 "mm4", "mm5", "mm6", "mm7"
2427 static const char *att_names_mm[] = {
2428 "%mm0", "%mm1", "%mm2", "%mm3",
2429 "%mm4", "%mm5", "%mm6", "%mm7"
2432 static const char **names_xmm;
2433 static const char *intel_names_xmm[] = {
2434 "xmm0", "xmm1", "xmm2", "xmm3",
2435 "xmm4", "xmm5", "xmm6", "xmm7",
2436 "xmm8", "xmm9", "xmm10", "xmm11",
2437 "xmm12", "xmm13", "xmm14", "xmm15"
2439 static const char *att_names_xmm[] = {
2440 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2441 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2442 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2443 "%xmm12", "%xmm13", "%xmm14", "%xmm15"
2446 static const char **names_ymm;
2447 static const char *intel_names_ymm[] = {
2448 "ymm0", "ymm1", "ymm2", "ymm3",
2449 "ymm4", "ymm5", "ymm6", "ymm7",
2450 "ymm8", "ymm9", "ymm10", "ymm11",
2451 "ymm12", "ymm13", "ymm14", "ymm15"
2453 static const char *att_names_ymm[] = {
2454 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2455 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2456 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2457 "%ymm12", "%ymm13", "%ymm14", "%ymm15"
2460 static const struct dis386 reg_table[][8] = {
2463 { "addA", { Ebh1, Ib } },
2464 { "orA", { Ebh1, Ib } },
2465 { "adcA", { Ebh1, Ib } },
2466 { "sbbA", { Ebh1, Ib } },
2467 { "andA", { Ebh1, Ib } },
2468 { "subA", { Ebh1, Ib } },
2469 { "xorA", { Ebh1, Ib } },
2470 { "cmpA", { Eb, Ib } },
2474 { "addQ", { Evh1, Iv } },
2475 { "orQ", { Evh1, Iv } },
2476 { "adcQ", { Evh1, Iv } },
2477 { "sbbQ", { Evh1, Iv } },
2478 { "andQ", { Evh1, Iv } },
2479 { "subQ", { Evh1, Iv } },
2480 { "xorQ", { Evh1, Iv } },
2481 { "cmpQ", { Ev, Iv } },
2485 { "addQ", { Evh1, sIb } },
2486 { "orQ", { Evh1, sIb } },
2487 { "adcQ", { Evh1, sIb } },
2488 { "sbbQ", { Evh1, sIb } },
2489 { "andQ", { Evh1, sIb } },
2490 { "subQ", { Evh1, sIb } },
2491 { "xorQ", { Evh1, sIb } },
2492 { "cmpQ", { Ev, sIb } },
2496 { "popU", { stackEv } },
2497 { XOP_8F_TABLE (XOP_09) },
2501 { XOP_8F_TABLE (XOP_09) },
2505 { "rolA", { Eb, Ib } },
2506 { "rorA", { Eb, Ib } },
2507 { "rclA", { Eb, Ib } },
2508 { "rcrA", { Eb, Ib } },
2509 { "shlA", { Eb, Ib } },
2510 { "shrA", { Eb, Ib } },
2512 { "sarA", { Eb, Ib } },
2516 { "rolQ", { Ev, Ib } },
2517 { "rorQ", { Ev, Ib } },
2518 { "rclQ", { Ev, Ib } },
2519 { "rcrQ", { Ev, Ib } },
2520 { "shlQ", { Ev, Ib } },
2521 { "shrQ", { Ev, Ib } },
2523 { "sarQ", { Ev, Ib } },
2527 { "movA", { Ebh3, Ib } },
2534 { MOD_TABLE (MOD_C6_REG_7) },
2538 { "movQ", { Evh3, Iv } },
2545 { MOD_TABLE (MOD_C7_REG_7) },
2549 { "rolA", { Eb, I1 } },
2550 { "rorA", { Eb, I1 } },
2551 { "rclA", { Eb, I1 } },
2552 { "rcrA", { Eb, I1 } },
2553 { "shlA", { Eb, I1 } },
2554 { "shrA", { Eb, I1 } },
2556 { "sarA", { Eb, I1 } },
2560 { "rolQ", { Ev, I1 } },
2561 { "rorQ", { Ev, I1 } },
2562 { "rclQ", { Ev, I1 } },
2563 { "rcrQ", { Ev, I1 } },
2564 { "shlQ", { Ev, I1 } },
2565 { "shrQ", { Ev, I1 } },
2567 { "sarQ", { Ev, I1 } },
2571 { "rolA", { Eb, CL } },
2572 { "rorA", { Eb, CL } },
2573 { "rclA", { Eb, CL } },
2574 { "rcrA", { Eb, CL } },
2575 { "shlA", { Eb, CL } },
2576 { "shrA", { Eb, CL } },
2578 { "sarA", { Eb, CL } },
2582 { "rolQ", { Ev, CL } },
2583 { "rorQ", { Ev, CL } },
2584 { "rclQ", { Ev, CL } },
2585 { "rcrQ", { Ev, CL } },
2586 { "shlQ", { Ev, CL } },
2587 { "shrQ", { Ev, CL } },
2589 { "sarQ", { Ev, CL } },
2593 { "testA", { Eb, Ib } },
2595 { "notA", { Ebh1 } },
2596 { "negA", { Ebh1 } },
2597 { "mulA", { Eb } }, /* Don't print the implicit %al register, */
2598 { "imulA", { Eb } }, /* to distinguish these opcodes from other */
2599 { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */
2600 { "idivA", { Eb } }, /* and idiv for consistency. */
2604 { "testQ", { Ev, Iv } },
2606 { "notQ", { Evh1 } },
2607 { "negQ", { Evh1 } },
2608 { "mulQ", { Ev } }, /* Don't print the implicit register. */
2609 { "imulQ", { Ev } },
2611 { "idivQ", { Ev } },
2615 { "incA", { Ebh1 } },
2616 { "decA", { Ebh1 } },
2620 { "incQ", { Evh1 } },
2621 { "decQ", { Evh1 } },
2622 { "call{T|}", { indirEv } },
2623 { "Jcall{T|}", { indirEp } },
2624 { "jmp{T|}", { indirEv } },
2625 { "Jjmp{T|}", { indirEp } },
2626 { "pushU", { stackEv } },
2631 { "sldtD", { Sv } },
2642 { MOD_TABLE (MOD_0F01_REG_0) },
2643 { MOD_TABLE (MOD_0F01_REG_1) },
2644 { MOD_TABLE (MOD_0F01_REG_2) },
2645 { MOD_TABLE (MOD_0F01_REG_3) },
2646 { "smswD", { Sv } },
2649 { MOD_TABLE (MOD_0F01_REG_7) },
2653 { "prefetch", { Mb } },
2654 { "prefetchw", { Mb } },
2658 { MOD_TABLE (MOD_0F18_REG_0) },
2659 { MOD_TABLE (MOD_0F18_REG_1) },
2660 { MOD_TABLE (MOD_0F18_REG_2) },
2661 { MOD_TABLE (MOD_0F18_REG_3) },
2667 { MOD_TABLE (MOD_0F71_REG_2) },
2669 { MOD_TABLE (MOD_0F71_REG_4) },
2671 { MOD_TABLE (MOD_0F71_REG_6) },
2677 { MOD_TABLE (MOD_0F72_REG_2) },
2679 { MOD_TABLE (MOD_0F72_REG_4) },
2681 { MOD_TABLE (MOD_0F72_REG_6) },
2687 { MOD_TABLE (MOD_0F73_REG_2) },
2688 { MOD_TABLE (MOD_0F73_REG_3) },
2691 { MOD_TABLE (MOD_0F73_REG_6) },
2692 { MOD_TABLE (MOD_0F73_REG_7) },
2696 { "montmul", { { OP_0f07, 0 } } },
2697 { "xsha1", { { OP_0f07, 0 } } },
2698 { "xsha256", { { OP_0f07, 0 } } },
2702 { "xstore-rng", { { OP_0f07, 0 } } },
2703 { "xcrypt-ecb", { { OP_0f07, 0 } } },
2704 { "xcrypt-cbc", { { OP_0f07, 0 } } },
2705 { "xcrypt-ctr", { { OP_0f07, 0 } } },
2706 { "xcrypt-cfb", { { OP_0f07, 0 } } },
2707 { "xcrypt-ofb", { { OP_0f07, 0 } } },
2711 { MOD_TABLE (MOD_0FAE_REG_0) },
2712 { MOD_TABLE (MOD_0FAE_REG_1) },
2713 { MOD_TABLE (MOD_0FAE_REG_2) },
2714 { MOD_TABLE (MOD_0FAE_REG_3) },
2715 { MOD_TABLE (MOD_0FAE_REG_4) },
2716 { MOD_TABLE (MOD_0FAE_REG_5) },
2717 { MOD_TABLE (MOD_0FAE_REG_6) },
2718 { MOD_TABLE (MOD_0FAE_REG_7) },
2726 { "btQ", { Ev, Ib } },
2727 { "btsQ", { Evh1, Ib } },
2728 { "btrQ", { Evh1, Ib } },
2729 { "btcQ", { Evh1, Ib } },
2734 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
2739 { MOD_TABLE (MOD_0FC7_REG_6) },
2740 { MOD_TABLE (MOD_0FC7_REG_7) },
2746 { MOD_TABLE (MOD_VEX_0F71_REG_2) },
2748 { MOD_TABLE (MOD_VEX_0F71_REG_4) },
2750 { MOD_TABLE (MOD_VEX_0F71_REG_6) },
2756 { MOD_TABLE (MOD_VEX_0F72_REG_2) },
2758 { MOD_TABLE (MOD_VEX_0F72_REG_4) },
2760 { MOD_TABLE (MOD_VEX_0F72_REG_6) },
2766 { MOD_TABLE (MOD_VEX_0F73_REG_2) },
2767 { MOD_TABLE (MOD_VEX_0F73_REG_3) },
2770 { MOD_TABLE (MOD_VEX_0F73_REG_6) },
2771 { MOD_TABLE (MOD_VEX_0F73_REG_7) },
2777 { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
2778 { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
2780 /* REG_VEX_0F38F3 */
2783 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
2784 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
2785 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
2789 { "llwpcb", { { OP_LWPCB_E, 0 } } },
2790 { "slwpcb", { { OP_LWPCB_E, 0 } } },
2794 { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
2795 { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } },
2797 /* REG_XOP_TBM_01 */
2800 { "blcfill", { { OP_LWP_E, 0 }, Ev } },
2801 { "blsfill", { { OP_LWP_E, 0 }, Ev } },
2802 { "blcs", { { OP_LWP_E, 0 }, Ev } },
2803 { "tzmsk", { { OP_LWP_E, 0 }, Ev } },
2804 { "blcic", { { OP_LWP_E, 0 }, Ev } },
2805 { "blsic", { { OP_LWP_E, 0 }, Ev } },
2806 { "t1mskc", { { OP_LWP_E, 0 }, Ev } },
2808 /* REG_XOP_TBM_02 */
2811 { "blcmsk", { { OP_LWP_E, 0 }, Ev } },
2816 { "blci", { { OP_LWP_E, 0 }, Ev } },
2820 static const struct dis386 prefix_table[][4] = {
2823 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2824 { "pause", { XX } },
2825 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2830 { "movups", { XM, EXx } },
2831 { "movss", { XM, EXd } },
2832 { "movupd", { XM, EXx } },
2833 { "movsd", { XM, EXq } },
2838 { "movups", { EXxS, XM } },
2839 { "movss", { EXdS, XM } },
2840 { "movupd", { EXxS, XM } },
2841 { "movsd", { EXqS, XM } },
2846 { MOD_TABLE (MOD_0F12_PREFIX_0) },
2847 { "movsldup", { XM, EXx } },
2848 { "movlpd", { XM, EXq } },
2849 { "movddup", { XM, EXq } },
2854 { MOD_TABLE (MOD_0F16_PREFIX_0) },
2855 { "movshdup", { XM, EXx } },
2856 { "movhpd", { XM, EXq } },
2861 { "cvtpi2ps", { XM, EMCq } },
2862 { "cvtsi2ss%LQ", { XM, Ev } },
2863 { "cvtpi2pd", { XM, EMCq } },
2864 { "cvtsi2sd%LQ", { XM, Ev } },
2869 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2870 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2871 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2872 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
2877 { "cvttps2pi", { MXC, EXq } },
2878 { "cvttss2siY", { Gv, EXd } },
2879 { "cvttpd2pi", { MXC, EXx } },
2880 { "cvttsd2siY", { Gv, EXq } },
2885 { "cvtps2pi", { MXC, EXq } },
2886 { "cvtss2siY", { Gv, EXd } },
2887 { "cvtpd2pi", { MXC, EXx } },
2888 { "cvtsd2siY", { Gv, EXq } },
2893 { "ucomiss",{ XM, EXd } },
2895 { "ucomisd",{ XM, EXq } },
2900 { "comiss", { XM, EXd } },
2902 { "comisd", { XM, EXq } },
2907 { "sqrtps", { XM, EXx } },
2908 { "sqrtss", { XM, EXd } },
2909 { "sqrtpd", { XM, EXx } },
2910 { "sqrtsd", { XM, EXq } },
2915 { "rsqrtps",{ XM, EXx } },
2916 { "rsqrtss",{ XM, EXd } },
2921 { "rcpps", { XM, EXx } },
2922 { "rcpss", { XM, EXd } },
2927 { "addps", { XM, EXx } },
2928 { "addss", { XM, EXd } },
2929 { "addpd", { XM, EXx } },
2930 { "addsd", { XM, EXq } },
2935 { "mulps", { XM, EXx } },
2936 { "mulss", { XM, EXd } },
2937 { "mulpd", { XM, EXx } },
2938 { "mulsd", { XM, EXq } },
2943 { "cvtps2pd", { XM, EXq } },
2944 { "cvtss2sd", { XM, EXd } },
2945 { "cvtpd2ps", { XM, EXx } },
2946 { "cvtsd2ss", { XM, EXq } },
2951 { "cvtdq2ps", { XM, EXx } },
2952 { "cvttps2dq", { XM, EXx } },
2953 { "cvtps2dq", { XM, EXx } },
2958 { "subps", { XM, EXx } },
2959 { "subss", { XM, EXd } },
2960 { "subpd", { XM, EXx } },
2961 { "subsd", { XM, EXq } },
2966 { "minps", { XM, EXx } },
2967 { "minss", { XM, EXd } },
2968 { "minpd", { XM, EXx } },
2969 { "minsd", { XM, EXq } },
2974 { "divps", { XM, EXx } },
2975 { "divss", { XM, EXd } },
2976 { "divpd", { XM, EXx } },
2977 { "divsd", { XM, EXq } },
2982 { "maxps", { XM, EXx } },
2983 { "maxss", { XM, EXd } },
2984 { "maxpd", { XM, EXx } },
2985 { "maxsd", { XM, EXq } },
2990 { "punpcklbw",{ MX, EMd } },
2992 { "punpcklbw",{ MX, EMx } },
2997 { "punpcklwd",{ MX, EMd } },
2999 { "punpcklwd",{ MX, EMx } },
3004 { "punpckldq",{ MX, EMd } },
3006 { "punpckldq",{ MX, EMx } },
3013 { "punpcklqdq", { XM, EXx } },
3020 { "punpckhqdq", { XM, EXx } },
3025 { "movq", { MX, EM } },
3026 { "movdqu", { XM, EXx } },
3027 { "movdqa", { XM, EXx } },
3032 { "pshufw", { MX, EM, Ib } },
3033 { "pshufhw",{ XM, EXx, Ib } },
3034 { "pshufd", { XM, EXx, Ib } },
3035 { "pshuflw",{ XM, EXx, Ib } },
3038 /* PREFIX_0F73_REG_3 */
3042 { "psrldq", { XS, Ib } },
3045 /* PREFIX_0F73_REG_7 */
3049 { "pslldq", { XS, Ib } },
3054 {"vmread", { Em, Gm } },
3056 {"extrq", { XS, Ib, Ib } },
3057 {"insertq", { XM, XS, Ib, Ib } },
3062 {"vmwrite", { Gm, Em } },
3064 {"extrq", { XM, XS } },
3065 {"insertq", { XM, XS } },
3072 { "haddpd", { XM, EXx } },
3073 { "haddps", { XM, EXx } },
3080 { "hsubpd", { XM, EXx } },
3081 { "hsubps", { XM, EXx } },
3086 { "movK", { Edq, MX } },
3087 { "movq", { XM, EXq } },
3088 { "movK", { Edq, XM } },
3093 { "movq", { EMS, MX } },
3094 { "movdqu", { EXxS, XM } },
3095 { "movdqa", { EXxS, XM } },
3098 /* PREFIX_0FAE_REG_0 */
3101 { "rdfsbase", { Ev } },
3104 /* PREFIX_0FAE_REG_1 */
3107 { "rdgsbase", { Ev } },
3110 /* PREFIX_0FAE_REG_2 */
3113 { "wrfsbase", { Ev } },
3116 /* PREFIX_0FAE_REG_3 */
3119 { "wrgsbase", { Ev } },
3125 { "popcntS", { Gv, Ev } },
3130 { "bsfS", { Gv, Ev } },
3131 { "tzcntS", { Gv, Ev } },
3132 { "bsfS", { Gv, Ev } },
3137 { "bsrS", { Gv, Ev } },
3138 { "lzcntS", { Gv, Ev } },
3139 { "bsrS", { Gv, Ev } },
3144 { "cmpps", { XM, EXx, CMP } },
3145 { "cmpss", { XM, EXd, CMP } },
3146 { "cmppd", { XM, EXx, CMP } },
3147 { "cmpsd", { XM, EXq, CMP } },
3152 { "movntiS", { Ma, Gv } },
3155 /* PREFIX_0FC7_REG_6 */
3157 { "vmptrld",{ Mq } },
3158 { "vmxon", { Mq } },
3159 { "vmclear",{ Mq } },
3166 { "addsubpd", { XM, EXx } },
3167 { "addsubps", { XM, EXx } },
3173 { "movq2dq",{ XM, MS } },
3174 { "movq", { EXqS, XM } },
3175 { "movdq2q",{ MX, XS } },
3181 { "cvtdq2pd", { XM, EXq } },
3182 { "cvttpd2dq", { XM, EXx } },
3183 { "cvtpd2dq", { XM, EXx } },
3188 { "movntq", { Mq, MX } },
3190 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3198 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3203 { "maskmovq", { MX, MS } },
3205 { "maskmovdqu", { XM, XS } },
3212 { "pblendvb", { XM, EXx, XMM0 } },
3219 { "blendvps", { XM, EXx, XMM0 } },
3226 { "blendvpd", { XM, EXx, XMM0 } },
3233 { "ptest", { XM, EXx } },
3240 { "pmovsxbw", { XM, EXq } },
3247 { "pmovsxbd", { XM, EXd } },
3254 { "pmovsxbq", { XM, EXw } },
3261 { "pmovsxwd", { XM, EXq } },
3268 { "pmovsxwq", { XM, EXd } },
3275 { "pmovsxdq", { XM, EXq } },
3282 { "pmuldq", { XM, EXx } },
3289 { "pcmpeqq", { XM, EXx } },
3296 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
3303 { "packusdw", { XM, EXx } },
3310 { "pmovzxbw", { XM, EXq } },
3317 { "pmovzxbd", { XM, EXd } },
3324 { "pmovzxbq", { XM, EXw } },
3331 { "pmovzxwd", { XM, EXq } },
3338 { "pmovzxwq", { XM, EXd } },
3345 { "pmovzxdq", { XM, EXq } },
3352 { "pcmpgtq", { XM, EXx } },
3359 { "pminsb", { XM, EXx } },
3366 { "pminsd", { XM, EXx } },
3373 { "pminuw", { XM, EXx } },
3380 { "pminud", { XM, EXx } },
3387 { "pmaxsb", { XM, EXx } },
3394 { "pmaxsd", { XM, EXx } },
3401 { "pmaxuw", { XM, EXx } },
3408 { "pmaxud", { XM, EXx } },
3415 { "pmulld", { XM, EXx } },
3422 { "phminposuw", { XM, EXx } },
3429 { "invept", { Gm, Mo } },
3436 { "invvpid", { Gm, Mo } },
3443 { "invpcid", { Gm, M } },
3450 { "aesimc", { XM, EXx } },
3457 { "aesenc", { XM, EXx } },
3464 { "aesenclast", { XM, EXx } },
3471 { "aesdec", { XM, EXx } },
3478 { "aesdeclast", { XM, EXx } },
3483 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3485 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3486 { "crc32", { Gdq, { CRC32_Fixup, b_mode } } },
3491 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3493 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3494 { "crc32", { Gdq, { CRC32_Fixup, v_mode } } },
3500 { "adoxS", { Gdq, Edq} },
3501 { "adcxS", { Gdq, Edq} },
3509 { "roundps", { XM, EXx, Ib } },
3516 { "roundpd", { XM, EXx, Ib } },
3523 { "roundss", { XM, EXd, Ib } },
3530 { "roundsd", { XM, EXq, Ib } },
3537 { "blendps", { XM, EXx, Ib } },
3544 { "blendpd", { XM, EXx, Ib } },
3551 { "pblendw", { XM, EXx, Ib } },
3558 { "pextrb", { Edqb, XM, Ib } },
3565 { "pextrw", { Edqw, XM, Ib } },
3572 { "pextrK", { Edq, XM, Ib } },
3579 { "extractps", { Edqd, XM, Ib } },
3586 { "pinsrb", { XM, Edqb, Ib } },
3593 { "insertps", { XM, EXd, Ib } },
3600 { "pinsrK", { XM, Edq, Ib } },
3607 { "dpps", { XM, EXx, Ib } },
3614 { "dppd", { XM, EXx, Ib } },
3621 { "mpsadbw", { XM, EXx, Ib } },
3628 { "pclmulqdq", { XM, EXx, PCLMUL } },
3635 { "pcmpestrm", { XM, EXx, Ib } },
3642 { "pcmpestri", { XM, EXx, Ib } },
3649 { "pcmpistrm", { XM, EXx, Ib } },
3656 { "pcmpistri", { XM, EXx, Ib } },
3663 { "aeskeygenassist", { XM, EXx, Ib } },
3666 /* PREFIX_VEX_0F10 */
3668 { VEX_W_TABLE (VEX_W_0F10_P_0) },
3669 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
3670 { VEX_W_TABLE (VEX_W_0F10_P_2) },
3671 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
3674 /* PREFIX_VEX_0F11 */
3676 { VEX_W_TABLE (VEX_W_0F11_P_0) },
3677 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
3678 { VEX_W_TABLE (VEX_W_0F11_P_2) },
3679 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
3682 /* PREFIX_VEX_0F12 */
3684 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
3685 { VEX_W_TABLE (VEX_W_0F12_P_1) },
3686 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
3687 { VEX_W_TABLE (VEX_W_0F12_P_3) },
3690 /* PREFIX_VEX_0F16 */
3692 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
3693 { VEX_W_TABLE (VEX_W_0F16_P_1) },
3694 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
3697 /* PREFIX_VEX_0F2A */
3700 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
3702 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
3705 /* PREFIX_VEX_0F2C */
3708 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
3710 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
3713 /* PREFIX_VEX_0F2D */
3716 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
3718 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
3721 /* PREFIX_VEX_0F2E */
3723 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
3725 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
3728 /* PREFIX_VEX_0F2F */
3730 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
3732 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
3735 /* PREFIX_VEX_0F51 */
3737 { VEX_W_TABLE (VEX_W_0F51_P_0) },
3738 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
3739 { VEX_W_TABLE (VEX_W_0F51_P_2) },
3740 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
3743 /* PREFIX_VEX_0F52 */
3745 { VEX_W_TABLE (VEX_W_0F52_P_0) },
3746 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
3749 /* PREFIX_VEX_0F53 */
3751 { VEX_W_TABLE (VEX_W_0F53_P_0) },
3752 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
3755 /* PREFIX_VEX_0F58 */
3757 { VEX_W_TABLE (VEX_W_0F58_P_0) },
3758 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
3759 { VEX_W_TABLE (VEX_W_0F58_P_2) },
3760 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
3763 /* PREFIX_VEX_0F59 */
3765 { VEX_W_TABLE (VEX_W_0F59_P_0) },
3766 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
3767 { VEX_W_TABLE (VEX_W_0F59_P_2) },
3768 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
3771 /* PREFIX_VEX_0F5A */
3773 { VEX_W_TABLE (VEX_W_0F5A_P_0) },
3774 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
3775 { "vcvtpd2ps%XY", { XMM, EXx } },
3776 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
3779 /* PREFIX_VEX_0F5B */
3781 { VEX_W_TABLE (VEX_W_0F5B_P_0) },
3782 { VEX_W_TABLE (VEX_W_0F5B_P_1) },
3783 { VEX_W_TABLE (VEX_W_0F5B_P_2) },
3786 /* PREFIX_VEX_0F5C */
3788 { VEX_W_TABLE (VEX_W_0F5C_P_0) },
3789 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
3790 { VEX_W_TABLE (VEX_W_0F5C_P_2) },
3791 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
3794 /* PREFIX_VEX_0F5D */
3796 { VEX_W_TABLE (VEX_W_0F5D_P_0) },
3797 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
3798 { VEX_W_TABLE (VEX_W_0F5D_P_2) },
3799 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
3802 /* PREFIX_VEX_0F5E */
3804 { VEX_W_TABLE (VEX_W_0F5E_P_0) },
3805 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
3806 { VEX_W_TABLE (VEX_W_0F5E_P_2) },
3807 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
3810 /* PREFIX_VEX_0F5F */
3812 { VEX_W_TABLE (VEX_W_0F5F_P_0) },
3813 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
3814 { VEX_W_TABLE (VEX_W_0F5F_P_2) },
3815 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
3818 /* PREFIX_VEX_0F60 */
3822 { VEX_W_TABLE (VEX_W_0F60_P_2) },
3825 /* PREFIX_VEX_0F61 */
3829 { VEX_W_TABLE (VEX_W_0F61_P_2) },
3832 /* PREFIX_VEX_0F62 */
3836 { VEX_W_TABLE (VEX_W_0F62_P_2) },
3839 /* PREFIX_VEX_0F63 */
3843 { VEX_W_TABLE (VEX_W_0F63_P_2) },
3846 /* PREFIX_VEX_0F64 */
3850 { VEX_W_TABLE (VEX_W_0F64_P_2) },
3853 /* PREFIX_VEX_0F65 */
3857 { VEX_W_TABLE (VEX_W_0F65_P_2) },
3860 /* PREFIX_VEX_0F66 */
3864 { VEX_W_TABLE (VEX_W_0F66_P_2) },
3867 /* PREFIX_VEX_0F67 */
3871 { VEX_W_TABLE (VEX_W_0F67_P_2) },
3874 /* PREFIX_VEX_0F68 */
3878 { VEX_W_TABLE (VEX_W_0F68_P_2) },
3881 /* PREFIX_VEX_0F69 */
3885 { VEX_W_TABLE (VEX_W_0F69_P_2) },
3888 /* PREFIX_VEX_0F6A */
3892 { VEX_W_TABLE (VEX_W_0F6A_P_2) },
3895 /* PREFIX_VEX_0F6B */
3899 { VEX_W_TABLE (VEX_W_0F6B_P_2) },
3902 /* PREFIX_VEX_0F6C */
3906 { VEX_W_TABLE (VEX_W_0F6C_P_2) },
3909 /* PREFIX_VEX_0F6D */
3913 { VEX_W_TABLE (VEX_W_0F6D_P_2) },
3916 /* PREFIX_VEX_0F6E */
3920 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
3923 /* PREFIX_VEX_0F6F */
3926 { VEX_W_TABLE (VEX_W_0F6F_P_1) },
3927 { VEX_W_TABLE (VEX_W_0F6F_P_2) },
3930 /* PREFIX_VEX_0F70 */
3933 { VEX_W_TABLE (VEX_W_0F70_P_1) },
3934 { VEX_W_TABLE (VEX_W_0F70_P_2) },
3935 { VEX_W_TABLE (VEX_W_0F70_P_3) },
3938 /* PREFIX_VEX_0F71_REG_2 */
3942 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
3945 /* PREFIX_VEX_0F71_REG_4 */
3949 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
3952 /* PREFIX_VEX_0F71_REG_6 */
3956 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
3959 /* PREFIX_VEX_0F72_REG_2 */
3963 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
3966 /* PREFIX_VEX_0F72_REG_4 */
3970 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
3973 /* PREFIX_VEX_0F72_REG_6 */
3977 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
3980 /* PREFIX_VEX_0F73_REG_2 */
3984 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
3987 /* PREFIX_VEX_0F73_REG_3 */
3991 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
3994 /* PREFIX_VEX_0F73_REG_6 */
3998 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
4001 /* PREFIX_VEX_0F73_REG_7 */
4005 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
4008 /* PREFIX_VEX_0F74 */
4012 { VEX_W_TABLE (VEX_W_0F74_P_2) },
4015 /* PREFIX_VEX_0F75 */
4019 { VEX_W_TABLE (VEX_W_0F75_P_2) },
4022 /* PREFIX_VEX_0F76 */
4026 { VEX_W_TABLE (VEX_W_0F76_P_2) },
4029 /* PREFIX_VEX_0F77 */
4031 { VEX_W_TABLE (VEX_W_0F77_P_0) },
4034 /* PREFIX_VEX_0F7C */
4038 { VEX_W_TABLE (VEX_W_0F7C_P_2) },
4039 { VEX_W_TABLE (VEX_W_0F7C_P_3) },
4042 /* PREFIX_VEX_0F7D */
4046 { VEX_W_TABLE (VEX_W_0F7D_P_2) },
4047 { VEX_W_TABLE (VEX_W_0F7D_P_3) },
4050 /* PREFIX_VEX_0F7E */
4053 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
4054 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
4057 /* PREFIX_VEX_0F7F */
4060 { VEX_W_TABLE (VEX_W_0F7F_P_1) },
4061 { VEX_W_TABLE (VEX_W_0F7F_P_2) },
4064 /* PREFIX_VEX_0FC2 */
4066 { VEX_W_TABLE (VEX_W_0FC2_P_0) },
4067 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
4068 { VEX_W_TABLE (VEX_W_0FC2_P_2) },
4069 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
4072 /* PREFIX_VEX_0FC4 */
4076 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
4079 /* PREFIX_VEX_0FC5 */
4083 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
4086 /* PREFIX_VEX_0FD0 */
4090 { VEX_W_TABLE (VEX_W_0FD0_P_2) },
4091 { VEX_W_TABLE (VEX_W_0FD0_P_3) },
4094 /* PREFIX_VEX_0FD1 */
4098 { VEX_W_TABLE (VEX_W_0FD1_P_2) },
4101 /* PREFIX_VEX_0FD2 */
4105 { VEX_W_TABLE (VEX_W_0FD2_P_2) },
4108 /* PREFIX_VEX_0FD3 */
4112 { VEX_W_TABLE (VEX_W_0FD3_P_2) },
4115 /* PREFIX_VEX_0FD4 */
4119 { VEX_W_TABLE (VEX_W_0FD4_P_2) },
4122 /* PREFIX_VEX_0FD5 */
4126 { VEX_W_TABLE (VEX_W_0FD5_P_2) },
4129 /* PREFIX_VEX_0FD6 */
4133 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
4136 /* PREFIX_VEX_0FD7 */
4140 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
4143 /* PREFIX_VEX_0FD8 */
4147 { VEX_W_TABLE (VEX_W_0FD8_P_2) },
4150 /* PREFIX_VEX_0FD9 */
4154 { VEX_W_TABLE (VEX_W_0FD9_P_2) },
4157 /* PREFIX_VEX_0FDA */
4161 { VEX_W_TABLE (VEX_W_0FDA_P_2) },
4164 /* PREFIX_VEX_0FDB */
4168 { VEX_W_TABLE (VEX_W_0FDB_P_2) },
4171 /* PREFIX_VEX_0FDC */
4175 { VEX_W_TABLE (VEX_W_0FDC_P_2) },
4178 /* PREFIX_VEX_0FDD */
4182 { VEX_W_TABLE (VEX_W_0FDD_P_2) },
4185 /* PREFIX_VEX_0FDE */
4189 { VEX_W_TABLE (VEX_W_0FDE_P_2) },
4192 /* PREFIX_VEX_0FDF */
4196 { VEX_W_TABLE (VEX_W_0FDF_P_2) },
4199 /* PREFIX_VEX_0FE0 */
4203 { VEX_W_TABLE (VEX_W_0FE0_P_2) },
4206 /* PREFIX_VEX_0FE1 */
4210 { VEX_W_TABLE (VEX_W_0FE1_P_2) },
4213 /* PREFIX_VEX_0FE2 */
4217 { VEX_W_TABLE (VEX_W_0FE2_P_2) },
4220 /* PREFIX_VEX_0FE3 */
4224 { VEX_W_TABLE (VEX_W_0FE3_P_2) },
4227 /* PREFIX_VEX_0FE4 */
4231 { VEX_W_TABLE (VEX_W_0FE4_P_2) },
4234 /* PREFIX_VEX_0FE5 */
4238 { VEX_W_TABLE (VEX_W_0FE5_P_2) },
4241 /* PREFIX_VEX_0FE6 */
4244 { VEX_W_TABLE (VEX_W_0FE6_P_1) },
4245 { VEX_W_TABLE (VEX_W_0FE6_P_2) },
4246 { VEX_W_TABLE (VEX_W_0FE6_P_3) },
4249 /* PREFIX_VEX_0FE7 */
4253 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
4256 /* PREFIX_VEX_0FE8 */
4260 { VEX_W_TABLE (VEX_W_0FE8_P_2) },
4263 /* PREFIX_VEX_0FE9 */
4267 { VEX_W_TABLE (VEX_W_0FE9_P_2) },
4270 /* PREFIX_VEX_0FEA */
4274 { VEX_W_TABLE (VEX_W_0FEA_P_2) },
4277 /* PREFIX_VEX_0FEB */
4281 { VEX_W_TABLE (VEX_W_0FEB_P_2) },
4284 /* PREFIX_VEX_0FEC */
4288 { VEX_W_TABLE (VEX_W_0FEC_P_2) },
4291 /* PREFIX_VEX_0FED */
4295 { VEX_W_TABLE (VEX_W_0FED_P_2) },
4298 /* PREFIX_VEX_0FEE */
4302 { VEX_W_TABLE (VEX_W_0FEE_P_2) },
4305 /* PREFIX_VEX_0FEF */
4309 { VEX_W_TABLE (VEX_W_0FEF_P_2) },
4312 /* PREFIX_VEX_0FF0 */
4317 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
4320 /* PREFIX_VEX_0FF1 */
4324 { VEX_W_TABLE (VEX_W_0FF1_P_2) },
4327 /* PREFIX_VEX_0FF2 */
4331 { VEX_W_TABLE (VEX_W_0FF2_P_2) },
4334 /* PREFIX_VEX_0FF3 */
4338 { VEX_W_TABLE (VEX_W_0FF3_P_2) },
4341 /* PREFIX_VEX_0FF4 */
4345 { VEX_W_TABLE (VEX_W_0FF4_P_2) },
4348 /* PREFIX_VEX_0FF5 */
4352 { VEX_W_TABLE (VEX_W_0FF5_P_2) },
4355 /* PREFIX_VEX_0FF6 */
4359 { VEX_W_TABLE (VEX_W_0FF6_P_2) },
4362 /* PREFIX_VEX_0FF7 */
4366 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
4369 /* PREFIX_VEX_0FF8 */
4373 { VEX_W_TABLE (VEX_W_0FF8_P_2) },
4376 /* PREFIX_VEX_0FF9 */
4380 { VEX_W_TABLE (VEX_W_0FF9_P_2) },
4383 /* PREFIX_VEX_0FFA */
4387 { VEX_W_TABLE (VEX_W_0FFA_P_2) },
4390 /* PREFIX_VEX_0FFB */
4394 { VEX_W_TABLE (VEX_W_0FFB_P_2) },
4397 /* PREFIX_VEX_0FFC */
4401 { VEX_W_TABLE (VEX_W_0FFC_P_2) },
4404 /* PREFIX_VEX_0FFD */
4408 { VEX_W_TABLE (VEX_W_0FFD_P_2) },
4411 /* PREFIX_VEX_0FFE */
4415 { VEX_W_TABLE (VEX_W_0FFE_P_2) },
4418 /* PREFIX_VEX_0F3800 */
4422 { VEX_W_TABLE (VEX_W_0F3800_P_2) },
4425 /* PREFIX_VEX_0F3801 */
4429 { VEX_W_TABLE (VEX_W_0F3801_P_2) },
4432 /* PREFIX_VEX_0F3802 */
4436 { VEX_W_TABLE (VEX_W_0F3802_P_2) },
4439 /* PREFIX_VEX_0F3803 */
4443 { VEX_W_TABLE (VEX_W_0F3803_P_2) },
4446 /* PREFIX_VEX_0F3804 */
4450 { VEX_W_TABLE (VEX_W_0F3804_P_2) },
4453 /* PREFIX_VEX_0F3805 */
4457 { VEX_W_TABLE (VEX_W_0F3805_P_2) },
4460 /* PREFIX_VEX_0F3806 */
4464 { VEX_W_TABLE (VEX_W_0F3806_P_2) },
4467 /* PREFIX_VEX_0F3807 */
4471 { VEX_W_TABLE (VEX_W_0F3807_P_2) },
4474 /* PREFIX_VEX_0F3808 */
4478 { VEX_W_TABLE (VEX_W_0F3808_P_2) },
4481 /* PREFIX_VEX_0F3809 */
4485 { VEX_W_TABLE (VEX_W_0F3809_P_2) },
4488 /* PREFIX_VEX_0F380A */
4492 { VEX_W_TABLE (VEX_W_0F380A_P_2) },
4495 /* PREFIX_VEX_0F380B */
4499 { VEX_W_TABLE (VEX_W_0F380B_P_2) },
4502 /* PREFIX_VEX_0F380C */
4506 { VEX_W_TABLE (VEX_W_0F380C_P_2) },
4509 /* PREFIX_VEX_0F380D */
4513 { VEX_W_TABLE (VEX_W_0F380D_P_2) },
4516 /* PREFIX_VEX_0F380E */
4520 { VEX_W_TABLE (VEX_W_0F380E_P_2) },
4523 /* PREFIX_VEX_0F380F */
4527 { VEX_W_TABLE (VEX_W_0F380F_P_2) },
4530 /* PREFIX_VEX_0F3813 */
4534 { "vcvtph2ps", { XM, EXxmmq } },
4537 /* PREFIX_VEX_0F3816 */
4541 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
4544 /* PREFIX_VEX_0F3817 */
4548 { VEX_W_TABLE (VEX_W_0F3817_P_2) },
4551 /* PREFIX_VEX_0F3818 */
4555 { VEX_W_TABLE (VEX_W_0F3818_P_2) },
4558 /* PREFIX_VEX_0F3819 */
4562 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
4565 /* PREFIX_VEX_0F381A */
4569 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
4572 /* PREFIX_VEX_0F381C */
4576 { VEX_W_TABLE (VEX_W_0F381C_P_2) },
4579 /* PREFIX_VEX_0F381D */
4583 { VEX_W_TABLE (VEX_W_0F381D_P_2) },
4586 /* PREFIX_VEX_0F381E */
4590 { VEX_W_TABLE (VEX_W_0F381E_P_2) },
4593 /* PREFIX_VEX_0F3820 */
4597 { VEX_W_TABLE (VEX_W_0F3820_P_2) },
4600 /* PREFIX_VEX_0F3821 */
4604 { VEX_W_TABLE (VEX_W_0F3821_P_2) },
4607 /* PREFIX_VEX_0F3822 */
4611 { VEX_W_TABLE (VEX_W_0F3822_P_2) },
4614 /* PREFIX_VEX_0F3823 */
4618 { VEX_W_TABLE (VEX_W_0F3823_P_2) },
4621 /* PREFIX_VEX_0F3824 */
4625 { VEX_W_TABLE (VEX_W_0F3824_P_2) },
4628 /* PREFIX_VEX_0F3825 */
4632 { VEX_W_TABLE (VEX_W_0F3825_P_2) },
4635 /* PREFIX_VEX_0F3828 */
4639 { VEX_W_TABLE (VEX_W_0F3828_P_2) },
4642 /* PREFIX_VEX_0F3829 */
4646 { VEX_W_TABLE (VEX_W_0F3829_P_2) },
4649 /* PREFIX_VEX_0F382A */
4653 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
4656 /* PREFIX_VEX_0F382B */
4660 { VEX_W_TABLE (VEX_W_0F382B_P_2) },
4663 /* PREFIX_VEX_0F382C */
4667 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
4670 /* PREFIX_VEX_0F382D */
4674 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
4677 /* PREFIX_VEX_0F382E */
4681 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
4684 /* PREFIX_VEX_0F382F */
4688 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
4691 /* PREFIX_VEX_0F3830 */
4695 { VEX_W_TABLE (VEX_W_0F3830_P_2) },
4698 /* PREFIX_VEX_0F3831 */
4702 { VEX_W_TABLE (VEX_W_0F3831_P_2) },
4705 /* PREFIX_VEX_0F3832 */
4709 { VEX_W_TABLE (VEX_W_0F3832_P_2) },
4712 /* PREFIX_VEX_0F3833 */
4716 { VEX_W_TABLE (VEX_W_0F3833_P_2) },
4719 /* PREFIX_VEX_0F3834 */
4723 { VEX_W_TABLE (VEX_W_0F3834_P_2) },
4726 /* PREFIX_VEX_0F3835 */
4730 { VEX_W_TABLE (VEX_W_0F3835_P_2) },
4733 /* PREFIX_VEX_0F3836 */
4737 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
4740 /* PREFIX_VEX_0F3837 */
4744 { VEX_W_TABLE (VEX_W_0F3837_P_2) },
4747 /* PREFIX_VEX_0F3838 */
4751 { VEX_W_TABLE (VEX_W_0F3838_P_2) },
4754 /* PREFIX_VEX_0F3839 */
4758 { VEX_W_TABLE (VEX_W_0F3839_P_2) },
4761 /* PREFIX_VEX_0F383A */
4765 { VEX_W_TABLE (VEX_W_0F383A_P_2) },
4768 /* PREFIX_VEX_0F383B */
4772 { VEX_W_TABLE (VEX_W_0F383B_P_2) },
4775 /* PREFIX_VEX_0F383C */
4779 { VEX_W_TABLE (VEX_W_0F383C_P_2) },
4782 /* PREFIX_VEX_0F383D */
4786 { VEX_W_TABLE (VEX_W_0F383D_P_2) },
4789 /* PREFIX_VEX_0F383E */
4793 { VEX_W_TABLE (VEX_W_0F383E_P_2) },
4796 /* PREFIX_VEX_0F383F */
4800 { VEX_W_TABLE (VEX_W_0F383F_P_2) },
4803 /* PREFIX_VEX_0F3840 */
4807 { VEX_W_TABLE (VEX_W_0F3840_P_2) },
4810 /* PREFIX_VEX_0F3841 */
4814 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
4817 /* PREFIX_VEX_0F3845 */
4821 { "vpsrlv%LW", { XM, Vex, EXx } },
4824 /* PREFIX_VEX_0F3846 */
4828 { VEX_W_TABLE (VEX_W_0F3846_P_2) },
4831 /* PREFIX_VEX_0F3847 */
4835 { "vpsllv%LW", { XM, Vex, EXx } },
4838 /* PREFIX_VEX_0F3858 */
4842 { VEX_W_TABLE (VEX_W_0F3858_P_2) },
4845 /* PREFIX_VEX_0F3859 */
4849 { VEX_W_TABLE (VEX_W_0F3859_P_2) },
4852 /* PREFIX_VEX_0F385A */
4856 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
4859 /* PREFIX_VEX_0F3878 */
4863 { VEX_W_TABLE (VEX_W_0F3878_P_2) },
4866 /* PREFIX_VEX_0F3879 */
4870 { VEX_W_TABLE (VEX_W_0F3879_P_2) },
4873 /* PREFIX_VEX_0F388C */
4877 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
4880 /* PREFIX_VEX_0F388E */
4884 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
4887 /* PREFIX_VEX_0F3890 */
4891 { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex } },
4894 /* PREFIX_VEX_0F3891 */
4898 { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
4901 /* PREFIX_VEX_0F3892 */
4905 { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex } },
4908 /* PREFIX_VEX_0F3893 */
4912 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
4915 /* PREFIX_VEX_0F3896 */
4919 { "vfmaddsub132p%XW", { XM, Vex, EXx } },
4922 /* PREFIX_VEX_0F3897 */
4926 { "vfmsubadd132p%XW", { XM, Vex, EXx } },
4929 /* PREFIX_VEX_0F3898 */
4933 { "vfmadd132p%XW", { XM, Vex, EXx } },
4936 /* PREFIX_VEX_0F3899 */
4940 { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4943 /* PREFIX_VEX_0F389A */
4947 { "vfmsub132p%XW", { XM, Vex, EXx } },
4950 /* PREFIX_VEX_0F389B */
4954 { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4957 /* PREFIX_VEX_0F389C */
4961 { "vfnmadd132p%XW", { XM, Vex, EXx } },
4964 /* PREFIX_VEX_0F389D */
4968 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4971 /* PREFIX_VEX_0F389E */
4975 { "vfnmsub132p%XW", { XM, Vex, EXx } },
4978 /* PREFIX_VEX_0F389F */
4982 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4985 /* PREFIX_VEX_0F38A6 */
4989 { "vfmaddsub213p%XW", { XM, Vex, EXx } },
4993 /* PREFIX_VEX_0F38A7 */
4997 { "vfmsubadd213p%XW", { XM, Vex, EXx } },
5000 /* PREFIX_VEX_0F38A8 */
5004 { "vfmadd213p%XW", { XM, Vex, EXx } },
5007 /* PREFIX_VEX_0F38A9 */
5011 { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5014 /* PREFIX_VEX_0F38AA */
5018 { "vfmsub213p%XW", { XM, Vex, EXx } },
5021 /* PREFIX_VEX_0F38AB */
5025 { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5028 /* PREFIX_VEX_0F38AC */
5032 { "vfnmadd213p%XW", { XM, Vex, EXx } },
5035 /* PREFIX_VEX_0F38AD */
5039 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5042 /* PREFIX_VEX_0F38AE */
5046 { "vfnmsub213p%XW", { XM, Vex, EXx } },
5049 /* PREFIX_VEX_0F38AF */
5053 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5056 /* PREFIX_VEX_0F38B6 */
5060 { "vfmaddsub231p%XW", { XM, Vex, EXx } },
5063 /* PREFIX_VEX_0F38B7 */
5067 { "vfmsubadd231p%XW", { XM, Vex, EXx } },
5070 /* PREFIX_VEX_0F38B8 */
5074 { "vfmadd231p%XW", { XM, Vex, EXx } },
5077 /* PREFIX_VEX_0F38B9 */
5081 { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5084 /* PREFIX_VEX_0F38BA */
5088 { "vfmsub231p%XW", { XM, Vex, EXx } },
5091 /* PREFIX_VEX_0F38BB */
5095 { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5098 /* PREFIX_VEX_0F38BC */
5102 { "vfnmadd231p%XW", { XM, Vex, EXx } },
5105 /* PREFIX_VEX_0F38BD */
5109 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5112 /* PREFIX_VEX_0F38BE */
5116 { "vfnmsub231p%XW", { XM, Vex, EXx } },
5119 /* PREFIX_VEX_0F38BF */
5123 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5126 /* PREFIX_VEX_0F38DB */
5130 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
5133 /* PREFIX_VEX_0F38DC */
5137 { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
5140 /* PREFIX_VEX_0F38DD */
5144 { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
5147 /* PREFIX_VEX_0F38DE */
5151 { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
5154 /* PREFIX_VEX_0F38DF */
5158 { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
5161 /* PREFIX_VEX_0F38F2 */
5163 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
5166 /* PREFIX_VEX_0F38F3_REG_1 */
5168 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
5171 /* PREFIX_VEX_0F38F3_REG_2 */
5173 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
5176 /* PREFIX_VEX_0F38F3_REG_3 */
5178 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
5181 /* PREFIX_VEX_0F38F5 */
5183 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
5184 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
5186 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
5189 /* PREFIX_VEX_0F38F6 */
5194 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
5197 /* PREFIX_VEX_0F38F7 */
5199 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
5200 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
5201 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
5202 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
5205 /* PREFIX_VEX_0F3A00 */
5209 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
5212 /* PREFIX_VEX_0F3A01 */
5216 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
5219 /* PREFIX_VEX_0F3A02 */
5223 { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
5226 /* PREFIX_VEX_0F3A04 */
5230 { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
5233 /* PREFIX_VEX_0F3A05 */
5237 { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
5240 /* PREFIX_VEX_0F3A06 */
5244 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
5247 /* PREFIX_VEX_0F3A08 */
5251 { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
5254 /* PREFIX_VEX_0F3A09 */
5258 { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
5261 /* PREFIX_VEX_0F3A0A */
5265 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
5268 /* PREFIX_VEX_0F3A0B */
5272 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
5275 /* PREFIX_VEX_0F3A0C */
5279 { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
5282 /* PREFIX_VEX_0F3A0D */
5286 { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
5289 /* PREFIX_VEX_0F3A0E */
5293 { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
5296 /* PREFIX_VEX_0F3A0F */
5300 { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
5303 /* PREFIX_VEX_0F3A14 */
5307 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
5310 /* PREFIX_VEX_0F3A15 */
5314 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
5317 /* PREFIX_VEX_0F3A16 */
5321 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
5324 /* PREFIX_VEX_0F3A17 */
5328 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
5331 /* PREFIX_VEX_0F3A18 */
5335 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
5338 /* PREFIX_VEX_0F3A19 */
5342 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
5345 /* PREFIX_VEX_0F3A1D */
5349 { "vcvtps2ph", { EXxmmq, XM, Ib } },
5352 /* PREFIX_VEX_0F3A20 */
5356 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
5359 /* PREFIX_VEX_0F3A21 */
5363 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
5366 /* PREFIX_VEX_0F3A22 */
5370 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
5373 /* PREFIX_VEX_0F3A38 */
5377 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
5380 /* PREFIX_VEX_0F3A39 */
5384 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
5387 /* PREFIX_VEX_0F3A40 */
5391 { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
5394 /* PREFIX_VEX_0F3A41 */
5398 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
5401 /* PREFIX_VEX_0F3A42 */
5405 { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
5408 /* PREFIX_VEX_0F3A44 */
5412 { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
5415 /* PREFIX_VEX_0F3A46 */
5419 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
5422 /* PREFIX_VEX_0F3A48 */
5426 { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
5429 /* PREFIX_VEX_0F3A49 */
5433 { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
5436 /* PREFIX_VEX_0F3A4A */
5440 { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
5443 /* PREFIX_VEX_0F3A4B */
5447 { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
5450 /* PREFIX_VEX_0F3A4C */
5454 { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
5457 /* PREFIX_VEX_0F3A5C */
5461 { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5464 /* PREFIX_VEX_0F3A5D */
5468 { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5471 /* PREFIX_VEX_0F3A5E */
5475 { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5478 /* PREFIX_VEX_0F3A5F */
5482 { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5485 /* PREFIX_VEX_0F3A60 */
5489 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
5493 /* PREFIX_VEX_0F3A61 */
5497 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
5500 /* PREFIX_VEX_0F3A62 */
5504 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
5507 /* PREFIX_VEX_0F3A63 */
5511 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
5514 /* PREFIX_VEX_0F3A68 */
5518 { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5521 /* PREFIX_VEX_0F3A69 */
5525 { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5528 /* PREFIX_VEX_0F3A6A */
5532 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
5535 /* PREFIX_VEX_0F3A6B */
5539 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
5542 /* PREFIX_VEX_0F3A6C */
5546 { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5549 /* PREFIX_VEX_0F3A6D */
5553 { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5556 /* PREFIX_VEX_0F3A6E */
5560 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
5563 /* PREFIX_VEX_0F3A6F */
5567 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
5570 /* PREFIX_VEX_0F3A78 */
5574 { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5577 /* PREFIX_VEX_0F3A79 */
5581 { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5584 /* PREFIX_VEX_0F3A7A */
5588 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
5591 /* PREFIX_VEX_0F3A7B */
5595 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
5598 /* PREFIX_VEX_0F3A7C */
5602 { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5606 /* PREFIX_VEX_0F3A7D */
5610 { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5613 /* PREFIX_VEX_0F3A7E */
5617 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
5620 /* PREFIX_VEX_0F3A7F */
5624 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
5627 /* PREFIX_VEX_0F3ADF */
5631 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
5634 /* PREFIX_VEX_0F3AF0 */
5639 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
5643 static const struct dis386 x86_64_table[][2] = {
5646 { "pushP", { es } },
5656 { "pushP", { cs } },
5661 { "pushP", { ss } },
5671 { "pushP", { ds } },
5701 { "pushaP", { XX } },
5706 { "popaP", { XX } },
5711 { MOD_TABLE (MOD_62_32BIT) },
5716 { "arpl", { Ew, Gw } },
5717 { "movs{lq|xd}", { Gv, Ed } },
5722 { "ins{R|}", { Yzr, indirDX } },
5723 { "ins{G|}", { Yzr, indirDX } },
5728 { "outs{R|}", { indirDXr, Xz } },
5729 { "outs{G|}", { indirDXr, Xz } },
5734 { "Jcall{T|}", { Ap } },
5739 { MOD_TABLE (MOD_C4_32BIT) },
5740 { VEX_C4_TABLE (VEX_0F) },
5745 { MOD_TABLE (MOD_C5_32BIT) },
5746 { VEX_C5_TABLE (VEX_0F) },
5766 { "Jjmp{T|}", { Ap } },
5769 /* X86_64_0F01_REG_0 */
5771 { "sgdt{Q|IQ}", { M } },
5775 /* X86_64_0F01_REG_1 */
5777 { "sidt{Q|IQ}", { M } },
5781 /* X86_64_0F01_REG_2 */
5783 { "lgdt{Q|Q}", { M } },
5787 /* X86_64_0F01_REG_3 */
5789 { "lidt{Q|Q}", { M } },
5794 static const struct dis386 three_byte_table[][256] = {
5796 /* THREE_BYTE_0F38 */
5799 { "pshufb", { MX, EM } },
5800 { "phaddw", { MX, EM } },
5801 { "phaddd", { MX, EM } },
5802 { "phaddsw", { MX, EM } },
5803 { "pmaddubsw", { MX, EM } },
5804 { "phsubw", { MX, EM } },
5805 { "phsubd", { MX, EM } },
5806 { "phsubsw", { MX, EM } },
5808 { "psignb", { MX, EM } },
5809 { "psignw", { MX, EM } },
5810 { "psignd", { MX, EM } },
5811 { "pmulhrsw", { MX, EM } },
5817 { PREFIX_TABLE (PREFIX_0F3810) },
5821 { PREFIX_TABLE (PREFIX_0F3814) },
5822 { PREFIX_TABLE (PREFIX_0F3815) },
5824 { PREFIX_TABLE (PREFIX_0F3817) },
5830 { "pabsb", { MX, EM } },
5831 { "pabsw", { MX, EM } },
5832 { "pabsd", { MX, EM } },
5835 { PREFIX_TABLE (PREFIX_0F3820) },
5836 { PREFIX_TABLE (PREFIX_0F3821) },
5837 { PREFIX_TABLE (PREFIX_0F3822) },
5838 { PREFIX_TABLE (PREFIX_0F3823) },
5839 { PREFIX_TABLE (PREFIX_0F3824) },
5840 { PREFIX_TABLE (PREFIX_0F3825) },
5844 { PREFIX_TABLE (PREFIX_0F3828) },
5845 { PREFIX_TABLE (PREFIX_0F3829) },
5846 { PREFIX_TABLE (PREFIX_0F382A) },
5847 { PREFIX_TABLE (PREFIX_0F382B) },
5853 { PREFIX_TABLE (PREFIX_0F3830) },
5854 { PREFIX_TABLE (PREFIX_0F3831) },
5855 { PREFIX_TABLE (PREFIX_0F3832) },
5856 { PREFIX_TABLE (PREFIX_0F3833) },
5857 { PREFIX_TABLE (PREFIX_0F3834) },
5858 { PREFIX_TABLE (PREFIX_0F3835) },
5860 { PREFIX_TABLE (PREFIX_0F3837) },
5862 { PREFIX_TABLE (PREFIX_0F3838) },
5863 { PREFIX_TABLE (PREFIX_0F3839) },
5864 { PREFIX_TABLE (PREFIX_0F383A) },
5865 { PREFIX_TABLE (PREFIX_0F383B) },
5866 { PREFIX_TABLE (PREFIX_0F383C) },
5867 { PREFIX_TABLE (PREFIX_0F383D) },
5868 { PREFIX_TABLE (PREFIX_0F383E) },
5869 { PREFIX_TABLE (PREFIX_0F383F) },
5871 { PREFIX_TABLE (PREFIX_0F3840) },
5872 { PREFIX_TABLE (PREFIX_0F3841) },
5943 { PREFIX_TABLE (PREFIX_0F3880) },
5944 { PREFIX_TABLE (PREFIX_0F3881) },
5945 { PREFIX_TABLE (PREFIX_0F3882) },
6045 { PREFIX_TABLE (PREFIX_0F38DB) },
6046 { PREFIX_TABLE (PREFIX_0F38DC) },
6047 { PREFIX_TABLE (PREFIX_0F38DD) },
6048 { PREFIX_TABLE (PREFIX_0F38DE) },
6049 { PREFIX_TABLE (PREFIX_0F38DF) },
6069 { PREFIX_TABLE (PREFIX_0F38F0) },
6070 { PREFIX_TABLE (PREFIX_0F38F1) },
6075 { PREFIX_TABLE (PREFIX_0F38F6) },
6087 /* THREE_BYTE_0F3A */
6099 { PREFIX_TABLE (PREFIX_0F3A08) },
6100 { PREFIX_TABLE (PREFIX_0F3A09) },
6101 { PREFIX_TABLE (PREFIX_0F3A0A) },
6102 { PREFIX_TABLE (PREFIX_0F3A0B) },
6103 { PREFIX_TABLE (PREFIX_0F3A0C) },
6104 { PREFIX_TABLE (PREFIX_0F3A0D) },
6105 { PREFIX_TABLE (PREFIX_0F3A0E) },
6106 { "palignr", { MX, EM, Ib } },
6112 { PREFIX_TABLE (PREFIX_0F3A14) },
6113 { PREFIX_TABLE (PREFIX_0F3A15) },
6114 { PREFIX_TABLE (PREFIX_0F3A16) },
6115 { PREFIX_TABLE (PREFIX_0F3A17) },
6126 { PREFIX_TABLE (PREFIX_0F3A20) },
6127 { PREFIX_TABLE (PREFIX_0F3A21) },
6128 { PREFIX_TABLE (PREFIX_0F3A22) },
6162 { PREFIX_TABLE (PREFIX_0F3A40) },
6163 { PREFIX_TABLE (PREFIX_0F3A41) },
6164 { PREFIX_TABLE (PREFIX_0F3A42) },
6166 { PREFIX_TABLE (PREFIX_0F3A44) },
6198 { PREFIX_TABLE (PREFIX_0F3A60) },
6199 { PREFIX_TABLE (PREFIX_0F3A61) },
6200 { PREFIX_TABLE (PREFIX_0F3A62) },
6201 { PREFIX_TABLE (PREFIX_0F3A63) },
6340 { PREFIX_TABLE (PREFIX_0F3ADF) },
6379 /* THREE_BYTE_0F7A */
6418 { "ptest", { XX } },
6455 { "phaddbw", { XM, EXq } },
6456 { "phaddbd", { XM, EXq } },
6457 { "phaddbq", { XM, EXq } },
6460 { "phaddwd", { XM, EXq } },
6461 { "phaddwq", { XM, EXq } },
6466 { "phadddq", { XM, EXq } },
6473 { "phaddubw", { XM, EXq } },
6474 { "phaddubd", { XM, EXq } },
6475 { "phaddubq", { XM, EXq } },
6478 { "phadduwd", { XM, EXq } },
6479 { "phadduwq", { XM, EXq } },
6484 { "phaddudq", { XM, EXq } },
6491 { "phsubbw", { XM, EXq } },
6492 { "phsubbd", { XM, EXq } },
6493 { "phsubbq", { XM, EXq } },
6672 static const struct dis386 xop_table[][256] = {
6825 { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6826 { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6827 { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6835 { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6836 { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6843 { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6844 { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6845 { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6853 { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6854 { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6858 { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6859 { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6862 { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6880 { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6892 { "vprotb", { XM, Vex_2src_1, Ib } },
6893 { "vprotw", { XM, Vex_2src_1, Ib } },
6894 { "vprotd", { XM, Vex_2src_1, Ib } },
6895 { "vprotq", { XM, Vex_2src_1, Ib } },
6905 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
6906 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
6907 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
6908 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
6941 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
6942 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
6943 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
6944 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
6968 { REG_TABLE (REG_XOP_TBM_01) },
6969 { REG_TABLE (REG_XOP_TBM_02) },
6987 { REG_TABLE (REG_XOP_LWPCB) },
7111 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7112 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7113 { "vfrczss", { XM, EXd } },
7114 { "vfrczsd", { XM, EXq } },
7129 { "vprotb", { XM, Vex_2src_1, Vex_2src_2 } },
7130 { "vprotw", { XM, Vex_2src_1, Vex_2src_2 } },
7131 { "vprotd", { XM, Vex_2src_1, Vex_2src_2 } },
7132 { "vprotq", { XM, Vex_2src_1, Vex_2src_2 } },
7133 { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 } },
7134 { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 } },
7135 { "vpshld", { XM, Vex_2src_1, Vex_2src_2 } },
7136 { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 } },
7138 { "vpshab", { XM, Vex_2src_1, Vex_2src_2 } },
7139 { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 } },
7140 { "vpshad", { XM, Vex_2src_1, Vex_2src_2 } },
7141 { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 } },
7184 { "vphaddbw", { XM, EXxmm } },
7185 { "vphaddbd", { XM, EXxmm } },
7186 { "vphaddbq", { XM, EXxmm } },
7189 { "vphaddwd", { XM, EXxmm } },
7190 { "vphaddwq", { XM, EXxmm } },
7195 { "vphadddq", { XM, EXxmm } },
7202 { "vphaddubw", { XM, EXxmm } },
7203 { "vphaddubd", { XM, EXxmm } },
7204 { "vphaddubq", { XM, EXxmm } },
7207 { "vphadduwd", { XM, EXxmm } },
7208 { "vphadduwq", { XM, EXxmm } },
7213 { "vphaddudq", { XM, EXxmm } },
7220 { "vphsubbw", { XM, EXxmm } },
7221 { "vphsubwd", { XM, EXxmm } },
7222 { "vphsubdq", { XM, EXxmm } },
7276 { "bextr", { Gv, Ev, Iq } },
7278 { REG_TABLE (REG_XOP_LWP) },
7548 static const struct dis386 vex_table[][256] = {
7570 { PREFIX_TABLE (PREFIX_VEX_0F10) },
7571 { PREFIX_TABLE (PREFIX_VEX_0F11) },
7572 { PREFIX_TABLE (PREFIX_VEX_0F12) },
7573 { MOD_TABLE (MOD_VEX_0F13) },
7574 { VEX_W_TABLE (VEX_W_0F14) },
7575 { VEX_W_TABLE (VEX_W_0F15) },
7576 { PREFIX_TABLE (PREFIX_VEX_0F16) },
7577 { MOD_TABLE (MOD_VEX_0F17) },
7597 { VEX_W_TABLE (VEX_W_0F28) },
7598 { VEX_W_TABLE (VEX_W_0F29) },
7599 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
7600 { MOD_TABLE (MOD_VEX_0F2B) },
7601 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
7602 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
7603 { PREFIX_TABLE (PREFIX_VEX_0F2E) },
7604 { PREFIX_TABLE (PREFIX_VEX_0F2F) },
7642 { MOD_TABLE (MOD_VEX_0F50) },
7643 { PREFIX_TABLE (PREFIX_VEX_0F51) },
7644 { PREFIX_TABLE (PREFIX_VEX_0F52) },
7645 { PREFIX_TABLE (PREFIX_VEX_0F53) },
7646 { "vandpX", { XM, Vex, EXx } },
7647 { "vandnpX", { XM, Vex, EXx } },
7648 { "vorpX", { XM, Vex, EXx } },
7649 { "vxorpX", { XM, Vex, EXx } },
7651 { PREFIX_TABLE (PREFIX_VEX_0F58) },
7652 { PREFIX_TABLE (PREFIX_VEX_0F59) },
7653 { PREFIX_TABLE (PREFIX_VEX_0F5A) },
7654 { PREFIX_TABLE (PREFIX_VEX_0F5B) },
7655 { PREFIX_TABLE (PREFIX_VEX_0F5C) },
7656 { PREFIX_TABLE (PREFIX_VEX_0F5D) },
7657 { PREFIX_TABLE (PREFIX_VEX_0F5E) },
7658 { PREFIX_TABLE (PREFIX_VEX_0F5F) },
7660 { PREFIX_TABLE (PREFIX_VEX_0F60) },
7661 { PREFIX_TABLE (PREFIX_VEX_0F61) },
7662 { PREFIX_TABLE (PREFIX_VEX_0F62) },
7663 { PREFIX_TABLE (PREFIX_VEX_0F63) },
7664 { PREFIX_TABLE (PREFIX_VEX_0F64) },
7665 { PREFIX_TABLE (PREFIX_VEX_0F65) },
7666 { PREFIX_TABLE (PREFIX_VEX_0F66) },
7667 { PREFIX_TABLE (PREFIX_VEX_0F67) },
7669 { PREFIX_TABLE (PREFIX_VEX_0F68) },
7670 { PREFIX_TABLE (PREFIX_VEX_0F69) },
7671 { PREFIX_TABLE (PREFIX_VEX_0F6A) },
7672 { PREFIX_TABLE (PREFIX_VEX_0F6B) },
7673 { PREFIX_TABLE (PREFIX_VEX_0F6C) },
7674 { PREFIX_TABLE (PREFIX_VEX_0F6D) },
7675 { PREFIX_TABLE (PREFIX_VEX_0F6E) },
7676 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
7678 { PREFIX_TABLE (PREFIX_VEX_0F70) },
7679 { REG_TABLE (REG_VEX_0F71) },
7680 { REG_TABLE (REG_VEX_0F72) },
7681 { REG_TABLE (REG_VEX_0F73) },
7682 { PREFIX_TABLE (PREFIX_VEX_0F74) },
7683 { PREFIX_TABLE (PREFIX_VEX_0F75) },
7684 { PREFIX_TABLE (PREFIX_VEX_0F76) },
7685 { PREFIX_TABLE (PREFIX_VEX_0F77) },
7691 { PREFIX_TABLE (PREFIX_VEX_0F7C) },
7692 { PREFIX_TABLE (PREFIX_VEX_0F7D) },
7693 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
7694 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
7747 { REG_TABLE (REG_VEX_0FAE) },
7770 { PREFIX_TABLE (PREFIX_VEX_0FC2) },
7772 { PREFIX_TABLE (PREFIX_VEX_0FC4) },
7773 { PREFIX_TABLE (PREFIX_VEX_0FC5) },
7774 { "vshufpX", { XM, Vex, EXx, Ib } },
7786 { PREFIX_TABLE (PREFIX_VEX_0FD0) },
7787 { PREFIX_TABLE (PREFIX_VEX_0FD1) },
7788 { PREFIX_TABLE (PREFIX_VEX_0FD2) },
7789 { PREFIX_TABLE (PREFIX_VEX_0FD3) },
7790 { PREFIX_TABLE (PREFIX_VEX_0FD4) },
7791 { PREFIX_TABLE (PREFIX_VEX_0FD5) },
7792 { PREFIX_TABLE (PREFIX_VEX_0FD6) },
7793 { PREFIX_TABLE (PREFIX_VEX_0FD7) },
7795 { PREFIX_TABLE (PREFIX_VEX_0FD8) },
7796 { PREFIX_TABLE (PREFIX_VEX_0FD9) },
7797 { PREFIX_TABLE (PREFIX_VEX_0FDA) },
7798 { PREFIX_TABLE (PREFIX_VEX_0FDB) },
7799 { PREFIX_TABLE (PREFIX_VEX_0FDC) },
7800 { PREFIX_TABLE (PREFIX_VEX_0FDD) },
7801 { PREFIX_TABLE (PREFIX_VEX_0FDE) },
7802 { PREFIX_TABLE (PREFIX_VEX_0FDF) },
7804 { PREFIX_TABLE (PREFIX_VEX_0FE0) },
7805 { PREFIX_TABLE (PREFIX_VEX_0FE1) },
7806 { PREFIX_TABLE (PREFIX_VEX_0FE2) },
7807 { PREFIX_TABLE (PREFIX_VEX_0FE3) },
7808 { PREFIX_TABLE (PREFIX_VEX_0FE4) },
7809 { PREFIX_TABLE (PREFIX_VEX_0FE5) },
7810 { PREFIX_TABLE (PREFIX_VEX_0FE6) },
7811 { PREFIX_TABLE (PREFIX_VEX_0FE7) },
7813 { PREFIX_TABLE (PREFIX_VEX_0FE8) },
7814 { PREFIX_TABLE (PREFIX_VEX_0FE9) },
7815 { PREFIX_TABLE (PREFIX_VEX_0FEA) },
7816 { PREFIX_TABLE (PREFIX_VEX_0FEB) },
7817 { PREFIX_TABLE (PREFIX_VEX_0FEC) },
7818 { PREFIX_TABLE (PREFIX_VEX_0FED) },
7819 { PREFIX_TABLE (PREFIX_VEX_0FEE) },
7820 { PREFIX_TABLE (PREFIX_VEX_0FEF) },
7822 { PREFIX_TABLE (PREFIX_VEX_0FF0) },
7823 { PREFIX_TABLE (PREFIX_VEX_0FF1) },
7824 { PREFIX_TABLE (PREFIX_VEX_0FF2) },
7825 { PREFIX_TABLE (PREFIX_VEX_0FF3) },
7826 { PREFIX_TABLE (PREFIX_VEX_0FF4) },
7827 { PREFIX_TABLE (PREFIX_VEX_0FF5) },
7828 { PREFIX_TABLE (PREFIX_VEX_0FF6) },
7829 { PREFIX_TABLE (PREFIX_VEX_0FF7) },
7831 { PREFIX_TABLE (PREFIX_VEX_0FF8) },
7832 { PREFIX_TABLE (PREFIX_VEX_0FF9) },
7833 { PREFIX_TABLE (PREFIX_VEX_0FFA) },
7834 { PREFIX_TABLE (PREFIX_VEX_0FFB) },
7835 { PREFIX_TABLE (PREFIX_VEX_0FFC) },
7836 { PREFIX_TABLE (PREFIX_VEX_0FFD) },
7837 { PREFIX_TABLE (PREFIX_VEX_0FFE) },
7843 { PREFIX_TABLE (PREFIX_VEX_0F3800) },
7844 { PREFIX_TABLE (PREFIX_VEX_0F3801) },
7845 { PREFIX_TABLE (PREFIX_VEX_0F3802) },
7846 { PREFIX_TABLE (PREFIX_VEX_0F3803) },
7847 { PREFIX_TABLE (PREFIX_VEX_0F3804) },
7848 { PREFIX_TABLE (PREFIX_VEX_0F3805) },
7849 { PREFIX_TABLE (PREFIX_VEX_0F3806) },
7850 { PREFIX_TABLE (PREFIX_VEX_0F3807) },
7852 { PREFIX_TABLE (PREFIX_VEX_0F3808) },
7853 { PREFIX_TABLE (PREFIX_VEX_0F3809) },
7854 { PREFIX_TABLE (PREFIX_VEX_0F380A) },
7855 { PREFIX_TABLE (PREFIX_VEX_0F380B) },
7856 { PREFIX_TABLE (PREFIX_VEX_0F380C) },
7857 { PREFIX_TABLE (PREFIX_VEX_0F380D) },
7858 { PREFIX_TABLE (PREFIX_VEX_0F380E) },
7859 { PREFIX_TABLE (PREFIX_VEX_0F380F) },
7864 { PREFIX_TABLE (PREFIX_VEX_0F3813) },
7867 { PREFIX_TABLE (PREFIX_VEX_0F3816) },
7868 { PREFIX_TABLE (PREFIX_VEX_0F3817) },
7870 { PREFIX_TABLE (PREFIX_VEX_0F3818) },
7871 { PREFIX_TABLE (PREFIX_VEX_0F3819) },
7872 { PREFIX_TABLE (PREFIX_VEX_0F381A) },
7874 { PREFIX_TABLE (PREFIX_VEX_0F381C) },
7875 { PREFIX_TABLE (PREFIX_VEX_0F381D) },
7876 { PREFIX_TABLE (PREFIX_VEX_0F381E) },
7879 { PREFIX_TABLE (PREFIX_VEX_0F3820) },
7880 { PREFIX_TABLE (PREFIX_VEX_0F3821) },
7881 { PREFIX_TABLE (PREFIX_VEX_0F3822) },
7882 { PREFIX_TABLE (PREFIX_VEX_0F3823) },
7883 { PREFIX_TABLE (PREFIX_VEX_0F3824) },
7884 { PREFIX_TABLE (PREFIX_VEX_0F3825) },
7888 { PREFIX_TABLE (PREFIX_VEX_0F3828) },
7889 { PREFIX_TABLE (PREFIX_VEX_0F3829) },
7890 { PREFIX_TABLE (PREFIX_VEX_0F382A) },
7891 { PREFIX_TABLE (PREFIX_VEX_0F382B) },
7892 { PREFIX_TABLE (PREFIX_VEX_0F382C) },
7893 { PREFIX_TABLE (PREFIX_VEX_0F382D) },
7894 { PREFIX_TABLE (PREFIX_VEX_0F382E) },
7895 { PREFIX_TABLE (PREFIX_VEX_0F382F) },
7897 { PREFIX_TABLE (PREFIX_VEX_0F3830) },
7898 { PREFIX_TABLE (PREFIX_VEX_0F3831) },
7899 { PREFIX_TABLE (PREFIX_VEX_0F3832) },
7900 { PREFIX_TABLE (PREFIX_VEX_0F3833) },
7901 { PREFIX_TABLE (PREFIX_VEX_0F3834) },
7902 { PREFIX_TABLE (PREFIX_VEX_0F3835) },
7903 { PREFIX_TABLE (PREFIX_VEX_0F3836) },
7904 { PREFIX_TABLE (PREFIX_VEX_0F3837) },
7906 { PREFIX_TABLE (PREFIX_VEX_0F3838) },
7907 { PREFIX_TABLE (PREFIX_VEX_0F3839) },
7908 { PREFIX_TABLE (PREFIX_VEX_0F383A) },
7909 { PREFIX_TABLE (PREFIX_VEX_0F383B) },
7910 { PREFIX_TABLE (PREFIX_VEX_0F383C) },
7911 { PREFIX_TABLE (PREFIX_VEX_0F383D) },
7912 { PREFIX_TABLE (PREFIX_VEX_0F383E) },
7913 { PREFIX_TABLE (PREFIX_VEX_0F383F) },
7915 { PREFIX_TABLE (PREFIX_VEX_0F3840) },
7916 { PREFIX_TABLE (PREFIX_VEX_0F3841) },
7920 { PREFIX_TABLE (PREFIX_VEX_0F3845) },
7921 { PREFIX_TABLE (PREFIX_VEX_0F3846) },
7922 { PREFIX_TABLE (PREFIX_VEX_0F3847) },
7942 { PREFIX_TABLE (PREFIX_VEX_0F3858) },
7943 { PREFIX_TABLE (PREFIX_VEX_0F3859) },
7944 { PREFIX_TABLE (PREFIX_VEX_0F385A) },
7978 { PREFIX_TABLE (PREFIX_VEX_0F3878) },
7979 { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8000 { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8002 { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8005 { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8006 { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8007 { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8008 { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8011 { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8012 { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8014 { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8015 { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8016 { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8017 { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8018 { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8019 { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8020 { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8021 { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8029 { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8030 { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8032 { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8033 { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8034 { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8035 { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8036 { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8037 { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8038 { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8039 { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8047 { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8048 { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8050 { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8051 { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8052 { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8053 { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8054 { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8055 { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8056 { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8057 { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8089 { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8090 { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8091 { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8092 { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8093 { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8115 { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8116 { REG_TABLE (REG_VEX_0F38F3) },
8118 { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8119 { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8120 { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8134 { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
8135 { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
8136 { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
8138 { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
8139 { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
8140 { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
8143 { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
8144 { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
8145 { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
8146 { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
8147 { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
8148 { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
8149 { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
8150 { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
8156 { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
8157 { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
8158 { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
8159 { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
8161 { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
8162 { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
8166 { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
8170 { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
8171 { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
8172 { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
8197 { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
8198 { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
8206 { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
8207 { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
8208 { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
8210 { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
8212 { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
8215 { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
8216 { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
8217 { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
8218 { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
8219 { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
8237 { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
8238 { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
8239 { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
8240 { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
8242 { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
8243 { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
8244 { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
8245 { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
8251 { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
8252 { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
8253 { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
8254 { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
8255 { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
8256 { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
8257 { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
8258 { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
8269 { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
8270 { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
8271 { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
8272 { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
8273 { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
8274 { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
8275 { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
8276 { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
8384 { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
8404 { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
8424 static const struct dis386 vex_len_table[][2] = {
8425 /* VEX_LEN_0F10_P_1 */
8427 { VEX_W_TABLE (VEX_W_0F10_P_1) },
8428 { VEX_W_TABLE (VEX_W_0F10_P_1) },
8431 /* VEX_LEN_0F10_P_3 */
8433 { VEX_W_TABLE (VEX_W_0F10_P_3) },
8434 { VEX_W_TABLE (VEX_W_0F10_P_3) },
8437 /* VEX_LEN_0F11_P_1 */
8439 { VEX_W_TABLE (VEX_W_0F11_P_1) },
8440 { VEX_W_TABLE (VEX_W_0F11_P_1) },
8443 /* VEX_LEN_0F11_P_3 */
8445 { VEX_W_TABLE (VEX_W_0F11_P_3) },
8446 { VEX_W_TABLE (VEX_W_0F11_P_3) },
8449 /* VEX_LEN_0F12_P_0_M_0 */
8451 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
8454 /* VEX_LEN_0F12_P_0_M_1 */
8456 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
8459 /* VEX_LEN_0F12_P_2 */
8461 { VEX_W_TABLE (VEX_W_0F12_P_2) },
8464 /* VEX_LEN_0F13_M_0 */
8466 { VEX_W_TABLE (VEX_W_0F13_M_0) },
8469 /* VEX_LEN_0F16_P_0_M_0 */
8471 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
8474 /* VEX_LEN_0F16_P_0_M_1 */
8476 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
8479 /* VEX_LEN_0F16_P_2 */
8481 { VEX_W_TABLE (VEX_W_0F16_P_2) },
8484 /* VEX_LEN_0F17_M_0 */
8486 { VEX_W_TABLE (VEX_W_0F17_M_0) },
8489 /* VEX_LEN_0F2A_P_1 */
8491 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } },
8492 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } },
8495 /* VEX_LEN_0F2A_P_3 */
8497 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } },
8498 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } },
8501 /* VEX_LEN_0F2C_P_1 */
8503 { "vcvttss2siY", { Gv, EXdScalar } },
8504 { "vcvttss2siY", { Gv, EXdScalar } },
8507 /* VEX_LEN_0F2C_P_3 */
8509 { "vcvttsd2siY", { Gv, EXqScalar } },
8510 { "vcvttsd2siY", { Gv, EXqScalar } },
8513 /* VEX_LEN_0F2D_P_1 */
8515 { "vcvtss2siY", { Gv, EXdScalar } },
8516 { "vcvtss2siY", { Gv, EXdScalar } },
8519 /* VEX_LEN_0F2D_P_3 */
8521 { "vcvtsd2siY", { Gv, EXqScalar } },
8522 { "vcvtsd2siY", { Gv, EXqScalar } },
8525 /* VEX_LEN_0F2E_P_0 */
8527 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
8528 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
8531 /* VEX_LEN_0F2E_P_2 */
8533 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
8534 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
8537 /* VEX_LEN_0F2F_P_0 */
8539 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
8540 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
8543 /* VEX_LEN_0F2F_P_2 */
8545 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
8546 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
8549 /* VEX_LEN_0F51_P_1 */
8551 { VEX_W_TABLE (VEX_W_0F51_P_1) },
8552 { VEX_W_TABLE (VEX_W_0F51_P_1) },
8555 /* VEX_LEN_0F51_P_3 */
8557 { VEX_W_TABLE (VEX_W_0F51_P_3) },
8558 { VEX_W_TABLE (VEX_W_0F51_P_3) },
8561 /* VEX_LEN_0F52_P_1 */
8563 { VEX_W_TABLE (VEX_W_0F52_P_1) },
8564 { VEX_W_TABLE (VEX_W_0F52_P_1) },
8567 /* VEX_LEN_0F53_P_1 */
8569 { VEX_W_TABLE (VEX_W_0F53_P_1) },
8570 { VEX_W_TABLE (VEX_W_0F53_P_1) },
8573 /* VEX_LEN_0F58_P_1 */
8575 { VEX_W_TABLE (VEX_W_0F58_P_1) },
8576 { VEX_W_TABLE (VEX_W_0F58_P_1) },
8579 /* VEX_LEN_0F58_P_3 */
8581 { VEX_W_TABLE (VEX_W_0F58_P_3) },
8582 { VEX_W_TABLE (VEX_W_0F58_P_3) },
8585 /* VEX_LEN_0F59_P_1 */
8587 { VEX_W_TABLE (VEX_W_0F59_P_1) },
8588 { VEX_W_TABLE (VEX_W_0F59_P_1) },
8591 /* VEX_LEN_0F59_P_3 */
8593 { VEX_W_TABLE (VEX_W_0F59_P_3) },
8594 { VEX_W_TABLE (VEX_W_0F59_P_3) },
8597 /* VEX_LEN_0F5A_P_1 */
8599 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
8600 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
8603 /* VEX_LEN_0F5A_P_3 */
8605 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
8606 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
8609 /* VEX_LEN_0F5C_P_1 */
8611 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
8612 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
8615 /* VEX_LEN_0F5C_P_3 */
8617 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
8618 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
8621 /* VEX_LEN_0F5D_P_1 */
8623 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
8624 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
8627 /* VEX_LEN_0F5D_P_3 */
8629 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
8630 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
8633 /* VEX_LEN_0F5E_P_1 */
8635 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
8636 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
8639 /* VEX_LEN_0F5E_P_3 */
8641 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
8642 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
8645 /* VEX_LEN_0F5F_P_1 */
8647 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
8648 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
8651 /* VEX_LEN_0F5F_P_3 */
8653 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
8654 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
8657 /* VEX_LEN_0F6E_P_2 */
8659 { "vmovK", { XMScalar, Edq } },
8660 { "vmovK", { XMScalar, Edq } },
8663 /* VEX_LEN_0F7E_P_1 */
8665 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
8666 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
8669 /* VEX_LEN_0F7E_P_2 */
8671 { "vmovK", { Edq, XMScalar } },
8672 { "vmovK", { Edq, XMScalar } },
8675 /* VEX_LEN_0FAE_R_2_M_0 */
8677 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
8680 /* VEX_LEN_0FAE_R_3_M_0 */
8682 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
8685 /* VEX_LEN_0FC2_P_1 */
8687 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
8688 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
8691 /* VEX_LEN_0FC2_P_3 */
8693 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
8694 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
8697 /* VEX_LEN_0FC4_P_2 */
8699 { VEX_W_TABLE (VEX_W_0FC4_P_2) },
8702 /* VEX_LEN_0FC5_P_2 */
8704 { VEX_W_TABLE (VEX_W_0FC5_P_2) },
8707 /* VEX_LEN_0FD6_P_2 */
8709 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
8710 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
8713 /* VEX_LEN_0FF7_P_2 */
8715 { VEX_W_TABLE (VEX_W_0FF7_P_2) },
8718 /* VEX_LEN_0F3816_P_2 */
8721 { VEX_W_TABLE (VEX_W_0F3816_P_2) },
8724 /* VEX_LEN_0F3819_P_2 */
8727 { VEX_W_TABLE (VEX_W_0F3819_P_2) },
8730 /* VEX_LEN_0F381A_P_2_M_0 */
8733 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
8736 /* VEX_LEN_0F3836_P_2 */
8739 { VEX_W_TABLE (VEX_W_0F3836_P_2) },
8742 /* VEX_LEN_0F3841_P_2 */
8744 { VEX_W_TABLE (VEX_W_0F3841_P_2) },
8747 /* VEX_LEN_0F385A_P_2_M_0 */
8750 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
8753 /* VEX_LEN_0F38DB_P_2 */
8755 { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
8758 /* VEX_LEN_0F38DC_P_2 */
8760 { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
8763 /* VEX_LEN_0F38DD_P_2 */
8765 { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
8768 /* VEX_LEN_0F38DE_P_2 */
8770 { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
8773 /* VEX_LEN_0F38DF_P_2 */
8775 { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
8778 /* VEX_LEN_0F38F2_P_0 */
8780 { "andnS", { Gdq, VexGdq, Edq } },
8783 /* VEX_LEN_0F38F3_R_1_P_0 */
8785 { "blsrS", { VexGdq, Edq } },
8788 /* VEX_LEN_0F38F3_R_2_P_0 */
8790 { "blsmskS", { VexGdq, Edq } },
8793 /* VEX_LEN_0F38F3_R_3_P_0 */
8795 { "blsiS", { VexGdq, Edq } },
8798 /* VEX_LEN_0F38F5_P_0 */
8800 { "bzhiS", { Gdq, Edq, VexGdq } },
8803 /* VEX_LEN_0F38F5_P_1 */
8805 { "pextS", { Gdq, VexGdq, Edq } },
8808 /* VEX_LEN_0F38F5_P_3 */
8810 { "pdepS", { Gdq, VexGdq, Edq } },
8813 /* VEX_LEN_0F38F6_P_3 */
8815 { "mulxS", { Gdq, VexGdq, Edq } },
8818 /* VEX_LEN_0F38F7_P_0 */
8820 { "bextrS", { Gdq, Edq, VexGdq } },
8823 /* VEX_LEN_0F38F7_P_1 */
8825 { "sarxS", { Gdq, Edq, VexGdq } },
8828 /* VEX_LEN_0F38F7_P_2 */
8830 { "shlxS", { Gdq, Edq, VexGdq } },
8833 /* VEX_LEN_0F38F7_P_3 */
8835 { "shrxS", { Gdq, Edq, VexGdq } },
8838 /* VEX_LEN_0F3A00_P_2 */
8841 { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
8844 /* VEX_LEN_0F3A01_P_2 */
8847 { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
8850 /* VEX_LEN_0F3A06_P_2 */
8853 { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
8856 /* VEX_LEN_0F3A0A_P_2 */
8858 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
8859 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
8862 /* VEX_LEN_0F3A0B_P_2 */
8864 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
8865 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
8868 /* VEX_LEN_0F3A14_P_2 */
8870 { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
8873 /* VEX_LEN_0F3A15_P_2 */
8875 { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
8878 /* VEX_LEN_0F3A16_P_2 */
8880 { "vpextrK", { Edq, XM, Ib } },
8883 /* VEX_LEN_0F3A17_P_2 */
8885 { "vextractps", { Edqd, XM, Ib } },
8888 /* VEX_LEN_0F3A18_P_2 */
8891 { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
8894 /* VEX_LEN_0F3A19_P_2 */
8897 { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
8900 /* VEX_LEN_0F3A20_P_2 */
8902 { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
8905 /* VEX_LEN_0F3A21_P_2 */
8907 { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
8910 /* VEX_LEN_0F3A22_P_2 */
8912 { "vpinsrK", { XM, Vex128, Edq, Ib } },
8915 /* VEX_LEN_0F3A38_P_2 */
8918 { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
8921 /* VEX_LEN_0F3A39_P_2 */
8924 { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
8927 /* VEX_LEN_0F3A41_P_2 */
8929 { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
8932 /* VEX_LEN_0F3A44_P_2 */
8934 { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
8937 /* VEX_LEN_0F3A46_P_2 */
8940 { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
8943 /* VEX_LEN_0F3A60_P_2 */
8945 { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
8948 /* VEX_LEN_0F3A61_P_2 */
8950 { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
8953 /* VEX_LEN_0F3A62_P_2 */
8955 { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
8958 /* VEX_LEN_0F3A63_P_2 */
8960 { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
8963 /* VEX_LEN_0F3A6A_P_2 */
8965 { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
8968 /* VEX_LEN_0F3A6B_P_2 */
8970 { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
8973 /* VEX_LEN_0F3A6E_P_2 */
8975 { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
8978 /* VEX_LEN_0F3A6F_P_2 */
8980 { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
8983 /* VEX_LEN_0F3A7A_P_2 */
8985 { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
8988 /* VEX_LEN_0F3A7B_P_2 */
8990 { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
8993 /* VEX_LEN_0F3A7E_P_2 */
8995 { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
8998 /* VEX_LEN_0F3A7F_P_2 */
9000 { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
9003 /* VEX_LEN_0F3ADF_P_2 */
9005 { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
9008 /* VEX_LEN_0F3AF0_P_3 */
9010 { "rorxS", { Gdq, Edq, Ib } },
9013 /* VEX_LEN_0FXOP_08_CC */
9015 { "vpcomb", { XM, Vex128, EXx, Ib } },
9018 /* VEX_LEN_0FXOP_08_CD */
9020 { "vpcomw", { XM, Vex128, EXx, Ib } },
9023 /* VEX_LEN_0FXOP_08_CE */
9025 { "vpcomd", { XM, Vex128, EXx, Ib } },
9028 /* VEX_LEN_0FXOP_08_CF */
9030 { "vpcomq", { XM, Vex128, EXx, Ib } },
9033 /* VEX_LEN_0FXOP_08_EC */
9035 { "vpcomub", { XM, Vex128, EXx, Ib } },
9038 /* VEX_LEN_0FXOP_08_ED */
9040 { "vpcomuw", { XM, Vex128, EXx, Ib } },
9043 /* VEX_LEN_0FXOP_08_EE */
9045 { "vpcomud", { XM, Vex128, EXx, Ib } },
9048 /* VEX_LEN_0FXOP_08_EF */
9050 { "vpcomuq", { XM, Vex128, EXx, Ib } },
9053 /* VEX_LEN_0FXOP_09_80 */
9055 { "vfrczps", { XM, EXxmm } },
9056 { "vfrczps", { XM, EXymmq } },
9059 /* VEX_LEN_0FXOP_09_81 */
9061 { "vfrczpd", { XM, EXxmm } },
9062 { "vfrczpd", { XM, EXymmq } },
9066 static const struct dis386 vex_w_table[][2] = {
9068 /* VEX_W_0F10_P_0 */
9069 { "vmovups", { XM, EXx } },
9072 /* VEX_W_0F10_P_1 */
9073 { "vmovss", { XMVexScalar, VexScalar, EXdScalar } },
9076 /* VEX_W_0F10_P_2 */
9077 { "vmovupd", { XM, EXx } },
9080 /* VEX_W_0F10_P_3 */
9081 { "vmovsd", { XMVexScalar, VexScalar, EXqScalar } },
9084 /* VEX_W_0F11_P_0 */
9085 { "vmovups", { EXxS, XM } },
9088 /* VEX_W_0F11_P_1 */
9089 { "vmovss", { EXdVexScalarS, VexScalar, XMScalar } },
9092 /* VEX_W_0F11_P_2 */
9093 { "vmovupd", { EXxS, XM } },
9096 /* VEX_W_0F11_P_3 */
9097 { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar } },
9100 /* VEX_W_0F12_P_0_M_0 */
9101 { "vmovlps", { XM, Vex128, EXq } },
9104 /* VEX_W_0F12_P_0_M_1 */
9105 { "vmovhlps", { XM, Vex128, EXq } },
9108 /* VEX_W_0F12_P_1 */
9109 { "vmovsldup", { XM, EXx } },
9112 /* VEX_W_0F12_P_2 */
9113 { "vmovlpd", { XM, Vex128, EXq } },
9116 /* VEX_W_0F12_P_3 */
9117 { "vmovddup", { XM, EXymmq } },
9120 /* VEX_W_0F13_M_0 */
9121 { "vmovlpX", { EXq, XM } },
9125 { "vunpcklpX", { XM, Vex, EXx } },
9129 { "vunpckhpX", { XM, Vex, EXx } },
9132 /* VEX_W_0F16_P_0_M_0 */
9133 { "vmovhps", { XM, Vex128, EXq } },
9136 /* VEX_W_0F16_P_0_M_1 */
9137 { "vmovlhps", { XM, Vex128, EXq } },
9140 /* VEX_W_0F16_P_1 */
9141 { "vmovshdup", { XM, EXx } },
9144 /* VEX_W_0F16_P_2 */
9145 { "vmovhpd", { XM, Vex128, EXq } },
9148 /* VEX_W_0F17_M_0 */
9149 { "vmovhpX", { EXq, XM } },
9153 { "vmovapX", { XM, EXx } },
9157 { "vmovapX", { EXxS, XM } },
9160 /* VEX_W_0F2B_M_0 */
9161 { "vmovntpX", { Mx, XM } },
9164 /* VEX_W_0F2E_P_0 */
9165 { "vucomiss", { XMScalar, EXdScalar } },
9168 /* VEX_W_0F2E_P_2 */
9169 { "vucomisd", { XMScalar, EXqScalar } },
9172 /* VEX_W_0F2F_P_0 */
9173 { "vcomiss", { XMScalar, EXdScalar } },
9176 /* VEX_W_0F2F_P_2 */
9177 { "vcomisd", { XMScalar, EXqScalar } },
9180 /* VEX_W_0F50_M_0 */
9181 { "vmovmskpX", { Gdq, XS } },
9184 /* VEX_W_0F51_P_0 */
9185 { "vsqrtps", { XM, EXx } },
9188 /* VEX_W_0F51_P_1 */
9189 { "vsqrtss", { XMScalar, VexScalar, EXdScalar } },
9192 /* VEX_W_0F51_P_2 */
9193 { "vsqrtpd", { XM, EXx } },
9196 /* VEX_W_0F51_P_3 */
9197 { "vsqrtsd", { XMScalar, VexScalar, EXqScalar } },
9200 /* VEX_W_0F52_P_0 */
9201 { "vrsqrtps", { XM, EXx } },
9204 /* VEX_W_0F52_P_1 */
9205 { "vrsqrtss", { XMScalar, VexScalar, EXdScalar } },
9208 /* VEX_W_0F53_P_0 */
9209 { "vrcpps", { XM, EXx } },
9212 /* VEX_W_0F53_P_1 */
9213 { "vrcpss", { XMScalar, VexScalar, EXdScalar } },
9216 /* VEX_W_0F58_P_0 */
9217 { "vaddps", { XM, Vex, EXx } },
9220 /* VEX_W_0F58_P_1 */
9221 { "vaddss", { XMScalar, VexScalar, EXdScalar } },
9224 /* VEX_W_0F58_P_2 */
9225 { "vaddpd", { XM, Vex, EXx } },
9228 /* VEX_W_0F58_P_3 */
9229 { "vaddsd", { XMScalar, VexScalar, EXqScalar } },
9232 /* VEX_W_0F59_P_0 */
9233 { "vmulps", { XM, Vex, EXx } },
9236 /* VEX_W_0F59_P_1 */
9237 { "vmulss", { XMScalar, VexScalar, EXdScalar } },
9240 /* VEX_W_0F59_P_2 */
9241 { "vmulpd", { XM, Vex, EXx } },
9244 /* VEX_W_0F59_P_3 */
9245 { "vmulsd", { XMScalar, VexScalar, EXqScalar } },
9248 /* VEX_W_0F5A_P_0 */
9249 { "vcvtps2pd", { XM, EXxmmq } },
9252 /* VEX_W_0F5A_P_1 */
9253 { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar } },
9256 /* VEX_W_0F5A_P_3 */
9257 { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar } },
9260 /* VEX_W_0F5B_P_0 */
9261 { "vcvtdq2ps", { XM, EXx } },
9264 /* VEX_W_0F5B_P_1 */
9265 { "vcvttps2dq", { XM, EXx } },
9268 /* VEX_W_0F5B_P_2 */
9269 { "vcvtps2dq", { XM, EXx } },
9272 /* VEX_W_0F5C_P_0 */
9273 { "vsubps", { XM, Vex, EXx } },
9276 /* VEX_W_0F5C_P_1 */
9277 { "vsubss", { XMScalar, VexScalar, EXdScalar } },
9280 /* VEX_W_0F5C_P_2 */
9281 { "vsubpd", { XM, Vex, EXx } },
9284 /* VEX_W_0F5C_P_3 */
9285 { "vsubsd", { XMScalar, VexScalar, EXqScalar } },
9288 /* VEX_W_0F5D_P_0 */
9289 { "vminps", { XM, Vex, EXx } },
9292 /* VEX_W_0F5D_P_1 */
9293 { "vminss", { XMScalar, VexScalar, EXdScalar } },
9296 /* VEX_W_0F5D_P_2 */
9297 { "vminpd", { XM, Vex, EXx } },
9300 /* VEX_W_0F5D_P_3 */
9301 { "vminsd", { XMScalar, VexScalar, EXqScalar } },
9304 /* VEX_W_0F5E_P_0 */
9305 { "vdivps", { XM, Vex, EXx } },
9308 /* VEX_W_0F5E_P_1 */
9309 { "vdivss", { XMScalar, VexScalar, EXdScalar } },
9312 /* VEX_W_0F5E_P_2 */
9313 { "vdivpd", { XM, Vex, EXx } },
9316 /* VEX_W_0F5E_P_3 */
9317 { "vdivsd", { XMScalar, VexScalar, EXqScalar } },
9320 /* VEX_W_0F5F_P_0 */
9321 { "vmaxps", { XM, Vex, EXx } },
9324 /* VEX_W_0F5F_P_1 */
9325 { "vmaxss", { XMScalar, VexScalar, EXdScalar } },
9328 /* VEX_W_0F5F_P_2 */
9329 { "vmaxpd", { XM, Vex, EXx } },
9332 /* VEX_W_0F5F_P_3 */
9333 { "vmaxsd", { XMScalar, VexScalar, EXqScalar } },
9336 /* VEX_W_0F60_P_2 */
9337 { "vpunpcklbw", { XM, Vex, EXx } },
9340 /* VEX_W_0F61_P_2 */
9341 { "vpunpcklwd", { XM, Vex, EXx } },
9344 /* VEX_W_0F62_P_2 */
9345 { "vpunpckldq", { XM, Vex, EXx } },
9348 /* VEX_W_0F63_P_2 */
9349 { "vpacksswb", { XM, Vex, EXx } },
9352 /* VEX_W_0F64_P_2 */
9353 { "vpcmpgtb", { XM, Vex, EXx } },
9356 /* VEX_W_0F65_P_2 */
9357 { "vpcmpgtw", { XM, Vex, EXx } },
9360 /* VEX_W_0F66_P_2 */
9361 { "vpcmpgtd", { XM, Vex, EXx } },
9364 /* VEX_W_0F67_P_2 */
9365 { "vpackuswb", { XM, Vex, EXx } },
9368 /* VEX_W_0F68_P_2 */
9369 { "vpunpckhbw", { XM, Vex, EXx } },
9372 /* VEX_W_0F69_P_2 */
9373 { "vpunpckhwd", { XM, Vex, EXx } },
9376 /* VEX_W_0F6A_P_2 */
9377 { "vpunpckhdq", { XM, Vex, EXx } },
9380 /* VEX_W_0F6B_P_2 */
9381 { "vpackssdw", { XM, Vex, EXx } },
9384 /* VEX_W_0F6C_P_2 */
9385 { "vpunpcklqdq", { XM, Vex, EXx } },
9388 /* VEX_W_0F6D_P_2 */
9389 { "vpunpckhqdq", { XM, Vex, EXx } },
9392 /* VEX_W_0F6F_P_1 */
9393 { "vmovdqu", { XM, EXx } },
9396 /* VEX_W_0F6F_P_2 */
9397 { "vmovdqa", { XM, EXx } },
9400 /* VEX_W_0F70_P_1 */
9401 { "vpshufhw", { XM, EXx, Ib } },
9404 /* VEX_W_0F70_P_2 */
9405 { "vpshufd", { XM, EXx, Ib } },
9408 /* VEX_W_0F70_P_3 */
9409 { "vpshuflw", { XM, EXx, Ib } },
9412 /* VEX_W_0F71_R_2_P_2 */
9413 { "vpsrlw", { Vex, XS, Ib } },
9416 /* VEX_W_0F71_R_4_P_2 */
9417 { "vpsraw", { Vex, XS, Ib } },
9420 /* VEX_W_0F71_R_6_P_2 */
9421 { "vpsllw", { Vex, XS, Ib } },
9424 /* VEX_W_0F72_R_2_P_2 */
9425 { "vpsrld", { Vex, XS, Ib } },
9428 /* VEX_W_0F72_R_4_P_2 */
9429 { "vpsrad", { Vex, XS, Ib } },
9432 /* VEX_W_0F72_R_6_P_2 */
9433 { "vpslld", { Vex, XS, Ib } },
9436 /* VEX_W_0F73_R_2_P_2 */
9437 { "vpsrlq", { Vex, XS, Ib } },
9440 /* VEX_W_0F73_R_3_P_2 */
9441 { "vpsrldq", { Vex, XS, Ib } },
9444 /* VEX_W_0F73_R_6_P_2 */
9445 { "vpsllq", { Vex, XS, Ib } },
9448 /* VEX_W_0F73_R_7_P_2 */
9449 { "vpslldq", { Vex, XS, Ib } },
9452 /* VEX_W_0F74_P_2 */
9453 { "vpcmpeqb", { XM, Vex, EXx } },
9456 /* VEX_W_0F75_P_2 */
9457 { "vpcmpeqw", { XM, Vex, EXx } },
9460 /* VEX_W_0F76_P_2 */
9461 { "vpcmpeqd", { XM, Vex, EXx } },
9464 /* VEX_W_0F77_P_0 */
9468 /* VEX_W_0F7C_P_2 */
9469 { "vhaddpd", { XM, Vex, EXx } },
9472 /* VEX_W_0F7C_P_3 */
9473 { "vhaddps", { XM, Vex, EXx } },
9476 /* VEX_W_0F7D_P_2 */
9477 { "vhsubpd", { XM, Vex, EXx } },
9480 /* VEX_W_0F7D_P_3 */
9481 { "vhsubps", { XM, Vex, EXx } },
9484 /* VEX_W_0F7E_P_1 */
9485 { "vmovq", { XMScalar, EXqScalar } },
9488 /* VEX_W_0F7F_P_1 */
9489 { "vmovdqu", { EXxS, XM } },
9492 /* VEX_W_0F7F_P_2 */
9493 { "vmovdqa", { EXxS, XM } },
9496 /* VEX_W_0FAE_R_2_M_0 */
9497 { "vldmxcsr", { Md } },
9500 /* VEX_W_0FAE_R_3_M_0 */
9501 { "vstmxcsr", { Md } },
9504 /* VEX_W_0FC2_P_0 */
9505 { "vcmpps", { XM, Vex, EXx, VCMP } },
9508 /* VEX_W_0FC2_P_1 */
9509 { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP } },
9512 /* VEX_W_0FC2_P_2 */
9513 { "vcmppd", { XM, Vex, EXx, VCMP } },
9516 /* VEX_W_0FC2_P_3 */
9517 { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP } },
9520 /* VEX_W_0FC4_P_2 */
9521 { "vpinsrw", { XM, Vex128, Edqw, Ib } },
9524 /* VEX_W_0FC5_P_2 */
9525 { "vpextrw", { Gdq, XS, Ib } },
9528 /* VEX_W_0FD0_P_2 */
9529 { "vaddsubpd", { XM, Vex, EXx } },
9532 /* VEX_W_0FD0_P_3 */
9533 { "vaddsubps", { XM, Vex, EXx } },
9536 /* VEX_W_0FD1_P_2 */
9537 { "vpsrlw", { XM, Vex, EXxmm } },
9540 /* VEX_W_0FD2_P_2 */
9541 { "vpsrld", { XM, Vex, EXxmm } },
9544 /* VEX_W_0FD3_P_2 */
9545 { "vpsrlq", { XM, Vex, EXxmm } },
9548 /* VEX_W_0FD4_P_2 */
9549 { "vpaddq", { XM, Vex, EXx } },
9552 /* VEX_W_0FD5_P_2 */
9553 { "vpmullw", { XM, Vex, EXx } },
9556 /* VEX_W_0FD6_P_2 */
9557 { "vmovq", { EXqScalarS, XMScalar } },
9560 /* VEX_W_0FD7_P_2_M_1 */
9561 { "vpmovmskb", { Gdq, XS } },
9564 /* VEX_W_0FD8_P_2 */
9565 { "vpsubusb", { XM, Vex, EXx } },
9568 /* VEX_W_0FD9_P_2 */
9569 { "vpsubusw", { XM, Vex, EXx } },
9572 /* VEX_W_0FDA_P_2 */
9573 { "vpminub", { XM, Vex, EXx } },
9576 /* VEX_W_0FDB_P_2 */
9577 { "vpand", { XM, Vex, EXx } },
9580 /* VEX_W_0FDC_P_2 */
9581 { "vpaddusb", { XM, Vex, EXx } },
9584 /* VEX_W_0FDD_P_2 */
9585 { "vpaddusw", { XM, Vex, EXx } },
9588 /* VEX_W_0FDE_P_2 */
9589 { "vpmaxub", { XM, Vex, EXx } },
9592 /* VEX_W_0FDF_P_2 */
9593 { "vpandn", { XM, Vex, EXx } },
9596 /* VEX_W_0FE0_P_2 */
9597 { "vpavgb", { XM, Vex, EXx } },
9600 /* VEX_W_0FE1_P_2 */
9601 { "vpsraw", { XM, Vex, EXxmm } },
9604 /* VEX_W_0FE2_P_2 */
9605 { "vpsrad", { XM, Vex, EXxmm } },
9608 /* VEX_W_0FE3_P_2 */
9609 { "vpavgw", { XM, Vex, EXx } },
9612 /* VEX_W_0FE4_P_2 */
9613 { "vpmulhuw", { XM, Vex, EXx } },
9616 /* VEX_W_0FE5_P_2 */
9617 { "vpmulhw", { XM, Vex, EXx } },
9620 /* VEX_W_0FE6_P_1 */
9621 { "vcvtdq2pd", { XM, EXxmmq } },
9624 /* VEX_W_0FE6_P_2 */
9625 { "vcvttpd2dq%XY", { XMM, EXx } },
9628 /* VEX_W_0FE6_P_3 */
9629 { "vcvtpd2dq%XY", { XMM, EXx } },
9632 /* VEX_W_0FE7_P_2_M_0 */
9633 { "vmovntdq", { Mx, XM } },
9636 /* VEX_W_0FE8_P_2 */
9637 { "vpsubsb", { XM, Vex, EXx } },
9640 /* VEX_W_0FE9_P_2 */
9641 { "vpsubsw", { XM, Vex, EXx } },
9644 /* VEX_W_0FEA_P_2 */
9645 { "vpminsw", { XM, Vex, EXx } },
9648 /* VEX_W_0FEB_P_2 */
9649 { "vpor", { XM, Vex, EXx } },
9652 /* VEX_W_0FEC_P_2 */
9653 { "vpaddsb", { XM, Vex, EXx } },
9656 /* VEX_W_0FED_P_2 */
9657 { "vpaddsw", { XM, Vex, EXx } },
9660 /* VEX_W_0FEE_P_2 */
9661 { "vpmaxsw", { XM, Vex, EXx } },
9664 /* VEX_W_0FEF_P_2 */
9665 { "vpxor", { XM, Vex, EXx } },
9668 /* VEX_W_0FF0_P_3_M_0 */
9669 { "vlddqu", { XM, M } },
9672 /* VEX_W_0FF1_P_2 */
9673 { "vpsllw", { XM, Vex, EXxmm } },
9676 /* VEX_W_0FF2_P_2 */
9677 { "vpslld", { XM, Vex, EXxmm } },
9680 /* VEX_W_0FF3_P_2 */
9681 { "vpsllq", { XM, Vex, EXxmm } },
9684 /* VEX_W_0FF4_P_2 */
9685 { "vpmuludq", { XM, Vex, EXx } },
9688 /* VEX_W_0FF5_P_2 */
9689 { "vpmaddwd", { XM, Vex, EXx } },
9692 /* VEX_W_0FF6_P_2 */
9693 { "vpsadbw", { XM, Vex, EXx } },
9696 /* VEX_W_0FF7_P_2 */
9697 { "vmaskmovdqu", { XM, XS } },
9700 /* VEX_W_0FF8_P_2 */
9701 { "vpsubb", { XM, Vex, EXx } },
9704 /* VEX_W_0FF9_P_2 */
9705 { "vpsubw", { XM, Vex, EXx } },
9708 /* VEX_W_0FFA_P_2 */
9709 { "vpsubd", { XM, Vex, EXx } },
9712 /* VEX_W_0FFB_P_2 */
9713 { "vpsubq", { XM, Vex, EXx } },
9716 /* VEX_W_0FFC_P_2 */
9717 { "vpaddb", { XM, Vex, EXx } },
9720 /* VEX_W_0FFD_P_2 */
9721 { "vpaddw", { XM, Vex, EXx } },
9724 /* VEX_W_0FFE_P_2 */
9725 { "vpaddd", { XM, Vex, EXx } },
9728 /* VEX_W_0F3800_P_2 */
9729 { "vpshufb", { XM, Vex, EXx } },
9732 /* VEX_W_0F3801_P_2 */
9733 { "vphaddw", { XM, Vex, EXx } },
9736 /* VEX_W_0F3802_P_2 */
9737 { "vphaddd", { XM, Vex, EXx } },
9740 /* VEX_W_0F3803_P_2 */
9741 { "vphaddsw", { XM, Vex, EXx } },
9744 /* VEX_W_0F3804_P_2 */
9745 { "vpmaddubsw", { XM, Vex, EXx } },
9748 /* VEX_W_0F3805_P_2 */
9749 { "vphsubw", { XM, Vex, EXx } },
9752 /* VEX_W_0F3806_P_2 */
9753 { "vphsubd", { XM, Vex, EXx } },
9756 /* VEX_W_0F3807_P_2 */
9757 { "vphsubsw", { XM, Vex, EXx } },
9760 /* VEX_W_0F3808_P_2 */
9761 { "vpsignb", { XM, Vex, EXx } },
9764 /* VEX_W_0F3809_P_2 */
9765 { "vpsignw", { XM, Vex, EXx } },
9768 /* VEX_W_0F380A_P_2 */
9769 { "vpsignd", { XM, Vex, EXx } },
9772 /* VEX_W_0F380B_P_2 */
9773 { "vpmulhrsw", { XM, Vex, EXx } },
9776 /* VEX_W_0F380C_P_2 */
9777 { "vpermilps", { XM, Vex, EXx } },
9780 /* VEX_W_0F380D_P_2 */
9781 { "vpermilpd", { XM, Vex, EXx } },
9784 /* VEX_W_0F380E_P_2 */
9785 { "vtestps", { XM, EXx } },
9788 /* VEX_W_0F380F_P_2 */
9789 { "vtestpd", { XM, EXx } },
9792 /* VEX_W_0F3816_P_2 */
9793 { "vpermps", { XM, Vex, EXx } },
9796 /* VEX_W_0F3817_P_2 */
9797 { "vptest", { XM, EXx } },
9800 /* VEX_W_0F3818_P_2 */
9801 { "vbroadcastss", { XM, EXxmm_md } },
9804 /* VEX_W_0F3819_P_2 */
9805 { "vbroadcastsd", { XM, EXxmm_mq } },
9808 /* VEX_W_0F381A_P_2_M_0 */
9809 { "vbroadcastf128", { XM, Mxmm } },
9812 /* VEX_W_0F381C_P_2 */
9813 { "vpabsb", { XM, EXx } },
9816 /* VEX_W_0F381D_P_2 */
9817 { "vpabsw", { XM, EXx } },
9820 /* VEX_W_0F381E_P_2 */
9821 { "vpabsd", { XM, EXx } },
9824 /* VEX_W_0F3820_P_2 */
9825 { "vpmovsxbw", { XM, EXxmmq } },
9828 /* VEX_W_0F3821_P_2 */
9829 { "vpmovsxbd", { XM, EXxmmqd } },
9832 /* VEX_W_0F3822_P_2 */
9833 { "vpmovsxbq", { XM, EXxmmdw } },
9836 /* VEX_W_0F3823_P_2 */
9837 { "vpmovsxwd", { XM, EXxmmq } },
9840 /* VEX_W_0F3824_P_2 */
9841 { "vpmovsxwq", { XM, EXxmmqd } },
9844 /* VEX_W_0F3825_P_2 */
9845 { "vpmovsxdq", { XM, EXxmmq } },
9848 /* VEX_W_0F3828_P_2 */
9849 { "vpmuldq", { XM, Vex, EXx } },
9852 /* VEX_W_0F3829_P_2 */
9853 { "vpcmpeqq", { XM, Vex, EXx } },
9856 /* VEX_W_0F382A_P_2_M_0 */
9857 { "vmovntdqa", { XM, Mx } },
9860 /* VEX_W_0F382B_P_2 */
9861 { "vpackusdw", { XM, Vex, EXx } },
9864 /* VEX_W_0F382C_P_2_M_0 */
9865 { "vmaskmovps", { XM, Vex, Mx } },
9868 /* VEX_W_0F382D_P_2_M_0 */
9869 { "vmaskmovpd", { XM, Vex, Mx } },
9872 /* VEX_W_0F382E_P_2_M_0 */
9873 { "vmaskmovps", { Mx, Vex, XM } },
9876 /* VEX_W_0F382F_P_2_M_0 */
9877 { "vmaskmovpd", { Mx, Vex, XM } },
9880 /* VEX_W_0F3830_P_2 */
9881 { "vpmovzxbw", { XM, EXxmmq } },
9884 /* VEX_W_0F3831_P_2 */
9885 { "vpmovzxbd", { XM, EXxmmqd } },
9888 /* VEX_W_0F3832_P_2 */
9889 { "vpmovzxbq", { XM, EXxmmdw } },
9892 /* VEX_W_0F3833_P_2 */
9893 { "vpmovzxwd", { XM, EXxmmq } },
9896 /* VEX_W_0F3834_P_2 */
9897 { "vpmovzxwq", { XM, EXxmmqd } },
9900 /* VEX_W_0F3835_P_2 */
9901 { "vpmovzxdq", { XM, EXxmmq } },
9904 /* VEX_W_0F3836_P_2 */
9905 { "vpermd", { XM, Vex, EXx } },
9908 /* VEX_W_0F3837_P_2 */
9909 { "vpcmpgtq", { XM, Vex, EXx } },
9912 /* VEX_W_0F3838_P_2 */
9913 { "vpminsb", { XM, Vex, EXx } },
9916 /* VEX_W_0F3839_P_2 */
9917 { "vpminsd", { XM, Vex, EXx } },
9920 /* VEX_W_0F383A_P_2 */
9921 { "vpminuw", { XM, Vex, EXx } },
9924 /* VEX_W_0F383B_P_2 */
9925 { "vpminud", { XM, Vex, EXx } },
9928 /* VEX_W_0F383C_P_2 */
9929 { "vpmaxsb", { XM, Vex, EXx } },
9932 /* VEX_W_0F383D_P_2 */
9933 { "vpmaxsd", { XM, Vex, EXx } },
9936 /* VEX_W_0F383E_P_2 */
9937 { "vpmaxuw", { XM, Vex, EXx } },
9940 /* VEX_W_0F383F_P_2 */
9941 { "vpmaxud", { XM, Vex, EXx } },
9944 /* VEX_W_0F3840_P_2 */
9945 { "vpmulld", { XM, Vex, EXx } },
9948 /* VEX_W_0F3841_P_2 */
9949 { "vphminposuw", { XM, EXx } },
9952 /* VEX_W_0F3846_P_2 */
9953 { "vpsravd", { XM, Vex, EXx } },
9956 /* VEX_W_0F3858_P_2 */
9957 { "vpbroadcastd", { XM, EXxmm_md } },
9960 /* VEX_W_0F3859_P_2 */
9961 { "vpbroadcastq", { XM, EXxmm_mq } },
9964 /* VEX_W_0F385A_P_2_M_0 */
9965 { "vbroadcasti128", { XM, Mxmm } },
9968 /* VEX_W_0F3878_P_2 */
9969 { "vpbroadcastb", { XM, EXxmm_mb } },
9972 /* VEX_W_0F3879_P_2 */
9973 { "vpbroadcastw", { XM, EXxmm_mw } },
9976 /* VEX_W_0F38DB_P_2 */
9977 { "vaesimc", { XM, EXx } },
9980 /* VEX_W_0F38DC_P_2 */
9981 { "vaesenc", { XM, Vex128, EXx } },
9984 /* VEX_W_0F38DD_P_2 */
9985 { "vaesenclast", { XM, Vex128, EXx } },
9988 /* VEX_W_0F38DE_P_2 */
9989 { "vaesdec", { XM, Vex128, EXx } },
9992 /* VEX_W_0F38DF_P_2 */
9993 { "vaesdeclast", { XM, Vex128, EXx } },
9996 /* VEX_W_0F3A00_P_2 */
9998 { "vpermq", { XM, EXx, Ib } },
10001 /* VEX_W_0F3A01_P_2 */
10003 { "vpermpd", { XM, EXx, Ib } },
10006 /* VEX_W_0F3A02_P_2 */
10007 { "vpblendd", { XM, Vex, EXx, Ib } },
10010 /* VEX_W_0F3A04_P_2 */
10011 { "vpermilps", { XM, EXx, Ib } },
10014 /* VEX_W_0F3A05_P_2 */
10015 { "vpermilpd", { XM, EXx, Ib } },
10018 /* VEX_W_0F3A06_P_2 */
10019 { "vperm2f128", { XM, Vex256, EXx, Ib } },
10022 /* VEX_W_0F3A08_P_2 */
10023 { "vroundps", { XM, EXx, Ib } },
10026 /* VEX_W_0F3A09_P_2 */
10027 { "vroundpd", { XM, EXx, Ib } },
10030 /* VEX_W_0F3A0A_P_2 */
10031 { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib } },
10034 /* VEX_W_0F3A0B_P_2 */
10035 { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib } },
10038 /* VEX_W_0F3A0C_P_2 */
10039 { "vblendps", { XM, Vex, EXx, Ib } },
10042 /* VEX_W_0F3A0D_P_2 */
10043 { "vblendpd", { XM, Vex, EXx, Ib } },
10046 /* VEX_W_0F3A0E_P_2 */
10047 { "vpblendw", { XM, Vex, EXx, Ib } },
10050 /* VEX_W_0F3A0F_P_2 */
10051 { "vpalignr", { XM, Vex, EXx, Ib } },
10054 /* VEX_W_0F3A14_P_2 */
10055 { "vpextrb", { Edqb, XM, Ib } },
10058 /* VEX_W_0F3A15_P_2 */
10059 { "vpextrw", { Edqw, XM, Ib } },
10062 /* VEX_W_0F3A18_P_2 */
10063 { "vinsertf128", { XM, Vex256, EXxmm, Ib } },
10066 /* VEX_W_0F3A19_P_2 */
10067 { "vextractf128", { EXxmm, XM, Ib } },
10070 /* VEX_W_0F3A20_P_2 */
10071 { "vpinsrb", { XM, Vex128, Edqb, Ib } },
10074 /* VEX_W_0F3A21_P_2 */
10075 { "vinsertps", { XM, Vex128, EXd, Ib } },
10078 /* VEX_W_0F3A38_P_2 */
10079 { "vinserti128", { XM, Vex256, EXxmm, Ib } },
10082 /* VEX_W_0F3A39_P_2 */
10083 { "vextracti128", { EXxmm, XM, Ib } },
10086 /* VEX_W_0F3A40_P_2 */
10087 { "vdpps", { XM, Vex, EXx, Ib } },
10090 /* VEX_W_0F3A41_P_2 */
10091 { "vdppd", { XM, Vex128, EXx, Ib } },
10094 /* VEX_W_0F3A42_P_2 */
10095 { "vmpsadbw", { XM, Vex, EXx, Ib } },
10098 /* VEX_W_0F3A44_P_2 */
10099 { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL } },
10102 /* VEX_W_0F3A46_P_2 */
10103 { "vperm2i128", { XM, Vex256, EXx, Ib } },
10106 /* VEX_W_0F3A48_P_2 */
10107 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10108 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10111 /* VEX_W_0F3A49_P_2 */
10112 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10113 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10116 /* VEX_W_0F3A4A_P_2 */
10117 { "vblendvps", { XM, Vex, EXx, XMVexI4 } },
10120 /* VEX_W_0F3A4B_P_2 */
10121 { "vblendvpd", { XM, Vex, EXx, XMVexI4 } },
10124 /* VEX_W_0F3A4C_P_2 */
10125 { "vpblendvb", { XM, Vex, EXx, XMVexI4 } },
10128 /* VEX_W_0F3A60_P_2 */
10129 { "vpcmpestrm", { XM, EXx, Ib } },
10132 /* VEX_W_0F3A61_P_2 */
10133 { "vpcmpestri", { XM, EXx, Ib } },
10136 /* VEX_W_0F3A62_P_2 */
10137 { "vpcmpistrm", { XM, EXx, Ib } },
10140 /* VEX_W_0F3A63_P_2 */
10141 { "vpcmpistri", { XM, EXx, Ib } },
10144 /* VEX_W_0F3ADF_P_2 */
10145 { "vaeskeygenassist", { XM, EXx, Ib } },
10149 static const struct dis386 mod_table[][2] = {
10152 { "leaS", { Gv, M } },
10157 { RM_TABLE (RM_C6_REG_7) },
10162 { RM_TABLE (RM_C7_REG_7) },
10165 /* MOD_0F01_REG_0 */
10166 { X86_64_TABLE (X86_64_0F01_REG_0) },
10167 { RM_TABLE (RM_0F01_REG_0) },
10170 /* MOD_0F01_REG_1 */
10171 { X86_64_TABLE (X86_64_0F01_REG_1) },
10172 { RM_TABLE (RM_0F01_REG_1) },
10175 /* MOD_0F01_REG_2 */
10176 { X86_64_TABLE (X86_64_0F01_REG_2) },
10177 { RM_TABLE (RM_0F01_REG_2) },
10180 /* MOD_0F01_REG_3 */
10181 { X86_64_TABLE (X86_64_0F01_REG_3) },
10182 { RM_TABLE (RM_0F01_REG_3) },
10185 /* MOD_0F01_REG_7 */
10186 { "invlpg", { Mb } },
10187 { RM_TABLE (RM_0F01_REG_7) },
10190 /* MOD_0F12_PREFIX_0 */
10191 { "movlps", { XM, EXq } },
10192 { "movhlps", { XM, EXq } },
10196 { "movlpX", { EXq, XM } },
10199 /* MOD_0F16_PREFIX_0 */
10200 { "movhps", { XM, EXq } },
10201 { "movlhps", { XM, EXq } },
10205 { "movhpX", { EXq, XM } },
10208 /* MOD_0F18_REG_0 */
10209 { "prefetchnta", { Mb } },
10212 /* MOD_0F18_REG_1 */
10213 { "prefetcht0", { Mb } },
10216 /* MOD_0F18_REG_2 */
10217 { "prefetcht1", { Mb } },
10220 /* MOD_0F18_REG_3 */
10221 { "prefetcht2", { Mb } },
10226 { "movZ", { Rm, Cm } },
10231 { "movZ", { Rm, Dm } },
10236 { "movZ", { Cm, Rm } },
10241 { "movZ", { Dm, Rm } },
10246 { "movL", { Rd, Td } },
10251 { "movL", { Td, Rd } },
10254 /* MOD_0F2B_PREFIX_0 */
10255 {"movntps", { Mx, XM } },
10258 /* MOD_0F2B_PREFIX_1 */
10259 {"movntss", { Md, XM } },
10262 /* MOD_0F2B_PREFIX_2 */
10263 {"movntpd", { Mx, XM } },
10266 /* MOD_0F2B_PREFIX_3 */
10267 {"movntsd", { Mq, XM } },
10272 { "movmskpX", { Gdq, XS } },
10275 /* MOD_0F71_REG_2 */
10277 { "psrlw", { MS, Ib } },
10280 /* MOD_0F71_REG_4 */
10282 { "psraw", { MS, Ib } },
10285 /* MOD_0F71_REG_6 */
10287 { "psllw", { MS, Ib } },
10290 /* MOD_0F72_REG_2 */
10292 { "psrld", { MS, Ib } },
10295 /* MOD_0F72_REG_4 */
10297 { "psrad", { MS, Ib } },
10300 /* MOD_0F72_REG_6 */
10302 { "pslld", { MS, Ib } },
10305 /* MOD_0F73_REG_2 */
10307 { "psrlq", { MS, Ib } },
10310 /* MOD_0F73_REG_3 */
10312 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10315 /* MOD_0F73_REG_6 */
10317 { "psllq", { MS, Ib } },
10320 /* MOD_0F73_REG_7 */
10322 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10325 /* MOD_0FAE_REG_0 */
10326 { "fxsave", { FXSAVE } },
10327 { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
10330 /* MOD_0FAE_REG_1 */
10331 { "fxrstor", { FXSAVE } },
10332 { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
10335 /* MOD_0FAE_REG_2 */
10336 { "ldmxcsr", { Md } },
10337 { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
10340 /* MOD_0FAE_REG_3 */
10341 { "stmxcsr", { Md } },
10342 { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
10345 /* MOD_0FAE_REG_4 */
10346 { "xsave", { FXSAVE } },
10349 /* MOD_0FAE_REG_5 */
10350 { "xrstor", { FXSAVE } },
10351 { RM_TABLE (RM_0FAE_REG_5) },
10354 /* MOD_0FAE_REG_6 */
10355 { "xsaveopt", { FXSAVE } },
10356 { RM_TABLE (RM_0FAE_REG_6) },
10359 /* MOD_0FAE_REG_7 */
10360 { "clflush", { Mb } },
10361 { RM_TABLE (RM_0FAE_REG_7) },
10365 { "lssS", { Gv, Mp } },
10369 { "lfsS", { Gv, Mp } },
10373 { "lgsS", { Gv, Mp } },
10376 /* MOD_0FC7_REG_6 */
10377 { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
10378 { "rdrand", { Ev } },
10381 /* MOD_0FC7_REG_7 */
10382 { "vmptrst", { Mq } },
10383 { "rdseed", { Ev } },
10388 { "pmovmskb", { Gdq, MS } },
10391 /* MOD_0FE7_PREFIX_2 */
10392 { "movntdq", { Mx, XM } },
10395 /* MOD_0FF0_PREFIX_3 */
10396 { "lddqu", { XM, M } },
10399 /* MOD_0F382A_PREFIX_2 */
10400 { "movntdqa", { XM, Mx } },
10404 { "bound{S|}", { Gv, Ma } },
10408 { "lesS", { Gv, Mp } },
10409 { VEX_C4_TABLE (VEX_0F) },
10413 { "ldsS", { Gv, Mp } },
10414 { VEX_C5_TABLE (VEX_0F) },
10417 /* MOD_VEX_0F12_PREFIX_0 */
10418 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10419 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10423 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10426 /* MOD_VEX_0F16_PREFIX_0 */
10427 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10428 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10432 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10436 { VEX_W_TABLE (VEX_W_0F2B_M_0) },
10441 { VEX_W_TABLE (VEX_W_0F50_M_0) },
10444 /* MOD_VEX_0F71_REG_2 */
10446 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10449 /* MOD_VEX_0F71_REG_4 */
10451 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10454 /* MOD_VEX_0F71_REG_6 */
10456 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10459 /* MOD_VEX_0F72_REG_2 */
10461 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10464 /* MOD_VEX_0F72_REG_4 */
10466 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10469 /* MOD_VEX_0F72_REG_6 */
10471 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10474 /* MOD_VEX_0F73_REG_2 */
10476 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10479 /* MOD_VEX_0F73_REG_3 */
10481 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10484 /* MOD_VEX_0F73_REG_6 */
10486 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10489 /* MOD_VEX_0F73_REG_7 */
10491 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10494 /* MOD_VEX_0FAE_REG_2 */
10495 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10498 /* MOD_VEX_0FAE_REG_3 */
10499 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10502 /* MOD_VEX_0FD7_PREFIX_2 */
10504 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
10507 /* MOD_VEX_0FE7_PREFIX_2 */
10508 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
10511 /* MOD_VEX_0FF0_PREFIX_3 */
10512 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
10515 /* MOD_VEX_0F381A_PREFIX_2 */
10516 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10519 /* MOD_VEX_0F382A_PREFIX_2 */
10520 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
10523 /* MOD_VEX_0F382C_PREFIX_2 */
10524 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10527 /* MOD_VEX_0F382D_PREFIX_2 */
10528 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10531 /* MOD_VEX_0F382E_PREFIX_2 */
10532 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10535 /* MOD_VEX_0F382F_PREFIX_2 */
10536 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10539 /* MOD_VEX_0F385A_PREFIX_2 */
10540 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10543 /* MOD_VEX_0F388C_PREFIX_2 */
10544 { "vpmaskmov%LW", { XM, Vex, Mx } },
10547 /* MOD_VEX_0F388E_PREFIX_2 */
10548 { "vpmaskmov%LW", { Mx, Vex, XM } },
10552 static const struct dis386 rm_table[][8] = {
10555 { "xabort", { Skip_MODRM, Ib } },
10559 { "xbeginT", { Skip_MODRM, Jv } },
10562 /* RM_0F01_REG_0 */
10564 { "vmcall", { Skip_MODRM } },
10565 { "vmlaunch", { Skip_MODRM } },
10566 { "vmresume", { Skip_MODRM } },
10567 { "vmxoff", { Skip_MODRM } },
10570 /* RM_0F01_REG_1 */
10571 { "monitor", { { OP_Monitor, 0 } } },
10572 { "mwait", { { OP_Mwait, 0 } } },
10575 /* RM_0F01_REG_2 */
10576 { "xgetbv", { Skip_MODRM } },
10577 { "xsetbv", { Skip_MODRM } },
10580 { "vmfunc", { Skip_MODRM } },
10581 { "xend", { Skip_MODRM } },
10582 { "xtest", { Skip_MODRM } },
10586 /* RM_0F01_REG_3 */
10587 { "vmrun", { Skip_MODRM } },
10588 { "vmmcall", { Skip_MODRM } },
10589 { "vmload", { Skip_MODRM } },
10590 { "vmsave", { Skip_MODRM } },
10591 { "stgi", { Skip_MODRM } },
10592 { "clgi", { Skip_MODRM } },
10593 { "skinit", { Skip_MODRM } },
10594 { "invlpga", { Skip_MODRM } },
10597 /* RM_0F01_REG_7 */
10598 { "swapgs", { Skip_MODRM } },
10599 { "rdtscp", { Skip_MODRM } },
10602 /* RM_0FAE_REG_5 */
10603 { "lfence", { Skip_MODRM } },
10606 /* RM_0FAE_REG_6 */
10607 { "mfence", { Skip_MODRM } },
10610 /* RM_0FAE_REG_7 */
10611 { "sfence", { Skip_MODRM } },
10615 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
10617 /* We use the high bit to indicate different name for the same
10619 #define ADDR16_PREFIX (0x67 | 0x100)
10620 #define ADDR32_PREFIX (0x67 | 0x200)
10621 #define DATA16_PREFIX (0x66 | 0x100)
10622 #define DATA32_PREFIX (0x66 | 0x200)
10623 #define REP_PREFIX (0xf3 | 0x100)
10624 #define XACQUIRE_PREFIX (0xf2 | 0x200)
10625 #define XRELEASE_PREFIX (0xf3 | 0x400)
10630 int newrex, i, length;
10636 last_lock_prefix = -1;
10637 last_repz_prefix = -1;
10638 last_repnz_prefix = -1;
10639 last_data_prefix = -1;
10640 last_addr_prefix = -1;
10641 last_rex_prefix = -1;
10642 last_seg_prefix = -1;
10643 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10644 all_prefixes[i] = 0;
10647 /* The maximum instruction length is 15bytes. */
10648 while (length < MAX_CODE_LENGTH - 1)
10650 FETCH_DATA (the_info, codep + 1);
10654 /* REX prefixes family. */
10671 if (address_mode == mode_64bit)
10675 last_rex_prefix = i;
10678 prefixes |= PREFIX_REPZ;
10679 last_repz_prefix = i;
10682 prefixes |= PREFIX_REPNZ;
10683 last_repnz_prefix = i;
10686 prefixes |= PREFIX_LOCK;
10687 last_lock_prefix = i;
10690 prefixes |= PREFIX_CS;
10691 last_seg_prefix = i;
10694 prefixes |= PREFIX_SS;
10695 last_seg_prefix = i;
10698 prefixes |= PREFIX_DS;
10699 last_seg_prefix = i;
10702 prefixes |= PREFIX_ES;
10703 last_seg_prefix = i;
10706 prefixes |= PREFIX_FS;
10707 last_seg_prefix = i;
10710 prefixes |= PREFIX_GS;
10711 last_seg_prefix = i;
10714 prefixes |= PREFIX_DATA;
10715 last_data_prefix = i;
10718 prefixes |= PREFIX_ADDR;
10719 last_addr_prefix = i;
10722 /* fwait is really an instruction. If there are prefixes
10723 before the fwait, they belong to the fwait, *not* to the
10724 following instruction. */
10725 if (prefixes || rex)
10727 prefixes |= PREFIX_FWAIT;
10731 prefixes = PREFIX_FWAIT;
10736 /* Rex is ignored when followed by another prefix. */
10742 if (*codep != FWAIT_OPCODE)
10743 all_prefixes[i++] = *codep;
10752 seg_prefix (int pref)
10773 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
10776 static const char *
10777 prefix_name (int pref, int sizeflag)
10779 static const char *rexes [16] =
10782 "rex.B", /* 0x41 */
10783 "rex.X", /* 0x42 */
10784 "rex.XB", /* 0x43 */
10785 "rex.R", /* 0x44 */
10786 "rex.RB", /* 0x45 */
10787 "rex.RX", /* 0x46 */
10788 "rex.RXB", /* 0x47 */
10789 "rex.W", /* 0x48 */
10790 "rex.WB", /* 0x49 */
10791 "rex.WX", /* 0x4a */
10792 "rex.WXB", /* 0x4b */
10793 "rex.WR", /* 0x4c */
10794 "rex.WRB", /* 0x4d */
10795 "rex.WRX", /* 0x4e */
10796 "rex.WRXB", /* 0x4f */
10801 /* REX prefixes family. */
10818 return rexes [pref - 0x40];
10838 return (sizeflag & DFLAG) ? "data16" : "data32";
10840 if (address_mode == mode_64bit)
10841 return (sizeflag & AFLAG) ? "addr32" : "addr64";
10843 return (sizeflag & AFLAG) ? "addr16" : "addr32";
10846 case ADDR16_PREFIX:
10848 case ADDR32_PREFIX:
10850 case DATA16_PREFIX:
10852 case DATA32_PREFIX:
10856 case XACQUIRE_PREFIX:
10858 case XRELEASE_PREFIX:
10865 static char op_out[MAX_OPERANDS][100];
10866 static int op_ad, op_index[MAX_OPERANDS];
10867 static int two_source_ops;
10868 static bfd_vma op_address[MAX_OPERANDS];
10869 static bfd_vma op_riprel[MAX_OPERANDS];
10870 static bfd_vma start_pc;
10873 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
10874 * (see topic "Redundant prefixes" in the "Differences from 8086"
10875 * section of the "Virtual 8086 Mode" chapter.)
10876 * 'pc' should be the address of this instruction, it will
10877 * be used to print the target address if this is a relative jump or call
10878 * The function returns the length of this instruction in bytes.
10881 static char intel_syntax;
10882 static char intel_mnemonic = !SYSV386_COMPAT;
10883 static char open_char;
10884 static char close_char;
10885 static char separator_char;
10886 static char scale_char;
10888 /* Here for backwards compatibility. When gdb stops using
10889 print_insn_i386_att and print_insn_i386_intel these functions can
10890 disappear, and print_insn_i386 be merged into print_insn. */
10892 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
10896 return print_insn (pc, info);
10900 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
10904 return print_insn (pc, info);
10908 print_insn_i386 (bfd_vma pc, disassemble_info *info)
10912 return print_insn (pc, info);
10916 print_i386_disassembler_options (FILE *stream)
10918 fprintf (stream, _("\n\
10919 The following i386/x86-64 specific disassembler options are supported for use\n\
10920 with the -M switch (multiple options should be separated by commas):\n"));
10922 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
10923 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
10924 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
10925 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
10926 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
10927 fprintf (stream, _(" att-mnemonic\n"
10928 " Display instruction in AT&T mnemonic\n"));
10929 fprintf (stream, _(" intel-mnemonic\n"
10930 " Display instruction in Intel mnemonic\n"));
10931 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
10932 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
10933 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
10934 fprintf (stream, _(" data32 Assume 32bit data size\n"));
10935 fprintf (stream, _(" data16 Assume 16bit data size\n"));
10936 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
10940 static const struct dis386 bad_opcode = { "(bad)", { XX } };
10942 /* Get a pointer to struct dis386 with a valid name. */
10944 static const struct dis386 *
10945 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
10947 int vindex, vex_table_index;
10949 if (dp->name != NULL)
10952 switch (dp->op[0].bytemode)
10954 case USE_REG_TABLE:
10955 dp = ®_table[dp->op[1].bytemode][modrm.reg];
10958 case USE_MOD_TABLE:
10959 vindex = modrm.mod == 0x3 ? 1 : 0;
10960 dp = &mod_table[dp->op[1].bytemode][vindex];
10964 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
10967 case USE_PREFIX_TABLE:
10970 /* The prefix in VEX is implicit. */
10971 switch (vex.prefix)
10976 case REPE_PREFIX_OPCODE:
10979 case DATA_PREFIX_OPCODE:
10982 case REPNE_PREFIX_OPCODE:
10993 used_prefixes |= (prefixes & PREFIX_REPZ);
10994 if (prefixes & PREFIX_REPZ)
10997 all_prefixes[last_repz_prefix] = 0;
11001 /* We should check PREFIX_REPNZ and PREFIX_REPZ before
11003 used_prefixes |= (prefixes & PREFIX_REPNZ);
11004 if (prefixes & PREFIX_REPNZ)
11007 all_prefixes[last_repnz_prefix] = 0;
11011 used_prefixes |= (prefixes & PREFIX_DATA);
11012 if (prefixes & PREFIX_DATA)
11015 all_prefixes[last_data_prefix] = 0;
11020 dp = &prefix_table[dp->op[1].bytemode][vindex];
11023 case USE_X86_64_TABLE:
11024 vindex = address_mode == mode_64bit ? 1 : 0;
11025 dp = &x86_64_table[dp->op[1].bytemode][vindex];
11028 case USE_3BYTE_TABLE:
11029 FETCH_DATA (info, codep + 2);
11031 dp = &three_byte_table[dp->op[1].bytemode][vindex];
11032 modrm.mod = (*codep >> 6) & 3;
11033 modrm.reg = (*codep >> 3) & 7;
11034 modrm.rm = *codep & 7;
11037 case USE_VEX_LEN_TABLE:
11041 switch (vex.length)
11054 dp = &vex_len_table[dp->op[1].bytemode][vindex];
11057 case USE_XOP_8F_TABLE:
11058 FETCH_DATA (info, codep + 3);
11059 /* All bits in the REX prefix are ignored. */
11061 rex = ~(*codep >> 5) & 0x7;
11063 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
11064 switch ((*codep & 0x1f))
11070 vex_table_index = XOP_08;
11073 vex_table_index = XOP_09;
11076 vex_table_index = XOP_0A;
11080 vex.w = *codep & 0x80;
11081 if (vex.w && address_mode == mode_64bit)
11084 vex.register_specifier = (~(*codep >> 3)) & 0xf;
11085 if (address_mode != mode_64bit
11086 && vex.register_specifier > 0x7)
11092 vex.length = (*codep & 0x4) ? 256 : 128;
11093 switch ((*codep & 0x3))
11099 vex.prefix = DATA_PREFIX_OPCODE;
11102 vex.prefix = REPE_PREFIX_OPCODE;
11105 vex.prefix = REPNE_PREFIX_OPCODE;
11112 dp = &xop_table[vex_table_index][vindex];
11114 FETCH_DATA (info, codep + 1);
11115 modrm.mod = (*codep >> 6) & 3;
11116 modrm.reg = (*codep >> 3) & 7;
11117 modrm.rm = *codep & 7;
11120 case USE_VEX_C4_TABLE:
11121 FETCH_DATA (info, codep + 3);
11122 /* All bits in the REX prefix are ignored. */
11124 rex = ~(*codep >> 5) & 0x7;
11125 switch ((*codep & 0x1f))
11131 vex_table_index = VEX_0F;
11134 vex_table_index = VEX_0F38;
11137 vex_table_index = VEX_0F3A;
11141 vex.w = *codep & 0x80;
11142 if (vex.w && address_mode == mode_64bit)
11145 vex.register_specifier = (~(*codep >> 3)) & 0xf;
11146 if (address_mode != mode_64bit
11147 && vex.register_specifier > 0x7)
11153 vex.length = (*codep & 0x4) ? 256 : 128;
11154 switch ((*codep & 0x3))
11160 vex.prefix = DATA_PREFIX_OPCODE;
11163 vex.prefix = REPE_PREFIX_OPCODE;
11166 vex.prefix = REPNE_PREFIX_OPCODE;
11173 dp = &vex_table[vex_table_index][vindex];
11174 /* There is no MODRM byte for VEX [82|77]. */
11175 if (vindex != 0x77 && vindex != 0x82)
11177 FETCH_DATA (info, codep + 1);
11178 modrm.mod = (*codep >> 6) & 3;
11179 modrm.reg = (*codep >> 3) & 7;
11180 modrm.rm = *codep & 7;
11184 case USE_VEX_C5_TABLE:
11185 FETCH_DATA (info, codep + 2);
11186 /* All bits in the REX prefix are ignored. */
11188 rex = (*codep & 0x80) ? 0 : REX_R;
11190 vex.register_specifier = (~(*codep >> 3)) & 0xf;
11191 if (address_mode != mode_64bit
11192 && vex.register_specifier > 0x7)
11200 vex.length = (*codep & 0x4) ? 256 : 128;
11201 switch ((*codep & 0x3))
11207 vex.prefix = DATA_PREFIX_OPCODE;
11210 vex.prefix = REPE_PREFIX_OPCODE;
11213 vex.prefix = REPNE_PREFIX_OPCODE;
11220 dp = &vex_table[dp->op[1].bytemode][vindex];
11221 /* There is no MODRM byte for VEX [82|77]. */
11222 if (vindex != 0x77 && vindex != 0x82)
11224 FETCH_DATA (info, codep + 1);
11225 modrm.mod = (*codep >> 6) & 3;
11226 modrm.reg = (*codep >> 3) & 7;
11227 modrm.rm = *codep & 7;
11231 case USE_VEX_W_TABLE:
11235 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11246 if (dp->name != NULL)
11249 return get_valid_dis386 (dp, info);
11253 get_sib (disassemble_info *info)
11255 /* If modrm.mod == 3, operand must be register. */
11257 && address_mode != mode_16bit
11261 FETCH_DATA (info, codep + 2);
11262 sib.index = (codep [1] >> 3) & 7;
11263 sib.scale = (codep [1] >> 6) & 3;
11264 sib.base = codep [1] & 7;
11269 print_insn (bfd_vma pc, disassemble_info *info)
11271 const struct dis386 *dp;
11273 char *op_txt[MAX_OPERANDS];
11277 struct dis_private priv;
11279 int default_prefixes;
11281 priv.orig_sizeflag = AFLAG | DFLAG;
11282 if ((info->mach & bfd_mach_i386_i386) != 0)
11283 address_mode = mode_32bit;
11284 else if (info->mach == bfd_mach_i386_i8086)
11286 address_mode = mode_16bit;
11287 priv.orig_sizeflag = 0;
11290 address_mode = mode_64bit;
11292 if (intel_syntax == (char) -1)
11293 intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11295 for (p = info->disassembler_options; p != NULL; )
11297 if (CONST_STRNEQ (p, "x86-64"))
11299 address_mode = mode_64bit;
11300 priv.orig_sizeflag = AFLAG | DFLAG;
11302 else if (CONST_STRNEQ (p, "i386"))
11304 address_mode = mode_32bit;
11305 priv.orig_sizeflag = AFLAG | DFLAG;
11307 else if (CONST_STRNEQ (p, "i8086"))
11309 address_mode = mode_16bit;
11310 priv.orig_sizeflag = 0;
11312 else if (CONST_STRNEQ (p, "intel"))
11315 if (CONST_STRNEQ (p + 5, "-mnemonic"))
11316 intel_mnemonic = 1;
11318 else if (CONST_STRNEQ (p, "att"))
11321 if (CONST_STRNEQ (p + 3, "-mnemonic"))
11322 intel_mnemonic = 0;
11324 else if (CONST_STRNEQ (p, "addr"))
11326 if (address_mode == mode_64bit)
11328 if (p[4] == '3' && p[5] == '2')
11329 priv.orig_sizeflag &= ~AFLAG;
11330 else if (p[4] == '6' && p[5] == '4')
11331 priv.orig_sizeflag |= AFLAG;
11335 if (p[4] == '1' && p[5] == '6')
11336 priv.orig_sizeflag &= ~AFLAG;
11337 else if (p[4] == '3' && p[5] == '2')
11338 priv.orig_sizeflag |= AFLAG;
11341 else if (CONST_STRNEQ (p, "data"))
11343 if (p[4] == '1' && p[5] == '6')
11344 priv.orig_sizeflag &= ~DFLAG;
11345 else if (p[4] == '3' && p[5] == '2')
11346 priv.orig_sizeflag |= DFLAG;
11348 else if (CONST_STRNEQ (p, "suffix"))
11349 priv.orig_sizeflag |= SUFFIX_ALWAYS;
11351 p = strchr (p, ',');
11358 names64 = intel_names64;
11359 names32 = intel_names32;
11360 names16 = intel_names16;
11361 names8 = intel_names8;
11362 names8rex = intel_names8rex;
11363 names_seg = intel_names_seg;
11364 names_mm = intel_names_mm;
11365 names_xmm = intel_names_xmm;
11366 names_ymm = intel_names_ymm;
11367 index64 = intel_index64;
11368 index32 = intel_index32;
11369 index16 = intel_index16;
11372 separator_char = '+';
11377 names64 = att_names64;
11378 names32 = att_names32;
11379 names16 = att_names16;
11380 names8 = att_names8;
11381 names8rex = att_names8rex;
11382 names_seg = att_names_seg;
11383 names_mm = att_names_mm;
11384 names_xmm = att_names_xmm;
11385 names_ymm = att_names_ymm;
11386 index64 = att_index64;
11387 index32 = att_index32;
11388 index16 = att_index16;
11391 separator_char = ',';
11395 /* The output looks better if we put 7 bytes on a line, since that
11396 puts most long word instructions on a single line. Use 8 bytes
11398 if ((info->mach & bfd_mach_l1om) != 0)
11399 info->bytes_per_line = 8;
11401 info->bytes_per_line = 7;
11403 info->private_data = &priv;
11404 priv.max_fetched = priv.the_buffer;
11405 priv.insn_start = pc;
11408 for (i = 0; i < MAX_OPERANDS; ++i)
11416 start_codep = priv.the_buffer;
11417 codep = priv.the_buffer;
11419 if (setjmp (priv.bailout) != 0)
11423 /* Getting here means we tried for data but didn't get it. That
11424 means we have an incomplete instruction of some sort. Just
11425 print the first byte as a prefix or a .byte pseudo-op. */
11426 if (codep > priv.the_buffer)
11428 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
11430 (*info->fprintf_func) (info->stream, "%s", name);
11433 /* Just print the first byte as a .byte instruction. */
11434 (*info->fprintf_func) (info->stream, ".byte 0x%x",
11435 (unsigned int) priv.the_buffer[0]);
11445 sizeflag = priv.orig_sizeflag;
11447 if (!ckprefix () || rex_used)
11449 /* Too many prefixes or unused REX prefixes. */
11451 i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
11453 (*info->fprintf_func) (info->stream, "%s",
11454 prefix_name (all_prefixes[i], sizeflag));
11458 insn_codep = codep;
11460 FETCH_DATA (info, codep + 1);
11461 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
11463 if (((prefixes & PREFIX_FWAIT)
11464 && ((*codep < 0xd8) || (*codep > 0xdf))))
11466 (*info->fprintf_func) (info->stream, "fwait");
11470 if (*codep == 0x0f)
11472 unsigned char threebyte;
11473 FETCH_DATA (info, codep + 2);
11474 threebyte = *++codep;
11475 dp = &dis386_twobyte[threebyte];
11476 need_modrm = twobyte_has_modrm[*codep];
11481 dp = &dis386[*codep];
11482 need_modrm = onebyte_has_modrm[*codep];
11486 if ((prefixes & PREFIX_REPZ))
11487 used_prefixes |= PREFIX_REPZ;
11488 if ((prefixes & PREFIX_REPNZ))
11489 used_prefixes |= PREFIX_REPNZ;
11490 if ((prefixes & PREFIX_LOCK))
11491 used_prefixes |= PREFIX_LOCK;
11493 default_prefixes = 0;
11494 if (prefixes & PREFIX_ADDR)
11497 if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
11499 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11500 all_prefixes[last_addr_prefix] = ADDR32_PREFIX;
11502 all_prefixes[last_addr_prefix] = ADDR16_PREFIX;
11503 default_prefixes |= PREFIX_ADDR;
11507 if ((prefixes & PREFIX_DATA))
11510 if (dp->op[2].bytemode == cond_jump_mode
11511 && dp->op[0].bytemode == v_mode
11514 if (sizeflag & DFLAG)
11515 all_prefixes[last_data_prefix] = DATA32_PREFIX;
11517 all_prefixes[last_data_prefix] = DATA16_PREFIX;
11518 default_prefixes |= PREFIX_DATA;
11520 else if (rex & REX_W)
11522 /* REX_W will override PREFIX_DATA. */
11523 default_prefixes |= PREFIX_DATA;
11529 FETCH_DATA (info, codep + 1);
11530 modrm.mod = (*codep >> 6) & 3;
11531 modrm.reg = (*codep >> 3) & 7;
11532 modrm.rm = *codep & 7;
11539 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
11542 dofloat (sizeflag);
11546 dp = get_valid_dis386 (dp, info);
11547 if (dp != NULL && putop (dp->name, sizeflag) == 0)
11550 for (i = 0; i < MAX_OPERANDS; ++i)
11553 op_ad = MAX_OPERANDS - 1 - i;
11555 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
11560 /* See if any prefixes were not used. If so, print the first one
11561 separately. If we don't do this, we'll wind up printing an
11562 instruction stream which does not precisely correspond to the
11563 bytes we are disassembling. */
11564 if ((prefixes & ~(used_prefixes | default_prefixes)) != 0)
11566 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11567 if (all_prefixes[i])
11570 name = prefix_name (all_prefixes[i], priv.orig_sizeflag);
11572 name = INTERNAL_DISASSEMBLER_ERROR;
11573 (*info->fprintf_func) (info->stream, "%s", name);
11578 /* Check if the REX prefix is used. */
11579 if (rex_ignored == 0 && (rex ^ rex_used) == 0)
11580 all_prefixes[last_rex_prefix] = 0;
11582 /* Check if the SEG prefix is used. */
11583 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
11584 | PREFIX_FS | PREFIX_GS)) != 0
11586 & seg_prefix (all_prefixes[last_seg_prefix])) != 0)
11587 all_prefixes[last_seg_prefix] = 0;
11589 /* Check if the ADDR prefix is used. */
11590 if ((prefixes & PREFIX_ADDR) != 0
11591 && (used_prefixes & PREFIX_ADDR) != 0)
11592 all_prefixes[last_addr_prefix] = 0;
11594 /* Check if the DATA prefix is used. */
11595 if ((prefixes & PREFIX_DATA) != 0
11596 && (used_prefixes & PREFIX_DATA) != 0)
11597 all_prefixes[last_data_prefix] = 0;
11600 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11601 if (all_prefixes[i])
11604 name = prefix_name (all_prefixes[i], sizeflag);
11607 prefix_length += strlen (name) + 1;
11608 (*info->fprintf_func) (info->stream, "%s ", name);
11611 /* Check maximum code length. */
11612 if ((codep - start_codep) > MAX_CODE_LENGTH)
11614 (*info->fprintf_func) (info->stream, "(bad)");
11615 return MAX_CODE_LENGTH;
11618 obufp = mnemonicendp;
11619 for (i = strlen (obuf) + prefix_length; i < 6; i++)
11622 (*info->fprintf_func) (info->stream, "%s", obuf);
11624 /* The enter and bound instructions are printed with operands in the same
11625 order as the intel book; everything else is printed in reverse order. */
11626 if (intel_syntax || two_source_ops)
11630 for (i = 0; i < MAX_OPERANDS; ++i)
11631 op_txt[i] = op_out[i];
11633 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
11635 op_ad = op_index[i];
11636 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
11637 op_index[MAX_OPERANDS - 1 - i] = op_ad;
11638 riprel = op_riprel[i];
11639 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
11640 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
11645 for (i = 0; i < MAX_OPERANDS; ++i)
11646 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
11650 for (i = 0; i < MAX_OPERANDS; ++i)
11654 (*info->fprintf_func) (info->stream, ",");
11655 if (op_index[i] != -1 && !op_riprel[i])
11656 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
11658 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
11662 for (i = 0; i < MAX_OPERANDS; i++)
11663 if (op_index[i] != -1 && op_riprel[i])
11665 (*info->fprintf_func) (info->stream, " # ");
11666 (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
11667 + op_address[op_index[i]]), info);
11670 return codep - priv.the_buffer;
11673 static const char *float_mem[] = {
11748 static const unsigned char float_mem_mode[] = {
11823 #define ST { OP_ST, 0 }
11824 #define STi { OP_STi, 0 }
11826 #define FGRPd9_2 NULL, { { NULL, 0 } }
11827 #define FGRPd9_4 NULL, { { NULL, 1 } }
11828 #define FGRPd9_5 NULL, { { NULL, 2 } }
11829 #define FGRPd9_6 NULL, { { NULL, 3 } }
11830 #define FGRPd9_7 NULL, { { NULL, 4 } }
11831 #define FGRPda_5 NULL, { { NULL, 5 } }
11832 #define FGRPdb_4 NULL, { { NULL, 6 } }
11833 #define FGRPde_3 NULL, { { NULL, 7 } }
11834 #define FGRPdf_4 NULL, { { NULL, 8 } }
11836 static const struct dis386 float_reg[][8] = {
11839 { "fadd", { ST, STi } },
11840 { "fmul", { ST, STi } },
11841 { "fcom", { STi } },
11842 { "fcomp", { STi } },
11843 { "fsub", { ST, STi } },
11844 { "fsubr", { ST, STi } },
11845 { "fdiv", { ST, STi } },
11846 { "fdivr", { ST, STi } },
11850 { "fld", { STi } },
11851 { "fxch", { STi } },
11861 { "fcmovb", { ST, STi } },
11862 { "fcmove", { ST, STi } },
11863 { "fcmovbe",{ ST, STi } },
11864 { "fcmovu", { ST, STi } },
11872 { "fcmovnb",{ ST, STi } },
11873 { "fcmovne",{ ST, STi } },
11874 { "fcmovnbe",{ ST, STi } },
11875 { "fcmovnu",{ ST, STi } },
11877 { "fucomi", { ST, STi } },
11878 { "fcomi", { ST, STi } },
11883 { "fadd", { STi, ST } },
11884 { "fmul", { STi, ST } },
11887 { "fsub!M", { STi, ST } },
11888 { "fsubM", { STi, ST } },
11889 { "fdiv!M", { STi, ST } },
11890 { "fdivM", { STi, ST } },
11894 { "ffree", { STi } },
11896 { "fst", { STi } },
11897 { "fstp", { STi } },
11898 { "fucom", { STi } },
11899 { "fucomp", { STi } },
11905 { "faddp", { STi, ST } },
11906 { "fmulp", { STi, ST } },
11909 { "fsub!Mp", { STi, ST } },
11910 { "fsubMp", { STi, ST } },
11911 { "fdiv!Mp", { STi, ST } },
11912 { "fdivMp", { STi, ST } },
11916 { "ffreep", { STi } },
11921 { "fucomip", { ST, STi } },
11922 { "fcomip", { ST, STi } },
11927 static char *fgrps[][8] = {
11930 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11935 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
11940 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
11945 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
11950 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
11955 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11960 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
11961 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
11966 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11971 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11976 swap_operand (void)
11978 mnemonicendp[0] = '.';
11979 mnemonicendp[1] = 's';
11984 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
11985 int sizeflag ATTRIBUTE_UNUSED)
11987 /* Skip mod/rm byte. */
11993 dofloat (int sizeflag)
11995 const struct dis386 *dp;
11996 unsigned char floatop;
11998 floatop = codep[-1];
12000 if (modrm.mod != 3)
12002 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12004 putop (float_mem[fp_indx], sizeflag);
12007 OP_E (float_mem_mode[fp_indx], sizeflag);
12010 /* Skip mod/rm byte. */
12014 dp = &float_reg[floatop - 0xd8][modrm.reg];
12015 if (dp->name == NULL)
12017 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12019 /* Instruction fnstsw is only one with strange arg. */
12020 if (floatop == 0xdf && codep[-1] == 0xe0)
12021 strcpy (op_out[0], names16[0]);
12025 putop (dp->name, sizeflag);
12030 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12035 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12040 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12042 oappend ("%st" + intel_syntax);
12046 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12048 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12049 oappend (scratchbuf + intel_syntax);
12052 /* Capital letters in template are macros. */
12054 putop (const char *in_template, int sizeflag)
12059 unsigned int l = 0, len = 1;
12062 #define SAVE_LAST(c) \
12063 if (l < len && l < sizeof (last)) \
12068 for (p = in_template; *p; p++)
12085 while (*++p != '|')
12086 if (*p == '}' || *p == '\0')
12089 /* Fall through. */
12094 while (*++p != '}')
12105 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12109 if (l == 0 && len == 1)
12114 if (sizeflag & SUFFIX_ALWAYS)
12127 if (address_mode == mode_64bit
12128 && !(prefixes & PREFIX_ADDR))
12139 if (intel_syntax && !alt)
12141 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12143 if (sizeflag & DFLAG)
12144 *obufp++ = intel_syntax ? 'd' : 'l';
12146 *obufp++ = intel_syntax ? 'w' : 's';
12147 used_prefixes |= (prefixes & PREFIX_DATA);
12151 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12154 if (modrm.mod == 3)
12160 if (sizeflag & DFLAG)
12161 *obufp++ = intel_syntax ? 'd' : 'l';
12164 used_prefixes |= (prefixes & PREFIX_DATA);
12170 case 'E': /* For jcxz/jecxz */
12171 if (address_mode == mode_64bit)
12173 if (sizeflag & AFLAG)
12179 if (sizeflag & AFLAG)
12181 used_prefixes |= (prefixes & PREFIX_ADDR);
12186 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12188 if (sizeflag & AFLAG)
12189 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12191 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12192 used_prefixes |= (prefixes & PREFIX_ADDR);
12196 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12198 if ((rex & REX_W) || (sizeflag & DFLAG))
12202 if (!(rex & REX_W))
12203 used_prefixes |= (prefixes & PREFIX_DATA);
12208 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12209 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12211 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12214 if (prefixes & PREFIX_DS)
12235 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12240 /* Fall through. */
12243 if (l != 0 || len != 1)
12251 if (sizeflag & SUFFIX_ALWAYS)
12255 if (intel_mnemonic != cond)
12259 if ((prefixes & PREFIX_FWAIT) == 0)
12262 used_prefixes |= PREFIX_FWAIT;
12268 else if (intel_syntax && (sizeflag & DFLAG))
12272 if (!(rex & REX_W))
12273 used_prefixes |= (prefixes & PREFIX_DATA);
12277 && address_mode == mode_64bit
12278 && (sizeflag & DFLAG))
12283 /* Fall through. */
12287 if ((rex & REX_W) == 0
12288 && (prefixes & PREFIX_DATA))
12290 if ((sizeflag & DFLAG) == 0)
12292 used_prefixes |= (prefixes & PREFIX_DATA);
12296 if ((prefixes & PREFIX_DATA)
12298 || (sizeflag & SUFFIX_ALWAYS))
12305 if (sizeflag & DFLAG)
12309 used_prefixes |= (prefixes & PREFIX_DATA);
12316 if (address_mode == mode_64bit && (sizeflag & DFLAG))
12318 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12322 /* Fall through. */
12325 if (l == 0 && len == 1)
12328 if (intel_syntax && !alt)
12331 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12337 if (sizeflag & DFLAG)
12338 *obufp++ = intel_syntax ? 'd' : 'l';
12341 used_prefixes |= (prefixes & PREFIX_DATA);
12347 if (l != 1 || len != 2 || last[0] != 'L')
12353 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12368 else if (sizeflag & DFLAG)
12377 if (intel_syntax && !p[1]
12378 && ((rex & REX_W) || (sizeflag & DFLAG)))
12380 if (!(rex & REX_W))
12381 used_prefixes |= (prefixes & PREFIX_DATA);
12384 if (l == 0 && len == 1)
12388 if (address_mode == mode_64bit && (sizeflag & DFLAG))
12390 if (sizeflag & SUFFIX_ALWAYS)
12412 /* Fall through. */
12415 if (l == 0 && len == 1)
12420 if (sizeflag & SUFFIX_ALWAYS)
12426 if (sizeflag & DFLAG)
12430 used_prefixes |= (prefixes & PREFIX_DATA);
12444 if (address_mode == mode_64bit
12445 && !(prefixes & PREFIX_ADDR))
12456 if (l != 0 || len != 1)
12461 if (need_vex && vex.prefix)
12463 if (vex.prefix == DATA_PREFIX_OPCODE)
12470 if (prefixes & PREFIX_DATA)
12474 used_prefixes |= (prefixes & PREFIX_DATA);
12478 if (l == 0 && len == 1)
12480 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12491 if (l != 1 || len != 2 || last[0] != 'X')
12499 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12501 switch (vex.length)
12515 if (l == 0 && len == 1)
12517 /* operand size flag for cwtl, cbtw */
12526 else if (sizeflag & DFLAG)
12530 if (!(rex & REX_W))
12531 used_prefixes |= (prefixes & PREFIX_DATA);
12538 && last[0] != 'L'))
12545 if (last[0] == 'X')
12546 *obufp++ = vex.w ? 'd': 's';
12548 *obufp++ = vex.w ? 'q': 'd';
12555 mnemonicendp = obufp;
12560 oappend (const char *s)
12562 obufp = stpcpy (obufp, s);
12568 if (prefixes & PREFIX_CS)
12570 used_prefixes |= PREFIX_CS;
12571 oappend ("%cs:" + intel_syntax);
12573 if (prefixes & PREFIX_DS)
12575 used_prefixes |= PREFIX_DS;
12576 oappend ("%ds:" + intel_syntax);
12578 if (prefixes & PREFIX_SS)
12580 used_prefixes |= PREFIX_SS;
12581 oappend ("%ss:" + intel_syntax);
12583 if (prefixes & PREFIX_ES)
12585 used_prefixes |= PREFIX_ES;
12586 oappend ("%es:" + intel_syntax);
12588 if (prefixes & PREFIX_FS)
12590 used_prefixes |= PREFIX_FS;
12591 oappend ("%fs:" + intel_syntax);
12593 if (prefixes & PREFIX_GS)
12595 used_prefixes |= PREFIX_GS;
12596 oappend ("%gs:" + intel_syntax);
12601 OP_indirE (int bytemode, int sizeflag)
12605 OP_E (bytemode, sizeflag);
12609 print_operand_value (char *buf, int hex, bfd_vma disp)
12611 if (address_mode == mode_64bit)
12619 sprintf_vma (tmp, disp);
12620 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
12621 strcpy (buf + 2, tmp + i);
12625 bfd_signed_vma v = disp;
12632 /* Check for possible overflow on 0x8000000000000000. */
12635 strcpy (buf, "9223372036854775808");
12649 tmp[28 - i] = (v % 10) + '0';
12653 strcpy (buf, tmp + 29 - i);
12659 sprintf (buf, "0x%x", (unsigned int) disp);
12661 sprintf (buf, "%d", (int) disp);
12665 /* Put DISP in BUF as signed hex number. */
12668 print_displacement (char *buf, bfd_vma disp)
12670 bfd_signed_vma val = disp;
12679 /* Check for possible overflow. */
12682 switch (address_mode)
12685 strcpy (buf + j, "0x8000000000000000");
12688 strcpy (buf + j, "0x80000000");
12691 strcpy (buf + j, "0x8000");
12701 sprintf_vma (tmp, (bfd_vma) val);
12702 for (i = 0; tmp[i] == '0'; i++)
12704 if (tmp[i] == '\0')
12706 strcpy (buf + j, tmp + i);
12710 intel_operand_size (int bytemode, int sizeflag)
12717 oappend ("BYTE PTR ");
12721 oappend ("WORD PTR ");
12724 if (address_mode == mode_64bit && (sizeflag & DFLAG))
12726 oappend ("QWORD PTR ");
12735 oappend ("QWORD PTR ");
12738 if ((sizeflag & DFLAG) || bytemode == dq_mode)
12739 oappend ("DWORD PTR ");
12741 oappend ("WORD PTR ");
12742 used_prefixes |= (prefixes & PREFIX_DATA);
12746 if ((rex & REX_W) || (sizeflag & DFLAG))
12748 oappend ("WORD PTR ");
12749 if (!(rex & REX_W))
12750 used_prefixes |= (prefixes & PREFIX_DATA);
12753 if (sizeflag & DFLAG)
12754 oappend ("QWORD PTR ");
12756 oappend ("DWORD PTR ");
12757 used_prefixes |= (prefixes & PREFIX_DATA);
12760 case d_scalar_mode:
12761 case d_scalar_swap_mode:
12764 oappend ("DWORD PTR ");
12767 case q_scalar_mode:
12768 case q_scalar_swap_mode:
12770 oappend ("QWORD PTR ");
12773 if (address_mode == mode_64bit)
12774 oappend ("QWORD PTR ");
12776 oappend ("DWORD PTR ");
12779 if (sizeflag & DFLAG)
12780 oappend ("FWORD PTR ");
12782 oappend ("DWORD PTR ");
12783 used_prefixes |= (prefixes & PREFIX_DATA);
12786 oappend ("TBYTE PTR ");
12792 switch (vex.length)
12795 oappend ("XMMWORD PTR ");
12798 oappend ("YMMWORD PTR ");
12805 oappend ("XMMWORD PTR ");
12808 oappend ("XMMWORD PTR ");
12814 switch (vex.length)
12817 oappend ("QWORD PTR ");
12820 oappend ("XMMWORD PTR ");
12830 switch (vex.length)
12834 oappend ("BYTE PTR ");
12844 switch (vex.length)
12848 oappend ("WORD PTR ");
12858 switch (vex.length)
12862 oappend ("DWORD PTR ");
12872 switch (vex.length)
12876 oappend ("QWORD PTR ");
12886 switch (vex.length)
12889 oappend ("WORD PTR ");
12892 oappend ("DWORD PTR ");
12902 switch (vex.length)
12905 oappend ("DWORD PTR ");
12908 oappend ("QWORD PTR ");
12918 switch (vex.length)
12921 oappend ("QWORD PTR ");
12924 oappend ("YMMWORD PTR ");
12934 switch (vex.length)
12938 oappend ("XMMWORD PTR ");
12945 oappend ("OWORD PTR ");
12947 case vex_w_dq_mode:
12948 case vex_scalar_w_dq_mode:
12949 case vex_vsib_d_w_dq_mode:
12950 case vex_vsib_q_w_dq_mode:
12955 oappend ("QWORD PTR ");
12957 oappend ("DWORD PTR ");
12965 OP_E_register (int bytemode, int sizeflag)
12967 int reg = modrm.rm;
12968 const char **names;
12974 if ((sizeflag & SUFFIX_ALWAYS)
12975 && (bytemode == b_swap_mode || bytemode == v_swap_mode))
12998 names = address_mode == mode_64bit ? names64 : names32;
13001 if (address_mode == mode_64bit && (sizeflag & DFLAG))
13019 if ((sizeflag & DFLAG)
13020 || (bytemode != v_mode
13021 && bytemode != v_swap_mode))
13025 used_prefixes |= (prefixes & PREFIX_DATA);
13031 oappend (INTERNAL_DISASSEMBLER_ERROR);
13034 oappend (names[reg]);
13038 OP_E_memory (int bytemode, int sizeflag)
13041 int add = (rex & REX_B) ? 8 : 0;
13046 intel_operand_size (bytemode, sizeflag);
13049 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13051 /* 32/64 bit address mode */
13060 const char **indexes64 = names64;
13061 const char **indexes32 = names32;
13071 vindex = sib.index;
13077 case vex_vsib_d_w_dq_mode:
13078 case vex_vsib_q_w_dq_mode:
13083 switch (vex.length)
13086 indexes64 = indexes32 = names_xmm;
13089 if (!vex.w || bytemode == vex_vsib_q_w_dq_mode)
13090 indexes64 = indexes32 = names_ymm;
13092 indexes64 = indexes32 = names_xmm;
13099 haveindex = vindex != 4;
13106 rbase = base + add;
13114 if (address_mode == mode_64bit && !havesib)
13120 FETCH_DATA (the_info, codep + 1);
13122 if ((disp & 0x80) != 0)
13130 /* In 32bit mode, we need index register to tell [offset] from
13131 [eiz*1 + offset]. */
13132 needindex = (havesib
13135 && address_mode == mode_32bit);
13136 havedisp = (havebase
13138 || (havesib && (haveindex || scale != 0)));
13141 if (modrm.mod != 0 || base == 5)
13143 if (havedisp || riprel)
13144 print_displacement (scratchbuf, disp);
13146 print_operand_value (scratchbuf, 1, disp);
13147 oappend (scratchbuf);
13151 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
13155 if (havebase || haveindex || riprel)
13156 used_prefixes |= PREFIX_ADDR;
13158 if (havedisp || (intel_syntax && riprel))
13160 *obufp++ = open_char;
13161 if (intel_syntax && riprel)
13164 oappend (sizeflag & AFLAG ? "rip" : "eip");
13168 oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
13169 ? names64[rbase] : names32[rbase]);
13172 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
13173 print index to tell base + index from base. */
13177 || (havebase && base != ESP_REG_NUM))
13179 if (!intel_syntax || havebase)
13181 *obufp++ = separator_char;
13185 oappend (address_mode == mode_64bit
13186 && (sizeflag & AFLAG)
13187 ? indexes64[vindex] : indexes32[vindex]);
13189 oappend (address_mode == mode_64bit
13190 && (sizeflag & AFLAG)
13191 ? index64 : index32);
13193 *obufp++ = scale_char;
13195 sprintf (scratchbuf, "%d", 1 << scale);
13196 oappend (scratchbuf);
13200 && (disp || modrm.mod != 0 || base == 5))
13202 if (!havedisp || (bfd_signed_vma) disp >= 0)
13207 else if (modrm.mod != 1 && disp != -disp)
13211 disp = - (bfd_signed_vma) disp;
13215 print_displacement (scratchbuf, disp);
13217 print_operand_value (scratchbuf, 1, disp);
13218 oappend (scratchbuf);
13221 *obufp++ = close_char;
13224 else if (intel_syntax)
13226 if (modrm.mod != 0 || base == 5)
13228 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13229 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13233 oappend (names_seg[ds_reg - es_reg]);
13236 print_operand_value (scratchbuf, 1, disp);
13237 oappend (scratchbuf);
13243 /* 16 bit address mode */
13244 used_prefixes |= prefixes & PREFIX_ADDR;
13251 if ((disp & 0x8000) != 0)
13256 FETCH_DATA (the_info, codep + 1);
13258 if ((disp & 0x80) != 0)
13263 if ((disp & 0x8000) != 0)
13269 if (modrm.mod != 0 || modrm.rm == 6)
13271 print_displacement (scratchbuf, disp);
13272 oappend (scratchbuf);
13275 if (modrm.mod != 0 || modrm.rm != 6)
13277 *obufp++ = open_char;
13279 oappend (index16[modrm.rm]);
13281 && (disp || modrm.mod != 0 || modrm.rm == 6))
13283 if ((bfd_signed_vma) disp >= 0)
13288 else if (modrm.mod != 1)
13292 disp = - (bfd_signed_vma) disp;
13295 print_displacement (scratchbuf, disp);
13296 oappend (scratchbuf);
13299 *obufp++ = close_char;
13302 else if (intel_syntax)
13304 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13305 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13309 oappend (names_seg[ds_reg - es_reg]);
13312 print_operand_value (scratchbuf, 1, disp & 0xffff);
13313 oappend (scratchbuf);
13319 OP_E (int bytemode, int sizeflag)
13321 /* Skip mod/rm byte. */
13325 if (modrm.mod == 3)
13326 OP_E_register (bytemode, sizeflag);
13328 OP_E_memory (bytemode, sizeflag);
13332 OP_G (int bytemode, int sizeflag)
13343 oappend (names8rex[modrm.reg + add]);
13345 oappend (names8[modrm.reg + add]);
13348 oappend (names16[modrm.reg + add]);
13351 oappend (names32[modrm.reg + add]);
13354 oappend (names64[modrm.reg + add]);
13363 oappend (names64[modrm.reg + add]);
13366 if ((sizeflag & DFLAG) || bytemode != v_mode)
13367 oappend (names32[modrm.reg + add]);
13369 oappend (names16[modrm.reg + add]);
13370 used_prefixes |= (prefixes & PREFIX_DATA);
13374 if (address_mode == mode_64bit)
13375 oappend (names64[modrm.reg + add]);
13377 oappend (names32[modrm.reg + add]);
13380 oappend (INTERNAL_DISASSEMBLER_ERROR);
13393 FETCH_DATA (the_info, codep + 8);
13394 a = *codep++ & 0xff;
13395 a |= (*codep++ & 0xff) << 8;
13396 a |= (*codep++ & 0xff) << 16;
13397 a |= (*codep++ & 0xff) << 24;
13398 b = *codep++ & 0xff;
13399 b |= (*codep++ & 0xff) << 8;
13400 b |= (*codep++ & 0xff) << 16;
13401 b |= (*codep++ & 0xff) << 24;
13402 x = a + ((bfd_vma) b << 32);
13410 static bfd_signed_vma
13413 bfd_signed_vma x = 0;
13415 FETCH_DATA (the_info, codep + 4);
13416 x = *codep++ & (bfd_signed_vma) 0xff;
13417 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
13418 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
13419 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
13423 static bfd_signed_vma
13426 bfd_signed_vma x = 0;
13428 FETCH_DATA (the_info, codep + 4);
13429 x = *codep++ & (bfd_signed_vma) 0xff;
13430 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
13431 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
13432 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
13434 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
13444 FETCH_DATA (the_info, codep + 2);
13445 x = *codep++ & 0xff;
13446 x |= (*codep++ & 0xff) << 8;
13451 set_op (bfd_vma op, int riprel)
13453 op_index[op_ad] = op_ad;
13454 if (address_mode == mode_64bit)
13456 op_address[op_ad] = op;
13457 op_riprel[op_ad] = riprel;
13461 /* Mask to get a 32-bit address. */
13462 op_address[op_ad] = op & 0xffffffff;
13463 op_riprel[op_ad] = riprel & 0xffffffff;
13468 OP_REG (int code, int sizeflag)
13480 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
13481 case sp_reg: case bp_reg: case si_reg: case di_reg:
13482 s = names16[code - ax_reg + add];
13484 case es_reg: case ss_reg: case cs_reg:
13485 case ds_reg: case fs_reg: case gs_reg:
13486 s = names_seg[code - es_reg + add];
13488 case al_reg: case ah_reg: case cl_reg: case ch_reg:
13489 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
13492 s = names8rex[code - al_reg + add];
13494 s = names8[code - al_reg];
13496 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
13497 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
13498 if (address_mode == mode_64bit && (sizeflag & DFLAG))
13500 s = names64[code - rAX_reg + add];
13503 code += eAX_reg - rAX_reg;
13504 /* Fall through. */
13505 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
13506 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
13509 s = names64[code - eAX_reg + add];
13512 if (sizeflag & DFLAG)
13513 s = names32[code - eAX_reg + add];
13515 s = names16[code - eAX_reg + add];
13516 used_prefixes |= (prefixes & PREFIX_DATA);
13520 s = INTERNAL_DISASSEMBLER_ERROR;
13527 OP_IMREG (int code, int sizeflag)
13539 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
13540 case sp_reg: case bp_reg: case si_reg: case di_reg:
13541 s = names16[code - ax_reg];
13543 case es_reg: case ss_reg: case cs_reg:
13544 case ds_reg: case fs_reg: case gs_reg:
13545 s = names_seg[code - es_reg];
13547 case al_reg: case ah_reg: case cl_reg: case ch_reg:
13548 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
13551 s = names8rex[code - al_reg];
13553 s = names8[code - al_reg];
13555 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
13556 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
13559 s = names64[code - eAX_reg];
13562 if (sizeflag & DFLAG)
13563 s = names32[code - eAX_reg];
13565 s = names16[code - eAX_reg];
13566 used_prefixes |= (prefixes & PREFIX_DATA);
13569 case z_mode_ax_reg:
13570 if ((rex & REX_W) || (sizeflag & DFLAG))
13574 if (!(rex & REX_W))
13575 used_prefixes |= (prefixes & PREFIX_DATA);
13578 s = INTERNAL_DISASSEMBLER_ERROR;
13585 OP_I (int bytemode, int sizeflag)
13588 bfd_signed_vma mask = -1;
13593 FETCH_DATA (the_info, codep + 1);
13598 if (address_mode == mode_64bit)
13603 /* Fall through. */
13610 if (sizeflag & DFLAG)
13620 used_prefixes |= (prefixes & PREFIX_DATA);
13632 oappend (INTERNAL_DISASSEMBLER_ERROR);
13637 scratchbuf[0] = '$';
13638 print_operand_value (scratchbuf + 1, 1, op);
13639 oappend (scratchbuf + intel_syntax);
13640 scratchbuf[0] = '\0';
13644 OP_I64 (int bytemode, int sizeflag)
13647 bfd_signed_vma mask = -1;
13649 if (address_mode != mode_64bit)
13651 OP_I (bytemode, sizeflag);
13658 FETCH_DATA (the_info, codep + 1);
13668 if (sizeflag & DFLAG)
13678 used_prefixes |= (prefixes & PREFIX_DATA);
13686 oappend (INTERNAL_DISASSEMBLER_ERROR);
13691 scratchbuf[0] = '$';
13692 print_operand_value (scratchbuf + 1, 1, op);
13693 oappend (scratchbuf + intel_syntax);
13694 scratchbuf[0] = '\0';
13698 OP_sI (int bytemode, int sizeflag)
13706 FETCH_DATA (the_info, codep + 1);
13708 if ((op & 0x80) != 0)
13710 if (bytemode == b_T_mode)
13712 if (address_mode != mode_64bit
13713 || !(sizeflag & DFLAG))
13715 if (sizeflag & DFLAG)
13723 if (!(rex & REX_W))
13725 if (sizeflag & DFLAG)
13733 if (sizeflag & DFLAG)
13739 oappend (INTERNAL_DISASSEMBLER_ERROR);
13743 scratchbuf[0] = '$';
13744 print_operand_value (scratchbuf + 1, 1, op);
13745 oappend (scratchbuf + intel_syntax);
13749 OP_J (int bytemode, int sizeflag)
13753 bfd_vma segment = 0;
13758 FETCH_DATA (the_info, codep + 1);
13760 if ((disp & 0x80) != 0)
13765 if ((sizeflag & DFLAG) || (rex & REX_W))
13770 if ((disp & 0x8000) != 0)
13772 /* In 16bit mode, address is wrapped around at 64k within
13773 the same segment. Otherwise, a data16 prefix on a jump
13774 instruction means that the pc is masked to 16 bits after
13775 the displacement is added! */
13777 if ((prefixes & PREFIX_DATA) == 0)
13778 segment = ((start_pc + codep - start_codep)
13779 & ~((bfd_vma) 0xffff));
13781 if (!(rex & REX_W))
13782 used_prefixes |= (prefixes & PREFIX_DATA);
13785 oappend (INTERNAL_DISASSEMBLER_ERROR);
13788 disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
13790 print_operand_value (scratchbuf, 1, disp);
13791 oappend (scratchbuf);
13795 OP_SEG (int bytemode, int sizeflag)
13797 if (bytemode == w_mode)
13798 oappend (names_seg[modrm.reg]);
13800 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
13804 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
13808 if (sizeflag & DFLAG)
13818 used_prefixes |= (prefixes & PREFIX_DATA);
13820 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
13822 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
13823 oappend (scratchbuf);
13827 OP_OFF (int bytemode, int sizeflag)
13831 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13832 intel_operand_size (bytemode, sizeflag);
13835 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13842 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13843 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
13845 oappend (names_seg[ds_reg - es_reg]);
13849 print_operand_value (scratchbuf, 1, off);
13850 oappend (scratchbuf);
13854 OP_OFF64 (int bytemode, int sizeflag)
13858 if (address_mode != mode_64bit
13859 || (prefixes & PREFIX_ADDR))
13861 OP_OFF (bytemode, sizeflag);
13865 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13866 intel_operand_size (bytemode, sizeflag);
13873 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13874 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
13876 oappend (names_seg[ds_reg - es_reg]);
13880 print_operand_value (scratchbuf, 1, off);
13881 oappend (scratchbuf);
13885 ptr_reg (int code, int sizeflag)
13889 *obufp++ = open_char;
13890 used_prefixes |= (prefixes & PREFIX_ADDR);
13891 if (address_mode == mode_64bit)
13893 if (!(sizeflag & AFLAG))
13894 s = names32[code - eAX_reg];
13896 s = names64[code - eAX_reg];
13898 else if (sizeflag & AFLAG)
13899 s = names32[code - eAX_reg];
13901 s = names16[code - eAX_reg];
13903 *obufp++ = close_char;
13908 OP_ESreg (int code, int sizeflag)
13914 case 0x6d: /* insw/insl */
13915 intel_operand_size (z_mode, sizeflag);
13917 case 0xa5: /* movsw/movsl/movsq */
13918 case 0xa7: /* cmpsw/cmpsl/cmpsq */
13919 case 0xab: /* stosw/stosl */
13920 case 0xaf: /* scasw/scasl */
13921 intel_operand_size (v_mode, sizeflag);
13924 intel_operand_size (b_mode, sizeflag);
13927 oappend ("%es:" + intel_syntax);
13928 ptr_reg (code, sizeflag);
13932 OP_DSreg (int code, int sizeflag)
13938 case 0x6f: /* outsw/outsl */
13939 intel_operand_size (z_mode, sizeflag);
13941 case 0xa5: /* movsw/movsl/movsq */
13942 case 0xa7: /* cmpsw/cmpsl/cmpsq */
13943 case 0xad: /* lodsw/lodsl/lodsq */
13944 intel_operand_size (v_mode, sizeflag);
13947 intel_operand_size (b_mode, sizeflag);
13956 | PREFIX_GS)) == 0)
13957 prefixes |= PREFIX_DS;
13959 ptr_reg (code, sizeflag);
13963 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13971 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
13973 all_prefixes[last_lock_prefix] = 0;
13974 used_prefixes |= PREFIX_LOCK;
13979 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
13980 oappend (scratchbuf + intel_syntax);
13984 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13993 sprintf (scratchbuf, "db%d", modrm.reg + add);
13995 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
13996 oappend (scratchbuf);
14000 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14002 sprintf (scratchbuf, "%%tr%d", modrm.reg);
14003 oappend (scratchbuf + intel_syntax);
14007 OP_R (int bytemode, int sizeflag)
14009 if (modrm.mod == 3)
14010 OP_E (bytemode, sizeflag);
14016 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14018 int reg = modrm.reg;
14019 const char **names;
14021 used_prefixes |= (prefixes & PREFIX_DATA);
14022 if (prefixes & PREFIX_DATA)
14031 oappend (names[reg]);
14035 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14037 int reg = modrm.reg;
14038 const char **names;
14044 && bytemode != xmm_mode
14045 && bytemode != scalar_mode)
14047 switch (vex.length)
14053 if (vex.w || bytemode != vex_vsib_q_w_dq_mode)
14064 oappend (names[reg]);
14068 OP_EM (int bytemode, int sizeflag)
14071 const char **names;
14073 if (modrm.mod != 3)
14076 && (bytemode == v_mode || bytemode == v_swap_mode))
14078 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14079 used_prefixes |= (prefixes & PREFIX_DATA);
14081 OP_E (bytemode, sizeflag);
14085 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
14088 /* Skip mod/rm byte. */
14091 used_prefixes |= (prefixes & PREFIX_DATA);
14093 if (prefixes & PREFIX_DATA)
14102 oappend (names[reg]);
14105 /* cvt* are the only instructions in sse2 which have
14106 both SSE and MMX operands and also have 0x66 prefix
14107 in their opcode. 0x66 was originally used to differentiate
14108 between SSE and MMX instruction(operands). So we have to handle the
14109 cvt* separately using OP_EMC and OP_MXC */
14111 OP_EMC (int bytemode, int sizeflag)
14113 if (modrm.mod != 3)
14115 if (intel_syntax && bytemode == v_mode)
14117 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14118 used_prefixes |= (prefixes & PREFIX_DATA);
14120 OP_E (bytemode, sizeflag);
14124 /* Skip mod/rm byte. */
14127 used_prefixes |= (prefixes & PREFIX_DATA);
14128 oappend (names_mm[modrm.rm]);
14132 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14134 used_prefixes |= (prefixes & PREFIX_DATA);
14135 oappend (names_mm[modrm.reg]);
14139 OP_EX (int bytemode, int sizeflag)
14142 const char **names;
14144 /* Skip mod/rm byte. */
14148 if (modrm.mod != 3)
14150 OP_E_memory (bytemode, sizeflag);
14159 if ((sizeflag & SUFFIX_ALWAYS)
14160 && (bytemode == x_swap_mode
14161 || bytemode == d_swap_mode
14162 || bytemode == d_scalar_swap_mode
14163 || bytemode == q_swap_mode
14164 || bytemode == q_scalar_swap_mode))
14168 && bytemode != xmm_mode
14169 && bytemode != xmmdw_mode
14170 && bytemode != xmmqd_mode
14171 && bytemode != xmm_mb_mode
14172 && bytemode != xmm_mw_mode
14173 && bytemode != xmm_md_mode
14174 && bytemode != xmm_mq_mode
14175 && bytemode != xmmq_mode
14176 && bytemode != d_scalar_mode
14177 && bytemode != d_scalar_swap_mode
14178 && bytemode != q_scalar_mode
14179 && bytemode != q_scalar_swap_mode
14180 && bytemode != vex_scalar_w_dq_mode)
14182 switch (vex.length)
14196 oappend (names[reg]);
14200 OP_MS (int bytemode, int sizeflag)
14202 if (modrm.mod == 3)
14203 OP_EM (bytemode, sizeflag);
14209 OP_XS (int bytemode, int sizeflag)
14211 if (modrm.mod == 3)
14212 OP_EX (bytemode, sizeflag);
14218 OP_M (int bytemode, int sizeflag)
14220 if (modrm.mod == 3)
14221 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
14224 OP_E (bytemode, sizeflag);
14228 OP_0f07 (int bytemode, int sizeflag)
14230 if (modrm.mod != 3 || modrm.rm != 0)
14233 OP_E (bytemode, sizeflag);
14236 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
14237 32bit mode and "xchg %rax,%rax" in 64bit mode. */
14240 NOP_Fixup1 (int bytemode, int sizeflag)
14242 if ((prefixes & PREFIX_DATA) != 0
14245 && address_mode == mode_64bit))
14246 OP_REG (bytemode, sizeflag);
14248 strcpy (obuf, "nop");
14252 NOP_Fixup2 (int bytemode, int sizeflag)
14254 if ((prefixes & PREFIX_DATA) != 0
14257 && address_mode == mode_64bit))
14258 OP_IMREG (bytemode, sizeflag);
14261 static const char *const Suffix3DNow[] = {
14262 /* 00 */ NULL, NULL, NULL, NULL,
14263 /* 04 */ NULL, NULL, NULL, NULL,
14264 /* 08 */ NULL, NULL, NULL, NULL,
14265 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
14266 /* 10 */ NULL, NULL, NULL, NULL,
14267 /* 14 */ NULL, NULL, NULL, NULL,
14268 /* 18 */ NULL, NULL, NULL, NULL,
14269 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
14270 /* 20 */ NULL, NULL, NULL, NULL,
14271 /* 24 */ NULL, NULL, NULL, NULL,
14272 /* 28 */ NULL, NULL, NULL, NULL,
14273 /* 2C */ NULL, NULL, NULL, NULL,
14274 /* 30 */ NULL, NULL, NULL, NULL,
14275 /* 34 */ NULL, NULL, NULL, NULL,
14276 /* 38 */ NULL, NULL, NULL, NULL,
14277 /* 3C */ NULL, NULL, NULL, NULL,
14278 /* 40 */ NULL, NULL, NULL, NULL,
14279 /* 44 */ NULL, NULL, NULL, NULL,
14280 /* 48 */ NULL, NULL, NULL, NULL,
14281 /* 4C */ NULL, NULL, NULL, NULL,
14282 /* 50 */ NULL, NULL, NULL, NULL,
14283 /* 54 */ NULL, NULL, NULL, NULL,
14284 /* 58 */ NULL, NULL, NULL, NULL,
14285 /* 5C */ NULL, NULL, NULL, NULL,
14286 /* 60 */ NULL, NULL, NULL, NULL,
14287 /* 64 */ NULL, NULL, NULL, NULL,
14288 /* 68 */ NULL, NULL, NULL, NULL,
14289 /* 6C */ NULL, NULL, NULL, NULL,
14290 /* 70 */ NULL, NULL, NULL, NULL,
14291 /* 74 */ NULL, NULL, NULL, NULL,
14292 /* 78 */ NULL, NULL, NULL, NULL,
14293 /* 7C */ NULL, NULL, NULL, NULL,
14294 /* 80 */ NULL, NULL, NULL, NULL,
14295 /* 84 */ NULL, NULL, NULL, NULL,
14296 /* 88 */ NULL, NULL, "pfnacc", NULL,
14297 /* 8C */ NULL, NULL, "pfpnacc", NULL,
14298 /* 90 */ "pfcmpge", NULL, NULL, NULL,
14299 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
14300 /* 98 */ NULL, NULL, "pfsub", NULL,
14301 /* 9C */ NULL, NULL, "pfadd", NULL,
14302 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
14303 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
14304 /* A8 */ NULL, NULL, "pfsubr", NULL,
14305 /* AC */ NULL, NULL, "pfacc", NULL,
14306 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
14307 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
14308 /* B8 */ NULL, NULL, NULL, "pswapd",
14309 /* BC */ NULL, NULL, NULL, "pavgusb",
14310 /* C0 */ NULL, NULL, NULL, NULL,
14311 /* C4 */ NULL, NULL, NULL, NULL,
14312 /* C8 */ NULL, NULL, NULL, NULL,
14313 /* CC */ NULL, NULL, NULL, NULL,
14314 /* D0 */ NULL, NULL, NULL, NULL,
14315 /* D4 */ NULL, NULL, NULL, NULL,
14316 /* D8 */ NULL, NULL, NULL, NULL,
14317 /* DC */ NULL, NULL, NULL, NULL,
14318 /* E0 */ NULL, NULL, NULL, NULL,
14319 /* E4 */ NULL, NULL, NULL, NULL,
14320 /* E8 */ NULL, NULL, NULL, NULL,
14321 /* EC */ NULL, NULL, NULL, NULL,
14322 /* F0 */ NULL, NULL, NULL, NULL,
14323 /* F4 */ NULL, NULL, NULL, NULL,
14324 /* F8 */ NULL, NULL, NULL, NULL,
14325 /* FC */ NULL, NULL, NULL, NULL,
14329 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14331 const char *mnemonic;
14333 FETCH_DATA (the_info, codep + 1);
14334 /* AMD 3DNow! instructions are specified by an opcode suffix in the
14335 place where an 8-bit immediate would normally go. ie. the last
14336 byte of the instruction. */
14337 obufp = mnemonicendp;
14338 mnemonic = Suffix3DNow[*codep++ & 0xff];
14340 oappend (mnemonic);
14343 /* Since a variable sized modrm/sib chunk is between the start
14344 of the opcode (0x0f0f) and the opcode suffix, we need to do
14345 all the modrm processing first, and don't know until now that
14346 we have a bad opcode. This necessitates some cleaning up. */
14347 op_out[0][0] = '\0';
14348 op_out[1][0] = '\0';
14351 mnemonicendp = obufp;
14354 static struct op simd_cmp_op[] =
14356 { STRING_COMMA_LEN ("eq") },
14357 { STRING_COMMA_LEN ("lt") },
14358 { STRING_COMMA_LEN ("le") },
14359 { STRING_COMMA_LEN ("unord") },
14360 { STRING_COMMA_LEN ("neq") },
14361 { STRING_COMMA_LEN ("nlt") },
14362 { STRING_COMMA_LEN ("nle") },
14363 { STRING_COMMA_LEN ("ord") }
14367 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14369 unsigned int cmp_type;
14371 FETCH_DATA (the_info, codep + 1);
14372 cmp_type = *codep++ & 0xff;
14373 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
14376 char *p = mnemonicendp - 2;
14380 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
14381 mnemonicendp += simd_cmp_op[cmp_type].len;
14385 /* We have a reserved extension byte. Output it directly. */
14386 scratchbuf[0] = '$';
14387 print_operand_value (scratchbuf + 1, 1, cmp_type);
14388 oappend (scratchbuf + intel_syntax);
14389 scratchbuf[0] = '\0';
14394 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
14395 int sizeflag ATTRIBUTE_UNUSED)
14397 /* mwait %eax,%ecx */
14400 const char **names = (address_mode == mode_64bit
14401 ? names64 : names32);
14402 strcpy (op_out[0], names[0]);
14403 strcpy (op_out[1], names[1]);
14404 two_source_ops = 1;
14406 /* Skip mod/rm byte. */
14412 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
14413 int sizeflag ATTRIBUTE_UNUSED)
14415 /* monitor %eax,%ecx,%edx" */
14418 const char **op1_names;
14419 const char **names = (address_mode == mode_64bit
14420 ? names64 : names32);
14422 if (!(prefixes & PREFIX_ADDR))
14423 op1_names = (address_mode == mode_16bit
14424 ? names16 : names);
14427 /* Remove "addr16/addr32". */
14428 all_prefixes[last_addr_prefix] = 0;
14429 op1_names = (address_mode != mode_32bit
14430 ? names32 : names16);
14431 used_prefixes |= PREFIX_ADDR;
14433 strcpy (op_out[0], op1_names[0]);
14434 strcpy (op_out[1], names[1]);
14435 strcpy (op_out[2], names[2]);
14436 two_source_ops = 1;
14438 /* Skip mod/rm byte. */
14446 /* Throw away prefixes and 1st. opcode byte. */
14447 codep = insn_codep + 1;
14452 REP_Fixup (int bytemode, int sizeflag)
14454 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
14456 if (prefixes & PREFIX_REPZ)
14457 all_prefixes[last_repz_prefix] = REP_PREFIX;
14464 OP_IMREG (bytemode, sizeflag);
14467 OP_ESreg (bytemode, sizeflag);
14470 OP_DSreg (bytemode, sizeflag);
14478 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
14479 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
14483 HLE_Fixup1 (int bytemode, int sizeflag)
14486 && (prefixes & PREFIX_LOCK) != 0)
14488 if (prefixes & PREFIX_REPZ)
14489 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
14490 if (prefixes & PREFIX_REPNZ)
14491 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
14494 OP_E (bytemode, sizeflag);
14497 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
14498 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
14502 HLE_Fixup2 (int bytemode, int sizeflag)
14504 if (modrm.mod != 3)
14506 if (prefixes & PREFIX_REPZ)
14507 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
14508 if (prefixes & PREFIX_REPNZ)
14509 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
14512 OP_E (bytemode, sizeflag);
14515 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
14516 "xrelease" for memory operand. No check for LOCK prefix. */
14519 HLE_Fixup3 (int bytemode, int sizeflag)
14522 && last_repz_prefix > last_repnz_prefix
14523 && (prefixes & PREFIX_REPZ) != 0)
14524 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
14526 OP_E (bytemode, sizeflag);
14530 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
14535 /* Change cmpxchg8b to cmpxchg16b. */
14536 char *p = mnemonicendp - 2;
14537 mnemonicendp = stpcpy (p, "16b");
14540 else if ((prefixes & PREFIX_LOCK) != 0)
14542 if (prefixes & PREFIX_REPZ)
14543 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
14544 if (prefixes & PREFIX_REPNZ)
14545 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
14548 OP_M (bytemode, sizeflag);
14552 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
14554 const char **names;
14558 switch (vex.length)
14572 oappend (names[reg]);
14576 CRC32_Fixup (int bytemode, int sizeflag)
14578 /* Add proper suffix to "crc32". */
14579 char *p = mnemonicendp;
14598 if (sizeflag & DFLAG)
14602 used_prefixes |= (prefixes & PREFIX_DATA);
14606 oappend (INTERNAL_DISASSEMBLER_ERROR);
14613 if (modrm.mod == 3)
14617 /* Skip mod/rm byte. */
14622 add = (rex & REX_B) ? 8 : 0;
14623 if (bytemode == b_mode)
14627 oappend (names8rex[modrm.rm + add]);
14629 oappend (names8[modrm.rm + add]);
14635 oappend (names64[modrm.rm + add]);
14636 else if ((prefixes & PREFIX_DATA))
14637 oappend (names16[modrm.rm + add]);
14639 oappend (names32[modrm.rm + add]);
14643 OP_E (bytemode, sizeflag);
14647 FXSAVE_Fixup (int bytemode, int sizeflag)
14649 /* Add proper suffix to "fxsave" and "fxrstor". */
14653 char *p = mnemonicendp;
14659 OP_M (bytemode, sizeflag);
14662 /* Display the destination register operand for instructions with
14666 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14669 const char **names;
14677 reg = vex.register_specifier;
14678 if (bytemode == vex_scalar_mode)
14680 oappend (names_xmm[reg]);
14684 switch (vex.length)
14691 case vex_vsib_q_w_dq_mode:
14712 case vex_vsib_q_w_dq_mode:
14713 names = vex.w ? names_ymm : names_xmm;
14724 oappend (names[reg]);
14727 /* Get the VEX immediate byte without moving codep. */
14729 static unsigned char
14730 get_vex_imm8 (int sizeflag, int opnum)
14732 int bytes_before_imm = 0;
14734 if (modrm.mod != 3)
14736 /* There are SIB/displacement bytes. */
14737 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14739 /* 32/64 bit address mode */
14740 int base = modrm.rm;
14742 /* Check SIB byte. */
14745 FETCH_DATA (the_info, codep + 1);
14747 /* When decoding the third source, don't increase
14748 bytes_before_imm as this has already been incremented
14749 by one in OP_E_memory while decoding the second
14752 bytes_before_imm++;
14755 /* Don't increase bytes_before_imm when decoding the third source,
14756 it has already been incremented by OP_E_memory while decoding
14757 the second source operand. */
14763 /* When modrm.rm == 5 or modrm.rm == 4 and base in
14764 SIB == 5, there is a 4 byte displacement. */
14766 /* No displacement. */
14769 /* 4 byte displacement. */
14770 bytes_before_imm += 4;
14773 /* 1 byte displacement. */
14774 bytes_before_imm++;
14781 /* 16 bit address mode */
14782 /* Don't increase bytes_before_imm when decoding the third source,
14783 it has already been incremented by OP_E_memory while decoding
14784 the second source operand. */
14790 /* When modrm.rm == 6, there is a 2 byte displacement. */
14792 /* No displacement. */
14795 /* 2 byte displacement. */
14796 bytes_before_imm += 2;
14799 /* 1 byte displacement: when decoding the third source,
14800 don't increase bytes_before_imm as this has already
14801 been incremented by one in OP_E_memory while decoding
14802 the second source operand. */
14804 bytes_before_imm++;
14812 FETCH_DATA (the_info, codep + bytes_before_imm + 1);
14813 return codep [bytes_before_imm];
14817 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
14819 const char **names;
14821 if (reg == -1 && modrm.mod != 3)
14823 OP_E_memory (bytemode, sizeflag);
14835 else if (reg > 7 && address_mode != mode_64bit)
14839 switch (vex.length)
14850 oappend (names[reg]);
14854 OP_EX_VexImmW (int bytemode, int sizeflag)
14857 static unsigned char vex_imm8;
14859 if (vex_w_done == 0)
14863 /* Skip mod/rm byte. */
14867 vex_imm8 = get_vex_imm8 (sizeflag, 0);
14870 reg = vex_imm8 >> 4;
14872 OP_EX_VexReg (bytemode, sizeflag, reg);
14874 else if (vex_w_done == 1)
14879 reg = vex_imm8 >> 4;
14881 OP_EX_VexReg (bytemode, sizeflag, reg);
14885 /* Output the imm8 directly. */
14886 scratchbuf[0] = '$';
14887 print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
14888 oappend (scratchbuf + intel_syntax);
14889 scratchbuf[0] = '\0';
14895 OP_Vex_2src (int bytemode, int sizeflag)
14897 if (modrm.mod == 3)
14899 int reg = modrm.rm;
14903 oappend (names_xmm[reg]);
14908 && (bytemode == v_mode || bytemode == v_swap_mode))
14910 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14911 used_prefixes |= (prefixes & PREFIX_DATA);
14913 OP_E (bytemode, sizeflag);
14918 OP_Vex_2src_1 (int bytemode, int sizeflag)
14920 if (modrm.mod == 3)
14922 /* Skip mod/rm byte. */
14928 oappend (names_xmm[vex.register_specifier]);
14930 OP_Vex_2src (bytemode, sizeflag);
14934 OP_Vex_2src_2 (int bytemode, int sizeflag)
14937 OP_Vex_2src (bytemode, sizeflag);
14939 oappend (names_xmm[vex.register_specifier]);
14943 OP_EX_VexW (int bytemode, int sizeflag)
14951 /* Skip mod/rm byte. */
14956 reg = get_vex_imm8 (sizeflag, 0) >> 4;
14961 reg = get_vex_imm8 (sizeflag, 1) >> 4;
14964 OP_EX_VexReg (bytemode, sizeflag, reg);
14968 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
14969 int sizeflag ATTRIBUTE_UNUSED)
14971 /* Skip the immediate byte and check for invalid bits. */
14972 FETCH_DATA (the_info, codep + 1);
14973 if (*codep++ & 0xf)
14978 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14981 const char **names;
14983 FETCH_DATA (the_info, codep + 1);
14986 if (bytemode != x_mode)
14993 if (reg > 7 && address_mode != mode_64bit)
14996 switch (vex.length)
15007 oappend (names[reg]);
15011 OP_XMM_VexW (int bytemode, int sizeflag)
15013 /* Turn off the REX.W bit since it is used for swapping operands
15016 OP_XMM (bytemode, sizeflag);
15020 OP_EX_Vex (int bytemode, int sizeflag)
15022 if (modrm.mod != 3)
15024 if (vex.register_specifier != 0)
15028 OP_EX (bytemode, sizeflag);
15032 OP_XMM_Vex (int bytemode, int sizeflag)
15034 if (modrm.mod != 3)
15036 if (vex.register_specifier != 0)
15040 OP_XMM (bytemode, sizeflag);
15044 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15046 switch (vex.length)
15049 mnemonicendp = stpcpy (obuf, "vzeroupper");
15052 mnemonicendp = stpcpy (obuf, "vzeroall");
15059 static struct op vex_cmp_op[] =
15061 { STRING_COMMA_LEN ("eq") },
15062 { STRING_COMMA_LEN ("lt") },
15063 { STRING_COMMA_LEN ("le") },
15064 { STRING_COMMA_LEN ("unord") },
15065 { STRING_COMMA_LEN ("neq") },
15066 { STRING_COMMA_LEN ("nlt") },
15067 { STRING_COMMA_LEN ("nle") },
15068 { STRING_COMMA_LEN ("ord") },
15069 { STRING_COMMA_LEN ("eq_uq") },
15070 { STRING_COMMA_LEN ("nge") },
15071 { STRING_COMMA_LEN ("ngt") },
15072 { STRING_COMMA_LEN ("false") },
15073 { STRING_COMMA_LEN ("neq_oq") },
15074 { STRING_COMMA_LEN ("ge") },
15075 { STRING_COMMA_LEN ("gt") },
15076 { STRING_COMMA_LEN ("true") },
15077 { STRING_COMMA_LEN ("eq_os") },
15078 { STRING_COMMA_LEN ("lt_oq") },
15079 { STRING_COMMA_LEN ("le_oq") },
15080 { STRING_COMMA_LEN ("unord_s") },
15081 { STRING_COMMA_LEN ("neq_us") },
15082 { STRING_COMMA_LEN ("nlt_uq") },
15083 { STRING_COMMA_LEN ("nle_uq") },
15084 { STRING_COMMA_LEN ("ord_s") },
15085 { STRING_COMMA_LEN ("eq_us") },
15086 { STRING_COMMA_LEN ("nge_uq") },
15087 { STRING_COMMA_LEN ("ngt_uq") },
15088 { STRING_COMMA_LEN ("false_os") },
15089 { STRING_COMMA_LEN ("neq_os") },
15090 { STRING_COMMA_LEN ("ge_oq") },
15091 { STRING_COMMA_LEN ("gt_oq") },
15092 { STRING_COMMA_LEN ("true_us") },
15096 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15098 unsigned int cmp_type;
15100 FETCH_DATA (the_info, codep + 1);
15101 cmp_type = *codep++ & 0xff;
15102 if (cmp_type < ARRAY_SIZE (vex_cmp_op))
15105 char *p = mnemonicendp - 2;
15109 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
15110 mnemonicendp += vex_cmp_op[cmp_type].len;
15114 /* We have a reserved extension byte. Output it directly. */
15115 scratchbuf[0] = '$';
15116 print_operand_value (scratchbuf + 1, 1, cmp_type);
15117 oappend (scratchbuf + intel_syntax);
15118 scratchbuf[0] = '\0';
15122 static const struct op pclmul_op[] =
15124 { STRING_COMMA_LEN ("lql") },
15125 { STRING_COMMA_LEN ("hql") },
15126 { STRING_COMMA_LEN ("lqh") },
15127 { STRING_COMMA_LEN ("hqh") }
15131 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
15132 int sizeflag ATTRIBUTE_UNUSED)
15134 unsigned int pclmul_type;
15136 FETCH_DATA (the_info, codep + 1);
15137 pclmul_type = *codep++ & 0xff;
15138 switch (pclmul_type)
15149 if (pclmul_type < ARRAY_SIZE (pclmul_op))
15152 char *p = mnemonicendp - 3;
15157 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
15158 mnemonicendp += pclmul_op[pclmul_type].len;
15162 /* We have a reserved extension byte. Output it directly. */
15163 scratchbuf[0] = '$';
15164 print_operand_value (scratchbuf + 1, 1, pclmul_type);
15165 oappend (scratchbuf + intel_syntax);
15166 scratchbuf[0] = '\0';
15171 MOVBE_Fixup (int bytemode, int sizeflag)
15173 /* Add proper suffix to "movbe". */
15174 char *p = mnemonicendp;
15183 if (sizeflag & SUFFIX_ALWAYS)
15189 if (sizeflag & DFLAG)
15193 used_prefixes |= (prefixes & PREFIX_DATA);
15198 oappend (INTERNAL_DISASSEMBLER_ERROR);
15205 OP_M (bytemode, sizeflag);
15209 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15212 const char **names;
15214 /* Skip mod/rm byte. */
15228 oappend (names[reg]);
15232 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15234 const char **names;
15241 oappend (names[vex.register_specifier]);