1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2017 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma, disassemble_info *);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma get64 (void);
58 static bfd_signed_vma get32 (void);
59 static bfd_signed_vma get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VEXI4_Fixup (int, int);
99 static void VZERO_Fixup (int, int);
100 static void VCMP_Fixup (int, int);
101 static void VPCMP_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void OP_Mwaitx (int, int);
106 static void NOP_Fixup1 (int, int);
107 static void NOP_Fixup2 (int, int);
108 static void OP_3DNowSuffix (int, int);
109 static void CMP_Fixup (int, int);
110 static void BadOp (void);
111 static void REP_Fixup (int, int);
112 static void BND_Fixup (int, int);
113 static void NOTRACK_Fixup (int, int);
114 static void HLE_Fixup1 (int, int);
115 static void HLE_Fixup2 (int, int);
116 static void HLE_Fixup3 (int, int);
117 static void CMPXCHG8B_Fixup (int, int);
118 static void XMM_Fixup (int, int);
119 static void CRC32_Fixup (int, int);
120 static void FXSAVE_Fixup (int, int);
121 static void PCMPESTR_Fixup (int, int);
122 static void OP_LWPCB_E (int, int);
123 static void OP_LWP_E (int, int);
124 static void OP_Vex_2src_1 (int, int);
125 static void OP_Vex_2src_2 (int, int);
127 static void MOVBE_Fixup (int, int);
129 static void OP_Mask (int, int);
132 /* Points to first byte not fetched. */
133 bfd_byte *max_fetched;
134 bfd_byte the_buffer[MAX_MNEM_SIZE];
137 OPCODES_SIGJMP_BUF bailout;
147 enum address_mode address_mode;
149 /* Flags for the prefixes for the current instruction. See below. */
152 /* REX prefix the current instruction. See below. */
154 /* Bits of REX we've already used. */
156 /* REX bits in original REX prefix ignored. */
157 static int rex_ignored;
158 /* Mark parts used in the REX prefix. When we are testing for
159 empty prefix (for 8bit register REX extension), just mask it
160 out. Otherwise test for REX bit is excuse for existence of REX
161 only in case value is nonzero. */
162 #define USED_REX(value) \
167 rex_used |= (value) | REX_OPCODE; \
170 rex_used |= REX_OPCODE; \
173 /* Flags for prefixes which we somehow handled when printing the
174 current instruction. */
175 static int used_prefixes;
177 /* Flags stored in PREFIXES. */
178 #define PREFIX_REPZ 1
179 #define PREFIX_REPNZ 2
180 #define PREFIX_LOCK 4
182 #define PREFIX_SS 0x10
183 #define PREFIX_DS 0x20
184 #define PREFIX_ES 0x40
185 #define PREFIX_FS 0x80
186 #define PREFIX_GS 0x100
187 #define PREFIX_DATA 0x200
188 #define PREFIX_ADDR 0x400
189 #define PREFIX_FWAIT 0x800
191 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
192 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
194 #define FETCH_DATA(info, addr) \
195 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
196 ? 1 : fetch_data ((info), (addr)))
199 fetch_data (struct disassemble_info *info, bfd_byte *addr)
202 struct dis_private *priv = (struct dis_private *) info->private_data;
203 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
205 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
206 status = (*info->read_memory_func) (start,
208 addr - priv->max_fetched,
214 /* If we did manage to read at least one byte, then
215 print_insn_i386 will do something sensible. Otherwise, print
216 an error. We do that here because this is where we know
218 if (priv->max_fetched == priv->the_buffer)
219 (*info->memory_error_func) (status, start, info);
220 OPCODES_SIGLONGJMP (priv->bailout, 1);
223 priv->max_fetched = addr;
227 /* Possible values for prefix requirement. */
228 #define PREFIX_IGNORED_SHIFT 16
229 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
232 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
233 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
235 /* Opcode prefixes. */
236 #define PREFIX_OPCODE (PREFIX_REPZ \
240 /* Prefixes ignored. */
241 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
242 | PREFIX_IGNORED_REPNZ \
243 | PREFIX_IGNORED_DATA)
245 #define XX { NULL, 0 }
246 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
248 #define Eb { OP_E, b_mode }
249 #define Ebnd { OP_E, bnd_mode }
250 #define EbS { OP_E, b_swap_mode }
251 #define Ev { OP_E, v_mode }
252 #define Ev_bnd { OP_E, v_bnd_mode }
253 #define EvS { OP_E, v_swap_mode }
254 #define Ed { OP_E, d_mode }
255 #define Edq { OP_E, dq_mode }
256 #define Edqw { OP_E, dqw_mode }
257 #define Edqb { OP_E, dqb_mode }
258 #define Edb { OP_E, db_mode }
259 #define Edw { OP_E, dw_mode }
260 #define Edqd { OP_E, dqd_mode }
261 #define Eq { OP_E, q_mode }
262 #define indirEv { OP_indirE, indir_v_mode }
263 #define indirEp { OP_indirE, f_mode }
264 #define stackEv { OP_E, stack_v_mode }
265 #define Em { OP_E, m_mode }
266 #define Ew { OP_E, w_mode }
267 #define M { OP_M, 0 } /* lea, lgdt, etc. */
268 #define Ma { OP_M, a_mode }
269 #define Mb { OP_M, b_mode }
270 #define Md { OP_M, d_mode }
271 #define Mo { OP_M, o_mode }
272 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
273 #define Mq { OP_M, q_mode }
274 #define Mx { OP_M, x_mode }
275 #define Mxmm { OP_M, xmm_mode }
276 #define Gb { OP_G, b_mode }
277 #define Gbnd { OP_G, bnd_mode }
278 #define Gv { OP_G, v_mode }
279 #define Gd { OP_G, d_mode }
280 #define Gdq { OP_G, dq_mode }
281 #define Gm { OP_G, m_mode }
282 #define Gw { OP_G, w_mode }
283 #define Rd { OP_R, d_mode }
284 #define Rdq { OP_R, dq_mode }
285 #define Rm { OP_R, m_mode }
286 #define Ib { OP_I, b_mode }
287 #define sIb { OP_sI, b_mode } /* sign extened byte */
288 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
289 #define Iv { OP_I, v_mode }
290 #define sIv { OP_sI, v_mode }
291 #define Iq { OP_I, q_mode }
292 #define Iv64 { OP_I64, v_mode }
293 #define Iw { OP_I, w_mode }
294 #define I1 { OP_I, const_1_mode }
295 #define Jb { OP_J, b_mode }
296 #define Jv { OP_J, v_mode }
297 #define Cm { OP_C, m_mode }
298 #define Dm { OP_D, m_mode }
299 #define Td { OP_T, d_mode }
300 #define Skip_MODRM { OP_Skip_MODRM, 0 }
302 #define RMeAX { OP_REG, eAX_reg }
303 #define RMeBX { OP_REG, eBX_reg }
304 #define RMeCX { OP_REG, eCX_reg }
305 #define RMeDX { OP_REG, eDX_reg }
306 #define RMeSP { OP_REG, eSP_reg }
307 #define RMeBP { OP_REG, eBP_reg }
308 #define RMeSI { OP_REG, eSI_reg }
309 #define RMeDI { OP_REG, eDI_reg }
310 #define RMrAX { OP_REG, rAX_reg }
311 #define RMrBX { OP_REG, rBX_reg }
312 #define RMrCX { OP_REG, rCX_reg }
313 #define RMrDX { OP_REG, rDX_reg }
314 #define RMrSP { OP_REG, rSP_reg }
315 #define RMrBP { OP_REG, rBP_reg }
316 #define RMrSI { OP_REG, rSI_reg }
317 #define RMrDI { OP_REG, rDI_reg }
318 #define RMAL { OP_REG, al_reg }
319 #define RMCL { OP_REG, cl_reg }
320 #define RMDL { OP_REG, dl_reg }
321 #define RMBL { OP_REG, bl_reg }
322 #define RMAH { OP_REG, ah_reg }
323 #define RMCH { OP_REG, ch_reg }
324 #define RMDH { OP_REG, dh_reg }
325 #define RMBH { OP_REG, bh_reg }
326 #define RMAX { OP_REG, ax_reg }
327 #define RMDX { OP_REG, dx_reg }
329 #define eAX { OP_IMREG, eAX_reg }
330 #define eBX { OP_IMREG, eBX_reg }
331 #define eCX { OP_IMREG, eCX_reg }
332 #define eDX { OP_IMREG, eDX_reg }
333 #define eSP { OP_IMREG, eSP_reg }
334 #define eBP { OP_IMREG, eBP_reg }
335 #define eSI { OP_IMREG, eSI_reg }
336 #define eDI { OP_IMREG, eDI_reg }
337 #define AL { OP_IMREG, al_reg }
338 #define CL { OP_IMREG, cl_reg }
339 #define DL { OP_IMREG, dl_reg }
340 #define BL { OP_IMREG, bl_reg }
341 #define AH { OP_IMREG, ah_reg }
342 #define CH { OP_IMREG, ch_reg }
343 #define DH { OP_IMREG, dh_reg }
344 #define BH { OP_IMREG, bh_reg }
345 #define AX { OP_IMREG, ax_reg }
346 #define DX { OP_IMREG, dx_reg }
347 #define zAX { OP_IMREG, z_mode_ax_reg }
348 #define indirDX { OP_IMREG, indir_dx_reg }
350 #define Sw { OP_SEG, w_mode }
351 #define Sv { OP_SEG, v_mode }
352 #define Ap { OP_DIR, 0 }
353 #define Ob { OP_OFF64, b_mode }
354 #define Ov { OP_OFF64, v_mode }
355 #define Xb { OP_DSreg, eSI_reg }
356 #define Xv { OP_DSreg, eSI_reg }
357 #define Xz { OP_DSreg, eSI_reg }
358 #define Yb { OP_ESreg, eDI_reg }
359 #define Yv { OP_ESreg, eDI_reg }
360 #define DSBX { OP_DSreg, eBX_reg }
362 #define es { OP_REG, es_reg }
363 #define ss { OP_REG, ss_reg }
364 #define cs { OP_REG, cs_reg }
365 #define ds { OP_REG, ds_reg }
366 #define fs { OP_REG, fs_reg }
367 #define gs { OP_REG, gs_reg }
369 #define MX { OP_MMX, 0 }
370 #define XM { OP_XMM, 0 }
371 #define XMScalar { OP_XMM, scalar_mode }
372 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
373 #define XMM { OP_XMM, xmm_mode }
374 #define XMxmmq { OP_XMM, xmmq_mode }
375 #define EM { OP_EM, v_mode }
376 #define EMS { OP_EM, v_swap_mode }
377 #define EMd { OP_EM, d_mode }
378 #define EMx { OP_EM, x_mode }
379 #define EXbScalar { OP_EX, b_scalar_mode }
380 #define EXw { OP_EX, w_mode }
381 #define EXwScalar { OP_EX, w_scalar_mode }
382 #define EXd { OP_EX, d_mode }
383 #define EXdScalar { OP_EX, d_scalar_mode }
384 #define EXdS { OP_EX, d_swap_mode }
385 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
386 #define EXq { OP_EX, q_mode }
387 #define EXqScalar { OP_EX, q_scalar_mode }
388 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
389 #define EXqS { OP_EX, q_swap_mode }
390 #define EXx { OP_EX, x_mode }
391 #define EXxS { OP_EX, x_swap_mode }
392 #define EXxmm { OP_EX, xmm_mode }
393 #define EXymm { OP_EX, ymm_mode }
394 #define EXxmmq { OP_EX, xmmq_mode }
395 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
396 #define EXxmm_mb { OP_EX, xmm_mb_mode }
397 #define EXxmm_mw { OP_EX, xmm_mw_mode }
398 #define EXxmm_md { OP_EX, xmm_md_mode }
399 #define EXxmm_mq { OP_EX, xmm_mq_mode }
400 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
401 #define EXxmmdw { OP_EX, xmmdw_mode }
402 #define EXxmmqd { OP_EX, xmmqd_mode }
403 #define EXymmq { OP_EX, ymmq_mode }
404 #define EXVexWdq { OP_EX, vex_w_dq_mode }
405 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
406 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
407 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
408 #define MS { OP_MS, v_mode }
409 #define XS { OP_XS, v_mode }
410 #define EMCq { OP_EMC, q_mode }
411 #define MXC { OP_MXC, 0 }
412 #define OPSUF { OP_3DNowSuffix, 0 }
413 #define CMP { CMP_Fixup, 0 }
414 #define XMM0 { XMM_Fixup, 0 }
415 #define FXSAVE { FXSAVE_Fixup, 0 }
416 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
417 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
419 #define Vex { OP_VEX, vex_mode }
420 #define VexScalar { OP_VEX, vex_scalar_mode }
421 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
422 #define Vex128 { OP_VEX, vex128_mode }
423 #define Vex256 { OP_VEX, vex256_mode }
424 #define VexGdq { OP_VEX, dq_mode }
425 #define VexI4 { VEXI4_Fixup, 0}
426 #define EXdVex { OP_EX_Vex, d_mode }
427 #define EXdVexS { OP_EX_Vex, d_swap_mode }
428 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
429 #define EXqVex { OP_EX_Vex, q_mode }
430 #define EXqVexS { OP_EX_Vex, q_swap_mode }
431 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
432 #define EXVexW { OP_EX_VexW, x_mode }
433 #define EXdVexW { OP_EX_VexW, d_mode }
434 #define EXqVexW { OP_EX_VexW, q_mode }
435 #define EXVexImmW { OP_EX_VexImmW, x_mode }
436 #define XMVex { OP_XMM_Vex, 0 }
437 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
438 #define XMVexW { OP_XMM_VexW, 0 }
439 #define XMVexI4 { OP_REG_VexI4, x_mode }
440 #define PCLMUL { PCLMUL_Fixup, 0 }
441 #define VZERO { VZERO_Fixup, 0 }
442 #define VCMP { VCMP_Fixup, 0 }
443 #define VPCMP { VPCMP_Fixup, 0 }
445 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
446 #define EXxEVexS { OP_Rounding, evex_sae_mode }
448 #define XMask { OP_Mask, mask_mode }
449 #define MaskG { OP_G, mask_mode }
450 #define MaskE { OP_E, mask_mode }
451 #define MaskBDE { OP_E, mask_bd_mode }
452 #define MaskR { OP_R, mask_mode }
453 #define MaskVex { OP_VEX, mask_mode }
455 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
456 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
457 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
458 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
460 /* Used handle "rep" prefix for string instructions. */
461 #define Xbr { REP_Fixup, eSI_reg }
462 #define Xvr { REP_Fixup, eSI_reg }
463 #define Ybr { REP_Fixup, eDI_reg }
464 #define Yvr { REP_Fixup, eDI_reg }
465 #define Yzr { REP_Fixup, eDI_reg }
466 #define indirDXr { REP_Fixup, indir_dx_reg }
467 #define ALr { REP_Fixup, al_reg }
468 #define eAXr { REP_Fixup, eAX_reg }
470 /* Used handle HLE prefix for lockable instructions. */
471 #define Ebh1 { HLE_Fixup1, b_mode }
472 #define Evh1 { HLE_Fixup1, v_mode }
473 #define Ebh2 { HLE_Fixup2, b_mode }
474 #define Evh2 { HLE_Fixup2, v_mode }
475 #define Ebh3 { HLE_Fixup3, b_mode }
476 #define Evh3 { HLE_Fixup3, v_mode }
478 #define BND { BND_Fixup, 0 }
479 #define NOTRACK { NOTRACK_Fixup, 0 }
481 #define cond_jump_flag { NULL, cond_jump_mode }
482 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
484 /* bits in sizeflag */
485 #define SUFFIX_ALWAYS 4
493 /* byte operand with operand swapped */
495 /* byte operand, sign extend like 'T' suffix */
497 /* operand size depends on prefixes */
499 /* operand size depends on prefixes with operand swapped */
503 /* double word operand */
505 /* double word operand with operand swapped */
507 /* quad word operand */
509 /* quad word operand with operand swapped */
511 /* ten-byte operand */
513 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
514 broadcast enabled. */
516 /* Similar to x_mode, but with different EVEX mem shifts. */
518 /* Similar to x_mode, but with disabled broadcast. */
520 /* Similar to x_mode, but with operands swapped and disabled broadcast
523 /* 16-byte XMM operand */
525 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
526 memory operand (depending on vector length). Broadcast isn't
529 /* Same as xmmq_mode, but broadcast is allowed. */
530 evex_half_bcst_xmmq_mode,
531 /* XMM register or byte memory operand */
533 /* XMM register or word memory operand */
535 /* XMM register or double word memory operand */
537 /* XMM register or quad word memory operand */
539 /* XMM register or double/quad word memory operand, depending on
542 /* 16-byte XMM, word, double word or quad word operand. */
544 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
546 /* 32-byte YMM operand */
548 /* quad word, ymmword or zmmword memory operand. */
550 /* 32-byte YMM or 16-byte word operand */
552 /* d_mode in 32bit, q_mode in 64bit mode. */
554 /* pair of v_mode operands */
559 /* operand size depends on REX prefixes. */
561 /* registers like dq_mode, memory like w_mode. */
564 /* 4- or 6-byte pointer operand */
567 /* v_mode for indirect branch opcodes. */
569 /* v_mode for stack-related opcodes. */
571 /* non-quad operand size depends on prefixes */
573 /* 16-byte operand */
575 /* registers like dq_mode, memory like b_mode. */
577 /* registers like d_mode, memory like b_mode. */
579 /* registers like d_mode, memory like w_mode. */
581 /* registers like dq_mode, memory like d_mode. */
583 /* normal vex mode */
585 /* 128bit vex mode */
587 /* 256bit vex mode */
589 /* operand size depends on the VEX.W bit. */
592 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
593 vex_vsib_d_w_dq_mode,
594 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
596 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
597 vex_vsib_q_w_dq_mode,
598 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
601 /* scalar, ignore vector length. */
603 /* like b_mode, ignore vector length. */
605 /* like w_mode, ignore vector length. */
607 /* like d_mode, ignore vector length. */
609 /* like d_swap_mode, ignore vector length. */
611 /* like q_mode, ignore vector length. */
613 /* like q_swap_mode, ignore vector length. */
615 /* like vex_mode, ignore vector length. */
617 /* like vex_w_dq_mode, ignore vector length. */
618 vex_scalar_w_dq_mode,
620 /* Static rounding. */
622 /* Supress all exceptions. */
625 /* Mask register operand. */
627 /* Mask register operand. */
694 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
696 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
697 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
698 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
699 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
700 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
701 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
702 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
703 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
704 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
705 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
706 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
707 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
708 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
709 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
710 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
832 MOD_VEX_0F12_PREFIX_0,
834 MOD_VEX_0F16_PREFIX_0,
837 MOD_VEX_W_0_0F41_P_0_LEN_1,
838 MOD_VEX_W_1_0F41_P_0_LEN_1,
839 MOD_VEX_W_0_0F41_P_2_LEN_1,
840 MOD_VEX_W_1_0F41_P_2_LEN_1,
841 MOD_VEX_W_0_0F42_P_0_LEN_1,
842 MOD_VEX_W_1_0F42_P_0_LEN_1,
843 MOD_VEX_W_0_0F42_P_2_LEN_1,
844 MOD_VEX_W_1_0F42_P_2_LEN_1,
845 MOD_VEX_W_0_0F44_P_0_LEN_1,
846 MOD_VEX_W_1_0F44_P_0_LEN_1,
847 MOD_VEX_W_0_0F44_P_2_LEN_1,
848 MOD_VEX_W_1_0F44_P_2_LEN_1,
849 MOD_VEX_W_0_0F45_P_0_LEN_1,
850 MOD_VEX_W_1_0F45_P_0_LEN_1,
851 MOD_VEX_W_0_0F45_P_2_LEN_1,
852 MOD_VEX_W_1_0F45_P_2_LEN_1,
853 MOD_VEX_W_0_0F46_P_0_LEN_1,
854 MOD_VEX_W_1_0F46_P_0_LEN_1,
855 MOD_VEX_W_0_0F46_P_2_LEN_1,
856 MOD_VEX_W_1_0F46_P_2_LEN_1,
857 MOD_VEX_W_0_0F47_P_0_LEN_1,
858 MOD_VEX_W_1_0F47_P_0_LEN_1,
859 MOD_VEX_W_0_0F47_P_2_LEN_1,
860 MOD_VEX_W_1_0F47_P_2_LEN_1,
861 MOD_VEX_W_0_0F4A_P_0_LEN_1,
862 MOD_VEX_W_1_0F4A_P_0_LEN_1,
863 MOD_VEX_W_0_0F4A_P_2_LEN_1,
864 MOD_VEX_W_1_0F4A_P_2_LEN_1,
865 MOD_VEX_W_0_0F4B_P_0_LEN_1,
866 MOD_VEX_W_1_0F4B_P_0_LEN_1,
867 MOD_VEX_W_0_0F4B_P_2_LEN_1,
879 MOD_VEX_W_0_0F91_P_0_LEN_0,
880 MOD_VEX_W_1_0F91_P_0_LEN_0,
881 MOD_VEX_W_0_0F91_P_2_LEN_0,
882 MOD_VEX_W_1_0F91_P_2_LEN_0,
883 MOD_VEX_W_0_0F92_P_0_LEN_0,
884 MOD_VEX_W_0_0F92_P_2_LEN_0,
885 MOD_VEX_W_0_0F92_P_3_LEN_0,
886 MOD_VEX_W_1_0F92_P_3_LEN_0,
887 MOD_VEX_W_0_0F93_P_0_LEN_0,
888 MOD_VEX_W_0_0F93_P_2_LEN_0,
889 MOD_VEX_W_0_0F93_P_3_LEN_0,
890 MOD_VEX_W_1_0F93_P_3_LEN_0,
891 MOD_VEX_W_0_0F98_P_0_LEN_0,
892 MOD_VEX_W_1_0F98_P_0_LEN_0,
893 MOD_VEX_W_0_0F98_P_2_LEN_0,
894 MOD_VEX_W_1_0F98_P_2_LEN_0,
895 MOD_VEX_W_0_0F99_P_0_LEN_0,
896 MOD_VEX_W_1_0F99_P_0_LEN_0,
897 MOD_VEX_W_0_0F99_P_2_LEN_0,
898 MOD_VEX_W_1_0F99_P_2_LEN_0,
901 MOD_VEX_0FD7_PREFIX_2,
902 MOD_VEX_0FE7_PREFIX_2,
903 MOD_VEX_0FF0_PREFIX_3,
904 MOD_VEX_0F381A_PREFIX_2,
905 MOD_VEX_0F382A_PREFIX_2,
906 MOD_VEX_0F382C_PREFIX_2,
907 MOD_VEX_0F382D_PREFIX_2,
908 MOD_VEX_0F382E_PREFIX_2,
909 MOD_VEX_0F382F_PREFIX_2,
910 MOD_VEX_0F385A_PREFIX_2,
911 MOD_VEX_0F388C_PREFIX_2,
912 MOD_VEX_0F388E_PREFIX_2,
913 MOD_VEX_W_0_0F3A30_P_2_LEN_0,
914 MOD_VEX_W_1_0F3A30_P_2_LEN_0,
915 MOD_VEX_W_0_0F3A31_P_2_LEN_0,
916 MOD_VEX_W_1_0F3A31_P_2_LEN_0,
917 MOD_VEX_W_0_0F3A32_P_2_LEN_0,
918 MOD_VEX_W_1_0F3A32_P_2_LEN_0,
919 MOD_VEX_W_0_0F3A33_P_2_LEN_0,
920 MOD_VEX_W_1_0F3A33_P_2_LEN_0,
922 MOD_EVEX_0F10_PREFIX_1,
923 MOD_EVEX_0F10_PREFIX_3,
924 MOD_EVEX_0F11_PREFIX_1,
925 MOD_EVEX_0F11_PREFIX_3,
926 MOD_EVEX_0F12_PREFIX_0,
927 MOD_EVEX_0F16_PREFIX_0,
928 MOD_EVEX_0F38C6_REG_1,
929 MOD_EVEX_0F38C6_REG_2,
930 MOD_EVEX_0F38C6_REG_5,
931 MOD_EVEX_0F38C6_REG_6,
932 MOD_EVEX_0F38C7_REG_1,
933 MOD_EVEX_0F38C7_REG_2,
934 MOD_EVEX_0F38C7_REG_5,
935 MOD_EVEX_0F38C7_REG_6
956 PREFIX_MOD_0_0F01_REG_5,
957 PREFIX_MOD_3_0F01_REG_5_RM_0,
958 PREFIX_MOD_3_0F01_REG_5_RM_2,
1002 PREFIX_MOD_0_0FAE_REG_4,
1003 PREFIX_MOD_3_0FAE_REG_4,
1004 PREFIX_MOD_0_0FAE_REG_5,
1005 PREFIX_MOD_3_0FAE_REG_5,
1013 PREFIX_MOD_0_0FC7_REG_6,
1014 PREFIX_MOD_3_0FC7_REG_6,
1015 PREFIX_MOD_3_0FC7_REG_7,
1143 PREFIX_VEX_0F71_REG_2,
1144 PREFIX_VEX_0F71_REG_4,
1145 PREFIX_VEX_0F71_REG_6,
1146 PREFIX_VEX_0F72_REG_2,
1147 PREFIX_VEX_0F72_REG_4,
1148 PREFIX_VEX_0F72_REG_6,
1149 PREFIX_VEX_0F73_REG_2,
1150 PREFIX_VEX_0F73_REG_3,
1151 PREFIX_VEX_0F73_REG_6,
1152 PREFIX_VEX_0F73_REG_7,
1325 PREFIX_VEX_0F38F3_REG_1,
1326 PREFIX_VEX_0F38F3_REG_2,
1327 PREFIX_VEX_0F38F3_REG_3,
1446 PREFIX_EVEX_0F71_REG_2,
1447 PREFIX_EVEX_0F71_REG_4,
1448 PREFIX_EVEX_0F71_REG_6,
1449 PREFIX_EVEX_0F72_REG_0,
1450 PREFIX_EVEX_0F72_REG_1,
1451 PREFIX_EVEX_0F72_REG_2,
1452 PREFIX_EVEX_0F72_REG_4,
1453 PREFIX_EVEX_0F72_REG_6,
1454 PREFIX_EVEX_0F73_REG_2,
1455 PREFIX_EVEX_0F73_REG_3,
1456 PREFIX_EVEX_0F73_REG_6,
1457 PREFIX_EVEX_0F73_REG_7,
1649 PREFIX_EVEX_0F38C6_REG_1,
1650 PREFIX_EVEX_0F38C6_REG_2,
1651 PREFIX_EVEX_0F38C6_REG_5,
1652 PREFIX_EVEX_0F38C6_REG_6,
1653 PREFIX_EVEX_0F38C7_REG_1,
1654 PREFIX_EVEX_0F38C7_REG_2,
1655 PREFIX_EVEX_0F38C7_REG_5,
1656 PREFIX_EVEX_0F38C7_REG_6,
1758 THREE_BYTE_0F38 = 0,
1785 VEX_LEN_0F10_P_1 = 0,
1789 VEX_LEN_0F12_P_0_M_0,
1790 VEX_LEN_0F12_P_0_M_1,
1793 VEX_LEN_0F16_P_0_M_0,
1794 VEX_LEN_0F16_P_0_M_1,
1858 VEX_LEN_0FAE_R_2_M_0,
1859 VEX_LEN_0FAE_R_3_M_0,
1868 VEX_LEN_0F381A_P_2_M_0,
1871 VEX_LEN_0F385A_P_2_M_0,
1874 VEX_LEN_0F38F3_R_1_P_0,
1875 VEX_LEN_0F38F3_R_2_P_0,
1876 VEX_LEN_0F38F3_R_3_P_0,
1921 VEX_LEN_0FXOP_08_CC,
1922 VEX_LEN_0FXOP_08_CD,
1923 VEX_LEN_0FXOP_08_CE,
1924 VEX_LEN_0FXOP_08_CF,
1925 VEX_LEN_0FXOP_08_EC,
1926 VEX_LEN_0FXOP_08_ED,
1927 VEX_LEN_0FXOP_08_EE,
1928 VEX_LEN_0FXOP_08_EF,
1929 VEX_LEN_0FXOP_09_80,
1963 VEX_W_0F41_P_0_LEN_1,
1964 VEX_W_0F41_P_2_LEN_1,
1965 VEX_W_0F42_P_0_LEN_1,
1966 VEX_W_0F42_P_2_LEN_1,
1967 VEX_W_0F44_P_0_LEN_0,
1968 VEX_W_0F44_P_2_LEN_0,
1969 VEX_W_0F45_P_0_LEN_1,
1970 VEX_W_0F45_P_2_LEN_1,
1971 VEX_W_0F46_P_0_LEN_1,
1972 VEX_W_0F46_P_2_LEN_1,
1973 VEX_W_0F47_P_0_LEN_1,
1974 VEX_W_0F47_P_2_LEN_1,
1975 VEX_W_0F4A_P_0_LEN_1,
1976 VEX_W_0F4A_P_2_LEN_1,
1977 VEX_W_0F4B_P_0_LEN_1,
1978 VEX_W_0F4B_P_2_LEN_1,
2058 VEX_W_0F90_P_0_LEN_0,
2059 VEX_W_0F90_P_2_LEN_0,
2060 VEX_W_0F91_P_0_LEN_0,
2061 VEX_W_0F91_P_2_LEN_0,
2062 VEX_W_0F92_P_0_LEN_0,
2063 VEX_W_0F92_P_2_LEN_0,
2064 VEX_W_0F92_P_3_LEN_0,
2065 VEX_W_0F93_P_0_LEN_0,
2066 VEX_W_0F93_P_2_LEN_0,
2067 VEX_W_0F93_P_3_LEN_0,
2068 VEX_W_0F98_P_0_LEN_0,
2069 VEX_W_0F98_P_2_LEN_0,
2070 VEX_W_0F99_P_0_LEN_0,
2071 VEX_W_0F99_P_2_LEN_0,
2150 VEX_W_0F381A_P_2_M_0,
2162 VEX_W_0F382A_P_2_M_0,
2164 VEX_W_0F382C_P_2_M_0,
2165 VEX_W_0F382D_P_2_M_0,
2166 VEX_W_0F382E_P_2_M_0,
2167 VEX_W_0F382F_P_2_M_0,
2189 VEX_W_0F385A_P_2_M_0,
2214 VEX_W_0F3A30_P_2_LEN_0,
2215 VEX_W_0F3A31_P_2_LEN_0,
2216 VEX_W_0F3A32_P_2_LEN_0,
2217 VEX_W_0F3A33_P_2_LEN_0,
2236 EVEX_W_0F10_P_1_M_0,
2237 EVEX_W_0F10_P_1_M_1,
2239 EVEX_W_0F10_P_3_M_0,
2240 EVEX_W_0F10_P_3_M_1,
2242 EVEX_W_0F11_P_1_M_0,
2243 EVEX_W_0F11_P_1_M_1,
2245 EVEX_W_0F11_P_3_M_0,
2246 EVEX_W_0F11_P_3_M_1,
2247 EVEX_W_0F12_P_0_M_0,
2248 EVEX_W_0F12_P_0_M_1,
2258 EVEX_W_0F16_P_0_M_0,
2259 EVEX_W_0F16_P_0_M_1,
2330 EVEX_W_0F72_R_2_P_2,
2331 EVEX_W_0F72_R_6_P_2,
2332 EVEX_W_0F73_R_2_P_2,
2333 EVEX_W_0F73_R_6_P_2,
2440 EVEX_W_0F38C7_R_1_P_2,
2441 EVEX_W_0F38C7_R_2_P_2,
2442 EVEX_W_0F38C7_R_5_P_2,
2443 EVEX_W_0F38C7_R_6_P_2,
2484 typedef void (*op_rtn) (int bytemode, int sizeflag);
2493 unsigned int prefix_requirement;
2496 /* Upper case letters in the instruction names here are macros.
2497 'A' => print 'b' if no register operands or suffix_always is true
2498 'B' => print 'b' if suffix_always is true
2499 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2501 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2502 suffix_always is true
2503 'E' => print 'e' if 32-bit form of jcxz
2504 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2505 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2506 'H' => print ",pt" or ",pn" branch hint
2507 'I' => honor following macro letter even in Intel mode (implemented only
2508 for some of the macro letters)
2510 'K' => print 'd' or 'q' if rex prefix is present.
2511 'L' => print 'l' if suffix_always is true
2512 'M' => print 'r' if intel_mnemonic is false.
2513 'N' => print 'n' if instruction has no wait "prefix"
2514 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2515 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2516 or suffix_always is true. print 'q' if rex prefix is present.
2517 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2519 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2520 'S' => print 'w', 'l' or 'q' if suffix_always is true
2521 'T' => print 'q' in 64bit mode if instruction has no operand size
2522 prefix and behave as 'P' otherwise
2523 'U' => print 'q' in 64bit mode if instruction has no operand size
2524 prefix and behave as 'Q' otherwise
2525 'V' => print 'q' in 64bit mode if instruction has no operand size
2526 prefix and behave as 'S' otherwise
2527 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2528 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2529 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
2530 suffix_always is true.
2531 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2532 '!' => change condition from true to false or from false to true.
2533 '%' => add 1 upper case letter to the macro.
2534 '^' => print 'w' or 'l' depending on operand size prefix or
2535 suffix_always is true (lcall/ljmp).
2536 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2537 on operand size prefix.
2538 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2539 has no operand size prefix for AMD64 ISA, behave as 'P'
2542 2 upper case letter macros:
2543 "XY" => print 'x' or 'y' if suffix_always is true or no register
2544 operands and no broadcast.
2545 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2546 register operands and no broadcast.
2547 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2548 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2549 or suffix_always is true
2550 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2551 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2552 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2553 "LW" => print 'd', 'q' depending on the VEX.W bit
2554 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2555 an operand size prefix, or suffix_always is true. print
2556 'q' if rex prefix is present.
2558 Many of the above letters print nothing in Intel mode. See "putop"
2561 Braces '{' and '}', and vertical bars '|', indicate alternative
2562 mnemonic strings for AT&T and Intel. */
2564 static const struct dis386 dis386[] = {
2566 { "addB", { Ebh1, Gb }, 0 },
2567 { "addS", { Evh1, Gv }, 0 },
2568 { "addB", { Gb, EbS }, 0 },
2569 { "addS", { Gv, EvS }, 0 },
2570 { "addB", { AL, Ib }, 0 },
2571 { "addS", { eAX, Iv }, 0 },
2572 { X86_64_TABLE (X86_64_06) },
2573 { X86_64_TABLE (X86_64_07) },
2575 { "orB", { Ebh1, Gb }, 0 },
2576 { "orS", { Evh1, Gv }, 0 },
2577 { "orB", { Gb, EbS }, 0 },
2578 { "orS", { Gv, EvS }, 0 },
2579 { "orB", { AL, Ib }, 0 },
2580 { "orS", { eAX, Iv }, 0 },
2581 { X86_64_TABLE (X86_64_0D) },
2582 { Bad_Opcode }, /* 0x0f extended opcode escape */
2584 { "adcB", { Ebh1, Gb }, 0 },
2585 { "adcS", { Evh1, Gv }, 0 },
2586 { "adcB", { Gb, EbS }, 0 },
2587 { "adcS", { Gv, EvS }, 0 },
2588 { "adcB", { AL, Ib }, 0 },
2589 { "adcS", { eAX, Iv }, 0 },
2590 { X86_64_TABLE (X86_64_16) },
2591 { X86_64_TABLE (X86_64_17) },
2593 { "sbbB", { Ebh1, Gb }, 0 },
2594 { "sbbS", { Evh1, Gv }, 0 },
2595 { "sbbB", { Gb, EbS }, 0 },
2596 { "sbbS", { Gv, EvS }, 0 },
2597 { "sbbB", { AL, Ib }, 0 },
2598 { "sbbS", { eAX, Iv }, 0 },
2599 { X86_64_TABLE (X86_64_1E) },
2600 { X86_64_TABLE (X86_64_1F) },
2602 { "andB", { Ebh1, Gb }, 0 },
2603 { "andS", { Evh1, Gv }, 0 },
2604 { "andB", { Gb, EbS }, 0 },
2605 { "andS", { Gv, EvS }, 0 },
2606 { "andB", { AL, Ib }, 0 },
2607 { "andS", { eAX, Iv }, 0 },
2608 { Bad_Opcode }, /* SEG ES prefix */
2609 { X86_64_TABLE (X86_64_27) },
2611 { "subB", { Ebh1, Gb }, 0 },
2612 { "subS", { Evh1, Gv }, 0 },
2613 { "subB", { Gb, EbS }, 0 },
2614 { "subS", { Gv, EvS }, 0 },
2615 { "subB", { AL, Ib }, 0 },
2616 { "subS", { eAX, Iv }, 0 },
2617 { Bad_Opcode }, /* SEG CS prefix */
2618 { X86_64_TABLE (X86_64_2F) },
2620 { "xorB", { Ebh1, Gb }, 0 },
2621 { "xorS", { Evh1, Gv }, 0 },
2622 { "xorB", { Gb, EbS }, 0 },
2623 { "xorS", { Gv, EvS }, 0 },
2624 { "xorB", { AL, Ib }, 0 },
2625 { "xorS", { eAX, Iv }, 0 },
2626 { Bad_Opcode }, /* SEG SS prefix */
2627 { X86_64_TABLE (X86_64_37) },
2629 { "cmpB", { Eb, Gb }, 0 },
2630 { "cmpS", { Ev, Gv }, 0 },
2631 { "cmpB", { Gb, EbS }, 0 },
2632 { "cmpS", { Gv, EvS }, 0 },
2633 { "cmpB", { AL, Ib }, 0 },
2634 { "cmpS", { eAX, Iv }, 0 },
2635 { Bad_Opcode }, /* SEG DS prefix */
2636 { X86_64_TABLE (X86_64_3F) },
2638 { "inc{S|}", { RMeAX }, 0 },
2639 { "inc{S|}", { RMeCX }, 0 },
2640 { "inc{S|}", { RMeDX }, 0 },
2641 { "inc{S|}", { RMeBX }, 0 },
2642 { "inc{S|}", { RMeSP }, 0 },
2643 { "inc{S|}", { RMeBP }, 0 },
2644 { "inc{S|}", { RMeSI }, 0 },
2645 { "inc{S|}", { RMeDI }, 0 },
2647 { "dec{S|}", { RMeAX }, 0 },
2648 { "dec{S|}", { RMeCX }, 0 },
2649 { "dec{S|}", { RMeDX }, 0 },
2650 { "dec{S|}", { RMeBX }, 0 },
2651 { "dec{S|}", { RMeSP }, 0 },
2652 { "dec{S|}", { RMeBP }, 0 },
2653 { "dec{S|}", { RMeSI }, 0 },
2654 { "dec{S|}", { RMeDI }, 0 },
2656 { "pushV", { RMrAX }, 0 },
2657 { "pushV", { RMrCX }, 0 },
2658 { "pushV", { RMrDX }, 0 },
2659 { "pushV", { RMrBX }, 0 },
2660 { "pushV", { RMrSP }, 0 },
2661 { "pushV", { RMrBP }, 0 },
2662 { "pushV", { RMrSI }, 0 },
2663 { "pushV", { RMrDI }, 0 },
2665 { "popV", { RMrAX }, 0 },
2666 { "popV", { RMrCX }, 0 },
2667 { "popV", { RMrDX }, 0 },
2668 { "popV", { RMrBX }, 0 },
2669 { "popV", { RMrSP }, 0 },
2670 { "popV", { RMrBP }, 0 },
2671 { "popV", { RMrSI }, 0 },
2672 { "popV", { RMrDI }, 0 },
2674 { X86_64_TABLE (X86_64_60) },
2675 { X86_64_TABLE (X86_64_61) },
2676 { X86_64_TABLE (X86_64_62) },
2677 { X86_64_TABLE (X86_64_63) },
2678 { Bad_Opcode }, /* seg fs */
2679 { Bad_Opcode }, /* seg gs */
2680 { Bad_Opcode }, /* op size prefix */
2681 { Bad_Opcode }, /* adr size prefix */
2683 { "pushT", { sIv }, 0 },
2684 { "imulS", { Gv, Ev, Iv }, 0 },
2685 { "pushT", { sIbT }, 0 },
2686 { "imulS", { Gv, Ev, sIb }, 0 },
2687 { "ins{b|}", { Ybr, indirDX }, 0 },
2688 { X86_64_TABLE (X86_64_6D) },
2689 { "outs{b|}", { indirDXr, Xb }, 0 },
2690 { X86_64_TABLE (X86_64_6F) },
2692 { "joH", { Jb, BND, cond_jump_flag }, 0 },
2693 { "jnoH", { Jb, BND, cond_jump_flag }, 0 },
2694 { "jbH", { Jb, BND, cond_jump_flag }, 0 },
2695 { "jaeH", { Jb, BND, cond_jump_flag }, 0 },
2696 { "jeH", { Jb, BND, cond_jump_flag }, 0 },
2697 { "jneH", { Jb, BND, cond_jump_flag }, 0 },
2698 { "jbeH", { Jb, BND, cond_jump_flag }, 0 },
2699 { "jaH", { Jb, BND, cond_jump_flag }, 0 },
2701 { "jsH", { Jb, BND, cond_jump_flag }, 0 },
2702 { "jnsH", { Jb, BND, cond_jump_flag }, 0 },
2703 { "jpH", { Jb, BND, cond_jump_flag }, 0 },
2704 { "jnpH", { Jb, BND, cond_jump_flag }, 0 },
2705 { "jlH", { Jb, BND, cond_jump_flag }, 0 },
2706 { "jgeH", { Jb, BND, cond_jump_flag }, 0 },
2707 { "jleH", { Jb, BND, cond_jump_flag }, 0 },
2708 { "jgH", { Jb, BND, cond_jump_flag }, 0 },
2710 { REG_TABLE (REG_80) },
2711 { REG_TABLE (REG_81) },
2712 { X86_64_TABLE (X86_64_82) },
2713 { REG_TABLE (REG_83) },
2714 { "testB", { Eb, Gb }, 0 },
2715 { "testS", { Ev, Gv }, 0 },
2716 { "xchgB", { Ebh2, Gb }, 0 },
2717 { "xchgS", { Evh2, Gv }, 0 },
2719 { "movB", { Ebh3, Gb }, 0 },
2720 { "movS", { Evh3, Gv }, 0 },
2721 { "movB", { Gb, EbS }, 0 },
2722 { "movS", { Gv, EvS }, 0 },
2723 { "movD", { Sv, Sw }, 0 },
2724 { MOD_TABLE (MOD_8D) },
2725 { "movD", { Sw, Sv }, 0 },
2726 { REG_TABLE (REG_8F) },
2728 { PREFIX_TABLE (PREFIX_90) },
2729 { "xchgS", { RMeCX, eAX }, 0 },
2730 { "xchgS", { RMeDX, eAX }, 0 },
2731 { "xchgS", { RMeBX, eAX }, 0 },
2732 { "xchgS", { RMeSP, eAX }, 0 },
2733 { "xchgS", { RMeBP, eAX }, 0 },
2734 { "xchgS", { RMeSI, eAX }, 0 },
2735 { "xchgS", { RMeDI, eAX }, 0 },
2737 { "cW{t|}R", { XX }, 0 },
2738 { "cR{t|}O", { XX }, 0 },
2739 { X86_64_TABLE (X86_64_9A) },
2740 { Bad_Opcode }, /* fwait */
2741 { "pushfT", { XX }, 0 },
2742 { "popfT", { XX }, 0 },
2743 { "sahf", { XX }, 0 },
2744 { "lahf", { XX }, 0 },
2746 { "mov%LB", { AL, Ob }, 0 },
2747 { "mov%LS", { eAX, Ov }, 0 },
2748 { "mov%LB", { Ob, AL }, 0 },
2749 { "mov%LS", { Ov, eAX }, 0 },
2750 { "movs{b|}", { Ybr, Xb }, 0 },
2751 { "movs{R|}", { Yvr, Xv }, 0 },
2752 { "cmps{b|}", { Xb, Yb }, 0 },
2753 { "cmps{R|}", { Xv, Yv }, 0 },
2755 { "testB", { AL, Ib }, 0 },
2756 { "testS", { eAX, Iv }, 0 },
2757 { "stosB", { Ybr, AL }, 0 },
2758 { "stosS", { Yvr, eAX }, 0 },
2759 { "lodsB", { ALr, Xb }, 0 },
2760 { "lodsS", { eAXr, Xv }, 0 },
2761 { "scasB", { AL, Yb }, 0 },
2762 { "scasS", { eAX, Yv }, 0 },
2764 { "movB", { RMAL, Ib }, 0 },
2765 { "movB", { RMCL, Ib }, 0 },
2766 { "movB", { RMDL, Ib }, 0 },
2767 { "movB", { RMBL, Ib }, 0 },
2768 { "movB", { RMAH, Ib }, 0 },
2769 { "movB", { RMCH, Ib }, 0 },
2770 { "movB", { RMDH, Ib }, 0 },
2771 { "movB", { RMBH, Ib }, 0 },
2773 { "mov%LV", { RMeAX, Iv64 }, 0 },
2774 { "mov%LV", { RMeCX, Iv64 }, 0 },
2775 { "mov%LV", { RMeDX, Iv64 }, 0 },
2776 { "mov%LV", { RMeBX, Iv64 }, 0 },
2777 { "mov%LV", { RMeSP, Iv64 }, 0 },
2778 { "mov%LV", { RMeBP, Iv64 }, 0 },
2779 { "mov%LV", { RMeSI, Iv64 }, 0 },
2780 { "mov%LV", { RMeDI, Iv64 }, 0 },
2782 { REG_TABLE (REG_C0) },
2783 { REG_TABLE (REG_C1) },
2784 { "retT", { Iw, BND }, 0 },
2785 { "retT", { BND }, 0 },
2786 { X86_64_TABLE (X86_64_C4) },
2787 { X86_64_TABLE (X86_64_C5) },
2788 { REG_TABLE (REG_C6) },
2789 { REG_TABLE (REG_C7) },
2791 { "enterT", { Iw, Ib }, 0 },
2792 { "leaveT", { XX }, 0 },
2793 { "Jret{|f}P", { Iw }, 0 },
2794 { "Jret{|f}P", { XX }, 0 },
2795 { "int3", { XX }, 0 },
2796 { "int", { Ib }, 0 },
2797 { X86_64_TABLE (X86_64_CE) },
2798 { "iret%LP", { XX }, 0 },
2800 { REG_TABLE (REG_D0) },
2801 { REG_TABLE (REG_D1) },
2802 { REG_TABLE (REG_D2) },
2803 { REG_TABLE (REG_D3) },
2804 { X86_64_TABLE (X86_64_D4) },
2805 { X86_64_TABLE (X86_64_D5) },
2807 { "xlat", { DSBX }, 0 },
2818 { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 },
2819 { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 },
2820 { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 },
2821 { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 },
2822 { "inB", { AL, Ib }, 0 },
2823 { "inG", { zAX, Ib }, 0 },
2824 { "outB", { Ib, AL }, 0 },
2825 { "outG", { Ib, zAX }, 0 },
2827 { X86_64_TABLE (X86_64_E8) },
2828 { X86_64_TABLE (X86_64_E9) },
2829 { X86_64_TABLE (X86_64_EA) },
2830 { "jmp", { Jb, BND }, 0 },
2831 { "inB", { AL, indirDX }, 0 },
2832 { "inG", { zAX, indirDX }, 0 },
2833 { "outB", { indirDX, AL }, 0 },
2834 { "outG", { indirDX, zAX }, 0 },
2836 { Bad_Opcode }, /* lock prefix */
2837 { "icebp", { XX }, 0 },
2838 { Bad_Opcode }, /* repne */
2839 { Bad_Opcode }, /* repz */
2840 { "hlt", { XX }, 0 },
2841 { "cmc", { XX }, 0 },
2842 { REG_TABLE (REG_F6) },
2843 { REG_TABLE (REG_F7) },
2845 { "clc", { XX }, 0 },
2846 { "stc", { XX }, 0 },
2847 { "cli", { XX }, 0 },
2848 { "sti", { XX }, 0 },
2849 { "cld", { XX }, 0 },
2850 { "std", { XX }, 0 },
2851 { REG_TABLE (REG_FE) },
2852 { REG_TABLE (REG_FF) },
2855 static const struct dis386 dis386_twobyte[] = {
2857 { REG_TABLE (REG_0F00 ) },
2858 { REG_TABLE (REG_0F01 ) },
2859 { "larS", { Gv, Ew }, 0 },
2860 { "lslS", { Gv, Ew }, 0 },
2862 { "syscall", { XX }, 0 },
2863 { "clts", { XX }, 0 },
2864 { "sysret%LP", { XX }, 0 },
2866 { "invd", { XX }, 0 },
2867 { "wbinvd", { XX }, 0 },
2869 { "ud2", { XX }, 0 },
2871 { REG_TABLE (REG_0F0D) },
2872 { "femms", { XX }, 0 },
2873 { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */
2875 { PREFIX_TABLE (PREFIX_0F10) },
2876 { PREFIX_TABLE (PREFIX_0F11) },
2877 { PREFIX_TABLE (PREFIX_0F12) },
2878 { MOD_TABLE (MOD_0F13) },
2879 { "unpcklpX", { XM, EXx }, PREFIX_OPCODE },
2880 { "unpckhpX", { XM, EXx }, PREFIX_OPCODE },
2881 { PREFIX_TABLE (PREFIX_0F16) },
2882 { MOD_TABLE (MOD_0F17) },
2884 { REG_TABLE (REG_0F18) },
2885 { "nopQ", { Ev }, 0 },
2886 { PREFIX_TABLE (PREFIX_0F1A) },
2887 { PREFIX_TABLE (PREFIX_0F1B) },
2888 { "nopQ", { Ev }, 0 },
2889 { "nopQ", { Ev }, 0 },
2890 { PREFIX_TABLE (PREFIX_0F1E) },
2891 { "nopQ", { Ev }, 0 },
2893 { "movZ", { Rm, Cm }, 0 },
2894 { "movZ", { Rm, Dm }, 0 },
2895 { "movZ", { Cm, Rm }, 0 },
2896 { "movZ", { Dm, Rm }, 0 },
2897 { MOD_TABLE (MOD_0F24) },
2899 { MOD_TABLE (MOD_0F26) },
2902 { "movapX", { XM, EXx }, PREFIX_OPCODE },
2903 { "movapX", { EXxS, XM }, PREFIX_OPCODE },
2904 { PREFIX_TABLE (PREFIX_0F2A) },
2905 { PREFIX_TABLE (PREFIX_0F2B) },
2906 { PREFIX_TABLE (PREFIX_0F2C) },
2907 { PREFIX_TABLE (PREFIX_0F2D) },
2908 { PREFIX_TABLE (PREFIX_0F2E) },
2909 { PREFIX_TABLE (PREFIX_0F2F) },
2911 { "wrmsr", { XX }, 0 },
2912 { "rdtsc", { XX }, 0 },
2913 { "rdmsr", { XX }, 0 },
2914 { "rdpmc", { XX }, 0 },
2915 { "sysenter", { XX }, 0 },
2916 { "sysexit", { XX }, 0 },
2918 { "getsec", { XX }, 0 },
2920 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2922 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2929 { "cmovoS", { Gv, Ev }, 0 },
2930 { "cmovnoS", { Gv, Ev }, 0 },
2931 { "cmovbS", { Gv, Ev }, 0 },
2932 { "cmovaeS", { Gv, Ev }, 0 },
2933 { "cmoveS", { Gv, Ev }, 0 },
2934 { "cmovneS", { Gv, Ev }, 0 },
2935 { "cmovbeS", { Gv, Ev }, 0 },
2936 { "cmovaS", { Gv, Ev }, 0 },
2938 { "cmovsS", { Gv, Ev }, 0 },
2939 { "cmovnsS", { Gv, Ev }, 0 },
2940 { "cmovpS", { Gv, Ev }, 0 },
2941 { "cmovnpS", { Gv, Ev }, 0 },
2942 { "cmovlS", { Gv, Ev }, 0 },
2943 { "cmovgeS", { Gv, Ev }, 0 },
2944 { "cmovleS", { Gv, Ev }, 0 },
2945 { "cmovgS", { Gv, Ev }, 0 },
2947 { MOD_TABLE (MOD_0F51) },
2948 { PREFIX_TABLE (PREFIX_0F51) },
2949 { PREFIX_TABLE (PREFIX_0F52) },
2950 { PREFIX_TABLE (PREFIX_0F53) },
2951 { "andpX", { XM, EXx }, PREFIX_OPCODE },
2952 { "andnpX", { XM, EXx }, PREFIX_OPCODE },
2953 { "orpX", { XM, EXx }, PREFIX_OPCODE },
2954 { "xorpX", { XM, EXx }, PREFIX_OPCODE },
2956 { PREFIX_TABLE (PREFIX_0F58) },
2957 { PREFIX_TABLE (PREFIX_0F59) },
2958 { PREFIX_TABLE (PREFIX_0F5A) },
2959 { PREFIX_TABLE (PREFIX_0F5B) },
2960 { PREFIX_TABLE (PREFIX_0F5C) },
2961 { PREFIX_TABLE (PREFIX_0F5D) },
2962 { PREFIX_TABLE (PREFIX_0F5E) },
2963 { PREFIX_TABLE (PREFIX_0F5F) },
2965 { PREFIX_TABLE (PREFIX_0F60) },
2966 { PREFIX_TABLE (PREFIX_0F61) },
2967 { PREFIX_TABLE (PREFIX_0F62) },
2968 { "packsswb", { MX, EM }, PREFIX_OPCODE },
2969 { "pcmpgtb", { MX, EM }, PREFIX_OPCODE },
2970 { "pcmpgtw", { MX, EM }, PREFIX_OPCODE },
2971 { "pcmpgtd", { MX, EM }, PREFIX_OPCODE },
2972 { "packuswb", { MX, EM }, PREFIX_OPCODE },
2974 { "punpckhbw", { MX, EM }, PREFIX_OPCODE },
2975 { "punpckhwd", { MX, EM }, PREFIX_OPCODE },
2976 { "punpckhdq", { MX, EM }, PREFIX_OPCODE },
2977 { "packssdw", { MX, EM }, PREFIX_OPCODE },
2978 { PREFIX_TABLE (PREFIX_0F6C) },
2979 { PREFIX_TABLE (PREFIX_0F6D) },
2980 { "movK", { MX, Edq }, PREFIX_OPCODE },
2981 { PREFIX_TABLE (PREFIX_0F6F) },
2983 { PREFIX_TABLE (PREFIX_0F70) },
2984 { REG_TABLE (REG_0F71) },
2985 { REG_TABLE (REG_0F72) },
2986 { REG_TABLE (REG_0F73) },
2987 { "pcmpeqb", { MX, EM }, PREFIX_OPCODE },
2988 { "pcmpeqw", { MX, EM }, PREFIX_OPCODE },
2989 { "pcmpeqd", { MX, EM }, PREFIX_OPCODE },
2990 { "emms", { XX }, PREFIX_OPCODE },
2992 { PREFIX_TABLE (PREFIX_0F78) },
2993 { PREFIX_TABLE (PREFIX_0F79) },
2996 { PREFIX_TABLE (PREFIX_0F7C) },
2997 { PREFIX_TABLE (PREFIX_0F7D) },
2998 { PREFIX_TABLE (PREFIX_0F7E) },
2999 { PREFIX_TABLE (PREFIX_0F7F) },
3001 { "joH", { Jv, BND, cond_jump_flag }, 0 },
3002 { "jnoH", { Jv, BND, cond_jump_flag }, 0 },
3003 { "jbH", { Jv, BND, cond_jump_flag }, 0 },
3004 { "jaeH", { Jv, BND, cond_jump_flag }, 0 },
3005 { "jeH", { Jv, BND, cond_jump_flag }, 0 },
3006 { "jneH", { Jv, BND, cond_jump_flag }, 0 },
3007 { "jbeH", { Jv, BND, cond_jump_flag }, 0 },
3008 { "jaH", { Jv, BND, cond_jump_flag }, 0 },
3010 { "jsH", { Jv, BND, cond_jump_flag }, 0 },
3011 { "jnsH", { Jv, BND, cond_jump_flag }, 0 },
3012 { "jpH", { Jv, BND, cond_jump_flag }, 0 },
3013 { "jnpH", { Jv, BND, cond_jump_flag }, 0 },
3014 { "jlH", { Jv, BND, cond_jump_flag }, 0 },
3015 { "jgeH", { Jv, BND, cond_jump_flag }, 0 },
3016 { "jleH", { Jv, BND, cond_jump_flag }, 0 },
3017 { "jgH", { Jv, BND, cond_jump_flag }, 0 },
3019 { "seto", { Eb }, 0 },
3020 { "setno", { Eb }, 0 },
3021 { "setb", { Eb }, 0 },
3022 { "setae", { Eb }, 0 },
3023 { "sete", { Eb }, 0 },
3024 { "setne", { Eb }, 0 },
3025 { "setbe", { Eb }, 0 },
3026 { "seta", { Eb }, 0 },
3028 { "sets", { Eb }, 0 },
3029 { "setns", { Eb }, 0 },
3030 { "setp", { Eb }, 0 },
3031 { "setnp", { Eb }, 0 },
3032 { "setl", { Eb }, 0 },
3033 { "setge", { Eb }, 0 },
3034 { "setle", { Eb }, 0 },
3035 { "setg", { Eb }, 0 },
3037 { "pushT", { fs }, 0 },
3038 { "popT", { fs }, 0 },
3039 { "cpuid", { XX }, 0 },
3040 { "btS", { Ev, Gv }, 0 },
3041 { "shldS", { Ev, Gv, Ib }, 0 },
3042 { "shldS", { Ev, Gv, CL }, 0 },
3043 { REG_TABLE (REG_0FA6) },
3044 { REG_TABLE (REG_0FA7) },
3046 { "pushT", { gs }, 0 },
3047 { "popT", { gs }, 0 },
3048 { "rsm", { XX }, 0 },
3049 { "btsS", { Evh1, Gv }, 0 },
3050 { "shrdS", { Ev, Gv, Ib }, 0 },
3051 { "shrdS", { Ev, Gv, CL }, 0 },
3052 { REG_TABLE (REG_0FAE) },
3053 { "imulS", { Gv, Ev }, 0 },
3055 { "cmpxchgB", { Ebh1, Gb }, 0 },
3056 { "cmpxchgS", { Evh1, Gv }, 0 },
3057 { MOD_TABLE (MOD_0FB2) },
3058 { "btrS", { Evh1, Gv }, 0 },
3059 { MOD_TABLE (MOD_0FB4) },
3060 { MOD_TABLE (MOD_0FB5) },
3061 { "movz{bR|x}", { Gv, Eb }, 0 },
3062 { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
3064 { PREFIX_TABLE (PREFIX_0FB8) },
3065 { "ud1", { XX }, 0 },
3066 { REG_TABLE (REG_0FBA) },
3067 { "btcS", { Evh1, Gv }, 0 },
3068 { PREFIX_TABLE (PREFIX_0FBC) },
3069 { PREFIX_TABLE (PREFIX_0FBD) },
3070 { "movs{bR|x}", { Gv, Eb }, 0 },
3071 { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
3073 { "xaddB", { Ebh1, Gb }, 0 },
3074 { "xaddS", { Evh1, Gv }, 0 },
3075 { PREFIX_TABLE (PREFIX_0FC2) },
3076 { MOD_TABLE (MOD_0FC3) },
3077 { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE },
3078 { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE },
3079 { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE },
3080 { REG_TABLE (REG_0FC7) },
3082 { "bswap", { RMeAX }, 0 },
3083 { "bswap", { RMeCX }, 0 },
3084 { "bswap", { RMeDX }, 0 },
3085 { "bswap", { RMeBX }, 0 },
3086 { "bswap", { RMeSP }, 0 },
3087 { "bswap", { RMeBP }, 0 },
3088 { "bswap", { RMeSI }, 0 },
3089 { "bswap", { RMeDI }, 0 },
3091 { PREFIX_TABLE (PREFIX_0FD0) },
3092 { "psrlw", { MX, EM }, PREFIX_OPCODE },
3093 { "psrld", { MX, EM }, PREFIX_OPCODE },
3094 { "psrlq", { MX, EM }, PREFIX_OPCODE },
3095 { "paddq", { MX, EM }, PREFIX_OPCODE },
3096 { "pmullw", { MX, EM }, PREFIX_OPCODE },
3097 { PREFIX_TABLE (PREFIX_0FD6) },
3098 { MOD_TABLE (MOD_0FD7) },
3100 { "psubusb", { MX, EM }, PREFIX_OPCODE },
3101 { "psubusw", { MX, EM }, PREFIX_OPCODE },
3102 { "pminub", { MX, EM }, PREFIX_OPCODE },
3103 { "pand", { MX, EM }, PREFIX_OPCODE },
3104 { "paddusb", { MX, EM }, PREFIX_OPCODE },
3105 { "paddusw", { MX, EM }, PREFIX_OPCODE },
3106 { "pmaxub", { MX, EM }, PREFIX_OPCODE },
3107 { "pandn", { MX, EM }, PREFIX_OPCODE },
3109 { "pavgb", { MX, EM }, PREFIX_OPCODE },
3110 { "psraw", { MX, EM }, PREFIX_OPCODE },
3111 { "psrad", { MX, EM }, PREFIX_OPCODE },
3112 { "pavgw", { MX, EM }, PREFIX_OPCODE },
3113 { "pmulhuw", { MX, EM }, PREFIX_OPCODE },
3114 { "pmulhw", { MX, EM }, PREFIX_OPCODE },
3115 { PREFIX_TABLE (PREFIX_0FE6) },
3116 { PREFIX_TABLE (PREFIX_0FE7) },
3118 { "psubsb", { MX, EM }, PREFIX_OPCODE },
3119 { "psubsw", { MX, EM }, PREFIX_OPCODE },
3120 { "pminsw", { MX, EM }, PREFIX_OPCODE },
3121 { "por", { MX, EM }, PREFIX_OPCODE },
3122 { "paddsb", { MX, EM }, PREFIX_OPCODE },
3123 { "paddsw", { MX, EM }, PREFIX_OPCODE },
3124 { "pmaxsw", { MX, EM }, PREFIX_OPCODE },
3125 { "pxor", { MX, EM }, PREFIX_OPCODE },
3127 { PREFIX_TABLE (PREFIX_0FF0) },
3128 { "psllw", { MX, EM }, PREFIX_OPCODE },
3129 { "pslld", { MX, EM }, PREFIX_OPCODE },
3130 { "psllq", { MX, EM }, PREFIX_OPCODE },
3131 { "pmuludq", { MX, EM }, PREFIX_OPCODE },
3132 { "pmaddwd", { MX, EM }, PREFIX_OPCODE },
3133 { "psadbw", { MX, EM }, PREFIX_OPCODE },
3134 { PREFIX_TABLE (PREFIX_0FF7) },
3136 { "psubb", { MX, EM }, PREFIX_OPCODE },
3137 { "psubw", { MX, EM }, PREFIX_OPCODE },
3138 { "psubd", { MX, EM }, PREFIX_OPCODE },
3139 { "psubq", { MX, EM }, PREFIX_OPCODE },
3140 { "paddb", { MX, EM }, PREFIX_OPCODE },
3141 { "paddw", { MX, EM }, PREFIX_OPCODE },
3142 { "paddd", { MX, EM }, PREFIX_OPCODE },
3146 static const unsigned char onebyte_has_modrm[256] = {
3147 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3148 /* ------------------------------- */
3149 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3150 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3151 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3152 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3153 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3154 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3155 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3156 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3157 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3158 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3159 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3160 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3161 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3162 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3163 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3164 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
3165 /* ------------------------------- */
3166 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3169 static const unsigned char twobyte_has_modrm[256] = {
3170 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3171 /* ------------------------------- */
3172 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3173 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3174 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3175 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3176 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3177 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3178 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3179 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3180 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3181 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3182 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3183 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
3184 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3185 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3186 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3187 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
3188 /* ------------------------------- */
3189 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3192 static char obuf[100];
3194 static char *mnemonicendp;
3195 static char scratchbuf[100];
3196 static unsigned char *start_codep;
3197 static unsigned char *insn_codep;
3198 static unsigned char *codep;
3199 static unsigned char *end_codep;
3200 static int last_lock_prefix;
3201 static int last_repz_prefix;
3202 static int last_repnz_prefix;
3203 static int last_data_prefix;
3204 static int last_addr_prefix;
3205 static int last_rex_prefix;
3206 static int last_seg_prefix;
3207 static int fwait_prefix;
3208 /* The active segment register prefix. */
3209 static int active_seg_prefix;
3210 #define MAX_CODE_LENGTH 15
3211 /* We can up to 14 prefixes since the maximum instruction length is
3213 static int all_prefixes[MAX_CODE_LENGTH - 1];
3214 static disassemble_info *the_info;
3222 static unsigned char need_modrm;
3232 int register_specifier;
3239 int mask_register_specifier;
3245 static unsigned char need_vex;
3246 static unsigned char need_vex_reg;
3247 static unsigned char vex_w_done;
3255 /* If we are accessing mod/rm/reg without need_modrm set, then the
3256 values are stale. Hitting this abort likely indicates that you
3257 need to update onebyte_has_modrm or twobyte_has_modrm. */
3258 #define MODRM_CHECK if (!need_modrm) abort ()
3260 static const char **names64;
3261 static const char **names32;
3262 static const char **names16;
3263 static const char **names8;
3264 static const char **names8rex;
3265 static const char **names_seg;
3266 static const char *index64;
3267 static const char *index32;
3268 static const char **index16;
3269 static const char **names_bnd;
3271 static const char *intel_names64[] = {
3272 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3273 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3275 static const char *intel_names32[] = {
3276 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3277 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3279 static const char *intel_names16[] = {
3280 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3281 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3283 static const char *intel_names8[] = {
3284 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3286 static const char *intel_names8rex[] = {
3287 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3288 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3290 static const char *intel_names_seg[] = {
3291 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3293 static const char *intel_index64 = "riz";
3294 static const char *intel_index32 = "eiz";
3295 static const char *intel_index16[] = {
3296 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3299 static const char *att_names64[] = {
3300 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3301 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3303 static const char *att_names32[] = {
3304 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3305 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3307 static const char *att_names16[] = {
3308 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3309 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3311 static const char *att_names8[] = {
3312 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3314 static const char *att_names8rex[] = {
3315 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3316 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3318 static const char *att_names_seg[] = {
3319 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3321 static const char *att_index64 = "%riz";
3322 static const char *att_index32 = "%eiz";
3323 static const char *att_index16[] = {
3324 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3327 static const char **names_mm;
3328 static const char *intel_names_mm[] = {
3329 "mm0", "mm1", "mm2", "mm3",
3330 "mm4", "mm5", "mm6", "mm7"
3332 static const char *att_names_mm[] = {
3333 "%mm0", "%mm1", "%mm2", "%mm3",
3334 "%mm4", "%mm5", "%mm6", "%mm7"
3337 static const char *intel_names_bnd[] = {
3338 "bnd0", "bnd1", "bnd2", "bnd3"
3341 static const char *att_names_bnd[] = {
3342 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3345 static const char **names_xmm;
3346 static const char *intel_names_xmm[] = {
3347 "xmm0", "xmm1", "xmm2", "xmm3",
3348 "xmm4", "xmm5", "xmm6", "xmm7",
3349 "xmm8", "xmm9", "xmm10", "xmm11",
3350 "xmm12", "xmm13", "xmm14", "xmm15",
3351 "xmm16", "xmm17", "xmm18", "xmm19",
3352 "xmm20", "xmm21", "xmm22", "xmm23",
3353 "xmm24", "xmm25", "xmm26", "xmm27",
3354 "xmm28", "xmm29", "xmm30", "xmm31"
3356 static const char *att_names_xmm[] = {
3357 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3358 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3359 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3360 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3361 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3362 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3363 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3364 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3367 static const char **names_ymm;
3368 static const char *intel_names_ymm[] = {
3369 "ymm0", "ymm1", "ymm2", "ymm3",
3370 "ymm4", "ymm5", "ymm6", "ymm7",
3371 "ymm8", "ymm9", "ymm10", "ymm11",
3372 "ymm12", "ymm13", "ymm14", "ymm15",
3373 "ymm16", "ymm17", "ymm18", "ymm19",
3374 "ymm20", "ymm21", "ymm22", "ymm23",
3375 "ymm24", "ymm25", "ymm26", "ymm27",
3376 "ymm28", "ymm29", "ymm30", "ymm31"
3378 static const char *att_names_ymm[] = {
3379 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3380 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3381 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3382 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3383 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3384 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3385 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3386 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3389 static const char **names_zmm;
3390 static const char *intel_names_zmm[] = {
3391 "zmm0", "zmm1", "zmm2", "zmm3",
3392 "zmm4", "zmm5", "zmm6", "zmm7",
3393 "zmm8", "zmm9", "zmm10", "zmm11",
3394 "zmm12", "zmm13", "zmm14", "zmm15",
3395 "zmm16", "zmm17", "zmm18", "zmm19",
3396 "zmm20", "zmm21", "zmm22", "zmm23",
3397 "zmm24", "zmm25", "zmm26", "zmm27",
3398 "zmm28", "zmm29", "zmm30", "zmm31"
3400 static const char *att_names_zmm[] = {
3401 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3402 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3403 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3404 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3405 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3406 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3407 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3408 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3411 static const char **names_mask;
3412 static const char *intel_names_mask[] = {
3413 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3415 static const char *att_names_mask[] = {
3416 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3419 static const char *names_rounding[] =
3427 static const struct dis386 reg_table[][8] = {
3430 { "addA", { Ebh1, Ib }, 0 },
3431 { "orA", { Ebh1, Ib }, 0 },
3432 { "adcA", { Ebh1, Ib }, 0 },
3433 { "sbbA", { Ebh1, Ib }, 0 },
3434 { "andA", { Ebh1, Ib }, 0 },
3435 { "subA", { Ebh1, Ib }, 0 },
3436 { "xorA", { Ebh1, Ib }, 0 },
3437 { "cmpA", { Eb, Ib }, 0 },
3441 { "addQ", { Evh1, Iv }, 0 },
3442 { "orQ", { Evh1, Iv }, 0 },
3443 { "adcQ", { Evh1, Iv }, 0 },
3444 { "sbbQ", { Evh1, Iv }, 0 },
3445 { "andQ", { Evh1, Iv }, 0 },
3446 { "subQ", { Evh1, Iv }, 0 },
3447 { "xorQ", { Evh1, Iv }, 0 },
3448 { "cmpQ", { Ev, Iv }, 0 },
3452 { "addQ", { Evh1, sIb }, 0 },
3453 { "orQ", { Evh1, sIb }, 0 },
3454 { "adcQ", { Evh1, sIb }, 0 },
3455 { "sbbQ", { Evh1, sIb }, 0 },
3456 { "andQ", { Evh1, sIb }, 0 },
3457 { "subQ", { Evh1, sIb }, 0 },
3458 { "xorQ", { Evh1, sIb }, 0 },
3459 { "cmpQ", { Ev, sIb }, 0 },
3463 { "popU", { stackEv }, 0 },
3464 { XOP_8F_TABLE (XOP_09) },
3468 { XOP_8F_TABLE (XOP_09) },
3472 { "rolA", { Eb, Ib }, 0 },
3473 { "rorA", { Eb, Ib }, 0 },
3474 { "rclA", { Eb, Ib }, 0 },
3475 { "rcrA", { Eb, Ib }, 0 },
3476 { "shlA", { Eb, Ib }, 0 },
3477 { "shrA", { Eb, Ib }, 0 },
3478 { "shlA", { Eb, Ib }, 0 },
3479 { "sarA", { Eb, Ib }, 0 },
3483 { "rolQ", { Ev, Ib }, 0 },
3484 { "rorQ", { Ev, Ib }, 0 },
3485 { "rclQ", { Ev, Ib }, 0 },
3486 { "rcrQ", { Ev, Ib }, 0 },
3487 { "shlQ", { Ev, Ib }, 0 },
3488 { "shrQ", { Ev, Ib }, 0 },
3489 { "shlQ", { Ev, Ib }, 0 },
3490 { "sarQ", { Ev, Ib }, 0 },
3494 { "movA", { Ebh3, Ib }, 0 },
3501 { MOD_TABLE (MOD_C6_REG_7) },
3505 { "movQ", { Evh3, Iv }, 0 },
3512 { MOD_TABLE (MOD_C7_REG_7) },
3516 { "rolA", { Eb, I1 }, 0 },
3517 { "rorA", { Eb, I1 }, 0 },
3518 { "rclA", { Eb, I1 }, 0 },
3519 { "rcrA", { Eb, I1 }, 0 },
3520 { "shlA", { Eb, I1 }, 0 },
3521 { "shrA", { Eb, I1 }, 0 },
3522 { "shlA", { Eb, I1 }, 0 },
3523 { "sarA", { Eb, I1 }, 0 },
3527 { "rolQ", { Ev, I1 }, 0 },
3528 { "rorQ", { Ev, I1 }, 0 },
3529 { "rclQ", { Ev, I1 }, 0 },
3530 { "rcrQ", { Ev, I1 }, 0 },
3531 { "shlQ", { Ev, I1 }, 0 },
3532 { "shrQ", { Ev, I1 }, 0 },
3533 { "shlQ", { Ev, I1 }, 0 },
3534 { "sarQ", { Ev, I1 }, 0 },
3538 { "rolA", { Eb, CL }, 0 },
3539 { "rorA", { Eb, CL }, 0 },
3540 { "rclA", { Eb, CL }, 0 },
3541 { "rcrA", { Eb, CL }, 0 },
3542 { "shlA", { Eb, CL }, 0 },
3543 { "shrA", { Eb, CL }, 0 },
3544 { "shlA", { Eb, CL }, 0 },
3545 { "sarA", { Eb, CL }, 0 },
3549 { "rolQ", { Ev, CL }, 0 },
3550 { "rorQ", { Ev, CL }, 0 },
3551 { "rclQ", { Ev, CL }, 0 },
3552 { "rcrQ", { Ev, CL }, 0 },
3553 { "shlQ", { Ev, CL }, 0 },
3554 { "shrQ", { Ev, CL }, 0 },
3555 { "shlQ", { Ev, CL }, 0 },
3556 { "sarQ", { Ev, CL }, 0 },
3560 { "testA", { Eb, Ib }, 0 },
3561 { "testA", { Eb, Ib }, 0 },
3562 { "notA", { Ebh1 }, 0 },
3563 { "negA", { Ebh1 }, 0 },
3564 { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */
3565 { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */
3566 { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */
3567 { "idivA", { Eb }, 0 }, /* and idiv for consistency. */
3571 { "testQ", { Ev, Iv }, 0 },
3572 { "testQ", { Ev, Iv }, 0 },
3573 { "notQ", { Evh1 }, 0 },
3574 { "negQ", { Evh1 }, 0 },
3575 { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */
3576 { "imulQ", { Ev }, 0 },
3577 { "divQ", { Ev }, 0 },
3578 { "idivQ", { Ev }, 0 },
3582 { "incA", { Ebh1 }, 0 },
3583 { "decA", { Ebh1 }, 0 },
3587 { "incQ", { Evh1 }, 0 },
3588 { "decQ", { Evh1 }, 0 },
3589 { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3590 { MOD_TABLE (MOD_FF_REG_3) },
3591 { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3592 { MOD_TABLE (MOD_FF_REG_5) },
3593 { "pushU", { stackEv }, 0 },
3598 { "sldtD", { Sv }, 0 },
3599 { "strD", { Sv }, 0 },
3600 { "lldt", { Ew }, 0 },
3601 { "ltr", { Ew }, 0 },
3602 { "verr", { Ew }, 0 },
3603 { "verw", { Ew }, 0 },
3609 { MOD_TABLE (MOD_0F01_REG_0) },
3610 { MOD_TABLE (MOD_0F01_REG_1) },
3611 { MOD_TABLE (MOD_0F01_REG_2) },
3612 { MOD_TABLE (MOD_0F01_REG_3) },
3613 { "smswD", { Sv }, 0 },
3614 { MOD_TABLE (MOD_0F01_REG_5) },
3615 { "lmsw", { Ew }, 0 },
3616 { MOD_TABLE (MOD_0F01_REG_7) },
3620 { "prefetch", { Mb }, 0 },
3621 { "prefetchw", { Mb }, 0 },
3622 { "prefetchwt1", { Mb }, 0 },
3623 { "prefetch", { Mb }, 0 },
3624 { "prefetch", { Mb }, 0 },
3625 { "prefetch", { Mb }, 0 },
3626 { "prefetch", { Mb }, 0 },
3627 { "prefetch", { Mb }, 0 },
3631 { MOD_TABLE (MOD_0F18_REG_0) },
3632 { MOD_TABLE (MOD_0F18_REG_1) },
3633 { MOD_TABLE (MOD_0F18_REG_2) },
3634 { MOD_TABLE (MOD_0F18_REG_3) },
3635 { MOD_TABLE (MOD_0F18_REG_4) },
3636 { MOD_TABLE (MOD_0F18_REG_5) },
3637 { MOD_TABLE (MOD_0F18_REG_6) },
3638 { MOD_TABLE (MOD_0F18_REG_7) },
3640 /* REG_0F1E_MOD_3 */
3642 { "nopQ", { Ev }, 0 },
3643 { "rdsspK", { Rdq }, PREFIX_OPCODE },
3644 { "nopQ", { Ev }, 0 },
3645 { "nopQ", { Ev }, 0 },
3646 { "nopQ", { Ev }, 0 },
3647 { "nopQ", { Ev }, 0 },
3648 { "nopQ", { Ev }, 0 },
3649 { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
3655 { MOD_TABLE (MOD_0F71_REG_2) },
3657 { MOD_TABLE (MOD_0F71_REG_4) },
3659 { MOD_TABLE (MOD_0F71_REG_6) },
3665 { MOD_TABLE (MOD_0F72_REG_2) },
3667 { MOD_TABLE (MOD_0F72_REG_4) },
3669 { MOD_TABLE (MOD_0F72_REG_6) },
3675 { MOD_TABLE (MOD_0F73_REG_2) },
3676 { MOD_TABLE (MOD_0F73_REG_3) },
3679 { MOD_TABLE (MOD_0F73_REG_6) },
3680 { MOD_TABLE (MOD_0F73_REG_7) },
3684 { "montmul", { { OP_0f07, 0 } }, 0 },
3685 { "xsha1", { { OP_0f07, 0 } }, 0 },
3686 { "xsha256", { { OP_0f07, 0 } }, 0 },
3690 { "xstore-rng", { { OP_0f07, 0 } }, 0 },
3691 { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 },
3692 { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 },
3693 { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 },
3694 { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 },
3695 { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 },
3699 { MOD_TABLE (MOD_0FAE_REG_0) },
3700 { MOD_TABLE (MOD_0FAE_REG_1) },
3701 { MOD_TABLE (MOD_0FAE_REG_2) },
3702 { MOD_TABLE (MOD_0FAE_REG_3) },
3703 { MOD_TABLE (MOD_0FAE_REG_4) },
3704 { MOD_TABLE (MOD_0FAE_REG_5) },
3705 { MOD_TABLE (MOD_0FAE_REG_6) },
3706 { MOD_TABLE (MOD_0FAE_REG_7) },
3714 { "btQ", { Ev, Ib }, 0 },
3715 { "btsQ", { Evh1, Ib }, 0 },
3716 { "btrQ", { Evh1, Ib }, 0 },
3717 { "btcQ", { Evh1, Ib }, 0 },
3722 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3724 { MOD_TABLE (MOD_0FC7_REG_3) },
3725 { MOD_TABLE (MOD_0FC7_REG_4) },
3726 { MOD_TABLE (MOD_0FC7_REG_5) },
3727 { MOD_TABLE (MOD_0FC7_REG_6) },
3728 { MOD_TABLE (MOD_0FC7_REG_7) },
3734 { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3736 { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3738 { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3744 { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3746 { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3748 { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3754 { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3755 { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3758 { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3759 { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3765 { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3766 { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3768 /* REG_VEX_0F38F3 */
3771 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3772 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3773 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3777 { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3778 { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3782 { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3783 { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3785 /* REG_XOP_TBM_01 */
3788 { "blcfill", { { OP_LWP_E, 0 }, Ev }, 0 },
3789 { "blsfill", { { OP_LWP_E, 0 }, Ev }, 0 },
3790 { "blcs", { { OP_LWP_E, 0 }, Ev }, 0 },
3791 { "tzmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3792 { "blcic", { { OP_LWP_E, 0 }, Ev }, 0 },
3793 { "blsic", { { OP_LWP_E, 0 }, Ev }, 0 },
3794 { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3796 /* REG_XOP_TBM_02 */
3799 { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3804 { "blci", { { OP_LWP_E, 0 }, Ev }, 0 },
3806 #define NEED_REG_TABLE
3807 #include "i386-dis-evex.h"
3808 #undef NEED_REG_TABLE
3811 static const struct dis386 prefix_table[][4] = {
3814 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3815 { "pause", { XX }, 0 },
3816 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3817 { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3820 /* PREFIX_MOD_0_0F01_REG_5 */
3823 { "rstorssp", { Mq }, PREFIX_OPCODE },
3826 /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3829 { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE },
3832 /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3835 { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE },
3840 { "movups", { XM, EXx }, PREFIX_OPCODE },
3841 { "movss", { XM, EXd }, PREFIX_OPCODE },
3842 { "movupd", { XM, EXx }, PREFIX_OPCODE },
3843 { "movsd", { XM, EXq }, PREFIX_OPCODE },
3848 { "movups", { EXxS, XM }, PREFIX_OPCODE },
3849 { "movss", { EXdS, XM }, PREFIX_OPCODE },
3850 { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3851 { "movsd", { EXqS, XM }, PREFIX_OPCODE },
3856 { MOD_TABLE (MOD_0F12_PREFIX_0) },
3857 { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3858 { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3859 { "movddup", { XM, EXq }, PREFIX_OPCODE },
3864 { MOD_TABLE (MOD_0F16_PREFIX_0) },
3865 { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3866 { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3871 { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3872 { "bndcl", { Gbnd, Ev_bnd }, 0 },
3873 { "bndmov", { Gbnd, Ebnd }, 0 },
3874 { "bndcu", { Gbnd, Ev_bnd }, 0 },
3879 { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3880 { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3881 { "bndmov", { Ebnd, Gbnd }, 0 },
3882 { "bndcn", { Gbnd, Ev_bnd }, 0 },
3887 { "nopQ", { Ev }, PREFIX_OPCODE },
3888 { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3889 { "nopQ", { Ev }, PREFIX_OPCODE },
3890 { "nopQ", { Ev }, PREFIX_OPCODE },
3895 { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3896 { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3897 { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3898 { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3903 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3904 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3905 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3906 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3911 { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3912 { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE },
3913 { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3914 { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3919 { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3920 { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE },
3921 { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3922 { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE },
3927 { "ucomiss",{ XM, EXd }, 0 },
3929 { "ucomisd",{ XM, EXq }, 0 },
3934 { "comiss", { XM, EXd }, 0 },
3936 { "comisd", { XM, EXq }, 0 },
3941 { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3942 { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3943 { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3944 { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3949 { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3950 { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3955 { "rcpps", { XM, EXx }, PREFIX_OPCODE },
3956 { "rcpss", { XM, EXd }, PREFIX_OPCODE },
3961 { "addps", { XM, EXx }, PREFIX_OPCODE },
3962 { "addss", { XM, EXd }, PREFIX_OPCODE },
3963 { "addpd", { XM, EXx }, PREFIX_OPCODE },
3964 { "addsd", { XM, EXq }, PREFIX_OPCODE },
3969 { "mulps", { XM, EXx }, PREFIX_OPCODE },
3970 { "mulss", { XM, EXd }, PREFIX_OPCODE },
3971 { "mulpd", { XM, EXx }, PREFIX_OPCODE },
3972 { "mulsd", { XM, EXq }, PREFIX_OPCODE },
3977 { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3978 { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3979 { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3980 { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3985 { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3986 { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3987 { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3992 { "subps", { XM, EXx }, PREFIX_OPCODE },
3993 { "subss", { XM, EXd }, PREFIX_OPCODE },
3994 { "subpd", { XM, EXx }, PREFIX_OPCODE },
3995 { "subsd", { XM, EXq }, PREFIX_OPCODE },
4000 { "minps", { XM, EXx }, PREFIX_OPCODE },
4001 { "minss", { XM, EXd }, PREFIX_OPCODE },
4002 { "minpd", { XM, EXx }, PREFIX_OPCODE },
4003 { "minsd", { XM, EXq }, PREFIX_OPCODE },
4008 { "divps", { XM, EXx }, PREFIX_OPCODE },
4009 { "divss", { XM, EXd }, PREFIX_OPCODE },
4010 { "divpd", { XM, EXx }, PREFIX_OPCODE },
4011 { "divsd", { XM, EXq }, PREFIX_OPCODE },
4016 { "maxps", { XM, EXx }, PREFIX_OPCODE },
4017 { "maxss", { XM, EXd }, PREFIX_OPCODE },
4018 { "maxpd", { XM, EXx }, PREFIX_OPCODE },
4019 { "maxsd", { XM, EXq }, PREFIX_OPCODE },
4024 { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
4026 { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
4031 { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
4033 { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
4038 { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
4040 { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
4047 { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
4054 { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
4059 { "movq", { MX, EM }, PREFIX_OPCODE },
4060 { "movdqu", { XM, EXx }, PREFIX_OPCODE },
4061 { "movdqa", { XM, EXx }, PREFIX_OPCODE },
4066 { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
4067 { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4068 { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
4069 { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4072 /* PREFIX_0F73_REG_3 */
4076 { "psrldq", { XS, Ib }, 0 },
4079 /* PREFIX_0F73_REG_7 */
4083 { "pslldq", { XS, Ib }, 0 },
4088 {"vmread", { Em, Gm }, 0 },
4090 {"extrq", { XS, Ib, Ib }, 0 },
4091 {"insertq", { XM, XS, Ib, Ib }, 0 },
4096 {"vmwrite", { Gm, Em }, 0 },
4098 {"extrq", { XM, XS }, 0 },
4099 {"insertq", { XM, XS }, 0 },
4106 { "haddpd", { XM, EXx }, PREFIX_OPCODE },
4107 { "haddps", { XM, EXx }, PREFIX_OPCODE },
4114 { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
4115 { "hsubps", { XM, EXx }, PREFIX_OPCODE },
4120 { "movK", { Edq, MX }, PREFIX_OPCODE },
4121 { "movq", { XM, EXq }, PREFIX_OPCODE },
4122 { "movK", { Edq, XM }, PREFIX_OPCODE },
4127 { "movq", { EMS, MX }, PREFIX_OPCODE },
4128 { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
4129 { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
4132 /* PREFIX_0FAE_REG_0 */
4135 { "rdfsbase", { Ev }, 0 },
4138 /* PREFIX_0FAE_REG_1 */
4141 { "rdgsbase", { Ev }, 0 },
4144 /* PREFIX_0FAE_REG_2 */
4147 { "wrfsbase", { Ev }, 0 },
4150 /* PREFIX_0FAE_REG_3 */
4153 { "wrgsbase", { Ev }, 0 },
4156 /* PREFIX_MOD_0_0FAE_REG_4 */
4158 { "xsave", { FXSAVE }, 0 },
4159 { "ptwrite%LQ", { Edq }, 0 },
4162 /* PREFIX_MOD_3_0FAE_REG_4 */
4165 { "ptwrite%LQ", { Edq }, 0 },
4168 /* PREFIX_MOD_0_0FAE_REG_5 */
4170 { "xrstor", { FXSAVE }, PREFIX_OPCODE },
4173 /* PREFIX_MOD_3_0FAE_REG_5 */
4175 { "lfence", { Skip_MODRM }, 0 },
4176 { "incsspK", { Rdq }, PREFIX_OPCODE },
4179 /* PREFIX_0FAE_REG_6 */
4181 { "xsaveopt", { FXSAVE }, PREFIX_OPCODE },
4182 { "clrssbsy", { Mq }, PREFIX_OPCODE },
4183 { "clwb", { Mb }, PREFIX_OPCODE },
4186 /* PREFIX_0FAE_REG_7 */
4188 { "clflush", { Mb }, 0 },
4190 { "clflushopt", { Mb }, 0 },
4196 { "popcntS", { Gv, Ev }, 0 },
4201 { "bsfS", { Gv, Ev }, 0 },
4202 { "tzcntS", { Gv, Ev }, 0 },
4203 { "bsfS", { Gv, Ev }, 0 },
4208 { "bsrS", { Gv, Ev }, 0 },
4209 { "lzcntS", { Gv, Ev }, 0 },
4210 { "bsrS", { Gv, Ev }, 0 },
4215 { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE },
4216 { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE },
4217 { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE },
4218 { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE },
4221 /* PREFIX_MOD_0_0FC3 */
4223 { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4226 /* PREFIX_MOD_0_0FC7_REG_6 */
4228 { "vmptrld",{ Mq }, 0 },
4229 { "vmxon", { Mq }, 0 },
4230 { "vmclear",{ Mq }, 0 },
4233 /* PREFIX_MOD_3_0FC7_REG_6 */
4235 { "rdrand", { Ev }, 0 },
4237 { "rdrand", { Ev }, 0 }
4240 /* PREFIX_MOD_3_0FC7_REG_7 */
4242 { "rdseed", { Ev }, 0 },
4243 { "rdpid", { Em }, 0 },
4244 { "rdseed", { Ev }, 0 },
4251 { "addsubpd", { XM, EXx }, 0 },
4252 { "addsubps", { XM, EXx }, 0 },
4258 { "movq2dq",{ XM, MS }, 0 },
4259 { "movq", { EXqS, XM }, 0 },
4260 { "movdq2q",{ MX, XS }, 0 },
4266 { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4267 { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4268 { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4273 { "movntq", { Mq, MX }, PREFIX_OPCODE },
4275 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4283 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4288 { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4290 { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4297 { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4304 { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4311 { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4318 { "ptest", { XM, EXx }, PREFIX_OPCODE },
4325 { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4332 { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4339 { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4346 { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4353 { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4360 { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4367 { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4374 { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4381 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4388 { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4395 { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4402 { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4409 { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4416 { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4423 { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4430 { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4437 { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4444 { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4451 { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4458 { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4465 { "pminud", { XM, EXx }, PREFIX_OPCODE },
4472 { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4479 { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4486 { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4493 { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4500 { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4507 { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4514 { "invept", { Gm, Mo }, PREFIX_OPCODE },
4521 { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4528 { "invpcid", { Gm, M }, PREFIX_OPCODE },
4533 { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4538 { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4543 { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4548 { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4553 { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4558 { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4565 { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4572 { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4579 { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4586 { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4593 { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4600 { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4605 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4607 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4608 { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4613 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4615 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4616 { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4623 { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4628 { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4629 { "adoxS", { Gdq, Edq}, PREFIX_OPCODE },
4630 { "adcxS", { Gdq, Edq}, PREFIX_OPCODE },
4638 { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4645 { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4652 { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4659 { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4666 { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4673 { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4680 { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4687 { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4694 { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4701 { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4708 { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4715 { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4722 { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4729 { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4736 { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE },
4743 { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE },
4750 { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4757 { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4764 { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4771 { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4778 { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4785 { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4790 { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4797 { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4804 { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4811 { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4814 /* PREFIX_VEX_0F10 */
4816 { VEX_W_TABLE (VEX_W_0F10_P_0) },
4817 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4818 { VEX_W_TABLE (VEX_W_0F10_P_2) },
4819 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4822 /* PREFIX_VEX_0F11 */
4824 { VEX_W_TABLE (VEX_W_0F11_P_0) },
4825 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4826 { VEX_W_TABLE (VEX_W_0F11_P_2) },
4827 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4830 /* PREFIX_VEX_0F12 */
4832 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4833 { VEX_W_TABLE (VEX_W_0F12_P_1) },
4834 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4835 { VEX_W_TABLE (VEX_W_0F12_P_3) },
4838 /* PREFIX_VEX_0F16 */
4840 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4841 { VEX_W_TABLE (VEX_W_0F16_P_1) },
4842 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4845 /* PREFIX_VEX_0F2A */
4848 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4850 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4853 /* PREFIX_VEX_0F2C */
4856 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4858 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4861 /* PREFIX_VEX_0F2D */
4864 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4866 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4869 /* PREFIX_VEX_0F2E */
4871 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4873 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4876 /* PREFIX_VEX_0F2F */
4878 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4880 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4883 /* PREFIX_VEX_0F41 */
4885 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4887 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4890 /* PREFIX_VEX_0F42 */
4892 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4894 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4897 /* PREFIX_VEX_0F44 */
4899 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4901 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4904 /* PREFIX_VEX_0F45 */
4906 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4908 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4911 /* PREFIX_VEX_0F46 */
4913 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4915 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4918 /* PREFIX_VEX_0F47 */
4920 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4922 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4925 /* PREFIX_VEX_0F4A */
4927 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4929 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4932 /* PREFIX_VEX_0F4B */
4934 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4936 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4939 /* PREFIX_VEX_0F51 */
4941 { VEX_W_TABLE (VEX_W_0F51_P_0) },
4942 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
4943 { VEX_W_TABLE (VEX_W_0F51_P_2) },
4944 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
4947 /* PREFIX_VEX_0F52 */
4949 { VEX_W_TABLE (VEX_W_0F52_P_0) },
4950 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
4953 /* PREFIX_VEX_0F53 */
4955 { VEX_W_TABLE (VEX_W_0F53_P_0) },
4956 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
4959 /* PREFIX_VEX_0F58 */
4961 { VEX_W_TABLE (VEX_W_0F58_P_0) },
4962 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
4963 { VEX_W_TABLE (VEX_W_0F58_P_2) },
4964 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
4967 /* PREFIX_VEX_0F59 */
4969 { VEX_W_TABLE (VEX_W_0F59_P_0) },
4970 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
4971 { VEX_W_TABLE (VEX_W_0F59_P_2) },
4972 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
4975 /* PREFIX_VEX_0F5A */
4977 { VEX_W_TABLE (VEX_W_0F5A_P_0) },
4978 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
4979 { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
4980 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
4983 /* PREFIX_VEX_0F5B */
4985 { VEX_W_TABLE (VEX_W_0F5B_P_0) },
4986 { VEX_W_TABLE (VEX_W_0F5B_P_1) },
4987 { VEX_W_TABLE (VEX_W_0F5B_P_2) },
4990 /* PREFIX_VEX_0F5C */
4992 { VEX_W_TABLE (VEX_W_0F5C_P_0) },
4993 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
4994 { VEX_W_TABLE (VEX_W_0F5C_P_2) },
4995 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
4998 /* PREFIX_VEX_0F5D */
5000 { VEX_W_TABLE (VEX_W_0F5D_P_0) },
5001 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
5002 { VEX_W_TABLE (VEX_W_0F5D_P_2) },
5003 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
5006 /* PREFIX_VEX_0F5E */
5008 { VEX_W_TABLE (VEX_W_0F5E_P_0) },
5009 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
5010 { VEX_W_TABLE (VEX_W_0F5E_P_2) },
5011 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
5014 /* PREFIX_VEX_0F5F */
5016 { VEX_W_TABLE (VEX_W_0F5F_P_0) },
5017 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
5018 { VEX_W_TABLE (VEX_W_0F5F_P_2) },
5019 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
5022 /* PREFIX_VEX_0F60 */
5026 { VEX_W_TABLE (VEX_W_0F60_P_2) },
5029 /* PREFIX_VEX_0F61 */
5033 { VEX_W_TABLE (VEX_W_0F61_P_2) },
5036 /* PREFIX_VEX_0F62 */
5040 { VEX_W_TABLE (VEX_W_0F62_P_2) },
5043 /* PREFIX_VEX_0F63 */
5047 { VEX_W_TABLE (VEX_W_0F63_P_2) },
5050 /* PREFIX_VEX_0F64 */
5054 { VEX_W_TABLE (VEX_W_0F64_P_2) },
5057 /* PREFIX_VEX_0F65 */
5061 { VEX_W_TABLE (VEX_W_0F65_P_2) },
5064 /* PREFIX_VEX_0F66 */
5068 { VEX_W_TABLE (VEX_W_0F66_P_2) },
5071 /* PREFIX_VEX_0F67 */
5075 { VEX_W_TABLE (VEX_W_0F67_P_2) },
5078 /* PREFIX_VEX_0F68 */
5082 { VEX_W_TABLE (VEX_W_0F68_P_2) },
5085 /* PREFIX_VEX_0F69 */
5089 { VEX_W_TABLE (VEX_W_0F69_P_2) },
5092 /* PREFIX_VEX_0F6A */
5096 { VEX_W_TABLE (VEX_W_0F6A_P_2) },
5099 /* PREFIX_VEX_0F6B */
5103 { VEX_W_TABLE (VEX_W_0F6B_P_2) },
5106 /* PREFIX_VEX_0F6C */
5110 { VEX_W_TABLE (VEX_W_0F6C_P_2) },
5113 /* PREFIX_VEX_0F6D */
5117 { VEX_W_TABLE (VEX_W_0F6D_P_2) },
5120 /* PREFIX_VEX_0F6E */
5124 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
5127 /* PREFIX_VEX_0F6F */
5130 { VEX_W_TABLE (VEX_W_0F6F_P_1) },
5131 { VEX_W_TABLE (VEX_W_0F6F_P_2) },
5134 /* PREFIX_VEX_0F70 */
5137 { VEX_W_TABLE (VEX_W_0F70_P_1) },
5138 { VEX_W_TABLE (VEX_W_0F70_P_2) },
5139 { VEX_W_TABLE (VEX_W_0F70_P_3) },
5142 /* PREFIX_VEX_0F71_REG_2 */
5146 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
5149 /* PREFIX_VEX_0F71_REG_4 */
5153 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
5156 /* PREFIX_VEX_0F71_REG_6 */
5160 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
5163 /* PREFIX_VEX_0F72_REG_2 */
5167 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
5170 /* PREFIX_VEX_0F72_REG_4 */
5174 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
5177 /* PREFIX_VEX_0F72_REG_6 */
5181 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
5184 /* PREFIX_VEX_0F73_REG_2 */
5188 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
5191 /* PREFIX_VEX_0F73_REG_3 */
5195 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
5198 /* PREFIX_VEX_0F73_REG_6 */
5202 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
5205 /* PREFIX_VEX_0F73_REG_7 */
5209 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5212 /* PREFIX_VEX_0F74 */
5216 { VEX_W_TABLE (VEX_W_0F74_P_2) },
5219 /* PREFIX_VEX_0F75 */
5223 { VEX_W_TABLE (VEX_W_0F75_P_2) },
5226 /* PREFIX_VEX_0F76 */
5230 { VEX_W_TABLE (VEX_W_0F76_P_2) },
5233 /* PREFIX_VEX_0F77 */
5235 { VEX_W_TABLE (VEX_W_0F77_P_0) },
5238 /* PREFIX_VEX_0F7C */
5242 { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5243 { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5246 /* PREFIX_VEX_0F7D */
5250 { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5251 { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5254 /* PREFIX_VEX_0F7E */
5257 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5258 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5261 /* PREFIX_VEX_0F7F */
5264 { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5265 { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5268 /* PREFIX_VEX_0F90 */
5270 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5272 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5275 /* PREFIX_VEX_0F91 */
5277 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5279 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5282 /* PREFIX_VEX_0F92 */
5284 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5286 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5287 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5290 /* PREFIX_VEX_0F93 */
5292 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5294 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5295 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5298 /* PREFIX_VEX_0F98 */
5300 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5302 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5305 /* PREFIX_VEX_0F99 */
5307 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5309 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5312 /* PREFIX_VEX_0FC2 */
5314 { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5315 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5316 { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5317 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5320 /* PREFIX_VEX_0FC4 */
5324 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5327 /* PREFIX_VEX_0FC5 */
5331 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5334 /* PREFIX_VEX_0FD0 */
5338 { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5339 { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5342 /* PREFIX_VEX_0FD1 */
5346 { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5349 /* PREFIX_VEX_0FD2 */
5353 { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5356 /* PREFIX_VEX_0FD3 */
5360 { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5363 /* PREFIX_VEX_0FD4 */
5367 { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5370 /* PREFIX_VEX_0FD5 */
5374 { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5377 /* PREFIX_VEX_0FD6 */
5381 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5384 /* PREFIX_VEX_0FD7 */
5388 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5391 /* PREFIX_VEX_0FD8 */
5395 { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5398 /* PREFIX_VEX_0FD9 */
5402 { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5405 /* PREFIX_VEX_0FDA */
5409 { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5412 /* PREFIX_VEX_0FDB */
5416 { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5419 /* PREFIX_VEX_0FDC */
5423 { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5426 /* PREFIX_VEX_0FDD */
5430 { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5433 /* PREFIX_VEX_0FDE */
5437 { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5440 /* PREFIX_VEX_0FDF */
5444 { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5447 /* PREFIX_VEX_0FE0 */
5451 { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5454 /* PREFIX_VEX_0FE1 */
5458 { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5461 /* PREFIX_VEX_0FE2 */
5465 { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5468 /* PREFIX_VEX_0FE3 */
5472 { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5475 /* PREFIX_VEX_0FE4 */
5479 { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5482 /* PREFIX_VEX_0FE5 */
5486 { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5489 /* PREFIX_VEX_0FE6 */
5492 { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5493 { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5494 { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5497 /* PREFIX_VEX_0FE7 */
5501 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5504 /* PREFIX_VEX_0FE8 */
5508 { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5511 /* PREFIX_VEX_0FE9 */
5515 { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5518 /* PREFIX_VEX_0FEA */
5522 { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5525 /* PREFIX_VEX_0FEB */
5529 { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5532 /* PREFIX_VEX_0FEC */
5536 { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5539 /* PREFIX_VEX_0FED */
5543 { VEX_W_TABLE (VEX_W_0FED_P_2) },
5546 /* PREFIX_VEX_0FEE */
5550 { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5553 /* PREFIX_VEX_0FEF */
5557 { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5560 /* PREFIX_VEX_0FF0 */
5565 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5568 /* PREFIX_VEX_0FF1 */
5572 { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5575 /* PREFIX_VEX_0FF2 */
5579 { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5582 /* PREFIX_VEX_0FF3 */
5586 { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5589 /* PREFIX_VEX_0FF4 */
5593 { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5596 /* PREFIX_VEX_0FF5 */
5600 { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5603 /* PREFIX_VEX_0FF6 */
5607 { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5610 /* PREFIX_VEX_0FF7 */
5614 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5617 /* PREFIX_VEX_0FF8 */
5621 { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5624 /* PREFIX_VEX_0FF9 */
5628 { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5631 /* PREFIX_VEX_0FFA */
5635 { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5638 /* PREFIX_VEX_0FFB */
5642 { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5645 /* PREFIX_VEX_0FFC */
5649 { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5652 /* PREFIX_VEX_0FFD */
5656 { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5659 /* PREFIX_VEX_0FFE */
5663 { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5666 /* PREFIX_VEX_0F3800 */
5670 { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5673 /* PREFIX_VEX_0F3801 */
5677 { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5680 /* PREFIX_VEX_0F3802 */
5684 { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5687 /* PREFIX_VEX_0F3803 */
5691 { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5694 /* PREFIX_VEX_0F3804 */
5698 { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5701 /* PREFIX_VEX_0F3805 */
5705 { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5708 /* PREFIX_VEX_0F3806 */
5712 { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5715 /* PREFIX_VEX_0F3807 */
5719 { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5722 /* PREFIX_VEX_0F3808 */
5726 { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5729 /* PREFIX_VEX_0F3809 */
5733 { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5736 /* PREFIX_VEX_0F380A */
5740 { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5743 /* PREFIX_VEX_0F380B */
5747 { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5750 /* PREFIX_VEX_0F380C */
5754 { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5757 /* PREFIX_VEX_0F380D */
5761 { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5764 /* PREFIX_VEX_0F380E */
5768 { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5771 /* PREFIX_VEX_0F380F */
5775 { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5778 /* PREFIX_VEX_0F3813 */
5782 { "vcvtph2ps", { XM, EXxmmq }, 0 },
5785 /* PREFIX_VEX_0F3816 */
5789 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5792 /* PREFIX_VEX_0F3817 */
5796 { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5799 /* PREFIX_VEX_0F3818 */
5803 { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5806 /* PREFIX_VEX_0F3819 */
5810 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5813 /* PREFIX_VEX_0F381A */
5817 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5820 /* PREFIX_VEX_0F381C */
5824 { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5827 /* PREFIX_VEX_0F381D */
5831 { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5834 /* PREFIX_VEX_0F381E */
5838 { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5841 /* PREFIX_VEX_0F3820 */
5845 { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5848 /* PREFIX_VEX_0F3821 */
5852 { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5855 /* PREFIX_VEX_0F3822 */
5859 { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5862 /* PREFIX_VEX_0F3823 */
5866 { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5869 /* PREFIX_VEX_0F3824 */
5873 { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5876 /* PREFIX_VEX_0F3825 */
5880 { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5883 /* PREFIX_VEX_0F3828 */
5887 { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5890 /* PREFIX_VEX_0F3829 */
5894 { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5897 /* PREFIX_VEX_0F382A */
5901 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5904 /* PREFIX_VEX_0F382B */
5908 { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5911 /* PREFIX_VEX_0F382C */
5915 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5918 /* PREFIX_VEX_0F382D */
5922 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5925 /* PREFIX_VEX_0F382E */
5929 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5932 /* PREFIX_VEX_0F382F */
5936 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5939 /* PREFIX_VEX_0F3830 */
5943 { VEX_W_TABLE (VEX_W_0F3830_P_2) },
5946 /* PREFIX_VEX_0F3831 */
5950 { VEX_W_TABLE (VEX_W_0F3831_P_2) },
5953 /* PREFIX_VEX_0F3832 */
5957 { VEX_W_TABLE (VEX_W_0F3832_P_2) },
5960 /* PREFIX_VEX_0F3833 */
5964 { VEX_W_TABLE (VEX_W_0F3833_P_2) },
5967 /* PREFIX_VEX_0F3834 */
5971 { VEX_W_TABLE (VEX_W_0F3834_P_2) },
5974 /* PREFIX_VEX_0F3835 */
5978 { VEX_W_TABLE (VEX_W_0F3835_P_2) },
5981 /* PREFIX_VEX_0F3836 */
5985 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5988 /* PREFIX_VEX_0F3837 */
5992 { VEX_W_TABLE (VEX_W_0F3837_P_2) },
5995 /* PREFIX_VEX_0F3838 */
5999 { VEX_W_TABLE (VEX_W_0F3838_P_2) },
6002 /* PREFIX_VEX_0F3839 */
6006 { VEX_W_TABLE (VEX_W_0F3839_P_2) },
6009 /* PREFIX_VEX_0F383A */
6013 { VEX_W_TABLE (VEX_W_0F383A_P_2) },
6016 /* PREFIX_VEX_0F383B */
6020 { VEX_W_TABLE (VEX_W_0F383B_P_2) },
6023 /* PREFIX_VEX_0F383C */
6027 { VEX_W_TABLE (VEX_W_0F383C_P_2) },
6030 /* PREFIX_VEX_0F383D */
6034 { VEX_W_TABLE (VEX_W_0F383D_P_2) },
6037 /* PREFIX_VEX_0F383E */
6041 { VEX_W_TABLE (VEX_W_0F383E_P_2) },
6044 /* PREFIX_VEX_0F383F */
6048 { VEX_W_TABLE (VEX_W_0F383F_P_2) },
6051 /* PREFIX_VEX_0F3840 */
6055 { VEX_W_TABLE (VEX_W_0F3840_P_2) },
6058 /* PREFIX_VEX_0F3841 */
6062 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
6065 /* PREFIX_VEX_0F3845 */
6069 { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
6072 /* PREFIX_VEX_0F3846 */
6076 { VEX_W_TABLE (VEX_W_0F3846_P_2) },
6079 /* PREFIX_VEX_0F3847 */
6083 { "vpsllv%LW", { XM, Vex, EXx }, 0 },
6086 /* PREFIX_VEX_0F3858 */
6090 { VEX_W_TABLE (VEX_W_0F3858_P_2) },
6093 /* PREFIX_VEX_0F3859 */
6097 { VEX_W_TABLE (VEX_W_0F3859_P_2) },
6100 /* PREFIX_VEX_0F385A */
6104 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
6107 /* PREFIX_VEX_0F3878 */
6111 { VEX_W_TABLE (VEX_W_0F3878_P_2) },
6114 /* PREFIX_VEX_0F3879 */
6118 { VEX_W_TABLE (VEX_W_0F3879_P_2) },
6121 /* PREFIX_VEX_0F388C */
6125 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
6128 /* PREFIX_VEX_0F388E */
6132 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
6135 /* PREFIX_VEX_0F3890 */
6139 { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
6142 /* PREFIX_VEX_0F3891 */
6146 { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6149 /* PREFIX_VEX_0F3892 */
6153 { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6156 /* PREFIX_VEX_0F3893 */
6160 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6163 /* PREFIX_VEX_0F3896 */
6167 { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6170 /* PREFIX_VEX_0F3897 */
6174 { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6177 /* PREFIX_VEX_0F3898 */
6181 { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6184 /* PREFIX_VEX_0F3899 */
6188 { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6191 /* PREFIX_VEX_0F389A */
6195 { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6198 /* PREFIX_VEX_0F389B */
6202 { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6205 /* PREFIX_VEX_0F389C */
6209 { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6212 /* PREFIX_VEX_0F389D */
6216 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6219 /* PREFIX_VEX_0F389E */
6223 { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6226 /* PREFIX_VEX_0F389F */
6230 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6233 /* PREFIX_VEX_0F38A6 */
6237 { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6241 /* PREFIX_VEX_0F38A7 */
6245 { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6248 /* PREFIX_VEX_0F38A8 */
6252 { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6255 /* PREFIX_VEX_0F38A9 */
6259 { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6262 /* PREFIX_VEX_0F38AA */
6266 { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6269 /* PREFIX_VEX_0F38AB */
6273 { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6276 /* PREFIX_VEX_0F38AC */
6280 { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6283 /* PREFIX_VEX_0F38AD */
6287 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6290 /* PREFIX_VEX_0F38AE */
6294 { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6297 /* PREFIX_VEX_0F38AF */
6301 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6304 /* PREFIX_VEX_0F38B6 */
6308 { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6311 /* PREFIX_VEX_0F38B7 */
6315 { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6318 /* PREFIX_VEX_0F38B8 */
6322 { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6325 /* PREFIX_VEX_0F38B9 */
6329 { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6332 /* PREFIX_VEX_0F38BA */
6336 { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6339 /* PREFIX_VEX_0F38BB */
6343 { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6346 /* PREFIX_VEX_0F38BC */
6350 { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6353 /* PREFIX_VEX_0F38BD */
6357 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6360 /* PREFIX_VEX_0F38BE */
6364 { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6367 /* PREFIX_VEX_0F38BF */
6371 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6374 /* PREFIX_VEX_0F38CF */
6378 { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6381 /* PREFIX_VEX_0F38DB */
6385 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6388 /* PREFIX_VEX_0F38DC */
6392 { "vaesenc", { XM, Vex, EXx }, 0 },
6395 /* PREFIX_VEX_0F38DD */
6399 { "vaesenclast", { XM, Vex, EXx }, 0 },
6402 /* PREFIX_VEX_0F38DE */
6406 { "vaesdec", { XM, Vex, EXx }, 0 },
6409 /* PREFIX_VEX_0F38DF */
6413 { "vaesdeclast", { XM, Vex, EXx }, 0 },
6416 /* PREFIX_VEX_0F38F2 */
6418 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6421 /* PREFIX_VEX_0F38F3_REG_1 */
6423 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6426 /* PREFIX_VEX_0F38F3_REG_2 */
6428 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6431 /* PREFIX_VEX_0F38F3_REG_3 */
6433 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6436 /* PREFIX_VEX_0F38F5 */
6438 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6439 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6441 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6444 /* PREFIX_VEX_0F38F6 */
6449 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6452 /* PREFIX_VEX_0F38F7 */
6454 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6455 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6456 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6457 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6460 /* PREFIX_VEX_0F3A00 */
6464 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6467 /* PREFIX_VEX_0F3A01 */
6471 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6474 /* PREFIX_VEX_0F3A02 */
6478 { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6481 /* PREFIX_VEX_0F3A04 */
6485 { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6488 /* PREFIX_VEX_0F3A05 */
6492 { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6495 /* PREFIX_VEX_0F3A06 */
6499 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6502 /* PREFIX_VEX_0F3A08 */
6506 { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6509 /* PREFIX_VEX_0F3A09 */
6513 { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6516 /* PREFIX_VEX_0F3A0A */
6520 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6523 /* PREFIX_VEX_0F3A0B */
6527 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6530 /* PREFIX_VEX_0F3A0C */
6534 { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6537 /* PREFIX_VEX_0F3A0D */
6541 { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6544 /* PREFIX_VEX_0F3A0E */
6548 { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6551 /* PREFIX_VEX_0F3A0F */
6555 { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6558 /* PREFIX_VEX_0F3A14 */
6562 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6565 /* PREFIX_VEX_0F3A15 */
6569 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6572 /* PREFIX_VEX_0F3A16 */
6576 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6579 /* PREFIX_VEX_0F3A17 */
6583 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6586 /* PREFIX_VEX_0F3A18 */
6590 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6593 /* PREFIX_VEX_0F3A19 */
6597 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6600 /* PREFIX_VEX_0F3A1D */
6604 { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6607 /* PREFIX_VEX_0F3A20 */
6611 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6614 /* PREFIX_VEX_0F3A21 */
6618 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6621 /* PREFIX_VEX_0F3A22 */
6625 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6628 /* PREFIX_VEX_0F3A30 */
6632 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6635 /* PREFIX_VEX_0F3A31 */
6639 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6642 /* PREFIX_VEX_0F3A32 */
6646 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6649 /* PREFIX_VEX_0F3A33 */
6653 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6656 /* PREFIX_VEX_0F3A38 */
6660 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6663 /* PREFIX_VEX_0F3A39 */
6667 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6670 /* PREFIX_VEX_0F3A40 */
6674 { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6677 /* PREFIX_VEX_0F3A41 */
6681 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6684 /* PREFIX_VEX_0F3A42 */
6688 { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6691 /* PREFIX_VEX_0F3A44 */
6695 { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, 0 },
6698 /* PREFIX_VEX_0F3A46 */
6702 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6705 /* PREFIX_VEX_0F3A48 */
6709 { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6712 /* PREFIX_VEX_0F3A49 */
6716 { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6719 /* PREFIX_VEX_0F3A4A */
6723 { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6726 /* PREFIX_VEX_0F3A4B */
6730 { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6733 /* PREFIX_VEX_0F3A4C */
6737 { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6740 /* PREFIX_VEX_0F3A5C */
6744 { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6747 /* PREFIX_VEX_0F3A5D */
6751 { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6754 /* PREFIX_VEX_0F3A5E */
6758 { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6761 /* PREFIX_VEX_0F3A5F */
6765 { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6768 /* PREFIX_VEX_0F3A60 */
6772 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6776 /* PREFIX_VEX_0F3A61 */
6780 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6783 /* PREFIX_VEX_0F3A62 */
6787 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6790 /* PREFIX_VEX_0F3A63 */
6794 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6797 /* PREFIX_VEX_0F3A68 */
6801 { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6804 /* PREFIX_VEX_0F3A69 */
6808 { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6811 /* PREFIX_VEX_0F3A6A */
6815 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6818 /* PREFIX_VEX_0F3A6B */
6822 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6825 /* PREFIX_VEX_0F3A6C */
6829 { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6832 /* PREFIX_VEX_0F3A6D */
6836 { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6839 /* PREFIX_VEX_0F3A6E */
6843 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6846 /* PREFIX_VEX_0F3A6F */
6850 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6853 /* PREFIX_VEX_0F3A78 */
6857 { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6860 /* PREFIX_VEX_0F3A79 */
6864 { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6867 /* PREFIX_VEX_0F3A7A */
6871 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6874 /* PREFIX_VEX_0F3A7B */
6878 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6881 /* PREFIX_VEX_0F3A7C */
6885 { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6889 /* PREFIX_VEX_0F3A7D */
6893 { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
6896 /* PREFIX_VEX_0F3A7E */
6900 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6903 /* PREFIX_VEX_0F3A7F */
6907 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6910 /* PREFIX_VEX_0F3ACE */
6914 { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6917 /* PREFIX_VEX_0F3ACF */
6921 { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6924 /* PREFIX_VEX_0F3ADF */
6928 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6931 /* PREFIX_VEX_0F3AF0 */
6936 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6939 #define NEED_PREFIX_TABLE
6940 #include "i386-dis-evex.h"
6941 #undef NEED_PREFIX_TABLE
6944 static const struct dis386 x86_64_table[][2] = {
6947 { "pushP", { es }, 0 },
6952 { "popP", { es }, 0 },
6957 { "pushP", { cs }, 0 },
6962 { "pushP", { ss }, 0 },
6967 { "popP", { ss }, 0 },
6972 { "pushP", { ds }, 0 },
6977 { "popP", { ds }, 0 },
6982 { "daa", { XX }, 0 },
6987 { "das", { XX }, 0 },
6992 { "aaa", { XX }, 0 },
6997 { "aas", { XX }, 0 },
7002 { "pushaP", { XX }, 0 },
7007 { "popaP", { XX }, 0 },
7012 { MOD_TABLE (MOD_62_32BIT) },
7013 { EVEX_TABLE (EVEX_0F) },
7018 { "arpl", { Ew, Gw }, 0 },
7019 { "movs{lq|xd}", { Gv, Ed }, 0 },
7024 { "ins{R|}", { Yzr, indirDX }, 0 },
7025 { "ins{G|}", { Yzr, indirDX }, 0 },
7030 { "outs{R|}", { indirDXr, Xz }, 0 },
7031 { "outs{G|}", { indirDXr, Xz }, 0 },
7036 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
7037 { REG_TABLE (REG_80) },
7042 { "Jcall{T|}", { Ap }, 0 },
7047 { MOD_TABLE (MOD_C4_32BIT) },
7048 { VEX_C4_TABLE (VEX_0F) },
7053 { MOD_TABLE (MOD_C5_32BIT) },
7054 { VEX_C5_TABLE (VEX_0F) },
7059 { "into", { XX }, 0 },
7064 { "aam", { Ib }, 0 },
7069 { "aad", { Ib }, 0 },
7074 { "callP", { Jv, BND }, 0 },
7075 { "call@", { Jv, BND }, 0 }
7080 { "jmpP", { Jv, BND }, 0 },
7081 { "jmp@", { Jv, BND }, 0 }
7086 { "Jjmp{T|}", { Ap }, 0 },
7089 /* X86_64_0F01_REG_0 */
7091 { "sgdt{Q|IQ}", { M }, 0 },
7092 { "sgdt", { M }, 0 },
7095 /* X86_64_0F01_REG_1 */
7097 { "sidt{Q|IQ}", { M }, 0 },
7098 { "sidt", { M }, 0 },
7101 /* X86_64_0F01_REG_2 */
7103 { "lgdt{Q|Q}", { M }, 0 },
7104 { "lgdt", { M }, 0 },
7107 /* X86_64_0F01_REG_3 */
7109 { "lidt{Q|Q}", { M }, 0 },
7110 { "lidt", { M }, 0 },
7114 static const struct dis386 three_byte_table[][256] = {
7116 /* THREE_BYTE_0F38 */
7119 { "pshufb", { MX, EM }, PREFIX_OPCODE },
7120 { "phaddw", { MX, EM }, PREFIX_OPCODE },
7121 { "phaddd", { MX, EM }, PREFIX_OPCODE },
7122 { "phaddsw", { MX, EM }, PREFIX_OPCODE },
7123 { "pmaddubsw", { MX, EM }, PREFIX_OPCODE },
7124 { "phsubw", { MX, EM }, PREFIX_OPCODE },
7125 { "phsubd", { MX, EM }, PREFIX_OPCODE },
7126 { "phsubsw", { MX, EM }, PREFIX_OPCODE },
7128 { "psignb", { MX, EM }, PREFIX_OPCODE },
7129 { "psignw", { MX, EM }, PREFIX_OPCODE },
7130 { "psignd", { MX, EM }, PREFIX_OPCODE },
7131 { "pmulhrsw", { MX, EM }, PREFIX_OPCODE },
7137 { PREFIX_TABLE (PREFIX_0F3810) },
7141 { PREFIX_TABLE (PREFIX_0F3814) },
7142 { PREFIX_TABLE (PREFIX_0F3815) },
7144 { PREFIX_TABLE (PREFIX_0F3817) },
7150 { "pabsb", { MX, EM }, PREFIX_OPCODE },
7151 { "pabsw", { MX, EM }, PREFIX_OPCODE },
7152 { "pabsd", { MX, EM }, PREFIX_OPCODE },
7155 { PREFIX_TABLE (PREFIX_0F3820) },
7156 { PREFIX_TABLE (PREFIX_0F3821) },
7157 { PREFIX_TABLE (PREFIX_0F3822) },
7158 { PREFIX_TABLE (PREFIX_0F3823) },
7159 { PREFIX_TABLE (PREFIX_0F3824) },
7160 { PREFIX_TABLE (PREFIX_0F3825) },
7164 { PREFIX_TABLE (PREFIX_0F3828) },
7165 { PREFIX_TABLE (PREFIX_0F3829) },
7166 { PREFIX_TABLE (PREFIX_0F382A) },
7167 { PREFIX_TABLE (PREFIX_0F382B) },
7173 { PREFIX_TABLE (PREFIX_0F3830) },
7174 { PREFIX_TABLE (PREFIX_0F3831) },
7175 { PREFIX_TABLE (PREFIX_0F3832) },
7176 { PREFIX_TABLE (PREFIX_0F3833) },
7177 { PREFIX_TABLE (PREFIX_0F3834) },
7178 { PREFIX_TABLE (PREFIX_0F3835) },
7180 { PREFIX_TABLE (PREFIX_0F3837) },
7182 { PREFIX_TABLE (PREFIX_0F3838) },
7183 { PREFIX_TABLE (PREFIX_0F3839) },
7184 { PREFIX_TABLE (PREFIX_0F383A) },
7185 { PREFIX_TABLE (PREFIX_0F383B) },
7186 { PREFIX_TABLE (PREFIX_0F383C) },
7187 { PREFIX_TABLE (PREFIX_0F383D) },
7188 { PREFIX_TABLE (PREFIX_0F383E) },
7189 { PREFIX_TABLE (PREFIX_0F383F) },
7191 { PREFIX_TABLE (PREFIX_0F3840) },
7192 { PREFIX_TABLE (PREFIX_0F3841) },
7263 { PREFIX_TABLE (PREFIX_0F3880) },
7264 { PREFIX_TABLE (PREFIX_0F3881) },
7265 { PREFIX_TABLE (PREFIX_0F3882) },
7344 { PREFIX_TABLE (PREFIX_0F38C8) },
7345 { PREFIX_TABLE (PREFIX_0F38C9) },
7346 { PREFIX_TABLE (PREFIX_0F38CA) },
7347 { PREFIX_TABLE (PREFIX_0F38CB) },
7348 { PREFIX_TABLE (PREFIX_0F38CC) },
7349 { PREFIX_TABLE (PREFIX_0F38CD) },
7351 { PREFIX_TABLE (PREFIX_0F38CF) },
7365 { PREFIX_TABLE (PREFIX_0F38DB) },
7366 { PREFIX_TABLE (PREFIX_0F38DC) },
7367 { PREFIX_TABLE (PREFIX_0F38DD) },
7368 { PREFIX_TABLE (PREFIX_0F38DE) },
7369 { PREFIX_TABLE (PREFIX_0F38DF) },
7389 { PREFIX_TABLE (PREFIX_0F38F0) },
7390 { PREFIX_TABLE (PREFIX_0F38F1) },
7394 { PREFIX_TABLE (PREFIX_0F38F5) },
7395 { PREFIX_TABLE (PREFIX_0F38F6) },
7407 /* THREE_BYTE_0F3A */
7419 { PREFIX_TABLE (PREFIX_0F3A08) },
7420 { PREFIX_TABLE (PREFIX_0F3A09) },
7421 { PREFIX_TABLE (PREFIX_0F3A0A) },
7422 { PREFIX_TABLE (PREFIX_0F3A0B) },
7423 { PREFIX_TABLE (PREFIX_0F3A0C) },
7424 { PREFIX_TABLE (PREFIX_0F3A0D) },
7425 { PREFIX_TABLE (PREFIX_0F3A0E) },
7426 { "palignr", { MX, EM, Ib }, PREFIX_OPCODE },
7432 { PREFIX_TABLE (PREFIX_0F3A14) },
7433 { PREFIX_TABLE (PREFIX_0F3A15) },
7434 { PREFIX_TABLE (PREFIX_0F3A16) },
7435 { PREFIX_TABLE (PREFIX_0F3A17) },
7446 { PREFIX_TABLE (PREFIX_0F3A20) },
7447 { PREFIX_TABLE (PREFIX_0F3A21) },
7448 { PREFIX_TABLE (PREFIX_0F3A22) },
7482 { PREFIX_TABLE (PREFIX_0F3A40) },
7483 { PREFIX_TABLE (PREFIX_0F3A41) },
7484 { PREFIX_TABLE (PREFIX_0F3A42) },
7486 { PREFIX_TABLE (PREFIX_0F3A44) },
7518 { PREFIX_TABLE (PREFIX_0F3A60) },
7519 { PREFIX_TABLE (PREFIX_0F3A61) },
7520 { PREFIX_TABLE (PREFIX_0F3A62) },
7521 { PREFIX_TABLE (PREFIX_0F3A63) },
7639 { PREFIX_TABLE (PREFIX_0F3ACC) },
7641 { PREFIX_TABLE (PREFIX_0F3ACE) },
7642 { PREFIX_TABLE (PREFIX_0F3ACF) },
7660 { PREFIX_TABLE (PREFIX_0F3ADF) },
7700 static const struct dis386 xop_table[][256] = {
7853 { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7854 { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7855 { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7863 { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7864 { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7871 { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7872 { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7873 { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7881 { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7882 { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7886 { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7887 { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7890 { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7908 { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 },
7920 { "vprotb", { XM, Vex_2src_1, Ib }, 0 },
7921 { "vprotw", { XM, Vex_2src_1, Ib }, 0 },
7922 { "vprotd", { XM, Vex_2src_1, Ib }, 0 },
7923 { "vprotq", { XM, Vex_2src_1, Ib }, 0 },
7933 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7934 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7935 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7936 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7969 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7970 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7971 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7972 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7996 { REG_TABLE (REG_XOP_TBM_01) },
7997 { REG_TABLE (REG_XOP_TBM_02) },
8015 { REG_TABLE (REG_XOP_LWPCB) },
8139 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8140 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8141 { "vfrczss", { XM, EXd }, 0 },
8142 { "vfrczsd", { XM, EXq }, 0 },
8157 { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8158 { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8159 { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8160 { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8161 { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8162 { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8163 { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8164 { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8166 { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8167 { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8168 { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8169 { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8212 { "vphaddbw", { XM, EXxmm }, 0 },
8213 { "vphaddbd", { XM, EXxmm }, 0 },
8214 { "vphaddbq", { XM, EXxmm }, 0 },
8217 { "vphaddwd", { XM, EXxmm }, 0 },
8218 { "vphaddwq", { XM, EXxmm }, 0 },
8223 { "vphadddq", { XM, EXxmm }, 0 },
8230 { "vphaddubw", { XM, EXxmm }, 0 },
8231 { "vphaddubd", { XM, EXxmm }, 0 },
8232 { "vphaddubq", { XM, EXxmm }, 0 },
8235 { "vphadduwd", { XM, EXxmm }, 0 },
8236 { "vphadduwq", { XM, EXxmm }, 0 },
8241 { "vphaddudq", { XM, EXxmm }, 0 },
8248 { "vphsubbw", { XM, EXxmm }, 0 },
8249 { "vphsubwd", { XM, EXxmm }, 0 },
8250 { "vphsubdq", { XM, EXxmm }, 0 },
8304 { "bextr", { Gv, Ev, Iq }, 0 },
8306 { REG_TABLE (REG_XOP_LWP) },
8576 static const struct dis386 vex_table[][256] = {
8598 { PREFIX_TABLE (PREFIX_VEX_0F10) },
8599 { PREFIX_TABLE (PREFIX_VEX_0F11) },
8600 { PREFIX_TABLE (PREFIX_VEX_0F12) },
8601 { MOD_TABLE (MOD_VEX_0F13) },
8602 { VEX_W_TABLE (VEX_W_0F14) },
8603 { VEX_W_TABLE (VEX_W_0F15) },
8604 { PREFIX_TABLE (PREFIX_VEX_0F16) },
8605 { MOD_TABLE (MOD_VEX_0F17) },
8625 { VEX_W_TABLE (VEX_W_0F28) },
8626 { VEX_W_TABLE (VEX_W_0F29) },
8627 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8628 { MOD_TABLE (MOD_VEX_0F2B) },
8629 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8630 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8631 { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8632 { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8653 { PREFIX_TABLE (PREFIX_VEX_0F41) },
8654 { PREFIX_TABLE (PREFIX_VEX_0F42) },
8656 { PREFIX_TABLE (PREFIX_VEX_0F44) },
8657 { PREFIX_TABLE (PREFIX_VEX_0F45) },
8658 { PREFIX_TABLE (PREFIX_VEX_0F46) },
8659 { PREFIX_TABLE (PREFIX_VEX_0F47) },
8663 { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8664 { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8670 { MOD_TABLE (MOD_VEX_0F50) },
8671 { PREFIX_TABLE (PREFIX_VEX_0F51) },
8672 { PREFIX_TABLE (PREFIX_VEX_0F52) },
8673 { PREFIX_TABLE (PREFIX_VEX_0F53) },
8674 { "vandpX", { XM, Vex, EXx }, 0 },
8675 { "vandnpX", { XM, Vex, EXx }, 0 },
8676 { "vorpX", { XM, Vex, EXx }, 0 },
8677 { "vxorpX", { XM, Vex, EXx }, 0 },
8679 { PREFIX_TABLE (PREFIX_VEX_0F58) },
8680 { PREFIX_TABLE (PREFIX_VEX_0F59) },
8681 { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8682 { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8683 { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8684 { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8685 { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8686 { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8688 { PREFIX_TABLE (PREFIX_VEX_0F60) },
8689 { PREFIX_TABLE (PREFIX_VEX_0F61) },
8690 { PREFIX_TABLE (PREFIX_VEX_0F62) },
8691 { PREFIX_TABLE (PREFIX_VEX_0F63) },
8692 { PREFIX_TABLE (PREFIX_VEX_0F64) },
8693 { PREFIX_TABLE (PREFIX_VEX_0F65) },
8694 { PREFIX_TABLE (PREFIX_VEX_0F66) },
8695 { PREFIX_TABLE (PREFIX_VEX_0F67) },
8697 { PREFIX_TABLE (PREFIX_VEX_0F68) },
8698 { PREFIX_TABLE (PREFIX_VEX_0F69) },
8699 { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8700 { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8701 { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8702 { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8703 { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8704 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8706 { PREFIX_TABLE (PREFIX_VEX_0F70) },
8707 { REG_TABLE (REG_VEX_0F71) },
8708 { REG_TABLE (REG_VEX_0F72) },
8709 { REG_TABLE (REG_VEX_0F73) },
8710 { PREFIX_TABLE (PREFIX_VEX_0F74) },
8711 { PREFIX_TABLE (PREFIX_VEX_0F75) },
8712 { PREFIX_TABLE (PREFIX_VEX_0F76) },
8713 { PREFIX_TABLE (PREFIX_VEX_0F77) },
8719 { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8720 { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8721 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8722 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8742 { PREFIX_TABLE (PREFIX_VEX_0F90) },
8743 { PREFIX_TABLE (PREFIX_VEX_0F91) },
8744 { PREFIX_TABLE (PREFIX_VEX_0F92) },
8745 { PREFIX_TABLE (PREFIX_VEX_0F93) },
8751 { PREFIX_TABLE (PREFIX_VEX_0F98) },
8752 { PREFIX_TABLE (PREFIX_VEX_0F99) },
8775 { REG_TABLE (REG_VEX_0FAE) },
8798 { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8800 { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8801 { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8802 { "vshufpX", { XM, Vex, EXx, Ib }, 0 },
8814 { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8815 { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8816 { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8817 { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8818 { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8819 { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8820 { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8821 { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8823 { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8824 { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8825 { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8826 { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8827 { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8828 { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8829 { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8830 { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8832 { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8833 { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8834 { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8835 { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8836 { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8837 { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8838 { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8839 { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8841 { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8842 { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8843 { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8844 { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8845 { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8846 { PREFIX_TABLE (PREFIX_VEX_0FED) },
8847 { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8848 { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8850 { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8851 { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8852 { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8853 { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8854 { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8855 { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8856 { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8857 { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8859 { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8860 { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8861 { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8862 { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8863 { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8864 { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8865 { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8871 { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8872 { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8873 { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8874 { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8875 { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8876 { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8877 { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8878 { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8880 { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8881 { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8882 { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8883 { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8884 { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8885 { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8886 { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8887 { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8892 { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8895 { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8896 { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8898 { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8899 { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8900 { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8902 { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8903 { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8904 { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8907 { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8908 { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8909 { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8910 { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8911 { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8912 { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8916 { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8917 { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8918 { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8919 { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8920 { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8921 { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8922 { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8923 { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8925 { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8926 { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8927 { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8928 { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8929 { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8930 { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8931 { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8932 { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8934 { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8935 { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8936 { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8937 { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8938 { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8939 { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8940 { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8941 { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8943 { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8944 { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8948 { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8949 { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8950 { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8970 { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8971 { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8972 { PREFIX_TABLE (PREFIX_VEX_0F385A) },
9006 { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9007 { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9028 { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9030 { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9033 { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9034 { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9035 { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9036 { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9039 { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9040 { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9042 { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9043 { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9044 { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9045 { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9046 { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9047 { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9048 { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9049 { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9057 { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9058 { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9060 { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9061 { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9062 { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9063 { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9064 { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9065 { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9066 { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9067 { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9075 { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9076 { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9078 { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9079 { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9080 { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9081 { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9082 { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9083 { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9084 { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9085 { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9103 { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
9117 { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9118 { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9119 { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9120 { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9121 { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9143 { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9144 { REG_TABLE (REG_VEX_0F38F3) },
9146 { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9147 { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9148 { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9162 { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9163 { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9164 { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9166 { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9167 { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9168 { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9171 { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9172 { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9173 { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9174 { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9175 { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9176 { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9177 { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9178 { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9184 { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9185 { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9186 { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9187 { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9189 { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9190 { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9194 { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9198 { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9199 { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9200 { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9216 { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9217 { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9218 { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9219 { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9225 { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9226 { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9234 { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9235 { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9236 { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9238 { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9240 { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9243 { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9244 { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9245 { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9246 { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9247 { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9265 { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9266 { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9267 { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9268 { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9270 { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9271 { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9272 { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9273 { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9279 { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9280 { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9281 { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9282 { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9283 { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9284 { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9285 { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9286 { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9297 { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9298 { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9299 { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9300 { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9301 { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9302 { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9303 { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9304 { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9393 { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9394 { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9412 { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9432 { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9452 #define NEED_OPCODE_TABLE
9453 #include "i386-dis-evex.h"
9454 #undef NEED_OPCODE_TABLE
9455 static const struct dis386 vex_len_table[][2] = {
9456 /* VEX_LEN_0F10_P_1 */
9458 { VEX_W_TABLE (VEX_W_0F10_P_1) },
9459 { VEX_W_TABLE (VEX_W_0F10_P_1) },
9462 /* VEX_LEN_0F10_P_3 */
9464 { VEX_W_TABLE (VEX_W_0F10_P_3) },
9465 { VEX_W_TABLE (VEX_W_0F10_P_3) },
9468 /* VEX_LEN_0F11_P_1 */
9470 { VEX_W_TABLE (VEX_W_0F11_P_1) },
9471 { VEX_W_TABLE (VEX_W_0F11_P_1) },
9474 /* VEX_LEN_0F11_P_3 */
9476 { VEX_W_TABLE (VEX_W_0F11_P_3) },
9477 { VEX_W_TABLE (VEX_W_0F11_P_3) },
9480 /* VEX_LEN_0F12_P_0_M_0 */
9482 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9485 /* VEX_LEN_0F12_P_0_M_1 */
9487 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9490 /* VEX_LEN_0F12_P_2 */
9492 { VEX_W_TABLE (VEX_W_0F12_P_2) },
9495 /* VEX_LEN_0F13_M_0 */
9497 { VEX_W_TABLE (VEX_W_0F13_M_0) },
9500 /* VEX_LEN_0F16_P_0_M_0 */
9502 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9505 /* VEX_LEN_0F16_P_0_M_1 */
9507 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9510 /* VEX_LEN_0F16_P_2 */
9512 { VEX_W_TABLE (VEX_W_0F16_P_2) },
9515 /* VEX_LEN_0F17_M_0 */
9517 { VEX_W_TABLE (VEX_W_0F17_M_0) },
9520 /* VEX_LEN_0F2A_P_1 */
9522 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
9523 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
9526 /* VEX_LEN_0F2A_P_3 */
9528 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
9529 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
9532 /* VEX_LEN_0F2C_P_1 */
9534 { "vcvttss2siY", { Gv, EXdScalar }, 0 },
9535 { "vcvttss2siY", { Gv, EXdScalar }, 0 },
9538 /* VEX_LEN_0F2C_P_3 */
9540 { "vcvttsd2siY", { Gv, EXqScalar }, 0 },
9541 { "vcvttsd2siY", { Gv, EXqScalar }, 0 },
9544 /* VEX_LEN_0F2D_P_1 */
9546 { "vcvtss2siY", { Gv, EXdScalar }, 0 },
9547 { "vcvtss2siY", { Gv, EXdScalar }, 0 },
9550 /* VEX_LEN_0F2D_P_3 */
9552 { "vcvtsd2siY", { Gv, EXqScalar }, 0 },
9553 { "vcvtsd2siY", { Gv, EXqScalar }, 0 },
9556 /* VEX_LEN_0F2E_P_0 */
9558 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9559 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9562 /* VEX_LEN_0F2E_P_2 */
9564 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9565 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9568 /* VEX_LEN_0F2F_P_0 */
9570 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9571 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9574 /* VEX_LEN_0F2F_P_2 */
9576 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9577 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9580 /* VEX_LEN_0F41_P_0 */
9583 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9585 /* VEX_LEN_0F41_P_2 */
9588 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9590 /* VEX_LEN_0F42_P_0 */
9593 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9595 /* VEX_LEN_0F42_P_2 */
9598 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9600 /* VEX_LEN_0F44_P_0 */
9602 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9604 /* VEX_LEN_0F44_P_2 */
9606 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9608 /* VEX_LEN_0F45_P_0 */
9611 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9613 /* VEX_LEN_0F45_P_2 */
9616 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9618 /* VEX_LEN_0F46_P_0 */
9621 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9623 /* VEX_LEN_0F46_P_2 */
9626 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9628 /* VEX_LEN_0F47_P_0 */
9631 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9633 /* VEX_LEN_0F47_P_2 */
9636 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9638 /* VEX_LEN_0F4A_P_0 */
9641 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9643 /* VEX_LEN_0F4A_P_2 */
9646 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9648 /* VEX_LEN_0F4B_P_0 */
9651 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9653 /* VEX_LEN_0F4B_P_2 */
9656 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9659 /* VEX_LEN_0F51_P_1 */
9661 { VEX_W_TABLE (VEX_W_0F51_P_1) },
9662 { VEX_W_TABLE (VEX_W_0F51_P_1) },
9665 /* VEX_LEN_0F51_P_3 */
9667 { VEX_W_TABLE (VEX_W_0F51_P_3) },
9668 { VEX_W_TABLE (VEX_W_0F51_P_3) },
9671 /* VEX_LEN_0F52_P_1 */
9673 { VEX_W_TABLE (VEX_W_0F52_P_1) },
9674 { VEX_W_TABLE (VEX_W_0F52_P_1) },
9677 /* VEX_LEN_0F53_P_1 */
9679 { VEX_W_TABLE (VEX_W_0F53_P_1) },
9680 { VEX_W_TABLE (VEX_W_0F53_P_1) },
9683 /* VEX_LEN_0F58_P_1 */
9685 { VEX_W_TABLE (VEX_W_0F58_P_1) },
9686 { VEX_W_TABLE (VEX_W_0F58_P_1) },
9689 /* VEX_LEN_0F58_P_3 */
9691 { VEX_W_TABLE (VEX_W_0F58_P_3) },
9692 { VEX_W_TABLE (VEX_W_0F58_P_3) },
9695 /* VEX_LEN_0F59_P_1 */
9697 { VEX_W_TABLE (VEX_W_0F59_P_1) },
9698 { VEX_W_TABLE (VEX_W_0F59_P_1) },
9701 /* VEX_LEN_0F59_P_3 */
9703 { VEX_W_TABLE (VEX_W_0F59_P_3) },
9704 { VEX_W_TABLE (VEX_W_0F59_P_3) },
9707 /* VEX_LEN_0F5A_P_1 */
9709 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9710 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9713 /* VEX_LEN_0F5A_P_3 */
9715 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9716 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9719 /* VEX_LEN_0F5C_P_1 */
9721 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9722 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9725 /* VEX_LEN_0F5C_P_3 */
9727 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9728 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9731 /* VEX_LEN_0F5D_P_1 */
9733 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9734 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9737 /* VEX_LEN_0F5D_P_3 */
9739 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9740 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9743 /* VEX_LEN_0F5E_P_1 */
9745 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9746 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9749 /* VEX_LEN_0F5E_P_3 */
9751 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9752 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9755 /* VEX_LEN_0F5F_P_1 */
9757 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9758 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9761 /* VEX_LEN_0F5F_P_3 */
9763 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9764 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9767 /* VEX_LEN_0F6E_P_2 */
9769 { "vmovK", { XMScalar, Edq }, 0 },
9770 { "vmovK", { XMScalar, Edq }, 0 },
9773 /* VEX_LEN_0F7E_P_1 */
9775 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9776 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9779 /* VEX_LEN_0F7E_P_2 */
9781 { "vmovK", { Edq, XMScalar }, 0 },
9782 { "vmovK", { Edq, XMScalar }, 0 },
9785 /* VEX_LEN_0F90_P_0 */
9787 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9790 /* VEX_LEN_0F90_P_2 */
9792 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9795 /* VEX_LEN_0F91_P_0 */
9797 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9800 /* VEX_LEN_0F91_P_2 */
9802 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9805 /* VEX_LEN_0F92_P_0 */
9807 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9810 /* VEX_LEN_0F92_P_2 */
9812 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9815 /* VEX_LEN_0F92_P_3 */
9817 { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9820 /* VEX_LEN_0F93_P_0 */
9822 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9825 /* VEX_LEN_0F93_P_2 */
9827 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9830 /* VEX_LEN_0F93_P_3 */
9832 { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9835 /* VEX_LEN_0F98_P_0 */
9837 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9840 /* VEX_LEN_0F98_P_2 */
9842 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9845 /* VEX_LEN_0F99_P_0 */
9847 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9850 /* VEX_LEN_0F99_P_2 */
9852 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9855 /* VEX_LEN_0FAE_R_2_M_0 */
9857 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9860 /* VEX_LEN_0FAE_R_3_M_0 */
9862 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9865 /* VEX_LEN_0FC2_P_1 */
9867 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9868 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9871 /* VEX_LEN_0FC2_P_3 */
9873 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9874 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9877 /* VEX_LEN_0FC4_P_2 */
9879 { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9882 /* VEX_LEN_0FC5_P_2 */
9884 { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9887 /* VEX_LEN_0FD6_P_2 */
9889 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9890 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9893 /* VEX_LEN_0FF7_P_2 */
9895 { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9898 /* VEX_LEN_0F3816_P_2 */
9901 { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9904 /* VEX_LEN_0F3819_P_2 */
9907 { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9910 /* VEX_LEN_0F381A_P_2_M_0 */
9913 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9916 /* VEX_LEN_0F3836_P_2 */
9919 { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9922 /* VEX_LEN_0F3841_P_2 */
9924 { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9927 /* VEX_LEN_0F385A_P_2_M_0 */
9930 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9933 /* VEX_LEN_0F38DB_P_2 */
9935 { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
9938 /* VEX_LEN_0F38F2_P_0 */
9940 { "andnS", { Gdq, VexGdq, Edq }, 0 },
9943 /* VEX_LEN_0F38F3_R_1_P_0 */
9945 { "blsrS", { VexGdq, Edq }, 0 },
9948 /* VEX_LEN_0F38F3_R_2_P_0 */
9950 { "blsmskS", { VexGdq, Edq }, 0 },
9953 /* VEX_LEN_0F38F3_R_3_P_0 */
9955 { "blsiS", { VexGdq, Edq }, 0 },
9958 /* VEX_LEN_0F38F5_P_0 */
9960 { "bzhiS", { Gdq, Edq, VexGdq }, 0 },
9963 /* VEX_LEN_0F38F5_P_1 */
9965 { "pextS", { Gdq, VexGdq, Edq }, 0 },
9968 /* VEX_LEN_0F38F5_P_3 */
9970 { "pdepS", { Gdq, VexGdq, Edq }, 0 },
9973 /* VEX_LEN_0F38F6_P_3 */
9975 { "mulxS", { Gdq, VexGdq, Edq }, 0 },
9978 /* VEX_LEN_0F38F7_P_0 */
9980 { "bextrS", { Gdq, Edq, VexGdq }, 0 },
9983 /* VEX_LEN_0F38F7_P_1 */
9985 { "sarxS", { Gdq, Edq, VexGdq }, 0 },
9988 /* VEX_LEN_0F38F7_P_2 */
9990 { "shlxS", { Gdq, Edq, VexGdq }, 0 },
9993 /* VEX_LEN_0F38F7_P_3 */
9995 { "shrxS", { Gdq, Edq, VexGdq }, 0 },
9998 /* VEX_LEN_0F3A00_P_2 */
10001 { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10004 /* VEX_LEN_0F3A01_P_2 */
10007 { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10010 /* VEX_LEN_0F3A06_P_2 */
10013 { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10016 /* VEX_LEN_0F3A0A_P_2 */
10018 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10019 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10022 /* VEX_LEN_0F3A0B_P_2 */
10024 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10025 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10028 /* VEX_LEN_0F3A14_P_2 */
10030 { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10033 /* VEX_LEN_0F3A15_P_2 */
10035 { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10038 /* VEX_LEN_0F3A16_P_2 */
10040 { "vpextrK", { Edq, XM, Ib }, 0 },
10043 /* VEX_LEN_0F3A17_P_2 */
10045 { "vextractps", { Edqd, XM, Ib }, 0 },
10048 /* VEX_LEN_0F3A18_P_2 */
10051 { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10054 /* VEX_LEN_0F3A19_P_2 */
10057 { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10060 /* VEX_LEN_0F3A20_P_2 */
10062 { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10065 /* VEX_LEN_0F3A21_P_2 */
10067 { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10070 /* VEX_LEN_0F3A22_P_2 */
10072 { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 },
10075 /* VEX_LEN_0F3A30_P_2 */
10077 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10080 /* VEX_LEN_0F3A31_P_2 */
10082 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10085 /* VEX_LEN_0F3A32_P_2 */
10087 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10090 /* VEX_LEN_0F3A33_P_2 */
10092 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10095 /* VEX_LEN_0F3A38_P_2 */
10098 { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10101 /* VEX_LEN_0F3A39_P_2 */
10104 { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10107 /* VEX_LEN_0F3A41_P_2 */
10109 { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10112 /* VEX_LEN_0F3A46_P_2 */
10115 { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10118 /* VEX_LEN_0F3A60_P_2 */
10120 { "vpcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10123 /* VEX_LEN_0F3A61_P_2 */
10125 { "vpcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10128 /* VEX_LEN_0F3A62_P_2 */
10130 { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10133 /* VEX_LEN_0F3A63_P_2 */
10135 { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10138 /* VEX_LEN_0F3A6A_P_2 */
10140 { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10143 /* VEX_LEN_0F3A6B_P_2 */
10145 { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10148 /* VEX_LEN_0F3A6E_P_2 */
10150 { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10153 /* VEX_LEN_0F3A6F_P_2 */
10155 { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10158 /* VEX_LEN_0F3A7A_P_2 */
10160 { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10163 /* VEX_LEN_0F3A7B_P_2 */
10165 { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10168 /* VEX_LEN_0F3A7E_P_2 */
10170 { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 },
10173 /* VEX_LEN_0F3A7F_P_2 */
10175 { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 },
10178 /* VEX_LEN_0F3ADF_P_2 */
10180 { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10183 /* VEX_LEN_0F3AF0_P_3 */
10185 { "rorxS", { Gdq, Edq, Ib }, 0 },
10188 /* VEX_LEN_0FXOP_08_CC */
10190 { "vpcomb", { XM, Vex128, EXx, Ib }, 0 },
10193 /* VEX_LEN_0FXOP_08_CD */
10195 { "vpcomw", { XM, Vex128, EXx, Ib }, 0 },
10198 /* VEX_LEN_0FXOP_08_CE */
10200 { "vpcomd", { XM, Vex128, EXx, Ib }, 0 },
10203 /* VEX_LEN_0FXOP_08_CF */
10205 { "vpcomq", { XM, Vex128, EXx, Ib }, 0 },
10208 /* VEX_LEN_0FXOP_08_EC */
10210 { "vpcomub", { XM, Vex128, EXx, Ib }, 0 },
10213 /* VEX_LEN_0FXOP_08_ED */
10215 { "vpcomuw", { XM, Vex128, EXx, Ib }, 0 },
10218 /* VEX_LEN_0FXOP_08_EE */
10220 { "vpcomud", { XM, Vex128, EXx, Ib }, 0 },
10223 /* VEX_LEN_0FXOP_08_EF */
10225 { "vpcomuq", { XM, Vex128, EXx, Ib }, 0 },
10228 /* VEX_LEN_0FXOP_09_80 */
10230 { "vfrczps", { XM, EXxmm }, 0 },
10231 { "vfrczps", { XM, EXymmq }, 0 },
10234 /* VEX_LEN_0FXOP_09_81 */
10236 { "vfrczpd", { XM, EXxmm }, 0 },
10237 { "vfrczpd", { XM, EXymmq }, 0 },
10241 static const struct dis386 vex_w_table[][2] = {
10243 /* VEX_W_0F10_P_0 */
10244 { "vmovups", { XM, EXx }, 0 },
10247 /* VEX_W_0F10_P_1 */
10248 { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 },
10251 /* VEX_W_0F10_P_2 */
10252 { "vmovupd", { XM, EXx }, 0 },
10255 /* VEX_W_0F10_P_3 */
10256 { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 },
10259 /* VEX_W_0F11_P_0 */
10260 { "vmovups", { EXxS, XM }, 0 },
10263 /* VEX_W_0F11_P_1 */
10264 { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10267 /* VEX_W_0F11_P_2 */
10268 { "vmovupd", { EXxS, XM }, 0 },
10271 /* VEX_W_0F11_P_3 */
10272 { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10275 /* VEX_W_0F12_P_0_M_0 */
10276 { "vmovlps", { XM, Vex128, EXq }, 0 },
10279 /* VEX_W_0F12_P_0_M_1 */
10280 { "vmovhlps", { XM, Vex128, EXq }, 0 },
10283 /* VEX_W_0F12_P_1 */
10284 { "vmovsldup", { XM, EXx }, 0 },
10287 /* VEX_W_0F12_P_2 */
10288 { "vmovlpd", { XM, Vex128, EXq }, 0 },
10291 /* VEX_W_0F12_P_3 */
10292 { "vmovddup", { XM, EXymmq }, 0 },
10295 /* VEX_W_0F13_M_0 */
10296 { "vmovlpX", { EXq, XM }, 0 },
10300 { "vunpcklpX", { XM, Vex, EXx }, 0 },
10304 { "vunpckhpX", { XM, Vex, EXx }, 0 },
10307 /* VEX_W_0F16_P_0_M_0 */
10308 { "vmovhps", { XM, Vex128, EXq }, 0 },
10311 /* VEX_W_0F16_P_0_M_1 */
10312 { "vmovlhps", { XM, Vex128, EXq }, 0 },
10315 /* VEX_W_0F16_P_1 */
10316 { "vmovshdup", { XM, EXx }, 0 },
10319 /* VEX_W_0F16_P_2 */
10320 { "vmovhpd", { XM, Vex128, EXq }, 0 },
10323 /* VEX_W_0F17_M_0 */
10324 { "vmovhpX", { EXq, XM }, 0 },
10328 { "vmovapX", { XM, EXx }, 0 },
10332 { "vmovapX", { EXxS, XM }, 0 },
10335 /* VEX_W_0F2B_M_0 */
10336 { "vmovntpX", { Mx, XM }, 0 },
10339 /* VEX_W_0F2E_P_0 */
10340 { "vucomiss", { XMScalar, EXdScalar }, 0 },
10343 /* VEX_W_0F2E_P_2 */
10344 { "vucomisd", { XMScalar, EXqScalar }, 0 },
10347 /* VEX_W_0F2F_P_0 */
10348 { "vcomiss", { XMScalar, EXdScalar }, 0 },
10351 /* VEX_W_0F2F_P_2 */
10352 { "vcomisd", { XMScalar, EXqScalar }, 0 },
10355 /* VEX_W_0F41_P_0_LEN_1 */
10356 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
10357 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
10360 /* VEX_W_0F41_P_2_LEN_1 */
10361 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
10362 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
10365 /* VEX_W_0F42_P_0_LEN_1 */
10366 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
10367 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
10370 /* VEX_W_0F42_P_2_LEN_1 */
10371 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
10372 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
10375 /* VEX_W_0F44_P_0_LEN_0 */
10376 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
10377 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
10380 /* VEX_W_0F44_P_2_LEN_0 */
10381 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
10382 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
10385 /* VEX_W_0F45_P_0_LEN_1 */
10386 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
10387 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
10390 /* VEX_W_0F45_P_2_LEN_1 */
10391 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
10392 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
10395 /* VEX_W_0F46_P_0_LEN_1 */
10396 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
10397 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
10400 /* VEX_W_0F46_P_2_LEN_1 */
10401 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
10402 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
10405 /* VEX_W_0F47_P_0_LEN_1 */
10406 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
10407 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
10410 /* VEX_W_0F47_P_2_LEN_1 */
10411 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
10412 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
10415 /* VEX_W_0F4A_P_0_LEN_1 */
10416 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
10417 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
10420 /* VEX_W_0F4A_P_2_LEN_1 */
10421 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
10422 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
10425 /* VEX_W_0F4B_P_0_LEN_1 */
10426 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10427 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10430 /* VEX_W_0F4B_P_2_LEN_1 */
10431 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10434 /* VEX_W_0F50_M_0 */
10435 { "vmovmskpX", { Gdq, XS }, 0 },
10438 /* VEX_W_0F51_P_0 */
10439 { "vsqrtps", { XM, EXx }, 0 },
10442 /* VEX_W_0F51_P_1 */
10443 { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
10446 /* VEX_W_0F51_P_2 */
10447 { "vsqrtpd", { XM, EXx }, 0 },
10450 /* VEX_W_0F51_P_3 */
10451 { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10454 /* VEX_W_0F52_P_0 */
10455 { "vrsqrtps", { XM, EXx }, 0 },
10458 /* VEX_W_0F52_P_1 */
10459 { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
10462 /* VEX_W_0F53_P_0 */
10463 { "vrcpps", { XM, EXx }, 0 },
10466 /* VEX_W_0F53_P_1 */
10467 { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 },
10470 /* VEX_W_0F58_P_0 */
10471 { "vaddps", { XM, Vex, EXx }, 0 },
10474 /* VEX_W_0F58_P_1 */
10475 { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 },
10478 /* VEX_W_0F58_P_2 */
10479 { "vaddpd", { XM, Vex, EXx }, 0 },
10482 /* VEX_W_0F58_P_3 */
10483 { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10486 /* VEX_W_0F59_P_0 */
10487 { "vmulps", { XM, Vex, EXx }, 0 },
10490 /* VEX_W_0F59_P_1 */
10491 { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 },
10494 /* VEX_W_0F59_P_2 */
10495 { "vmulpd", { XM, Vex, EXx }, 0 },
10498 /* VEX_W_0F59_P_3 */
10499 { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10502 /* VEX_W_0F5A_P_0 */
10503 { "vcvtps2pd", { XM, EXxmmq }, 0 },
10506 /* VEX_W_0F5A_P_1 */
10507 { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 },
10510 /* VEX_W_0F5A_P_3 */
10511 { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 },
10514 /* VEX_W_0F5B_P_0 */
10515 { "vcvtdq2ps", { XM, EXx }, 0 },
10518 /* VEX_W_0F5B_P_1 */
10519 { "vcvttps2dq", { XM, EXx }, 0 },
10522 /* VEX_W_0F5B_P_2 */
10523 { "vcvtps2dq", { XM, EXx }, 0 },
10526 /* VEX_W_0F5C_P_0 */
10527 { "vsubps", { XM, Vex, EXx }, 0 },
10530 /* VEX_W_0F5C_P_1 */
10531 { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 },
10534 /* VEX_W_0F5C_P_2 */
10535 { "vsubpd", { XM, Vex, EXx }, 0 },
10538 /* VEX_W_0F5C_P_3 */
10539 { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10542 /* VEX_W_0F5D_P_0 */
10543 { "vminps", { XM, Vex, EXx }, 0 },
10546 /* VEX_W_0F5D_P_1 */
10547 { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 },
10550 /* VEX_W_0F5D_P_2 */
10551 { "vminpd", { XM, Vex, EXx }, 0 },
10554 /* VEX_W_0F5D_P_3 */
10555 { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10558 /* VEX_W_0F5E_P_0 */
10559 { "vdivps", { XM, Vex, EXx }, 0 },
10562 /* VEX_W_0F5E_P_1 */
10563 { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 },
10566 /* VEX_W_0F5E_P_2 */
10567 { "vdivpd", { XM, Vex, EXx }, 0 },
10570 /* VEX_W_0F5E_P_3 */
10571 { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10574 /* VEX_W_0F5F_P_0 */
10575 { "vmaxps", { XM, Vex, EXx }, 0 },
10578 /* VEX_W_0F5F_P_1 */
10579 { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 },
10582 /* VEX_W_0F5F_P_2 */
10583 { "vmaxpd", { XM, Vex, EXx }, 0 },
10586 /* VEX_W_0F5F_P_3 */
10587 { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10590 /* VEX_W_0F60_P_2 */
10591 { "vpunpcklbw", { XM, Vex, EXx }, 0 },
10594 /* VEX_W_0F61_P_2 */
10595 { "vpunpcklwd", { XM, Vex, EXx }, 0 },
10598 /* VEX_W_0F62_P_2 */
10599 { "vpunpckldq", { XM, Vex, EXx }, 0 },
10602 /* VEX_W_0F63_P_2 */
10603 { "vpacksswb", { XM, Vex, EXx }, 0 },
10606 /* VEX_W_0F64_P_2 */
10607 { "vpcmpgtb", { XM, Vex, EXx }, 0 },
10610 /* VEX_W_0F65_P_2 */
10611 { "vpcmpgtw", { XM, Vex, EXx }, 0 },
10614 /* VEX_W_0F66_P_2 */
10615 { "vpcmpgtd", { XM, Vex, EXx }, 0 },
10618 /* VEX_W_0F67_P_2 */
10619 { "vpackuswb", { XM, Vex, EXx }, 0 },
10622 /* VEX_W_0F68_P_2 */
10623 { "vpunpckhbw", { XM, Vex, EXx }, 0 },
10626 /* VEX_W_0F69_P_2 */
10627 { "vpunpckhwd", { XM, Vex, EXx }, 0 },
10630 /* VEX_W_0F6A_P_2 */
10631 { "vpunpckhdq", { XM, Vex, EXx }, 0 },
10634 /* VEX_W_0F6B_P_2 */
10635 { "vpackssdw", { XM, Vex, EXx }, 0 },
10638 /* VEX_W_0F6C_P_2 */
10639 { "vpunpcklqdq", { XM, Vex, EXx }, 0 },
10642 /* VEX_W_0F6D_P_2 */
10643 { "vpunpckhqdq", { XM, Vex, EXx }, 0 },
10646 /* VEX_W_0F6F_P_1 */
10647 { "vmovdqu", { XM, EXx }, 0 },
10650 /* VEX_W_0F6F_P_2 */
10651 { "vmovdqa", { XM, EXx }, 0 },
10654 /* VEX_W_0F70_P_1 */
10655 { "vpshufhw", { XM, EXx, Ib }, 0 },
10658 /* VEX_W_0F70_P_2 */
10659 { "vpshufd", { XM, EXx, Ib }, 0 },
10662 /* VEX_W_0F70_P_3 */
10663 { "vpshuflw", { XM, EXx, Ib }, 0 },
10666 /* VEX_W_0F71_R_2_P_2 */
10667 { "vpsrlw", { Vex, XS, Ib }, 0 },
10670 /* VEX_W_0F71_R_4_P_2 */
10671 { "vpsraw", { Vex, XS, Ib }, 0 },
10674 /* VEX_W_0F71_R_6_P_2 */
10675 { "vpsllw", { Vex, XS, Ib }, 0 },
10678 /* VEX_W_0F72_R_2_P_2 */
10679 { "vpsrld", { Vex, XS, Ib }, 0 },
10682 /* VEX_W_0F72_R_4_P_2 */
10683 { "vpsrad", { Vex, XS, Ib }, 0 },
10686 /* VEX_W_0F72_R_6_P_2 */
10687 { "vpslld", { Vex, XS, Ib }, 0 },
10690 /* VEX_W_0F73_R_2_P_2 */
10691 { "vpsrlq", { Vex, XS, Ib }, 0 },
10694 /* VEX_W_0F73_R_3_P_2 */
10695 { "vpsrldq", { Vex, XS, Ib }, 0 },
10698 /* VEX_W_0F73_R_6_P_2 */
10699 { "vpsllq", { Vex, XS, Ib }, 0 },
10702 /* VEX_W_0F73_R_7_P_2 */
10703 { "vpslldq", { Vex, XS, Ib }, 0 },
10706 /* VEX_W_0F74_P_2 */
10707 { "vpcmpeqb", { XM, Vex, EXx }, 0 },
10710 /* VEX_W_0F75_P_2 */
10711 { "vpcmpeqw", { XM, Vex, EXx }, 0 },
10714 /* VEX_W_0F76_P_2 */
10715 { "vpcmpeqd", { XM, Vex, EXx }, 0 },
10718 /* VEX_W_0F77_P_0 */
10719 { "", { VZERO }, 0 },
10722 /* VEX_W_0F7C_P_2 */
10723 { "vhaddpd", { XM, Vex, EXx }, 0 },
10726 /* VEX_W_0F7C_P_3 */
10727 { "vhaddps", { XM, Vex, EXx }, 0 },
10730 /* VEX_W_0F7D_P_2 */
10731 { "vhsubpd", { XM, Vex, EXx }, 0 },
10734 /* VEX_W_0F7D_P_3 */
10735 { "vhsubps", { XM, Vex, EXx }, 0 },
10738 /* VEX_W_0F7E_P_1 */
10739 { "vmovq", { XMScalar, EXqScalar }, 0 },
10742 /* VEX_W_0F7F_P_1 */
10743 { "vmovdqu", { EXxS, XM }, 0 },
10746 /* VEX_W_0F7F_P_2 */
10747 { "vmovdqa", { EXxS, XM }, 0 },
10750 /* VEX_W_0F90_P_0_LEN_0 */
10751 { "kmovw", { MaskG, MaskE }, 0 },
10752 { "kmovq", { MaskG, MaskE }, 0 },
10755 /* VEX_W_0F90_P_2_LEN_0 */
10756 { "kmovb", { MaskG, MaskBDE }, 0 },
10757 { "kmovd", { MaskG, MaskBDE }, 0 },
10760 /* VEX_W_0F91_P_0_LEN_0 */
10761 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10762 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10765 /* VEX_W_0F91_P_2_LEN_0 */
10766 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10767 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10770 /* VEX_W_0F92_P_0_LEN_0 */
10771 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10774 /* VEX_W_0F92_P_2_LEN_0 */
10775 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10778 /* VEX_W_0F92_P_3_LEN_0 */
10779 { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
10780 { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
10783 /* VEX_W_0F93_P_0_LEN_0 */
10784 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10787 /* VEX_W_0F93_P_2_LEN_0 */
10788 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10791 /* VEX_W_0F93_P_3_LEN_0 */
10792 { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
10793 { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
10796 /* VEX_W_0F98_P_0_LEN_0 */
10797 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10798 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10801 /* VEX_W_0F98_P_2_LEN_0 */
10802 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10803 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10806 /* VEX_W_0F99_P_0_LEN_0 */
10807 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10808 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10811 /* VEX_W_0F99_P_2_LEN_0 */
10812 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10813 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10816 /* VEX_W_0FAE_R_2_M_0 */
10817 { "vldmxcsr", { Md }, 0 },
10820 /* VEX_W_0FAE_R_3_M_0 */
10821 { "vstmxcsr", { Md }, 0 },
10824 /* VEX_W_0FC2_P_0 */
10825 { "vcmpps", { XM, Vex, EXx, VCMP }, 0 },
10828 /* VEX_W_0FC2_P_1 */
10829 { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
10832 /* VEX_W_0FC2_P_2 */
10833 { "vcmppd", { XM, Vex, EXx, VCMP }, 0 },
10836 /* VEX_W_0FC2_P_3 */
10837 { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
10840 /* VEX_W_0FC4_P_2 */
10841 { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 },
10844 /* VEX_W_0FC5_P_2 */
10845 { "vpextrw", { Gdq, XS, Ib }, 0 },
10848 /* VEX_W_0FD0_P_2 */
10849 { "vaddsubpd", { XM, Vex, EXx }, 0 },
10852 /* VEX_W_0FD0_P_3 */
10853 { "vaddsubps", { XM, Vex, EXx }, 0 },
10856 /* VEX_W_0FD1_P_2 */
10857 { "vpsrlw", { XM, Vex, EXxmm }, 0 },
10860 /* VEX_W_0FD2_P_2 */
10861 { "vpsrld", { XM, Vex, EXxmm }, 0 },
10864 /* VEX_W_0FD3_P_2 */
10865 { "vpsrlq", { XM, Vex, EXxmm }, 0 },
10868 /* VEX_W_0FD4_P_2 */
10869 { "vpaddq", { XM, Vex, EXx }, 0 },
10872 /* VEX_W_0FD5_P_2 */
10873 { "vpmullw", { XM, Vex, EXx }, 0 },
10876 /* VEX_W_0FD6_P_2 */
10877 { "vmovq", { EXqScalarS, XMScalar }, 0 },
10880 /* VEX_W_0FD7_P_2_M_1 */
10881 { "vpmovmskb", { Gdq, XS }, 0 },
10884 /* VEX_W_0FD8_P_2 */
10885 { "vpsubusb", { XM, Vex, EXx }, 0 },
10888 /* VEX_W_0FD9_P_2 */
10889 { "vpsubusw", { XM, Vex, EXx }, 0 },
10892 /* VEX_W_0FDA_P_2 */
10893 { "vpminub", { XM, Vex, EXx }, 0 },
10896 /* VEX_W_0FDB_P_2 */
10897 { "vpand", { XM, Vex, EXx }, 0 },
10900 /* VEX_W_0FDC_P_2 */
10901 { "vpaddusb", { XM, Vex, EXx }, 0 },
10904 /* VEX_W_0FDD_P_2 */
10905 { "vpaddusw", { XM, Vex, EXx }, 0 },
10908 /* VEX_W_0FDE_P_2 */
10909 { "vpmaxub", { XM, Vex, EXx }, 0 },
10912 /* VEX_W_0FDF_P_2 */
10913 { "vpandn", { XM, Vex, EXx }, 0 },
10916 /* VEX_W_0FE0_P_2 */
10917 { "vpavgb", { XM, Vex, EXx }, 0 },
10920 /* VEX_W_0FE1_P_2 */
10921 { "vpsraw", { XM, Vex, EXxmm }, 0 },
10924 /* VEX_W_0FE2_P_2 */
10925 { "vpsrad", { XM, Vex, EXxmm }, 0 },
10928 /* VEX_W_0FE3_P_2 */
10929 { "vpavgw", { XM, Vex, EXx }, 0 },
10932 /* VEX_W_0FE4_P_2 */
10933 { "vpmulhuw", { XM, Vex, EXx }, 0 },
10936 /* VEX_W_0FE5_P_2 */
10937 { "vpmulhw", { XM, Vex, EXx }, 0 },
10940 /* VEX_W_0FE6_P_1 */
10941 { "vcvtdq2pd", { XM, EXxmmq }, 0 },
10944 /* VEX_W_0FE6_P_2 */
10945 { "vcvttpd2dq%XY", { XMM, EXx }, 0 },
10948 /* VEX_W_0FE6_P_3 */
10949 { "vcvtpd2dq%XY", { XMM, EXx }, 0 },
10952 /* VEX_W_0FE7_P_2_M_0 */
10953 { "vmovntdq", { Mx, XM }, 0 },
10956 /* VEX_W_0FE8_P_2 */
10957 { "vpsubsb", { XM, Vex, EXx }, 0 },
10960 /* VEX_W_0FE9_P_2 */
10961 { "vpsubsw", { XM, Vex, EXx }, 0 },
10964 /* VEX_W_0FEA_P_2 */
10965 { "vpminsw", { XM, Vex, EXx }, 0 },
10968 /* VEX_W_0FEB_P_2 */
10969 { "vpor", { XM, Vex, EXx }, 0 },
10972 /* VEX_W_0FEC_P_2 */
10973 { "vpaddsb", { XM, Vex, EXx }, 0 },
10976 /* VEX_W_0FED_P_2 */
10977 { "vpaddsw", { XM, Vex, EXx }, 0 },
10980 /* VEX_W_0FEE_P_2 */
10981 { "vpmaxsw", { XM, Vex, EXx }, 0 },
10984 /* VEX_W_0FEF_P_2 */
10985 { "vpxor", { XM, Vex, EXx }, 0 },
10988 /* VEX_W_0FF0_P_3_M_0 */
10989 { "vlddqu", { XM, M }, 0 },
10992 /* VEX_W_0FF1_P_2 */
10993 { "vpsllw", { XM, Vex, EXxmm }, 0 },
10996 /* VEX_W_0FF2_P_2 */
10997 { "vpslld", { XM, Vex, EXxmm }, 0 },
11000 /* VEX_W_0FF3_P_2 */
11001 { "vpsllq", { XM, Vex, EXxmm }, 0 },
11004 /* VEX_W_0FF4_P_2 */
11005 { "vpmuludq", { XM, Vex, EXx }, 0 },
11008 /* VEX_W_0FF5_P_2 */
11009 { "vpmaddwd", { XM, Vex, EXx }, 0 },
11012 /* VEX_W_0FF6_P_2 */
11013 { "vpsadbw", { XM, Vex, EXx }, 0 },
11016 /* VEX_W_0FF7_P_2 */
11017 { "vmaskmovdqu", { XM, XS }, 0 },
11020 /* VEX_W_0FF8_P_2 */
11021 { "vpsubb", { XM, Vex, EXx }, 0 },
11024 /* VEX_W_0FF9_P_2 */
11025 { "vpsubw", { XM, Vex, EXx }, 0 },
11028 /* VEX_W_0FFA_P_2 */
11029 { "vpsubd", { XM, Vex, EXx }, 0 },
11032 /* VEX_W_0FFB_P_2 */
11033 { "vpsubq", { XM, Vex, EXx }, 0 },
11036 /* VEX_W_0FFC_P_2 */
11037 { "vpaddb", { XM, Vex, EXx }, 0 },
11040 /* VEX_W_0FFD_P_2 */
11041 { "vpaddw", { XM, Vex, EXx }, 0 },
11044 /* VEX_W_0FFE_P_2 */
11045 { "vpaddd", { XM, Vex, EXx }, 0 },
11048 /* VEX_W_0F3800_P_2 */
11049 { "vpshufb", { XM, Vex, EXx }, 0 },
11052 /* VEX_W_0F3801_P_2 */
11053 { "vphaddw", { XM, Vex, EXx }, 0 },
11056 /* VEX_W_0F3802_P_2 */
11057 { "vphaddd", { XM, Vex, EXx }, 0 },
11060 /* VEX_W_0F3803_P_2 */
11061 { "vphaddsw", { XM, Vex, EXx }, 0 },
11064 /* VEX_W_0F3804_P_2 */
11065 { "vpmaddubsw", { XM, Vex, EXx }, 0 },
11068 /* VEX_W_0F3805_P_2 */
11069 { "vphsubw", { XM, Vex, EXx }, 0 },
11072 /* VEX_W_0F3806_P_2 */
11073 { "vphsubd", { XM, Vex, EXx }, 0 },
11076 /* VEX_W_0F3807_P_2 */
11077 { "vphsubsw", { XM, Vex, EXx }, 0 },
11080 /* VEX_W_0F3808_P_2 */
11081 { "vpsignb", { XM, Vex, EXx }, 0 },
11084 /* VEX_W_0F3809_P_2 */
11085 { "vpsignw", { XM, Vex, EXx }, 0 },
11088 /* VEX_W_0F380A_P_2 */
11089 { "vpsignd", { XM, Vex, EXx }, 0 },
11092 /* VEX_W_0F380B_P_2 */
11093 { "vpmulhrsw", { XM, Vex, EXx }, 0 },
11096 /* VEX_W_0F380C_P_2 */
11097 { "vpermilps", { XM, Vex, EXx }, 0 },
11100 /* VEX_W_0F380D_P_2 */
11101 { "vpermilpd", { XM, Vex, EXx }, 0 },
11104 /* VEX_W_0F380E_P_2 */
11105 { "vtestps", { XM, EXx }, 0 },
11108 /* VEX_W_0F380F_P_2 */
11109 { "vtestpd", { XM, EXx }, 0 },
11112 /* VEX_W_0F3816_P_2 */
11113 { "vpermps", { XM, Vex, EXx }, 0 },
11116 /* VEX_W_0F3817_P_2 */
11117 { "vptest", { XM, EXx }, 0 },
11120 /* VEX_W_0F3818_P_2 */
11121 { "vbroadcastss", { XM, EXxmm_md }, 0 },
11124 /* VEX_W_0F3819_P_2 */
11125 { "vbroadcastsd", { XM, EXxmm_mq }, 0 },
11128 /* VEX_W_0F381A_P_2_M_0 */
11129 { "vbroadcastf128", { XM, Mxmm }, 0 },
11132 /* VEX_W_0F381C_P_2 */
11133 { "vpabsb", { XM, EXx }, 0 },
11136 /* VEX_W_0F381D_P_2 */
11137 { "vpabsw", { XM, EXx }, 0 },
11140 /* VEX_W_0F381E_P_2 */
11141 { "vpabsd", { XM, EXx }, 0 },
11144 /* VEX_W_0F3820_P_2 */
11145 { "vpmovsxbw", { XM, EXxmmq }, 0 },
11148 /* VEX_W_0F3821_P_2 */
11149 { "vpmovsxbd", { XM, EXxmmqd }, 0 },
11152 /* VEX_W_0F3822_P_2 */
11153 { "vpmovsxbq", { XM, EXxmmdw }, 0 },
11156 /* VEX_W_0F3823_P_2 */
11157 { "vpmovsxwd", { XM, EXxmmq }, 0 },
11160 /* VEX_W_0F3824_P_2 */
11161 { "vpmovsxwq", { XM, EXxmmqd }, 0 },
11164 /* VEX_W_0F3825_P_2 */
11165 { "vpmovsxdq", { XM, EXxmmq }, 0 },
11168 /* VEX_W_0F3828_P_2 */
11169 { "vpmuldq", { XM, Vex, EXx }, 0 },
11172 /* VEX_W_0F3829_P_2 */
11173 { "vpcmpeqq", { XM, Vex, EXx }, 0 },
11176 /* VEX_W_0F382A_P_2_M_0 */
11177 { "vmovntdqa", { XM, Mx }, 0 },
11180 /* VEX_W_0F382B_P_2 */
11181 { "vpackusdw", { XM, Vex, EXx }, 0 },
11184 /* VEX_W_0F382C_P_2_M_0 */
11185 { "vmaskmovps", { XM, Vex, Mx }, 0 },
11188 /* VEX_W_0F382D_P_2_M_0 */
11189 { "vmaskmovpd", { XM, Vex, Mx }, 0 },
11192 /* VEX_W_0F382E_P_2_M_0 */
11193 { "vmaskmovps", { Mx, Vex, XM }, 0 },
11196 /* VEX_W_0F382F_P_2_M_0 */
11197 { "vmaskmovpd", { Mx, Vex, XM }, 0 },
11200 /* VEX_W_0F3830_P_2 */
11201 { "vpmovzxbw", { XM, EXxmmq }, 0 },
11204 /* VEX_W_0F3831_P_2 */
11205 { "vpmovzxbd", { XM, EXxmmqd }, 0 },
11208 /* VEX_W_0F3832_P_2 */
11209 { "vpmovzxbq", { XM, EXxmmdw }, 0 },
11212 /* VEX_W_0F3833_P_2 */
11213 { "vpmovzxwd", { XM, EXxmmq }, 0 },
11216 /* VEX_W_0F3834_P_2 */
11217 { "vpmovzxwq", { XM, EXxmmqd }, 0 },
11220 /* VEX_W_0F3835_P_2 */
11221 { "vpmovzxdq", { XM, EXxmmq }, 0 },
11224 /* VEX_W_0F3836_P_2 */
11225 { "vpermd", { XM, Vex, EXx }, 0 },
11228 /* VEX_W_0F3837_P_2 */
11229 { "vpcmpgtq", { XM, Vex, EXx }, 0 },
11232 /* VEX_W_0F3838_P_2 */
11233 { "vpminsb", { XM, Vex, EXx }, 0 },
11236 /* VEX_W_0F3839_P_2 */
11237 { "vpminsd", { XM, Vex, EXx }, 0 },
11240 /* VEX_W_0F383A_P_2 */
11241 { "vpminuw", { XM, Vex, EXx }, 0 },
11244 /* VEX_W_0F383B_P_2 */
11245 { "vpminud", { XM, Vex, EXx }, 0 },
11248 /* VEX_W_0F383C_P_2 */
11249 { "vpmaxsb", { XM, Vex, EXx }, 0 },
11252 /* VEX_W_0F383D_P_2 */
11253 { "vpmaxsd", { XM, Vex, EXx }, 0 },
11256 /* VEX_W_0F383E_P_2 */
11257 { "vpmaxuw", { XM, Vex, EXx }, 0 },
11260 /* VEX_W_0F383F_P_2 */
11261 { "vpmaxud", { XM, Vex, EXx }, 0 },
11264 /* VEX_W_0F3840_P_2 */
11265 { "vpmulld", { XM, Vex, EXx }, 0 },
11268 /* VEX_W_0F3841_P_2 */
11269 { "vphminposuw", { XM, EXx }, 0 },
11272 /* VEX_W_0F3846_P_2 */
11273 { "vpsravd", { XM, Vex, EXx }, 0 },
11276 /* VEX_W_0F3858_P_2 */
11277 { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11280 /* VEX_W_0F3859_P_2 */
11281 { "vpbroadcastq", { XM, EXxmm_mq }, 0 },
11284 /* VEX_W_0F385A_P_2_M_0 */
11285 { "vbroadcasti128", { XM, Mxmm }, 0 },
11288 /* VEX_W_0F3878_P_2 */
11289 { "vpbroadcastb", { XM, EXxmm_mb }, 0 },
11292 /* VEX_W_0F3879_P_2 */
11293 { "vpbroadcastw", { XM, EXxmm_mw }, 0 },
11296 /* VEX_W_0F38CF_P_2 */
11297 { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
11300 /* VEX_W_0F38DB_P_2 */
11301 { "vaesimc", { XM, EXx }, 0 },
11304 /* VEX_W_0F3A00_P_2 */
11306 { "vpermq", { XM, EXx, Ib }, 0 },
11309 /* VEX_W_0F3A01_P_2 */
11311 { "vpermpd", { XM, EXx, Ib }, 0 },
11314 /* VEX_W_0F3A02_P_2 */
11315 { "vpblendd", { XM, Vex, EXx, Ib }, 0 },
11318 /* VEX_W_0F3A04_P_2 */
11319 { "vpermilps", { XM, EXx, Ib }, 0 },
11322 /* VEX_W_0F3A05_P_2 */
11323 { "vpermilpd", { XM, EXx, Ib }, 0 },
11326 /* VEX_W_0F3A06_P_2 */
11327 { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 },
11330 /* VEX_W_0F3A08_P_2 */
11331 { "vroundps", { XM, EXx, Ib }, 0 },
11334 /* VEX_W_0F3A09_P_2 */
11335 { "vroundpd", { XM, EXx, Ib }, 0 },
11338 /* VEX_W_0F3A0A_P_2 */
11339 { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11342 /* VEX_W_0F3A0B_P_2 */
11343 { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11346 /* VEX_W_0F3A0C_P_2 */
11347 { "vblendps", { XM, Vex, EXx, Ib }, 0 },
11350 /* VEX_W_0F3A0D_P_2 */
11351 { "vblendpd", { XM, Vex, EXx, Ib }, 0 },
11354 /* VEX_W_0F3A0E_P_2 */
11355 { "vpblendw", { XM, Vex, EXx, Ib }, 0 },
11358 /* VEX_W_0F3A0F_P_2 */
11359 { "vpalignr", { XM, Vex, EXx, Ib }, 0 },
11362 /* VEX_W_0F3A14_P_2 */
11363 { "vpextrb", { Edqb, XM, Ib }, 0 },
11366 /* VEX_W_0F3A15_P_2 */
11367 { "vpextrw", { Edqw, XM, Ib }, 0 },
11370 /* VEX_W_0F3A18_P_2 */
11371 { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 },
11374 /* VEX_W_0F3A19_P_2 */
11375 { "vextractf128", { EXxmm, XM, Ib }, 0 },
11378 /* VEX_W_0F3A20_P_2 */
11379 { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 },
11382 /* VEX_W_0F3A21_P_2 */
11383 { "vinsertps", { XM, Vex128, EXd, Ib }, 0 },
11386 /* VEX_W_0F3A30_P_2_LEN_0 */
11387 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
11388 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
11391 /* VEX_W_0F3A31_P_2_LEN_0 */
11392 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
11393 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
11396 /* VEX_W_0F3A32_P_2_LEN_0 */
11397 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
11398 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
11401 /* VEX_W_0F3A33_P_2_LEN_0 */
11402 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
11403 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
11406 /* VEX_W_0F3A38_P_2 */
11407 { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 },
11410 /* VEX_W_0F3A39_P_2 */
11411 { "vextracti128", { EXxmm, XM, Ib }, 0 },
11414 /* VEX_W_0F3A40_P_2 */
11415 { "vdpps", { XM, Vex, EXx, Ib }, 0 },
11418 /* VEX_W_0F3A41_P_2 */
11419 { "vdppd", { XM, Vex128, EXx, Ib }, 0 },
11422 /* VEX_W_0F3A42_P_2 */
11423 { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 },
11426 /* VEX_W_0F3A46_P_2 */
11427 { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 },
11430 /* VEX_W_0F3A48_P_2 */
11431 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11432 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11435 /* VEX_W_0F3A49_P_2 */
11436 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11437 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11440 /* VEX_W_0F3A4A_P_2 */
11441 { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 },
11444 /* VEX_W_0F3A4B_P_2 */
11445 { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 },
11448 /* VEX_W_0F3A4C_P_2 */
11449 { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 },
11452 /* VEX_W_0F3A62_P_2 */
11453 { "vpcmpistrm", { XM, EXx, Ib }, 0 },
11456 /* VEX_W_0F3A63_P_2 */
11457 { "vpcmpistri", { XM, EXx, Ib }, 0 },
11460 /* VEX_W_0F3ACE_P_2 */
11462 { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
11465 /* VEX_W_0F3ACF_P_2 */
11467 { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, 0 },
11470 /* VEX_W_0F3ADF_P_2 */
11471 { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11473 #define NEED_VEX_W_TABLE
11474 #include "i386-dis-evex.h"
11475 #undef NEED_VEX_W_TABLE
11478 static const struct dis386 mod_table[][2] = {
11481 { "leaS", { Gv, M }, 0 },
11486 { RM_TABLE (RM_C6_REG_7) },
11491 { RM_TABLE (RM_C7_REG_7) },
11495 { "Jcall^", { indirEp }, 0 },
11499 { "Jjmp^", { indirEp }, 0 },
11502 /* MOD_0F01_REG_0 */
11503 { X86_64_TABLE (X86_64_0F01_REG_0) },
11504 { RM_TABLE (RM_0F01_REG_0) },
11507 /* MOD_0F01_REG_1 */
11508 { X86_64_TABLE (X86_64_0F01_REG_1) },
11509 { RM_TABLE (RM_0F01_REG_1) },
11512 /* MOD_0F01_REG_2 */
11513 { X86_64_TABLE (X86_64_0F01_REG_2) },
11514 { RM_TABLE (RM_0F01_REG_2) },
11517 /* MOD_0F01_REG_3 */
11518 { X86_64_TABLE (X86_64_0F01_REG_3) },
11519 { RM_TABLE (RM_0F01_REG_3) },
11522 /* MOD_0F01_REG_5 */
11523 { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
11524 { RM_TABLE (RM_0F01_REG_5) },
11527 /* MOD_0F01_REG_7 */
11528 { "invlpg", { Mb }, 0 },
11529 { RM_TABLE (RM_0F01_REG_7) },
11532 /* MOD_0F12_PREFIX_0 */
11533 { "movlps", { XM, EXq }, PREFIX_OPCODE },
11534 { "movhlps", { XM, EXq }, PREFIX_OPCODE },
11538 { "movlpX", { EXq, XM }, PREFIX_OPCODE },
11541 /* MOD_0F16_PREFIX_0 */
11542 { "movhps", { XM, EXq }, 0 },
11543 { "movlhps", { XM, EXq }, 0 },
11547 { "movhpX", { EXq, XM }, PREFIX_OPCODE },
11550 /* MOD_0F18_REG_0 */
11551 { "prefetchnta", { Mb }, 0 },
11554 /* MOD_0F18_REG_1 */
11555 { "prefetcht0", { Mb }, 0 },
11558 /* MOD_0F18_REG_2 */
11559 { "prefetcht1", { Mb }, 0 },
11562 /* MOD_0F18_REG_3 */
11563 { "prefetcht2", { Mb }, 0 },
11566 /* MOD_0F18_REG_4 */
11567 { "nop/reserved", { Mb }, 0 },
11570 /* MOD_0F18_REG_5 */
11571 { "nop/reserved", { Mb }, 0 },
11574 /* MOD_0F18_REG_6 */
11575 { "nop/reserved", { Mb }, 0 },
11578 /* MOD_0F18_REG_7 */
11579 { "nop/reserved", { Mb }, 0 },
11582 /* MOD_0F1A_PREFIX_0 */
11583 { "bndldx", { Gbnd, Ev_bnd }, 0 },
11584 { "nopQ", { Ev }, 0 },
11587 /* MOD_0F1B_PREFIX_0 */
11588 { "bndstx", { Ev_bnd, Gbnd }, 0 },
11589 { "nopQ", { Ev }, 0 },
11592 /* MOD_0F1B_PREFIX_1 */
11593 { "bndmk", { Gbnd, Ev_bnd }, 0 },
11594 { "nopQ", { Ev }, 0 },
11597 /* MOD_0F1E_PREFIX_1 */
11598 { "nopQ", { Ev }, 0 },
11599 { REG_TABLE (REG_0F1E_MOD_3) },
11604 { "movL", { Rd, Td }, 0 },
11609 { "movL", { Td, Rd }, 0 },
11612 /* MOD_0F2B_PREFIX_0 */
11613 {"movntps", { Mx, XM }, PREFIX_OPCODE },
11616 /* MOD_0F2B_PREFIX_1 */
11617 {"movntss", { Md, XM }, PREFIX_OPCODE },
11620 /* MOD_0F2B_PREFIX_2 */
11621 {"movntpd", { Mx, XM }, PREFIX_OPCODE },
11624 /* MOD_0F2B_PREFIX_3 */
11625 {"movntsd", { Mq, XM }, PREFIX_OPCODE },
11630 { "movmskpX", { Gdq, XS }, PREFIX_OPCODE },
11633 /* MOD_0F71_REG_2 */
11635 { "psrlw", { MS, Ib }, 0 },
11638 /* MOD_0F71_REG_4 */
11640 { "psraw", { MS, Ib }, 0 },
11643 /* MOD_0F71_REG_6 */
11645 { "psllw", { MS, Ib }, 0 },
11648 /* MOD_0F72_REG_2 */
11650 { "psrld", { MS, Ib }, 0 },
11653 /* MOD_0F72_REG_4 */
11655 { "psrad", { MS, Ib }, 0 },
11658 /* MOD_0F72_REG_6 */
11660 { "pslld", { MS, Ib }, 0 },
11663 /* MOD_0F73_REG_2 */
11665 { "psrlq", { MS, Ib }, 0 },
11668 /* MOD_0F73_REG_3 */
11670 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11673 /* MOD_0F73_REG_6 */
11675 { "psllq", { MS, Ib }, 0 },
11678 /* MOD_0F73_REG_7 */
11680 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11683 /* MOD_0FAE_REG_0 */
11684 { "fxsave", { FXSAVE }, 0 },
11685 { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11688 /* MOD_0FAE_REG_1 */
11689 { "fxrstor", { FXSAVE }, 0 },
11690 { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11693 /* MOD_0FAE_REG_2 */
11694 { "ldmxcsr", { Md }, 0 },
11695 { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11698 /* MOD_0FAE_REG_3 */
11699 { "stmxcsr", { Md }, 0 },
11700 { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11703 /* MOD_0FAE_REG_4 */
11704 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
11705 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
11708 /* MOD_0FAE_REG_5 */
11709 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
11710 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
11713 /* MOD_0FAE_REG_6 */
11714 { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
11715 { RM_TABLE (RM_0FAE_REG_6) },
11718 /* MOD_0FAE_REG_7 */
11719 { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11720 { RM_TABLE (RM_0FAE_REG_7) },
11724 { "lssS", { Gv, Mp }, 0 },
11728 { "lfsS", { Gv, Mp }, 0 },
11732 { "lgsS", { Gv, Mp }, 0 },
11736 { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
11739 /* MOD_0FC7_REG_3 */
11740 { "xrstors", { FXSAVE }, 0 },
11743 /* MOD_0FC7_REG_4 */
11744 { "xsavec", { FXSAVE }, 0 },
11747 /* MOD_0FC7_REG_5 */
11748 { "xsaves", { FXSAVE }, 0 },
11751 /* MOD_0FC7_REG_6 */
11752 { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11753 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11756 /* MOD_0FC7_REG_7 */
11757 { "vmptrst", { Mq }, 0 },
11758 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11763 { "pmovmskb", { Gdq, MS }, 0 },
11766 /* MOD_0FE7_PREFIX_2 */
11767 { "movntdq", { Mx, XM }, 0 },
11770 /* MOD_0FF0_PREFIX_3 */
11771 { "lddqu", { XM, M }, 0 },
11774 /* MOD_0F382A_PREFIX_2 */
11775 { "movntdqa", { XM, Mx }, 0 },
11778 /* MOD_0F38F5_PREFIX_2 */
11779 { "wrussK", { M, Gdq }, PREFIX_OPCODE },
11782 /* MOD_0F38F6_PREFIX_0 */
11783 { "wrssK", { M, Gdq }, PREFIX_OPCODE },
11787 { "bound{S|}", { Gv, Ma }, 0 },
11788 { EVEX_TABLE (EVEX_0F) },
11792 { "lesS", { Gv, Mp }, 0 },
11793 { VEX_C4_TABLE (VEX_0F) },
11797 { "ldsS", { Gv, Mp }, 0 },
11798 { VEX_C5_TABLE (VEX_0F) },
11801 /* MOD_VEX_0F12_PREFIX_0 */
11802 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11803 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11807 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11810 /* MOD_VEX_0F16_PREFIX_0 */
11811 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11812 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11816 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11820 { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11823 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11825 { "kandw", { MaskG, MaskVex, MaskR }, 0 },
11828 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11830 { "kandq", { MaskG, MaskVex, MaskR }, 0 },
11833 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11835 { "kandb", { MaskG, MaskVex, MaskR }, 0 },
11838 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11840 { "kandd", { MaskG, MaskVex, MaskR }, 0 },
11843 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11845 { "kandnw", { MaskG, MaskVex, MaskR }, 0 },
11848 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11850 { "kandnq", { MaskG, MaskVex, MaskR }, 0 },
11853 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11855 { "kandnb", { MaskG, MaskVex, MaskR }, 0 },
11858 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11860 { "kandnd", { MaskG, MaskVex, MaskR }, 0 },
11863 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11865 { "knotw", { MaskG, MaskR }, 0 },
11868 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11870 { "knotq", { MaskG, MaskR }, 0 },
11873 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11875 { "knotb", { MaskG, MaskR }, 0 },
11878 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11880 { "knotd", { MaskG, MaskR }, 0 },
11883 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11885 { "korw", { MaskG, MaskVex, MaskR }, 0 },
11888 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11890 { "korq", { MaskG, MaskVex, MaskR }, 0 },
11893 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11895 { "korb", { MaskG, MaskVex, MaskR }, 0 },
11898 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11900 { "kord", { MaskG, MaskVex, MaskR }, 0 },
11903 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11905 { "kxnorw", { MaskG, MaskVex, MaskR }, 0 },
11908 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11910 { "kxnorq", { MaskG, MaskVex, MaskR }, 0 },
11913 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
11915 { "kxnorb", { MaskG, MaskVex, MaskR }, 0 },
11918 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
11920 { "kxnord", { MaskG, MaskVex, MaskR }, 0 },
11923 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
11925 { "kxorw", { MaskG, MaskVex, MaskR }, 0 },
11928 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
11930 { "kxorq", { MaskG, MaskVex, MaskR }, 0 },
11933 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
11935 { "kxorb", { MaskG, MaskVex, MaskR }, 0 },
11938 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
11940 { "kxord", { MaskG, MaskVex, MaskR }, 0 },
11943 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
11945 { "kaddw", { MaskG, MaskVex, MaskR }, 0 },
11948 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
11950 { "kaddq", { MaskG, MaskVex, MaskR }, 0 },
11953 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
11955 { "kaddb", { MaskG, MaskVex, MaskR }, 0 },
11958 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
11960 { "kaddd", { MaskG, MaskVex, MaskR }, 0 },
11963 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
11965 { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 },
11968 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
11970 { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 },
11973 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
11975 { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 },
11980 { VEX_W_TABLE (VEX_W_0F50_M_0) },
11983 /* MOD_VEX_0F71_REG_2 */
11985 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
11988 /* MOD_VEX_0F71_REG_4 */
11990 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
11993 /* MOD_VEX_0F71_REG_6 */
11995 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
11998 /* MOD_VEX_0F72_REG_2 */
12000 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
12003 /* MOD_VEX_0F72_REG_4 */
12005 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
12008 /* MOD_VEX_0F72_REG_6 */
12010 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
12013 /* MOD_VEX_0F73_REG_2 */
12015 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
12018 /* MOD_VEX_0F73_REG_3 */
12020 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
12023 /* MOD_VEX_0F73_REG_6 */
12025 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
12028 /* MOD_VEX_0F73_REG_7 */
12030 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
12033 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12034 { "kmovw", { Ew, MaskG }, 0 },
12038 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12039 { "kmovq", { Eq, MaskG }, 0 },
12043 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12044 { "kmovb", { Eb, MaskG }, 0 },
12048 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12049 { "kmovd", { Ed, MaskG }, 0 },
12053 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
12055 { "kmovw", { MaskG, Rdq }, 0 },
12058 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
12060 { "kmovb", { MaskG, Rdq }, 0 },
12063 /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
12065 { "kmovd", { MaskG, Rdq }, 0 },
12068 /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
12070 { "kmovq", { MaskG, Rdq }, 0 },
12073 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
12075 { "kmovw", { Gdq, MaskR }, 0 },
12078 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
12080 { "kmovb", { Gdq, MaskR }, 0 },
12083 /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
12085 { "kmovd", { Gdq, MaskR }, 0 },
12088 /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
12090 { "kmovq", { Gdq, MaskR }, 0 },
12093 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
12095 { "kortestw", { MaskG, MaskR }, 0 },
12098 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
12100 { "kortestq", { MaskG, MaskR }, 0 },
12103 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
12105 { "kortestb", { MaskG, MaskR }, 0 },
12108 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
12110 { "kortestd", { MaskG, MaskR }, 0 },
12113 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
12115 { "ktestw", { MaskG, MaskR }, 0 },
12118 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12120 { "ktestq", { MaskG, MaskR }, 0 },
12123 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12125 { "ktestb", { MaskG, MaskR }, 0 },
12128 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12130 { "ktestd", { MaskG, MaskR }, 0 },
12133 /* MOD_VEX_0FAE_REG_2 */
12134 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
12137 /* MOD_VEX_0FAE_REG_3 */
12138 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
12141 /* MOD_VEX_0FD7_PREFIX_2 */
12143 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
12146 /* MOD_VEX_0FE7_PREFIX_2 */
12147 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
12150 /* MOD_VEX_0FF0_PREFIX_3 */
12151 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
12154 /* MOD_VEX_0F381A_PREFIX_2 */
12155 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
12158 /* MOD_VEX_0F382A_PREFIX_2 */
12159 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
12162 /* MOD_VEX_0F382C_PREFIX_2 */
12163 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
12166 /* MOD_VEX_0F382D_PREFIX_2 */
12167 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
12170 /* MOD_VEX_0F382E_PREFIX_2 */
12171 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
12174 /* MOD_VEX_0F382F_PREFIX_2 */
12175 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
12178 /* MOD_VEX_0F385A_PREFIX_2 */
12179 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
12182 /* MOD_VEX_0F388C_PREFIX_2 */
12183 { "vpmaskmov%LW", { XM, Vex, Mx }, 0 },
12186 /* MOD_VEX_0F388E_PREFIX_2 */
12187 { "vpmaskmov%LW", { Mx, Vex, XM }, 0 },
12190 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12192 { "kshiftrb", { MaskG, MaskR, Ib }, 0 },
12195 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12197 { "kshiftrw", { MaskG, MaskR, Ib }, 0 },
12200 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12202 { "kshiftrd", { MaskG, MaskR, Ib }, 0 },
12205 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12207 { "kshiftrq", { MaskG, MaskR, Ib }, 0 },
12210 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12212 { "kshiftlb", { MaskG, MaskR, Ib }, 0 },
12215 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12217 { "kshiftlw", { MaskG, MaskR, Ib }, 0 },
12220 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12222 { "kshiftld", { MaskG, MaskR, Ib }, 0 },
12225 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12227 { "kshiftlq", { MaskG, MaskR, Ib }, 0 },
12229 #define NEED_MOD_TABLE
12230 #include "i386-dis-evex.h"
12231 #undef NEED_MOD_TABLE
12234 static const struct dis386 rm_table[][8] = {
12237 { "xabort", { Skip_MODRM, Ib }, 0 },
12241 { "xbeginT", { Skip_MODRM, Jv }, 0 },
12244 /* RM_0F01_REG_0 */
12246 { "vmcall", { Skip_MODRM }, 0 },
12247 { "vmlaunch", { Skip_MODRM }, 0 },
12248 { "vmresume", { Skip_MODRM }, 0 },
12249 { "vmxoff", { Skip_MODRM }, 0 },
12252 /* RM_0F01_REG_1 */
12253 { "monitor", { { OP_Monitor, 0 } }, 0 },
12254 { "mwait", { { OP_Mwait, 0 } }, 0 },
12255 { "clac", { Skip_MODRM }, 0 },
12256 { "stac", { Skip_MODRM }, 0 },
12260 { "encls", { Skip_MODRM }, 0 },
12263 /* RM_0F01_REG_2 */
12264 { "xgetbv", { Skip_MODRM }, 0 },
12265 { "xsetbv", { Skip_MODRM }, 0 },
12268 { "vmfunc", { Skip_MODRM }, 0 },
12269 { "xend", { Skip_MODRM }, 0 },
12270 { "xtest", { Skip_MODRM }, 0 },
12271 { "enclu", { Skip_MODRM }, 0 },
12274 /* RM_0F01_REG_3 */
12275 { "vmrun", { Skip_MODRM }, 0 },
12276 { "vmmcall", { Skip_MODRM }, 0 },
12277 { "vmload", { Skip_MODRM }, 0 },
12278 { "vmsave", { Skip_MODRM }, 0 },
12279 { "stgi", { Skip_MODRM }, 0 },
12280 { "clgi", { Skip_MODRM }, 0 },
12281 { "skinit", { Skip_MODRM }, 0 },
12282 { "invlpga", { Skip_MODRM }, 0 },
12285 /* RM_0F01_REG_5 */
12286 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
12288 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
12292 { "rdpkru", { Skip_MODRM }, 0 },
12293 { "wrpkru", { Skip_MODRM }, 0 },
12296 /* RM_0F01_REG_7 */
12297 { "swapgs", { Skip_MODRM }, 0 },
12298 { "rdtscp", { Skip_MODRM }, 0 },
12299 { "monitorx", { { OP_Monitor, 0 } }, 0 },
12300 { "mwaitx", { { OP_Mwaitx, 0 } }, 0 },
12301 { "clzero", { Skip_MODRM }, 0 },
12304 /* RM_0F1E_MOD_3_REG_7 */
12305 { "nopQ", { Ev }, 0 },
12306 { "nopQ", { Ev }, 0 },
12307 { "endbr64", { Skip_MODRM }, PREFIX_OPCODE },
12308 { "endbr32", { Skip_MODRM }, PREFIX_OPCODE },
12309 { "nopQ", { Ev }, 0 },
12310 { "nopQ", { Ev }, 0 },
12311 { "nopQ", { Ev }, 0 },
12312 { "nopQ", { Ev }, 0 },
12315 /* RM_0FAE_REG_6 */
12316 { "mfence", { Skip_MODRM }, 0 },
12319 /* RM_0FAE_REG_7 */
12320 { "sfence", { Skip_MODRM }, 0 },
12325 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12327 /* We use the high bit to indicate different name for the same
12329 #define REP_PREFIX (0xf3 | 0x100)
12330 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12331 #define XRELEASE_PREFIX (0xf3 | 0x400)
12332 #define BND_PREFIX (0xf2 | 0x400)
12333 #define NOTRACK_PREFIX (0x3e | 0x100)
12338 int newrex, i, length;
12344 last_lock_prefix = -1;
12345 last_repz_prefix = -1;
12346 last_repnz_prefix = -1;
12347 last_data_prefix = -1;
12348 last_addr_prefix = -1;
12349 last_rex_prefix = -1;
12350 last_seg_prefix = -1;
12352 active_seg_prefix = 0;
12353 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12354 all_prefixes[i] = 0;
12357 /* The maximum instruction length is 15bytes. */
12358 while (length < MAX_CODE_LENGTH - 1)
12360 FETCH_DATA (the_info, codep + 1);
12364 /* REX prefixes family. */
12381 if (address_mode == mode_64bit)
12385 last_rex_prefix = i;
12388 prefixes |= PREFIX_REPZ;
12389 last_repz_prefix = i;
12392 prefixes |= PREFIX_REPNZ;
12393 last_repnz_prefix = i;
12396 prefixes |= PREFIX_LOCK;
12397 last_lock_prefix = i;
12400 prefixes |= PREFIX_CS;
12401 last_seg_prefix = i;
12402 active_seg_prefix = PREFIX_CS;
12405 prefixes |= PREFIX_SS;
12406 last_seg_prefix = i;
12407 active_seg_prefix = PREFIX_SS;
12410 prefixes |= PREFIX_DS;
12411 last_seg_prefix = i;
12412 active_seg_prefix = PREFIX_DS;
12415 prefixes |= PREFIX_ES;
12416 last_seg_prefix = i;
12417 active_seg_prefix = PREFIX_ES;
12420 prefixes |= PREFIX_FS;
12421 last_seg_prefix = i;
12422 active_seg_prefix = PREFIX_FS;
12425 prefixes |= PREFIX_GS;
12426 last_seg_prefix = i;
12427 active_seg_prefix = PREFIX_GS;
12430 prefixes |= PREFIX_DATA;
12431 last_data_prefix = i;
12434 prefixes |= PREFIX_ADDR;
12435 last_addr_prefix = i;
12438 /* fwait is really an instruction. If there are prefixes
12439 before the fwait, they belong to the fwait, *not* to the
12440 following instruction. */
12442 if (prefixes || rex)
12444 prefixes |= PREFIX_FWAIT;
12446 /* This ensures that the previous REX prefixes are noticed
12447 as unused prefixes, as in the return case below. */
12451 prefixes = PREFIX_FWAIT;
12456 /* Rex is ignored when followed by another prefix. */
12462 if (*codep != FWAIT_OPCODE)
12463 all_prefixes[i++] = *codep;
12471 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12474 static const char *
12475 prefix_name (int pref, int sizeflag)
12477 static const char *rexes [16] =
12480 "rex.B", /* 0x41 */
12481 "rex.X", /* 0x42 */
12482 "rex.XB", /* 0x43 */
12483 "rex.R", /* 0x44 */
12484 "rex.RB", /* 0x45 */
12485 "rex.RX", /* 0x46 */
12486 "rex.RXB", /* 0x47 */
12487 "rex.W", /* 0x48 */
12488 "rex.WB", /* 0x49 */
12489 "rex.WX", /* 0x4a */
12490 "rex.WXB", /* 0x4b */
12491 "rex.WR", /* 0x4c */
12492 "rex.WRB", /* 0x4d */
12493 "rex.WRX", /* 0x4e */
12494 "rex.WRXB", /* 0x4f */
12499 /* REX prefixes family. */
12516 return rexes [pref - 0x40];
12536 return (sizeflag & DFLAG) ? "data16" : "data32";
12538 if (address_mode == mode_64bit)
12539 return (sizeflag & AFLAG) ? "addr32" : "addr64";
12541 return (sizeflag & AFLAG) ? "addr16" : "addr32";
12546 case XACQUIRE_PREFIX:
12548 case XRELEASE_PREFIX:
12552 case NOTRACK_PREFIX:
12559 static char op_out[MAX_OPERANDS][100];
12560 static int op_ad, op_index[MAX_OPERANDS];
12561 static int two_source_ops;
12562 static bfd_vma op_address[MAX_OPERANDS];
12563 static bfd_vma op_riprel[MAX_OPERANDS];
12564 static bfd_vma start_pc;
12567 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12568 * (see topic "Redundant prefixes" in the "Differences from 8086"
12569 * section of the "Virtual 8086 Mode" chapter.)
12570 * 'pc' should be the address of this instruction, it will
12571 * be used to print the target address if this is a relative jump or call
12572 * The function returns the length of this instruction in bytes.
12575 static char intel_syntax;
12576 static char intel_mnemonic = !SYSV386_COMPAT;
12577 static char open_char;
12578 static char close_char;
12579 static char separator_char;
12580 static char scale_char;
12588 static enum x86_64_isa isa64;
12590 /* Here for backwards compatibility. When gdb stops using
12591 print_insn_i386_att and print_insn_i386_intel these functions can
12592 disappear, and print_insn_i386 be merged into print_insn. */
12594 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12598 return print_insn (pc, info);
12602 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12606 return print_insn (pc, info);
12610 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12614 return print_insn (pc, info);
12618 print_i386_disassembler_options (FILE *stream)
12620 fprintf (stream, _("\n\
12621 The following i386/x86-64 specific disassembler options are supported for use\n\
12622 with the -M switch (multiple options should be separated by commas):\n"));
12624 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
12625 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
12626 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
12627 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
12628 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
12629 fprintf (stream, _(" att-mnemonic\n"
12630 " Display instruction in AT&T mnemonic\n"));
12631 fprintf (stream, _(" intel-mnemonic\n"
12632 " Display instruction in Intel mnemonic\n"));
12633 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
12634 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
12635 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
12636 fprintf (stream, _(" data32 Assume 32bit data size\n"));
12637 fprintf (stream, _(" data16 Assume 16bit data size\n"));
12638 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
12639 fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n"));
12640 fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n"));
12644 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12646 /* Get a pointer to struct dis386 with a valid name. */
12648 static const struct dis386 *
12649 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12651 int vindex, vex_table_index;
12653 if (dp->name != NULL)
12656 switch (dp->op[0].bytemode)
12658 case USE_REG_TABLE:
12659 dp = ®_table[dp->op[1].bytemode][modrm.reg];
12662 case USE_MOD_TABLE:
12663 vindex = modrm.mod == 0x3 ? 1 : 0;
12664 dp = &mod_table[dp->op[1].bytemode][vindex];
12668 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12671 case USE_PREFIX_TABLE:
12674 /* The prefix in VEX is implicit. */
12675 switch (vex.prefix)
12680 case REPE_PREFIX_OPCODE:
12683 case DATA_PREFIX_OPCODE:
12686 case REPNE_PREFIX_OPCODE:
12696 int last_prefix = -1;
12699 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12700 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12702 if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12704 if (last_repz_prefix > last_repnz_prefix)
12707 prefix = PREFIX_REPZ;
12708 last_prefix = last_repz_prefix;
12713 prefix = PREFIX_REPNZ;
12714 last_prefix = last_repnz_prefix;
12717 /* Check if prefix should be ignored. */
12718 if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12719 & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12724 if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12727 prefix = PREFIX_DATA;
12728 last_prefix = last_data_prefix;
12733 used_prefixes |= prefix;
12734 all_prefixes[last_prefix] = 0;
12737 dp = &prefix_table[dp->op[1].bytemode][vindex];
12740 case USE_X86_64_TABLE:
12741 vindex = address_mode == mode_64bit ? 1 : 0;
12742 dp = &x86_64_table[dp->op[1].bytemode][vindex];
12745 case USE_3BYTE_TABLE:
12746 FETCH_DATA (info, codep + 2);
12748 dp = &three_byte_table[dp->op[1].bytemode][vindex];
12750 modrm.mod = (*codep >> 6) & 3;
12751 modrm.reg = (*codep >> 3) & 7;
12752 modrm.rm = *codep & 7;
12755 case USE_VEX_LEN_TABLE:
12759 switch (vex.length)
12772 dp = &vex_len_table[dp->op[1].bytemode][vindex];
12775 case USE_XOP_8F_TABLE:
12776 FETCH_DATA (info, codep + 3);
12777 /* All bits in the REX prefix are ignored. */
12779 rex = ~(*codep >> 5) & 0x7;
12781 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
12782 switch ((*codep & 0x1f))
12788 vex_table_index = XOP_08;
12791 vex_table_index = XOP_09;
12794 vex_table_index = XOP_0A;
12798 vex.w = *codep & 0x80;
12799 if (vex.w && address_mode == mode_64bit)
12802 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12803 if (address_mode != mode_64bit)
12805 /* In 16/32-bit mode REX_B is silently ignored. */
12807 if (vex.register_specifier > 0x7)
12814 vex.length = (*codep & 0x4) ? 256 : 128;
12815 switch ((*codep & 0x3))
12821 vex.prefix = DATA_PREFIX_OPCODE;
12824 vex.prefix = REPE_PREFIX_OPCODE;
12827 vex.prefix = REPNE_PREFIX_OPCODE;
12834 dp = &xop_table[vex_table_index][vindex];
12837 FETCH_DATA (info, codep + 1);
12838 modrm.mod = (*codep >> 6) & 3;
12839 modrm.reg = (*codep >> 3) & 7;
12840 modrm.rm = *codep & 7;
12843 case USE_VEX_C4_TABLE:
12845 FETCH_DATA (info, codep + 3);
12846 /* All bits in the REX prefix are ignored. */
12848 rex = ~(*codep >> 5) & 0x7;
12849 switch ((*codep & 0x1f))
12855 vex_table_index = VEX_0F;
12858 vex_table_index = VEX_0F38;
12861 vex_table_index = VEX_0F3A;
12865 vex.w = *codep & 0x80;
12866 if (address_mode == mode_64bit)
12870 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12874 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12875 is ignored, other REX bits are 0 and the highest bit in
12876 VEX.vvvv is also ignored. */
12878 vex.register_specifier = (~(*codep >> 3)) & 0x7;
12880 vex.length = (*codep & 0x4) ? 256 : 128;
12881 switch ((*codep & 0x3))
12887 vex.prefix = DATA_PREFIX_OPCODE;
12890 vex.prefix = REPE_PREFIX_OPCODE;
12893 vex.prefix = REPNE_PREFIX_OPCODE;
12900 dp = &vex_table[vex_table_index][vindex];
12902 /* There is no MODRM byte for VEX0F 77. */
12903 if (vex_table_index != VEX_0F || vindex != 0x77)
12905 FETCH_DATA (info, codep + 1);
12906 modrm.mod = (*codep >> 6) & 3;
12907 modrm.reg = (*codep >> 3) & 7;
12908 modrm.rm = *codep & 7;
12912 case USE_VEX_C5_TABLE:
12914 FETCH_DATA (info, codep + 2);
12915 /* All bits in the REX prefix are ignored. */
12917 rex = (*codep & 0x80) ? 0 : REX_R;
12919 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
12921 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12923 vex.length = (*codep & 0x4) ? 256 : 128;
12924 switch ((*codep & 0x3))
12930 vex.prefix = DATA_PREFIX_OPCODE;
12933 vex.prefix = REPE_PREFIX_OPCODE;
12936 vex.prefix = REPNE_PREFIX_OPCODE;
12943 dp = &vex_table[dp->op[1].bytemode][vindex];
12945 /* There is no MODRM byte for VEX 77. */
12946 if (vindex != 0x77)
12948 FETCH_DATA (info, codep + 1);
12949 modrm.mod = (*codep >> 6) & 3;
12950 modrm.reg = (*codep >> 3) & 7;
12951 modrm.rm = *codep & 7;
12955 case USE_VEX_W_TABLE:
12959 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
12962 case USE_EVEX_TABLE:
12963 two_source_ops = 0;
12966 FETCH_DATA (info, codep + 4);
12967 /* All bits in the REX prefix are ignored. */
12969 /* The first byte after 0x62. */
12970 rex = ~(*codep >> 5) & 0x7;
12971 vex.r = *codep & 0x10;
12972 switch ((*codep & 0xf))
12975 return &bad_opcode;
12977 vex_table_index = EVEX_0F;
12980 vex_table_index = EVEX_0F38;
12983 vex_table_index = EVEX_0F3A;
12987 /* The second byte after 0x62. */
12989 vex.w = *codep & 0x80;
12990 if (vex.w && address_mode == mode_64bit)
12993 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12994 if (address_mode != mode_64bit)
12996 /* In 16/32-bit mode silently ignore following bits. */
13000 vex.register_specifier &= 0x7;
13004 if (!(*codep & 0x4))
13005 return &bad_opcode;
13007 switch ((*codep & 0x3))
13013 vex.prefix = DATA_PREFIX_OPCODE;
13016 vex.prefix = REPE_PREFIX_OPCODE;
13019 vex.prefix = REPNE_PREFIX_OPCODE;
13023 /* The third byte after 0x62. */
13026 /* Remember the static rounding bits. */
13027 vex.ll = (*codep >> 5) & 3;
13028 vex.b = (*codep & 0x10) != 0;
13030 vex.v = *codep & 0x8;
13031 vex.mask_register_specifier = *codep & 0x7;
13032 vex.zeroing = *codep & 0x80;
13038 dp = &evex_table[vex_table_index][vindex];
13040 FETCH_DATA (info, codep + 1);
13041 modrm.mod = (*codep >> 6) & 3;
13042 modrm.reg = (*codep >> 3) & 7;
13043 modrm.rm = *codep & 7;
13045 /* Set vector length. */
13046 if (modrm.mod == 3 && vex.b)
13062 return &bad_opcode;
13075 if (dp->name != NULL)
13078 return get_valid_dis386 (dp, info);
13082 get_sib (disassemble_info *info, int sizeflag)
13084 /* If modrm.mod == 3, operand must be register. */
13086 && ((sizeflag & AFLAG) || address_mode == mode_64bit)
13090 FETCH_DATA (info, codep + 2);
13091 sib.index = (codep [1] >> 3) & 7;
13092 sib.scale = (codep [1] >> 6) & 3;
13093 sib.base = codep [1] & 7;
13098 print_insn (bfd_vma pc, disassemble_info *info)
13100 const struct dis386 *dp;
13102 char *op_txt[MAX_OPERANDS];
13104 int sizeflag, orig_sizeflag;
13106 struct dis_private priv;
13109 priv.orig_sizeflag = AFLAG | DFLAG;
13110 if ((info->mach & bfd_mach_i386_i386) != 0)
13111 address_mode = mode_32bit;
13112 else if (info->mach == bfd_mach_i386_i8086)
13114 address_mode = mode_16bit;
13115 priv.orig_sizeflag = 0;
13118 address_mode = mode_64bit;
13120 if (intel_syntax == (char) -1)
13121 intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
13123 for (p = info->disassembler_options; p != NULL; )
13125 if (CONST_STRNEQ (p, "amd64"))
13127 else if (CONST_STRNEQ (p, "intel64"))
13129 else if (CONST_STRNEQ (p, "x86-64"))
13131 address_mode = mode_64bit;
13132 priv.orig_sizeflag = AFLAG | DFLAG;
13134 else if (CONST_STRNEQ (p, "i386"))
13136 address_mode = mode_32bit;
13137 priv.orig_sizeflag = AFLAG | DFLAG;
13139 else if (CONST_STRNEQ (p, "i8086"))
13141 address_mode = mode_16bit;
13142 priv.orig_sizeflag = 0;
13144 else if (CONST_STRNEQ (p, "intel"))
13147 if (CONST_STRNEQ (p + 5, "-mnemonic"))
13148 intel_mnemonic = 1;
13150 else if (CONST_STRNEQ (p, "att"))
13153 if (CONST_STRNEQ (p + 3, "-mnemonic"))
13154 intel_mnemonic = 0;
13156 else if (CONST_STRNEQ (p, "addr"))
13158 if (address_mode == mode_64bit)
13160 if (p[4] == '3' && p[5] == '2')
13161 priv.orig_sizeflag &= ~AFLAG;
13162 else if (p[4] == '6' && p[5] == '4')
13163 priv.orig_sizeflag |= AFLAG;
13167 if (p[4] == '1' && p[5] == '6')
13168 priv.orig_sizeflag &= ~AFLAG;
13169 else if (p[4] == '3' && p[5] == '2')
13170 priv.orig_sizeflag |= AFLAG;
13173 else if (CONST_STRNEQ (p, "data"))
13175 if (p[4] == '1' && p[5] == '6')
13176 priv.orig_sizeflag &= ~DFLAG;
13177 else if (p[4] == '3' && p[5] == '2')
13178 priv.orig_sizeflag |= DFLAG;
13180 else if (CONST_STRNEQ (p, "suffix"))
13181 priv.orig_sizeflag |= SUFFIX_ALWAYS;
13183 p = strchr (p, ',');
13188 if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
13190 (*info->fprintf_func) (info->stream,
13191 _("64-bit address is disabled"));
13197 names64 = intel_names64;
13198 names32 = intel_names32;
13199 names16 = intel_names16;
13200 names8 = intel_names8;
13201 names8rex = intel_names8rex;
13202 names_seg = intel_names_seg;
13203 names_mm = intel_names_mm;
13204 names_bnd = intel_names_bnd;
13205 names_xmm = intel_names_xmm;
13206 names_ymm = intel_names_ymm;
13207 names_zmm = intel_names_zmm;
13208 index64 = intel_index64;
13209 index32 = intel_index32;
13210 names_mask = intel_names_mask;
13211 index16 = intel_index16;
13214 separator_char = '+';
13219 names64 = att_names64;
13220 names32 = att_names32;
13221 names16 = att_names16;
13222 names8 = att_names8;
13223 names8rex = att_names8rex;
13224 names_seg = att_names_seg;
13225 names_mm = att_names_mm;
13226 names_bnd = att_names_bnd;
13227 names_xmm = att_names_xmm;
13228 names_ymm = att_names_ymm;
13229 names_zmm = att_names_zmm;
13230 index64 = att_index64;
13231 index32 = att_index32;
13232 names_mask = att_names_mask;
13233 index16 = att_index16;
13236 separator_char = ',';
13240 /* The output looks better if we put 7 bytes on a line, since that
13241 puts most long word instructions on a single line. Use 8 bytes
13243 if ((info->mach & bfd_mach_l1om) != 0)
13244 info->bytes_per_line = 8;
13246 info->bytes_per_line = 7;
13248 info->private_data = &priv;
13249 priv.max_fetched = priv.the_buffer;
13250 priv.insn_start = pc;
13253 for (i = 0; i < MAX_OPERANDS; ++i)
13261 start_codep = priv.the_buffer;
13262 codep = priv.the_buffer;
13264 if (OPCODES_SIGSETJMP (priv.bailout) != 0)
13268 /* Getting here means we tried for data but didn't get it. That
13269 means we have an incomplete instruction of some sort. Just
13270 print the first byte as a prefix or a .byte pseudo-op. */
13271 if (codep > priv.the_buffer)
13273 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
13275 (*info->fprintf_func) (info->stream, "%s", name);
13278 /* Just print the first byte as a .byte instruction. */
13279 (*info->fprintf_func) (info->stream, ".byte 0x%x",
13280 (unsigned int) priv.the_buffer[0]);
13290 sizeflag = priv.orig_sizeflag;
13292 if (!ckprefix () || rex_used)
13294 /* Too many prefixes or unused REX prefixes. */
13296 i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13298 (*info->fprintf_func) (info->stream, "%s%s",
13300 prefix_name (all_prefixes[i], sizeflag));
13304 insn_codep = codep;
13306 FETCH_DATA (info, codep + 1);
13307 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13309 if (((prefixes & PREFIX_FWAIT)
13310 && ((*codep < 0xd8) || (*codep > 0xdf))))
13312 /* Handle prefixes before fwait. */
13313 for (i = 0; i < fwait_prefix && all_prefixes[i];
13315 (*info->fprintf_func) (info->stream, "%s ",
13316 prefix_name (all_prefixes[i], sizeflag));
13317 (*info->fprintf_func) (info->stream, "fwait");
13321 if (*codep == 0x0f)
13323 unsigned char threebyte;
13326 FETCH_DATA (info, codep + 1);
13327 threebyte = *codep;
13328 dp = &dis386_twobyte[threebyte];
13329 need_modrm = twobyte_has_modrm[*codep];
13334 dp = &dis386[*codep];
13335 need_modrm = onebyte_has_modrm[*codep];
13339 /* Save sizeflag for printing the extra prefixes later before updating
13340 it for mnemonic and operand processing. The prefix names depend
13341 only on the address mode. */
13342 orig_sizeflag = sizeflag;
13343 if (prefixes & PREFIX_ADDR)
13345 if ((prefixes & PREFIX_DATA))
13351 FETCH_DATA (info, codep + 1);
13352 modrm.mod = (*codep >> 6) & 3;
13353 modrm.reg = (*codep >> 3) & 7;
13354 modrm.rm = *codep & 7;
13362 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13364 get_sib (info, sizeflag);
13365 dofloat (sizeflag);
13369 dp = get_valid_dis386 (dp, info);
13370 if (dp != NULL && putop (dp->name, sizeflag) == 0)
13372 get_sib (info, sizeflag);
13373 for (i = 0; i < MAX_OPERANDS; ++i)
13376 op_ad = MAX_OPERANDS - 1 - i;
13378 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13379 /* For EVEX instruction after the last operand masking
13380 should be printed. */
13381 if (i == 0 && vex.evex)
13383 /* Don't print {%k0}. */
13384 if (vex.mask_register_specifier)
13387 oappend (names_mask[vex.mask_register_specifier]);
13397 /* Check if the REX prefix is used. */
13398 if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13399 all_prefixes[last_rex_prefix] = 0;
13401 /* Check if the SEG prefix is used. */
13402 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13403 | PREFIX_FS | PREFIX_GS)) != 0
13404 && (used_prefixes & active_seg_prefix) != 0)
13405 all_prefixes[last_seg_prefix] = 0;
13407 /* Check if the ADDR prefix is used. */
13408 if ((prefixes & PREFIX_ADDR) != 0
13409 && (used_prefixes & PREFIX_ADDR) != 0)
13410 all_prefixes[last_addr_prefix] = 0;
13412 /* Check if the DATA prefix is used. */
13413 if ((prefixes & PREFIX_DATA) != 0
13414 && (used_prefixes & PREFIX_DATA) != 0)
13415 all_prefixes[last_data_prefix] = 0;
13417 /* Print the extra prefixes. */
13419 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13420 if (all_prefixes[i])
13423 name = prefix_name (all_prefixes[i], orig_sizeflag);
13426 prefix_length += strlen (name) + 1;
13427 (*info->fprintf_func) (info->stream, "%s ", name);
13430 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13431 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
13432 used by putop and MMX/SSE operand and may be overriden by the
13433 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13435 if (dp->prefix_requirement == PREFIX_OPCODE
13436 && dp != &bad_opcode
13438 & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13440 & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13442 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13444 && (used_prefixes & PREFIX_DATA) == 0))))
13446 (*info->fprintf_func) (info->stream, "(bad)");
13447 return end_codep - priv.the_buffer;
13450 /* Check maximum code length. */
13451 if ((codep - start_codep) > MAX_CODE_LENGTH)
13453 (*info->fprintf_func) (info->stream, "(bad)");
13454 return MAX_CODE_LENGTH;
13457 obufp = mnemonicendp;
13458 for (i = strlen (obuf) + prefix_length; i < 6; i++)
13461 (*info->fprintf_func) (info->stream, "%s", obuf);
13463 /* The enter and bound instructions are printed with operands in the same
13464 order as the intel book; everything else is printed in reverse order. */
13465 if (intel_syntax || two_source_ops)
13469 for (i = 0; i < MAX_OPERANDS; ++i)
13470 op_txt[i] = op_out[i];
13472 if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
13473 && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
13475 op_txt[2] = op_out[3];
13476 op_txt[3] = op_out[2];
13479 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13481 op_ad = op_index[i];
13482 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13483 op_index[MAX_OPERANDS - 1 - i] = op_ad;
13484 riprel = op_riprel[i];
13485 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13486 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13491 for (i = 0; i < MAX_OPERANDS; ++i)
13492 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13496 for (i = 0; i < MAX_OPERANDS; ++i)
13500 (*info->fprintf_func) (info->stream, ",");
13501 if (op_index[i] != -1 && !op_riprel[i])
13502 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13504 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13508 for (i = 0; i < MAX_OPERANDS; i++)
13509 if (op_index[i] != -1 && op_riprel[i])
13511 (*info->fprintf_func) (info->stream, " # ");
13512 (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
13513 + op_address[op_index[i]]), info);
13516 return codep - priv.the_buffer;
13519 static const char *float_mem[] = {
13594 static const unsigned char float_mem_mode[] = {
13669 #define ST { OP_ST, 0 }
13670 #define STi { OP_STi, 0 }
13672 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13673 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13674 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13675 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13676 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13677 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
13678 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13679 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
13680 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13682 static const struct dis386 float_reg[][8] = {
13685 { "fadd", { ST, STi }, 0 },
13686 { "fmul", { ST, STi }, 0 },
13687 { "fcom", { STi }, 0 },
13688 { "fcomp", { STi }, 0 },
13689 { "fsub", { ST, STi }, 0 },
13690 { "fsubr", { ST, STi }, 0 },
13691 { "fdiv", { ST, STi }, 0 },
13692 { "fdivr", { ST, STi }, 0 },
13696 { "fld", { STi }, 0 },
13697 { "fxch", { STi }, 0 },
13707 { "fcmovb", { ST, STi }, 0 },
13708 { "fcmove", { ST, STi }, 0 },
13709 { "fcmovbe",{ ST, STi }, 0 },
13710 { "fcmovu", { ST, STi }, 0 },
13718 { "fcmovnb",{ ST, STi }, 0 },
13719 { "fcmovne",{ ST, STi }, 0 },
13720 { "fcmovnbe",{ ST, STi }, 0 },
13721 { "fcmovnu",{ ST, STi }, 0 },
13723 { "fucomi", { ST, STi }, 0 },
13724 { "fcomi", { ST, STi }, 0 },
13729 { "fadd", { STi, ST }, 0 },
13730 { "fmul", { STi, ST }, 0 },
13733 { "fsub!M", { STi, ST }, 0 },
13734 { "fsubM", { STi, ST }, 0 },
13735 { "fdiv!M", { STi, ST }, 0 },
13736 { "fdivM", { STi, ST }, 0 },
13740 { "ffree", { STi }, 0 },
13742 { "fst", { STi }, 0 },
13743 { "fstp", { STi }, 0 },
13744 { "fucom", { STi }, 0 },
13745 { "fucomp", { STi }, 0 },
13751 { "faddp", { STi, ST }, 0 },
13752 { "fmulp", { STi, ST }, 0 },
13755 { "fsub!Mp", { STi, ST }, 0 },
13756 { "fsubMp", { STi, ST }, 0 },
13757 { "fdiv!Mp", { STi, ST }, 0 },
13758 { "fdivMp", { STi, ST }, 0 },
13762 { "ffreep", { STi }, 0 },
13767 { "fucomip", { ST, STi }, 0 },
13768 { "fcomip", { ST, STi }, 0 },
13773 static char *fgrps[][8] = {
13776 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13781 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13786 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13791 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13796 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13801 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13806 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13811 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13812 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13817 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13822 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13827 swap_operand (void)
13829 mnemonicendp[0] = '.';
13830 mnemonicendp[1] = 's';
13835 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13836 int sizeflag ATTRIBUTE_UNUSED)
13838 /* Skip mod/rm byte. */
13844 dofloat (int sizeflag)
13846 const struct dis386 *dp;
13847 unsigned char floatop;
13849 floatop = codep[-1];
13851 if (modrm.mod != 3)
13853 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13855 putop (float_mem[fp_indx], sizeflag);
13858 OP_E (float_mem_mode[fp_indx], sizeflag);
13861 /* Skip mod/rm byte. */
13865 dp = &float_reg[floatop - 0xd8][modrm.reg];
13866 if (dp->name == NULL)
13868 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13870 /* Instruction fnstsw is only one with strange arg. */
13871 if (floatop == 0xdf && codep[-1] == 0xe0)
13872 strcpy (op_out[0], names16[0]);
13876 putop (dp->name, sizeflag);
13881 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13886 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13890 /* Like oappend (below), but S is a string starting with '%'.
13891 In Intel syntax, the '%' is elided. */
13893 oappend_maybe_intel (const char *s)
13895 oappend (s + intel_syntax);
13899 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13901 oappend_maybe_intel ("%st");
13905 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13907 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13908 oappend_maybe_intel (scratchbuf);
13911 /* Capital letters in template are macros. */
13913 putop (const char *in_template, int sizeflag)
13918 unsigned int l = 0, len = 1;
13921 #define SAVE_LAST(c) \
13922 if (l < len && l < sizeof (last)) \
13927 for (p = in_template; *p; p++)
13943 while (*++p != '|')
13944 if (*p == '}' || *p == '\0')
13947 /* Fall through. */
13952 while (*++p != '}')
13963 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13967 if (l == 0 && len == 1)
13972 if (sizeflag & SUFFIX_ALWAYS)
13985 if (address_mode == mode_64bit
13986 && !(prefixes & PREFIX_ADDR))
13997 if (intel_syntax && !alt)
13999 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14001 if (sizeflag & DFLAG)
14002 *obufp++ = intel_syntax ? 'd' : 'l';
14004 *obufp++ = intel_syntax ? 'w' : 's';
14005 used_prefixes |= (prefixes & PREFIX_DATA);
14009 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14012 if (modrm.mod == 3)
14018 if (sizeflag & DFLAG)
14019 *obufp++ = intel_syntax ? 'd' : 'l';
14022 used_prefixes |= (prefixes & PREFIX_DATA);
14028 case 'E': /* For jcxz/jecxz */
14029 if (address_mode == mode_64bit)
14031 if (sizeflag & AFLAG)
14037 if (sizeflag & AFLAG)
14039 used_prefixes |= (prefixes & PREFIX_ADDR);
14044 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
14046 if (sizeflag & AFLAG)
14047 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
14049 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
14050 used_prefixes |= (prefixes & PREFIX_ADDR);
14054 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
14056 if ((rex & REX_W) || (sizeflag & DFLAG))
14060 if (!(rex & REX_W))
14061 used_prefixes |= (prefixes & PREFIX_DATA);
14066 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
14067 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
14069 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
14072 if (prefixes & PREFIX_DS)
14091 if (l != 0 || len != 1)
14093 if (l != 1 || len != 2 || last[0] != 'X')
14098 if (!need_vex || !vex.evex)
14101 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14103 switch (vex.length)
14121 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
14126 /* Fall through. */
14129 if (l != 0 || len != 1)
14137 if (sizeflag & SUFFIX_ALWAYS)
14141 if (intel_mnemonic != cond)
14145 if ((prefixes & PREFIX_FWAIT) == 0)
14148 used_prefixes |= PREFIX_FWAIT;
14154 else if (intel_syntax && (sizeflag & DFLAG))
14158 if (!(rex & REX_W))
14159 used_prefixes |= (prefixes & PREFIX_DATA);
14163 && address_mode == mode_64bit
14164 && isa64 == intel64)
14169 /* Fall through. */
14172 && address_mode == mode_64bit
14173 && ((sizeflag & DFLAG) || (rex & REX_W)))
14178 /* Fall through. */
14181 if (l == 0 && len == 1)
14186 if ((rex & REX_W) == 0
14187 && (prefixes & PREFIX_DATA))
14189 if ((sizeflag & DFLAG) == 0)
14191 used_prefixes |= (prefixes & PREFIX_DATA);
14195 if ((prefixes & PREFIX_DATA)
14197 || (sizeflag & SUFFIX_ALWAYS))
14204 if (sizeflag & DFLAG)
14208 used_prefixes |= (prefixes & PREFIX_DATA);
14214 if (l != 1 || len != 2 || last[0] != 'L')
14220 if ((prefixes & PREFIX_DATA)
14222 || (sizeflag & SUFFIX_ALWAYS))
14229 if (sizeflag & DFLAG)
14230 *obufp++ = intel_syntax ? 'd' : 'l';
14233 used_prefixes |= (prefixes & PREFIX_DATA);
14241 if (address_mode == mode_64bit
14242 && ((sizeflag & DFLAG) || (rex & REX_W)))
14244 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14248 /* Fall through. */
14251 if (l == 0 && len == 1)
14254 if (intel_syntax && !alt)
14257 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14263 if (sizeflag & DFLAG)
14264 *obufp++ = intel_syntax ? 'd' : 'l';
14267 used_prefixes |= (prefixes & PREFIX_DATA);
14273 if (l != 1 || len != 2 || last[0] != 'L')
14279 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14294 else if (sizeflag & DFLAG)
14303 if (intel_syntax && !p[1]
14304 && ((rex & REX_W) || (sizeflag & DFLAG)))
14306 if (!(rex & REX_W))
14307 used_prefixes |= (prefixes & PREFIX_DATA);
14310 if (l == 0 && len == 1)
14314 if (address_mode == mode_64bit
14315 && ((sizeflag & DFLAG) || (rex & REX_W)))
14317 if (sizeflag & SUFFIX_ALWAYS)
14339 /* Fall through. */
14342 if (l == 0 && len == 1)
14347 if (sizeflag & SUFFIX_ALWAYS)
14353 if (sizeflag & DFLAG)
14357 used_prefixes |= (prefixes & PREFIX_DATA);
14371 if (address_mode == mode_64bit
14372 && !(prefixes & PREFIX_ADDR))
14383 if (l != 0 || len != 1)
14388 if (need_vex && vex.prefix)
14390 if (vex.prefix == DATA_PREFIX_OPCODE)
14397 if (prefixes & PREFIX_DATA)
14401 used_prefixes |= (prefixes & PREFIX_DATA);
14405 if (l == 0 && len == 1)
14407 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14418 if (l != 1 || len != 2 || last[0] != 'X')
14426 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14428 switch (vex.length)
14444 if (l == 0 && len == 1)
14446 /* operand size flag for cwtl, cbtw */
14455 else if (sizeflag & DFLAG)
14459 if (!(rex & REX_W))
14460 used_prefixes |= (prefixes & PREFIX_DATA);
14467 && last[0] != 'L'))
14474 if (last[0] == 'X')
14475 *obufp++ = vex.w ? 'd': 's';
14477 *obufp++ = vex.w ? 'q': 'd';
14483 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14485 if (sizeflag & DFLAG)
14489 used_prefixes |= (prefixes & PREFIX_DATA);
14495 if (address_mode == mode_64bit
14496 && (isa64 == intel64
14497 || ((sizeflag & DFLAG) || (rex & REX_W))))
14499 else if ((prefixes & PREFIX_DATA))
14501 if (!(sizeflag & DFLAG))
14503 used_prefixes |= (prefixes & PREFIX_DATA);
14510 mnemonicendp = obufp;
14515 oappend (const char *s)
14517 obufp = stpcpy (obufp, s);
14523 /* Only print the active segment register. */
14524 if (!active_seg_prefix)
14527 used_prefixes |= active_seg_prefix;
14528 switch (active_seg_prefix)
14531 oappend_maybe_intel ("%cs:");
14534 oappend_maybe_intel ("%ds:");
14537 oappend_maybe_intel ("%ss:");
14540 oappend_maybe_intel ("%es:");
14543 oappend_maybe_intel ("%fs:");
14546 oappend_maybe_intel ("%gs:");
14554 OP_indirE (int bytemode, int sizeflag)
14558 OP_E (bytemode, sizeflag);
14562 print_operand_value (char *buf, int hex, bfd_vma disp)
14564 if (address_mode == mode_64bit)
14572 sprintf_vma (tmp, disp);
14573 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14574 strcpy (buf + 2, tmp + i);
14578 bfd_signed_vma v = disp;
14585 /* Check for possible overflow on 0x8000000000000000. */
14588 strcpy (buf, "9223372036854775808");
14602 tmp[28 - i] = (v % 10) + '0';
14606 strcpy (buf, tmp + 29 - i);
14612 sprintf (buf, "0x%x", (unsigned int) disp);
14614 sprintf (buf, "%d", (int) disp);
14618 /* Put DISP in BUF as signed hex number. */
14621 print_displacement (char *buf, bfd_vma disp)
14623 bfd_signed_vma val = disp;
14632 /* Check for possible overflow. */
14635 switch (address_mode)
14638 strcpy (buf + j, "0x8000000000000000");
14641 strcpy (buf + j, "0x80000000");
14644 strcpy (buf + j, "0x8000");
14654 sprintf_vma (tmp, (bfd_vma) val);
14655 for (i = 0; tmp[i] == '0'; i++)
14657 if (tmp[i] == '\0')
14659 strcpy (buf + j, tmp + i);
14663 intel_operand_size (int bytemode, int sizeflag)
14667 && (bytemode == x_mode
14668 || bytemode == evex_half_bcst_xmmq_mode))
14671 oappend ("QWORD PTR ");
14673 oappend ("DWORD PTR ");
14682 oappend ("BYTE PTR ");
14687 oappend ("WORD PTR ");
14690 if (address_mode == mode_64bit && isa64 == intel64)
14692 oappend ("QWORD PTR ");
14695 /* Fall through. */
14697 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14699 oappend ("QWORD PTR ");
14702 /* Fall through. */
14708 oappend ("QWORD PTR ");
14711 if ((sizeflag & DFLAG) || bytemode == dq_mode)
14712 oappend ("DWORD PTR ");
14714 oappend ("WORD PTR ");
14715 used_prefixes |= (prefixes & PREFIX_DATA);
14719 if ((rex & REX_W) || (sizeflag & DFLAG))
14721 oappend ("WORD PTR ");
14722 if (!(rex & REX_W))
14723 used_prefixes |= (prefixes & PREFIX_DATA);
14726 if (sizeflag & DFLAG)
14727 oappend ("QWORD PTR ");
14729 oappend ("DWORD PTR ");
14730 used_prefixes |= (prefixes & PREFIX_DATA);
14733 case d_scalar_mode:
14734 case d_scalar_swap_mode:
14737 oappend ("DWORD PTR ");
14740 case q_scalar_mode:
14741 case q_scalar_swap_mode:
14743 oappend ("QWORD PTR ");
14746 if (address_mode == mode_64bit)
14747 oappend ("QWORD PTR ");
14749 oappend ("DWORD PTR ");
14752 if (sizeflag & DFLAG)
14753 oappend ("FWORD PTR ");
14755 oappend ("DWORD PTR ");
14756 used_prefixes |= (prefixes & PREFIX_DATA);
14759 oappend ("TBYTE PTR ");
14763 case evex_x_gscat_mode:
14764 case evex_x_nobcst_mode:
14765 case b_scalar_mode:
14766 case w_scalar_mode:
14769 switch (vex.length)
14772 oappend ("XMMWORD PTR ");
14775 oappend ("YMMWORD PTR ");
14778 oappend ("ZMMWORD PTR ");
14785 oappend ("XMMWORD PTR ");
14788 oappend ("XMMWORD PTR ");
14791 oappend ("YMMWORD PTR ");
14794 case evex_half_bcst_xmmq_mode:
14798 switch (vex.length)
14801 oappend ("QWORD PTR ");
14804 oappend ("XMMWORD PTR ");
14807 oappend ("YMMWORD PTR ");
14817 switch (vex.length)
14822 oappend ("BYTE PTR ");
14832 switch (vex.length)
14837 oappend ("WORD PTR ");
14847 switch (vex.length)
14852 oappend ("DWORD PTR ");
14862 switch (vex.length)
14867 oappend ("QWORD PTR ");
14877 switch (vex.length)
14880 oappend ("WORD PTR ");
14883 oappend ("DWORD PTR ");
14886 oappend ("QWORD PTR ");
14896 switch (vex.length)
14899 oappend ("DWORD PTR ");
14902 oappend ("QWORD PTR ");
14905 oappend ("XMMWORD PTR ");
14915 switch (vex.length)
14918 oappend ("QWORD PTR ");
14921 oappend ("YMMWORD PTR ");
14924 oappend ("ZMMWORD PTR ");
14934 switch (vex.length)
14938 oappend ("XMMWORD PTR ");
14945 oappend ("OWORD PTR ");
14948 case vex_w_dq_mode:
14949 case vex_scalar_w_dq_mode:
14954 oappend ("QWORD PTR ");
14956 oappend ("DWORD PTR ");
14958 case vex_vsib_d_w_dq_mode:
14959 case vex_vsib_q_w_dq_mode:
14966 oappend ("QWORD PTR ");
14968 oappend ("DWORD PTR ");
14972 switch (vex.length)
14975 oappend ("XMMWORD PTR ");
14978 oappend ("YMMWORD PTR ");
14981 oappend ("ZMMWORD PTR ");
14988 case vex_vsib_q_w_d_mode:
14989 case vex_vsib_d_w_d_mode:
14990 if (!need_vex || !vex.evex)
14993 switch (vex.length)
14996 oappend ("QWORD PTR ");
14999 oappend ("XMMWORD PTR ");
15002 oappend ("YMMWORD PTR ");
15010 if (!need_vex || vex.length != 128)
15013 oappend ("DWORD PTR ");
15015 oappend ("BYTE PTR ");
15021 oappend ("QWORD PTR ");
15023 oappend ("WORD PTR ");
15032 OP_E_register (int bytemode, int sizeflag)
15034 int reg = modrm.rm;
15035 const char **names;
15041 if ((sizeflag & SUFFIX_ALWAYS)
15042 && (bytemode == b_swap_mode
15043 || bytemode == v_swap_mode))
15069 names = address_mode == mode_64bit ? names64 : names32;
15080 if (address_mode == mode_64bit && isa64 == intel64)
15085 /* Fall through. */
15087 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
15093 /* Fall through. */
15105 if ((sizeflag & DFLAG)
15106 || (bytemode != v_mode
15107 && bytemode != v_swap_mode))
15111 used_prefixes |= (prefixes & PREFIX_DATA);
15121 names = names_mask;
15126 oappend (INTERNAL_DISASSEMBLER_ERROR);
15129 oappend (names[reg]);
15133 OP_E_memory (int bytemode, int sizeflag)
15136 int add = (rex & REX_B) ? 8 : 0;
15142 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
15144 && bytemode != x_mode
15145 && bytemode != xmmq_mode
15146 && bytemode != evex_half_bcst_xmmq_mode)
15161 case vex_vsib_d_w_dq_mode:
15162 case vex_vsib_d_w_d_mode:
15163 case vex_vsib_q_w_dq_mode:
15164 case vex_vsib_q_w_d_mode:
15165 case evex_x_gscat_mode:
15167 shift = vex.w ? 3 : 2;
15170 case evex_half_bcst_xmmq_mode:
15174 shift = vex.w ? 3 : 2;
15177 /* Fall through. */
15181 case evex_x_nobcst_mode:
15183 switch (vex.length)
15206 case q_scalar_mode:
15208 case q_scalar_swap_mode:
15214 case d_scalar_mode:
15216 case d_scalar_swap_mode:
15219 case w_scalar_mode:
15223 case b_scalar_mode:
15230 /* Make necessary corrections to shift for modes that need it.
15231 For these modes we currently have shift 4, 5 or 6 depending on
15232 vex.length (it corresponds to xmmword, ymmword or zmmword
15233 operand). We might want to make it 3, 4 or 5 (e.g. for
15234 xmmq_mode). In case of broadcast enabled the corrections
15235 aren't needed, as element size is always 32 or 64 bits. */
15237 && (bytemode == xmmq_mode
15238 || bytemode == evex_half_bcst_xmmq_mode))
15240 else if (bytemode == xmmqd_mode)
15242 else if (bytemode == xmmdw_mode)
15244 else if (bytemode == ymmq_mode && vex.length == 128)
15252 intel_operand_size (bytemode, sizeflag);
15255 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15257 /* 32/64 bit address mode */
15266 int addr32flag = !((sizeflag & AFLAG)
15267 || bytemode == v_bnd_mode
15268 || bytemode == bnd_mode);
15269 const char **indexes64 = names64;
15270 const char **indexes32 = names32;
15280 vindex = sib.index;
15286 case vex_vsib_d_w_dq_mode:
15287 case vex_vsib_d_w_d_mode:
15288 case vex_vsib_q_w_dq_mode:
15289 case vex_vsib_q_w_d_mode:
15299 switch (vex.length)
15302 indexes64 = indexes32 = names_xmm;
15306 || bytemode == vex_vsib_q_w_dq_mode
15307 || bytemode == vex_vsib_q_w_d_mode)
15308 indexes64 = indexes32 = names_ymm;
15310 indexes64 = indexes32 = names_xmm;
15314 || bytemode == vex_vsib_q_w_dq_mode
15315 || bytemode == vex_vsib_q_w_d_mode)
15316 indexes64 = indexes32 = names_zmm;
15318 indexes64 = indexes32 = names_ymm;
15325 haveindex = vindex != 4;
15332 rbase = base + add;
15340 if (address_mode == mode_64bit && !havesib)
15346 FETCH_DATA (the_info, codep + 1);
15348 if ((disp & 0x80) != 0)
15350 if (vex.evex && shift > 0)
15358 /* In 32bit mode, we need index register to tell [offset] from
15359 [eiz*1 + offset]. */
15360 needindex = (havesib
15363 && address_mode == mode_32bit);
15364 havedisp = (havebase
15366 || (havesib && (haveindex || scale != 0)));
15369 if (modrm.mod != 0 || base == 5)
15371 if (havedisp || riprel)
15372 print_displacement (scratchbuf, disp);
15374 print_operand_value (scratchbuf, 1, disp);
15375 oappend (scratchbuf);
15379 oappend (!addr32flag ? "(%rip)" : "(%eip)");
15383 if ((havebase || haveindex || riprel)
15384 && (bytemode != v_bnd_mode)
15385 && (bytemode != bnd_mode))
15386 used_prefixes |= PREFIX_ADDR;
15388 if (havedisp || (intel_syntax && riprel))
15390 *obufp++ = open_char;
15391 if (intel_syntax && riprel)
15394 oappend (!addr32flag ? "rip" : "eip");
15398 oappend (address_mode == mode_64bit && !addr32flag
15399 ? names64[rbase] : names32[rbase]);
15402 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
15403 print index to tell base + index from base. */
15407 || (havebase && base != ESP_REG_NUM))
15409 if (!intel_syntax || havebase)
15411 *obufp++ = separator_char;
15415 oappend (address_mode == mode_64bit && !addr32flag
15416 ? indexes64[vindex] : indexes32[vindex]);
15418 oappend (address_mode == mode_64bit && !addr32flag
15419 ? index64 : index32);
15421 *obufp++ = scale_char;
15423 sprintf (scratchbuf, "%d", 1 << scale);
15424 oappend (scratchbuf);
15428 && (disp || modrm.mod != 0 || base == 5))
15430 if (!havedisp || (bfd_signed_vma) disp >= 0)
15435 else if (modrm.mod != 1 && disp != -disp)
15439 disp = - (bfd_signed_vma) disp;
15443 print_displacement (scratchbuf, disp);
15445 print_operand_value (scratchbuf, 1, disp);
15446 oappend (scratchbuf);
15449 *obufp++ = close_char;
15452 else if (intel_syntax)
15454 if (modrm.mod != 0 || base == 5)
15456 if (!active_seg_prefix)
15458 oappend (names_seg[ds_reg - es_reg]);
15461 print_operand_value (scratchbuf, 1, disp);
15462 oappend (scratchbuf);
15468 /* 16 bit address mode */
15469 used_prefixes |= prefixes & PREFIX_ADDR;
15476 if ((disp & 0x8000) != 0)
15481 FETCH_DATA (the_info, codep + 1);
15483 if ((disp & 0x80) != 0)
15488 if ((disp & 0x8000) != 0)
15494 if (modrm.mod != 0 || modrm.rm == 6)
15496 print_displacement (scratchbuf, disp);
15497 oappend (scratchbuf);
15500 if (modrm.mod != 0 || modrm.rm != 6)
15502 *obufp++ = open_char;
15504 oappend (index16[modrm.rm]);
15506 && (disp || modrm.mod != 0 || modrm.rm == 6))
15508 if ((bfd_signed_vma) disp >= 0)
15513 else if (modrm.mod != 1)
15517 disp = - (bfd_signed_vma) disp;
15520 print_displacement (scratchbuf, disp);
15521 oappend (scratchbuf);
15524 *obufp++ = close_char;
15527 else if (intel_syntax)
15529 if (!active_seg_prefix)
15531 oappend (names_seg[ds_reg - es_reg]);
15534 print_operand_value (scratchbuf, 1, disp & 0xffff);
15535 oappend (scratchbuf);
15538 if (vex.evex && vex.b
15539 && (bytemode == x_mode
15540 || bytemode == xmmq_mode
15541 || bytemode == evex_half_bcst_xmmq_mode))
15544 || bytemode == xmmq_mode
15545 || bytemode == evex_half_bcst_xmmq_mode)
15547 switch (vex.length)
15550 oappend ("{1to2}");
15553 oappend ("{1to4}");
15556 oappend ("{1to8}");
15564 switch (vex.length)
15567 oappend ("{1to4}");
15570 oappend ("{1to8}");
15573 oappend ("{1to16}");
15583 OP_E (int bytemode, int sizeflag)
15585 /* Skip mod/rm byte. */
15589 if (modrm.mod == 3)
15590 OP_E_register (bytemode, sizeflag);
15592 OP_E_memory (bytemode, sizeflag);
15596 OP_G (int bytemode, int sizeflag)
15607 oappend (names8rex[modrm.reg + add]);
15609 oappend (names8[modrm.reg + add]);
15612 oappend (names16[modrm.reg + add]);
15617 oappend (names32[modrm.reg + add]);
15620 oappend (names64[modrm.reg + add]);
15623 if (modrm.reg > 0x3)
15628 oappend (names_bnd[modrm.reg]);
15637 oappend (names64[modrm.reg + add]);
15640 if ((sizeflag & DFLAG) || bytemode != v_mode)
15641 oappend (names32[modrm.reg + add]);
15643 oappend (names16[modrm.reg + add]);
15644 used_prefixes |= (prefixes & PREFIX_DATA);
15648 if (address_mode == mode_64bit)
15649 oappend (names64[modrm.reg + add]);
15651 oappend (names32[modrm.reg + add]);
15655 if ((modrm.reg + add) > 0x7)
15660 oappend (names_mask[modrm.reg + add]);
15663 oappend (INTERNAL_DISASSEMBLER_ERROR);
15676 FETCH_DATA (the_info, codep + 8);
15677 a = *codep++ & 0xff;
15678 a |= (*codep++ & 0xff) << 8;
15679 a |= (*codep++ & 0xff) << 16;
15680 a |= (*codep++ & 0xffu) << 24;
15681 b = *codep++ & 0xff;
15682 b |= (*codep++ & 0xff) << 8;
15683 b |= (*codep++ & 0xff) << 16;
15684 b |= (*codep++ & 0xffu) << 24;
15685 x = a + ((bfd_vma) b << 32);
15693 static bfd_signed_vma
15696 bfd_signed_vma x = 0;
15698 FETCH_DATA (the_info, codep + 4);
15699 x = *codep++ & (bfd_signed_vma) 0xff;
15700 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15701 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15702 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15706 static bfd_signed_vma
15709 bfd_signed_vma x = 0;
15711 FETCH_DATA (the_info, codep + 4);
15712 x = *codep++ & (bfd_signed_vma) 0xff;
15713 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15714 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15715 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15717 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15727 FETCH_DATA (the_info, codep + 2);
15728 x = *codep++ & 0xff;
15729 x |= (*codep++ & 0xff) << 8;
15734 set_op (bfd_vma op, int riprel)
15736 op_index[op_ad] = op_ad;
15737 if (address_mode == mode_64bit)
15739 op_address[op_ad] = op;
15740 op_riprel[op_ad] = riprel;
15744 /* Mask to get a 32-bit address. */
15745 op_address[op_ad] = op & 0xffffffff;
15746 op_riprel[op_ad] = riprel & 0xffffffff;
15751 OP_REG (int code, int sizeflag)
15758 case es_reg: case ss_reg: case cs_reg:
15759 case ds_reg: case fs_reg: case gs_reg:
15760 oappend (names_seg[code - es_reg]);
15772 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15773 case sp_reg: case bp_reg: case si_reg: case di_reg:
15774 s = names16[code - ax_reg + add];
15776 case al_reg: case ah_reg: case cl_reg: case ch_reg:
15777 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15780 s = names8rex[code - al_reg + add];
15782 s = names8[code - al_reg];
15784 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15785 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15786 if (address_mode == mode_64bit
15787 && ((sizeflag & DFLAG) || (rex & REX_W)))
15789 s = names64[code - rAX_reg + add];
15792 code += eAX_reg - rAX_reg;
15793 /* Fall through. */
15794 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15795 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15798 s = names64[code - eAX_reg + add];
15801 if (sizeflag & DFLAG)
15802 s = names32[code - eAX_reg + add];
15804 s = names16[code - eAX_reg + add];
15805 used_prefixes |= (prefixes & PREFIX_DATA);
15809 s = INTERNAL_DISASSEMBLER_ERROR;
15816 OP_IMREG (int code, int sizeflag)
15828 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15829 case sp_reg: case bp_reg: case si_reg: case di_reg:
15830 s = names16[code - ax_reg];
15832 case es_reg: case ss_reg: case cs_reg:
15833 case ds_reg: case fs_reg: case gs_reg:
15834 s = names_seg[code - es_reg];
15836 case al_reg: case ah_reg: case cl_reg: case ch_reg:
15837 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15840 s = names8rex[code - al_reg];
15842 s = names8[code - al_reg];
15844 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15845 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15848 s = names64[code - eAX_reg];
15851 if (sizeflag & DFLAG)
15852 s = names32[code - eAX_reg];
15854 s = names16[code - eAX_reg];
15855 used_prefixes |= (prefixes & PREFIX_DATA);
15858 case z_mode_ax_reg:
15859 if ((rex & REX_W) || (sizeflag & DFLAG))
15863 if (!(rex & REX_W))
15864 used_prefixes |= (prefixes & PREFIX_DATA);
15867 s = INTERNAL_DISASSEMBLER_ERROR;
15874 OP_I (int bytemode, int sizeflag)
15877 bfd_signed_vma mask = -1;
15882 FETCH_DATA (the_info, codep + 1);
15887 if (address_mode == mode_64bit)
15892 /* Fall through. */
15899 if (sizeflag & DFLAG)
15909 used_prefixes |= (prefixes & PREFIX_DATA);
15921 oappend (INTERNAL_DISASSEMBLER_ERROR);
15926 scratchbuf[0] = '$';
15927 print_operand_value (scratchbuf + 1, 1, op);
15928 oappend_maybe_intel (scratchbuf);
15929 scratchbuf[0] = '\0';
15933 OP_I64 (int bytemode, int sizeflag)
15936 bfd_signed_vma mask = -1;
15938 if (address_mode != mode_64bit)
15940 OP_I (bytemode, sizeflag);
15947 FETCH_DATA (the_info, codep + 1);
15957 if (sizeflag & DFLAG)
15967 used_prefixes |= (prefixes & PREFIX_DATA);
15975 oappend (INTERNAL_DISASSEMBLER_ERROR);
15980 scratchbuf[0] = '$';
15981 print_operand_value (scratchbuf + 1, 1, op);
15982 oappend_maybe_intel (scratchbuf);
15983 scratchbuf[0] = '\0';
15987 OP_sI (int bytemode, int sizeflag)
15995 FETCH_DATA (the_info, codep + 1);
15997 if ((op & 0x80) != 0)
15999 if (bytemode == b_T_mode)
16001 if (address_mode != mode_64bit
16002 || !((sizeflag & DFLAG) || (rex & REX_W)))
16004 /* The operand-size prefix is overridden by a REX prefix. */
16005 if ((sizeflag & DFLAG) || (rex & REX_W))
16013 if (!(rex & REX_W))
16015 if (sizeflag & DFLAG)
16023 /* The operand-size prefix is overridden by a REX prefix. */
16024 if ((sizeflag & DFLAG) || (rex & REX_W))
16030 oappend (INTERNAL_DISASSEMBLER_ERROR);
16034 scratchbuf[0] = '$';
16035 print_operand_value (scratchbuf + 1, 1, op);
16036 oappend_maybe_intel (scratchbuf);
16040 OP_J (int bytemode, int sizeflag)
16044 bfd_vma segment = 0;
16049 FETCH_DATA (the_info, codep + 1);
16051 if ((disp & 0x80) != 0)
16055 if (isa64 == amd64)
16057 if ((sizeflag & DFLAG)
16058 || (address_mode == mode_64bit
16059 && (isa64 != amd64 || (rex & REX_W))))
16064 if ((disp & 0x8000) != 0)
16066 /* In 16bit mode, address is wrapped around at 64k within
16067 the same segment. Otherwise, a data16 prefix on a jump
16068 instruction means that the pc is masked to 16 bits after
16069 the displacement is added! */
16071 if ((prefixes & PREFIX_DATA) == 0)
16072 segment = ((start_pc + (codep - start_codep))
16073 & ~((bfd_vma) 0xffff));
16075 if (address_mode != mode_64bit
16076 || (isa64 == amd64 && !(rex & REX_W)))
16077 used_prefixes |= (prefixes & PREFIX_DATA);
16080 oappend (INTERNAL_DISASSEMBLER_ERROR);
16083 disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
16085 print_operand_value (scratchbuf, 1, disp);
16086 oappend (scratchbuf);
16090 OP_SEG (int bytemode, int sizeflag)
16092 if (bytemode == w_mode)
16093 oappend (names_seg[modrm.reg]);
16095 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
16099 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
16103 if (sizeflag & DFLAG)
16113 used_prefixes |= (prefixes & PREFIX_DATA);
16115 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
16117 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
16118 oappend (scratchbuf);
16122 OP_OFF (int bytemode, int sizeflag)
16126 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16127 intel_operand_size (bytemode, sizeflag);
16130 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16137 if (!active_seg_prefix)
16139 oappend (names_seg[ds_reg - es_reg]);
16143 print_operand_value (scratchbuf, 1, off);
16144 oappend (scratchbuf);
16148 OP_OFF64 (int bytemode, int sizeflag)
16152 if (address_mode != mode_64bit
16153 || (prefixes & PREFIX_ADDR))
16155 OP_OFF (bytemode, sizeflag);
16159 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16160 intel_operand_size (bytemode, sizeflag);
16167 if (!active_seg_prefix)
16169 oappend (names_seg[ds_reg - es_reg]);
16173 print_operand_value (scratchbuf, 1, off);
16174 oappend (scratchbuf);
16178 ptr_reg (int code, int sizeflag)
16182 *obufp++ = open_char;
16183 used_prefixes |= (prefixes & PREFIX_ADDR);
16184 if (address_mode == mode_64bit)
16186 if (!(sizeflag & AFLAG))
16187 s = names32[code - eAX_reg];
16189 s = names64[code - eAX_reg];
16191 else if (sizeflag & AFLAG)
16192 s = names32[code - eAX_reg];
16194 s = names16[code - eAX_reg];
16196 *obufp++ = close_char;
16201 OP_ESreg (int code, int sizeflag)
16207 case 0x6d: /* insw/insl */
16208 intel_operand_size (z_mode, sizeflag);
16210 case 0xa5: /* movsw/movsl/movsq */
16211 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16212 case 0xab: /* stosw/stosl */
16213 case 0xaf: /* scasw/scasl */
16214 intel_operand_size (v_mode, sizeflag);
16217 intel_operand_size (b_mode, sizeflag);
16220 oappend_maybe_intel ("%es:");
16221 ptr_reg (code, sizeflag);
16225 OP_DSreg (int code, int sizeflag)
16231 case 0x6f: /* outsw/outsl */
16232 intel_operand_size (z_mode, sizeflag);
16234 case 0xa5: /* movsw/movsl/movsq */
16235 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16236 case 0xad: /* lodsw/lodsl/lodsq */
16237 intel_operand_size (v_mode, sizeflag);
16240 intel_operand_size (b_mode, sizeflag);
16243 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16244 default segment register DS is printed. */
16245 if (!active_seg_prefix)
16246 active_seg_prefix = PREFIX_DS;
16248 ptr_reg (code, sizeflag);
16252 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16260 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
16262 all_prefixes[last_lock_prefix] = 0;
16263 used_prefixes |= PREFIX_LOCK;
16268 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
16269 oappend_maybe_intel (scratchbuf);
16273 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16282 sprintf (scratchbuf, "db%d", modrm.reg + add);
16284 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
16285 oappend (scratchbuf);
16289 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16291 sprintf (scratchbuf, "%%tr%d", modrm.reg);
16292 oappend_maybe_intel (scratchbuf);
16296 OP_R (int bytemode, int sizeflag)
16298 /* Skip mod/rm byte. */
16301 OP_E_register (bytemode, sizeflag);
16305 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16307 int reg = modrm.reg;
16308 const char **names;
16310 used_prefixes |= (prefixes & PREFIX_DATA);
16311 if (prefixes & PREFIX_DATA)
16320 oappend (names[reg]);
16324 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16326 int reg = modrm.reg;
16327 const char **names;
16339 && bytemode != xmm_mode
16340 && bytemode != xmmq_mode
16341 && bytemode != evex_half_bcst_xmmq_mode
16342 && bytemode != ymm_mode
16343 && bytemode != scalar_mode)
16345 switch (vex.length)
16352 || (bytemode != vex_vsib_q_w_dq_mode
16353 && bytemode != vex_vsib_q_w_d_mode))
16365 else if (bytemode == xmmq_mode
16366 || bytemode == evex_half_bcst_xmmq_mode)
16368 switch (vex.length)
16381 else if (bytemode == ymm_mode)
16385 oappend (names[reg]);
16389 OP_EM (int bytemode, int sizeflag)
16392 const char **names;
16394 if (modrm.mod != 3)
16397 && (bytemode == v_mode || bytemode == v_swap_mode))
16399 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16400 used_prefixes |= (prefixes & PREFIX_DATA);
16402 OP_E (bytemode, sizeflag);
16406 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16409 /* Skip mod/rm byte. */
16412 used_prefixes |= (prefixes & PREFIX_DATA);
16414 if (prefixes & PREFIX_DATA)
16423 oappend (names[reg]);
16426 /* cvt* are the only instructions in sse2 which have
16427 both SSE and MMX operands and also have 0x66 prefix
16428 in their opcode. 0x66 was originally used to differentiate
16429 between SSE and MMX instruction(operands). So we have to handle the
16430 cvt* separately using OP_EMC and OP_MXC */
16432 OP_EMC (int bytemode, int sizeflag)
16434 if (modrm.mod != 3)
16436 if (intel_syntax && bytemode == v_mode)
16438 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16439 used_prefixes |= (prefixes & PREFIX_DATA);
16441 OP_E (bytemode, sizeflag);
16445 /* Skip mod/rm byte. */
16448 used_prefixes |= (prefixes & PREFIX_DATA);
16449 oappend (names_mm[modrm.rm]);
16453 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16455 used_prefixes |= (prefixes & PREFIX_DATA);
16456 oappend (names_mm[modrm.reg]);
16460 OP_EX (int bytemode, int sizeflag)
16463 const char **names;
16465 /* Skip mod/rm byte. */
16469 if (modrm.mod != 3)
16471 OP_E_memory (bytemode, sizeflag);
16486 if ((sizeflag & SUFFIX_ALWAYS)
16487 && (bytemode == x_swap_mode
16488 || bytemode == d_swap_mode
16489 || bytemode == d_scalar_swap_mode
16490 || bytemode == q_swap_mode
16491 || bytemode == q_scalar_swap_mode))
16495 && bytemode != xmm_mode
16496 && bytemode != xmmdw_mode
16497 && bytemode != xmmqd_mode
16498 && bytemode != xmm_mb_mode
16499 && bytemode != xmm_mw_mode
16500 && bytemode != xmm_md_mode
16501 && bytemode != xmm_mq_mode
16502 && bytemode != xmm_mdq_mode
16503 && bytemode != xmmq_mode
16504 && bytemode != evex_half_bcst_xmmq_mode
16505 && bytemode != ymm_mode
16506 && bytemode != d_scalar_mode
16507 && bytemode != d_scalar_swap_mode
16508 && bytemode != q_scalar_mode
16509 && bytemode != q_scalar_swap_mode
16510 && bytemode != vex_scalar_w_dq_mode)
16512 switch (vex.length)
16527 else if (bytemode == xmmq_mode
16528 || bytemode == evex_half_bcst_xmmq_mode)
16530 switch (vex.length)
16543 else if (bytemode == ymm_mode)
16547 oappend (names[reg]);
16551 OP_MS (int bytemode, int sizeflag)
16553 if (modrm.mod == 3)
16554 OP_EM (bytemode, sizeflag);
16560 OP_XS (int bytemode, int sizeflag)
16562 if (modrm.mod == 3)
16563 OP_EX (bytemode, sizeflag);
16569 OP_M (int bytemode, int sizeflag)
16571 if (modrm.mod == 3)
16572 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16575 OP_E (bytemode, sizeflag);
16579 OP_0f07 (int bytemode, int sizeflag)
16581 if (modrm.mod != 3 || modrm.rm != 0)
16584 OP_E (bytemode, sizeflag);
16587 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16588 32bit mode and "xchg %rax,%rax" in 64bit mode. */
16591 NOP_Fixup1 (int bytemode, int sizeflag)
16593 if ((prefixes & PREFIX_DATA) != 0
16596 && address_mode == mode_64bit))
16597 OP_REG (bytemode, sizeflag);
16599 strcpy (obuf, "nop");
16603 NOP_Fixup2 (int bytemode, int sizeflag)
16605 if ((prefixes & PREFIX_DATA) != 0
16608 && address_mode == mode_64bit))
16609 OP_IMREG (bytemode, sizeflag);
16612 static const char *const Suffix3DNow[] = {
16613 /* 00 */ NULL, NULL, NULL, NULL,
16614 /* 04 */ NULL, NULL, NULL, NULL,
16615 /* 08 */ NULL, NULL, NULL, NULL,
16616 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
16617 /* 10 */ NULL, NULL, NULL, NULL,
16618 /* 14 */ NULL, NULL, NULL, NULL,
16619 /* 18 */ NULL, NULL, NULL, NULL,
16620 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
16621 /* 20 */ NULL, NULL, NULL, NULL,
16622 /* 24 */ NULL, NULL, NULL, NULL,
16623 /* 28 */ NULL, NULL, NULL, NULL,
16624 /* 2C */ NULL, NULL, NULL, NULL,
16625 /* 30 */ NULL, NULL, NULL, NULL,
16626 /* 34 */ NULL, NULL, NULL, NULL,
16627 /* 38 */ NULL, NULL, NULL, NULL,
16628 /* 3C */ NULL, NULL, NULL, NULL,
16629 /* 40 */ NULL, NULL, NULL, NULL,
16630 /* 44 */ NULL, NULL, NULL, NULL,
16631 /* 48 */ NULL, NULL, NULL, NULL,
16632 /* 4C */ NULL, NULL, NULL, NULL,
16633 /* 50 */ NULL, NULL, NULL, NULL,
16634 /* 54 */ NULL, NULL, NULL, NULL,
16635 /* 58 */ NULL, NULL, NULL, NULL,
16636 /* 5C */ NULL, NULL, NULL, NULL,
16637 /* 60 */ NULL, NULL, NULL, NULL,
16638 /* 64 */ NULL, NULL, NULL, NULL,
16639 /* 68 */ NULL, NULL, NULL, NULL,
16640 /* 6C */ NULL, NULL, NULL, NULL,
16641 /* 70 */ NULL, NULL, NULL, NULL,
16642 /* 74 */ NULL, NULL, NULL, NULL,
16643 /* 78 */ NULL, NULL, NULL, NULL,
16644 /* 7C */ NULL, NULL, NULL, NULL,
16645 /* 80 */ NULL, NULL, NULL, NULL,
16646 /* 84 */ NULL, NULL, NULL, NULL,
16647 /* 88 */ NULL, NULL, "pfnacc", NULL,
16648 /* 8C */ NULL, NULL, "pfpnacc", NULL,
16649 /* 90 */ "pfcmpge", NULL, NULL, NULL,
16650 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
16651 /* 98 */ NULL, NULL, "pfsub", NULL,
16652 /* 9C */ NULL, NULL, "pfadd", NULL,
16653 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
16654 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
16655 /* A8 */ NULL, NULL, "pfsubr", NULL,
16656 /* AC */ NULL, NULL, "pfacc", NULL,
16657 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
16658 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
16659 /* B8 */ NULL, NULL, NULL, "pswapd",
16660 /* BC */ NULL, NULL, NULL, "pavgusb",
16661 /* C0 */ NULL, NULL, NULL, NULL,
16662 /* C4 */ NULL, NULL, NULL, NULL,
16663 /* C8 */ NULL, NULL, NULL, NULL,
16664 /* CC */ NULL, NULL, NULL, NULL,
16665 /* D0 */ NULL, NULL, NULL, NULL,
16666 /* D4 */ NULL, NULL, NULL, NULL,
16667 /* D8 */ NULL, NULL, NULL, NULL,
16668 /* DC */ NULL, NULL, NULL, NULL,
16669 /* E0 */ NULL, NULL, NULL, NULL,
16670 /* E4 */ NULL, NULL, NULL, NULL,
16671 /* E8 */ NULL, NULL, NULL, NULL,
16672 /* EC */ NULL, NULL, NULL, NULL,
16673 /* F0 */ NULL, NULL, NULL, NULL,
16674 /* F4 */ NULL, NULL, NULL, NULL,
16675 /* F8 */ NULL, NULL, NULL, NULL,
16676 /* FC */ NULL, NULL, NULL, NULL,
16680 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16682 const char *mnemonic;
16684 FETCH_DATA (the_info, codep + 1);
16685 /* AMD 3DNow! instructions are specified by an opcode suffix in the
16686 place where an 8-bit immediate would normally go. ie. the last
16687 byte of the instruction. */
16688 obufp = mnemonicendp;
16689 mnemonic = Suffix3DNow[*codep++ & 0xff];
16691 oappend (mnemonic);
16694 /* Since a variable sized modrm/sib chunk is between the start
16695 of the opcode (0x0f0f) and the opcode suffix, we need to do
16696 all the modrm processing first, and don't know until now that
16697 we have a bad opcode. This necessitates some cleaning up. */
16698 op_out[0][0] = '\0';
16699 op_out[1][0] = '\0';
16702 mnemonicendp = obufp;
16705 static struct op simd_cmp_op[] =
16707 { STRING_COMMA_LEN ("eq") },
16708 { STRING_COMMA_LEN ("lt") },
16709 { STRING_COMMA_LEN ("le") },
16710 { STRING_COMMA_LEN ("unord") },
16711 { STRING_COMMA_LEN ("neq") },
16712 { STRING_COMMA_LEN ("nlt") },
16713 { STRING_COMMA_LEN ("nle") },
16714 { STRING_COMMA_LEN ("ord") }
16718 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16720 unsigned int cmp_type;
16722 FETCH_DATA (the_info, codep + 1);
16723 cmp_type = *codep++ & 0xff;
16724 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16727 char *p = mnemonicendp - 2;
16731 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16732 mnemonicendp += simd_cmp_op[cmp_type].len;
16736 /* We have a reserved extension byte. Output it directly. */
16737 scratchbuf[0] = '$';
16738 print_operand_value (scratchbuf + 1, 1, cmp_type);
16739 oappend_maybe_intel (scratchbuf);
16740 scratchbuf[0] = '\0';
16745 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
16746 int sizeflag ATTRIBUTE_UNUSED)
16748 /* mwaitx %eax,%ecx,%ebx */
16751 const char **names = (address_mode == mode_64bit
16752 ? names64 : names32);
16753 strcpy (op_out[0], names[0]);
16754 strcpy (op_out[1], names[1]);
16755 strcpy (op_out[2], names[3]);
16756 two_source_ops = 1;
16758 /* Skip mod/rm byte. */
16764 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16765 int sizeflag ATTRIBUTE_UNUSED)
16767 /* mwait %eax,%ecx */
16770 const char **names = (address_mode == mode_64bit
16771 ? names64 : names32);
16772 strcpy (op_out[0], names[0]);
16773 strcpy (op_out[1], names[1]);
16774 two_source_ops = 1;
16776 /* Skip mod/rm byte. */
16782 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16783 int sizeflag ATTRIBUTE_UNUSED)
16785 /* monitor %eax,%ecx,%edx" */
16788 const char **op1_names;
16789 const char **names = (address_mode == mode_64bit
16790 ? names64 : names32);
16792 if (!(prefixes & PREFIX_ADDR))
16793 op1_names = (address_mode == mode_16bit
16794 ? names16 : names);
16797 /* Remove "addr16/addr32". */
16798 all_prefixes[last_addr_prefix] = 0;
16799 op1_names = (address_mode != mode_32bit
16800 ? names32 : names16);
16801 used_prefixes |= PREFIX_ADDR;
16803 strcpy (op_out[0], op1_names[0]);
16804 strcpy (op_out[1], names[1]);
16805 strcpy (op_out[2], names[2]);
16806 two_source_ops = 1;
16808 /* Skip mod/rm byte. */
16816 /* Throw away prefixes and 1st. opcode byte. */
16817 codep = insn_codep + 1;
16822 REP_Fixup (int bytemode, int sizeflag)
16824 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16826 if (prefixes & PREFIX_REPZ)
16827 all_prefixes[last_repz_prefix] = REP_PREFIX;
16834 OP_IMREG (bytemode, sizeflag);
16837 OP_ESreg (bytemode, sizeflag);
16840 OP_DSreg (bytemode, sizeflag);
16848 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16852 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16854 if (prefixes & PREFIX_REPNZ)
16855 all_prefixes[last_repnz_prefix] = BND_PREFIX;
16858 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
16862 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
16863 int sizeflag ATTRIBUTE_UNUSED)
16865 if (active_seg_prefix == PREFIX_DS
16866 && (address_mode != mode_64bit || last_data_prefix < 0))
16868 /* NOTRACK prefix is only valid on indirect branch instructions.
16869 NB: DATA prefix is unsupported for Intel64. */
16870 active_seg_prefix = 0;
16871 all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
16875 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16876 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
16880 HLE_Fixup1 (int bytemode, int sizeflag)
16883 && (prefixes & PREFIX_LOCK) != 0)
16885 if (prefixes & PREFIX_REPZ)
16886 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16887 if (prefixes & PREFIX_REPNZ)
16888 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16891 OP_E (bytemode, sizeflag);
16894 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
16895 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
16899 HLE_Fixup2 (int bytemode, int sizeflag)
16901 if (modrm.mod != 3)
16903 if (prefixes & PREFIX_REPZ)
16904 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16905 if (prefixes & PREFIX_REPNZ)
16906 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16909 OP_E (bytemode, sizeflag);
16912 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
16913 "xrelease" for memory operand. No check for LOCK prefix. */
16916 HLE_Fixup3 (int bytemode, int sizeflag)
16919 && last_repz_prefix > last_repnz_prefix
16920 && (prefixes & PREFIX_REPZ) != 0)
16921 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16923 OP_E (bytemode, sizeflag);
16927 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
16932 /* Change cmpxchg8b to cmpxchg16b. */
16933 char *p = mnemonicendp - 2;
16934 mnemonicendp = stpcpy (p, "16b");
16937 else if ((prefixes & PREFIX_LOCK) != 0)
16939 if (prefixes & PREFIX_REPZ)
16940 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
16941 if (prefixes & PREFIX_REPNZ)
16942 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
16945 OP_M (bytemode, sizeflag);
16949 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
16951 const char **names;
16955 switch (vex.length)
16969 oappend (names[reg]);
16973 CRC32_Fixup (int bytemode, int sizeflag)
16975 /* Add proper suffix to "crc32". */
16976 char *p = mnemonicendp;
16995 if (sizeflag & DFLAG)
16999 used_prefixes |= (prefixes & PREFIX_DATA);
17003 oappend (INTERNAL_DISASSEMBLER_ERROR);
17010 if (modrm.mod == 3)
17014 /* Skip mod/rm byte. */
17019 add = (rex & REX_B) ? 8 : 0;
17020 if (bytemode == b_mode)
17024 oappend (names8rex[modrm.rm + add]);
17026 oappend (names8[modrm.rm + add]);
17032 oappend (names64[modrm.rm + add]);
17033 else if ((prefixes & PREFIX_DATA))
17034 oappend (names16[modrm.rm + add]);
17036 oappend (names32[modrm.rm + add]);
17040 OP_E (bytemode, sizeflag);
17044 FXSAVE_Fixup (int bytemode, int sizeflag)
17046 /* Add proper suffix to "fxsave" and "fxrstor". */
17050 char *p = mnemonicendp;
17056 OP_M (bytemode, sizeflag);
17060 PCMPESTR_Fixup (int bytemode, int sizeflag)
17062 /* Add proper suffix to "{,v}pcmpestr{i,m}". */
17065 char *p = mnemonicendp;
17070 else if (sizeflag & SUFFIX_ALWAYS)
17077 OP_EX (bytemode, sizeflag);
17080 /* Display the destination register operand for instructions with
17084 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17087 const char **names;
17095 reg = vex.register_specifier;
17102 if (bytemode == vex_scalar_mode)
17104 oappend (names_xmm[reg]);
17108 switch (vex.length)
17115 case vex_vsib_q_w_dq_mode:
17116 case vex_vsib_q_w_d_mode:
17132 names = names_mask;
17146 case vex_vsib_q_w_dq_mode:
17147 case vex_vsib_q_w_d_mode:
17148 names = vex.w ? names_ymm : names_xmm;
17157 names = names_mask;
17160 /* See PR binutils/20893 for a reproducer. */
17172 oappend (names[reg]);
17175 /* Get the VEX immediate byte without moving codep. */
17177 static unsigned char
17178 get_vex_imm8 (int sizeflag, int opnum)
17180 int bytes_before_imm = 0;
17182 if (modrm.mod != 3)
17184 /* There are SIB/displacement bytes. */
17185 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
17187 /* 32/64 bit address mode */
17188 int base = modrm.rm;
17190 /* Check SIB byte. */
17193 FETCH_DATA (the_info, codep + 1);
17195 /* When decoding the third source, don't increase
17196 bytes_before_imm as this has already been incremented
17197 by one in OP_E_memory while decoding the second
17200 bytes_before_imm++;
17203 /* Don't increase bytes_before_imm when decoding the third source,
17204 it has already been incremented by OP_E_memory while decoding
17205 the second source operand. */
17211 /* When modrm.rm == 5 or modrm.rm == 4 and base in
17212 SIB == 5, there is a 4 byte displacement. */
17214 /* No displacement. */
17216 /* Fall through. */
17218 /* 4 byte displacement. */
17219 bytes_before_imm += 4;
17222 /* 1 byte displacement. */
17223 bytes_before_imm++;
17230 /* 16 bit address mode */
17231 /* Don't increase bytes_before_imm when decoding the third source,
17232 it has already been incremented by OP_E_memory while decoding
17233 the second source operand. */
17239 /* When modrm.rm == 6, there is a 2 byte displacement. */
17241 /* No displacement. */
17243 /* Fall through. */
17245 /* 2 byte displacement. */
17246 bytes_before_imm += 2;
17249 /* 1 byte displacement: when decoding the third source,
17250 don't increase bytes_before_imm as this has already
17251 been incremented by one in OP_E_memory while decoding
17252 the second source operand. */
17254 bytes_before_imm++;
17262 FETCH_DATA (the_info, codep + bytes_before_imm + 1);
17263 return codep [bytes_before_imm];
17267 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
17269 const char **names;
17271 if (reg == -1 && modrm.mod != 3)
17273 OP_E_memory (bytemode, sizeflag);
17285 else if (reg > 7 && address_mode != mode_64bit)
17289 switch (vex.length)
17300 oappend (names[reg]);
17304 OP_EX_VexImmW (int bytemode, int sizeflag)
17307 static unsigned char vex_imm8;
17309 if (vex_w_done == 0)
17313 /* Skip mod/rm byte. */
17317 vex_imm8 = get_vex_imm8 (sizeflag, 0);
17320 reg = vex_imm8 >> 4;
17322 OP_EX_VexReg (bytemode, sizeflag, reg);
17324 else if (vex_w_done == 1)
17329 reg = vex_imm8 >> 4;
17331 OP_EX_VexReg (bytemode, sizeflag, reg);
17335 /* Output the imm8 directly. */
17336 scratchbuf[0] = '$';
17337 print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
17338 oappend_maybe_intel (scratchbuf);
17339 scratchbuf[0] = '\0';
17345 OP_Vex_2src (int bytemode, int sizeflag)
17347 if (modrm.mod == 3)
17349 int reg = modrm.rm;
17353 oappend (names_xmm[reg]);
17358 && (bytemode == v_mode || bytemode == v_swap_mode))
17360 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
17361 used_prefixes |= (prefixes & PREFIX_DATA);
17363 OP_E (bytemode, sizeflag);
17368 OP_Vex_2src_1 (int bytemode, int sizeflag)
17370 if (modrm.mod == 3)
17372 /* Skip mod/rm byte. */
17378 oappend (names_xmm[vex.register_specifier]);
17380 OP_Vex_2src (bytemode, sizeflag);
17384 OP_Vex_2src_2 (int bytemode, int sizeflag)
17387 OP_Vex_2src (bytemode, sizeflag);
17389 oappend (names_xmm[vex.register_specifier]);
17393 OP_EX_VexW (int bytemode, int sizeflag)
17401 /* Skip mod/rm byte. */
17406 reg = get_vex_imm8 (sizeflag, 0) >> 4;
17411 reg = get_vex_imm8 (sizeflag, 1) >> 4;
17414 OP_EX_VexReg (bytemode, sizeflag, reg);
17418 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
17419 int sizeflag ATTRIBUTE_UNUSED)
17421 /* Skip the immediate byte and check for invalid bits. */
17422 FETCH_DATA (the_info, codep + 1);
17423 if (*codep++ & 0xf)
17428 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17431 const char **names;
17433 FETCH_DATA (the_info, codep + 1);
17436 if (bytemode != x_mode)
17443 if (reg > 7 && address_mode != mode_64bit)
17446 switch (vex.length)
17457 oappend (names[reg]);
17461 OP_XMM_VexW (int bytemode, int sizeflag)
17463 /* Turn off the REX.W bit since it is used for swapping operands
17466 OP_XMM (bytemode, sizeflag);
17470 OP_EX_Vex (int bytemode, int sizeflag)
17472 if (modrm.mod != 3)
17474 if (vex.register_specifier != 0)
17478 OP_EX (bytemode, sizeflag);
17482 OP_XMM_Vex (int bytemode, int sizeflag)
17484 if (modrm.mod != 3)
17486 if (vex.register_specifier != 0)
17490 OP_XMM (bytemode, sizeflag);
17494 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17496 switch (vex.length)
17499 mnemonicendp = stpcpy (obuf, "vzeroupper");
17502 mnemonicendp = stpcpy (obuf, "vzeroall");
17509 static struct op vex_cmp_op[] =
17511 { STRING_COMMA_LEN ("eq") },
17512 { STRING_COMMA_LEN ("lt") },
17513 { STRING_COMMA_LEN ("le") },
17514 { STRING_COMMA_LEN ("unord") },
17515 { STRING_COMMA_LEN ("neq") },
17516 { STRING_COMMA_LEN ("nlt") },
17517 { STRING_COMMA_LEN ("nle") },
17518 { STRING_COMMA_LEN ("ord") },
17519 { STRING_COMMA_LEN ("eq_uq") },
17520 { STRING_COMMA_LEN ("nge") },
17521 { STRING_COMMA_LEN ("ngt") },
17522 { STRING_COMMA_LEN ("false") },
17523 { STRING_COMMA_LEN ("neq_oq") },
17524 { STRING_COMMA_LEN ("ge") },
17525 { STRING_COMMA_LEN ("gt") },
17526 { STRING_COMMA_LEN ("true") },
17527 { STRING_COMMA_LEN ("eq_os") },
17528 { STRING_COMMA_LEN ("lt_oq") },
17529 { STRING_COMMA_LEN ("le_oq") },
17530 { STRING_COMMA_LEN ("unord_s") },
17531 { STRING_COMMA_LEN ("neq_us") },
17532 { STRING_COMMA_LEN ("nlt_uq") },
17533 { STRING_COMMA_LEN ("nle_uq") },
17534 { STRING_COMMA_LEN ("ord_s") },
17535 { STRING_COMMA_LEN ("eq_us") },
17536 { STRING_COMMA_LEN ("nge_uq") },
17537 { STRING_COMMA_LEN ("ngt_uq") },
17538 { STRING_COMMA_LEN ("false_os") },
17539 { STRING_COMMA_LEN ("neq_os") },
17540 { STRING_COMMA_LEN ("ge_oq") },
17541 { STRING_COMMA_LEN ("gt_oq") },
17542 { STRING_COMMA_LEN ("true_us") },
17546 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17548 unsigned int cmp_type;
17550 FETCH_DATA (the_info, codep + 1);
17551 cmp_type = *codep++ & 0xff;
17552 if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17555 char *p = mnemonicendp - 2;
17559 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17560 mnemonicendp += vex_cmp_op[cmp_type].len;
17564 /* We have a reserved extension byte. Output it directly. */
17565 scratchbuf[0] = '$';
17566 print_operand_value (scratchbuf + 1, 1, cmp_type);
17567 oappend_maybe_intel (scratchbuf);
17568 scratchbuf[0] = '\0';
17573 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17574 int sizeflag ATTRIBUTE_UNUSED)
17576 unsigned int cmp_type;
17581 FETCH_DATA (the_info, codep + 1);
17582 cmp_type = *codep++ & 0xff;
17583 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17584 If it's the case, print suffix, otherwise - print the immediate. */
17585 if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17590 char *p = mnemonicendp - 2;
17592 /* vpcmp* can have both one- and two-lettered suffix. */
17606 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17607 mnemonicendp += simd_cmp_op[cmp_type].len;
17611 /* We have a reserved extension byte. Output it directly. */
17612 scratchbuf[0] = '$';
17613 print_operand_value (scratchbuf + 1, 1, cmp_type);
17614 oappend_maybe_intel (scratchbuf);
17615 scratchbuf[0] = '\0';
17619 static const struct op pclmul_op[] =
17621 { STRING_COMMA_LEN ("lql") },
17622 { STRING_COMMA_LEN ("hql") },
17623 { STRING_COMMA_LEN ("lqh") },
17624 { STRING_COMMA_LEN ("hqh") }
17628 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17629 int sizeflag ATTRIBUTE_UNUSED)
17631 unsigned int pclmul_type;
17633 FETCH_DATA (the_info, codep + 1);
17634 pclmul_type = *codep++ & 0xff;
17635 switch (pclmul_type)
17646 if (pclmul_type < ARRAY_SIZE (pclmul_op))
17649 char *p = mnemonicendp - 3;
17654 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17655 mnemonicendp += pclmul_op[pclmul_type].len;
17659 /* We have a reserved extension byte. Output it directly. */
17660 scratchbuf[0] = '$';
17661 print_operand_value (scratchbuf + 1, 1, pclmul_type);
17662 oappend_maybe_intel (scratchbuf);
17663 scratchbuf[0] = '\0';
17668 MOVBE_Fixup (int bytemode, int sizeflag)
17670 /* Add proper suffix to "movbe". */
17671 char *p = mnemonicendp;
17680 if (sizeflag & SUFFIX_ALWAYS)
17686 if (sizeflag & DFLAG)
17690 used_prefixes |= (prefixes & PREFIX_DATA);
17695 oappend (INTERNAL_DISASSEMBLER_ERROR);
17702 OP_M (bytemode, sizeflag);
17706 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17709 const char **names;
17711 /* Skip mod/rm byte. */
17725 oappend (names[reg]);
17729 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17731 const char **names;
17738 oappend (names[vex.register_specifier]);
17742 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17745 || (bytemode != mask_mode && bytemode != mask_bd_mode))
17749 if ((rex & REX_R) != 0 || !vex.r)
17755 oappend (names_mask [modrm.reg]);
17759 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17762 || (bytemode != evex_rounding_mode
17763 && bytemode != evex_sae_mode))
17765 if (modrm.mod == 3 && vex.b)
17768 case evex_rounding_mode:
17769 oappend (names_rounding[vex.ll]);
17771 case evex_sae_mode: