1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of the GNU opcodes library.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
26 modified by John Hassey (hassey@dg-rtp.dg.com)
27 x86-64 support added by Jan Hubicka (jh@suse.cz)
28 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
30 /* The main tables describing the instructions is essentially a copy
31 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
32 Programmers Manual. Usually, there is a capital letter, followed
33 by a small letter. The capital letter tell the addressing mode,
34 and the small letter tells about the operand size. Refer to
35 the Intel manual for details. */
40 #include "opcode/i386.h"
41 #include "libiberty.h"
45 static int fetch_data (struct disassemble_info *, bfd_byte *);
46 static void ckprefix (void);
47 static const char *prefix_name (int, int);
48 static int print_insn (bfd_vma, disassemble_info *);
49 static void dofloat (int);
50 static void OP_ST (int, int);
51 static void OP_STi (int, int);
52 static int putop (const char *, int);
53 static void oappend (const char *);
54 static void append_seg (void);
55 static void OP_indirE (int, int);
56 static void print_operand_value (char *, int, bfd_vma);
57 static void OP_E_register (int, int);
58 static void OP_E_memory (int, int, int);
59 static void OP_E_extended (int, int, int);
60 static void print_displacement (char *, bfd_vma);
61 static void OP_E (int, int);
62 static void OP_G (int, int);
63 static bfd_vma get64 (void);
64 static bfd_signed_vma get32 (void);
65 static bfd_signed_vma get32s (void);
66 static int get16 (void);
67 static void set_op (bfd_vma, int);
68 static void OP_Skip_MODRM (int, int);
69 static void OP_REG (int, int);
70 static void OP_IMREG (int, int);
71 static void OP_I (int, int);
72 static void OP_I64 (int, int);
73 static void OP_sI (int, int);
74 static void OP_J (int, int);
75 static void OP_SEG (int, int);
76 static void OP_DIR (int, int);
77 static void OP_OFF (int, int);
78 static void OP_OFF64 (int, int);
79 static void ptr_reg (int, int);
80 static void OP_ESreg (int, int);
81 static void OP_DSreg (int, int);
82 static void OP_C (int, int);
83 static void OP_D (int, int);
84 static void OP_T (int, int);
85 static void OP_R (int, int);
86 static void OP_MMX (int, int);
87 static void OP_XMM (int, int);
88 static void OP_EM (int, int);
89 static void OP_EX (int, int);
90 static void OP_EMC (int,int);
91 static void OP_MXC (int,int);
92 static void OP_MS (int, int);
93 static void OP_XS (int, int);
94 static void OP_M (int, int);
95 static void OP_VEX (int, int);
96 static void OP_VEX_FMA (int, int);
97 static void OP_EX_Vex (int, int);
98 static void OP_EX_VexW (int, int);
99 static void OP_EX_VexImmW (int, int);
100 static void OP_XMM_Vex (int, int);
101 static void OP_XMM_VexW (int, int);
102 static void OP_REG_VexI4 (int, int);
103 static void PCLMUL_Fixup (int, int);
104 static void VEXI4_Fixup (int, int);
105 static void VZERO_Fixup (int, int);
106 static void VCMP_Fixup (int, int);
107 static void VPERMIL2_Fixup (int, int);
108 static void OP_0f07 (int, int);
109 static void OP_Monitor (int, int);
110 static void OP_Mwait (int, int);
111 static void NOP_Fixup1 (int, int);
112 static void NOP_Fixup2 (int, int);
113 static void OP_3DNowSuffix (int, int);
114 static void CMP_Fixup (int, int);
115 static void BadOp (void);
116 static void REP_Fixup (int, int);
117 static void CMPXCHG8B_Fixup (int, int);
118 static void XMM_Fixup (int, int);
119 static void CRC32_Fixup (int, int);
120 static void print_drex_arg (unsigned int, int, int);
121 static void OP_DREX4 (int, int);
122 static void OP_DREX3 (int, int);
123 static void OP_DREX_ICMP (int, int);
124 static void OP_DREX_FCMP (int, int);
125 static void MOVBE_Fixup (int, int);
128 /* Points to first byte not fetched. */
129 bfd_byte *max_fetched;
130 bfd_byte the_buffer[MAX_MNEM_SIZE];
143 enum address_mode address_mode;
145 /* Flags for the prefixes for the current instruction. See below. */
148 /* REX prefix the current instruction. See below. */
150 /* Bits of REX we've already used. */
152 /* Original REX prefix. */
153 static int rex_original;
154 /* REX bits in original REX prefix ignored. It may not be the same
155 as rex_original since some bits may not be ignored. */
156 static int rex_ignored;
157 /* Mark parts used in the REX prefix. When we are testing for
158 empty prefix (for 8bit register REX extension), just mask it
159 out. Otherwise test for REX bit is excuse for existence of REX
160 only in case value is nonzero. */
161 #define USED_REX(value) \
166 rex_used |= (value) | REX_OPCODE; \
169 rex_used |= REX_OPCODE; \
172 /* Special 'registers' for DREX handling */
173 #define DREX_REG_UNKNOWN 1000 /* not initialized */
174 #define DREX_REG_MEMORY 1001 /* use MODRM/SIB/OFFSET memory */
176 /* The DREX byte has the following fields:
177 Bits 7-4 -- DREX.Dest, xmm destination register
178 Bit 3 -- DREX.OC0, operand config bit defines operand order
179 Bit 2 -- DREX.R, equivalent to REX_R bit, to extend ModRM register
180 Bit 1 -- DREX.X, equivalent to REX_X bit, to extend SIB index field
181 Bit 0 -- DREX.W, equivalent to REX_B bit, to extend ModRM r/m field,
182 SIB base field, or opcode reg field. */
183 #define DREX_XMM(drex) ((drex >> 4) & 0xf)
184 #define DREX_OC0(drex) ((drex >> 3) & 0x1)
186 /* Flags for prefixes which we somehow handled when printing the
187 current instruction. */
188 static int used_prefixes;
190 /* Flags stored in PREFIXES. */
191 #define PREFIX_REPZ 1
192 #define PREFIX_REPNZ 2
193 #define PREFIX_LOCK 4
195 #define PREFIX_SS 0x10
196 #define PREFIX_DS 0x20
197 #define PREFIX_ES 0x40
198 #define PREFIX_FS 0x80
199 #define PREFIX_GS 0x100
200 #define PREFIX_DATA 0x200
201 #define PREFIX_ADDR 0x400
202 #define PREFIX_FWAIT 0x800
204 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
205 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
207 #define FETCH_DATA(info, addr) \
208 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
209 ? 1 : fetch_data ((info), (addr)))
212 fetch_data (struct disassemble_info *info, bfd_byte *addr)
215 struct dis_private *priv = (struct dis_private *) info->private_data;
216 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
218 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
219 status = (*info->read_memory_func) (start,
221 addr - priv->max_fetched,
227 /* If we did manage to read at least one byte, then
228 print_insn_i386 will do something sensible. Otherwise, print
229 an error. We do that here because this is where we know
231 if (priv->max_fetched == priv->the_buffer)
232 (*info->memory_error_func) (status, start, info);
233 longjmp (priv->bailout, 1);
236 priv->max_fetched = addr;
240 #define XX { NULL, 0 }
242 #define Eb { OP_E, b_mode }
243 #define EbS { OP_E, b_swap_mode }
244 #define Ev { OP_E, v_mode }
245 #define EvS { OP_E, v_swap_mode }
246 #define Ed { OP_E, d_mode }
247 #define Edq { OP_E, dq_mode }
248 #define Edqw { OP_E, dqw_mode }
249 #define Edqb { OP_E, dqb_mode }
250 #define Edqd { OP_E, dqd_mode }
251 #define Eq { OP_E, q_mode }
252 #define indirEv { OP_indirE, stack_v_mode }
253 #define indirEp { OP_indirE, f_mode }
254 #define stackEv { OP_E, stack_v_mode }
255 #define Em { OP_E, m_mode }
256 #define Ew { OP_E, w_mode }
257 #define M { OP_M, 0 } /* lea, lgdt, etc. */
258 #define Ma { OP_M, a_mode }
259 #define Mb { OP_M, b_mode }
260 #define Md { OP_M, d_mode }
261 #define Mo { OP_M, o_mode }
262 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
263 #define Mq { OP_M, q_mode }
264 #define Mx { OP_M, x_mode }
265 #define Mxmm { OP_M, xmm_mode }
266 #define Gb { OP_G, b_mode }
267 #define Gv { OP_G, v_mode }
268 #define Gd { OP_G, d_mode }
269 #define Gdq { OP_G, dq_mode }
270 #define Gm { OP_G, m_mode }
271 #define Gw { OP_G, w_mode }
272 #define Rd { OP_R, d_mode }
273 #define Rm { OP_R, m_mode }
274 #define Ib { OP_I, b_mode }
275 #define sIb { OP_sI, b_mode } /* sign extened byte */
276 #define Iv { OP_I, v_mode }
277 #define Iq { OP_I, q_mode }
278 #define Iv64 { OP_I64, v_mode }
279 #define Iw { OP_I, w_mode }
280 #define I1 { OP_I, const_1_mode }
281 #define Jb { OP_J, b_mode }
282 #define Jv { OP_J, v_mode }
283 #define Cm { OP_C, m_mode }
284 #define Dm { OP_D, m_mode }
285 #define Td { OP_T, d_mode }
286 #define Skip_MODRM { OP_Skip_MODRM, 0 }
288 #define RMeAX { OP_REG, eAX_reg }
289 #define RMeBX { OP_REG, eBX_reg }
290 #define RMeCX { OP_REG, eCX_reg }
291 #define RMeDX { OP_REG, eDX_reg }
292 #define RMeSP { OP_REG, eSP_reg }
293 #define RMeBP { OP_REG, eBP_reg }
294 #define RMeSI { OP_REG, eSI_reg }
295 #define RMeDI { OP_REG, eDI_reg }
296 #define RMrAX { OP_REG, rAX_reg }
297 #define RMrBX { OP_REG, rBX_reg }
298 #define RMrCX { OP_REG, rCX_reg }
299 #define RMrDX { OP_REG, rDX_reg }
300 #define RMrSP { OP_REG, rSP_reg }
301 #define RMrBP { OP_REG, rBP_reg }
302 #define RMrSI { OP_REG, rSI_reg }
303 #define RMrDI { OP_REG, rDI_reg }
304 #define RMAL { OP_REG, al_reg }
305 #define RMAL { OP_REG, al_reg }
306 #define RMCL { OP_REG, cl_reg }
307 #define RMDL { OP_REG, dl_reg }
308 #define RMBL { OP_REG, bl_reg }
309 #define RMAH { OP_REG, ah_reg }
310 #define RMCH { OP_REG, ch_reg }
311 #define RMDH { OP_REG, dh_reg }
312 #define RMBH { OP_REG, bh_reg }
313 #define RMAX { OP_REG, ax_reg }
314 #define RMDX { OP_REG, dx_reg }
316 #define eAX { OP_IMREG, eAX_reg }
317 #define eBX { OP_IMREG, eBX_reg }
318 #define eCX { OP_IMREG, eCX_reg }
319 #define eDX { OP_IMREG, eDX_reg }
320 #define eSP { OP_IMREG, eSP_reg }
321 #define eBP { OP_IMREG, eBP_reg }
322 #define eSI { OP_IMREG, eSI_reg }
323 #define eDI { OP_IMREG, eDI_reg }
324 #define AL { OP_IMREG, al_reg }
325 #define CL { OP_IMREG, cl_reg }
326 #define DL { OP_IMREG, dl_reg }
327 #define BL { OP_IMREG, bl_reg }
328 #define AH { OP_IMREG, ah_reg }
329 #define CH { OP_IMREG, ch_reg }
330 #define DH { OP_IMREG, dh_reg }
331 #define BH { OP_IMREG, bh_reg }
332 #define AX { OP_IMREG, ax_reg }
333 #define DX { OP_IMREG, dx_reg }
334 #define zAX { OP_IMREG, z_mode_ax_reg }
335 #define indirDX { OP_IMREG, indir_dx_reg }
337 #define Sw { OP_SEG, w_mode }
338 #define Sv { OP_SEG, v_mode }
339 #define Ap { OP_DIR, 0 }
340 #define Ob { OP_OFF64, b_mode }
341 #define Ov { OP_OFF64, v_mode }
342 #define Xb { OP_DSreg, eSI_reg }
343 #define Xv { OP_DSreg, eSI_reg }
344 #define Xz { OP_DSreg, eSI_reg }
345 #define Yb { OP_ESreg, eDI_reg }
346 #define Yv { OP_ESreg, eDI_reg }
347 #define DSBX { OP_DSreg, eBX_reg }
349 #define es { OP_REG, es_reg }
350 #define ss { OP_REG, ss_reg }
351 #define cs { OP_REG, cs_reg }
352 #define ds { OP_REG, ds_reg }
353 #define fs { OP_REG, fs_reg }
354 #define gs { OP_REG, gs_reg }
356 #define MX { OP_MMX, 0 }
357 #define XM { OP_XMM, 0 }
358 #define XMM { OP_XMM, xmm_mode }
359 #define EM { OP_EM, v_mode }
360 #define EMS { OP_EM, v_swap_mode }
361 #define EMd { OP_EM, d_mode }
362 #define EMx { OP_EM, x_mode }
363 #define EXw { OP_EX, w_mode }
364 #define EXd { OP_EX, d_mode }
365 #define EXdS { OP_EX, d_swap_mode }
366 #define EXq { OP_EX, q_mode }
367 #define EXqS { OP_EX, q_swap_mode }
368 #define EXx { OP_EX, x_mode }
369 #define EXxS { OP_EX, x_swap_mode }
370 #define EXxmm { OP_EX, xmm_mode }
371 #define EXxmmq { OP_EX, xmmq_mode }
372 #define EXymmq { OP_EX, ymmq_mode }
373 #define MS { OP_MS, v_mode }
374 #define XS { OP_XS, v_mode }
375 #define EMCq { OP_EMC, q_mode }
376 #define MXC { OP_MXC, 0 }
377 #define OPSUF { OP_3DNowSuffix, 0 }
378 #define CMP { CMP_Fixup, 0 }
379 #define XMM0 { XMM_Fixup, 0 }
381 #define Vex { OP_VEX, vex_mode }
382 #define Vex128 { OP_VEX, vex128_mode }
383 #define Vex256 { OP_VEX, vex256_mode }
384 #define VexI4 { VEXI4_Fixup, 0}
385 #define VexFMA { OP_VEX_FMA, vex_mode }
386 #define Vex128FMA { OP_VEX_FMA, vex128_mode }
387 #define EXdVex { OP_EX_Vex, d_mode }
388 #define EXdVexS { OP_EX_Vex, d_swap_mode }
389 #define EXqVex { OP_EX_Vex, q_mode }
390 #define EXqVexS { OP_EX_Vex, q_swap_mode }
391 #define EXVexW { OP_EX_VexW, x_mode }
392 #define EXdVexW { OP_EX_VexW, d_mode }
393 #define EXqVexW { OP_EX_VexW, q_mode }
394 #define EXVexImmW { OP_EX_VexImmW, x_mode }
395 #define XMVex { OP_XMM_Vex, 0 }
396 #define XMVexW { OP_XMM_VexW, 0 }
397 #define XMVexI4 { OP_REG_VexI4, x_mode }
398 #define PCLMUL { PCLMUL_Fixup, 0 }
399 #define VZERO { VZERO_Fixup, 0 }
400 #define VCMP { VCMP_Fixup, 0 }
401 #define VPERMIL2 { VPERMIL2_Fixup, 0 }
403 /* Used handle "rep" prefix for string instructions. */
404 #define Xbr { REP_Fixup, eSI_reg }
405 #define Xvr { REP_Fixup, eSI_reg }
406 #define Ybr { REP_Fixup, eDI_reg }
407 #define Yvr { REP_Fixup, eDI_reg }
408 #define Yzr { REP_Fixup, eDI_reg }
409 #define indirDXr { REP_Fixup, indir_dx_reg }
410 #define ALr { REP_Fixup, al_reg }
411 #define eAXr { REP_Fixup, eAX_reg }
413 #define cond_jump_flag { NULL, cond_jump_mode }
414 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
416 /* bits in sizeflag */
417 #define SUFFIX_ALWAYS 4
423 /* byte operand with operand swapped */
424 #define b_swap_mode (b_mode + 1)
425 /* operand size depends on prefixes */
426 #define v_mode (b_swap_mode + 1)
427 /* operand size depends on prefixes with operand swapped */
428 #define v_swap_mode (v_mode + 1)
430 #define w_mode (v_swap_mode + 1)
431 /* double word operand */
432 #define d_mode (w_mode + 1)
433 /* double word operand with operand swapped */
434 #define d_swap_mode (d_mode + 1)
435 /* quad word operand */
436 #define q_mode (d_swap_mode + 1)
437 /* quad word operand with operand swapped */
438 #define q_swap_mode (q_mode + 1)
439 /* ten-byte operand */
440 #define t_mode (q_swap_mode + 1)
441 /* 16-byte XMM or 32-byte YMM operand */
442 #define x_mode (t_mode + 1)
443 /* 16-byte XMM or 32-byte YMM operand with operand swapped */
444 #define x_swap_mode (x_mode + 1)
445 /* 16-byte XMM operand */
446 #define xmm_mode (x_swap_mode + 1)
447 /* 16-byte XMM or quad word operand */
448 #define xmmq_mode (xmm_mode + 1)
449 /* 32-byte YMM or quad word operand */
450 #define ymmq_mode (xmmq_mode + 1)
451 /* d_mode in 32bit, q_mode in 64bit mode. */
452 #define m_mode (ymmq_mode + 1)
453 /* pair of v_mode operands */
454 #define a_mode (m_mode + 1)
455 #define cond_jump_mode (a_mode + 1)
456 #define loop_jcxz_mode (cond_jump_mode + 1)
457 /* operand size depends on REX prefixes. */
458 #define dq_mode (loop_jcxz_mode + 1)
459 /* registers like dq_mode, memory like w_mode. */
460 #define dqw_mode (dq_mode + 1)
461 /* 4- or 6-byte pointer operand */
462 #define f_mode (dqw_mode + 1)
463 #define const_1_mode (f_mode + 1)
464 /* v_mode for stack-related opcodes. */
465 #define stack_v_mode (const_1_mode + 1)
466 /* non-quad operand size depends on prefixes */
467 #define z_mode (stack_v_mode + 1)
468 /* 16-byte operand */
469 #define o_mode (z_mode + 1)
470 /* registers like dq_mode, memory like b_mode. */
471 #define dqb_mode (o_mode + 1)
472 /* registers like dq_mode, memory like d_mode. */
473 #define dqd_mode (dqb_mode + 1)
474 /* normal vex mode */
475 #define vex_mode (dqd_mode + 1)
476 /* 128bit vex mode */
477 #define vex128_mode (vex_mode + 1)
478 /* 256bit vex mode */
479 #define vex256_mode (vex128_mode + 1)
481 #define es_reg (vex256_mode + 1)
482 #define cs_reg (es_reg + 1)
483 #define ss_reg (cs_reg + 1)
484 #define ds_reg (ss_reg + 1)
485 #define fs_reg (ds_reg + 1)
486 #define gs_reg (fs_reg + 1)
488 #define eAX_reg (gs_reg + 1)
489 #define eCX_reg (eAX_reg + 1)
490 #define eDX_reg (eCX_reg + 1)
491 #define eBX_reg (eDX_reg + 1)
492 #define eSP_reg (eBX_reg + 1)
493 #define eBP_reg (eSP_reg + 1)
494 #define eSI_reg (eBP_reg + 1)
495 #define eDI_reg (eSI_reg + 1)
497 #define al_reg (eDI_reg + 1)
498 #define cl_reg (al_reg + 1)
499 #define dl_reg (cl_reg + 1)
500 #define bl_reg (dl_reg + 1)
501 #define ah_reg (bl_reg + 1)
502 #define ch_reg (ah_reg + 1)
503 #define dh_reg (ch_reg + 1)
504 #define bh_reg (dh_reg + 1)
506 #define ax_reg (bh_reg + 1)
507 #define cx_reg (ax_reg + 1)
508 #define dx_reg (cx_reg + 1)
509 #define bx_reg (dx_reg + 1)
510 #define sp_reg (bx_reg + 1)
511 #define bp_reg (sp_reg + 1)
512 #define si_reg (bp_reg + 1)
513 #define di_reg (si_reg + 1)
515 #define rAX_reg (di_reg + 1)
516 #define rCX_reg (rAX_reg + 1)
517 #define rDX_reg (rCX_reg + 1)
518 #define rBX_reg (rDX_reg + 1)
519 #define rSP_reg (rBX_reg + 1)
520 #define rBP_reg (rSP_reg + 1)
521 #define rSI_reg (rBP_reg + 1)
522 #define rDI_reg (rSI_reg + 1)
524 #define z_mode_ax_reg (rDI_reg + 1)
525 #define indir_dx_reg (z_mode_ax_reg + 1)
527 #define MAX_BYTEMODE indir_dx_reg
529 /* Flags that are OR'ed into the bytemode field to pass extra
531 #define DREX_OC1 0x10000 /* OC1 bit set */
532 #define DREX_NO_OC0 0x20000 /* OC0 bit not used */
533 #define DREX_MASK 0x40000 /* mask to delete */
535 #if MAX_BYTEMODE >= DREX_OC1
536 #error MAX_BYTEMODE must be less than DREX_OC1
540 #define USE_REG_TABLE (FLOATCODE + 1)
541 #define USE_MOD_TABLE (USE_REG_TABLE + 1)
542 #define USE_RM_TABLE (USE_MOD_TABLE + 1)
543 #define USE_PREFIX_TABLE (USE_RM_TABLE + 1)
544 #define USE_X86_64_TABLE (USE_PREFIX_TABLE + 1)
545 #define USE_3BYTE_TABLE (USE_X86_64_TABLE + 1)
546 #define USE_VEX_C4_TABLE (USE_3BYTE_TABLE + 1)
547 #define USE_VEX_C5_TABLE (USE_VEX_C4_TABLE + 1)
548 #define USE_VEX_LEN_TABLE (USE_VEX_C5_TABLE + 1)
550 #define FLOAT NULL, { { NULL, FLOATCODE } }
552 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
553 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
554 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
555 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
556 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
557 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
558 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
559 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
560 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
561 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
564 #define REG_81 (REG_80 + 1)
565 #define REG_82 (REG_81 + 1)
566 #define REG_8F (REG_82 + 1)
567 #define REG_C0 (REG_8F + 1)
568 #define REG_C1 (REG_C0 + 1)
569 #define REG_C6 (REG_C1 + 1)
570 #define REG_C7 (REG_C6 + 1)
571 #define REG_D0 (REG_C7 + 1)
572 #define REG_D1 (REG_D0 + 1)
573 #define REG_D2 (REG_D1 + 1)
574 #define REG_D3 (REG_D2 + 1)
575 #define REG_F6 (REG_D3 + 1)
576 #define REG_F7 (REG_F6 + 1)
577 #define REG_FE (REG_F7 + 1)
578 #define REG_FF (REG_FE + 1)
579 #define REG_0F00 (REG_FF + 1)
580 #define REG_0F01 (REG_0F00 + 1)
581 #define REG_0F0D (REG_0F01 + 1)
582 #define REG_0F18 (REG_0F0D + 1)
583 #define REG_0F71 (REG_0F18 + 1)
584 #define REG_0F72 (REG_0F71 + 1)
585 #define REG_0F73 (REG_0F72 + 1)
586 #define REG_0FA6 (REG_0F73 + 1)
587 #define REG_0FA7 (REG_0FA6 + 1)
588 #define REG_0FAE (REG_0FA7 + 1)
589 #define REG_0FBA (REG_0FAE + 1)
590 #define REG_0FC7 (REG_0FBA + 1)
591 #define REG_VEX_71 (REG_0FC7 + 1)
592 #define REG_VEX_72 (REG_VEX_71 + 1)
593 #define REG_VEX_73 (REG_VEX_72 + 1)
594 #define REG_VEX_AE (REG_VEX_73 + 1)
597 #define MOD_0F01_REG_0 (MOD_8D + 1)
598 #define MOD_0F01_REG_1 (MOD_0F01_REG_0 + 1)
599 #define MOD_0F01_REG_2 (MOD_0F01_REG_1 + 1)
600 #define MOD_0F01_REG_3 (MOD_0F01_REG_2 + 1)
601 #define MOD_0F01_REG_7 (MOD_0F01_REG_3 + 1)
602 #define MOD_0F12_PREFIX_0 (MOD_0F01_REG_7 + 1)
603 #define MOD_0F13 (MOD_0F12_PREFIX_0 + 1)
604 #define MOD_0F16_PREFIX_0 (MOD_0F13 + 1)
605 #define MOD_0F17 (MOD_0F16_PREFIX_0 + 1)
606 #define MOD_0F18_REG_0 (MOD_0F17 + 1)
607 #define MOD_0F18_REG_1 (MOD_0F18_REG_0 + 1)
608 #define MOD_0F18_REG_2 (MOD_0F18_REG_1 + 1)
609 #define MOD_0F18_REG_3 (MOD_0F18_REG_2 + 1)
610 #define MOD_0F20 (MOD_0F18_REG_3 + 1)
611 #define MOD_0F21 (MOD_0F20 + 1)
612 #define MOD_0F22 (MOD_0F21 + 1)
613 #define MOD_0F23 (MOD_0F22 + 1)
614 #define MOD_0F24 (MOD_0F23 + 1)
615 #define MOD_0F26 (MOD_0F24 + 1)
616 #define MOD_0F2B_PREFIX_0 (MOD_0F26 + 1)
617 #define MOD_0F2B_PREFIX_1 (MOD_0F2B_PREFIX_0 + 1)
618 #define MOD_0F2B_PREFIX_2 (MOD_0F2B_PREFIX_1 + 1)
619 #define MOD_0F2B_PREFIX_3 (MOD_0F2B_PREFIX_2 + 1)
620 #define MOD_0F51 (MOD_0F2B_PREFIX_3 + 1)
621 #define MOD_0F71_REG_2 (MOD_0F51 + 1)
622 #define MOD_0F71_REG_4 (MOD_0F71_REG_2 + 1)
623 #define MOD_0F71_REG_6 (MOD_0F71_REG_4 + 1)
624 #define MOD_0F72_REG_2 (MOD_0F71_REG_6 + 1)
625 #define MOD_0F72_REG_4 (MOD_0F72_REG_2 + 1)
626 #define MOD_0F72_REG_6 (MOD_0F72_REG_4 + 1)
627 #define MOD_0F73_REG_2 (MOD_0F72_REG_6 + 1)
628 #define MOD_0F73_REG_3 (MOD_0F73_REG_2 + 1)
629 #define MOD_0F73_REG_6 (MOD_0F73_REG_3 + 1)
630 #define MOD_0F73_REG_7 (MOD_0F73_REG_6 + 1)
631 #define MOD_0FAE_REG_0 (MOD_0F73_REG_7 + 1)
632 #define MOD_0FAE_REG_1 (MOD_0FAE_REG_0 + 1)
633 #define MOD_0FAE_REG_2 (MOD_0FAE_REG_1 + 1)
634 #define MOD_0FAE_REG_3 (MOD_0FAE_REG_2 + 1)
635 #define MOD_0FAE_REG_4 (MOD_0FAE_REG_3 + 1)
636 #define MOD_0FAE_REG_5 (MOD_0FAE_REG_4 + 1)
637 #define MOD_0FAE_REG_6 (MOD_0FAE_REG_5 + 1)
638 #define MOD_0FAE_REG_7 (MOD_0FAE_REG_6 + 1)
639 #define MOD_0FB2 (MOD_0FAE_REG_7 + 1)
640 #define MOD_0FB4 (MOD_0FB2 + 1)
641 #define MOD_0FB5 (MOD_0FB4 + 1)
642 #define MOD_0FC7_REG_6 (MOD_0FB5 + 1)
643 #define MOD_0FC7_REG_7 (MOD_0FC7_REG_6 + 1)
644 #define MOD_0FD7 (MOD_0FC7_REG_7 + 1)
645 #define MOD_0FE7_PREFIX_2 (MOD_0FD7 + 1)
646 #define MOD_0FF0_PREFIX_3 (MOD_0FE7_PREFIX_2 + 1)
647 #define MOD_0F382A_PREFIX_2 (MOD_0FF0_PREFIX_3 + 1)
648 #define MOD_62_32BIT (MOD_0F382A_PREFIX_2 + 1)
649 #define MOD_C4_32BIT (MOD_62_32BIT + 1)
650 #define MOD_C5_32BIT (MOD_C4_32BIT + 1)
651 #define MOD_VEX_12_PREFIX_0 (MOD_C5_32BIT + 1)
652 #define MOD_VEX_13 (MOD_VEX_12_PREFIX_0 + 1)
653 #define MOD_VEX_16_PREFIX_0 (MOD_VEX_13 + 1)
654 #define MOD_VEX_17 (MOD_VEX_16_PREFIX_0 + 1)
655 #define MOD_VEX_2B (MOD_VEX_17 + 1)
656 #define MOD_VEX_51 (MOD_VEX_2B + 1)
657 #define MOD_VEX_71_REG_2 (MOD_VEX_51 + 1)
658 #define MOD_VEX_71_REG_4 (MOD_VEX_71_REG_2 + 1)
659 #define MOD_VEX_71_REG_6 (MOD_VEX_71_REG_4 + 1)
660 #define MOD_VEX_72_REG_2 (MOD_VEX_71_REG_6 + 1)
661 #define MOD_VEX_72_REG_4 (MOD_VEX_72_REG_2 + 1)
662 #define MOD_VEX_72_REG_6 (MOD_VEX_72_REG_4 + 1)
663 #define MOD_VEX_73_REG_2 (MOD_VEX_72_REG_6 + 1)
664 #define MOD_VEX_73_REG_3 (MOD_VEX_73_REG_2 + 1)
665 #define MOD_VEX_73_REG_6 (MOD_VEX_73_REG_3 + 1)
666 #define MOD_VEX_73_REG_7 (MOD_VEX_73_REG_6 + 1)
667 #define MOD_VEX_AE_REG_2 (MOD_VEX_73_REG_7 + 1)
668 #define MOD_VEX_AE_REG_3 (MOD_VEX_AE_REG_2 + 1)
669 #define MOD_VEX_D7_PREFIX_2 (MOD_VEX_AE_REG_3 + 1)
670 #define MOD_VEX_E7_PREFIX_2 (MOD_VEX_D7_PREFIX_2 + 1)
671 #define MOD_VEX_F0_PREFIX_3 (MOD_VEX_E7_PREFIX_2 + 1)
672 #define MOD_VEX_3818_PREFIX_2 (MOD_VEX_F0_PREFIX_3 + 1)
673 #define MOD_VEX_3819_PREFIX_2 (MOD_VEX_3818_PREFIX_2 + 1)
674 #define MOD_VEX_381A_PREFIX_2 (MOD_VEX_3819_PREFIX_2 + 1)
675 #define MOD_VEX_382A_PREFIX_2 (MOD_VEX_381A_PREFIX_2 + 1)
676 #define MOD_VEX_382C_PREFIX_2 (MOD_VEX_382A_PREFIX_2 + 1)
677 #define MOD_VEX_382D_PREFIX_2 (MOD_VEX_382C_PREFIX_2 + 1)
678 #define MOD_VEX_382E_PREFIX_2 (MOD_VEX_382D_PREFIX_2 + 1)
679 #define MOD_VEX_382F_PREFIX_2 (MOD_VEX_382E_PREFIX_2 + 1)
681 #define RM_0F01_REG_0 0
682 #define RM_0F01_REG_1 (RM_0F01_REG_0 + 1)
683 #define RM_0F01_REG_2 (RM_0F01_REG_1 + 1)
684 #define RM_0F01_REG_3 (RM_0F01_REG_2 + 1)
685 #define RM_0F01_REG_7 (RM_0F01_REG_3 + 1)
686 #define RM_0FAE_REG_5 (RM_0F01_REG_7 + 1)
687 #define RM_0FAE_REG_6 (RM_0FAE_REG_5 + 1)
688 #define RM_0FAE_REG_7 (RM_0FAE_REG_6 + 1)
691 #define PREFIX_0F10 (PREFIX_90 + 1)
692 #define PREFIX_0F11 (PREFIX_0F10 + 1)
693 #define PREFIX_0F12 (PREFIX_0F11 + 1)
694 #define PREFIX_0F16 (PREFIX_0F12 + 1)
695 #define PREFIX_0F2A (PREFIX_0F16 + 1)
696 #define PREFIX_0F2B (PREFIX_0F2A + 1)
697 #define PREFIX_0F2C (PREFIX_0F2B + 1)
698 #define PREFIX_0F2D (PREFIX_0F2C + 1)
699 #define PREFIX_0F2E (PREFIX_0F2D + 1)
700 #define PREFIX_0F2F (PREFIX_0F2E + 1)
701 #define PREFIX_0F51 (PREFIX_0F2F + 1)
702 #define PREFIX_0F52 (PREFIX_0F51 + 1)
703 #define PREFIX_0F53 (PREFIX_0F52 + 1)
704 #define PREFIX_0F58 (PREFIX_0F53 + 1)
705 #define PREFIX_0F59 (PREFIX_0F58 + 1)
706 #define PREFIX_0F5A (PREFIX_0F59 + 1)
707 #define PREFIX_0F5B (PREFIX_0F5A + 1)
708 #define PREFIX_0F5C (PREFIX_0F5B + 1)
709 #define PREFIX_0F5D (PREFIX_0F5C + 1)
710 #define PREFIX_0F5E (PREFIX_0F5D + 1)
711 #define PREFIX_0F5F (PREFIX_0F5E + 1)
712 #define PREFIX_0F60 (PREFIX_0F5F + 1)
713 #define PREFIX_0F61 (PREFIX_0F60 + 1)
714 #define PREFIX_0F62 (PREFIX_0F61 + 1)
715 #define PREFIX_0F6C (PREFIX_0F62 + 1)
716 #define PREFIX_0F6D (PREFIX_0F6C + 1)
717 #define PREFIX_0F6F (PREFIX_0F6D + 1)
718 #define PREFIX_0F70 (PREFIX_0F6F + 1)
719 #define PREFIX_0F73_REG_3 (PREFIX_0F70 + 1)
720 #define PREFIX_0F73_REG_7 (PREFIX_0F73_REG_3 + 1)
721 #define PREFIX_0F78 (PREFIX_0F73_REG_7 + 1)
722 #define PREFIX_0F79 (PREFIX_0F78 + 1)
723 #define PREFIX_0F7C (PREFIX_0F79 + 1)
724 #define PREFIX_0F7D (PREFIX_0F7C + 1)
725 #define PREFIX_0F7E (PREFIX_0F7D + 1)
726 #define PREFIX_0F7F (PREFIX_0F7E + 1)
727 #define PREFIX_0FB8 (PREFIX_0F7F + 1)
728 #define PREFIX_0FBD (PREFIX_0FB8 + 1)
729 #define PREFIX_0FC2 (PREFIX_0FBD + 1)
730 #define PREFIX_0FC3 (PREFIX_0FC2 + 1)
731 #define PREFIX_0FC7_REG_6 (PREFIX_0FC3 + 1)
732 #define PREFIX_0FD0 (PREFIX_0FC7_REG_6 + 1)
733 #define PREFIX_0FD6 (PREFIX_0FD0 + 1)
734 #define PREFIX_0FE6 (PREFIX_0FD6 + 1)
735 #define PREFIX_0FE7 (PREFIX_0FE6 + 1)
736 #define PREFIX_0FF0 (PREFIX_0FE7 + 1)
737 #define PREFIX_0FF7 (PREFIX_0FF0 + 1)
738 #define PREFIX_0F3810 (PREFIX_0FF7 + 1)
739 #define PREFIX_0F3814 (PREFIX_0F3810 + 1)
740 #define PREFIX_0F3815 (PREFIX_0F3814 + 1)
741 #define PREFIX_0F3817 (PREFIX_0F3815 + 1)
742 #define PREFIX_0F3820 (PREFIX_0F3817 + 1)
743 #define PREFIX_0F3821 (PREFIX_0F3820 + 1)
744 #define PREFIX_0F3822 (PREFIX_0F3821 + 1)
745 #define PREFIX_0F3823 (PREFIX_0F3822 + 1)
746 #define PREFIX_0F3824 (PREFIX_0F3823 + 1)
747 #define PREFIX_0F3825 (PREFIX_0F3824 + 1)
748 #define PREFIX_0F3828 (PREFIX_0F3825 + 1)
749 #define PREFIX_0F3829 (PREFIX_0F3828 + 1)
750 #define PREFIX_0F382A (PREFIX_0F3829 + 1)
751 #define PREFIX_0F382B (PREFIX_0F382A + 1)
752 #define PREFIX_0F3830 (PREFIX_0F382B + 1)
753 #define PREFIX_0F3831 (PREFIX_0F3830 + 1)
754 #define PREFIX_0F3832 (PREFIX_0F3831 + 1)
755 #define PREFIX_0F3833 (PREFIX_0F3832 + 1)
756 #define PREFIX_0F3834 (PREFIX_0F3833 + 1)
757 #define PREFIX_0F3835 (PREFIX_0F3834 + 1)
758 #define PREFIX_0F3837 (PREFIX_0F3835 + 1)
759 #define PREFIX_0F3838 (PREFIX_0F3837 + 1)
760 #define PREFIX_0F3839 (PREFIX_0F3838 + 1)
761 #define PREFIX_0F383A (PREFIX_0F3839 + 1)
762 #define PREFIX_0F383B (PREFIX_0F383A + 1)
763 #define PREFIX_0F383C (PREFIX_0F383B + 1)
764 #define PREFIX_0F383D (PREFIX_0F383C + 1)
765 #define PREFIX_0F383E (PREFIX_0F383D + 1)
766 #define PREFIX_0F383F (PREFIX_0F383E + 1)
767 #define PREFIX_0F3840 (PREFIX_0F383F + 1)
768 #define PREFIX_0F3841 (PREFIX_0F3840 + 1)
769 #define PREFIX_0F3880 (PREFIX_0F3841 + 1)
770 #define PREFIX_0F3881 (PREFIX_0F3880 + 1)
771 #define PREFIX_0F38DB (PREFIX_0F3881 + 1)
772 #define PREFIX_0F38DC (PREFIX_0F38DB + 1)
773 #define PREFIX_0F38DD (PREFIX_0F38DC + 1)
774 #define PREFIX_0F38DE (PREFIX_0F38DD + 1)
775 #define PREFIX_0F38DF (PREFIX_0F38DE + 1)
776 #define PREFIX_0F38F0 (PREFIX_0F38DF + 1)
777 #define PREFIX_0F38F1 (PREFIX_0F38F0 + 1)
778 #define PREFIX_0F3A08 (PREFIX_0F38F1 + 1)
779 #define PREFIX_0F3A09 (PREFIX_0F3A08 + 1)
780 #define PREFIX_0F3A0A (PREFIX_0F3A09 + 1)
781 #define PREFIX_0F3A0B (PREFIX_0F3A0A + 1)
782 #define PREFIX_0F3A0C (PREFIX_0F3A0B + 1)
783 #define PREFIX_0F3A0D (PREFIX_0F3A0C + 1)
784 #define PREFIX_0F3A0E (PREFIX_0F3A0D + 1)
785 #define PREFIX_0F3A14 (PREFIX_0F3A0E + 1)
786 #define PREFIX_0F3A15 (PREFIX_0F3A14 + 1)
787 #define PREFIX_0F3A16 (PREFIX_0F3A15 + 1)
788 #define PREFIX_0F3A17 (PREFIX_0F3A16 + 1)
789 #define PREFIX_0F3A20 (PREFIX_0F3A17 + 1)
790 #define PREFIX_0F3A21 (PREFIX_0F3A20 + 1)
791 #define PREFIX_0F3A22 (PREFIX_0F3A21 + 1)
792 #define PREFIX_0F3A40 (PREFIX_0F3A22 + 1)
793 #define PREFIX_0F3A41 (PREFIX_0F3A40 + 1)
794 #define PREFIX_0F3A42 (PREFIX_0F3A41 + 1)
795 #define PREFIX_0F3A44 (PREFIX_0F3A42 + 1)
796 #define PREFIX_0F3A60 (PREFIX_0F3A44 + 1)
797 #define PREFIX_0F3A61 (PREFIX_0F3A60 + 1)
798 #define PREFIX_0F3A62 (PREFIX_0F3A61 + 1)
799 #define PREFIX_0F3A63 (PREFIX_0F3A62 + 1)
800 #define PREFIX_0F3ADF (PREFIX_0F3A63 + 1)
801 #define PREFIX_VEX_10 (PREFIX_0F3ADF + 1)
802 #define PREFIX_VEX_11 (PREFIX_VEX_10 + 1)
803 #define PREFIX_VEX_12 (PREFIX_VEX_11 + 1)
804 #define PREFIX_VEX_16 (PREFIX_VEX_12 + 1)
805 #define PREFIX_VEX_2A (PREFIX_VEX_16 + 1)
806 #define PREFIX_VEX_2C (PREFIX_VEX_2A + 1)
807 #define PREFIX_VEX_2D (PREFIX_VEX_2C + 1)
808 #define PREFIX_VEX_2E (PREFIX_VEX_2D + 1)
809 #define PREFIX_VEX_2F (PREFIX_VEX_2E + 1)
810 #define PREFIX_VEX_51 (PREFIX_VEX_2F + 1)
811 #define PREFIX_VEX_52 (PREFIX_VEX_51 + 1)
812 #define PREFIX_VEX_53 (PREFIX_VEX_52 + 1)
813 #define PREFIX_VEX_58 (PREFIX_VEX_53 + 1)
814 #define PREFIX_VEX_59 (PREFIX_VEX_58 + 1)
815 #define PREFIX_VEX_5A (PREFIX_VEX_59 + 1)
816 #define PREFIX_VEX_5B (PREFIX_VEX_5A + 1)
817 #define PREFIX_VEX_5C (PREFIX_VEX_5B + 1)
818 #define PREFIX_VEX_5D (PREFIX_VEX_5C + 1)
819 #define PREFIX_VEX_5E (PREFIX_VEX_5D + 1)
820 #define PREFIX_VEX_5F (PREFIX_VEX_5E + 1)
821 #define PREFIX_VEX_60 (PREFIX_VEX_5F + 1)
822 #define PREFIX_VEX_61 (PREFIX_VEX_60 + 1)
823 #define PREFIX_VEX_62 (PREFIX_VEX_61 + 1)
824 #define PREFIX_VEX_63 (PREFIX_VEX_62 + 1)
825 #define PREFIX_VEX_64 (PREFIX_VEX_63 + 1)
826 #define PREFIX_VEX_65 (PREFIX_VEX_64 + 1)
827 #define PREFIX_VEX_66 (PREFIX_VEX_65 + 1)
828 #define PREFIX_VEX_67 (PREFIX_VEX_66 + 1)
829 #define PREFIX_VEX_68 (PREFIX_VEX_67 + 1)
830 #define PREFIX_VEX_69 (PREFIX_VEX_68 + 1)
831 #define PREFIX_VEX_6A (PREFIX_VEX_69 + 1)
832 #define PREFIX_VEX_6B (PREFIX_VEX_6A + 1)
833 #define PREFIX_VEX_6C (PREFIX_VEX_6B + 1)
834 #define PREFIX_VEX_6D (PREFIX_VEX_6C + 1)
835 #define PREFIX_VEX_6E (PREFIX_VEX_6D + 1)
836 #define PREFIX_VEX_6F (PREFIX_VEX_6E + 1)
837 #define PREFIX_VEX_70 (PREFIX_VEX_6F + 1)
838 #define PREFIX_VEX_71_REG_2 (PREFIX_VEX_70 + 1)
839 #define PREFIX_VEX_71_REG_4 (PREFIX_VEX_71_REG_2 + 1)
840 #define PREFIX_VEX_71_REG_6 (PREFIX_VEX_71_REG_4 + 1)
841 #define PREFIX_VEX_72_REG_2 (PREFIX_VEX_71_REG_6 + 1)
842 #define PREFIX_VEX_72_REG_4 (PREFIX_VEX_72_REG_2 + 1)
843 #define PREFIX_VEX_72_REG_6 (PREFIX_VEX_72_REG_4 + 1)
844 #define PREFIX_VEX_73_REG_2 (PREFIX_VEX_72_REG_6 + 1)
845 #define PREFIX_VEX_73_REG_3 (PREFIX_VEX_73_REG_2 + 1)
846 #define PREFIX_VEX_73_REG_6 (PREFIX_VEX_73_REG_3 + 1)
847 #define PREFIX_VEX_73_REG_7 (PREFIX_VEX_73_REG_6 + 1)
848 #define PREFIX_VEX_74 (PREFIX_VEX_73_REG_7 + 1)
849 #define PREFIX_VEX_75 (PREFIX_VEX_74 + 1)
850 #define PREFIX_VEX_76 (PREFIX_VEX_75 + 1)
851 #define PREFIX_VEX_77 (PREFIX_VEX_76 + 1)
852 #define PREFIX_VEX_7C (PREFIX_VEX_77 + 1)
853 #define PREFIX_VEX_7D (PREFIX_VEX_7C + 1)
854 #define PREFIX_VEX_7E (PREFIX_VEX_7D + 1)
855 #define PREFIX_VEX_7F (PREFIX_VEX_7E + 1)
856 #define PREFIX_VEX_C2 (PREFIX_VEX_7F + 1)
857 #define PREFIX_VEX_C4 (PREFIX_VEX_C2 + 1)
858 #define PREFIX_VEX_C5 (PREFIX_VEX_C4 + 1)
859 #define PREFIX_VEX_D0 (PREFIX_VEX_C5 + 1)
860 #define PREFIX_VEX_D1 (PREFIX_VEX_D0 + 1)
861 #define PREFIX_VEX_D2 (PREFIX_VEX_D1 + 1)
862 #define PREFIX_VEX_D3 (PREFIX_VEX_D2 + 1)
863 #define PREFIX_VEX_D4 (PREFIX_VEX_D3 + 1)
864 #define PREFIX_VEX_D5 (PREFIX_VEX_D4 + 1)
865 #define PREFIX_VEX_D6 (PREFIX_VEX_D5 + 1)
866 #define PREFIX_VEX_D7 (PREFIX_VEX_D6 + 1)
867 #define PREFIX_VEX_D8 (PREFIX_VEX_D7 + 1)
868 #define PREFIX_VEX_D9 (PREFIX_VEX_D8 + 1)
869 #define PREFIX_VEX_DA (PREFIX_VEX_D9 + 1)
870 #define PREFIX_VEX_DB (PREFIX_VEX_DA + 1)
871 #define PREFIX_VEX_DC (PREFIX_VEX_DB + 1)
872 #define PREFIX_VEX_DD (PREFIX_VEX_DC + 1)
873 #define PREFIX_VEX_DE (PREFIX_VEX_DD + 1)
874 #define PREFIX_VEX_DF (PREFIX_VEX_DE + 1)
875 #define PREFIX_VEX_E0 (PREFIX_VEX_DF + 1)
876 #define PREFIX_VEX_E1 (PREFIX_VEX_E0 + 1)
877 #define PREFIX_VEX_E2 (PREFIX_VEX_E1 + 1)
878 #define PREFIX_VEX_E3 (PREFIX_VEX_E2 + 1)
879 #define PREFIX_VEX_E4 (PREFIX_VEX_E3 + 1)
880 #define PREFIX_VEX_E5 (PREFIX_VEX_E4 + 1)
881 #define PREFIX_VEX_E6 (PREFIX_VEX_E5 + 1)
882 #define PREFIX_VEX_E7 (PREFIX_VEX_E6 + 1)
883 #define PREFIX_VEX_E8 (PREFIX_VEX_E7 + 1)
884 #define PREFIX_VEX_E9 (PREFIX_VEX_E8 + 1)
885 #define PREFIX_VEX_EA (PREFIX_VEX_E9 + 1)
886 #define PREFIX_VEX_EB (PREFIX_VEX_EA + 1)
887 #define PREFIX_VEX_EC (PREFIX_VEX_EB + 1)
888 #define PREFIX_VEX_ED (PREFIX_VEX_EC + 1)
889 #define PREFIX_VEX_EE (PREFIX_VEX_ED + 1)
890 #define PREFIX_VEX_EF (PREFIX_VEX_EE + 1)
891 #define PREFIX_VEX_F0 (PREFIX_VEX_EF + 1)
892 #define PREFIX_VEX_F1 (PREFIX_VEX_F0 + 1)
893 #define PREFIX_VEX_F2 (PREFIX_VEX_F1 + 1)
894 #define PREFIX_VEX_F3 (PREFIX_VEX_F2 + 1)
895 #define PREFIX_VEX_F4 (PREFIX_VEX_F3 + 1)
896 #define PREFIX_VEX_F5 (PREFIX_VEX_F4 + 1)
897 #define PREFIX_VEX_F6 (PREFIX_VEX_F5 + 1)
898 #define PREFIX_VEX_F7 (PREFIX_VEX_F6 + 1)
899 #define PREFIX_VEX_F8 (PREFIX_VEX_F7 + 1)
900 #define PREFIX_VEX_F9 (PREFIX_VEX_F8 + 1)
901 #define PREFIX_VEX_FA (PREFIX_VEX_F9 + 1)
902 #define PREFIX_VEX_FB (PREFIX_VEX_FA + 1)
903 #define PREFIX_VEX_FC (PREFIX_VEX_FB + 1)
904 #define PREFIX_VEX_FD (PREFIX_VEX_FC + 1)
905 #define PREFIX_VEX_FE (PREFIX_VEX_FD + 1)
906 #define PREFIX_VEX_3800 (PREFIX_VEX_FE + 1)
907 #define PREFIX_VEX_3801 (PREFIX_VEX_3800 + 1)
908 #define PREFIX_VEX_3802 (PREFIX_VEX_3801 + 1)
909 #define PREFIX_VEX_3803 (PREFIX_VEX_3802 + 1)
910 #define PREFIX_VEX_3804 (PREFIX_VEX_3803 + 1)
911 #define PREFIX_VEX_3805 (PREFIX_VEX_3804 + 1)
912 #define PREFIX_VEX_3806 (PREFIX_VEX_3805 + 1)
913 #define PREFIX_VEX_3807 (PREFIX_VEX_3806 + 1)
914 #define PREFIX_VEX_3808 (PREFIX_VEX_3807 + 1)
915 #define PREFIX_VEX_3809 (PREFIX_VEX_3808 + 1)
916 #define PREFIX_VEX_380A (PREFIX_VEX_3809 + 1)
917 #define PREFIX_VEX_380B (PREFIX_VEX_380A + 1)
918 #define PREFIX_VEX_380C (PREFIX_VEX_380B + 1)
919 #define PREFIX_VEX_380D (PREFIX_VEX_380C + 1)
920 #define PREFIX_VEX_380E (PREFIX_VEX_380D + 1)
921 #define PREFIX_VEX_380F (PREFIX_VEX_380E + 1)
922 #define PREFIX_VEX_3817 (PREFIX_VEX_380F + 1)
923 #define PREFIX_VEX_3818 (PREFIX_VEX_3817 + 1)
924 #define PREFIX_VEX_3819 (PREFIX_VEX_3818 + 1)
925 #define PREFIX_VEX_381A (PREFIX_VEX_3819 + 1)
926 #define PREFIX_VEX_381C (PREFIX_VEX_381A + 1)
927 #define PREFIX_VEX_381D (PREFIX_VEX_381C + 1)
928 #define PREFIX_VEX_381E (PREFIX_VEX_381D + 1)
929 #define PREFIX_VEX_3820 (PREFIX_VEX_381E + 1)
930 #define PREFIX_VEX_3821 (PREFIX_VEX_3820 + 1)
931 #define PREFIX_VEX_3822 (PREFIX_VEX_3821 + 1)
932 #define PREFIX_VEX_3823 (PREFIX_VEX_3822 + 1)
933 #define PREFIX_VEX_3824 (PREFIX_VEX_3823 + 1)
934 #define PREFIX_VEX_3825 (PREFIX_VEX_3824 + 1)
935 #define PREFIX_VEX_3828 (PREFIX_VEX_3825 + 1)
936 #define PREFIX_VEX_3829 (PREFIX_VEX_3828 + 1)
937 #define PREFIX_VEX_382A (PREFIX_VEX_3829 + 1)
938 #define PREFIX_VEX_382B (PREFIX_VEX_382A + 1)
939 #define PREFIX_VEX_382C (PREFIX_VEX_382B + 1)
940 #define PREFIX_VEX_382D (PREFIX_VEX_382C + 1)
941 #define PREFIX_VEX_382E (PREFIX_VEX_382D + 1)
942 #define PREFIX_VEX_382F (PREFIX_VEX_382E + 1)
943 #define PREFIX_VEX_3830 (PREFIX_VEX_382F + 1)
944 #define PREFIX_VEX_3831 (PREFIX_VEX_3830 + 1)
945 #define PREFIX_VEX_3832 (PREFIX_VEX_3831 + 1)
946 #define PREFIX_VEX_3833 (PREFIX_VEX_3832 + 1)
947 #define PREFIX_VEX_3834 (PREFIX_VEX_3833 + 1)
948 #define PREFIX_VEX_3835 (PREFIX_VEX_3834 + 1)
949 #define PREFIX_VEX_3837 (PREFIX_VEX_3835 + 1)
950 #define PREFIX_VEX_3838 (PREFIX_VEX_3837 + 1)
951 #define PREFIX_VEX_3839 (PREFIX_VEX_3838 + 1)
952 #define PREFIX_VEX_383A (PREFIX_VEX_3839 + 1)
953 #define PREFIX_VEX_383B (PREFIX_VEX_383A + 1)
954 #define PREFIX_VEX_383C (PREFIX_VEX_383B + 1)
955 #define PREFIX_VEX_383D (PREFIX_VEX_383C + 1)
956 #define PREFIX_VEX_383E (PREFIX_VEX_383D + 1)
957 #define PREFIX_VEX_383F (PREFIX_VEX_383E + 1)
958 #define PREFIX_VEX_3840 (PREFIX_VEX_383F + 1)
959 #define PREFIX_VEX_3841 (PREFIX_VEX_3840 + 1)
960 #define PREFIX_VEX_38DB (PREFIX_VEX_3841 + 1)
961 #define PREFIX_VEX_38DC (PREFIX_VEX_38DB + 1)
962 #define PREFIX_VEX_38DD (PREFIX_VEX_38DC + 1)
963 #define PREFIX_VEX_38DE (PREFIX_VEX_38DD + 1)
964 #define PREFIX_VEX_38DF (PREFIX_VEX_38DE + 1)
965 #define PREFIX_VEX_3A04 (PREFIX_VEX_38DF + 1)
966 #define PREFIX_VEX_3A05 (PREFIX_VEX_3A04 + 1)
967 #define PREFIX_VEX_3A06 (PREFIX_VEX_3A05 + 1)
968 #define PREFIX_VEX_3A08 (PREFIX_VEX_3A06 + 1)
969 #define PREFIX_VEX_3A09 (PREFIX_VEX_3A08 + 1)
970 #define PREFIX_VEX_3A0A (PREFIX_VEX_3A09 + 1)
971 #define PREFIX_VEX_3A0B (PREFIX_VEX_3A0A + 1)
972 #define PREFIX_VEX_3A0C (PREFIX_VEX_3A0B + 1)
973 #define PREFIX_VEX_3A0D (PREFIX_VEX_3A0C + 1)
974 #define PREFIX_VEX_3A0E (PREFIX_VEX_3A0D + 1)
975 #define PREFIX_VEX_3A0F (PREFIX_VEX_3A0E + 1)
976 #define PREFIX_VEX_3A14 (PREFIX_VEX_3A0F + 1)
977 #define PREFIX_VEX_3A15 (PREFIX_VEX_3A14 + 1)
978 #define PREFIX_VEX_3A16 (PREFIX_VEX_3A15 + 1)
979 #define PREFIX_VEX_3A17 (PREFIX_VEX_3A16 + 1)
980 #define PREFIX_VEX_3A18 (PREFIX_VEX_3A17 + 1)
981 #define PREFIX_VEX_3A19 (PREFIX_VEX_3A18 + 1)
982 #define PREFIX_VEX_3A20 (PREFIX_VEX_3A19 + 1)
983 #define PREFIX_VEX_3A21 (PREFIX_VEX_3A20 + 1)
984 #define PREFIX_VEX_3A22 (PREFIX_VEX_3A21 + 1)
985 #define PREFIX_VEX_3A40 (PREFIX_VEX_3A22 + 1)
986 #define PREFIX_VEX_3A41 (PREFIX_VEX_3A40 + 1)
987 #define PREFIX_VEX_3A42 (PREFIX_VEX_3A41 + 1)
988 #define PREFIX_VEX_3A48 (PREFIX_VEX_3A42 + 1)
989 #define PREFIX_VEX_3A49 (PREFIX_VEX_3A48 + 1)
990 #define PREFIX_VEX_3A4A (PREFIX_VEX_3A49 + 1)
991 #define PREFIX_VEX_3A4B (PREFIX_VEX_3A4A + 1)
992 #define PREFIX_VEX_3A4C (PREFIX_VEX_3A4B + 1)
993 #define PREFIX_VEX_3A5C (PREFIX_VEX_3A4C + 1)
994 #define PREFIX_VEX_3A5D (PREFIX_VEX_3A5C + 1)
995 #define PREFIX_VEX_3A5E (PREFIX_VEX_3A5D + 1)
996 #define PREFIX_VEX_3A5F (PREFIX_VEX_3A5E + 1)
997 #define PREFIX_VEX_3A60 (PREFIX_VEX_3A5F + 1)
998 #define PREFIX_VEX_3A61 (PREFIX_VEX_3A60 + 1)
999 #define PREFIX_VEX_3A62 (PREFIX_VEX_3A61 + 1)
1000 #define PREFIX_VEX_3A63 (PREFIX_VEX_3A62 + 1)
1001 #define PREFIX_VEX_3A68 (PREFIX_VEX_3A63 + 1)
1002 #define PREFIX_VEX_3A69 (PREFIX_VEX_3A68 + 1)
1003 #define PREFIX_VEX_3A6A (PREFIX_VEX_3A69 + 1)
1004 #define PREFIX_VEX_3A6B (PREFIX_VEX_3A6A + 1)
1005 #define PREFIX_VEX_3A6C (PREFIX_VEX_3A6B + 1)
1006 #define PREFIX_VEX_3A6D (PREFIX_VEX_3A6C + 1)
1007 #define PREFIX_VEX_3A6E (PREFIX_VEX_3A6D + 1)
1008 #define PREFIX_VEX_3A6F (PREFIX_VEX_3A6E + 1)
1009 #define PREFIX_VEX_3A78 (PREFIX_VEX_3A6F + 1)
1010 #define PREFIX_VEX_3A79 (PREFIX_VEX_3A78 + 1)
1011 #define PREFIX_VEX_3A7A (PREFIX_VEX_3A79 + 1)
1012 #define PREFIX_VEX_3A7B (PREFIX_VEX_3A7A + 1)
1013 #define PREFIX_VEX_3A7C (PREFIX_VEX_3A7B + 1)
1014 #define PREFIX_VEX_3A7D (PREFIX_VEX_3A7C + 1)
1015 #define PREFIX_VEX_3A7E (PREFIX_VEX_3A7D + 1)
1016 #define PREFIX_VEX_3A7F (PREFIX_VEX_3A7E + 1)
1017 #define PREFIX_VEX_3ADF (PREFIX_VEX_3A7F + 1)
1020 #define X86_64_07 (X86_64_06 + 1)
1021 #define X86_64_0D (X86_64_07 + 1)
1022 #define X86_64_16 (X86_64_0D + 1)
1023 #define X86_64_17 (X86_64_16 + 1)
1024 #define X86_64_1E (X86_64_17 + 1)
1025 #define X86_64_1F (X86_64_1E + 1)
1026 #define X86_64_27 (X86_64_1F + 1)
1027 #define X86_64_2F (X86_64_27 + 1)
1028 #define X86_64_37 (X86_64_2F + 1)
1029 #define X86_64_3F (X86_64_37 + 1)
1030 #define X86_64_60 (X86_64_3F + 1)
1031 #define X86_64_61 (X86_64_60 + 1)
1032 #define X86_64_62 (X86_64_61 + 1)
1033 #define X86_64_63 (X86_64_62 + 1)
1034 #define X86_64_6D (X86_64_63 + 1)
1035 #define X86_64_6F (X86_64_6D + 1)
1036 #define X86_64_9A (X86_64_6F + 1)
1037 #define X86_64_C4 (X86_64_9A + 1)
1038 #define X86_64_C5 (X86_64_C4 + 1)
1039 #define X86_64_CE (X86_64_C5 + 1)
1040 #define X86_64_D4 (X86_64_CE + 1)
1041 #define X86_64_D5 (X86_64_D4 + 1)
1042 #define X86_64_EA (X86_64_D5 + 1)
1043 #define X86_64_0F01_REG_0 (X86_64_EA + 1)
1044 #define X86_64_0F01_REG_1 (X86_64_0F01_REG_0 + 1)
1045 #define X86_64_0F01_REG_2 (X86_64_0F01_REG_1 + 1)
1046 #define X86_64_0F01_REG_3 (X86_64_0F01_REG_2 + 1)
1048 #define THREE_BYTE_0F24 0
1049 #define THREE_BYTE_0F25 (THREE_BYTE_0F24 + 1)
1050 #define THREE_BYTE_0F38 (THREE_BYTE_0F25 + 1)
1051 #define THREE_BYTE_0F3A (THREE_BYTE_0F38 + 1)
1052 #define THREE_BYTE_0F7A (THREE_BYTE_0F3A + 1)
1053 #define THREE_BYTE_0F7B (THREE_BYTE_0F7A + 1)
1056 #define VEX_0F38 (VEX_0F + 1)
1057 #define VEX_0F3A (VEX_0F38 + 1)
1059 #define VEX_LEN_10_P_1 0
1060 #define VEX_LEN_10_P_3 (VEX_LEN_10_P_1 + 1)
1061 #define VEX_LEN_11_P_1 (VEX_LEN_10_P_3 + 1)
1062 #define VEX_LEN_11_P_3 (VEX_LEN_11_P_1 + 1)
1063 #define VEX_LEN_12_P_0_M_0 (VEX_LEN_11_P_3 + 1)
1064 #define VEX_LEN_12_P_0_M_1 (VEX_LEN_12_P_0_M_0 + 1)
1065 #define VEX_LEN_12_P_2 (VEX_LEN_12_P_0_M_1 + 1)
1066 #define VEX_LEN_13_M_0 (VEX_LEN_12_P_2 + 1)
1067 #define VEX_LEN_16_P_0_M_0 (VEX_LEN_13_M_0 + 1)
1068 #define VEX_LEN_16_P_0_M_1 (VEX_LEN_16_P_0_M_0 + 1)
1069 #define VEX_LEN_16_P_2 (VEX_LEN_16_P_0_M_1 + 1)
1070 #define VEX_LEN_17_M_0 (VEX_LEN_16_P_2 + 1)
1071 #define VEX_LEN_2A_P_1 (VEX_LEN_17_M_0 + 1)
1072 #define VEX_LEN_2A_P_3 (VEX_LEN_2A_P_1 + 1)
1073 #define VEX_LEN_2B_M_0 (VEX_LEN_2A_P_3 + 1)
1074 #define VEX_LEN_2C_P_1 (VEX_LEN_2B_M_0 + 1)
1075 #define VEX_LEN_2C_P_3 (VEX_LEN_2C_P_1 + 1)
1076 #define VEX_LEN_2D_P_1 (VEX_LEN_2C_P_3 + 1)
1077 #define VEX_LEN_2D_P_3 (VEX_LEN_2D_P_1 + 1)
1078 #define VEX_LEN_2E_P_0 (VEX_LEN_2D_P_3 + 1)
1079 #define VEX_LEN_2E_P_2 (VEX_LEN_2E_P_0 + 1)
1080 #define VEX_LEN_2F_P_0 (VEX_LEN_2E_P_2 + 1)
1081 #define VEX_LEN_2F_P_2 (VEX_LEN_2F_P_0 + 1)
1082 #define VEX_LEN_51_P_1 (VEX_LEN_2F_P_2 + 1)
1083 #define VEX_LEN_51_P_3 (VEX_LEN_51_P_1 + 1)
1084 #define VEX_LEN_52_P_1 (VEX_LEN_51_P_3 + 1)
1085 #define VEX_LEN_53_P_1 (VEX_LEN_52_P_1 + 1)
1086 #define VEX_LEN_58_P_1 (VEX_LEN_53_P_1 + 1)
1087 #define VEX_LEN_58_P_3 (VEX_LEN_58_P_1 + 1)
1088 #define VEX_LEN_59_P_1 (VEX_LEN_58_P_3 + 1)
1089 #define VEX_LEN_59_P_3 (VEX_LEN_59_P_1 + 1)
1090 #define VEX_LEN_5A_P_1 (VEX_LEN_59_P_3 + 1)
1091 #define VEX_LEN_5A_P_3 (VEX_LEN_5A_P_1 + 1)
1092 #define VEX_LEN_5C_P_1 (VEX_LEN_5A_P_3 + 1)
1093 #define VEX_LEN_5C_P_3 (VEX_LEN_5C_P_1 + 1)
1094 #define VEX_LEN_5D_P_1 (VEX_LEN_5C_P_3 + 1)
1095 #define VEX_LEN_5D_P_3 (VEX_LEN_5D_P_1 + 1)
1096 #define VEX_LEN_5E_P_1 (VEX_LEN_5D_P_3 + 1)
1097 #define VEX_LEN_5E_P_3 (VEX_LEN_5E_P_1 + 1)
1098 #define VEX_LEN_5F_P_1 (VEX_LEN_5E_P_3 + 1)
1099 #define VEX_LEN_5F_P_3 (VEX_LEN_5F_P_1 + 1)
1100 #define VEX_LEN_60_P_2 (VEX_LEN_5F_P_3 + 1)
1101 #define VEX_LEN_61_P_2 (VEX_LEN_60_P_2 + 1)
1102 #define VEX_LEN_62_P_2 (VEX_LEN_61_P_2 + 1)
1103 #define VEX_LEN_63_P_2 (VEX_LEN_62_P_2 + 1)
1104 #define VEX_LEN_64_P_2 (VEX_LEN_63_P_2 + 1)
1105 #define VEX_LEN_65_P_2 (VEX_LEN_64_P_2 + 1)
1106 #define VEX_LEN_66_P_2 (VEX_LEN_65_P_2 + 1)
1107 #define VEX_LEN_67_P_2 (VEX_LEN_66_P_2 + 1)
1108 #define VEX_LEN_68_P_2 (VEX_LEN_67_P_2 + 1)
1109 #define VEX_LEN_69_P_2 (VEX_LEN_68_P_2 + 1)
1110 #define VEX_LEN_6A_P_2 (VEX_LEN_69_P_2 + 1)
1111 #define VEX_LEN_6B_P_2 (VEX_LEN_6A_P_2 + 1)
1112 #define VEX_LEN_6C_P_2 (VEX_LEN_6B_P_2 + 1)
1113 #define VEX_LEN_6D_P_2 (VEX_LEN_6C_P_2 + 1)
1114 #define VEX_LEN_6E_P_2 (VEX_LEN_6D_P_2 + 1)
1115 #define VEX_LEN_70_P_1 (VEX_LEN_6E_P_2 + 1)
1116 #define VEX_LEN_70_P_2 (VEX_LEN_70_P_1 + 1)
1117 #define VEX_LEN_70_P_3 (VEX_LEN_70_P_2 + 1)
1118 #define VEX_LEN_71_R_2_P_2 (VEX_LEN_70_P_3 + 1)
1119 #define VEX_LEN_71_R_4_P_2 (VEX_LEN_71_R_2_P_2 + 1)
1120 #define VEX_LEN_71_R_6_P_2 (VEX_LEN_71_R_4_P_2 + 1)
1121 #define VEX_LEN_72_R_2_P_2 (VEX_LEN_71_R_6_P_2 + 1)
1122 #define VEX_LEN_72_R_4_P_2 (VEX_LEN_72_R_2_P_2 + 1)
1123 #define VEX_LEN_72_R_6_P_2 (VEX_LEN_72_R_4_P_2 + 1)
1124 #define VEX_LEN_73_R_2_P_2 (VEX_LEN_72_R_6_P_2 + 1)
1125 #define VEX_LEN_73_R_3_P_2 (VEX_LEN_73_R_2_P_2 + 1)
1126 #define VEX_LEN_73_R_6_P_2 (VEX_LEN_73_R_3_P_2 + 1)
1127 #define VEX_LEN_73_R_7_P_2 (VEX_LEN_73_R_6_P_2 + 1)
1128 #define VEX_LEN_74_P_2 (VEX_LEN_73_R_7_P_2 + 1)
1129 #define VEX_LEN_75_P_2 (VEX_LEN_74_P_2 + 1)
1130 #define VEX_LEN_76_P_2 (VEX_LEN_75_P_2 + 1)
1131 #define VEX_LEN_7E_P_1 (VEX_LEN_76_P_2 + 1)
1132 #define VEX_LEN_7E_P_2 (VEX_LEN_7E_P_1 + 1)
1133 #define VEX_LEN_AE_R_2_M_0 (VEX_LEN_7E_P_2 + 1)
1134 #define VEX_LEN_AE_R_3_M_0 (VEX_LEN_AE_R_2_M_0 + 1)
1135 #define VEX_LEN_C2_P_1 (VEX_LEN_AE_R_3_M_0 + 1)
1136 #define VEX_LEN_C2_P_3 (VEX_LEN_C2_P_1 + 1)
1137 #define VEX_LEN_C4_P_2 (VEX_LEN_C2_P_3 + 1)
1138 #define VEX_LEN_C5_P_2 (VEX_LEN_C4_P_2 + 1)
1139 #define VEX_LEN_D1_P_2 (VEX_LEN_C5_P_2 + 1)
1140 #define VEX_LEN_D2_P_2 (VEX_LEN_D1_P_2 + 1)
1141 #define VEX_LEN_D3_P_2 (VEX_LEN_D2_P_2 + 1)
1142 #define VEX_LEN_D4_P_2 (VEX_LEN_D3_P_2 + 1)
1143 #define VEX_LEN_D5_P_2 (VEX_LEN_D4_P_2 + 1)
1144 #define VEX_LEN_D6_P_2 (VEX_LEN_D5_P_2 + 1)
1145 #define VEX_LEN_D7_P_2_M_1 (VEX_LEN_D6_P_2 + 1)
1146 #define VEX_LEN_D8_P_2 (VEX_LEN_D7_P_2_M_1 + 1)
1147 #define VEX_LEN_D9_P_2 (VEX_LEN_D8_P_2 + 1)
1148 #define VEX_LEN_DA_P_2 (VEX_LEN_D9_P_2 + 1)
1149 #define VEX_LEN_DB_P_2 (VEX_LEN_DA_P_2 + 1)
1150 #define VEX_LEN_DC_P_2 (VEX_LEN_DB_P_2 + 1)
1151 #define VEX_LEN_DD_P_2 (VEX_LEN_DC_P_2 + 1)
1152 #define VEX_LEN_DE_P_2 (VEX_LEN_DD_P_2 + 1)
1153 #define VEX_LEN_DF_P_2 (VEX_LEN_DE_P_2 + 1)
1154 #define VEX_LEN_E0_P_2 (VEX_LEN_DF_P_2 + 1)
1155 #define VEX_LEN_E1_P_2 (VEX_LEN_E0_P_2 + 1)
1156 #define VEX_LEN_E2_P_2 (VEX_LEN_E1_P_2 + 1)
1157 #define VEX_LEN_E3_P_2 (VEX_LEN_E2_P_2 + 1)
1158 #define VEX_LEN_E4_P_2 (VEX_LEN_E3_P_2 + 1)
1159 #define VEX_LEN_E5_P_2 (VEX_LEN_E4_P_2 + 1)
1160 #define VEX_LEN_E7_P_2_M_0 (VEX_LEN_E5_P_2 + 1)
1161 #define VEX_LEN_E8_P_2 (VEX_LEN_E7_P_2_M_0 + 1)
1162 #define VEX_LEN_E9_P_2 (VEX_LEN_E8_P_2 + 1)
1163 #define VEX_LEN_EA_P_2 (VEX_LEN_E9_P_2 + 1)
1164 #define VEX_LEN_EB_P_2 (VEX_LEN_EA_P_2 + 1)
1165 #define VEX_LEN_EC_P_2 (VEX_LEN_EB_P_2 + 1)
1166 #define VEX_LEN_ED_P_2 (VEX_LEN_EC_P_2 + 1)
1167 #define VEX_LEN_EE_P_2 (VEX_LEN_ED_P_2 + 1)
1168 #define VEX_LEN_EF_P_2 (VEX_LEN_EE_P_2 + 1)
1169 #define VEX_LEN_F1_P_2 (VEX_LEN_EF_P_2 + 1)
1170 #define VEX_LEN_F2_P_2 (VEX_LEN_F1_P_2 + 1)
1171 #define VEX_LEN_F3_P_2 (VEX_LEN_F2_P_2 + 1)
1172 #define VEX_LEN_F4_P_2 (VEX_LEN_F3_P_2 + 1)
1173 #define VEX_LEN_F5_P_2 (VEX_LEN_F4_P_2 + 1)
1174 #define VEX_LEN_F6_P_2 (VEX_LEN_F5_P_2 + 1)
1175 #define VEX_LEN_F7_P_2 (VEX_LEN_F6_P_2 + 1)
1176 #define VEX_LEN_F8_P_2 (VEX_LEN_F7_P_2 + 1)
1177 #define VEX_LEN_F9_P_2 (VEX_LEN_F8_P_2 + 1)
1178 #define VEX_LEN_FA_P_2 (VEX_LEN_F9_P_2 + 1)
1179 #define VEX_LEN_FB_P_2 (VEX_LEN_FA_P_2 + 1)
1180 #define VEX_LEN_FC_P_2 (VEX_LEN_FB_P_2 + 1)
1181 #define VEX_LEN_FD_P_2 (VEX_LEN_FC_P_2 + 1)
1182 #define VEX_LEN_FE_P_2 (VEX_LEN_FD_P_2 + 1)
1183 #define VEX_LEN_3800_P_2 (VEX_LEN_FE_P_2 + 1)
1184 #define VEX_LEN_3801_P_2 (VEX_LEN_3800_P_2 + 1)
1185 #define VEX_LEN_3802_P_2 (VEX_LEN_3801_P_2 + 1)
1186 #define VEX_LEN_3803_P_2 (VEX_LEN_3802_P_2 + 1)
1187 #define VEX_LEN_3804_P_2 (VEX_LEN_3803_P_2 + 1)
1188 #define VEX_LEN_3805_P_2 (VEX_LEN_3804_P_2 + 1)
1189 #define VEX_LEN_3806_P_2 (VEX_LEN_3805_P_2 + 1)
1190 #define VEX_LEN_3807_P_2 (VEX_LEN_3806_P_2 + 1)
1191 #define VEX_LEN_3808_P_2 (VEX_LEN_3807_P_2 + 1)
1192 #define VEX_LEN_3809_P_2 (VEX_LEN_3808_P_2 + 1)
1193 #define VEX_LEN_380A_P_2 (VEX_LEN_3809_P_2 + 1)
1194 #define VEX_LEN_380B_P_2 (VEX_LEN_380A_P_2 + 1)
1195 #define VEX_LEN_3819_P_2_M_0 (VEX_LEN_380B_P_2 + 1)
1196 #define VEX_LEN_381A_P_2_M_0 (VEX_LEN_3819_P_2_M_0 + 1)
1197 #define VEX_LEN_381C_P_2 (VEX_LEN_381A_P_2_M_0 + 1)
1198 #define VEX_LEN_381D_P_2 (VEX_LEN_381C_P_2 + 1)
1199 #define VEX_LEN_381E_P_2 (VEX_LEN_381D_P_2 + 1)
1200 #define VEX_LEN_3820_P_2 (VEX_LEN_381E_P_2 + 1)
1201 #define VEX_LEN_3821_P_2 (VEX_LEN_3820_P_2 + 1)
1202 #define VEX_LEN_3822_P_2 (VEX_LEN_3821_P_2 + 1)
1203 #define VEX_LEN_3823_P_2 (VEX_LEN_3822_P_2 + 1)
1204 #define VEX_LEN_3824_P_2 (VEX_LEN_3823_P_2 + 1)
1205 #define VEX_LEN_3825_P_2 (VEX_LEN_3824_P_2 + 1)
1206 #define VEX_LEN_3828_P_2 (VEX_LEN_3825_P_2 + 1)
1207 #define VEX_LEN_3829_P_2 (VEX_LEN_3828_P_2 + 1)
1208 #define VEX_LEN_382A_P_2_M_0 (VEX_LEN_3829_P_2 + 1)
1209 #define VEX_LEN_382B_P_2 (VEX_LEN_382A_P_2_M_0 + 1)
1210 #define VEX_LEN_3830_P_2 (VEX_LEN_382B_P_2 + 1)
1211 #define VEX_LEN_3831_P_2 (VEX_LEN_3830_P_2 + 1)
1212 #define VEX_LEN_3832_P_2 (VEX_LEN_3831_P_2 + 1)
1213 #define VEX_LEN_3833_P_2 (VEX_LEN_3832_P_2 + 1)
1214 #define VEX_LEN_3834_P_2 (VEX_LEN_3833_P_2 + 1)
1215 #define VEX_LEN_3835_P_2 (VEX_LEN_3834_P_2 + 1)
1216 #define VEX_LEN_3837_P_2 (VEX_LEN_3835_P_2 + 1)
1217 #define VEX_LEN_3838_P_2 (VEX_LEN_3837_P_2 + 1)
1218 #define VEX_LEN_3839_P_2 (VEX_LEN_3838_P_2 + 1)
1219 #define VEX_LEN_383A_P_2 (VEX_LEN_3839_P_2 + 1)
1220 #define VEX_LEN_383B_P_2 (VEX_LEN_383A_P_2 + 1)
1221 #define VEX_LEN_383C_P_2 (VEX_LEN_383B_P_2 + 1)
1222 #define VEX_LEN_383D_P_2 (VEX_LEN_383C_P_2 + 1)
1223 #define VEX_LEN_383E_P_2 (VEX_LEN_383D_P_2 + 1)
1224 #define VEX_LEN_383F_P_2 (VEX_LEN_383E_P_2 + 1)
1225 #define VEX_LEN_3840_P_2 (VEX_LEN_383F_P_2 + 1)
1226 #define VEX_LEN_3841_P_2 (VEX_LEN_3840_P_2 + 1)
1227 #define VEX_LEN_38DB_P_2 (VEX_LEN_3841_P_2 + 1)
1228 #define VEX_LEN_38DC_P_2 (VEX_LEN_38DB_P_2 + 1)
1229 #define VEX_LEN_38DD_P_2 (VEX_LEN_38DC_P_2 + 1)
1230 #define VEX_LEN_38DE_P_2 (VEX_LEN_38DD_P_2 + 1)
1231 #define VEX_LEN_38DF_P_2 (VEX_LEN_38DE_P_2 + 1)
1232 #define VEX_LEN_3A06_P_2 (VEX_LEN_38DF_P_2 + 1)
1233 #define VEX_LEN_3A0A_P_2 (VEX_LEN_3A06_P_2 + 1)
1234 #define VEX_LEN_3A0B_P_2 (VEX_LEN_3A0A_P_2 + 1)
1235 #define VEX_LEN_3A0E_P_2 (VEX_LEN_3A0B_P_2 + 1)
1236 #define VEX_LEN_3A0F_P_2 (VEX_LEN_3A0E_P_2 + 1)
1237 #define VEX_LEN_3A14_P_2 (VEX_LEN_3A0F_P_2 + 1)
1238 #define VEX_LEN_3A15_P_2 (VEX_LEN_3A14_P_2 + 1)
1239 #define VEX_LEN_3A16_P_2 (VEX_LEN_3A15_P_2 + 1)
1240 #define VEX_LEN_3A17_P_2 (VEX_LEN_3A16_P_2 + 1)
1241 #define VEX_LEN_3A18_P_2 (VEX_LEN_3A17_P_2 + 1)
1242 #define VEX_LEN_3A19_P_2 (VEX_LEN_3A18_P_2 + 1)
1243 #define VEX_LEN_3A20_P_2 (VEX_LEN_3A19_P_2 + 1)
1244 #define VEX_LEN_3A21_P_2 (VEX_LEN_3A20_P_2 + 1)
1245 #define VEX_LEN_3A22_P_2 (VEX_LEN_3A21_P_2 + 1)
1246 #define VEX_LEN_3A41_P_2 (VEX_LEN_3A22_P_2 + 1)
1247 #define VEX_LEN_3A42_P_2 (VEX_LEN_3A41_P_2 + 1)
1248 #define VEX_LEN_3A4C_P_2 (VEX_LEN_3A42_P_2 + 1)
1249 #define VEX_LEN_3A60_P_2 (VEX_LEN_3A4C_P_2 + 1)
1250 #define VEX_LEN_3A61_P_2 (VEX_LEN_3A60_P_2 + 1)
1251 #define VEX_LEN_3A62_P_2 (VEX_LEN_3A61_P_2 + 1)
1252 #define VEX_LEN_3A63_P_2 (VEX_LEN_3A62_P_2 + 1)
1253 #define VEX_LEN_3A6A_P_2 (VEX_LEN_3A63_P_2 + 1)
1254 #define VEX_LEN_3A6B_P_2 (VEX_LEN_3A6A_P_2 + 1)
1255 #define VEX_LEN_3A6E_P_2 (VEX_LEN_3A6B_P_2 + 1)
1256 #define VEX_LEN_3A6F_P_2 (VEX_LEN_3A6E_P_2 + 1)
1257 #define VEX_LEN_3A7A_P_2 (VEX_LEN_3A6F_P_2 + 1)
1258 #define VEX_LEN_3A7B_P_2 (VEX_LEN_3A7A_P_2 + 1)
1259 #define VEX_LEN_3A7E_P_2 (VEX_LEN_3A7B_P_2 + 1)
1260 #define VEX_LEN_3A7F_P_2 (VEX_LEN_3A7E_P_2 + 1)
1261 #define VEX_LEN_3ADF_P_2 (VEX_LEN_3A7F_P_2 + 1)
1263 typedef void (*op_rtn) (int bytemode, int sizeflag);
1274 /* Upper case letters in the instruction names here are macros.
1275 'A' => print 'b' if no register operands or suffix_always is true
1276 'B' => print 'b' if suffix_always is true
1277 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1279 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1280 suffix_always is true
1281 'E' => print 'e' if 32-bit form of jcxz
1282 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1283 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1284 'H' => print ",pt" or ",pn" branch hint
1285 'I' => honor following macro letter even in Intel mode (implemented only
1286 for some of the macro letters)
1288 'K' => print 'd' or 'q' if rex prefix is present.
1289 'L' => print 'l' if suffix_always is true
1290 'M' => print 'r' if intel_mnemonic is false.
1291 'N' => print 'n' if instruction has no wait "prefix"
1292 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1293 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1294 or suffix_always is true. print 'q' if rex prefix is present.
1295 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1297 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1298 'S' => print 'w', 'l' or 'q' if suffix_always is true
1299 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1300 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1301 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1302 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1303 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1304 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1305 suffix_always is true.
1306 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1307 '!' => change condition from true to false or from false to true.
1308 '%' => add 1 upper case letter to the macro.
1310 2 upper case letter macros:
1311 "XY" => print 'x' or 'y' if no register operands or suffix_always
1313 'LQ' => print 'l' ('d' in Intel mode) or 'q' for memory operand
1314 or suffix_always is true
1316 Many of the above letters print nothing in Intel mode. See "putop"
1319 Braces '{' and '}', and vertical bars '|', indicate alternative
1320 mnemonic strings for AT&T and Intel. */
1322 static const struct dis386 dis386[] = {
1324 { "addB", { Eb, Gb } },
1325 { "addS", { Ev, Gv } },
1326 { "addB", { Gb, Eb } },
1327 { "addS", { Gv, Ev } },
1328 { "addB", { AL, Ib } },
1329 { "addS", { eAX, Iv } },
1330 { X86_64_TABLE (X86_64_06) },
1331 { X86_64_TABLE (X86_64_07) },
1333 { "orB", { Eb, Gb } },
1334 { "orS", { Ev, Gv } },
1335 { "orB", { Gb, Eb } },
1336 { "orS", { Gv, Ev } },
1337 { "orB", { AL, Ib } },
1338 { "orS", { eAX, Iv } },
1339 { X86_64_TABLE (X86_64_0D) },
1340 { "(bad)", { XX } }, /* 0x0f extended opcode escape */
1342 { "adcB", { Eb, Gb } },
1343 { "adcS", { Ev, Gv } },
1344 { "adcB", { Gb, Eb } },
1345 { "adcS", { Gv, Ev } },
1346 { "adcB", { AL, Ib } },
1347 { "adcS", { eAX, Iv } },
1348 { X86_64_TABLE (X86_64_16) },
1349 { X86_64_TABLE (X86_64_17) },
1351 { "sbbB", { Eb, Gb } },
1352 { "sbbS", { Ev, Gv } },
1353 { "sbbB", { Gb, Eb } },
1354 { "sbbS", { Gv, Ev } },
1355 { "sbbB", { AL, Ib } },
1356 { "sbbS", { eAX, Iv } },
1357 { X86_64_TABLE (X86_64_1E) },
1358 { X86_64_TABLE (X86_64_1F) },
1360 { "andB", { Eb, Gb } },
1361 { "andS", { Ev, Gv } },
1362 { "andB", { Gb, Eb } },
1363 { "andS", { Gv, Ev } },
1364 { "andB", { AL, Ib } },
1365 { "andS", { eAX, Iv } },
1366 { "(bad)", { XX } }, /* SEG ES prefix */
1367 { X86_64_TABLE (X86_64_27) },
1369 { "subB", { Eb, Gb } },
1370 { "subS", { Ev, Gv } },
1371 { "subB", { Gb, Eb } },
1372 { "subS", { Gv, Ev } },
1373 { "subB", { AL, Ib } },
1374 { "subS", { eAX, Iv } },
1375 { "(bad)", { XX } }, /* SEG CS prefix */
1376 { X86_64_TABLE (X86_64_2F) },
1378 { "xorB", { Eb, Gb } },
1379 { "xorS", { Ev, Gv } },
1380 { "xorB", { Gb, Eb } },
1381 { "xorS", { Gv, Ev } },
1382 { "xorB", { AL, Ib } },
1383 { "xorS", { eAX, Iv } },
1384 { "(bad)", { XX } }, /* SEG SS prefix */
1385 { X86_64_TABLE (X86_64_37) },
1387 { "cmpB", { Eb, Gb } },
1388 { "cmpS", { Ev, Gv } },
1389 { "cmpB", { Gb, Eb } },
1390 { "cmpS", { Gv, Ev } },
1391 { "cmpB", { AL, Ib } },
1392 { "cmpS", { eAX, Iv } },
1393 { "(bad)", { XX } }, /* SEG DS prefix */
1394 { X86_64_TABLE (X86_64_3F) },
1396 { "inc{S|}", { RMeAX } },
1397 { "inc{S|}", { RMeCX } },
1398 { "inc{S|}", { RMeDX } },
1399 { "inc{S|}", { RMeBX } },
1400 { "inc{S|}", { RMeSP } },
1401 { "inc{S|}", { RMeBP } },
1402 { "inc{S|}", { RMeSI } },
1403 { "inc{S|}", { RMeDI } },
1405 { "dec{S|}", { RMeAX } },
1406 { "dec{S|}", { RMeCX } },
1407 { "dec{S|}", { RMeDX } },
1408 { "dec{S|}", { RMeBX } },
1409 { "dec{S|}", { RMeSP } },
1410 { "dec{S|}", { RMeBP } },
1411 { "dec{S|}", { RMeSI } },
1412 { "dec{S|}", { RMeDI } },
1414 { "pushV", { RMrAX } },
1415 { "pushV", { RMrCX } },
1416 { "pushV", { RMrDX } },
1417 { "pushV", { RMrBX } },
1418 { "pushV", { RMrSP } },
1419 { "pushV", { RMrBP } },
1420 { "pushV", { RMrSI } },
1421 { "pushV", { RMrDI } },
1423 { "popV", { RMrAX } },
1424 { "popV", { RMrCX } },
1425 { "popV", { RMrDX } },
1426 { "popV", { RMrBX } },
1427 { "popV", { RMrSP } },
1428 { "popV", { RMrBP } },
1429 { "popV", { RMrSI } },
1430 { "popV", { RMrDI } },
1432 { X86_64_TABLE (X86_64_60) },
1433 { X86_64_TABLE (X86_64_61) },
1434 { X86_64_TABLE (X86_64_62) },
1435 { X86_64_TABLE (X86_64_63) },
1436 { "(bad)", { XX } }, /* seg fs */
1437 { "(bad)", { XX } }, /* seg gs */
1438 { "(bad)", { XX } }, /* op size prefix */
1439 { "(bad)", { XX } }, /* adr size prefix */
1441 { "pushT", { Iq } },
1442 { "imulS", { Gv, Ev, Iv } },
1443 { "pushT", { sIb } },
1444 { "imulS", { Gv, Ev, sIb } },
1445 { "ins{b|}", { Ybr, indirDX } },
1446 { X86_64_TABLE (X86_64_6D) },
1447 { "outs{b|}", { indirDXr, Xb } },
1448 { X86_64_TABLE (X86_64_6F) },
1450 { "joH", { Jb, XX, cond_jump_flag } },
1451 { "jnoH", { Jb, XX, cond_jump_flag } },
1452 { "jbH", { Jb, XX, cond_jump_flag } },
1453 { "jaeH", { Jb, XX, cond_jump_flag } },
1454 { "jeH", { Jb, XX, cond_jump_flag } },
1455 { "jneH", { Jb, XX, cond_jump_flag } },
1456 { "jbeH", { Jb, XX, cond_jump_flag } },
1457 { "jaH", { Jb, XX, cond_jump_flag } },
1459 { "jsH", { Jb, XX, cond_jump_flag } },
1460 { "jnsH", { Jb, XX, cond_jump_flag } },
1461 { "jpH", { Jb, XX, cond_jump_flag } },
1462 { "jnpH", { Jb, XX, cond_jump_flag } },
1463 { "jlH", { Jb, XX, cond_jump_flag } },
1464 { "jgeH", { Jb, XX, cond_jump_flag } },
1465 { "jleH", { Jb, XX, cond_jump_flag } },
1466 { "jgH", { Jb, XX, cond_jump_flag } },
1468 { REG_TABLE (REG_80) },
1469 { REG_TABLE (REG_81) },
1470 { "(bad)", { XX } },
1471 { REG_TABLE (REG_82) },
1472 { "testB", { Eb, Gb } },
1473 { "testS", { Ev, Gv } },
1474 { "xchgB", { Eb, Gb } },
1475 { "xchgS", { Ev, Gv } },
1477 { "movB", { Eb, Gb } },
1478 { "movS", { Ev, Gv } },
1479 { "movB", { Gb, EbS } },
1480 { "movS", { Gv, EvS } },
1481 { "movD", { Sv, Sw } },
1482 { MOD_TABLE (MOD_8D) },
1483 { "movD", { Sw, Sv } },
1484 { REG_TABLE (REG_8F) },
1486 { PREFIX_TABLE (PREFIX_90) },
1487 { "xchgS", { RMeCX, eAX } },
1488 { "xchgS", { RMeDX, eAX } },
1489 { "xchgS", { RMeBX, eAX } },
1490 { "xchgS", { RMeSP, eAX } },
1491 { "xchgS", { RMeBP, eAX } },
1492 { "xchgS", { RMeSI, eAX } },
1493 { "xchgS", { RMeDI, eAX } },
1495 { "cW{t|}R", { XX } },
1496 { "cR{t|}O", { XX } },
1497 { X86_64_TABLE (X86_64_9A) },
1498 { "(bad)", { XX } }, /* fwait */
1499 { "pushfT", { XX } },
1500 { "popfT", { XX } },
1504 { "movB", { AL, Ob } },
1505 { "movS", { eAX, Ov } },
1506 { "movB", { Ob, AL } },
1507 { "movS", { Ov, eAX } },
1508 { "movs{b|}", { Ybr, Xb } },
1509 { "movs{R|}", { Yvr, Xv } },
1510 { "cmps{b|}", { Xb, Yb } },
1511 { "cmps{R|}", { Xv, Yv } },
1513 { "testB", { AL, Ib } },
1514 { "testS", { eAX, Iv } },
1515 { "stosB", { Ybr, AL } },
1516 { "stosS", { Yvr, eAX } },
1517 { "lodsB", { ALr, Xb } },
1518 { "lodsS", { eAXr, Xv } },
1519 { "scasB", { AL, Yb } },
1520 { "scasS", { eAX, Yv } },
1522 { "movB", { RMAL, Ib } },
1523 { "movB", { RMCL, Ib } },
1524 { "movB", { RMDL, Ib } },
1525 { "movB", { RMBL, Ib } },
1526 { "movB", { RMAH, Ib } },
1527 { "movB", { RMCH, Ib } },
1528 { "movB", { RMDH, Ib } },
1529 { "movB", { RMBH, Ib } },
1531 { "movS", { RMeAX, Iv64 } },
1532 { "movS", { RMeCX, Iv64 } },
1533 { "movS", { RMeDX, Iv64 } },
1534 { "movS", { RMeBX, Iv64 } },
1535 { "movS", { RMeSP, Iv64 } },
1536 { "movS", { RMeBP, Iv64 } },
1537 { "movS", { RMeSI, Iv64 } },
1538 { "movS", { RMeDI, Iv64 } },
1540 { REG_TABLE (REG_C0) },
1541 { REG_TABLE (REG_C1) },
1544 { X86_64_TABLE (X86_64_C4) },
1545 { X86_64_TABLE (X86_64_C5) },
1546 { REG_TABLE (REG_C6) },
1547 { REG_TABLE (REG_C7) },
1549 { "enterT", { Iw, Ib } },
1550 { "leaveT", { XX } },
1551 { "Jret{|f}P", { Iw } },
1552 { "Jret{|f}P", { XX } },
1555 { X86_64_TABLE (X86_64_CE) },
1556 { "iretP", { XX } },
1558 { REG_TABLE (REG_D0) },
1559 { REG_TABLE (REG_D1) },
1560 { REG_TABLE (REG_D2) },
1561 { REG_TABLE (REG_D3) },
1562 { X86_64_TABLE (X86_64_D4) },
1563 { X86_64_TABLE (X86_64_D5) },
1564 { "(bad)", { XX } },
1565 { "xlat", { DSBX } },
1576 { "loopneFH", { Jb, XX, loop_jcxz_flag } },
1577 { "loopeFH", { Jb, XX, loop_jcxz_flag } },
1578 { "loopFH", { Jb, XX, loop_jcxz_flag } },
1579 { "jEcxzH", { Jb, XX, loop_jcxz_flag } },
1580 { "inB", { AL, Ib } },
1581 { "inG", { zAX, Ib } },
1582 { "outB", { Ib, AL } },
1583 { "outG", { Ib, zAX } },
1585 { "callT", { Jv } },
1587 { X86_64_TABLE (X86_64_EA) },
1589 { "inB", { AL, indirDX } },
1590 { "inG", { zAX, indirDX } },
1591 { "outB", { indirDX, AL } },
1592 { "outG", { indirDX, zAX } },
1594 { "(bad)", { XX } }, /* lock prefix */
1595 { "icebp", { XX } },
1596 { "(bad)", { XX } }, /* repne */
1597 { "(bad)", { XX } }, /* repz */
1600 { REG_TABLE (REG_F6) },
1601 { REG_TABLE (REG_F7) },
1609 { REG_TABLE (REG_FE) },
1610 { REG_TABLE (REG_FF) },
1613 static const struct dis386 dis386_twobyte[] = {
1615 { REG_TABLE (REG_0F00 ) },
1616 { REG_TABLE (REG_0F01 ) },
1617 { "larS", { Gv, Ew } },
1618 { "lslS", { Gv, Ew } },
1619 { "(bad)", { XX } },
1620 { "syscall", { XX } },
1622 { "sysretP", { XX } },
1625 { "wbinvd", { XX } },
1626 { "(bad)", { XX } },
1628 { "(bad)", { XX } },
1629 { REG_TABLE (REG_0F0D) },
1630 { "femms", { XX } },
1631 { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */
1633 { PREFIX_TABLE (PREFIX_0F10) },
1634 { PREFIX_TABLE (PREFIX_0F11) },
1635 { PREFIX_TABLE (PREFIX_0F12) },
1636 { MOD_TABLE (MOD_0F13) },
1637 { "unpcklpX", { XM, EXx } },
1638 { "unpckhpX", { XM, EXx } },
1639 { PREFIX_TABLE (PREFIX_0F16) },
1640 { MOD_TABLE (MOD_0F17) },
1642 { REG_TABLE (REG_0F18) },
1651 { MOD_TABLE (MOD_0F20) },
1652 { MOD_TABLE (MOD_0F21) },
1653 { MOD_TABLE (MOD_0F22) },
1654 { MOD_TABLE (MOD_0F23) },
1655 { MOD_TABLE (MOD_0F24) },
1656 { THREE_BYTE_TABLE (THREE_BYTE_0F25) },
1657 { MOD_TABLE (MOD_0F26) },
1658 { "(bad)", { XX } },
1660 { "movapX", { XM, EXx } },
1661 { "movapX", { EXxS, XM } },
1662 { PREFIX_TABLE (PREFIX_0F2A) },
1663 { PREFIX_TABLE (PREFIX_0F2B) },
1664 { PREFIX_TABLE (PREFIX_0F2C) },
1665 { PREFIX_TABLE (PREFIX_0F2D) },
1666 { PREFIX_TABLE (PREFIX_0F2E) },
1667 { PREFIX_TABLE (PREFIX_0F2F) },
1669 { "wrmsr", { XX } },
1670 { "rdtsc", { XX } },
1671 { "rdmsr", { XX } },
1672 { "rdpmc", { XX } },
1673 { "sysenter", { XX } },
1674 { "sysexit", { XX } },
1675 { "(bad)", { XX } },
1676 { "getsec", { XX } },
1678 { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
1679 { "(bad)", { XX } },
1680 { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
1681 { "(bad)", { XX } },
1682 { "(bad)", { XX } },
1683 { "(bad)", { XX } },
1684 { "(bad)", { XX } },
1685 { "(bad)", { XX } },
1687 { "cmovoS", { Gv, Ev } },
1688 { "cmovnoS", { Gv, Ev } },
1689 { "cmovbS", { Gv, Ev } },
1690 { "cmovaeS", { Gv, Ev } },
1691 { "cmoveS", { Gv, Ev } },
1692 { "cmovneS", { Gv, Ev } },
1693 { "cmovbeS", { Gv, Ev } },
1694 { "cmovaS", { Gv, Ev } },
1696 { "cmovsS", { Gv, Ev } },
1697 { "cmovnsS", { Gv, Ev } },
1698 { "cmovpS", { Gv, Ev } },
1699 { "cmovnpS", { Gv, Ev } },
1700 { "cmovlS", { Gv, Ev } },
1701 { "cmovgeS", { Gv, Ev } },
1702 { "cmovleS", { Gv, Ev } },
1703 { "cmovgS", { Gv, Ev } },
1705 { MOD_TABLE (MOD_0F51) },
1706 { PREFIX_TABLE (PREFIX_0F51) },
1707 { PREFIX_TABLE (PREFIX_0F52) },
1708 { PREFIX_TABLE (PREFIX_0F53) },
1709 { "andpX", { XM, EXx } },
1710 { "andnpX", { XM, EXx } },
1711 { "orpX", { XM, EXx } },
1712 { "xorpX", { XM, EXx } },
1714 { PREFIX_TABLE (PREFIX_0F58) },
1715 { PREFIX_TABLE (PREFIX_0F59) },
1716 { PREFIX_TABLE (PREFIX_0F5A) },
1717 { PREFIX_TABLE (PREFIX_0F5B) },
1718 { PREFIX_TABLE (PREFIX_0F5C) },
1719 { PREFIX_TABLE (PREFIX_0F5D) },
1720 { PREFIX_TABLE (PREFIX_0F5E) },
1721 { PREFIX_TABLE (PREFIX_0F5F) },
1723 { PREFIX_TABLE (PREFIX_0F60) },
1724 { PREFIX_TABLE (PREFIX_0F61) },
1725 { PREFIX_TABLE (PREFIX_0F62) },
1726 { "packsswb", { MX, EM } },
1727 { "pcmpgtb", { MX, EM } },
1728 { "pcmpgtw", { MX, EM } },
1729 { "pcmpgtd", { MX, EM } },
1730 { "packuswb", { MX, EM } },
1732 { "punpckhbw", { MX, EM } },
1733 { "punpckhwd", { MX, EM } },
1734 { "punpckhdq", { MX, EM } },
1735 { "packssdw", { MX, EM } },
1736 { PREFIX_TABLE (PREFIX_0F6C) },
1737 { PREFIX_TABLE (PREFIX_0F6D) },
1738 { "movK", { MX, Edq } },
1739 { PREFIX_TABLE (PREFIX_0F6F) },
1741 { PREFIX_TABLE (PREFIX_0F70) },
1742 { REG_TABLE (REG_0F71) },
1743 { REG_TABLE (REG_0F72) },
1744 { REG_TABLE (REG_0F73) },
1745 { "pcmpeqb", { MX, EM } },
1746 { "pcmpeqw", { MX, EM } },
1747 { "pcmpeqd", { MX, EM } },
1750 { PREFIX_TABLE (PREFIX_0F78) },
1751 { PREFIX_TABLE (PREFIX_0F79) },
1752 { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
1753 { THREE_BYTE_TABLE (THREE_BYTE_0F7B) },
1754 { PREFIX_TABLE (PREFIX_0F7C) },
1755 { PREFIX_TABLE (PREFIX_0F7D) },
1756 { PREFIX_TABLE (PREFIX_0F7E) },
1757 { PREFIX_TABLE (PREFIX_0F7F) },
1759 { "joH", { Jv, XX, cond_jump_flag } },
1760 { "jnoH", { Jv, XX, cond_jump_flag } },
1761 { "jbH", { Jv, XX, cond_jump_flag } },
1762 { "jaeH", { Jv, XX, cond_jump_flag } },
1763 { "jeH", { Jv, XX, cond_jump_flag } },
1764 { "jneH", { Jv, XX, cond_jump_flag } },
1765 { "jbeH", { Jv, XX, cond_jump_flag } },
1766 { "jaH", { Jv, XX, cond_jump_flag } },
1768 { "jsH", { Jv, XX, cond_jump_flag } },
1769 { "jnsH", { Jv, XX, cond_jump_flag } },
1770 { "jpH", { Jv, XX, cond_jump_flag } },
1771 { "jnpH", { Jv, XX, cond_jump_flag } },
1772 { "jlH", { Jv, XX, cond_jump_flag } },
1773 { "jgeH", { Jv, XX, cond_jump_flag } },
1774 { "jleH", { Jv, XX, cond_jump_flag } },
1775 { "jgH", { Jv, XX, cond_jump_flag } },
1778 { "setno", { Eb } },
1780 { "setae", { Eb } },
1782 { "setne", { Eb } },
1783 { "setbe", { Eb } },
1787 { "setns", { Eb } },
1789 { "setnp", { Eb } },
1791 { "setge", { Eb } },
1792 { "setle", { Eb } },
1795 { "pushT", { fs } },
1797 { "cpuid", { XX } },
1798 { "btS", { Ev, Gv } },
1799 { "shldS", { Ev, Gv, Ib } },
1800 { "shldS", { Ev, Gv, CL } },
1801 { REG_TABLE (REG_0FA6) },
1802 { REG_TABLE (REG_0FA7) },
1804 { "pushT", { gs } },
1807 { "btsS", { Ev, Gv } },
1808 { "shrdS", { Ev, Gv, Ib } },
1809 { "shrdS", { Ev, Gv, CL } },
1810 { REG_TABLE (REG_0FAE) },
1811 { "imulS", { Gv, Ev } },
1813 { "cmpxchgB", { Eb, Gb } },
1814 { "cmpxchgS", { Ev, Gv } },
1815 { MOD_TABLE (MOD_0FB2) },
1816 { "btrS", { Ev, Gv } },
1817 { MOD_TABLE (MOD_0FB4) },
1818 { MOD_TABLE (MOD_0FB5) },
1819 { "movz{bR|x}", { Gv, Eb } },
1820 { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */
1822 { PREFIX_TABLE (PREFIX_0FB8) },
1824 { REG_TABLE (REG_0FBA) },
1825 { "btcS", { Ev, Gv } },
1826 { "bsfS", { Gv, Ev } },
1827 { PREFIX_TABLE (PREFIX_0FBD) },
1828 { "movs{bR|x}", { Gv, Eb } },
1829 { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */
1831 { "xaddB", { Eb, Gb } },
1832 { "xaddS", { Ev, Gv } },
1833 { PREFIX_TABLE (PREFIX_0FC2) },
1834 { PREFIX_TABLE (PREFIX_0FC3) },
1835 { "pinsrw", { MX, Edqw, Ib } },
1836 { "pextrw", { Gdq, MS, Ib } },
1837 { "shufpX", { XM, EXx, Ib } },
1838 { REG_TABLE (REG_0FC7) },
1840 { "bswap", { RMeAX } },
1841 { "bswap", { RMeCX } },
1842 { "bswap", { RMeDX } },
1843 { "bswap", { RMeBX } },
1844 { "bswap", { RMeSP } },
1845 { "bswap", { RMeBP } },
1846 { "bswap", { RMeSI } },
1847 { "bswap", { RMeDI } },
1849 { PREFIX_TABLE (PREFIX_0FD0) },
1850 { "psrlw", { MX, EM } },
1851 { "psrld", { MX, EM } },
1852 { "psrlq", { MX, EM } },
1853 { "paddq", { MX, EM } },
1854 { "pmullw", { MX, EM } },
1855 { PREFIX_TABLE (PREFIX_0FD6) },
1856 { MOD_TABLE (MOD_0FD7) },
1858 { "psubusb", { MX, EM } },
1859 { "psubusw", { MX, EM } },
1860 { "pminub", { MX, EM } },
1861 { "pand", { MX, EM } },
1862 { "paddusb", { MX, EM } },
1863 { "paddusw", { MX, EM } },
1864 { "pmaxub", { MX, EM } },
1865 { "pandn", { MX, EM } },
1867 { "pavgb", { MX, EM } },
1868 { "psraw", { MX, EM } },
1869 { "psrad", { MX, EM } },
1870 { "pavgw", { MX, EM } },
1871 { "pmulhuw", { MX, EM } },
1872 { "pmulhw", { MX, EM } },
1873 { PREFIX_TABLE (PREFIX_0FE6) },
1874 { PREFIX_TABLE (PREFIX_0FE7) },
1876 { "psubsb", { MX, EM } },
1877 { "psubsw", { MX, EM } },
1878 { "pminsw", { MX, EM } },
1879 { "por", { MX, EM } },
1880 { "paddsb", { MX, EM } },
1881 { "paddsw", { MX, EM } },
1882 { "pmaxsw", { MX, EM } },
1883 { "pxor", { MX, EM } },
1885 { PREFIX_TABLE (PREFIX_0FF0) },
1886 { "psllw", { MX, EM } },
1887 { "pslld", { MX, EM } },
1888 { "psllq", { MX, EM } },
1889 { "pmuludq", { MX, EM } },
1890 { "pmaddwd", { MX, EM } },
1891 { "psadbw", { MX, EM } },
1892 { PREFIX_TABLE (PREFIX_0FF7) },
1894 { "psubb", { MX, EM } },
1895 { "psubw", { MX, EM } },
1896 { "psubd", { MX, EM } },
1897 { "psubq", { MX, EM } },
1898 { "paddb", { MX, EM } },
1899 { "paddw", { MX, EM } },
1900 { "paddd", { MX, EM } },
1901 { "(bad)", { XX } },
1904 static const unsigned char onebyte_has_modrm[256] = {
1905 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1906 /* ------------------------------- */
1907 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1908 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1909 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1910 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1911 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1912 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1913 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1914 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1915 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1916 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1917 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1918 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1919 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1920 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1921 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1922 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1923 /* ------------------------------- */
1924 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1927 static const unsigned char twobyte_has_modrm[256] = {
1928 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1929 /* ------------------------------- */
1930 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1931 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
1932 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1933 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1934 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1935 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1936 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1937 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1938 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1939 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1940 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1941 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1942 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1943 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1944 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1945 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
1946 /* ------------------------------- */
1947 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1950 static char obuf[100];
1952 static char *mnemonicendp;
1953 static char scratchbuf[100];
1954 static unsigned char *start_codep;
1955 static unsigned char *insn_codep;
1956 static unsigned char *codep;
1957 static const char *lock_prefix;
1958 static const char *data_prefix;
1959 static const char *addr_prefix;
1960 static const char *repz_prefix;
1961 static const char *repnz_prefix;
1962 static disassemble_info *the_info;
1970 static unsigned char need_modrm;
1973 int register_specifier;
1979 static unsigned char need_vex;
1980 static unsigned char need_vex_reg;
1981 static unsigned char vex_w_done;
1989 /* If we are accessing mod/rm/reg without need_modrm set, then the
1990 values are stale. Hitting this abort likely indicates that you
1991 need to update onebyte_has_modrm or twobyte_has_modrm. */
1992 #define MODRM_CHECK if (!need_modrm) abort ()
1994 static const char **names64;
1995 static const char **names32;
1996 static const char **names16;
1997 static const char **names8;
1998 static const char **names8rex;
1999 static const char **names_seg;
2000 static const char *index64;
2001 static const char *index32;
2002 static const char **index16;
2004 static const char *intel_names64[] = {
2005 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2006 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2008 static const char *intel_names32[] = {
2009 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2010 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2012 static const char *intel_names16[] = {
2013 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2014 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2016 static const char *intel_names8[] = {
2017 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2019 static const char *intel_names8rex[] = {
2020 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2021 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2023 static const char *intel_names_seg[] = {
2024 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2026 static const char *intel_index64 = "riz";
2027 static const char *intel_index32 = "eiz";
2028 static const char *intel_index16[] = {
2029 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2032 static const char *att_names64[] = {
2033 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2034 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2036 static const char *att_names32[] = {
2037 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2038 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2040 static const char *att_names16[] = {
2041 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2042 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2044 static const char *att_names8[] = {
2045 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2047 static const char *att_names8rex[] = {
2048 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2049 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2051 static const char *att_names_seg[] = {
2052 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2054 static const char *att_index64 = "%riz";
2055 static const char *att_index32 = "%eiz";
2056 static const char *att_index16[] = {
2057 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2060 static const struct dis386 reg_table[][8] = {
2063 { "addA", { Eb, Ib } },
2064 { "orA", { Eb, Ib } },
2065 { "adcA", { Eb, Ib } },
2066 { "sbbA", { Eb, Ib } },
2067 { "andA", { Eb, Ib } },
2068 { "subA", { Eb, Ib } },
2069 { "xorA", { Eb, Ib } },
2070 { "cmpA", { Eb, Ib } },
2074 { "addQ", { Ev, Iv } },
2075 { "orQ", { Ev, Iv } },
2076 { "adcQ", { Ev, Iv } },
2077 { "sbbQ", { Ev, Iv } },
2078 { "andQ", { Ev, Iv } },
2079 { "subQ", { Ev, Iv } },
2080 { "xorQ", { Ev, Iv } },
2081 { "cmpQ", { Ev, Iv } },
2085 { "addQ", { Ev, sIb } },
2086 { "orQ", { Ev, sIb } },
2087 { "adcQ", { Ev, sIb } },
2088 { "sbbQ", { Ev, sIb } },
2089 { "andQ", { Ev, sIb } },
2090 { "subQ", { Ev, sIb } },
2091 { "xorQ", { Ev, sIb } },
2092 { "cmpQ", { Ev, sIb } },
2096 { "popU", { stackEv } },
2097 { "(bad)", { XX } },
2098 { "(bad)", { XX } },
2099 { "(bad)", { XX } },
2100 { "(bad)", { XX } },
2101 { "(bad)", { XX } },
2102 { "(bad)", { XX } },
2103 { "(bad)", { XX } },
2107 { "rolA", { Eb, Ib } },
2108 { "rorA", { Eb, Ib } },
2109 { "rclA", { Eb, Ib } },
2110 { "rcrA", { Eb, Ib } },
2111 { "shlA", { Eb, Ib } },
2112 { "shrA", { Eb, Ib } },
2113 { "(bad)", { XX } },
2114 { "sarA", { Eb, Ib } },
2118 { "rolQ", { Ev, Ib } },
2119 { "rorQ", { Ev, Ib } },
2120 { "rclQ", { Ev, Ib } },
2121 { "rcrQ", { Ev, Ib } },
2122 { "shlQ", { Ev, Ib } },
2123 { "shrQ", { Ev, Ib } },
2124 { "(bad)", { XX } },
2125 { "sarQ", { Ev, Ib } },
2129 { "movA", { Eb, Ib } },
2130 { "(bad)", { XX } },
2131 { "(bad)", { XX } },
2132 { "(bad)", { XX } },
2133 { "(bad)", { XX } },
2134 { "(bad)", { XX } },
2135 { "(bad)", { XX } },
2136 { "(bad)", { XX } },
2140 { "movQ", { Ev, Iv } },
2141 { "(bad)", { XX } },
2142 { "(bad)", { XX } },
2143 { "(bad)", { XX } },
2144 { "(bad)", { XX } },
2145 { "(bad)", { XX } },
2146 { "(bad)", { XX } },
2147 { "(bad)", { XX } },
2151 { "rolA", { Eb, I1 } },
2152 { "rorA", { Eb, I1 } },
2153 { "rclA", { Eb, I1 } },
2154 { "rcrA", { Eb, I1 } },
2155 { "shlA", { Eb, I1 } },
2156 { "shrA", { Eb, I1 } },
2157 { "(bad)", { XX } },
2158 { "sarA", { Eb, I1 } },
2162 { "rolQ", { Ev, I1 } },
2163 { "rorQ", { Ev, I1 } },
2164 { "rclQ", { Ev, I1 } },
2165 { "rcrQ", { Ev, I1 } },
2166 { "shlQ", { Ev, I1 } },
2167 { "shrQ", { Ev, I1 } },
2168 { "(bad)", { XX } },
2169 { "sarQ", { Ev, I1 } },
2173 { "rolA", { Eb, CL } },
2174 { "rorA", { Eb, CL } },
2175 { "rclA", { Eb, CL } },
2176 { "rcrA", { Eb, CL } },
2177 { "shlA", { Eb, CL } },
2178 { "shrA", { Eb, CL } },
2179 { "(bad)", { XX } },
2180 { "sarA", { Eb, CL } },
2184 { "rolQ", { Ev, CL } },
2185 { "rorQ", { Ev, CL } },
2186 { "rclQ", { Ev, CL } },
2187 { "rcrQ", { Ev, CL } },
2188 { "shlQ", { Ev, CL } },
2189 { "shrQ", { Ev, CL } },
2190 { "(bad)", { XX } },
2191 { "sarQ", { Ev, CL } },
2195 { "testA", { Eb, Ib } },
2196 { "(bad)", { XX } },
2199 { "mulA", { Eb } }, /* Don't print the implicit %al register, */
2200 { "imulA", { Eb } }, /* to distinguish these opcodes from other */
2201 { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */
2202 { "idivA", { Eb } }, /* and idiv for consistency. */
2206 { "testQ", { Ev, Iv } },
2207 { "(bad)", { XX } },
2210 { "mulQ", { Ev } }, /* Don't print the implicit register. */
2211 { "imulQ", { Ev } },
2213 { "idivQ", { Ev } },
2219 { "(bad)", { XX } },
2220 { "(bad)", { XX } },
2221 { "(bad)", { XX } },
2222 { "(bad)", { XX } },
2223 { "(bad)", { XX } },
2224 { "(bad)", { XX } },
2230 { "callT", { indirEv } },
2231 { "JcallT", { indirEp } },
2232 { "jmpT", { indirEv } },
2233 { "JjmpT", { indirEp } },
2234 { "pushU", { stackEv } },
2235 { "(bad)", { XX } },
2239 { "sldtD", { Sv } },
2245 { "(bad)", { XX } },
2246 { "(bad)", { XX } },
2250 { MOD_TABLE (MOD_0F01_REG_0) },
2251 { MOD_TABLE (MOD_0F01_REG_1) },
2252 { MOD_TABLE (MOD_0F01_REG_2) },
2253 { MOD_TABLE (MOD_0F01_REG_3) },
2254 { "smswD", { Sv } },
2255 { "(bad)", { XX } },
2257 { MOD_TABLE (MOD_0F01_REG_7) },
2261 { "prefetch", { Eb } },
2262 { "prefetchw", { Eb } },
2263 { "(bad)", { XX } },
2264 { "(bad)", { XX } },
2265 { "(bad)", { XX } },
2266 { "(bad)", { XX } },
2267 { "(bad)", { XX } },
2268 { "(bad)", { XX } },
2272 { MOD_TABLE (MOD_0F18_REG_0) },
2273 { MOD_TABLE (MOD_0F18_REG_1) },
2274 { MOD_TABLE (MOD_0F18_REG_2) },
2275 { MOD_TABLE (MOD_0F18_REG_3) },
2276 { "(bad)", { XX } },
2277 { "(bad)", { XX } },
2278 { "(bad)", { XX } },
2279 { "(bad)", { XX } },
2283 { "(bad)", { XX } },
2284 { "(bad)", { XX } },
2285 { MOD_TABLE (MOD_0F71_REG_2) },
2286 { "(bad)", { XX } },
2287 { MOD_TABLE (MOD_0F71_REG_4) },
2288 { "(bad)", { XX } },
2289 { MOD_TABLE (MOD_0F71_REG_6) },
2290 { "(bad)", { XX } },
2294 { "(bad)", { XX } },
2295 { "(bad)", { XX } },
2296 { MOD_TABLE (MOD_0F72_REG_2) },
2297 { "(bad)", { XX } },
2298 { MOD_TABLE (MOD_0F72_REG_4) },
2299 { "(bad)", { XX } },
2300 { MOD_TABLE (MOD_0F72_REG_6) },
2301 { "(bad)", { XX } },
2305 { "(bad)", { XX } },
2306 { "(bad)", { XX } },
2307 { MOD_TABLE (MOD_0F73_REG_2) },
2308 { MOD_TABLE (MOD_0F73_REG_3) },
2309 { "(bad)", { XX } },
2310 { "(bad)", { XX } },
2311 { MOD_TABLE (MOD_0F73_REG_6) },
2312 { MOD_TABLE (MOD_0F73_REG_7) },
2316 { "montmul", { { OP_0f07, 0 } } },
2317 { "xsha1", { { OP_0f07, 0 } } },
2318 { "xsha256", { { OP_0f07, 0 } } },
2319 { "(bad)", { { OP_0f07, 0 } } },
2320 { "(bad)", { { OP_0f07, 0 } } },
2321 { "(bad)", { { OP_0f07, 0 } } },
2322 { "(bad)", { { OP_0f07, 0 } } },
2323 { "(bad)", { { OP_0f07, 0 } } },
2327 { "xstore-rng", { { OP_0f07, 0 } } },
2328 { "xcrypt-ecb", { { OP_0f07, 0 } } },
2329 { "xcrypt-cbc", { { OP_0f07, 0 } } },
2330 { "xcrypt-ctr", { { OP_0f07, 0 } } },
2331 { "xcrypt-cfb", { { OP_0f07, 0 } } },
2332 { "xcrypt-ofb", { { OP_0f07, 0 } } },
2333 { "(bad)", { { OP_0f07, 0 } } },
2334 { "(bad)", { { OP_0f07, 0 } } },
2338 { MOD_TABLE (MOD_0FAE_REG_0) },
2339 { MOD_TABLE (MOD_0FAE_REG_1) },
2340 { MOD_TABLE (MOD_0FAE_REG_2) },
2341 { MOD_TABLE (MOD_0FAE_REG_3) },
2342 { MOD_TABLE (MOD_0FAE_REG_4) },
2343 { MOD_TABLE (MOD_0FAE_REG_5) },
2344 { MOD_TABLE (MOD_0FAE_REG_6) },
2345 { MOD_TABLE (MOD_0FAE_REG_7) },
2349 { "(bad)", { XX } },
2350 { "(bad)", { XX } },
2351 { "(bad)", { XX } },
2352 { "(bad)", { XX } },
2353 { "btQ", { Ev, Ib } },
2354 { "btsQ", { Ev, Ib } },
2355 { "btrQ", { Ev, Ib } },
2356 { "btcQ", { Ev, Ib } },
2360 { "(bad)", { XX } },
2361 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
2362 { "(bad)", { XX } },
2363 { "(bad)", { XX } },
2364 { "(bad)", { XX } },
2365 { "(bad)", { XX } },
2366 { MOD_TABLE (MOD_0FC7_REG_6) },
2367 { MOD_TABLE (MOD_0FC7_REG_7) },
2371 { "(bad)", { XX } },
2372 { "(bad)", { XX } },
2373 { MOD_TABLE (MOD_VEX_71_REG_2) },
2374 { "(bad)", { XX } },
2375 { MOD_TABLE (MOD_VEX_71_REG_4) },
2376 { "(bad)", { XX } },
2377 { MOD_TABLE (MOD_VEX_71_REG_6) },
2378 { "(bad)", { XX } },
2382 { "(bad)", { XX } },
2383 { "(bad)", { XX } },
2384 { MOD_TABLE (MOD_VEX_72_REG_2) },
2385 { "(bad)", { XX } },
2386 { MOD_TABLE (MOD_VEX_72_REG_4) },
2387 { "(bad)", { XX } },
2388 { MOD_TABLE (MOD_VEX_72_REG_6) },
2389 { "(bad)", { XX } },
2393 { "(bad)", { XX } },
2394 { "(bad)", { XX } },
2395 { MOD_TABLE (MOD_VEX_73_REG_2) },
2396 { MOD_TABLE (MOD_VEX_73_REG_3) },
2397 { "(bad)", { XX } },
2398 { "(bad)", { XX } },
2399 { MOD_TABLE (MOD_VEX_73_REG_6) },
2400 { MOD_TABLE (MOD_VEX_73_REG_7) },
2404 { "(bad)", { XX } },
2405 { "(bad)", { XX } },
2406 { MOD_TABLE (MOD_VEX_AE_REG_2) },
2407 { MOD_TABLE (MOD_VEX_AE_REG_3) },
2408 { "(bad)", { XX } },
2409 { "(bad)", { XX } },
2410 { "(bad)", { XX } },
2411 { "(bad)", { XX } },
2415 static const struct dis386 prefix_table[][4] = {
2418 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2419 { "pause", { XX } },
2420 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2421 { "(bad)", { XX } },
2426 { "movups", { XM, EXx } },
2427 { "movss", { XM, EXd } },
2428 { "movupd", { XM, EXx } },
2429 { "movsd", { XM, EXq } },
2434 { "movups", { EXxS, XM } },
2435 { "movss", { EXdS, XM } },
2436 { "movupd", { EXxS, XM } },
2437 { "movsd", { EXqS, XM } },
2442 { MOD_TABLE (MOD_0F12_PREFIX_0) },
2443 { "movsldup", { XM, EXx } },
2444 { "movlpd", { XM, EXq } },
2445 { "movddup", { XM, EXq } },
2450 { MOD_TABLE (MOD_0F16_PREFIX_0) },
2451 { "movshdup", { XM, EXx } },
2452 { "movhpd", { XM, EXq } },
2453 { "(bad)", { XX } },
2458 { "cvtpi2ps", { XM, EMCq } },
2459 { "cvtsi2ss%LQ", { XM, Ev } },
2460 { "cvtpi2pd", { XM, EMCq } },
2461 { "cvtsi2sd%LQ", { XM, Ev } },
2466 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2467 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2468 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2469 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
2474 { "cvttps2pi", { MXC, EXq } },
2475 { "cvttss2siY", { Gv, EXd } },
2476 { "cvttpd2pi", { MXC, EXx } },
2477 { "cvttsd2siY", { Gv, EXq } },
2482 { "cvtps2pi", { MXC, EXq } },
2483 { "cvtss2siY", { Gv, EXd } },
2484 { "cvtpd2pi", { MXC, EXx } },
2485 { "cvtsd2siY", { Gv, EXq } },
2490 { "ucomiss",{ XM, EXd } },
2491 { "(bad)", { XX } },
2492 { "ucomisd",{ XM, EXq } },
2493 { "(bad)", { XX } },
2498 { "comiss", { XM, EXd } },
2499 { "(bad)", { XX } },
2500 { "comisd", { XM, EXq } },
2501 { "(bad)", { XX } },
2506 { "sqrtps", { XM, EXx } },
2507 { "sqrtss", { XM, EXd } },
2508 { "sqrtpd", { XM, EXx } },
2509 { "sqrtsd", { XM, EXq } },
2514 { "rsqrtps",{ XM, EXx } },
2515 { "rsqrtss",{ XM, EXd } },
2516 { "(bad)", { XX } },
2517 { "(bad)", { XX } },
2522 { "rcpps", { XM, EXx } },
2523 { "rcpss", { XM, EXd } },
2524 { "(bad)", { XX } },
2525 { "(bad)", { XX } },
2530 { "addps", { XM, EXx } },
2531 { "addss", { XM, EXd } },
2532 { "addpd", { XM, EXx } },
2533 { "addsd", { XM, EXq } },
2538 { "mulps", { XM, EXx } },
2539 { "mulss", { XM, EXd } },
2540 { "mulpd", { XM, EXx } },
2541 { "mulsd", { XM, EXq } },
2546 { "cvtps2pd", { XM, EXq } },
2547 { "cvtss2sd", { XM, EXd } },
2548 { "cvtpd2ps", { XM, EXx } },
2549 { "cvtsd2ss", { XM, EXq } },
2554 { "cvtdq2ps", { XM, EXx } },
2555 { "cvttps2dq", { XM, EXx } },
2556 { "cvtps2dq", { XM, EXx } },
2557 { "(bad)", { XX } },
2562 { "subps", { XM, EXx } },
2563 { "subss", { XM, EXd } },
2564 { "subpd", { XM, EXx } },
2565 { "subsd", { XM, EXq } },
2570 { "minps", { XM, EXx } },
2571 { "minss", { XM, EXd } },
2572 { "minpd", { XM, EXx } },
2573 { "minsd", { XM, EXq } },
2578 { "divps", { XM, EXx } },
2579 { "divss", { XM, EXd } },
2580 { "divpd", { XM, EXx } },
2581 { "divsd", { XM, EXq } },
2586 { "maxps", { XM, EXx } },
2587 { "maxss", { XM, EXd } },
2588 { "maxpd", { XM, EXx } },
2589 { "maxsd", { XM, EXq } },
2594 { "punpcklbw",{ MX, EMd } },
2595 { "(bad)", { XX } },
2596 { "punpcklbw",{ MX, EMx } },
2597 { "(bad)", { XX } },
2602 { "punpcklwd",{ MX, EMd } },
2603 { "(bad)", { XX } },
2604 { "punpcklwd",{ MX, EMx } },
2605 { "(bad)", { XX } },
2610 { "punpckldq",{ MX, EMd } },
2611 { "(bad)", { XX } },
2612 { "punpckldq",{ MX, EMx } },
2613 { "(bad)", { XX } },
2618 { "(bad)", { XX } },
2619 { "(bad)", { XX } },
2620 { "punpcklqdq", { XM, EXx } },
2621 { "(bad)", { XX } },
2626 { "(bad)", { XX } },
2627 { "(bad)", { XX } },
2628 { "punpckhqdq", { XM, EXx } },
2629 { "(bad)", { XX } },
2634 { "movq", { MX, EM } },
2635 { "movdqu", { XM, EXx } },
2636 { "movdqa", { XM, EXx } },
2637 { "(bad)", { XX } },
2642 { "pshufw", { MX, EM, Ib } },
2643 { "pshufhw",{ XM, EXx, Ib } },
2644 { "pshufd", { XM, EXx, Ib } },
2645 { "pshuflw",{ XM, EXx, Ib } },
2648 /* PREFIX_0F73_REG_3 */
2650 { "(bad)", { XX } },
2651 { "(bad)", { XX } },
2652 { "psrldq", { XS, Ib } },
2653 { "(bad)", { XX } },
2656 /* PREFIX_0F73_REG_7 */
2658 { "(bad)", { XX } },
2659 { "(bad)", { XX } },
2660 { "pslldq", { XS, Ib } },
2661 { "(bad)", { XX } },
2666 {"vmread", { Em, Gm } },
2668 {"extrq", { XS, Ib, Ib } },
2669 {"insertq", { XM, XS, Ib, Ib } },
2674 {"vmwrite", { Gm, Em } },
2676 {"extrq", { XM, XS } },
2677 {"insertq", { XM, XS } },
2682 { "(bad)", { XX } },
2683 { "(bad)", { XX } },
2684 { "haddpd", { XM, EXx } },
2685 { "haddps", { XM, EXx } },
2690 { "(bad)", { XX } },
2691 { "(bad)", { XX } },
2692 { "hsubpd", { XM, EXx } },
2693 { "hsubps", { XM, EXx } },
2698 { "movK", { Edq, MX } },
2699 { "movq", { XM, EXq } },
2700 { "movK", { Edq, XM } },
2701 { "(bad)", { XX } },
2706 { "movq", { EMS, MX } },
2707 { "movdqu", { EXxS, XM } },
2708 { "movdqa", { EXxS, XM } },
2709 { "(bad)", { XX } },
2714 { "(bad)", { XX } },
2715 { "popcntS", { Gv, Ev } },
2716 { "(bad)", { XX } },
2717 { "(bad)", { XX } },
2722 { "bsrS", { Gv, Ev } },
2723 { "lzcntS", { Gv, Ev } },
2724 { "bsrS", { Gv, Ev } },
2725 { "(bad)", { XX } },
2730 { "cmpps", { XM, EXx, CMP } },
2731 { "cmpss", { XM, EXd, CMP } },
2732 { "cmppd", { XM, EXx, CMP } },
2733 { "cmpsd", { XM, EXq, CMP } },
2738 { "movntiS", { Ma, Gv } },
2739 { "(bad)", { XX } },
2740 { "(bad)", { XX } },
2741 { "(bad)", { XX } },
2744 /* PREFIX_0FC7_REG_6 */
2746 { "vmptrld",{ Mq } },
2747 { "vmxon", { Mq } },
2748 { "vmclear",{ Mq } },
2749 { "(bad)", { XX } },
2754 { "(bad)", { XX } },
2755 { "(bad)", { XX } },
2756 { "addsubpd", { XM, EXx } },
2757 { "addsubps", { XM, EXx } },
2762 { "(bad)", { XX } },
2763 { "movq2dq",{ XM, MS } },
2764 { "movq", { EXqS, XM } },
2765 { "movdq2q",{ MX, XS } },
2770 { "(bad)", { XX } },
2771 { "cvtdq2pd", { XM, EXq } },
2772 { "cvttpd2dq", { XM, EXx } },
2773 { "cvtpd2dq", { XM, EXx } },
2778 { "movntq", { Mq, MX } },
2779 { "(bad)", { XX } },
2780 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
2781 { "(bad)", { XX } },
2786 { "(bad)", { XX } },
2787 { "(bad)", { XX } },
2788 { "(bad)", { XX } },
2789 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
2794 { "maskmovq", { MX, MS } },
2795 { "(bad)", { XX } },
2796 { "maskmovdqu", { XM, XS } },
2797 { "(bad)", { XX } },
2802 { "(bad)", { XX } },
2803 { "(bad)", { XX } },
2804 { "pblendvb", { XM, EXx, XMM0 } },
2805 { "(bad)", { XX } },
2810 { "(bad)", { XX } },
2811 { "(bad)", { XX } },
2812 { "blendvps", { XM, EXx, XMM0 } },
2813 { "(bad)", { XX } },
2818 { "(bad)", { XX } },
2819 { "(bad)", { XX } },
2820 { "blendvpd", { XM, EXx, XMM0 } },
2821 { "(bad)", { XX } },
2826 { "(bad)", { XX } },
2827 { "(bad)", { XX } },
2828 { "ptest", { XM, EXx } },
2829 { "(bad)", { XX } },
2834 { "(bad)", { XX } },
2835 { "(bad)", { XX } },
2836 { "pmovsxbw", { XM, EXq } },
2837 { "(bad)", { XX } },
2842 { "(bad)", { XX } },
2843 { "(bad)", { XX } },
2844 { "pmovsxbd", { XM, EXd } },
2845 { "(bad)", { XX } },
2850 { "(bad)", { XX } },
2851 { "(bad)", { XX } },
2852 { "pmovsxbq", { XM, EXw } },
2853 { "(bad)", { XX } },
2858 { "(bad)", { XX } },
2859 { "(bad)", { XX } },
2860 { "pmovsxwd", { XM, EXq } },
2861 { "(bad)", { XX } },
2866 { "(bad)", { XX } },
2867 { "(bad)", { XX } },
2868 { "pmovsxwq", { XM, EXd } },
2869 { "(bad)", { XX } },
2874 { "(bad)", { XX } },
2875 { "(bad)", { XX } },
2876 { "pmovsxdq", { XM, EXq } },
2877 { "(bad)", { XX } },
2882 { "(bad)", { XX } },
2883 { "(bad)", { XX } },
2884 { "pmuldq", { XM, EXx } },
2885 { "(bad)", { XX } },
2890 { "(bad)", { XX } },
2891 { "(bad)", { XX } },
2892 { "pcmpeqq", { XM, EXx } },
2893 { "(bad)", { XX } },
2898 { "(bad)", { XX } },
2899 { "(bad)", { XX } },
2900 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
2901 { "(bad)", { XX } },
2906 { "(bad)", { XX } },
2907 { "(bad)", { XX } },
2908 { "packusdw", { XM, EXx } },
2909 { "(bad)", { XX } },
2914 { "(bad)", { XX } },
2915 { "(bad)", { XX } },
2916 { "pmovzxbw", { XM, EXq } },
2917 { "(bad)", { XX } },
2922 { "(bad)", { XX } },
2923 { "(bad)", { XX } },
2924 { "pmovzxbd", { XM, EXd } },
2925 { "(bad)", { XX } },
2930 { "(bad)", { XX } },
2931 { "(bad)", { XX } },
2932 { "pmovzxbq", { XM, EXw } },
2933 { "(bad)", { XX } },
2938 { "(bad)", { XX } },
2939 { "(bad)", { XX } },
2940 { "pmovzxwd", { XM, EXq } },
2941 { "(bad)", { XX } },
2946 { "(bad)", { XX } },
2947 { "(bad)", { XX } },
2948 { "pmovzxwq", { XM, EXd } },
2949 { "(bad)", { XX } },
2954 { "(bad)", { XX } },
2955 { "(bad)", { XX } },
2956 { "pmovzxdq", { XM, EXq } },
2957 { "(bad)", { XX } },
2962 { "(bad)", { XX } },
2963 { "(bad)", { XX } },
2964 { "pcmpgtq", { XM, EXx } },
2965 { "(bad)", { XX } },
2970 { "(bad)", { XX } },
2971 { "(bad)", { XX } },
2972 { "pminsb", { XM, EXx } },
2973 { "(bad)", { XX } },
2978 { "(bad)", { XX } },
2979 { "(bad)", { XX } },
2980 { "pminsd", { XM, EXx } },
2981 { "(bad)", { XX } },
2986 { "(bad)", { XX } },
2987 { "(bad)", { XX } },
2988 { "pminuw", { XM, EXx } },
2989 { "(bad)", { XX } },
2994 { "(bad)", { XX } },
2995 { "(bad)", { XX } },
2996 { "pminud", { XM, EXx } },
2997 { "(bad)", { XX } },
3002 { "(bad)", { XX } },
3003 { "(bad)", { XX } },
3004 { "pmaxsb", { XM, EXx } },
3005 { "(bad)", { XX } },
3010 { "(bad)", { XX } },
3011 { "(bad)", { XX } },
3012 { "pmaxsd", { XM, EXx } },
3013 { "(bad)", { XX } },
3018 { "(bad)", { XX } },
3019 { "(bad)", { XX } },
3020 { "pmaxuw", { XM, EXx } },
3021 { "(bad)", { XX } },
3026 { "(bad)", { XX } },
3027 { "(bad)", { XX } },
3028 { "pmaxud", { XM, EXx } },
3029 { "(bad)", { XX } },
3034 { "(bad)", { XX } },
3035 { "(bad)", { XX } },
3036 { "pmulld", { XM, EXx } },
3037 { "(bad)", { XX } },
3042 { "(bad)", { XX } },
3043 { "(bad)", { XX } },
3044 { "phminposuw", { XM, EXx } },
3045 { "(bad)", { XX } },
3050 { "(bad)", { XX } },
3051 { "(bad)", { XX } },
3052 { "invept", { Gm, Mo } },
3053 { "(bad)", { XX } },
3058 { "(bad)", { XX } },
3059 { "(bad)", { XX } },
3060 { "invvpid", { Gm, Mo } },
3061 { "(bad)", { XX } },
3066 { "(bad)", { XX } },
3067 { "(bad)", { XX } },
3068 { "aesimc", { XM, EXx } },
3069 { "(bad)", { XX } },
3074 { "(bad)", { XX } },
3075 { "(bad)", { XX } },
3076 { "aesenc", { XM, EXx } },
3077 { "(bad)", { XX } },
3082 { "(bad)", { XX } },
3083 { "(bad)", { XX } },
3084 { "aesenclast", { XM, EXx } },
3085 { "(bad)", { XX } },
3090 { "(bad)", { XX } },
3091 { "(bad)", { XX } },
3092 { "aesdec", { XM, EXx } },
3093 { "(bad)", { XX } },
3098 { "(bad)", { XX } },
3099 { "(bad)", { XX } },
3100 { "aesdeclast", { XM, EXx } },
3101 { "(bad)", { XX } },
3106 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3107 { "(bad)", { XX } },
3108 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3109 { "crc32", { Gdq, { CRC32_Fixup, b_mode } } },
3114 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3115 { "(bad)", { XX } },
3116 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3117 { "crc32", { Gdq, { CRC32_Fixup, v_mode } } },
3122 { "(bad)", { XX } },
3123 { "(bad)", { XX } },
3124 { "roundps", { XM, EXx, Ib } },
3125 { "(bad)", { XX } },
3130 { "(bad)", { XX } },
3131 { "(bad)", { XX } },
3132 { "roundpd", { XM, EXx, Ib } },
3133 { "(bad)", { XX } },
3138 { "(bad)", { XX } },
3139 { "(bad)", { XX } },
3140 { "roundss", { XM, EXd, Ib } },
3141 { "(bad)", { XX } },
3146 { "(bad)", { XX } },
3147 { "(bad)", { XX } },
3148 { "roundsd", { XM, EXq, Ib } },
3149 { "(bad)", { XX } },
3154 { "(bad)", { XX } },
3155 { "(bad)", { XX } },
3156 { "blendps", { XM, EXx, Ib } },
3157 { "(bad)", { XX } },
3162 { "(bad)", { XX } },
3163 { "(bad)", { XX } },
3164 { "blendpd", { XM, EXx, Ib } },
3165 { "(bad)", { XX } },
3170 { "(bad)", { XX } },
3171 { "(bad)", { XX } },
3172 { "pblendw", { XM, EXx, Ib } },
3173 { "(bad)", { XX } },
3178 { "(bad)", { XX } },
3179 { "(bad)", { XX } },
3180 { "pextrb", { Edqb, XM, Ib } },
3181 { "(bad)", { XX } },
3186 { "(bad)", { XX } },
3187 { "(bad)", { XX } },
3188 { "pextrw", { Edqw, XM, Ib } },
3189 { "(bad)", { XX } },
3194 { "(bad)", { XX } },
3195 { "(bad)", { XX } },
3196 { "pextrK", { Edq, XM, Ib } },
3197 { "(bad)", { XX } },
3202 { "(bad)", { XX } },
3203 { "(bad)", { XX } },
3204 { "extractps", { Edqd, XM, Ib } },
3205 { "(bad)", { XX } },
3210 { "(bad)", { XX } },
3211 { "(bad)", { XX } },
3212 { "pinsrb", { XM, Edqb, Ib } },
3213 { "(bad)", { XX } },
3218 { "(bad)", { XX } },
3219 { "(bad)", { XX } },
3220 { "insertps", { XM, EXd, Ib } },
3221 { "(bad)", { XX } },
3226 { "(bad)", { XX } },
3227 { "(bad)", { XX } },
3228 { "pinsrK", { XM, Edq, Ib } },
3229 { "(bad)", { XX } },
3234 { "(bad)", { XX } },
3235 { "(bad)", { XX } },
3236 { "dpps", { XM, EXx, Ib } },
3237 { "(bad)", { XX } },
3242 { "(bad)", { XX } },
3243 { "(bad)", { XX } },
3244 { "dppd", { XM, EXx, Ib } },
3245 { "(bad)", { XX } },
3250 { "(bad)", { XX } },
3251 { "(bad)", { XX } },
3252 { "mpsadbw", { XM, EXx, Ib } },
3253 { "(bad)", { XX } },
3258 { "(bad)", { XX } },
3259 { "(bad)", { XX } },
3260 { "pclmulqdq", { XM, EXx, PCLMUL } },
3261 { "(bad)", { XX } },
3266 { "(bad)", { XX } },
3267 { "(bad)", { XX } },
3268 { "pcmpestrm", { XM, EXx, Ib } },
3269 { "(bad)", { XX } },
3274 { "(bad)", { XX } },
3275 { "(bad)", { XX } },
3276 { "pcmpestri", { XM, EXx, Ib } },
3277 { "(bad)", { XX } },
3282 { "(bad)", { XX } },
3283 { "(bad)", { XX } },
3284 { "pcmpistrm", { XM, EXx, Ib } },
3285 { "(bad)", { XX } },
3290 { "(bad)", { XX } },
3291 { "(bad)", { XX } },
3292 { "pcmpistri", { XM, EXx, Ib } },
3293 { "(bad)", { XX } },
3298 { "(bad)", { XX } },
3299 { "(bad)", { XX } },
3300 { "aeskeygenassist", { XM, EXx, Ib } },
3301 { "(bad)", { XX } },
3306 { "vmovups", { XM, EXx } },
3307 { VEX_LEN_TABLE (VEX_LEN_10_P_1) },
3308 { "vmovupd", { XM, EXx } },
3309 { VEX_LEN_TABLE (VEX_LEN_10_P_3) },
3314 { "vmovups", { EXxS, XM } },
3315 { VEX_LEN_TABLE (VEX_LEN_11_P_1) },
3316 { "vmovupd", { EXxS, XM } },
3317 { VEX_LEN_TABLE (VEX_LEN_11_P_3) },
3322 { MOD_TABLE (MOD_VEX_12_PREFIX_0) },
3323 { "vmovsldup", { XM, EXx } },
3324 { VEX_LEN_TABLE (VEX_LEN_12_P_2) },
3325 { "vmovddup", { XM, EXymmq } },
3330 { MOD_TABLE (MOD_VEX_16_PREFIX_0) },
3331 { "vmovshdup", { XM, EXx } },
3332 { VEX_LEN_TABLE (VEX_LEN_16_P_2) },
3333 { "(bad)", { XX } },
3338 { "(bad)", { XX } },
3339 { VEX_LEN_TABLE (VEX_LEN_2A_P_1) },
3340 { "(bad)", { XX } },
3341 { VEX_LEN_TABLE (VEX_LEN_2A_P_3) },
3346 { "(bad)", { XX } },
3347 { VEX_LEN_TABLE (VEX_LEN_2C_P_1) },
3348 { "(bad)", { XX } },
3349 { VEX_LEN_TABLE (VEX_LEN_2C_P_3) },
3354 { "(bad)", { XX } },
3355 { VEX_LEN_TABLE (VEX_LEN_2D_P_1) },
3356 { "(bad)", { XX } },
3357 { VEX_LEN_TABLE (VEX_LEN_2D_P_3) },
3362 { VEX_LEN_TABLE (VEX_LEN_2E_P_0) },
3363 { "(bad)", { XX } },
3364 { VEX_LEN_TABLE (VEX_LEN_2E_P_2) },
3365 { "(bad)", { XX } },
3370 { VEX_LEN_TABLE (VEX_LEN_2F_P_0) },
3371 { "(bad)", { XX } },
3372 { VEX_LEN_TABLE (VEX_LEN_2F_P_2) },
3373 { "(bad)", { XX } },
3378 { "vsqrtps", { XM, EXx } },
3379 { VEX_LEN_TABLE (VEX_LEN_51_P_1) },
3380 { "vsqrtpd", { XM, EXx } },
3381 { VEX_LEN_TABLE (VEX_LEN_51_P_3) },
3386 { "vrsqrtps", { XM, EXx } },
3387 { VEX_LEN_TABLE (VEX_LEN_52_P_1) },
3388 { "(bad)", { XX } },
3389 { "(bad)", { XX } },
3394 { "vrcpps", { XM, EXx } },
3395 { VEX_LEN_TABLE (VEX_LEN_53_P_1) },
3396 { "(bad)", { XX } },
3397 { "(bad)", { XX } },
3402 { "vaddps", { XM, Vex, EXx } },
3403 { VEX_LEN_TABLE (VEX_LEN_58_P_1) },
3404 { "vaddpd", { XM, Vex, EXx } },
3405 { VEX_LEN_TABLE (VEX_LEN_58_P_3) },
3410 { "vmulps", { XM, Vex, EXx } },
3411 { VEX_LEN_TABLE (VEX_LEN_59_P_1) },
3412 { "vmulpd", { XM, Vex, EXx } },
3413 { VEX_LEN_TABLE (VEX_LEN_59_P_3) },
3418 { "vcvtps2pd", { XM, EXxmmq } },
3419 { VEX_LEN_TABLE (VEX_LEN_5A_P_1) },
3420 { "vcvtpd2ps%XY", { XMM, EXx } },
3421 { VEX_LEN_TABLE (VEX_LEN_5A_P_3) },
3426 { "vcvtdq2ps", { XM, EXx } },
3427 { "vcvttps2dq", { XM, EXx } },
3428 { "vcvtps2dq", { XM, EXx } },
3429 { "(bad)", { XX } },
3434 { "vsubps", { XM, Vex, EXx } },
3435 { VEX_LEN_TABLE (VEX_LEN_5C_P_1) },
3436 { "vsubpd", { XM, Vex, EXx } },
3437 { VEX_LEN_TABLE (VEX_LEN_5C_P_3) },
3442 { "vminps", { XM, Vex, EXx } },
3443 { VEX_LEN_TABLE (VEX_LEN_5D_P_1) },
3444 { "vminpd", { XM, Vex, EXx } },
3445 { VEX_LEN_TABLE (VEX_LEN_5D_P_3) },
3450 { "vdivps", { XM, Vex, EXx } },
3451 { VEX_LEN_TABLE (VEX_LEN_5E_P_1) },
3452 { "vdivpd", { XM, Vex, EXx } },
3453 { VEX_LEN_TABLE (VEX_LEN_5E_P_3) },
3458 { "vmaxps", { XM, Vex, EXx } },
3459 { VEX_LEN_TABLE (VEX_LEN_5F_P_1) },
3460 { "vmaxpd", { XM, Vex, EXx } },
3461 { VEX_LEN_TABLE (VEX_LEN_5F_P_3) },
3466 { "(bad)", { XX } },
3467 { "(bad)", { XX } },
3468 { VEX_LEN_TABLE (VEX_LEN_60_P_2) },
3469 { "(bad)", { XX } },
3474 { "(bad)", { XX } },
3475 { "(bad)", { XX } },
3476 { VEX_LEN_TABLE (VEX_LEN_61_P_2) },
3477 { "(bad)", { XX } },
3482 { "(bad)", { XX } },
3483 { "(bad)", { XX } },
3484 { VEX_LEN_TABLE (VEX_LEN_62_P_2) },
3485 { "(bad)", { XX } },
3490 { "(bad)", { XX } },
3491 { "(bad)", { XX } },
3492 { VEX_LEN_TABLE (VEX_LEN_63_P_2) },
3493 { "(bad)", { XX } },
3498 { "(bad)", { XX } },
3499 { "(bad)", { XX } },
3500 { VEX_LEN_TABLE (VEX_LEN_64_P_2) },
3501 { "(bad)", { XX } },
3506 { "(bad)", { XX } },
3507 { "(bad)", { XX } },
3508 { VEX_LEN_TABLE (VEX_LEN_65_P_2) },
3509 { "(bad)", { XX } },
3514 { "(bad)", { XX } },
3515 { "(bad)", { XX } },
3516 { VEX_LEN_TABLE (VEX_LEN_66_P_2) },
3517 { "(bad)", { XX } },
3522 { "(bad)", { XX } },
3523 { "(bad)", { XX } },
3524 { VEX_LEN_TABLE (VEX_LEN_67_P_2) },
3525 { "(bad)", { XX } },
3530 { "(bad)", { XX } },
3531 { "(bad)", { XX } },
3532 { VEX_LEN_TABLE (VEX_LEN_68_P_2) },
3533 { "(bad)", { XX } },
3538 { "(bad)", { XX } },
3539 { "(bad)", { XX } },
3540 { VEX_LEN_TABLE (VEX_LEN_69_P_2) },
3541 { "(bad)", { XX } },
3546 { "(bad)", { XX } },
3547 { "(bad)", { XX } },
3548 { VEX_LEN_TABLE (VEX_LEN_6A_P_2) },
3549 { "(bad)", { XX } },
3554 { "(bad)", { XX } },
3555 { "(bad)", { XX } },
3556 { VEX_LEN_TABLE (VEX_LEN_6B_P_2) },
3557 { "(bad)", { XX } },
3562 { "(bad)", { XX } },
3563 { "(bad)", { XX } },
3564 { VEX_LEN_TABLE (VEX_LEN_6C_P_2) },
3565 { "(bad)", { XX } },
3570 { "(bad)", { XX } },
3571 { "(bad)", { XX } },
3572 { VEX_LEN_TABLE (VEX_LEN_6D_P_2) },
3573 { "(bad)", { XX } },
3578 { "(bad)", { XX } },
3579 { "(bad)", { XX } },
3580 { VEX_LEN_TABLE (VEX_LEN_6E_P_2) },
3581 { "(bad)", { XX } },
3586 { "(bad)", { XX } },
3587 { "vmovdqu", { XM, EXx } },
3588 { "vmovdqa", { XM, EXx } },
3589 { "(bad)", { XX } },
3594 { "(bad)", { XX } },
3595 { VEX_LEN_TABLE (VEX_LEN_70_P_1) },
3596 { VEX_LEN_TABLE (VEX_LEN_70_P_2) },
3597 { VEX_LEN_TABLE (VEX_LEN_70_P_3) },
3600 /* PREFIX_VEX_71_REG_2 */
3602 { "(bad)", { XX } },
3603 { "(bad)", { XX } },
3604 { VEX_LEN_TABLE (VEX_LEN_71_R_2_P_2) },
3605 { "(bad)", { XX } },
3608 /* PREFIX_VEX_71_REG_4 */
3610 { "(bad)", { XX } },
3611 { "(bad)", { XX } },
3612 { VEX_LEN_TABLE (VEX_LEN_71_R_4_P_2) },
3613 { "(bad)", { XX } },
3616 /* PREFIX_VEX_71_REG_6 */
3618 { "(bad)", { XX } },
3619 { "(bad)", { XX } },
3620 { VEX_LEN_TABLE (VEX_LEN_71_R_6_P_2) },
3621 { "(bad)", { XX } },
3624 /* PREFIX_VEX_72_REG_2 */
3626 { "(bad)", { XX } },
3627 { "(bad)", { XX } },
3628 { VEX_LEN_TABLE (VEX_LEN_72_R_2_P_2) },
3629 { "(bad)", { XX } },
3632 /* PREFIX_VEX_72_REG_4 */
3634 { "(bad)", { XX } },
3635 { "(bad)", { XX } },
3636 { VEX_LEN_TABLE (VEX_LEN_72_R_4_P_2) },
3637 { "(bad)", { XX } },
3640 /* PREFIX_VEX_72_REG_6 */
3642 { "(bad)", { XX } },
3643 { "(bad)", { XX } },
3644 { VEX_LEN_TABLE (VEX_LEN_72_R_6_P_2) },
3645 { "(bad)", { XX } },
3648 /* PREFIX_VEX_73_REG_2 */
3650 { "(bad)", { XX } },
3651 { "(bad)", { XX } },
3652 { VEX_LEN_TABLE (VEX_LEN_73_R_2_P_2) },
3653 { "(bad)", { XX } },
3656 /* PREFIX_VEX_73_REG_3 */
3658 { "(bad)", { XX } },
3659 { "(bad)", { XX } },
3660 { VEX_LEN_TABLE (VEX_LEN_73_R_3_P_2) },
3661 { "(bad)", { XX } },
3664 /* PREFIX_VEX_73_REG_6 */
3666 { "(bad)", { XX } },
3667 { "(bad)", { XX } },
3668 { VEX_LEN_TABLE (VEX_LEN_73_R_6_P_2) },
3669 { "(bad)", { XX } },
3672 /* PREFIX_VEX_73_REG_7 */
3674 { "(bad)", { XX } },
3675 { "(bad)", { XX } },
3676 { VEX_LEN_TABLE (VEX_LEN_73_R_7_P_2) },
3677 { "(bad)", { XX } },
3682 { "(bad)", { XX } },
3683 { "(bad)", { XX } },
3684 { VEX_LEN_TABLE (VEX_LEN_74_P_2) },
3685 { "(bad)", { XX } },
3690 { "(bad)", { XX } },
3691 { "(bad)", { XX } },
3692 { VEX_LEN_TABLE (VEX_LEN_75_P_2) },
3693 { "(bad)", { XX } },
3698 { "(bad)", { XX } },
3699 { "(bad)", { XX } },
3700 { VEX_LEN_TABLE (VEX_LEN_76_P_2) },
3701 { "(bad)", { XX } },
3707 { "(bad)", { XX } },
3708 { "(bad)", { XX } },
3709 { "(bad)", { XX } },
3714 { "(bad)", { XX } },
3715 { "(bad)", { XX } },
3716 { "vhaddpd", { XM, Vex, EXx } },
3717 { "vhaddps", { XM, Vex, EXx } },
3722 { "(bad)", { XX } },
3723 { "(bad)", { XX } },
3724 { "vhsubpd", { XM, Vex, EXx } },
3725 { "vhsubps", { XM, Vex, EXx } },
3730 { "(bad)", { XX } },
3731 { VEX_LEN_TABLE (VEX_LEN_7E_P_1) },
3732 { VEX_LEN_TABLE (VEX_LEN_7E_P_2) },
3733 { "(bad)", { XX } },
3738 { "(bad)", { XX } },
3739 { "vmovdqu", { EXxS, XM } },
3740 { "vmovdqa", { EXxS, XM } },
3741 { "(bad)", { XX } },
3746 { "vcmpps", { XM, Vex, EXx, VCMP } },
3747 { VEX_LEN_TABLE (VEX_LEN_C2_P_1) },
3748 { "vcmppd", { XM, Vex, EXx, VCMP } },
3749 { VEX_LEN_TABLE (VEX_LEN_C2_P_3) },
3754 { "(bad)", { XX } },
3755 { "(bad)", { XX } },
3756 { VEX_LEN_TABLE (VEX_LEN_C4_P_2) },
3757 { "(bad)", { XX } },
3762 { "(bad)", { XX } },
3763 { "(bad)", { XX } },
3764 { VEX_LEN_TABLE (VEX_LEN_C5_P_2) },
3765 { "(bad)", { XX } },
3770 { "(bad)", { XX } },
3771 { "(bad)", { XX } },
3772 { "vaddsubpd", { XM, Vex, EXx } },
3773 { "vaddsubps", { XM, Vex, EXx } },
3778 { "(bad)", { XX } },
3779 { "(bad)", { XX } },
3780 { VEX_LEN_TABLE (VEX_LEN_D1_P_2) },
3781 { "(bad)", { XX } },
3786 { "(bad)", { XX } },
3787 { "(bad)", { XX } },
3788 { VEX_LEN_TABLE (VEX_LEN_D2_P_2) },
3789 { "(bad)", { XX } },
3794 { "(bad)", { XX } },
3795 { "(bad)", { XX } },
3796 { VEX_LEN_TABLE (VEX_LEN_D3_P_2) },
3797 { "(bad)", { XX } },
3802 { "(bad)", { XX } },
3803 { "(bad)", { XX } },
3804 { VEX_LEN_TABLE (VEX_LEN_D4_P_2) },
3805 { "(bad)", { XX } },
3810 { "(bad)", { XX } },
3811 { "(bad)", { XX } },
3812 { VEX_LEN_TABLE (VEX_LEN_D5_P_2) },
3813 { "(bad)", { XX } },
3818 { "(bad)", { XX } },
3819 { "(bad)", { XX } },
3820 { VEX_LEN_TABLE (VEX_LEN_D6_P_2) },
3821 { "(bad)", { XX } },
3826 { "(bad)", { XX } },
3827 { "(bad)", { XX } },
3828 { MOD_TABLE (MOD_VEX_D7_PREFIX_2) },
3829 { "(bad)", { XX } },
3834 { "(bad)", { XX } },
3835 { "(bad)", { XX } },
3836 { VEX_LEN_TABLE (VEX_LEN_D8_P_2) },
3837 { "(bad)", { XX } },
3842 { "(bad)", { XX } },
3843 { "(bad)", { XX } },
3844 { VEX_LEN_TABLE (VEX_LEN_D9_P_2) },
3845 { "(bad)", { XX } },
3850 { "(bad)", { XX } },
3851 { "(bad)", { XX } },
3852 { VEX_LEN_TABLE (VEX_LEN_DA_P_2) },
3853 { "(bad)", { XX } },
3858 { "(bad)", { XX } },
3859 { "(bad)", { XX } },
3860 { VEX_LEN_TABLE (VEX_LEN_DB_P_2) },
3861 { "(bad)", { XX } },
3866 { "(bad)", { XX } },
3867 { "(bad)", { XX } },
3868 { VEX_LEN_TABLE (VEX_LEN_DC_P_2) },
3869 { "(bad)", { XX } },
3874 { "(bad)", { XX } },
3875 { "(bad)", { XX } },
3876 { VEX_LEN_TABLE (VEX_LEN_DD_P_2) },
3877 { "(bad)", { XX } },
3882 { "(bad)", { XX } },
3883 { "(bad)", { XX } },
3884 { VEX_LEN_TABLE (VEX_LEN_DE_P_2) },
3885 { "(bad)", { XX } },
3890 { "(bad)", { XX } },
3891 { "(bad)", { XX } },
3892 { VEX_LEN_TABLE (VEX_LEN_DF_P_2) },
3893 { "(bad)", { XX } },
3898 { "(bad)", { XX } },
3899 { "(bad)", { XX } },
3900 { VEX_LEN_TABLE (VEX_LEN_E0_P_2) },
3901 { "(bad)", { XX } },
3906 { "(bad)", { XX } },
3907 { "(bad)", { XX } },
3908 { VEX_LEN_TABLE (VEX_LEN_E1_P_2) },
3909 { "(bad)", { XX } },
3914 { "(bad)", { XX } },
3915 { "(bad)", { XX } },
3916 { VEX_LEN_TABLE (VEX_LEN_E2_P_2) },
3917 { "(bad)", { XX } },
3922 { "(bad)", { XX } },
3923 { "(bad)", { XX } },
3924 { VEX_LEN_TABLE (VEX_LEN_E3_P_2) },
3925 { "(bad)", { XX } },
3930 { "(bad)", { XX } },
3931 { "(bad)", { XX } },
3932 { VEX_LEN_TABLE (VEX_LEN_E4_P_2) },
3933 { "(bad)", { XX } },
3938 { "(bad)", { XX } },
3939 { "(bad)", { XX } },
3940 { VEX_LEN_TABLE (VEX_LEN_E5_P_2) },
3941 { "(bad)", { XX } },
3946 { "(bad)", { XX } },
3947 { "vcvtdq2pd", { XM, EXxmmq } },
3948 { "vcvttpd2dq%XY", { XMM, EXx } },
3949 { "vcvtpd2dq%XY", { XMM, EXx } },
3954 { "(bad)", { XX } },
3955 { "(bad)", { XX } },
3956 { MOD_TABLE (MOD_VEX_E7_PREFIX_2) },
3957 { "(bad)", { XX } },
3962 { "(bad)", { XX } },
3963 { "(bad)", { XX } },
3964 { VEX_LEN_TABLE (VEX_LEN_E8_P_2) },
3965 { "(bad)", { XX } },
3970 { "(bad)", { XX } },
3971 { "(bad)", { XX } },
3972 { VEX_LEN_TABLE (VEX_LEN_E9_P_2) },
3973 { "(bad)", { XX } },
3978 { "(bad)", { XX } },
3979 { "(bad)", { XX } },
3980 { VEX_LEN_TABLE (VEX_LEN_EA_P_2) },
3981 { "(bad)", { XX } },
3986 { "(bad)", { XX } },
3987 { "(bad)", { XX } },
3988 { VEX_LEN_TABLE (VEX_LEN_EB_P_2) },
3989 { "(bad)", { XX } },
3994 { "(bad)", { XX } },
3995 { "(bad)", { XX } },
3996 { VEX_LEN_TABLE (VEX_LEN_EC_P_2) },
3997 { "(bad)", { XX } },
4002 { "(bad)", { XX } },
4003 { "(bad)", { XX } },
4004 { VEX_LEN_TABLE (VEX_LEN_ED_P_2) },
4005 { "(bad)", { XX } },
4010 { "(bad)", { XX } },
4011 { "(bad)", { XX } },
4012 { VEX_LEN_TABLE (VEX_LEN_EE_P_2) },
4013 { "(bad)", { XX } },
4018 { "(bad)", { XX } },
4019 { "(bad)", { XX } },
4020 { VEX_LEN_TABLE (VEX_LEN_EF_P_2) },
4021 { "(bad)", { XX } },
4026 { "(bad)", { XX } },
4027 { "(bad)", { XX } },
4028 { "(bad)", { XX } },
4029 { MOD_TABLE (MOD_VEX_F0_PREFIX_3) },
4034 { "(bad)", { XX } },
4035 { "(bad)", { XX } },
4036 { VEX_LEN_TABLE (VEX_LEN_F1_P_2) },
4037 { "(bad)", { XX } },
4042 { "(bad)", { XX } },
4043 { "(bad)", { XX } },
4044 { VEX_LEN_TABLE (VEX_LEN_F2_P_2) },
4045 { "(bad)", { XX } },
4050 { "(bad)", { XX } },
4051 { "(bad)", { XX } },
4052 { VEX_LEN_TABLE (VEX_LEN_F3_P_2) },
4053 { "(bad)", { XX } },
4058 { "(bad)", { XX } },
4059 { "(bad)", { XX } },
4060 { VEX_LEN_TABLE (VEX_LEN_F4_P_2) },
4061 { "(bad)", { XX } },
4066 { "(bad)", { XX } },
4067 { "(bad)", { XX } },
4068 { VEX_LEN_TABLE (VEX_LEN_F5_P_2) },
4069 { "(bad)", { XX } },
4074 { "(bad)", { XX } },
4075 { "(bad)", { XX } },
4076 { VEX_LEN_TABLE (VEX_LEN_F6_P_2) },
4077 { "(bad)", { XX } },
4082 { "(bad)", { XX } },
4083 { "(bad)", { XX } },
4084 { VEX_LEN_TABLE (VEX_LEN_F7_P_2) },
4085 { "(bad)", { XX } },
4090 { "(bad)", { XX } },
4091 { "(bad)", { XX } },
4092 { VEX_LEN_TABLE (VEX_LEN_F8_P_2) },
4093 { "(bad)", { XX } },
4098 { "(bad)", { XX } },
4099 { "(bad)", { XX } },
4100 { VEX_LEN_TABLE (VEX_LEN_F9_P_2) },
4101 { "(bad)", { XX } },
4106 { "(bad)", { XX } },
4107 { "(bad)", { XX } },
4108 { VEX_LEN_TABLE (VEX_LEN_FA_P_2) },
4109 { "(bad)", { XX } },
4114 { "(bad)", { XX } },
4115 { "(bad)", { XX } },
4116 { VEX_LEN_TABLE (VEX_LEN_FB_P_2) },
4117 { "(bad)", { XX } },
4122 { "(bad)", { XX } },
4123 { "(bad)", { XX } },
4124 { VEX_LEN_TABLE (VEX_LEN_FC_P_2) },
4125 { "(bad)", { XX } },
4130 { "(bad)", { XX } },
4131 { "(bad)", { XX } },
4132 { VEX_LEN_TABLE (VEX_LEN_FD_P_2) },
4133 { "(bad)", { XX } },
4138 { "(bad)", { XX } },
4139 { "(bad)", { XX } },
4140 { VEX_LEN_TABLE (VEX_LEN_FE_P_2) },
4141 { "(bad)", { XX } },
4144 /* PREFIX_VEX_3800 */
4146 { "(bad)", { XX } },
4147 { "(bad)", { XX } },
4148 { VEX_LEN_TABLE (VEX_LEN_3800_P_2) },
4149 { "(bad)", { XX } },
4152 /* PREFIX_VEX_3801 */
4154 { "(bad)", { XX } },
4155 { "(bad)", { XX } },
4156 { VEX_LEN_TABLE (VEX_LEN_3801_P_2) },
4157 { "(bad)", { XX } },
4160 /* PREFIX_VEX_3802 */
4162 { "(bad)", { XX } },
4163 { "(bad)", { XX } },
4164 { VEX_LEN_TABLE (VEX_LEN_3802_P_2) },
4165 { "(bad)", { XX } },
4168 /* PREFIX_VEX_3803 */
4170 { "(bad)", { XX } },
4171 { "(bad)", { XX } },
4172 { VEX_LEN_TABLE (VEX_LEN_3803_P_2) },
4173 { "(bad)", { XX } },
4176 /* PREFIX_VEX_3804 */
4178 { "(bad)", { XX } },
4179 { "(bad)", { XX } },
4180 { VEX_LEN_TABLE (VEX_LEN_3804_P_2) },
4181 { "(bad)", { XX } },
4184 /* PREFIX_VEX_3805 */
4186 { "(bad)", { XX } },
4187 { "(bad)", { XX } },
4188 { VEX_LEN_TABLE (VEX_LEN_3805_P_2) },
4189 { "(bad)", { XX } },
4192 /* PREFIX_VEX_3806 */
4194 { "(bad)", { XX } },
4195 { "(bad)", { XX } },
4196 { VEX_LEN_TABLE (VEX_LEN_3806_P_2) },
4197 { "(bad)", { XX } },
4200 /* PREFIX_VEX_3807 */
4202 { "(bad)", { XX } },
4203 { "(bad)", { XX } },
4204 { VEX_LEN_TABLE (VEX_LEN_3807_P_2) },
4205 { "(bad)", { XX } },
4208 /* PREFIX_VEX_3808 */
4210 { "(bad)", { XX } },
4211 { "(bad)", { XX } },
4212 { VEX_LEN_TABLE (VEX_LEN_3808_P_2) },
4213 { "(bad)", { XX } },
4216 /* PREFIX_VEX_3809 */
4218 { "(bad)", { XX } },
4219 { "(bad)", { XX } },
4220 { VEX_LEN_TABLE (VEX_LEN_3809_P_2) },
4221 { "(bad)", { XX } },
4224 /* PREFIX_VEX_380A */
4226 { "(bad)", { XX } },
4227 { "(bad)", { XX } },
4228 { VEX_LEN_TABLE (VEX_LEN_380A_P_2) },
4229 { "(bad)", { XX } },
4232 /* PREFIX_VEX_380B */
4234 { "(bad)", { XX } },
4235 { "(bad)", { XX } },
4236 { VEX_LEN_TABLE (VEX_LEN_380B_P_2) },
4237 { "(bad)", { XX } },
4240 /* PREFIX_VEX_380C */
4242 { "(bad)", { XX } },
4243 { "(bad)", { XX } },
4244 { "vpermilps", { XM, Vex, EXx } },
4245 { "(bad)", { XX } },
4248 /* PREFIX_VEX_380D */
4250 { "(bad)", { XX } },
4251 { "(bad)", { XX } },
4252 { "vpermilpd", { XM, Vex, EXx } },
4253 { "(bad)", { XX } },
4256 /* PREFIX_VEX_380E */
4258 { "(bad)", { XX } },
4259 { "(bad)", { XX } },
4260 { "vtestps", { XM, EXx } },
4261 { "(bad)", { XX } },
4264 /* PREFIX_VEX_380F */
4266 { "(bad)", { XX } },
4267 { "(bad)", { XX } },
4268 { "vtestpd", { XM, EXx } },
4269 { "(bad)", { XX } },
4272 /* PREFIX_VEX_3817 */
4274 { "(bad)", { XX } },
4275 { "(bad)", { XX } },
4276 { "vptest", { XM, EXx } },
4277 { "(bad)", { XX } },
4280 /* PREFIX_VEX_3818 */
4282 { "(bad)", { XX } },
4283 { "(bad)", { XX } },
4284 { MOD_TABLE (MOD_VEX_3818_PREFIX_2) },
4285 { "(bad)", { XX } },
4288 /* PREFIX_VEX_3819 */
4290 { "(bad)", { XX } },
4291 { "(bad)", { XX } },
4292 { MOD_TABLE (MOD_VEX_3819_PREFIX_2) },
4293 { "(bad)", { XX } },
4296 /* PREFIX_VEX_381A */
4298 { "(bad)", { XX } },
4299 { "(bad)", { XX } },
4300 { MOD_TABLE (MOD_VEX_381A_PREFIX_2) },
4301 { "(bad)", { XX } },
4304 /* PREFIX_VEX_381C */
4306 { "(bad)", { XX } },
4307 { "(bad)", { XX } },
4308 { VEX_LEN_TABLE (VEX_LEN_381C_P_2) },
4309 { "(bad)", { XX } },
4312 /* PREFIX_VEX_381D */
4314 { "(bad)", { XX } },
4315 { "(bad)", { XX } },
4316 { VEX_LEN_TABLE (VEX_LEN_381D_P_2) },
4317 { "(bad)", { XX } },
4320 /* PREFIX_VEX_381E */
4322 { "(bad)", { XX } },
4323 { "(bad)", { XX } },
4324 { VEX_LEN_TABLE (VEX_LEN_381E_P_2) },
4325 { "(bad)", { XX } },
4328 /* PREFIX_VEX_3820 */
4330 { "(bad)", { XX } },
4331 { "(bad)", { XX } },
4332 { VEX_LEN_TABLE (VEX_LEN_3820_P_2) },
4333 { "(bad)", { XX } },
4336 /* PREFIX_VEX_3821 */
4338 { "(bad)", { XX } },
4339 { "(bad)", { XX } },
4340 { VEX_LEN_TABLE (VEX_LEN_3821_P_2) },
4341 { "(bad)", { XX } },
4344 /* PREFIX_VEX_3822 */
4346 { "(bad)", { XX } },
4347 { "(bad)", { XX } },
4348 { VEX_LEN_TABLE (VEX_LEN_3822_P_2) },
4349 { "(bad)", { XX } },
4352 /* PREFIX_VEX_3823 */
4354 { "(bad)", { XX } },
4355 { "(bad)", { XX } },
4356 { VEX_LEN_TABLE (VEX_LEN_3823_P_2) },
4357 { "(bad)", { XX } },
4360 /* PREFIX_VEX_3824 */
4362 { "(bad)", { XX } },
4363 { "(bad)", { XX } },
4364 { VEX_LEN_TABLE (VEX_LEN_3824_P_2) },
4365 { "(bad)", { XX } },
4368 /* PREFIX_VEX_3825 */
4370 { "(bad)", { XX } },
4371 { "(bad)", { XX } },
4372 { VEX_LEN_TABLE (VEX_LEN_3825_P_2) },
4373 { "(bad)", { XX } },
4376 /* PREFIX_VEX_3828 */
4378 { "(bad)", { XX } },
4379 { "(bad)", { XX } },
4380 { VEX_LEN_TABLE (VEX_LEN_3828_P_2) },
4381 { "(bad)", { XX } },
4384 /* PREFIX_VEX_3829 */
4386 { "(bad)", { XX } },
4387 { "(bad)", { XX } },
4388 { VEX_LEN_TABLE (VEX_LEN_3829_P_2) },
4389 { "(bad)", { XX } },
4392 /* PREFIX_VEX_382A */
4394 { "(bad)", { XX } },
4395 { "(bad)", { XX } },
4396 { MOD_TABLE (MOD_VEX_382A_PREFIX_2) },
4397 { "(bad)", { XX } },
4400 /* PREFIX_VEX_382B */
4402 { "(bad)", { XX } },
4403 { "(bad)", { XX } },
4404 { VEX_LEN_TABLE (VEX_LEN_382B_P_2) },
4405 { "(bad)", { XX } },
4408 /* PREFIX_VEX_382C */
4410 { "(bad)", { XX } },
4411 { "(bad)", { XX } },
4412 { MOD_TABLE (MOD_VEX_382C_PREFIX_2) },
4413 { "(bad)", { XX } },
4416 /* PREFIX_VEX_382D */
4418 { "(bad)", { XX } },
4419 { "(bad)", { XX } },
4420 { MOD_TABLE (MOD_VEX_382D_PREFIX_2) },
4421 { "(bad)", { XX } },
4424 /* PREFIX_VEX_382E */
4426 { "(bad)", { XX } },
4427 { "(bad)", { XX } },
4428 { MOD_TABLE (MOD_VEX_382E_PREFIX_2) },
4429 { "(bad)", { XX } },
4432 /* PREFIX_VEX_382F */
4434 { "(bad)", { XX } },
4435 { "(bad)", { XX } },
4436 { MOD_TABLE (MOD_VEX_382F_PREFIX_2) },
4437 { "(bad)", { XX } },
4440 /* PREFIX_VEX_3830 */
4442 { "(bad)", { XX } },
4443 { "(bad)", { XX } },
4444 { VEX_LEN_TABLE (VEX_LEN_3830_P_2) },
4445 { "(bad)", { XX } },
4448 /* PREFIX_VEX_3831 */
4450 { "(bad)", { XX } },
4451 { "(bad)", { XX } },
4452 { VEX_LEN_TABLE (VEX_LEN_3831_P_2) },
4453 { "(bad)", { XX } },
4456 /* PREFIX_VEX_3832 */
4458 { "(bad)", { XX } },
4459 { "(bad)", { XX } },
4460 { VEX_LEN_TABLE (VEX_LEN_3832_P_2) },
4461 { "(bad)", { XX } },
4464 /* PREFIX_VEX_3833 */
4466 { "(bad)", { XX } },
4467 { "(bad)", { XX } },
4468 { VEX_LEN_TABLE (VEX_LEN_3833_P_2) },
4469 { "(bad)", { XX } },
4472 /* PREFIX_VEX_3834 */
4474 { "(bad)", { XX } },
4475 { "(bad)", { XX } },
4476 { VEX_LEN_TABLE (VEX_LEN_3834_P_2) },
4477 { "(bad)", { XX } },
4480 /* PREFIX_VEX_3835 */
4482 { "(bad)", { XX } },
4483 { "(bad)", { XX } },
4484 { VEX_LEN_TABLE (VEX_LEN_3835_P_2) },
4485 { "(bad)", { XX } },
4488 /* PREFIX_VEX_3837 */
4490 { "(bad)", { XX } },
4491 { "(bad)", { XX } },
4492 { VEX_LEN_TABLE (VEX_LEN_3837_P_2) },
4493 { "(bad)", { XX } },
4496 /* PREFIX_VEX_3838 */
4498 { "(bad)", { XX } },
4499 { "(bad)", { XX } },
4500 { VEX_LEN_TABLE (VEX_LEN_3838_P_2) },
4501 { "(bad)", { XX } },
4504 /* PREFIX_VEX_3839 */
4506 { "(bad)", { XX } },
4507 { "(bad)", { XX } },
4508 { VEX_LEN_TABLE (VEX_LEN_3839_P_2) },
4509 { "(bad)", { XX } },
4512 /* PREFIX_VEX_383A */
4514 { "(bad)", { XX } },
4515 { "(bad)", { XX } },
4516 { VEX_LEN_TABLE (VEX_LEN_383A_P_2) },
4517 { "(bad)", { XX } },
4520 /* PREFIX_VEX_383B */
4522 { "(bad)", { XX } },
4523 { "(bad)", { XX } },
4524 { VEX_LEN_TABLE (VEX_LEN_383B_P_2) },
4525 { "(bad)", { XX } },
4528 /* PREFIX_VEX_383C */
4530 { "(bad)", { XX } },
4531 { "(bad)", { XX } },
4532 { VEX_LEN_TABLE (VEX_LEN_383C_P_2) },
4533 { "(bad)", { XX } },
4536 /* PREFIX_VEX_383D */
4538 { "(bad)", { XX } },
4539 { "(bad)", { XX } },
4540 { VEX_LEN_TABLE (VEX_LEN_383D_P_2) },
4541 { "(bad)", { XX } },
4544 /* PREFIX_VEX_383E */
4546 { "(bad)", { XX } },
4547 { "(bad)", { XX } },
4548 { VEX_LEN_TABLE (VEX_LEN_383E_P_2) },
4549 { "(bad)", { XX } },
4552 /* PREFIX_VEX_383F */
4554 { "(bad)", { XX } },
4555 { "(bad)", { XX } },
4556 { VEX_LEN_TABLE (VEX_LEN_383F_P_2) },
4557 { "(bad)", { XX } },
4560 /* PREFIX_VEX_3840 */
4562 { "(bad)", { XX } },
4563 { "(bad)", { XX } },
4564 { VEX_LEN_TABLE (VEX_LEN_3840_P_2) },
4565 { "(bad)", { XX } },
4568 /* PREFIX_VEX_3841 */
4570 { "(bad)", { XX } },
4571 { "(bad)", { XX } },
4572 { VEX_LEN_TABLE (VEX_LEN_3841_P_2) },
4573 { "(bad)", { XX } },
4576 /* PREFIX_VEX_38DB */
4578 { "(bad)", { XX } },
4579 { "(bad)", { XX } },
4580 { VEX_LEN_TABLE (VEX_LEN_38DB_P_2) },
4581 { "(bad)", { XX } },
4584 /* PREFIX_VEX_38DC */
4586 { "(bad)", { XX } },
4587 { "(bad)", { XX } },
4588 { VEX_LEN_TABLE (VEX_LEN_38DC_P_2) },
4589 { "(bad)", { XX } },
4592 /* PREFIX_VEX_38DD */
4594 { "(bad)", { XX } },
4595 { "(bad)", { XX } },
4596 { VEX_LEN_TABLE (VEX_LEN_38DD_P_2) },
4597 { "(bad)", { XX } },
4600 /* PREFIX_VEX_38DE */
4602 { "(bad)", { XX } },
4603 { "(bad)", { XX } },
4604 { VEX_LEN_TABLE (VEX_LEN_38DE_P_2) },
4605 { "(bad)", { XX } },
4608 /* PREFIX_VEX_38DF */
4610 { "(bad)", { XX } },
4611 { "(bad)", { XX } },
4612 { VEX_LEN_TABLE (VEX_LEN_38DF_P_2) },
4613 { "(bad)", { XX } },
4616 /* PREFIX_VEX_3A04 */
4618 { "(bad)", { XX } },
4619 { "(bad)", { XX } },
4620 { "vpermilps", { XM, EXx, Ib } },
4621 { "(bad)", { XX } },
4624 /* PREFIX_VEX_3A05 */
4626 { "(bad)", { XX } },
4627 { "(bad)", { XX } },
4628 { "vpermilpd", { XM, EXx, Ib } },
4629 { "(bad)", { XX } },
4632 /* PREFIX_VEX_3A06 */
4634 { "(bad)", { XX } },
4635 { "(bad)", { XX } },
4636 { VEX_LEN_TABLE (VEX_LEN_3A06_P_2) },
4637 { "(bad)", { XX } },
4640 /* PREFIX_VEX_3A08 */
4642 { "(bad)", { XX } },
4643 { "(bad)", { XX } },
4644 { "vroundps", { XM, EXx, Ib } },
4645 { "(bad)", { XX } },
4648 /* PREFIX_VEX_3A09 */
4650 { "(bad)", { XX } },
4651 { "(bad)", { XX } },
4652 { "vroundpd", { XM, EXx, Ib } },
4653 { "(bad)", { XX } },
4656 /* PREFIX_VEX_3A0A */
4658 { "(bad)", { XX } },
4659 { "(bad)", { XX } },
4660 { VEX_LEN_TABLE (VEX_LEN_3A0A_P_2) },
4661 { "(bad)", { XX } },
4664 /* PREFIX_VEX_3A0B */
4666 { "(bad)", { XX } },
4667 { "(bad)", { XX } },
4668 { VEX_LEN_TABLE (VEX_LEN_3A0B_P_2) },
4669 { "(bad)", { XX } },
4672 /* PREFIX_VEX_3A0C */
4674 { "(bad)", { XX } },
4675 { "(bad)", { XX } },
4676 { "vblendps", { XM, Vex, EXx, Ib } },
4677 { "(bad)", { XX } },
4680 /* PREFIX_VEX_3A0D */
4682 { "(bad)", { XX } },
4683 { "(bad)", { XX } },
4684 { "vblendpd", { XM, Vex, EXx, Ib } },
4685 { "(bad)", { XX } },
4688 /* PREFIX_VEX_3A0E */
4690 { "(bad)", { XX } },
4691 { "(bad)", { XX } },
4692 { VEX_LEN_TABLE (VEX_LEN_3A0E_P_2) },
4693 { "(bad)", { XX } },
4696 /* PREFIX_VEX_3A0F */
4698 { "(bad)", { XX } },
4699 { "(bad)", { XX } },
4700 { VEX_LEN_TABLE (VEX_LEN_3A0F_P_2) },
4701 { "(bad)", { XX } },
4704 /* PREFIX_VEX_3A14 */
4706 { "(bad)", { XX } },
4707 { "(bad)", { XX } },
4708 { VEX_LEN_TABLE (VEX_LEN_3A14_P_2) },
4709 { "(bad)", { XX } },
4712 /* PREFIX_VEX_3A15 */
4714 { "(bad)", { XX } },
4715 { "(bad)", { XX } },
4716 { VEX_LEN_TABLE (VEX_LEN_3A15_P_2) },
4717 { "(bad)", { XX } },
4720 /* PREFIX_VEX_3A16 */
4722 { "(bad)", { XX } },
4723 { "(bad)", { XX } },
4724 { VEX_LEN_TABLE (VEX_LEN_3A16_P_2) },
4725 { "(bad)", { XX } },
4728 /* PREFIX_VEX_3A17 */
4730 { "(bad)", { XX } },
4731 { "(bad)", { XX } },
4732 { VEX_LEN_TABLE (VEX_LEN_3A17_P_2) },
4733 { "(bad)", { XX } },
4736 /* PREFIX_VEX_3A18 */
4738 { "(bad)", { XX } },
4739 { "(bad)", { XX } },
4740 { VEX_LEN_TABLE (VEX_LEN_3A18_P_2) },
4741 { "(bad)", { XX } },
4744 /* PREFIX_VEX_3A19 */
4746 { "(bad)", { XX } },
4747 { "(bad)", { XX } },
4748 { VEX_LEN_TABLE (VEX_LEN_3A19_P_2) },
4749 { "(bad)", { XX } },
4752 /* PREFIX_VEX_3A20 */
4754 { "(bad)", { XX } },
4755 { "(bad)", { XX } },
4756 { VEX_LEN_TABLE (VEX_LEN_3A20_P_2) },
4757 { "(bad)", { XX } },
4760 /* PREFIX_VEX_3A21 */
4762 { "(bad)", { XX } },
4763 { "(bad)", { XX } },
4764 { VEX_LEN_TABLE (VEX_LEN_3A21_P_2) },
4765 { "(bad)", { XX } },
4768 /* PREFIX_VEX_3A22 */
4770 { "(bad)", { XX } },
4771 { "(bad)", { XX } },
4772 { VEX_LEN_TABLE (VEX_LEN_3A22_P_2) },
4773 { "(bad)", { XX } },
4776 /* PREFIX_VEX_3A40 */
4778 { "(bad)", { XX } },
4779 { "(bad)", { XX } },
4780 { "vdpps", { XM, Vex, EXx, Ib } },
4781 { "(bad)", { XX } },
4784 /* PREFIX_VEX_3A41 */
4786 { "(bad)", { XX } },
4787 { "(bad)", { XX } },
4788 { VEX_LEN_TABLE (VEX_LEN_3A41_P_2) },
4789 { "(bad)", { XX } },
4792 /* PREFIX_VEX_3A42 */
4794 { "(bad)", { XX } },
4795 { "(bad)", { XX } },
4796 { VEX_LEN_TABLE (VEX_LEN_3A42_P_2) },
4797 { "(bad)", { XX } },
4800 /* PREFIX_VEX_3A48 */
4802 { "(bad)", { XX } },
4803 { "(bad)", { XX } },
4804 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, VPERMIL2 } },
4805 { "(bad)", { XX } },
4808 /* PREFIX_VEX_3A49 */
4810 { "(bad)", { XX } },
4811 { "(bad)", { XX } },
4812 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, VPERMIL2 } },
4813 { "(bad)", { XX } },
4816 /* PREFIX_VEX_3A4A */
4818 { "(bad)", { XX } },
4819 { "(bad)", { XX } },
4820 { "vblendvps", { XM, Vex, EXx, XMVexI4 } },
4821 { "(bad)", { XX } },
4824 /* PREFIX_VEX_3A4B */
4826 { "(bad)", { XX } },
4827 { "(bad)", { XX } },
4828 { "vblendvpd", { XM, Vex, EXx, XMVexI4 } },
4829 { "(bad)", { XX } },
4832 /* PREFIX_VEX_3A4C */
4834 { "(bad)", { XX } },
4835 { "(bad)", { XX } },
4836 { VEX_LEN_TABLE (VEX_LEN_3A4C_P_2) },
4837 { "(bad)", { XX } },
4840 /* PREFIX_VEX_3A5C */
4842 { "(bad)", { XX } },
4843 { "(bad)", { XX } },
4844 { "vfmaddsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4845 { "(bad)", { XX } },
4848 /* PREFIX_VEX_3A5D */
4850 { "(bad)", { XX } },
4851 { "(bad)", { XX } },
4852 { "vfmaddsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4853 { "(bad)", { XX } },
4856 /* PREFIX_VEX_3A5E */
4858 { "(bad)", { XX } },
4859 { "(bad)", { XX } },
4860 { "vfmsubaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4861 { "(bad)", { XX } },
4864 /* PREFIX_VEX_3A5F */
4866 { "(bad)", { XX } },
4867 { "(bad)", { XX } },
4868 { "vfmsubaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4869 { "(bad)", { XX } },
4872 /* PREFIX_VEX_3A60 */
4874 { "(bad)", { XX } },
4875 { "(bad)", { XX } },
4876 { VEX_LEN_TABLE (VEX_LEN_3A60_P_2) },
4877 { "(bad)", { XX } },
4880 /* PREFIX_VEX_3A61 */
4882 { "(bad)", { XX } },
4883 { "(bad)", { XX } },
4884 { VEX_LEN_TABLE (VEX_LEN_3A61_P_2) },
4885 { "(bad)", { XX } },
4888 /* PREFIX_VEX_3A62 */
4890 { "(bad)", { XX } },
4891 { "(bad)", { XX } },
4892 { VEX_LEN_TABLE (VEX_LEN_3A62_P_2) },
4893 { "(bad)", { XX } },
4896 /* PREFIX_VEX_3A63 */
4898 { "(bad)", { XX } },
4899 { "(bad)", { XX } },
4900 { VEX_LEN_TABLE (VEX_LEN_3A63_P_2) },
4901 { "(bad)", { XX } },
4904 /* PREFIX_VEX_3A68 */
4906 { "(bad)", { XX } },
4907 { "(bad)", { XX } },
4908 { "vfmaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4909 { "(bad)", { XX } },
4912 /* PREFIX_VEX_3A69 */
4914 { "(bad)", { XX } },
4915 { "(bad)", { XX } },
4916 { "vfmaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4917 { "(bad)", { XX } },
4920 /* PREFIX_VEX_3A6A */
4922 { "(bad)", { XX } },
4923 { "(bad)", { XX } },
4924 { VEX_LEN_TABLE (VEX_LEN_3A6A_P_2) },
4925 { "(bad)", { XX } },
4928 /* PREFIX_VEX_3A6B */
4930 { "(bad)", { XX } },
4931 { "(bad)", { XX } },
4932 { VEX_LEN_TABLE (VEX_LEN_3A6B_P_2) },
4933 { "(bad)", { XX } },
4936 /* PREFIX_VEX_3A6C */
4938 { "(bad)", { XX } },
4939 { "(bad)", { XX } },
4940 { "vfmsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4941 { "(bad)", { XX } },
4944 /* PREFIX_VEX_3A6D */
4946 { "(bad)", { XX } },
4947 { "(bad)", { XX } },
4948 { "vfmsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4949 { "(bad)", { XX } },
4952 /* PREFIX_VEX_3A6E */
4954 { "(bad)", { XX } },
4955 { "(bad)", { XX } },
4956 { VEX_LEN_TABLE (VEX_LEN_3A6E_P_2) },
4957 { "(bad)", { XX } },
4960 /* PREFIX_VEX_3A6F */
4962 { "(bad)", { XX } },
4963 { "(bad)", { XX } },
4964 { VEX_LEN_TABLE (VEX_LEN_3A6F_P_2) },
4965 { "(bad)", { XX } },
4968 /* PREFIX_VEX_3A78 */
4970 { "(bad)", { XX } },
4971 { "(bad)", { XX } },
4972 { "vfnmaddps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4973 { "(bad)", { XX } },
4976 /* PREFIX_VEX_3A79 */
4978 { "(bad)", { XX } },
4979 { "(bad)", { XX } },
4980 { "vfnmaddpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
4981 { "(bad)", { XX } },
4984 /* PREFIX_VEX_3A7A */
4986 { "(bad)", { XX } },
4987 { "(bad)", { XX } },
4988 { VEX_LEN_TABLE (VEX_LEN_3A7A_P_2) },
4989 { "(bad)", { XX } },
4992 /* PREFIX_VEX_3A7B */
4994 { "(bad)", { XX } },
4995 { "(bad)", { XX } },
4996 { VEX_LEN_TABLE (VEX_LEN_3A7B_P_2) },
4997 { "(bad)", { XX } },
5000 /* PREFIX_VEX_3A7C */
5002 { "(bad)", { XX } },
5003 { "(bad)", { XX } },
5004 { "vfnmsubps", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
5005 { "(bad)", { XX } },
5008 /* PREFIX_VEX_3A7D */
5010 { "(bad)", { XX } },
5011 { "(bad)", { XX } },
5012 { "vfnmsubpd", { XMVexW, VexFMA, EXVexW, EXVexW, VexI4 } },
5013 { "(bad)", { XX } },
5016 /* PREFIX_VEX_3A7E */
5018 { "(bad)", { XX } },
5019 { "(bad)", { XX } },
5020 { VEX_LEN_TABLE (VEX_LEN_3A7E_P_2) },
5021 { "(bad)", { XX } },
5024 /* PREFIX_VEX_3A7F */
5026 { "(bad)", { XX } },
5027 { "(bad)", { XX } },
5028 { VEX_LEN_TABLE (VEX_LEN_3A7F_P_2) },
5029 { "(bad)", { XX } },
5032 /* PREFIX_VEX_3ADF */
5034 { "(bad)", { XX } },
5035 { "(bad)", { XX } },
5036 { VEX_LEN_TABLE (VEX_LEN_3ADF_P_2) },
5037 { "(bad)", { XX } },
5041 static const struct dis386 x86_64_table[][2] = {
5044 { "push{T|}", { es } },
5045 { "(bad)", { XX } },
5050 { "pop{T|}", { es } },
5051 { "(bad)", { XX } },
5056 { "push{T|}", { cs } },
5057 { "(bad)", { XX } },
5062 { "push{T|}", { ss } },
5063 { "(bad)", { XX } },
5068 { "pop{T|}", { ss } },
5069 { "(bad)", { XX } },
5074 { "push{T|}", { ds } },
5075 { "(bad)", { XX } },
5080 { "pop{T|}", { ds } },
5081 { "(bad)", { XX } },
5087 { "(bad)", { XX } },
5093 { "(bad)", { XX } },
5099 { "(bad)", { XX } },
5105 { "(bad)", { XX } },
5110 { "pusha{P|}", { XX } },
5111 { "(bad)", { XX } },
5116 { "popa{P|}", { XX } },
5117 { "(bad)", { XX } },
5122 { MOD_TABLE (MOD_62_32BIT) },
5123 { "(bad)", { XX } },
5128 { "arpl", { Ew, Gw } },
5129 { "movs{lq|xd}", { Gv, Ed } },
5134 { "ins{R|}", { Yzr, indirDX } },
5135 { "ins{G|}", { Yzr, indirDX } },
5140 { "outs{R|}", { indirDXr, Xz } },
5141 { "outs{G|}", { indirDXr, Xz } },
5146 { "Jcall{T|}", { Ap } },
5147 { "(bad)", { XX } },
5152 { MOD_TABLE (MOD_C4_32BIT) },
5153 { VEX_C4_TABLE (VEX_0F) },
5158 { MOD_TABLE (MOD_C5_32BIT) },
5159 { VEX_C5_TABLE (VEX_0F) },
5165 { "(bad)", { XX } },
5171 { "(bad)", { XX } },
5177 { "(bad)", { XX } },
5182 { "Jjmp{T|}", { Ap } },
5183 { "(bad)", { XX } },
5186 /* X86_64_0F01_REG_0 */
5188 { "sgdt{Q|IQ}", { M } },
5192 /* X86_64_0F01_REG_1 */
5194 { "sidt{Q|IQ}", { M } },
5198 /* X86_64_0F01_REG_2 */
5200 { "lgdt{Q|Q}", { M } },
5204 /* X86_64_0F01_REG_3 */
5206 { "lidt{Q|Q}", { M } },
5211 static const struct dis386 three_byte_table[][256] = {
5212 /* THREE_BYTE_0F24 */
5215 { "fmaddps", { { OP_DREX4, q_mode } } },
5216 { "fmaddpd", { { OP_DREX4, q_mode } } },
5217 { "fmaddss", { { OP_DREX4, w_mode } } },
5218 { "fmaddsd", { { OP_DREX4, d_mode } } },
5219 { "fmaddps", { { OP_DREX4, DREX_OC1 + q_mode } } },
5220 { "fmaddpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
5221 { "fmaddss", { { OP_DREX4, DREX_OC1 + w_mode } } },
5222 { "fmaddsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
5224 { "fmsubps", { { OP_DREX4, q_mode } } },
5225 { "fmsubpd", { { OP_DREX4, q_mode } } },
5226 { "fmsubss", { { OP_DREX4, w_mode } } },
5227 { "fmsubsd", { { OP_DREX4, d_mode } } },
5228 { "fmsubps", { { OP_DREX4, DREX_OC1 + q_mode } } },
5229 { "fmsubpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
5230 { "fmsubss", { { OP_DREX4, DREX_OC1 + w_mode } } },
5231 { "fmsubsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
5233 { "fnmaddps", { { OP_DREX4, q_mode } } },
5234 { "fnmaddpd", { { OP_DREX4, q_mode } } },
5235 { "fnmaddss", { { OP_DREX4, w_mode } } },
5236 { "fnmaddsd", { { OP_DREX4, d_mode } } },
5237 { "fnmaddps", { { OP_DREX4, DREX_OC1 + q_mode } } },
5238 { "fnmaddpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
5239 { "fnmaddss", { { OP_DREX4, DREX_OC1 + w_mode } } },
5240 { "fnmaddsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
5242 { "fnmsubps", { { OP_DREX4, q_mode } } },
5243 { "fnmsubpd", { { OP_DREX4, q_mode } } },
5244 { "fnmsubss", { { OP_DREX4, w_mode } } },
5245 { "fnmsubsd", { { OP_DREX4, d_mode } } },
5246 { "fnmsubps", { { OP_DREX4, DREX_OC1 + q_mode } } },
5247 { "fnmsubpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
5248 { "fnmsubss", { { OP_DREX4, DREX_OC1 + w_mode } } },
5249 { "fnmsubsd", { { OP_DREX4, DREX_OC1 + d_mode } } },
5251 { "permps", { { OP_DREX4, q_mode } } },
5252 { "permpd", { { OP_DREX4, q_mode } } },
5253 { "pcmov", { { OP_DREX4, q_mode } } },
5254 { "pperm", { { OP_DREX4, q_mode } } },
5255 { "permps", { { OP_DREX4, DREX_OC1 + q_mode } } },
5256 { "permpd", { { OP_DREX4, DREX_OC1 + q_mode } } },
5257 { "pcmov", { { OP_DREX4, DREX_OC1 + w_mode } } },
5258 { "pperm", { { OP_DREX4, DREX_OC1 + d_mode } } },
5260 { "(bad)", { XX } },
5261 { "(bad)", { XX } },
5262 { "(bad)", { XX } },
5263 { "(bad)", { XX } },
5264 { "(bad)", { XX } },
5265 { "(bad)", { XX } },
5266 { "(bad)", { XX } },
5267 { "(bad)", { XX } },
5269 { "(bad)", { XX } },
5270 { "(bad)", { XX } },
5271 { "(bad)", { XX } },
5272 { "(bad)", { XX } },
5273 { "(bad)", { XX } },
5274 { "(bad)", { XX } },
5275 { "(bad)", { XX } },
5276 { "(bad)", { XX } },
5278 { "(bad)", { XX } },
5279 { "(bad)", { XX } },
5280 { "(bad)", { XX } },
5281 { "(bad)", { XX } },
5282 { "(bad)", { XX } },
5283 { "(bad)", { XX } },
5284 { "(bad)", { XX } },
5285 { "(bad)", { XX } },
5287 { "protb", { { OP_DREX3, q_mode } } },
5288 { "protw", { { OP_DREX3, q_mode } } },
5289 { "protd", { { OP_DREX3, q_mode } } },
5290 { "protq", { { OP_DREX3, q_mode } } },
5291 { "pshlb", { { OP_DREX3, q_mode } } },
5292 { "pshlw", { { OP_DREX3, q_mode } } },
5293 { "pshld", { { OP_DREX3, q_mode } } },
5294 { "pshlq", { { OP_DREX3, q_mode } } },
5296 { "pshab", { { OP_DREX3, q_mode } } },
5297 { "pshaw", { { OP_DREX3, q_mode } } },
5298 { "pshad", { { OP_DREX3, q_mode } } },
5299 { "pshaq", { { OP_DREX3, q_mode } } },
5300 { "(bad)", { XX } },
5301 { "(bad)", { XX } },
5302 { "(bad)", { XX } },
5303 { "(bad)", { XX } },
5305 { "(bad)", { XX } },
5306 { "(bad)", { XX } },
5307 { "(bad)", { XX } },
5308 { "(bad)", { XX } },
5309 { "(bad)", { XX } },
5310 { "(bad)", { XX } },
5311 { "(bad)", { XX } },
5312 { "(bad)", { XX } },
5314 { "(bad)", { XX } },
5315 { "(bad)", { XX } },
5316 { "(bad)", { XX } },
5317 { "(bad)", { XX } },
5318 { "(bad)", { XX } },
5319 { "(bad)", { XX } },
5320 { "(bad)", { XX } },
5321 { "(bad)", { XX } },
5323 { "(bad)", { XX } },
5324 { "(bad)", { XX } },
5325 { "(bad)", { XX } },
5326 { "(bad)", { XX } },
5327 { "(bad)", { XX } },
5328 { "(bad)", { XX } },
5329 { "(bad)", { XX } },
5330 { "(bad)", { XX } },
5332 { "(bad)", { XX } },
5333 { "(bad)", { XX } },
5334 { "(bad)", { XX } },
5335 { "(bad)", { XX } },
5336 { "(bad)", { XX } },
5337 { "(bad)", { XX } },
5338 { "(bad)", { XX } },
5339 { "(bad)", { XX } },
5341 { "(bad)", { XX } },
5342 { "(bad)", { XX } },
5343 { "(bad)", { XX } },
5344 { "(bad)", { XX } },
5345 { "(bad)", { XX } },
5346 { "(bad)", { XX } },
5347 { "(bad)", { XX } },
5348 { "(bad)", { XX } },
5350 { "(bad)", { XX } },
5351 { "(bad)", { XX } },
5352 { "(bad)", { XX } },
5353 { "(bad)", { XX } },
5354 { "(bad)", { XX } },
5355 { "(bad)", { XX } },
5356 { "(bad)", { XX } },
5357 { "(bad)", { XX } },
5359 { "(bad)", { XX } },
5360 { "(bad)", { XX } },
5361 { "(bad)", { XX } },
5362 { "(bad)", { XX } },
5363 { "(bad)", { XX } },
5364 { "pmacssww", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5365 { "pmacsswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5366 { "pmacssdql", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5368 { "(bad)", { XX } },
5369 { "(bad)", { XX } },
5370 { "(bad)", { XX } },
5371 { "(bad)", { XX } },
5372 { "(bad)", { XX } },
5373 { "(bad)", { XX } },
5374 { "pmacssdd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5375 { "pmacssdqh", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5377 { "(bad)", { XX } },
5378 { "(bad)", { XX } },
5379 { "(bad)", { XX } },
5380 { "(bad)", { XX } },
5381 { "(bad)", { XX } },
5382 { "pmacsww", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5383 { "pmacswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5384 { "pmacsdql", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5386 { "(bad)", { XX } },
5387 { "(bad)", { XX } },
5388 { "(bad)", { XX } },
5389 { "(bad)", { XX } },
5390 { "(bad)", { XX } },
5391 { "(bad)", { XX } },
5392 { "pmacsdd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5393 { "pmacsdqh", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5395 { "(bad)", { XX } },
5396 { "(bad)", { XX } },
5397 { "(bad)", { XX } },
5398 { "(bad)", { XX } },
5399 { "(bad)", { XX } },
5400 { "(bad)", { XX } },
5401 { "pmadcsswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5402 { "(bad)", { XX } },
5404 { "(bad)", { XX } },
5405 { "(bad)", { XX } },
5406 { "(bad)", { XX } },
5407 { "(bad)", { XX } },
5408 { "(bad)", { XX } },
5409 { "(bad)", { XX } },
5410 { "(bad)", { XX } },
5411 { "(bad)", { XX } },
5413 { "(bad)", { XX } },
5414 { "(bad)", { XX } },
5415 { "(bad)", { XX } },
5416 { "(bad)", { XX } },
5417 { "(bad)", { XX } },
5418 { "(bad)", { XX } },
5419 { "pmadcswd", { { OP_DREX4, DREX_OC1 + DREX_NO_OC0 + q_mode } } },
5420 { "(bad)", { XX } },
5422 { "(bad)", { XX } },
5423 { "(bad)", { XX } },
5424 { "(bad)", { XX } },
5425 { "(bad)", { XX } },
5426 { "(bad)", { XX } },
5427 { "(bad)", { XX } },
5428 { "(bad)", { XX } },
5429 { "(bad)", { XX } },
5431 { "(bad)", { XX } },
5432 { "(bad)", { XX } },
5433 { "(bad)", { XX } },
5434 { "(bad)", { XX } },
5435 { "(bad)", { XX } },
5436 { "(bad)", { XX } },
5437 { "(bad)", { XX } },
5438 { "(bad)", { XX } },
5440 { "(bad)", { XX } },
5441 { "(bad)", { XX } },
5442 { "(bad)", { XX } },
5443 { "(bad)", { XX } },
5444 { "(bad)", { XX } },
5445 { "(bad)", { XX } },
5446 { "(bad)", { XX } },
5447 { "(bad)", { XX } },
5449 { "(bad)", { XX } },
5450 { "(bad)", { XX } },
5451 { "(bad)", { XX } },
5452 { "(bad)", { XX } },
5453 { "(bad)", { XX } },
5454 { "(bad)", { XX } },
5455 { "(bad)", { XX } },
5456 { "(bad)", { XX } },
5458 { "(bad)", { XX } },
5459 { "(bad)", { XX } },
5460 { "(bad)", { XX } },
5461 { "(bad)", { XX } },
5462 { "(bad)", { XX } },
5463 { "(bad)", { XX } },
5464 { "(bad)", { XX } },
5465 { "(bad)", { XX } },
5467 { "(bad)", { XX } },
5468 { "(bad)", { XX } },
5469 { "(bad)", { XX } },
5470 { "(bad)", { XX } },
5471 { "(bad)", { XX } },
5472 { "(bad)", { XX } },
5473 { "(bad)", { XX } },
5474 { "(bad)", { XX } },
5476 { "(bad)", { XX } },
5477 { "(bad)", { XX } },
5478 { "(bad)", { XX } },
5479 { "(bad)", { XX } },
5480 { "(bad)", { XX } },
5481 { "(bad)", { XX } },
5482 { "(bad)", { XX } },
5483 { "(bad)", { XX } },
5485 { "(bad)", { XX } },
5486 { "(bad)", { XX } },
5487 { "(bad)", { XX } },
5488 { "(bad)", { XX } },
5489 { "(bad)", { XX } },
5490 { "(bad)", { XX } },
5491 { "(bad)", { XX } },
5492 { "(bad)", { XX } },
5494 { "(bad)", { XX } },
5495 { "(bad)", { XX } },
5496 { "(bad)", { XX } },
5497 { "(bad)", { XX } },
5498 { "(bad)", { XX } },
5499 { "(bad)", { XX } },
5500 { "(bad)", { XX } },
5501 { "(bad)", { XX } },
5503 /* THREE_BYTE_0F25 */
5506 { "(bad)", { XX } },
5507 { "(bad)", { XX } },
5508 { "(bad)", { XX } },
5509 { "(bad)", { XX } },
5510 { "(bad)", { XX } },
5511 { "(bad)", { XX } },
5512 { "(bad)", { XX } },
5513 { "(bad)", { XX } },
5515 { "(bad)", { XX } },
5516 { "(bad)", { XX } },
5517 { "(bad)", { XX } },
5518 { "(bad)", { XX } },
5519 { "(bad)", { XX } },
5520 { "(bad)", { XX } },
5521 { "(bad)", { XX } },
5522 { "(bad)", { XX } },
5524 { "(bad)", { XX } },
5525 { "(bad)", { XX } },
5526 { "(bad)", { XX } },
5527 { "(bad)", { XX } },
5528 { "(bad)", { XX } },
5529 { "(bad)", { XX } },
5530 { "(bad)", { XX } },
5531 { "(bad)", { XX } },
5533 { "(bad)", { XX } },
5534 { "(bad)", { XX } },
5535 { "(bad)", { XX } },
5536 { "(bad)", { XX } },
5537 { "(bad)", { XX } },
5538 { "(bad)", { XX } },
5539 { "(bad)", { XX } },
5540 { "(bad)", { XX } },
5542 { "(bad)", { XX } },
5543 { "(bad)", { XX } },
5544 { "(bad)", { XX } },
5545 { "(bad)", { XX } },
5546 { "(bad)", { XX } },
5547 { "(bad)", { XX } },
5548 { "(bad)", { XX } },
5549 { "(bad)", { XX } },
5551 { "(bad)", { XX } },
5552 { "(bad)", { XX } },
5553 { "(bad)", { XX } },
5554 { "(bad)", { XX } },
5555 { "comps", { { OP_DREX3, q_mode }, { OP_DREX_FCMP, b_mode } } },
5556 { "compd", { { OP_DREX3, q_mode }, { OP_DREX_FCMP, b_mode } } },
5557 { "comss", { { OP_DREX3, w_mode }, { OP_DREX_FCMP, b_mode } } },
5558 { "comsd", { { OP_DREX3, d_mode }, { OP_DREX_FCMP, b_mode } } },
5560 { "(bad)", { XX } },
5561 { "(bad)", { XX } },
5562 { "(bad)", { XX } },
5563 { "(bad)", { XX } },
5564 { "(bad)", { XX } },
5565 { "(bad)", { XX } },
5566 { "(bad)", { XX } },
5567 { "(bad)", { XX } },
5569 { "(bad)", { XX } },
5570 { "(bad)", { XX } },
5571 { "(bad)", { XX } },
5572 { "(bad)", { XX } },
5573 { "(bad)", { XX } },
5574 { "(bad)", { XX } },
5575 { "(bad)", { XX } },
5576 { "(bad)", { XX } },
5578 { "(bad)", { XX } },
5579 { "(bad)", { XX } },
5580 { "(bad)", { XX } },
5581 { "(bad)", { XX } },
5582 { "(bad)", { XX } },
5583 { "(bad)", { XX } },
5584 { "(bad)", { XX } },
5585 { "(bad)", { XX } },
5587 { "(bad)", { XX } },
5588 { "(bad)", { XX } },
5589 { "(bad)", { XX } },
5590 { "(bad)", { XX } },
5591 { "pcomb", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5592 { "pcomw", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5593 { "pcomd", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5594 { "pcomq", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5596 { "(bad)", { XX } },
5597 { "(bad)", { XX } },
5598 { "(bad)", { XX } },
5599 { "(bad)", { XX } },
5600 { "(bad)", { XX } },
5601 { "(bad)", { XX } },
5602 { "(bad)", { XX } },
5603 { "(bad)", { XX } },
5605 { "(bad)", { XX } },
5606 { "(bad)", { XX } },
5607 { "(bad)", { XX } },
5608 { "(bad)", { XX } },
5609 { "(bad)", { XX } },
5610 { "(bad)", { XX } },
5611 { "(bad)", { XX } },
5612 { "(bad)", { XX } },
5614 { "(bad)", { XX } },
5615 { "(bad)", { XX } },
5616 { "(bad)", { XX } },
5617 { "(bad)", { XX } },
5618 { "(bad)", { XX } },
5619 { "(bad)", { XX } },
5620 { "(bad)", { XX } },
5621 { "(bad)", { XX } },
5623 { "(bad)", { XX } },
5624 { "(bad)", { XX } },
5625 { "(bad)", { XX } },
5626 { "(bad)", { XX } },
5627 { "pcomub", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5628 { "pcomuw", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5629 { "pcomud", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5630 { "pcomuq", { { OP_DREX3, q_mode }, { OP_DREX_ICMP, b_mode } } },
5632 { "(bad)", { XX } },
5633 { "(bad)", { XX } },
5634 { "(bad)", { XX } },
5635 { "(bad)", { XX } },
5636 { "(bad)", { XX } },
5637 { "(bad)", { XX } },
5638 { "(bad)", { XX } },
5639 { "(bad)", { XX } },
5641 { "(bad)", { XX } },
5642 { "(bad)", { XX } },
5643 { "(bad)", { XX } },
5644 { "(bad)", { XX } },
5645 { "(bad)", { XX } },
5646 { "(bad)", { XX } },
5647 { "(bad)", { XX } },
5648 { "(bad)", { XX } },
5650 { "(bad)", { XX } },
5651 { "(bad)", { XX } },
5652 { "(bad)", { XX } },
5653 { "(bad)", { XX } },
5654 { "(bad)", { XX } },
5655 { "(bad)", { XX } },
5656 { "(bad)", { XX } },
5657 { "(bad)", { XX } },
5659 { "(bad)", { XX } },
5660 { "(bad)", { XX } },
5661 { "(bad)", { XX } },
5662 { "(bad)", { XX } },
5663 { "(bad)", { XX } },
5664 { "(bad)", { XX } },
5665 { "(bad)", { XX } },
5666 { "(bad)", { XX } },
5668 { "(bad)", { XX } },
5669 { "(bad)", { XX } },
5670 { "(bad)", { XX } },
5671 { "(bad)", { XX } },
5672 { "(bad)", { XX } },
5673 { "(bad)", { XX } },
5674 { "(bad)", { XX } },
5675 { "(bad)", { XX } },
5677 { "(bad)", { XX } },
5678 { "(bad)", { XX } },
5679 { "(bad)", { XX } },
5680 { "(bad)", { XX } },
5681 { "(bad)", { XX } },
5682 { "(bad)", { XX } },
5683 { "(bad)", { XX } },
5684 { "(bad)", { XX } },
5686 { "(bad)", { XX } },
5687 { "(bad)", { XX } },
5688 { "(bad)", { XX } },
5689 { "(bad)", { XX } },
5690 { "(bad)", { XX } },
5691 { "(bad)", { XX } },
5692 { "(bad)", { XX } },
5693 { "(bad)", { XX } },
5695 { "(bad)", { XX } },
5696 { "(bad)", { XX } },
5697 { "(bad)", { XX } },
5698 { "(bad)", { XX } },
5699 { "(bad)", { XX } },
5700 { "(bad)", { XX } },
5701 { "(bad)", { XX } },
5702 { "(bad)", { XX } },
5704 { "(bad)", { XX } },
5705 { "(bad)", { XX } },
5706 { "(bad)", { XX } },
5707 { "(bad)", { XX } },
5708 { "(bad)", { XX } },
5709 { "(bad)", { XX } },
5710 { "(bad)", { XX } },
5711 { "(bad)", { XX } },
5713 { "(bad)", { XX } },
5714 { "(bad)", { XX } },
5715 { "(bad)", { XX } },
5716 { "(bad)", { XX } },
5717 { "(bad)", { XX } },
5718 { "(bad)", { XX } },
5719 { "(bad)", { XX } },
5720 { "(bad)", { XX } },
5722 { "(bad)", { XX } },
5723 { "(bad)", { XX } },
5724 { "(bad)", { XX } },
5725 { "(bad)", { XX } },
5726 { "(bad)", { XX } },
5727 { "(bad)", { XX } },
5728 { "(bad)", { XX } },
5729 { "(bad)", { XX } },
5731 { "(bad)", { XX } },
5732 { "(bad)", { XX } },
5733 { "(bad)", { XX } },
5734 { "(bad)", { XX } },
5735 { "(bad)", { XX } },
5736 { "(bad)", { XX } },
5737 { "(bad)", { XX } },
5738 { "(bad)", { XX } },
5740 { "(bad)", { XX } },
5741 { "(bad)", { XX } },
5742 { "(bad)", { XX } },
5743 { "(bad)", { XX } },
5744 { "(bad)", { XX } },
5745 { "(bad)", { XX } },
5746 { "(bad)", { XX } },
5747 { "(bad)", { XX } },
5749 { "(bad)", { XX } },
5750 { "(bad)", { XX } },
5751 { "(bad)", { XX } },
5752 { "(bad)", { XX } },
5753 { "(bad)", { XX } },
5754 { "(bad)", { XX } },
5755 { "(bad)", { XX } },
5756 { "(bad)", { XX } },
5758 { "(bad)", { XX } },
5759 { "(bad)", { XX } },
5760 { "(bad)", { XX } },
5761 { "(bad)", { XX } },
5762 { "(bad)", { XX } },
5763 { "(bad)", { XX } },
5764 { "(bad)", { XX } },
5765 { "(bad)", { XX } },
5767 { "(bad)", { XX } },
5768 { "(bad)", { XX } },
5769 { "(bad)", { XX } },
5770 { "(bad)", { XX } },
5771 { "(bad)", { XX } },
5772 { "(bad)", { XX } },
5773 { "(bad)", { XX } },
5774 { "(bad)", { XX } },
5776 { "(bad)", { XX } },
5777 { "(bad)", { XX } },
5778 { "(bad)", { XX } },
5779 { "(bad)", { XX } },
5780 { "(bad)", { XX } },
5781 { "(bad)", { XX } },
5782 { "(bad)", { XX } },
5783 { "(bad)", { XX } },
5785 { "(bad)", { XX } },
5786 { "(bad)", { XX } },
5787 { "(bad)", { XX } },
5788 { "(bad)", { XX } },
5789 { "(bad)", { XX } },
5790 { "(bad)", { XX } },
5791 { "(bad)", { XX } },
5792 { "(bad)", { XX } },
5794 /* THREE_BYTE_0F38 */
5797 { "pshufb", { MX, EM } },
5798 { "phaddw", { MX, EM } },
5799 { "phaddd", { MX, EM } },
5800 { "phaddsw", { MX, EM } },
5801 { "pmaddubsw", { MX, EM } },
5802 { "phsubw", { MX, EM } },
5803 { "phsubd", { MX, EM } },
5804 { "phsubsw", { MX, EM } },
5806 { "psignb", { MX, EM } },
5807 { "psignw", { MX, EM } },
5808 { "psignd", { MX, EM } },
5809 { "pmulhrsw", { MX, EM } },
5810 { "(bad)", { XX } },
5811 { "(bad)", { XX } },
5812 { "(bad)", { XX } },
5813 { "(bad)", { XX } },
5815 { PREFIX_TABLE (PREFIX_0F3810) },
5816 { "(bad)", { XX } },
5817 { "(bad)", { XX } },
5818 { "(bad)", { XX } },
5819 { PREFIX_TABLE (PREFIX_0F3814) },
5820 { PREFIX_TABLE (PREFIX_0F3815) },
5821 { "(bad)", { XX } },
5822 { PREFIX_TABLE (PREFIX_0F3817) },
5824 { "(bad)", { XX } },
5825 { "(bad)", { XX } },
5826 { "(bad)", { XX } },
5827 { "(bad)", { XX } },
5828 { "pabsb", { MX, EM } },
5829 { "pabsw", { MX, EM } },
5830 { "pabsd", { MX, EM } },
5831 { "(bad)", { XX } },
5833 { PREFIX_TABLE (PREFIX_0F3820) },
5834 { PREFIX_TABLE (PREFIX_0F3821) },
5835 { PREFIX_TABLE (PREFIX_0F3822) },
5836 { PREFIX_TABLE (PREFIX_0F3823) },
5837 { PREFIX_TABLE (PREFIX_0F3824) },
5838 { PREFIX_TABLE (PREFIX_0F3825) },
5839 { "(bad)", { XX } },
5840 { "(bad)", { XX } },
5842 { PREFIX_TABLE (PREFIX_0F3828) },
5843 { PREFIX_TABLE (PREFIX_0F3829) },
5844 { PREFIX_TABLE (PREFIX_0F382A) },
5845 { PREFIX_TABLE (PREFIX_0F382B) },
5846 { "(bad)", { XX } },
5847 { "(bad)", { XX } },
5848 { "(bad)", { XX } },
5849 { "(bad)", { XX } },
5851 { PREFIX_TABLE (PREFIX_0F3830) },
5852 { PREFIX_TABLE (PREFIX_0F3831) },
5853 { PREFIX_TABLE (PREFIX_0F3832) },
5854 { PREFIX_TABLE (PREFIX_0F3833) },
5855 { PREFIX_TABLE (PREFIX_0F3834) },
5856 { PREFIX_TABLE (PREFIX_0F3835) },
5857 { "(bad)", { XX } },
5858 { PREFIX_TABLE (PREFIX_0F3837) },
5860 { PREFIX_TABLE (PREFIX_0F3838) },
5861 { PREFIX_TABLE (PREFIX_0F3839) },
5862 { PREFIX_TABLE (PREFIX_0F383A) },
5863 { PREFIX_TABLE (PREFIX_0F383B) },
5864 { PREFIX_TABLE (PREFIX_0F383C) },
5865 { PREFIX_TABLE (PREFIX_0F383D) },
5866 { PREFIX_TABLE (PREFIX_0F383E) },
5867 { PREFIX_TABLE (PREFIX_0F383F) },
5869 { PREFIX_TABLE (PREFIX_0F3840) },
5870 { PREFIX_TABLE (PREFIX_0F3841) },
5871 { "(bad)", { XX } },
5872 { "(bad)", { XX } },
5873 { "(bad)", { XX } },
5874 { "(bad)", { XX } },
5875 { "(bad)", { XX } },
5876 { "(bad)", { XX } },
5878 { "(bad)", { XX } },
5879 { "(bad)", { XX } },
5880 { "(bad)", { XX } },
5881 { "(bad)", { XX } },
5882 { "(bad)", { XX } },
5883 { "(bad)", { XX } },
5884 { "(bad)", { XX } },
5885 { "(bad)", { XX } },
5887 { "(bad)", { XX } },
5888 { "(bad)", { XX } },
5889 { "(bad)", { XX } },
5890 { "(bad)", { XX } },
5891 { "(bad)", { XX } },
5892 { "(bad)", { XX } },
5893 { "(bad)", { XX } },
5894 { "(bad)", { XX } },
5896 { "(bad)", { XX } },
5897 { "(bad)", { XX } },
5898 { "(bad)", { XX } },
5899 { "(bad)", { XX } },
5900 { "(bad)", { XX } },
5901 { "(bad)", { XX } },
5902 { "(bad)", { XX } },
5903 { "(bad)", { XX } },
5905 { "(bad)", { XX } },
5906 { "(bad)", { XX } },
5907 { "(bad)", { XX } },
5908 { "(bad)", { XX } },
5909 { "(bad)", { XX } },
5910 { "(bad)", { XX } },
5911 { "(bad)", { XX } },
5912 { "(bad)", { XX } },
5914 { "(bad)", { XX } },
5915 { "(bad)", { XX } },
5916 { "(bad)", { XX } },
5917 { "(bad)", { XX } },
5918 { "(bad)", { XX } },
5919 { "(bad)", { XX } },
5920 { "(bad)", { XX } },
5921 { "(bad)", { XX } },
5923 { "(bad)", { XX } },
5924 { "(bad)", { XX } },
5925 { "(bad)", { XX } },
5926 { "(bad)", { XX } },
5927 { "(bad)", { XX } },
5928 { "(bad)", { XX } },
5929 { "(bad)", { XX } },
5930 { "(bad)", { XX } },
5932 { "(bad)", { XX } },
5933 { "(bad)", { XX } },
5934 { "(bad)", { XX } },
5935 { "(bad)", { XX } },
5936 { "(bad)", { XX } },
5937 { "(bad)", { XX } },
5938 { "(bad)", { XX } },
5939 { "(bad)", { XX } },
5941 { PREFIX_TABLE (PREFIX_0F3880) },
5942 { PREFIX_TABLE (PREFIX_0F3881) },
5943 { "(bad)", { XX } },
5944 { "(bad)", { XX } },
5945 { "(bad)", { XX } },
5946 { "(bad)", { XX } },
5947 { "(bad)", { XX } },
5948 { "(bad)", { XX } },
5950 { "(bad)", { XX } },
5951 { "(bad)", { XX } },
5952 { "(bad)", { XX } },
5953 { "(bad)", { XX } },
5954 { "(bad)", { XX } },
5955 { "(bad)", { XX } },
5956 { "(bad)", { XX } },
5957 { "(bad)", { XX } },
5959 { "(bad)", { XX } },
5960 { "(bad)", { XX } },
5961 { "(bad)", { XX } },
5962 { "(bad)", { XX } },
5963 { "(bad)", { XX } },
5964 { "(bad)", { XX } },
5965 { "(bad)", { XX } },
5966 { "(bad)", { XX } },
5968 { "(bad)", { XX } },
5969 { "(bad)", { XX } },
5970 { "(bad)", { XX } },
5971 { "(bad)", { XX } },
5972 { "(bad)", { XX } },
5973 { "(bad)", { XX } },
5974 { "(bad)", { XX } },
5975 { "(bad)", { XX } },
5977 { "(bad)", { XX } },
5978 { "(bad)", { XX } },
5979 { "(bad)", { XX } },
5980 { "(bad)", { XX } },
5981 { "(bad)", { XX } },
5982 { "(bad)", { XX } },
5983 { "(bad)", { XX } },
5984 { "(bad)", { XX } },
5986 { "(bad)", { XX } },
5987 { "(bad)", { XX } },
5988 { "(bad)", { XX } },
5989 { "(bad)", { XX } },
5990 { "(bad)", { XX } },
5991 { "(bad)", { XX } },
5992 { "(bad)", { XX } },
5993 { "(bad)", { XX } },
5995 { "(bad)", { XX } },
5996 { "(bad)", { XX } },
5997 { "(bad)", { XX } },
5998 { "(bad)", { XX } },
5999 { "(bad)", { XX } },
6000 { "(bad)", { XX } },
6001 { "(bad)", { XX } },
6002 { "(bad)", { XX } },
6004 { "(bad)", { XX } },
6005 { "(bad)", { XX } },
6006 { "(bad)", { XX } },
6007 { "(bad)", { XX } },
6008 { "(bad)", { XX } },
6009 { "(bad)", { XX } },
6010 { "(bad)", { XX } },
6011 { "(bad)", { XX } },
6013 { "(bad)", { XX } },
6014 { "(bad)", { XX } },
6015 { "(bad)", { XX } },
6016 { "(bad)", { XX } },
6017 { "(bad)", { XX } },
6018 { "(bad)", { XX } },
6019 { "(bad)", { XX } },
6020 { "(bad)", { XX } },
6022 { "(bad)", { XX } },
6023 { "(bad)", { XX } },
6024 { "(bad)", { XX } },
6025 { "(bad)", { XX } },
6026 { "(bad)", { XX } },
6027 { "(bad)", { XX } },
6028 { "(bad)", { XX } },
6029 { "(bad)", { XX } },
6031 { "(bad)", { XX } },
6032 { "(bad)", { XX } },
6033 { "(bad)", { XX } },
6034 { "(bad)", { XX } },
6035 { "(bad)", { XX } },
6036 { "(bad)", { XX } },
6037 { "(bad)", { XX } },
6038 { "(bad)", { XX } },
6040 { "(bad)", { XX } },
6041 { "(bad)", { XX } },
6042 { "(bad)", { XX } },
6043 { PREFIX_TABLE (PREFIX_0F38DB) },
6044 { PREFIX_TABLE (PREFIX_0F38DC) },
6045 { PREFIX_TABLE (PREFIX_0F38DD) },
6046 { PREFIX_TABLE (PREFIX_0F38DE) },
6047 { PREFIX_TABLE (PREFIX_0F38DF) },
6049 { "(bad)", { XX } },
6050 { "(bad)", { XX } },
6051 { "(bad)", { XX } },
6052 { "(bad)", { XX } },
6053 { "(bad)", { XX } },
6054 { "(bad)", { XX } },
6055 { "(bad)", { XX } },
6056 { "(bad)", { XX } },
6058 { "(bad)", { XX } },
6059 { "(bad)", { XX } },
6060 { "(bad)", { XX } },
6061 { "(bad)", { XX } },
6062 { "(bad)", { XX } },
6063 { "(bad)", { XX } },
6064 { "(bad)", { XX } },
6065 { "(bad)", { XX } },
6067 { PREFIX_TABLE (PREFIX_0F38F0) },
6068 { PREFIX_TABLE (PREFIX_0F38F1) },
6069 { "(bad)", { XX } },
6070 { "(bad)", { XX } },
6071 { "(bad)", { XX } },
6072 { "(bad)", { XX } },
6073 { "(bad)", { XX } },
6074 { "(bad)", { XX } },
6076 { "(bad)", { XX } },
6077 { "(bad)", { XX } },
6078 { "(bad)", { XX } },
6079 { "(bad)", { XX } },
6080 { "(bad)", { XX } },
6081 { "(bad)", { XX } },
6082 { "(bad)", { XX } },
6083 { "(bad)", { XX } },
6085 /* THREE_BYTE_0F3A */
6088 { "(bad)", { XX } },
6089 { "(bad)", { XX } },
6090 { "(bad)", { XX } },
6091 { "(bad)", { XX } },
6092 { "(bad)", { XX } },
6093 { "(bad)", { XX } },
6094 { "(bad)", { XX } },
6095 { "(bad)", { XX } },
6097 { PREFIX_TABLE (PREFIX_0F3A08) },
6098 { PREFIX_TABLE (PREFIX_0F3A09) },
6099 { PREFIX_TABLE (PREFIX_0F3A0A) },
6100 { PREFIX_TABLE (PREFIX_0F3A0B) },
6101 { PREFIX_TABLE (PREFIX_0F3A0C) },
6102 { PREFIX_TABLE (PREFIX_0F3A0D) },
6103 { PREFIX_TABLE (PREFIX_0F3A0E) },
6104 { "palignr", { MX, EM, Ib } },
6106 { "(bad)", { XX } },
6107 { "(bad)", { XX } },
6108 { "(bad)", { XX } },
6109 { "(bad)", { XX } },
6110 { PREFIX_TABLE (PREFIX_0F3A14) },
6111 { PREFIX_TABLE (PREFIX_0F3A15) },
6112 { PREFIX_TABLE (PREFIX_0F3A16) },
6113 { PREFIX_TABLE (PREFIX_0F3A17) },
6115 { "(bad)", { XX } },
6116 { "(bad)", { XX } },
6117 { "(bad)", { XX } },
6118 { "(bad)", { XX } },
6119 { "(bad)", { XX } },
6120 { "(bad)", { XX } },
6121 { "(bad)", { XX } },
6122 { "(bad)", { XX } },
6124 { PREFIX_TABLE (PREFIX_0F3A20) },
6125 { PREFIX_TABLE (PREFIX_0F3A21) },
6126 { PREFIX_TABLE (PREFIX_0F3A22) },
6127 { "(bad)", { XX } },
6128 { "(bad)", { XX } },
6129 { "(bad)", { XX } },
6130 { "(bad)", { XX } },
6131 { "(bad)", { XX } },
6133 { "(bad)", { XX } },
6134 { "(bad)", { XX } },
6135 { "(bad)", { XX } },
6136 { "(bad)", { XX } },
6137 { "(bad)", { XX } },
6138 { "(bad)", { XX } },
6139 { "(bad)", { XX } },
6140 { "(bad)", { XX } },
6142 { "(bad)", { XX } },
6143 { "(bad)", { XX } },
6144 { "(bad)", { XX } },
6145 { "(bad)", { XX } },
6146 { "(bad)", { XX } },
6147 { "(bad)", { XX } },
6148 { "(bad)", { XX } },
6149 { "(bad)", { XX } },
6151 { "(bad)", { XX } },
6152 { "(bad)", { XX } },
6153 { "(bad)", { XX } },
6154 { "(bad)", { XX } },
6155 { "(bad)", { XX } },
6156 { "(bad)", { XX } },
6157 { "(bad)", { XX } },
6158 { "(bad)", { XX } },
6160 { PREFIX_TABLE (PREFIX_0F3A40) },
6161 { PREFIX_TABLE (PREFIX_0F3A41) },
6162 { PREFIX_TABLE (PREFIX_0F3A42) },
6163 { "(bad)", { XX } },
6164 { PREFIX_TABLE (PREFIX_0F3A44) },
6165 { "(bad)", { XX } },
6166 { "(bad)", { XX } },
6167 { "(bad)", { XX } },
6169 { "(bad)", { XX } },
6170 { "(bad)", { XX } },
6171 { "(bad)", { XX } },
6172 { "(bad)", { XX } },
6173 { "(bad)", { XX } },
6174 { "(bad)", { XX } },
6175 { "(bad)", { XX } },
6176 { "(bad)", { XX } },
6178 { "(bad)", { XX } },
6179 { "(bad)", { XX } },
6180 { "(bad)", { XX } },
6181 { "(bad)", { XX } },
6182 { "(bad)", { XX } },
6183 { "(bad)", { XX } },
6184 { "(bad)", { XX } },
6185 { "(bad)", { XX } },
6187 { "(bad)", { XX } },
6188 { "(bad)", { XX } },
6189 { "(bad)", { XX } },
6190 { "(bad)", { XX } },
6191 { "(bad)", { XX } },
6192 { "(bad)", { XX } },
6193 { "(bad)", { XX } },
6194 { "(bad)", { XX } },
6196 { PREFIX_TABLE (PREFIX_0F3A60) },
6197 { PREFIX_TABLE (PREFIX_0F3A61) },
6198 { PREFIX_TABLE (PREFIX_0F3A62) },
6199 { PREFIX_TABLE (PREFIX_0F3A63) },
6200 { "(bad)", { XX } },
6201 { "(bad)", { XX } },
6202 { "(bad)", { XX } },
6203 { "(bad)", { XX } },
6205 { "(bad)", { XX } },
6206 { "(bad)", { XX } },
6207 { "(bad)", { XX } },
6208 { "(bad)", { XX } },
6209 { "(bad)", { XX } },
6210 { "(bad)", { XX } },
6211 { "(bad)", { XX } },
6212 { "(bad)", { XX } },
6214 { "(bad)", { XX } },
6215 { "(bad)", { XX } },
6216 { "(bad)", { XX } },
6217 { "(bad)", { XX } },
6218 { "(bad)", { XX } },
6219 { "(bad)", { XX } },
6220 { "(bad)", { XX } },
6221 { "(bad)", { XX } },
6223 { "(bad)", { XX } },
6224 { "(bad)", { XX } },
6225 { "(bad)", { XX } },
6226 { "(bad)", { XX } },
6227 { "(bad)", { XX } },
6228 { "(bad)", { XX } },
6229 { "(bad)", { XX } },
6230 { "(bad)", { XX } },
6232 { "(bad)", { XX } },
6233 { "(bad)", { XX } },
6234 { "(bad)", { XX } },
6235 { "(bad)", { XX } },
6236 { "(bad)", { XX } },
6237 { "(bad)", { XX } },
6238 { "(bad)", { XX } },
6239 { "(bad)", { XX } },
6241 { "(bad)", { XX } },
6242 { "(bad)", { XX } },
6243 { "(bad)", { XX } },
6244 { "(bad)", { XX } },
6245 { "(bad)", { XX } },
6246 { "(bad)", { XX } },
6247 { "(bad)", { XX } },
6248 { "(bad)", { XX } },
6250 { "(bad)", { XX } },
6251 { "(bad)", { XX } },
6252 { "(bad)", { XX } },
6253 { "(bad)", { XX } },
6254 { "(bad)", { XX } },
6255 { "(bad)", { XX } },
6256 { "(bad)", { XX } },
6257 { "(bad)", { XX } },
6259 { "(bad)", { XX } },
6260 { "(bad)", { XX } },
6261 { "(bad)", { XX } },
6262 { "(bad)", { XX } },
6263 { "(bad)", { XX } },
6264 { "(bad)", { XX } },
6265 { "(bad)", { XX } },
6266 { "(bad)", { XX } },
6268 { "(bad)", { XX } },
6269 { "(bad)", { XX } },
6270 { "(bad)", { XX } },
6271 { "(bad)", { XX } },
6272 { "(bad)", { XX } },
6273 { "(bad)", { XX } },
6274 { "(bad)", { XX } },
6275 { "(bad)", { XX } },
6277 { "(bad)", { XX } },
6278 { "(bad)", { XX } },
6279 { "(bad)", { XX } },
6280 { "(bad)", { XX } },
6281 { "(bad)", { XX } },
6282 { "(bad)", { XX } },
6283 { "(bad)", { XX } },
6284 { "(bad)", { XX } },
6286 { "(bad)", { XX } },
6287 { "(bad)", { XX } },
6288 { "(bad)", { XX } },
6289 { "(bad)", { XX } },
6290 { "(bad)", { XX } },
6291 { "(bad)", { XX } },
6292 { "(bad)", { XX } },
6293 { "(bad)", { XX } },
6295 { "(bad)", { XX } },
6296 { "(bad)", { XX } },
6297 { "(bad)", { XX } },
6298 { "(bad)", { XX } },
6299 { "(bad)", { XX } },
6300 { "(bad)", { XX } },
6301 { "(bad)", { XX } },
6302 { "(bad)", { XX } },
6304 { "(bad)", { XX } },
6305 { "(bad)", { XX } },
6306 { "(bad)", { XX } },
6307 { "(bad)", { XX } },
6308 { "(bad)", { XX } },
6309 { "(bad)", { XX } },
6310 { "(bad)", { XX } },
6311 { "(bad)", { XX } },
6313 { "(bad)", { XX } },
6314 { "(bad)", { XX } },
6315 { "(bad)", { XX } },
6316 { "(bad)", { XX } },
6317 { "(bad)", { XX } },
6318 { "(bad)", { XX } },
6319 { "(bad)", { XX } },
6320 { "(bad)", { XX } },
6322 { "(bad)", { XX } },
6323 { "(bad)", { XX } },
6324 { "(bad)", { XX } },
6325 { "(bad)", { XX } },
6326 { "(bad)", { XX } },
6327 { "(bad)", { XX } },
6328 { "(bad)", { XX } },
6329 { "(bad)", { XX } },
6331 { "(bad)", { XX } },
6332 { "(bad)", { XX } },
6333 { "(bad)", { XX } },
6334 { "(bad)", { XX } },
6335 { "(bad)", { XX } },
6336 { "(bad)", { XX } },
6337 { "(bad)", { XX } },
6338 { PREFIX_TABLE (PREFIX_0F3ADF) },
6340 { "(bad)", { XX } },
6341 { "(bad)", { XX } },
6342 { "(bad)", { XX } },
6343 { "(bad)", { XX } },
6344 { "(bad)", { XX } },
6345 { "(bad)", { XX } },
6346 { "(bad)", { XX } },
6347 { "(bad)", { XX } },
6349 { "(bad)", { XX } },
6350 { "(bad)", { XX } },
6351 { "(bad)", { XX } },
6352 { "(bad)", { XX } },
6353 { "(bad)", { XX } },
6354 { "(bad)", { XX } },
6355 { "(bad)", { XX } },
6356 { "(bad)", { XX } },
6358 { "(bad)", { XX } },
6359 { "(bad)", { XX } },
6360 { "(bad)", { XX } },
6361 { "(bad)", { XX } },
6362 { "(bad)", { XX } },
6363 { "(bad)", { XX } },
6364 { "(bad)", { XX } },
6365 { "(bad)", { XX } },
6367 { "(bad)", { XX } },
6368 { "(bad)", { XX } },
6369 { "(bad)", { XX } },
6370 { "(bad)", { XX } },
6371 { "(bad)", { XX } },
6372 { "(bad)", { XX } },
6373 { "(bad)", { XX } },
6374 { "(bad)", { XX } },
6376 /* THREE_BYTE_0F7A */
6379 { "(bad)", { XX } },
6380 { "(bad)", { XX } },
6381 { "(bad)", { XX } },
6382 { "(bad)", { XX } },
6383 { "(bad)", { XX } },
6384 { "(bad)", { XX } },
6385 { "(bad)", { XX } },
6386 { "(bad)", { XX } },
6388 { "(bad)", { XX } },
6389 { "(bad)", { XX } },
6390 { "(bad)", { XX } },
6391 { "(bad)", { XX } },
6392 { "(bad)", { XX } },
6393 { "(bad)", { XX } },
6394 { "(bad)", { XX } },
6395 { "(bad)", { XX } },
6397 { "frczps", { XM, EXq } },
6398 { "frczpd", { XM, EXq } },
6399 { "frczss", { XM, EXq } },
6400 { "frczsd", { XM, EXq } },
6401 { "(bad)", { XX } },
6402 { "(bad)", { XX } },
6403 { "(bad)", { XX } },
6404 { "(bad)", { XX } },
6406 { "(bad)", { XX } },
6407 { "(bad)", { XX } },
6408 { "(bad)", { XX } },
6409 { "(bad)", { XX } },
6410 { "(bad)", { XX } },
6411 { "(bad)", { XX } },
6412 { "(bad)", { XX } },
6413 { "(bad)", { XX } },
6415 { "ptest", { XX } },
6416 { "(bad)", { XX } },
6417 { "(bad)", { XX } },
6418 { "(bad)", { XX } },
6419 { "(bad)", { XX } },
6420 { "(bad)", { XX } },
6421 { "(bad)", { XX } },
6422 { "(bad)", { XX } },
6424 { "(bad)", { XX } },
6425 { "(bad)", { XX } },
6426 { "(bad)", { XX } },
6427 { "(bad)", { XX } },
6428 { "(bad)", { XX } },
6429 { "(bad)", { XX } },
6430 { "(bad)", { XX } },
6431 { "(bad)", { XX } },
6433 { "cvtph2ps", { XM, EXd } },
6434 { "cvtps2ph", { EXd, XM } },
6435 { "(bad)", { XX } },
6436 { "(bad)", { XX } },
6437 { "(bad)", { XX } },
6438 { "(bad)", { XX } },
6439 { "(bad)", { XX } },
6440 { "(bad)", { XX } },
6442 { "(bad)", { XX } },
6443 { "(bad)", { XX } },
6444 { "(bad)", { XX } },
6445 { "(bad)", { XX } },
6446 { "(bad)", { XX } },
6447 { "(bad)", { XX } },
6448 { "(bad)", { XX } },
6449 { "(bad)", { XX } },
6451 { "(bad)", { XX } },
6452 { "phaddbw", { XM, EXq } },
6453 { "phaddbd", { XM, EXq } },
6454 { "phaddbq", { XM, EXq } },
6455 { "(bad)", { XX } },
6456 { "(bad)", { XX } },
6457 { "phaddwd", { XM, EXq } },
6458 { "phaddwq", { XM, EXq } },
6460 { "(bad)", { XX } },
6461 { "(bad)", { XX } },
6462 { "(bad)", { XX } },
6463 { "phadddq", { XM, EXq } },
6464 { "(bad)", { XX } },
6465 { "(bad)", { XX } },
6466 { "(bad)", { XX } },
6467 { "(bad)", { XX } },
6469 { "(bad)", { XX } },
6470 { "phaddubw", { XM, EXq } },
6471 { "phaddubd", { XM, EXq } },
6472 { "phaddubq", { XM, EXq } },
6473 { "(bad)", { XX } },
6474 { "(bad)", { XX } },
6475 { "phadduwd", { XM, EXq } },
6476 { "phadduwq", { XM, EXq } },
6478 { "(bad)", { XX } },
6479 { "(bad)", { XX } },
6480 { "(bad)", { XX } },
6481 { "phaddudq", { XM, EXq } },
6482 { "(bad)", { XX } },
6483 { "(bad)", { XX } },
6484 { "(bad)", { XX } },
6485 { "(bad)", { XX } },
6487 { "(bad)", { XX } },
6488 { "phsubbw", { XM, EXq } },
6489 { "phsubbd", { XM, EXq } },
6490 { "phsubbq", { XM, EXq } },
6491 { "(bad)", { XX } },
6492 { "(bad)", { XX } },
6493 { "(bad)", { XX } },
6494 { "(bad)", { XX } },
6496 { "(bad)", { XX } },
6497 { "(bad)", { XX } },
6498 { "(bad)", { XX } },
6499 { "(bad)", { XX } },
6500 { "(bad)", { XX } },
6501 { "(bad)", { XX } },
6502 { "(bad)", { XX } },
6503 { "(bad)", { XX } },
6505 { "(bad)", { XX } },
6506 { "(bad)", { XX } },
6507 { "(bad)", { XX } },
6508 { "(bad)", { XX } },
6509 { "(bad)", { XX } },
6510 { "(bad)", { XX } },
6511 { "(bad)", { XX } },
6512 { "(bad)", { XX } },
6514 { "(bad)", { XX } },
6515 { "(bad)", { XX } },
6516 { "(bad)", { XX } },
6517 { "(bad)", { XX } },
6518 { "(bad)", { XX } },
6519 { "(bad)", { XX } },
6520 { "(bad)", { XX } },
6521 { "(bad)", { XX } },
6523 { "(bad)", { XX } },
6524 { "(bad)", { XX } },
6525 { "(bad)", { XX } },
6526 { "(bad)", { XX } },
6527 { "(bad)", { XX } },
6528 { "(bad)", { XX } },
6529 { "(bad)", { XX } },
6530 { "(bad)", { XX } },
6532 { "(bad)", { XX } },
6533 { "(bad)", { XX } },
6534 { "(bad)", { XX } },
6535 { "(bad)", { XX } },
6536 { "(bad)", { XX } },
6537 { "(bad)", { XX } },
6538 { "(bad)", { XX } },
6539 { "(bad)", { XX } },
6541 { "(bad)", { XX } },
6542 { "(bad)", { XX } },
6543 { "(bad)", { XX } },
6544 { "(bad)", { XX } },
6545 { "(bad)", { XX } },
6546 { "(bad)", { XX } },
6547 { "(bad)", { XX } },
6548 { "(bad)", { XX } },
6550 { "(bad)", { XX } },
6551 { "(bad)", { XX } },
6552 { "(bad)", { XX } },
6553 { "(bad)", { XX } },
6554 { "(bad)", { XX } },
6555 { "(bad)", { XX } },
6556 { "(bad)", { XX } },
6557 { "(bad)", { XX } },
6559 { "(bad)", { XX } },
6560 { "(bad)", { XX } },
6561 { "(bad)", { XX } },
6562 { "(bad)", { XX } },
6563 { "(bad)", { XX } },
6564 { "(bad)", { XX } },
6565 { "(bad)", { XX } },
6566 { "(bad)", { XX } },
6568 { "(bad)", { XX } },
6569 { "(bad)", { XX } },
6570 { "(bad)", { XX } },
6571 { "(bad)", { XX } },
6572 { "(bad)", { XX } },
6573 { "(bad)", { XX } },
6574 { "(bad)", { XX } },
6575 { "(bad)", { XX } },
6577 { "(bad)", { XX } },
6578 { "(bad)", { XX } },
6579 { "(bad)", { XX } },
6580 { "(bad)", { XX } },
6581 { "(bad)", { XX } },
6582 { "(bad)", { XX } },
6583 { "(bad)", { XX } },
6584 { "(bad)", { XX } },
6586 { "(bad)", { XX } },
6587 { "(bad)", { XX } },
6588 { "(bad)", { XX } },
6589 { "(bad)", { XX } },
6590 { "(bad)", { XX } },
6591 { "(bad)", { XX } },
6592 { "(bad)", { XX } },
6593 { "(bad)", { XX } },
6595 { "(bad)", { XX } },
6596 { "(bad)", { XX } },
6597 { "(bad)", { XX } },
6598 { "(bad)", { XX } },
6599 { "(bad)", { XX } },
6600 { "(bad)", { XX } },
6601 { "(bad)", { XX } },
6602 { "(bad)", { XX } },
6604 { "(bad)", { XX } },
6605 { "(bad)", { XX } },
6606 { "(bad)", { XX } },
6607 { "(bad)", { XX } },
6608 { "(bad)", { XX } },
6609 { "(bad)", { XX } },
6610 { "(bad)", { XX } },
6611 { "(bad)", { XX } },
6613 { "(bad)", { XX } },
6614 { "(bad)", { XX } },
6615 { "(bad)", { XX } },
6616 { "(bad)", { XX } },
6617 { "(bad)", { XX } },
6618 { "(bad)", { XX } },
6619 { "(bad)", { XX } },
6620 { "(bad)", { XX } },
6622 { "(bad)", { XX } },
6623 { "(bad)", { XX } },
6624 { "(bad)", { XX } },
6625 { "(bad)", { XX } },
6626 { "(bad)", { XX } },
6627 { "(bad)", { XX } },
6628 { "(bad)", { XX } },
6629 { "(bad)", { XX } },
6631 { "(bad)", { XX } },
6632 { "(bad)", { XX } },
6633 { "(bad)", { XX } },
6634 { "(bad)", { XX } },
6635 { "(bad)", { XX } },
6636 { "(bad)", { XX } },
6637 { "(bad)", { XX } },
6638 { "(bad)", { XX } },
6640 { "(bad)", { XX } },
6641 { "(bad)", { XX } },
6642 { "(bad)", { XX } },
6643 { "(bad)", { XX } },
6644 { "(bad)", { XX } },
6645 { "(bad)", { XX } },
6646 { "(bad)", { XX } },
6647 { "(bad)", { XX } },
6649 { "(bad)", { XX } },
6650 { "(bad)", { XX } },
6651 { "(bad)", { XX } },
6652 { "(bad)", { XX } },
6653 { "(bad)", { XX } },
6654 { "(bad)", { XX } },
6655 { "(bad)", { XX } },
6656 { "(bad)", { XX } },
6658 { "(bad)", { XX } },
6659 { "(bad)", { XX } },
6660 { "(bad)", { XX } },
6661 { "(bad)", { XX } },
6662 { "(bad)", { XX } },
6663 { "(bad)", { XX } },
6664 { "(bad)", { XX } },
6665 { "(bad)", { XX } },
6667 /* THREE_BYTE_0F7B */
6670 { "(bad)", { XX } },
6671 { "(bad)", { XX } },
6672 { "(bad)", { XX } },
6673 { "(bad)", { XX } },
6674 { "(bad)", { XX } },
6675 { "(bad)", { XX } },
6676 { "(bad)", { XX } },
6677 { "(bad)", { XX } },
6679 { "(bad)", { XX } },
6680 { "(bad)", { XX } },
6681 { "(bad)", { XX } },
6682 { "(bad)", { XX } },
6683 { "(bad)", { XX } },
6684 { "(bad)", { XX } },
6685 { "(bad)", { XX } },
6686 { "(bad)", { XX } },
6688 { "(bad)", { XX } },
6689 { "(bad)", { XX } },
6690 { "(bad)", { XX } },
6691 { "(bad)", { XX } },
6692 { "(bad)", { XX } },
6693 { "(bad)", { XX } },
6694 { "(bad)", { XX } },
6695 { "(bad)", { XX } },
6697 { "(bad)", { XX } },
6698 { "(bad)", { XX } },
6699 { "(bad)", { XX } },
6700 { "(bad)", { XX } },
6701 { "(bad)", { XX } },
6702 { "(bad)", { XX } },
6703 { "(bad)", { XX } },
6704 { "(bad)", { XX } },
6706 { "(bad)", { XX } },
6707 { "(bad)", { XX } },
6708 { "(bad)", { XX } },
6709 { "(bad)", { XX } },
6710 { "(bad)", { XX } },
6711 { "(bad)", { XX } },
6712 { "(bad)", { XX } },
6713 { "(bad)", { XX } },
6715 { "(bad)", { XX } },
6716 { "(bad)", { XX } },
6717 { "(bad)", { XX } },
6718 { "(bad)", { XX } },
6719 { "(bad)", { XX } },
6720 { "(bad)", { XX } },
6721 { "(bad)", { XX } },
6722 { "(bad)", { XX } },
6724 { "(bad)", { XX } },
6725 { "(bad)", { XX } },
6726 { "(bad)", { XX } },
6727 { "(bad)", { XX } },
6728 { "(bad)", { XX } },
6729 { "(bad)", { XX } },
6730 { "(bad)", { XX } },
6731 { "(bad)", { XX } },
6733 { "(bad)", { XX } },
6734 { "(bad)", { XX } },
6735 { "(bad)", { XX } },
6736 { "(bad)", { XX } },
6737 { "(bad)", { XX } },
6738 { "(bad)", { XX } },
6739 { "(bad)", { XX } },
6740 { "(bad)", { XX } },
6742 { "protb", { XM, EXq, Ib } },
6743 { "protw", { XM, EXq, Ib } },
6744 { "protd", { XM, EXq, Ib } },
6745 { "protq", { XM, EXq, Ib } },
6746 { "pshlb", { XM, EXq, Ib } },
6747 { "pshlw", { XM, EXq, Ib } },
6748 { "pshld", { XM, EXq, Ib } },
6749 { "pshlq", { XM, EXq, Ib } },
6751 { "pshab", { XM, EXq, Ib } },
6752 { "pshaw", { XM, EXq, Ib } },
6753 { "pshad", { XM, EXq, Ib } },
6754 { "pshaq", { XM, EXq, Ib } },
6755 { "(bad)", { XX } },
6756 { "(bad)", { XX } },
6757 { "(bad)", { XX } },
6758 { "(bad)", { XX } },
6760 { "(bad)", { XX } },
6761 { "(bad)", { XX } },
6762 { "(bad)", { XX } },
6763 { "(bad)", { XX } },
6764 { "(bad)", { XX } },
6765 { "(bad)", { XX } },
6766 { "(bad)", { XX } },
6767 { "(bad)", { XX } },
6769 { "(bad)", { XX } },
6770 { "(bad)", { XX } },
6771 { "(bad)", { XX } },
6772 { "(bad)", { XX } },
6773 { "(bad)", { XX } },
6774 { "(bad)", { XX } },
6775 { "(bad)", { XX } },
6776 { "(bad)", { XX } },
6778 { "(bad)", { XX } },
6779 { "(bad)", { XX } },
6780 { "(bad)", { XX } },
6781 { "(bad)", { XX } },
6782 { "(bad)", { XX } },
6783 { "(bad)", { XX } },
6784 { "(bad)", { XX } },
6785 { "(bad)", { XX } },
6787 { "(bad)", { XX } },
6788 { "(bad)", { XX } },
6789 { "(bad)", { XX } },
6790 { "(bad)", { XX } },
6791 { "(bad)", { XX } },
6792 { "(bad)", { XX } },
6793 { "(bad)", { XX } },
6794 { "(bad)", { XX } },
6796 { "(bad)", { XX } },
6797 { "(bad)", { XX } },
6798 { "(bad)", { XX } },
6799 { "(bad)", { XX } },
6800 { "(bad)", { XX } },
6801 { "(bad)", { XX } },
6802 { "(bad)", { XX } },
6803 { "(bad)", { XX } },
6805 { "(bad)", { XX } },
6806 { "(bad)", { XX } },
6807 { "(bad)", { XX } },
6808 { "(bad)", { XX } },
6809 { "(bad)", { XX } },
6810 { "(bad)", { XX } },
6811 { "(bad)", { XX } },
6812 { "(bad)", { XX } },
6814 { "(bad)", { XX } },
6815 { "(bad)", { XX } },
6816 { "(bad)", { XX } },
6817 { "(bad)", { XX } },
6818 { "(bad)", { XX } },
6819 { "(bad)", { XX } },
6820 { "(bad)", { XX } },
6821 { "(bad)", { XX } },
6823 { "(bad)", { XX } },
6824 { "(bad)", { XX } },
6825 { "(bad)", { XX } },
6826 { "(bad)", { XX } },
6827 { "(bad)", { XX } },
6828 { "(bad)", { XX } },
6829 { "(bad)", { XX } },
6830 { "(bad)", { XX } },
6832 { "(bad)", { XX } },
6833 { "(bad)", { XX } },
6834 { "(bad)", { XX } },
6835 { "(bad)", { XX } },
6836 { "(bad)", { XX } },
6837 { "(bad)", { XX } },
6838 { "(bad)", { XX } },
6839 { "(bad)", { XX } },
6841 { "(bad)", { XX } },
6842 { "(bad)", { XX } },
6843 { "(bad)", { XX } },
6844 { "(bad)", { XX } },
6845 { "(bad)", { XX } },
6846 { "(bad)", { XX } },
6847 { "(bad)", { XX } },
6848 { "(bad)", { XX } },
6850 { "(bad)", { XX } },
6851 { "(bad)", { XX } },
6852 { "(bad)", { XX } },
6853 { "(bad)", { XX } },
6854 { "(bad)", { XX } },
6855 { "(bad)", { XX } },
6856 { "(bad)", { XX } },
6857 { "(bad)", { XX } },
6859 { "(bad)", { XX } },
6860 { "(bad)", { XX } },
6861 { "(bad)", { XX } },
6862 { "(bad)", { XX } },
6863 { "(bad)", { XX } },
6864 { "(bad)", { XX } },
6865 { "(bad)", { XX } },
6866 { "(bad)", { XX } },
6868 { "(bad)", { XX } },
6869 { "(bad)", { XX } },
6870 { "(bad)", { XX } },
6871 { "(bad)", { XX } },
6872 { "(bad)", { XX } },
6873 { "(bad)", { XX } },
6874 { "(bad)", { XX } },
6875 { "(bad)", { XX } },
6877 { "(bad)", { XX } },
6878 { "(bad)", { XX } },
6879 { "(bad)", { XX } },
6880 { "(bad)", { XX } },
6881 { "(bad)", { XX } },
6882 { "(bad)", { XX } },
6883 { "(bad)", { XX } },
6884 { "(bad)", { XX } },
6886 { "(bad)", { XX } },
6887 { "(bad)", { XX } },
6888 { "(bad)", { XX } },
6889 { "(bad)", { XX } },
6890 { "(bad)", { XX } },
6891 { "(bad)", { XX } },
6892 { "(bad)", { XX } },
6893 { "(bad)", { XX } },
6895 { "(bad)", { XX } },
6896 { "(bad)", { XX } },
6897 { "(bad)", { XX } },
6898 { "(bad)", { XX } },
6899 { "(bad)", { XX } },
6900 { "(bad)", { XX } },
6901 { "(bad)", { XX } },
6902 { "(bad)", { XX } },
6904 { "(bad)", { XX } },
6905 { "(bad)", { XX } },
6906 { "(bad)", { XX } },
6907 { "(bad)", { XX } },
6908 { "(bad)", { XX } },
6909 { "(bad)", { XX } },
6910 { "(bad)", { XX } },
6911 { "(bad)", { XX } },
6913 { "(bad)", { XX } },
6914 { "(bad)", { XX } },
6915 { "(bad)", { XX } },
6916 { "(bad)", { XX } },
6917 { "(bad)", { XX } },
6918 { "(bad)", { XX } },
6919 { "(bad)", { XX } },
6920 { "(bad)", { XX } },
6922 { "(bad)", { XX } },
6923 { "(bad)", { XX } },
6924 { "(bad)", { XX } },
6925 { "(bad)", { XX } },
6926 { "(bad)", { XX } },
6927 { "(bad)", { XX } },
6928 { "(bad)", { XX } },
6929 { "(bad)", { XX } },
6931 { "(bad)", { XX } },
6932 { "(bad)", { XX } },
6933 { "(bad)", { XX } },
6934 { "(bad)", { XX } },
6935 { "(bad)", { XX } },
6936 { "(bad)", { XX } },
6937 { "(bad)", { XX } },
6938 { "(bad)", { XX } },
6940 { "(bad)", { XX } },
6941 { "(bad)", { XX } },
6942 { "(bad)", { XX } },
6943 { "(bad)", { XX } },
6944 { "(bad)", { XX } },
6945 { "(bad)", { XX } },
6946 { "(bad)", { XX } },
6947 { "(bad)", { XX } },
6949 { "(bad)", { XX } },
6950 { "(bad)", { XX } },
6951 { "(bad)", { XX } },
6952 { "(bad)", { XX } },
6953 { "(bad)", { XX } },
6954 { "(bad)", { XX } },
6955 { "(bad)", { XX } },
6956 { "(bad)", { XX } },
6960 static const struct dis386 vex_table[][256] = {
6964 { "(bad)", { XX } },
6965 { "(bad)", { XX } },
6966 { "(bad)", { XX } },
6967 { "(bad)", { XX } },
6968 { "(bad)", { XX } },
6969 { "(bad)", { XX } },
6970 { "(bad)", { XX } },
6971 { "(bad)", { XX } },
6973 { "(bad)", { XX } },
6974 { "(bad)", { XX } },
6975 { "(bad)", { XX } },
6976 { "(bad)", { XX } },
6977 { "(bad)", { XX } },
6978 { "(bad)", { XX } },
6979 { "(bad)", { XX } },
6980 { "(bad)", { XX } },
6982 { PREFIX_TABLE (PREFIX_VEX_10) },
6983 { PREFIX_TABLE (PREFIX_VEX_11) },
6984 { PREFIX_TABLE (PREFIX_VEX_12) },
6985 { MOD_TABLE (MOD_VEX_13) },
6986 { "vunpcklpX", { XM, Vex, EXx } },
6987 { "vunpckhpX", { XM, Vex, EXx } },
6988 { PREFIX_TABLE (PREFIX_VEX_16) },
6989 { MOD_TABLE (MOD_VEX_17) },
6991 { "(bad)", { XX } },
6992 { "(bad)", { XX } },
6993 { "(bad)", { XX } },
6994 { "(bad)", { XX } },
6995 { "(bad)", { XX } },
6996 { "(bad)", { XX } },
6997 { "(bad)", { XX } },
6998 { "(bad)", { XX } },
7000 { "(bad)", { XX } },
7001 { "(bad)", { XX } },
7002 { "(bad)", { XX } },
7003 { "(bad)", { XX } },
7004 { "(bad)", { XX } },
7005 { "(bad)", { XX } },
7006 { "(bad)", { XX } },
7007 { "(bad)", { XX } },
7009 { "vmovapX", { XM, EXx } },
7010 { "vmovapX", { EXxS, XM } },
7011 { PREFIX_TABLE (PREFIX_VEX_2A) },
7012 { MOD_TABLE (MOD_VEX_2B) },
7013 { PREFIX_TABLE (PREFIX_VEX_2C) },
7014 { PREFIX_TABLE (PREFIX_VEX_2D) },
7015 { PREFIX_TABLE (PREFIX_VEX_2E) },
7016 { PREFIX_TABLE (PREFIX_VEX_2F) },
7018 { "(bad)", { XX } },
7019 { "(bad)", { XX } },
7020 { "(bad)", { XX } },
7021 { "(bad)", { XX } },
7022 { "(bad)", { XX } },
7023 { "(bad)", { XX } },
7024 { "(bad)", { XX } },
7025 { "(bad)", { XX } },
7027 { "(bad)", { XX } },
7028 { "(bad)", { XX } },
7029 { "(bad)", { XX } },
7030 { "(bad)", { XX } },
7031 { "(bad)", { XX } },
7032 { "(bad)", { XX } },
7033 { "(bad)", { XX } },
7034 { "(bad)", { XX } },
7036 { "(bad)", { XX } },
7037 { "(bad)", { XX } },
7038 { "(bad)", { XX } },
7039 { "(bad)", { XX } },
7040 { "(bad)", { XX } },
7041 { "(bad)", { XX } },
7042 { "(bad)", { XX } },
7043 { "(bad)", { XX } },
7045 { "(bad)", { XX } },
7046 { "(bad)", { XX } },
7047 { "(bad)", { XX } },
7048 { "(bad)", { XX } },
7049 { "(bad)", { XX } },
7050 { "(bad)", { XX } },
7051 { "(bad)", { XX } },
7052 { "(bad)", { XX } },
7054 { MOD_TABLE (MOD_VEX_51) },
7055 { PREFIX_TABLE (PREFIX_VEX_51) },
7056 { PREFIX_TABLE (PREFIX_VEX_52) },
7057 { PREFIX_TABLE (PREFIX_VEX_53) },
7058 { "vandpX", { XM, Vex, EXx } },
7059 { "vandnpX", { XM, Vex, EXx } },
7060 { "vorpX", { XM, Vex, EXx } },
7061 { "vxorpX", { XM, Vex, EXx } },
7063 { PREFIX_TABLE (PREFIX_VEX_58) },
7064 { PREFIX_TABLE (PREFIX_VEX_59) },
7065 { PREFIX_TABLE (PREFIX_VEX_5A) },
7066 { PREFIX_TABLE (PREFIX_VEX_5B) },
7067 { PREFIX_TABLE (PREFIX_VEX_5C) },
7068 { PREFIX_TABLE (PREFIX_VEX_5D) },
7069 { PREFIX_TABLE (PREFIX_VEX_5E) },
7070 { PREFIX_TABLE (PREFIX_VEX_5F) },
7072 { PREFIX_TABLE (PREFIX_VEX_60) },
7073 { PREFIX_TABLE (PREFIX_VEX_61) },
7074 { PREFIX_TABLE (PREFIX_VEX_62) },
7075 { PREFIX_TABLE (PREFIX_VEX_63) },
7076 { PREFIX_TABLE (PREFIX_VEX_64) },
7077 { PREFIX_TABLE (PREFIX_VEX_65) },
7078 { PREFIX_TABLE (PREFIX_VEX_66) },
7079 { PREFIX_TABLE (PREFIX_VEX_67) },
7081 { PREFIX_TABLE (PREFIX_VEX_68) },
7082 { PREFIX_TABLE (PREFIX_VEX_69) },
7083 { PREFIX_TABLE (PREFIX_VEX_6A) },
7084 { PREFIX_TABLE (PREFIX_VEX_6B) },
7085 { PREFIX_TABLE (PREFIX_VEX_6C) },
7086 { PREFIX_TABLE (PREFIX_VEX_6D) },
7087 { PREFIX_TABLE (PREFIX_VEX_6E) },
7088 { PREFIX_TABLE (PREFIX_VEX_6F) },
7090 { PREFIX_TABLE (PREFIX_VEX_70) },
7091 { REG_TABLE (REG_VEX_71) },
7092 { REG_TABLE (REG_VEX_72) },
7093 { REG_TABLE (REG_VEX_73) },
7094 { PREFIX_TABLE (PREFIX_VEX_74) },
7095 { PREFIX_TABLE (PREFIX_VEX_75) },
7096 { PREFIX_TABLE (PREFIX_VEX_76) },
7097 { PREFIX_TABLE (PREFIX_VEX_77) },
7099 { "(bad)", { XX } },
7100 { "(bad)", { XX } },
7101 { "(bad)", { XX } },
7102 { "(bad)", { XX } },
7103 { PREFIX_TABLE (PREFIX_VEX_7C) },
7104 { PREFIX_TABLE (PREFIX_VEX_7D) },
7105 { PREFIX_TABLE (PREFIX_VEX_7E) },
7106 { PREFIX_TABLE (PREFIX_VEX_7F) },
7108 { "(bad)", { XX } },
7109 { "(bad)", { XX } },
7110 { "(bad)", { XX } },
7111 { "(bad)", { XX } },
7112 { "(bad)", { XX } },
7113 { "(bad)", { XX } },
7114 { "(bad)", { XX } },
7115 { "(bad)", { XX } },
7117 { "(bad)", { XX } },
7118 { "(bad)", { XX } },
7119 { "(bad)", { XX } },
7120 { "(bad)", { XX } },
7121 { "(bad)", { XX } },
7122 { "(bad)", { XX } },
7123 { "(bad)", { XX } },
7124 { "(bad)", { XX } },
7126 { "(bad)", { XX } },
7127 { "(bad)", { XX } },
7128 { "(bad)", { XX } },
7129 { "(bad)", { XX } },
7130 { "(bad)", { XX } },
7131 { "(bad)", { XX } },
7132 { "(bad)", { XX } },
7133 { "(bad)", { XX } },
7135 { "(bad)", { XX } },
7136 { "(bad)", { XX } },
7137 { "(bad)", { XX } },
7138 { "(bad)", { XX } },
7139 { "(bad)", { XX } },
7140 { "(bad)", { XX } },
7141 { "(bad)", { XX } },
7142 { "(bad)", { XX } },
7144 { "(bad)", { XX } },
7145 { "(bad)", { XX } },
7146 { "(bad)", { XX } },
7147 { "(bad)", { XX } },
7148 { "(bad)", { XX } },
7149 { "(bad)", { XX } },
7150 { "(bad)", { XX } },
7151 { "(bad)", { XX } },
7153 { "(bad)", { XX } },
7154 { "(bad)", { XX } },
7155 { "(bad)", { XX } },
7156 { "(bad)", { XX } },
7157 { "(bad)", { XX } },
7158 { "(bad)", { XX } },
7159 { REG_TABLE (REG_VEX_AE) },
7160 { "(bad)", { XX } },
7162 { "(bad)", { XX } },
7163 { "(bad)", { XX } },
7164 { "(bad)", { XX } },
7165 { "(bad)", { XX } },
7166 { "(bad)", { XX } },
7167 { "(bad)", { XX } },
7168 { "(bad)", { XX } },
7169 { "(bad)", { XX } },
7171 { "(bad)", { XX } },
7172 { "(bad)", { XX } },
7173 { "(bad)", { XX } },
7174 { "(bad)", { XX } },
7175 { "(bad)", { XX } },
7176 { "(bad)", { XX } },
7177 { "(bad)", { XX } },
7178 { "(bad)", { XX } },
7180 { "(bad)", { XX } },
7181 { "(bad)", { XX } },
7182 { PREFIX_TABLE (PREFIX_VEX_C2) },
7183 { "(bad)", { XX } },
7184 { PREFIX_TABLE (PREFIX_VEX_C4) },
7185 { PREFIX_TABLE (PREFIX_VEX_C5) },
7186 { "vshufpX", { XM, Vex, EXx, Ib } },
7187 { "(bad)", { XX } },
7189 { "(bad)", { XX } },
7190 { "(bad)", { XX } },
7191 { "(bad)", { XX } },
7192 { "(bad)", { XX } },
7193 { "(bad)", { XX } },
7194 { "(bad)", { XX } },
7195 { "(bad)", { XX } },
7196 { "(bad)", { XX } },
7198 { PREFIX_TABLE (PREFIX_VEX_D0) },
7199 { PREFIX_TABLE (PREFIX_VEX_D1) },
7200 { PREFIX_TABLE (PREFIX_VEX_D2) },
7201 { PREFIX_TABLE (PREFIX_VEX_D3) },
7202 { PREFIX_TABLE (PREFIX_VEX_D4) },
7203 { PREFIX_TABLE (PREFIX_VEX_D5) },
7204 { PREFIX_TABLE (PREFIX_VEX_D6) },
7205 { PREFIX_TABLE (PREFIX_VEX_D7) },
7207 { PREFIX_TABLE (PREFIX_VEX_D8) },
7208 { PREFIX_TABLE (PREFIX_VEX_D9) },
7209 { PREFIX_TABLE (PREFIX_VEX_DA) },
7210 { PREFIX_TABLE (PREFIX_VEX_DB) },
7211 { PREFIX_TABLE (PREFIX_VEX_DC) },
7212 { PREFIX_TABLE (PREFIX_VEX_DD) },
7213 { PREFIX_TABLE (PREFIX_VEX_DE) },
7214 { PREFIX_TABLE (PREFIX_VEX_DF) },
7216 { PREFIX_TABLE (PREFIX_VEX_E0) },
7217 { PREFIX_TABLE (PREFIX_VEX_E1) },
7218 { PREFIX_TABLE (PREFIX_VEX_E2) },
7219 { PREFIX_TABLE (PREFIX_VEX_E3) },
7220 { PREFIX_TABLE (PREFIX_VEX_E4) },
7221 { PREFIX_TABLE (PREFIX_VEX_E5) },
7222 { PREFIX_TABLE (PREFIX_VEX_E6) },
7223 { PREFIX_TABLE (PREFIX_VEX_E7) },
7225 { PREFIX_TABLE (PREFIX_VEX_E8) },
7226 { PREFIX_TABLE (PREFIX_VEX_E9) },
7227 { PREFIX_TABLE (PREFIX_VEX_EA) },
7228 { PREFIX_TABLE (PREFIX_VEX_EB) },
7229 { PREFIX_TABLE (PREFIX_VEX_EC) },
7230 { PREFIX_TABLE (PREFIX_VEX_ED) },
7231 { PREFIX_TABLE (PREFIX_VEX_EE) },
7232 { PREFIX_TABLE (PREFIX_VEX_EF) },
7234 { PREFIX_TABLE (PREFIX_VEX_F0) },
7235 { PREFIX_TABLE (PREFIX_VEX_F1) },
7236 { PREFIX_TABLE (PREFIX_VEX_F2) },
7237 { PREFIX_TABLE (PREFIX_VEX_F3) },
7238 { PREFIX_TABLE (PREFIX_VEX_F4) },
7239 { PREFIX_TABLE (PREFIX_VEX_F5) },
7240 { PREFIX_TABLE (PREFIX_VEX_F6) },
7241 { PREFIX_TABLE (PREFIX_VEX_F7) },
7243 { PREFIX_TABLE (PREFIX_VEX_F8) },
7244 { PREFIX_TABLE (PREFIX_VEX_F9) },
7245 { PREFIX_TABLE (PREFIX_VEX_FA) },
7246 { PREFIX_TABLE (PREFIX_VEX_FB) },
7247 { PREFIX_TABLE (PREFIX_VEX_FC) },
7248 { PREFIX_TABLE (PREFIX_VEX_FD) },
7249 { PREFIX_TABLE (PREFIX_VEX_FE) },
7250 { "(bad)", { XX } },
7255 { PREFIX_TABLE (PREFIX_VEX_3800) },
7256 { PREFIX_TABLE (PREFIX_VEX_3801) },
7257 { PREFIX_TABLE (PREFIX_VEX_3802) },
7258 { PREFIX_TABLE (PREFIX_VEX_3803) },
7259 { PREFIX_TABLE (PREFIX_VEX_3804) },
7260 { PREFIX_TABLE (PREFIX_VEX_3805) },
7261 { PREFIX_TABLE (PREFIX_VEX_3806) },
7262 { PREFIX_TABLE (PREFIX_VEX_3807) },
7264 { PREFIX_TABLE (PREFIX_VEX_3808) },
7265 { PREFIX_TABLE (PREFIX_VEX_3809) },
7266 { PREFIX_TABLE (PREFIX_VEX_380A) },
7267 { PREFIX_TABLE (PREFIX_VEX_380B) },
7268 { PREFIX_TABLE (PREFIX_VEX_380C) },
7269 { PREFIX_TABLE (PREFIX_VEX_380D) },
7270 { PREFIX_TABLE (PREFIX_VEX_380E) },
7271 { PREFIX_TABLE (PREFIX_VEX_380F) },
7273 { "(bad)", { XX } },
7274 { "(bad)", { XX } },
7275 { "(bad)", { XX } },
7276 { "(bad)", { XX } },
7277 { "(bad)", { XX } },
7278 { "(bad)", { XX } },
7279 { "(bad)", { XX } },
7280 { PREFIX_TABLE (PREFIX_VEX_3817) },
7282 { PREFIX_TABLE (PREFIX_VEX_3818) },
7283 { PREFIX_TABLE (PREFIX_VEX_3819) },
7284 { PREFIX_TABLE (PREFIX_VEX_381A) },
7285 { "(bad)", { XX } },
7286 { PREFIX_TABLE (PREFIX_VEX_381C) },
7287 { PREFIX_TABLE (PREFIX_VEX_381D) },
7288 { PREFIX_TABLE (PREFIX_VEX_381E) },
7289 { "(bad)", { XX } },
7291 { PREFIX_TABLE (PREFIX_VEX_3820) },
7292 { PREFIX_TABLE (PREFIX_VEX_3821) },
7293 { PREFIX_TABLE (PREFIX_VEX_3822) },
7294 { PREFIX_TABLE (PREFIX_VEX_3823) },
7295 { PREFIX_TABLE (PREFIX_VEX_3824) },
7296 { PREFIX_TABLE (PREFIX_VEX_3825) },
7297 { "(bad)", { XX } },
7298 { "(bad)", { XX } },
7300 { PREFIX_TABLE (PREFIX_VEX_3828) },
7301 { PREFIX_TABLE (PREFIX_VEX_3829) },
7302 { PREFIX_TABLE (PREFIX_VEX_382A) },
7303 { PREFIX_TABLE (PREFIX_VEX_382B) },
7304 { PREFIX_TABLE (PREFIX_VEX_382C) },
7305 { PREFIX_TABLE (PREFIX_VEX_382D) },
7306 { PREFIX_TABLE (PREFIX_VEX_382E) },
7307 { PREFIX_TABLE (PREFIX_VEX_382F) },
7309 { PREFIX_TABLE (PREFIX_VEX_3830) },
7310 { PREFIX_TABLE (PREFIX_VEX_3831) },
7311 { PREFIX_TABLE (PREFIX_VEX_3832) },
7312 { PREFIX_TABLE (PREFIX_VEX_3833) },
7313 { PREFIX_TABLE (PREFIX_VEX_3834) },
7314 { PREFIX_TABLE (PREFIX_VEX_3835) },
7315 { "(bad)", { XX } },
7316 { PREFIX_TABLE (PREFIX_VEX_3837) },
7318 { PREFIX_TABLE (PREFIX_VEX_3838) },
7319 { PREFIX_TABLE (PREFIX_VEX_3839) },
7320 { PREFIX_TABLE (PREFIX_VEX_383A) },
7321 { PREFIX_TABLE (PREFIX_VEX_383B) },
7322 { PREFIX_TABLE (PREFIX_VEX_383C) },
7323 { PREFIX_TABLE (PREFIX_VEX_383D) },
7324 { PREFIX_TABLE (PREFIX_VEX_383E) },
7325 { PREFIX_TABLE (PREFIX_VEX_383F) },
7327 { PREFIX_TABLE (PREFIX_VEX_3840) },
7328 { PREFIX_TABLE (PREFIX_VEX_3841) },
7329 { "(bad)", { XX } },
7330 { "(bad)", { XX } },
7331 { "(bad)", { XX } },
7332 { "(bad)", { XX } },
7333 { "(bad)", { XX } },
7334 { "(bad)", { XX } },
7336 { "(bad)", { XX } },
7337 { "(bad)", { XX } },
7338 { "(bad)", { XX } },
7339 { "(bad)", { XX } },
7340 { "(bad)", { XX } },
7341 { "(bad)", { XX } },
7342 { "(bad)", { XX } },
7343 { "(bad)", { XX } },
7345 { "(bad)", { XX } },
7346 { "(bad)", { XX } },
7347 { "(bad)", { XX } },
7348 { "(bad)", { XX } },
7349 { "(bad)", { XX } },
7350 { "(bad)", { XX } },
7351 { "(bad)", { XX } },
7352 { "(bad)", { XX } },
7354 { "(bad)", { XX } },
7355 { "(bad)", { XX } },
7356 { "(bad)", { XX } },
7357 { "(bad)", { XX } },
7358 { "(bad)", { XX } },
7359 { "(bad)", { XX } },
7360 { "(bad)", { XX } },
7361 { "(bad)", { XX } },
7363 { "(bad)", { XX } },
7364 { "(bad)", { XX } },
7365 { "(bad)", { XX } },
7366 { "(bad)", { XX } },
7367 { "(bad)", { XX } },
7368 { "(bad)", { XX } },
7369 { "(bad)", { XX } },
7370 { "(bad)", { XX } },
7372 { "(bad)", { XX } },
7373 { "(bad)", { XX } },
7374 { "(bad)", { XX } },
7375 { "(bad)", { XX } },
7376 { "(bad)", { XX } },
7377 { "(bad)", { XX } },
7378 { "(bad)", { XX } },
7379 { "(bad)", { XX } },
7381 { "(bad)", { XX } },
7382 { "(bad)", { XX } },
7383 { "(bad)", { XX } },
7384 { "(bad)", { XX } },
7385 { "(bad)", { XX } },
7386 { "(bad)", { XX } },
7387 { "(bad)", { XX } },
7388 { "(bad)", { XX } },
7390 { "(bad)", { XX } },
7391 { "(bad)", { XX } },
7392 { "(bad)", { XX } },
7393 { "(bad)", { XX } },
7394 { "(bad)", { XX } },
7395 { "(bad)", { XX } },
7396 { "(bad)", { XX } },
7397 { "(bad)", { XX } },
7399 { "(bad)", { XX } },
7400 { "(bad)", { XX } },
7401 { "(bad)", { XX } },
7402 { "(bad)", { XX } },
7403 { "(bad)", { XX } },
7404 { "(bad)", { XX } },
7405 { "(bad)", { XX } },
7406 { "(bad)", { XX } },
7408 { "(bad)", { XX } },
7409 { "(bad)", { XX } },
7410 { "(bad)", { XX } },
7411 { "(bad)", { XX } },
7412 { "(bad)", { XX } },
7413 { "(bad)", { XX } },
7414 { "(bad)", { XX } },
7415 { "(bad)", { XX } },
7417 { "(bad)", { XX } },
7418 { "(bad)", { XX } },
7419 { "(bad)", { XX } },
7420 { "(bad)", { XX } },
7421 { "(bad)", { XX } },
7422 { "(bad)", { XX } },
7423 { "(bad)", { XX } },
7424 { "(bad)", { XX } },
7426 { "(bad)", { XX } },
7427 { "(bad)", { XX } },
7428 { "(bad)", { XX } },
7429 { "(bad)", { XX } },
7430 { "(bad)", { XX } },
7431 { "(bad)", { XX } },
7432 { "(bad)", { XX } },
7433 { "(bad)", { XX } },
7435 { "(bad)", { XX } },
7436 { "(bad)", { XX } },
7437 { "(bad)", { XX } },
7438 { "(bad)", { XX } },
7439 { "(bad)", { XX } },
7440 { "(bad)", { XX } },
7441 { "(bad)", { XX } },
7442 { "(bad)", { XX } },
7444 { "(bad)", { XX } },
7445 { "(bad)", { XX } },
7446 { "(bad)", { XX } },
7447 { "(bad)", { XX } },
7448 { "(bad)", { XX } },
7449 { "(bad)", { XX } },
7450 { "(bad)", { XX } },
7451 { "(bad)", { XX } },
7453 { "(bad)", { XX } },
7454 { "(bad)", { XX } },
7455 { "(bad)", { XX } },
7456 { "(bad)", { XX } },
7457 { "(bad)", { XX } },
7458 { "(bad)", { XX } },
7459 { "(bad)", { XX } },
7460 { "(bad)", { XX } },
7462 { "(bad)", { XX } },
7463 { "(bad)", { XX } },
7464 { "(bad)", { XX } },
7465 { "(bad)", { XX } },
7466 { "(bad)", { XX } },
7467 { "(bad)", { XX } },
7468 { "(bad)", { XX } },
7469 { "(bad)", { XX } },
7471 { "(bad)", { XX } },
7472 { "(bad)", { XX } },
7473 { "(bad)", { XX } },
7474 { "(bad)", { XX } },
7475 { "(bad)", { XX } },
7476 { "(bad)", { XX } },
7477 { "(bad)", { XX } },
7478 { "(bad)", { XX } },
7480 { "(bad)", { XX } },
7481 { "(bad)", { XX } },
7482 { "(bad)", { XX } },
7483 { "(bad)", { XX } },
7484 { "(bad)", { XX } },
7485 { "(bad)", { XX } },
7486 { "(bad)", { XX } },
7487 { "(bad)", { XX } },
7489 { "(bad)", { XX } },
7490 { "(bad)", { XX } },
7491 { "(bad)", { XX } },
7492 { "(bad)", { XX } },
7493 { "(bad)", { XX } },
7494 { "(bad)", { XX } },
7495 { "(bad)", { XX } },
7496 { "(bad)", { XX } },
7498 { "(bad)", { XX } },
7499 { "(bad)", { XX } },
7500 { "(bad)", { XX } },
7501 { PREFIX_TABLE (PREFIX_VEX_38DB) },
7502 { PREFIX_TABLE (PREFIX_VEX_38DC) },
7503 { PREFIX_TABLE (PREFIX_VEX_38DD) },
7504 { PREFIX_TABLE (PREFIX_VEX_38DE) },
7505 { PREFIX_TABLE (PREFIX_VEX_38DF) },
7507 { "(bad)", { XX } },
7508 { "(bad)", { XX } },
7509 { "(bad)", { XX } },
7510 { "(bad)", { XX } },
7511 { "(bad)", { XX } },
7512 { "(bad)", { XX } },
7513 { "(bad)", { XX } },
7514 { "(bad)", { XX } },
7516 { "(bad)", { XX } },
7517 { "(bad)", { XX } },
7518 { "(bad)", { XX } },
7519 { "(bad)", { XX } },
7520 { "(bad)", { XX } },
7521 { "(bad)", { XX } },
7522 { "(bad)", { XX } },
7523 { "(bad)", { XX } },
7525 { "(bad)", { XX } },
7526 { "(bad)", { XX } },
7527 { "(bad)", { XX } },
7528 { "(bad)", { XX } },
7529 { "(bad)", { XX } },
7530 { "(bad)", { XX } },
7531 { "(bad)", { XX } },
7532 { "(bad)", { XX } },
7534 { "(bad)", { XX } },
7535 { "(bad)", { XX } },
7536 { "(bad)", { XX } },
7537 { "(bad)", { XX } },
7538 { "(bad)", { XX } },
7539 { "(bad)", { XX } },
7540 { "(bad)", { XX } },
7541 { "(bad)", { XX } },
7546 { "(bad)", { XX } },
7547 { "(bad)", { XX } },
7548 { "(bad)", { XX } },
7549 { "(bad)", { XX } },
7550 { PREFIX_TABLE (PREFIX_VEX_3A04) },
7551 { PREFIX_TABLE (PREFIX_VEX_3A05) },
7552 { PREFIX_TABLE (PREFIX_VEX_3A06) },
7553 { "(bad)", { XX } },
7555 { PREFIX_TABLE (PREFIX_VEX_3A08) },
7556 { PREFIX_TABLE (PREFIX_VEX_3A09) },
7557 { PREFIX_TABLE (PREFIX_VEX_3A0A) },
7558 { PREFIX_TABLE (PREFIX_VEX_3A0B) },
7559 { PREFIX_TABLE (PREFIX_VEX_3A0C) },
7560 { PREFIX_TABLE (PREFIX_VEX_3A0D) },
7561 { PREFIX_TABLE (PREFIX_VEX_3A0E) },
7562 { PREFIX_TABLE (PREFIX_VEX_3A0F) },
7564 { "(bad)", { XX } },
7565 { "(bad)", { XX } },
7566 { "(bad)", { XX } },
7567 { "(bad)", { XX } },
7568 { PREFIX_TABLE (PREFIX_VEX_3A14) },
7569 { PREFIX_TABLE (PREFIX_VEX_3A15) },
7570 { PREFIX_TABLE (PREFIX_VEX_3A16) },
7571 { PREFIX_TABLE (PREFIX_VEX_3A17) },
7573 { PREFIX_TABLE (PREFIX_VEX_3A18) },
7574 { PREFIX_TABLE (PREFIX_VEX_3A19) },
7575 { "(bad)", { XX } },
7576 { "(bad)", { XX } },
7577 { "(bad)", { XX } },
7578 { "(bad)", { XX } },
7579 { "(bad)", { XX } },
7580 { "(bad)", { XX } },
7582 { PREFIX_TABLE (PREFIX_VEX_3A20) },
7583 { PREFIX_TABLE (PREFIX_VEX_3A21) },
7584 { PREFIX_TABLE (PREFIX_VEX_3A22) },
7585 { "(bad)", { XX } },
7586 { "(bad)", { XX } },
7587 { "(bad)", { XX } },
7588 { "(bad)", { XX } },
7589 { "(bad)", { XX } },
7591 { "(bad)", { XX } },
7592 { "(bad)", { XX } },
7593 { "(bad)", { XX } },
7594 { "(bad)", { XX } },
7595 { "(bad)", { XX } },
7596 { "(bad)", { XX } },
7597 { "(bad)", { XX } },
7598 { "(bad)", { XX } },
7600 { "(bad)", { XX } },
7601 { "(bad)", { XX } },
7602 { "(bad)", { XX } },
7603 { "(bad)", { XX } },
7604 { "(bad)", { XX } },
7605 { "(bad)", { XX } },
7606 { "(bad)", { XX } },
7607 { "(bad)", { XX } },
7609 { "(bad)", { XX } },
7610 { "(bad)", { XX } },
7611 { "(bad)", { XX } },
7612 { "(bad)", { XX } },
7613 { "(bad)", { XX } },
7614 { "(bad)", { XX } },
7615 { "(bad)", { XX } },
7616 { "(bad)", { XX } },
7618 { PREFIX_TABLE (PREFIX_VEX_3A40) },
7619 { PREFIX_TABLE (PREFIX_VEX_3A41) },
7620 { PREFIX_TABLE (PREFIX_VEX_3A42) },
7621 { "(bad)", { XX } },
7622 { "(bad)", { XX } },
7623 { "(bad)", { XX } },
7624 { "(bad)", { XX } },
7625 { "(bad)", { XX } },
7627 { PREFIX_TABLE (PREFIX_VEX_3A48) },
7628 { PREFIX_TABLE (PREFIX_VEX_3A49) },
7629 { PREFIX_TABLE (PREFIX_VEX_3A4A) },
7630 { PREFIX_TABLE (PREFIX_VEX_3A4B) },
7631 { PREFIX_TABLE (PREFIX_VEX_3A4C) },
7632 { "(bad)", { XX } },
7633 { "(bad)", { XX } },
7634 { "(bad)", { XX } },
7636 { "(bad)", { XX } },
7637 { "(bad)", { XX } },
7638 { "(bad)", { XX } },
7639 { "(bad)", { XX } },
7640 { "(bad)", { XX } },
7641 { "(bad)", { XX } },
7642 { "(bad)", { XX } },
7643 { "(bad)", { XX } },
7645 { "(bad)", { XX } },
7646 { "(bad)", { XX } },
7647 { "(bad)", { XX } },
7648 { "(bad)", { XX } },
7649 { PREFIX_TABLE (PREFIX_VEX_3A5C) },
7650 { PREFIX_TABLE (PREFIX_VEX_3A5D) },
7651 { PREFIX_TABLE (PREFIX_VEX_3A5E) },
7652 { PREFIX_TABLE (PREFIX_VEX_3A5F) },
7654 { PREFIX_TABLE (PREFIX_VEX_3A60) },
7655 { PREFIX_TABLE (PREFIX_VEX_3A61) },
7656 { PREFIX_TABLE (PREFIX_VEX_3A62) },
7657 { PREFIX_TABLE (PREFIX_VEX_3A63) },
7658 { "(bad)", { XX } },
7659 { "(bad)", { XX } },
7660 { "(bad)", { XX } },
7661 { "(bad)", { XX } },
7663 { PREFIX_TABLE (PREFIX_VEX_3A68) },
7664 { PREFIX_TABLE (PREFIX_VEX_3A69) },
7665 { PREFIX_TABLE (PREFIX_VEX_3A6A) },
7666 { PREFIX_TABLE (PREFIX_VEX_3A6B) },
7667 { PREFIX_TABLE (PREFIX_VEX_3A6C) },
7668 { PREFIX_TABLE (PREFIX_VEX_3A6D) },
7669 { PREFIX_TABLE (PREFIX_VEX_3A6E) },
7670 { PREFIX_TABLE (PREFIX_VEX_3A6F) },
7672 { "(bad)", { XX } },
7673 { "(bad)", { XX } },
7674 { "(bad)", { XX } },
7675 { "(bad)", { XX } },
7676 { "(bad)", { XX } },
7677 { "(bad)", { XX } },
7678 { "(bad)", { XX } },
7679 { "(bad)", { XX } },
7681 { PREFIX_TABLE (PREFIX_VEX_3A78) },
7682 { PREFIX_TABLE (PREFIX_VEX_3A79) },
7683 { PREFIX_TABLE (PREFIX_VEX_3A7A) },
7684 { PREFIX_TABLE (PREFIX_VEX_3A7B) },
7685 { PREFIX_TABLE (PREFIX_VEX_3A7C) },
7686 { PREFIX_TABLE (PREFIX_VEX_3A7D) },
7687 { PREFIX_TABLE (PREFIX_VEX_3A7E) },
7688 { PREFIX_TABLE (PREFIX_VEX_3A7F) },
7690 { "(bad)", { XX } },
7691 { "(bad)", { XX } },
7692 { "(bad)", { XX } },
7693 { "(bad)", { XX } },
7694 { "(bad)", { XX } },
7695 { "(bad)", { XX } },
7696 { "(bad)", { XX } },
7697 { "(bad)", { XX } },
7699 { "(bad)", { XX } },
7700 { "(bad)", { XX } },
7701 { "(bad)", { XX } },
7702 { "(bad)", { XX } },
7703 { "(bad)", { XX } },
7704 { "(bad)", { XX } },
7705 { "(bad)", { XX } },
7706 { "(bad)", { XX } },
7708 { "(bad)", { XX } },
7709 { "(bad)", { XX } },
7710 { "(bad)", { XX } },
7711 { "(bad)", { XX } },
7712 { "(bad)", { XX } },
7713 { "(bad)", { XX } },
7714 { "(bad)", { XX } },
7715 { "(bad)", { XX } },
7717 { "(bad)", { XX } },
7718 { "(bad)", { XX } },
7719 { "(bad)", { XX } },
7720 { "(bad)", { XX } },
7721 { "(bad)", { XX } },
7722 { "(bad)", { XX } },
7723 { "(bad)", { XX } },
7724 { "(bad)", { XX } },
7726 { "(bad)", { XX } },
7727 { "(bad)", { XX } },
7728 { "(bad)", { XX } },
7729 { "(bad)", { XX } },
7730 { "(bad)", { XX } },
7731 { "(bad)", { XX } },
7732 { "(bad)", { XX } },
7733 { "(bad)", { XX } },
7735 { "(bad)", { XX } },
7736 { "(bad)", { XX } },
7737 { "(bad)", { XX } },
7738 { "(bad)", { XX } },
7739 { "(bad)", { XX } },
7740 { "(bad)", { XX } },
7741 { "(bad)", { XX } },
7742 { "(bad)", { XX } },
7744 { "(bad)", { XX } },
7745 { "(bad)", { XX } },
7746 { "(bad)", { XX } },
7747 { "(bad)", { XX } },
7748 { "(bad)", { XX } },
7749 { "(bad)", { XX } },
7750 { "(bad)", { XX } },
7751 { "(bad)", { XX } },
7753 { "(bad)", { XX } },
7754 { "(bad)", { XX } },
7755 { "(bad)", { XX } },
7756 { "(bad)", { XX } },
7757 { "(bad)", { XX } },
7758 { "(bad)", { XX } },
7759 { "(bad)", { XX } },
7760 { "(bad)", { XX } },
7762 { "(bad)", { XX } },
7763 { "(bad)", { XX } },
7764 { "(bad)", { XX } },
7765 { "(bad)", { XX } },
7766 { "(bad)", { XX } },
7767 { "(bad)", { XX } },
7768 { "(bad)", { XX } },
7769 { "(bad)", { XX } },
7771 { "(bad)", { XX } },
7772 { "(bad)", { XX } },
7773 { "(bad)", { XX } },
7774 { "(bad)", { XX } },
7775 { "(bad)", { XX } },
7776 { "(bad)", { XX } },
7777 { "(bad)", { XX } },
7778 { "(bad)", { XX } },
7780 { "(bad)", { XX } },
7781 { "(bad)", { XX } },
7782 { "(bad)", { XX } },
7783 { "(bad)", { XX } },
7784 { "(bad)", { XX } },
7785 { "(bad)", { XX } },
7786 { "(bad)", { XX } },
7787 { "(bad)", { XX } },
7789 { "(bad)", { XX } },
7790 { "(bad)", { XX } },
7791 { "(bad)", { XX } },
7792 { "(bad)", { XX } },
7793 { "(bad)", { XX } },
7794 { "(bad)", { XX } },
7795 { "(bad)", { XX } },
7796 { PREFIX_TABLE (PREFIX_VEX_3ADF) },
7798 { "(bad)", { XX } },
7799 { "(bad)", { XX } },
7800 { "(bad)", { XX } },
7801 { "(bad)", { XX } },
7802 { "(bad)", { XX } },
7803 { "(bad)", { XX } },
7804 { "(bad)", { XX } },
7805 { "(bad)", { XX } },
7807 { "(bad)", { XX } },
7808 { "(bad)", { XX } },
7809 { "(bad)", { XX } },
7810 { "(bad)", { XX } },
7811 { "(bad)", { XX } },
7812 { "(bad)", { XX } },
7813 { "(bad)", { XX } },
7814 { "(bad)", { XX } },
7816 { "(bad)", { XX } },
7817 { "(bad)", { XX } },
7818 { "(bad)", { XX } },
7819 { "(bad)", { XX } },
7820 { "(bad)", { XX } },
7821 { "(bad)", { XX } },
7822 { "(bad)", { XX } },
7823 { "(bad)", { XX } },
7825 { "(bad)", { XX } },
7826 { "(bad)", { XX } },
7827 { "(bad)", { XX } },
7828 { "(bad)", { XX } },
7829 { "(bad)", { XX } },
7830 { "(bad)", { XX } },
7831 { "(bad)", { XX } },
7832 { "(bad)", { XX } },
7836 static const struct dis386 vex_len_table[][2] = {
7837 /* VEX_LEN_10_P_1 */
7839 { "vmovss", { XMVex, Vex128, EXd } },
7840 { "(bad)", { XX } },
7843 /* VEX_LEN_10_P_3 */
7845 { "vmovsd", { XMVex, Vex128, EXq } },
7846 { "(bad)", { XX } },
7849 /* VEX_LEN_11_P_1 */
7851 { "vmovss", { EXdVexS, Vex128, XM } },
7852 { "(bad)", { XX } },
7855 /* VEX_LEN_11_P_3 */
7857 { "vmovsd", { EXqVexS, Vex128, XM } },
7858 { "(bad)", { XX } },
7861 /* VEX_LEN_12_P_0_M_0 */
7863 { "vmovlps", { XM, Vex128, EXq } },
7864 { "(bad)", { XX } },
7867 /* VEX_LEN_12_P_0_M_1 */
7869 { "vmovhlps", { XM, Vex128, EXq } },
7870 { "(bad)", { XX } },
7873 /* VEX_LEN_12_P_2 */
7875 { "vmovlpd", { XM, Vex128, EXq } },
7876 { "(bad)", { XX } },
7879 /* VEX_LEN_13_M_0 */
7881 { "vmovlpX", { EXq, XM } },
7882 { "(bad)", { XX } },
7885 /* VEX_LEN_16_P_0_M_0 */
7887 { "vmovhps", { XM, Vex128, EXq } },
7888 { "(bad)", { XX } },
7891 /* VEX_LEN_16_P_0_M_1 */
7893 { "vmovlhps", { XM, Vex128, EXq } },
7894 { "(bad)", { XX } },
7897 /* VEX_LEN_16_P_2 */
7899 { "vmovhpd", { XM, Vex128, EXq } },
7900 { "(bad)", { XX } },
7903 /* VEX_LEN_17_M_0 */
7905 { "vmovhpX", { EXq, XM } },
7906 { "(bad)", { XX } },
7909 /* VEX_LEN_2A_P_1 */
7911 { "vcvtsi2ss%LQ", { XM, Vex128, Ev } },
7912 { "(bad)", { XX } },
7915 /* VEX_LEN_2A_P_3 */
7917 { "vcvtsi2sd%LQ", { XM, Vex128, Ev } },
7918 { "(bad)", { XX } },
7921 /* VEX_LEN_2B_M_0 */
7923 { "vmovntpX", { Mx, XM } },
7924 { "(bad)", { XX } },
7927 /* VEX_LEN_2C_P_1 */
7929 { "vcvttss2siY", { Gv, EXd } },
7930 { "(bad)", { XX } },
7933 /* VEX_LEN_2C_P_3 */
7935 { "vcvttsd2siY", { Gv, EXq } },
7936 { "(bad)", { XX } },
7939 /* VEX_LEN_2D_P_1 */
7941 { "vcvtss2siY", { Gv, EXd } },
7942 { "(bad)", { XX } },
7945 /* VEX_LEN_2D_P_3 */
7947 { "vcvtsd2siY", { Gv, EXq } },
7948 { "(bad)", { XX } },
7951 /* VEX_LEN_2E_P_0 */
7953 { "vucomiss", { XM, EXd } },
7954 { "(bad)", { XX } },
7957 /* VEX_LEN_2E_P_2 */
7959 { "vucomisd", { XM, EXq } },
7960 { "(bad)", { XX } },
7963 /* VEX_LEN_2F_P_0 */
7965 { "vcomiss", { XM, EXd } },
7966 { "(bad)", { XX } },
7969 /* VEX_LEN_2F_P_2 */
7971 { "vcomisd", { XM, EXq } },
7972 { "(bad)", { XX } },
7975 /* VEX_LEN_51_P_1 */
7977 { "vsqrtss", { XM, Vex128, EXd } },
7978 { "(bad)", { XX } },
7981 /* VEX_LEN_51_P_3 */
7983 { "vsqrtsd", { XM, Vex128, EXq } },
7984 { "(bad)", { XX } },
7987 /* VEX_LEN_52_P_1 */
7989 { "vrsqrtss", { XM, Vex128, EXd } },
7990 { "(bad)", { XX } },
7993 /* VEX_LEN_53_P_1 */
7995 { "vrcpss", { XM, Vex128, EXd } },
7996 { "(bad)", { XX } },
7999 /* VEX_LEN_58_P_1 */
8001 { "vaddss", { XM, Vex128, EXd } },
8002 { "(bad)", { XX } },
8005 /* VEX_LEN_58_P_3 */
8007 { "vaddsd", { XM, Vex128, EXq } },
8008 { "(bad)", { XX } },
8011 /* VEX_LEN_59_P_1 */
8013 { "vmulss", { XM, Vex128, EXd } },
8014 { "(bad)", { XX } },
8017 /* VEX_LEN_59_P_3 */
8019 { "vmulsd", { XM, Vex128, EXq } },
8020 { "(bad)", { XX } },
8023 /* VEX_LEN_5A_P_1 */
8025 { "vcvtss2sd", { XM, Vex128, EXd } },
8026 { "(bad)", { XX } },
8029 /* VEX_LEN_5A_P_3 */
8031 { "vcvtsd2ss", { XM, Vex128, EXq } },
8032 { "(bad)", { XX } },
8035 /* VEX_LEN_5C_P_1 */
8037 { "vsubss", { XM, Vex128, EXd } },
8038 { "(bad)", { XX } },
8041 /* VEX_LEN_5C_P_3 */
8043 { "vsubsd", { XM, Vex128, EXq } },
8044 { "(bad)", { XX } },
8047 /* VEX_LEN_5D_P_1 */
8049 { "vminss", { XM, Vex128, EXd } },
8050 { "(bad)", { XX } },
8053 /* VEX_LEN_5D_P_3 */
8055 { "vminsd", { XM, Vex128, EXq } },
8056 { "(bad)", { XX } },
8059 /* VEX_LEN_5E_P_1 */
8061 { "vdivss", { XM, Vex128, EXd } },
8062 { "(bad)", { XX } },
8065 /* VEX_LEN_5E_P_3 */
8067 { "vdivsd", { XM, Vex128, EXq } },
8068 { "(bad)", { XX } },
8071 /* VEX_LEN_5F_P_1 */
8073 { "vmaxss", { XM, Vex128, EXd } },
8074 { "(bad)", { XX } },
8077 /* VEX_LEN_5F_P_3 */
8079 { "vmaxsd", { XM, Vex128, EXq } },
8080 { "(bad)", { XX } },
8083 /* VEX_LEN_60_P_2 */
8085 { "vpunpcklbw", { XM, Vex128, EXx } },
8086 { "(bad)", { XX } },
8089 /* VEX_LEN_61_P_2 */
8091 { "vpunpcklwd", { XM, Vex128, EXx } },
8092 { "(bad)", { XX } },
8095 /* VEX_LEN_62_P_2 */
8097 { "vpunpckldq", { XM, Vex128, EXx } },
8098 { "(bad)", { XX } },
8101 /* VEX_LEN_63_P_2 */
8103 { "vpacksswb", { XM, Vex128, EXx } },
8104 { "(bad)", { XX } },
8107 /* VEX_LEN_64_P_2 */
8109 { "vpcmpgtb", { XM, Vex128, EXx } },
8110 { "(bad)", { XX } },
8113 /* VEX_LEN_65_P_2 */
8115 { "vpcmpgtw", { XM, Vex128, EXx } },
8116 { "(bad)", { XX } },
8119 /* VEX_LEN_66_P_2 */
8121 { "vpcmpgtd", { XM, Vex128, EXx } },
8122 { "(bad)", { XX } },
8125 /* VEX_LEN_67_P_2 */
8127 { "vpackuswb", { XM, Vex128, EXx } },
8128 { "(bad)", { XX } },
8131 /* VEX_LEN_68_P_2 */
8133 { "vpunpckhbw", { XM, Vex128, EXx } },
8134 { "(bad)", { XX } },
8137 /* VEX_LEN_69_P_2 */
8139 { "vpunpckhwd", { XM, Vex128, EXx } },
8140 { "(bad)", { XX } },
8143 /* VEX_LEN_6A_P_2 */
8145 { "vpunpckhdq", { XM, Vex128, EXx } },
8146 { "(bad)", { XX } },
8149 /* VEX_LEN_6B_P_2 */
8151 { "vpackssdw", { XM, Vex128, EXx } },
8152 { "(bad)", { XX } },
8155 /* VEX_LEN_6C_P_2 */
8157 { "vpunpcklqdq", { XM, Vex128, EXx } },
8158 { "(bad)", { XX } },
8161 /* VEX_LEN_6D_P_2 */
8163 { "vpunpckhqdq", { XM, Vex128, EXx } },
8164 { "(bad)", { XX } },
8167 /* VEX_LEN_6E_P_2 */
8169 { "vmovK", { XM, Edq } },
8170 { "(bad)", { XX } },
8173 /* VEX_LEN_70_P_1 */
8175 { "vpshufhw", { XM, EXx, Ib } },
8176 { "(bad)", { XX } },
8179 /* VEX_LEN_70_P_2 */
8181 { "vpshufd", { XM, EXx, Ib } },
8182 { "(bad)", { XX } },
8185 /* VEX_LEN_70_P_3 */
8187 { "vpshuflw", { XM, EXx, Ib } },
8188 { "(bad)", { XX } },
8191 /* VEX_LEN_71_R_2_P_2 */
8193 { "vpsrlw", { Vex128, XS, Ib } },
8194 { "(bad)", { XX } },
8197 /* VEX_LEN_71_R_4_P_2 */
8199 { "vpsraw", { Vex128, XS, Ib } },
8200 { "(bad)", { XX } },
8203 /* VEX_LEN_71_R_6_P_2 */
8205 { "vpsllw", { Vex128, XS, Ib } },
8206 { "(bad)", { XX } },
8209 /* VEX_LEN_72_R_2_P_2 */
8211 { "vpsrld", { Vex128, XS, Ib } },
8212 { "(bad)", { XX } },
8215 /* VEX_LEN_72_R_4_P_2 */
8217 { "vpsrad", { Vex128, XS, Ib } },
8218 { "(bad)", { XX } },
8221 /* VEX_LEN_72_R_6_P_2 */
8223 { "vpslld", { Vex128, XS, Ib } },
8224 { "(bad)", { XX } },
8227 /* VEX_LEN_73_R_2_P_2 */
8229 { "vpsrlq", { Vex128, XS, Ib } },
8230 { "(bad)", { XX } },
8233 /* VEX_LEN_73_R_3_P_2 */
8235 { "vpsrldq", { Vex128, XS, Ib } },
8236 { "(bad)", { XX } },
8239 /* VEX_LEN_73_R_6_P_2 */
8241 { "vpsllq", { Vex128, XS, Ib } },
8242 { "(bad)", { XX } },
8245 /* VEX_LEN_73_R_7_P_2 */
8247 { "vpslldq", { Vex128, XS, Ib } },
8248 { "(bad)", { XX } },
8251 /* VEX_LEN_74_P_2 */
8253 { "vpcmpeqb", { XM, Vex128, EXx } },
8254 { "(bad)", { XX } },
8257 /* VEX_LEN_75_P_2 */
8259 { "vpcmpeqw", { XM, Vex128, EXx } },
8260 { "(bad)", { XX } },
8263 /* VEX_LEN_76_P_2 */
8265 { "vpcmpeqd", { XM, Vex128, EXx } },
8266 { "(bad)", { XX } },
8269 /* VEX_LEN_7E_P_1 */
8271 { "vmovq", { XM, EXq } },
8272 { "(bad)", { XX } },
8275 /* VEX_LEN_7E_P_2 */
8277 { "vmovK", { Edq, XM } },
8278 { "(bad)", { XX } },
8281 /* VEX_LEN_AE_R_2_M0 */
8283 { "vldmxcsr", { Md } },
8284 { "(bad)", { XX } },
8287 /* VEX_LEN_AE_R_3_M0 */
8289 { "vstmxcsr", { Md } },
8290 { "(bad)", { XX } },
8293 /* VEX_LEN_C2_P_1 */
8295 { "vcmpss", { XM, Vex128, EXd, VCMP } },
8296 { "(bad)", { XX } },
8299 /* VEX_LEN_C2_P_3 */
8301 { "vcmpsd", { XM, Vex128, EXq, VCMP } },
8302 { "(bad)", { XX } },
8305 /* VEX_LEN_C4_P_2 */
8307 { "vpinsrw", { XM, Vex128, Edqw, Ib } },
8308 { "(bad)", { XX } },
8311 /* VEX_LEN_C5_P_2 */
8313 { "vpextrw", { Gdq, XS, Ib } },
8314 { "(bad)", { XX } },
8317 /* VEX_LEN_D1_P_2 */
8319 { "vpsrlw", { XM, Vex128, EXx } },
8320 { "(bad)", { XX } },
8323 /* VEX_LEN_D2_P_2 */
8325 { "vpsrld", { XM, Vex128, EXx } },
8326 { "(bad)", { XX } },
8329 /* VEX_LEN_D3_P_2 */
8331 { "vpsrlq", { XM, Vex128, EXx } },
8332 { "(bad)", { XX } },
8335 /* VEX_LEN_D4_P_2 */
8337 { "vpaddq", { XM, Vex128, EXx } },
8338 { "(bad)", { XX } },
8341 /* VEX_LEN_D5_P_2 */
8343 { "vpmullw", { XM, Vex128, EXx } },
8344 { "(bad)", { XX } },
8347 /* VEX_LEN_D6_P_2 */
8349 { "vmovq", { EXqS, XM } },
8350 { "(bad)", { XX } },
8353 /* VEX_LEN_D7_P_2_M_1 */
8355 { "vpmovmskb", { Gdq, XS } },
8356 { "(bad)", { XX } },
8359 /* VEX_LEN_D8_P_2 */
8361 { "vpsubusb", { XM, Vex128, EXx } },
8362 { "(bad)", { XX } },
8365 /* VEX_LEN_D9_P_2 */
8367 { "vpsubusw", { XM, Vex128, EXx } },
8368 { "(bad)", { XX } },
8371 /* VEX_LEN_DA_P_2 */
8373 { "vpminub", { XM, Vex128, EXx } },
8374 { "(bad)", { XX } },
8377 /* VEX_LEN_DB_P_2 */
8379 { "vpand", { XM, Vex128, EXx } },
8380 { "(bad)", { XX } },
8383 /* VEX_LEN_DC_P_2 */
8385 { "vpaddusb", { XM, Vex128, EXx } },
8386 { "(bad)", { XX } },
8389 /* VEX_LEN_DD_P_2 */
8391 { "vpaddusw", { XM, Vex128, EXx } },
8392 { "(bad)", { XX } },
8395 /* VEX_LEN_DE_P_2 */
8397 { "vpmaxub", { XM, Vex128, EXx } },
8398 { "(bad)", { XX } },
8401 /* VEX_LEN_DF_P_2 */
8403 { "vpandn", { XM, Vex128, EXx } },
8404 { "(bad)", { XX } },
8407 /* VEX_LEN_E0_P_2 */
8409 { "vpavgb", { XM, Vex128, EXx } },
8410 { "(bad)", { XX } },
8413 /* VEX_LEN_E1_P_2 */
8415 { "vpsraw", { XM, Vex128, EXx } },
8416 { "(bad)", { XX } },
8419 /* VEX_LEN_E2_P_2 */
8421 { "vpsrad", { XM, Vex128, EXx } },
8422 { "(bad)", { XX } },
8425 /* VEX_LEN_E3_P_2 */
8427 { "vpavgw", { XM, Vex128, EXx } },
8428 { "(bad)", { XX } },
8431 /* VEX_LEN_E4_P_2 */
8433 { "vpmulhuw", { XM, Vex128, EXx } },
8434 { "(bad)", { XX } },
8437 /* VEX_LEN_E5_P_2 */
8439 { "vpmulhw", { XM, Vex128, EXx } },
8440 { "(bad)", { XX } },
8443 /* VEX_LEN_E7_P_2_M_0 */
8445 { "vmovntdq", { Mx, XM } },
8446 { "(bad)", { XX } },
8449 /* VEX_LEN_E8_P_2 */
8451 { "vpsubsb", { XM, Vex128, EXx } },
8452 { "(bad)", { XX } },
8455 /* VEX_LEN_E9_P_2 */
8457 { "vpsubsw", { XM, Vex128, EXx } },
8458 { "(bad)", { XX } },
8461 /* VEX_LEN_EA_P_2 */
8463 { "vpminsw", { XM, Vex128, EXx } },
8464 { "(bad)", { XX } },
8467 /* VEX_LEN_EB_P_2 */
8469 { "vpor", { XM, Vex128, EXx } },
8470 { "(bad)", { XX } },
8473 /* VEX_LEN_EC_P_2 */
8475 { "vpaddsb", { XM, Vex128, EXx } },
8476 { "(bad)", { XX } },
8479 /* VEX_LEN_ED_P_2 */
8481 { "vpaddsw", { XM, Vex128, EXx } },
8482 { "(bad)", { XX } },
8485 /* VEX_LEN_EE_P_2 */
8487 { "vpmaxsw", { XM, Vex128, EXx } },
8488 { "(bad)", { XX } },
8491 /* VEX_LEN_EF_P_2 */
8493 { "vpxor", { XM, Vex128, EXx } },
8494 { "(bad)", { XX } },
8497 /* VEX_LEN_F1_P_2 */
8499 { "vpsllw", { XM, Vex128, EXx } },
8500 { "(bad)", { XX } },
8503 /* VEX_LEN_F2_P_2 */
8505 { "vpslld", { XM, Vex128, EXx } },
8506 { "(bad)", { XX } },
8509 /* VEX_LEN_F3_P_2 */
8511 { "vpsllq", { XM, Vex128, EXx } },
8512 { "(bad)", { XX } },
8515 /* VEX_LEN_F4_P_2 */
8517 { "vpmuludq", { XM, Vex128, EXx } },
8518 { "(bad)", { XX } },
8521 /* VEX_LEN_F5_P_2 */
8523 { "vpmaddwd", { XM, Vex128, EXx } },
8524 { "(bad)", { XX } },
8527 /* VEX_LEN_F6_P_2 */
8529 { "vpsadbw", { XM, Vex128, EXx } },
8530 { "(bad)", { XX } },
8533 /* VEX_LEN_F7_P_2 */
8535 { "vmaskmovdqu", { XM, XS } },
8536 { "(bad)", { XX } },
8539 /* VEX_LEN_F8_P_2 */
8541 { "vpsubb", { XM, Vex128, EXx } },
8542 { "(bad)", { XX } },
8545 /* VEX_LEN_F9_P_2 */
8547 { "vpsubw", { XM, Vex128, EXx } },
8548 { "(bad)", { XX } },
8551 /* VEX_LEN_FA_P_2 */
8553 { "vpsubd", { XM, Vex128, EXx } },
8554 { "(bad)", { XX } },
8557 /* VEX_LEN_FB_P_2 */
8559 { "vpsubq", { XM, Vex128, EXx } },
8560 { "(bad)", { XX } },
8563 /* VEX_LEN_FC_P_2 */
8565 { "vpaddb", { XM, Vex128, EXx } },
8566 { "(bad)", { XX } },
8569 /* VEX_LEN_FD_P_2 */
8571 { "vpaddw", { XM, Vex128, EXx } },
8572 { "(bad)", { XX } },
8575 /* VEX_LEN_FE_P_2 */
8577 { "vpaddd", { XM, Vex128, EXx } },
8578 { "(bad)", { XX } },
8581 /* VEX_LEN_3800_P_2 */
8583 { "vpshufb", { XM, Vex128, EXx } },
8584 { "(bad)", { XX } },
8587 /* VEX_LEN_3801_P_2 */
8589 { "vphaddw", { XM, Vex128, EXx } },
8590 { "(bad)", { XX } },
8593 /* VEX_LEN_3802_P_2 */
8595 { "vphaddd", { XM, Vex128, EXx } },
8596 { "(bad)", { XX } },
8599 /* VEX_LEN_3803_P_2 */
8601 { "vphaddsw", { XM, Vex128, EXx } },
8602 { "(bad)", { XX } },
8605 /* VEX_LEN_3804_P_2 */
8607 { "vpmaddubsw", { XM, Vex128, EXx } },
8608 { "(bad)", { XX } },
8611 /* VEX_LEN_3805_P_2 */
8613 { "vphsubw", { XM, Vex128, EXx } },
8614 { "(bad)", { XX } },
8617 /* VEX_LEN_3806_P_2 */
8619 { "vphsubd", { XM, Vex128, EXx } },
8620 { "(bad)", { XX } },
8623 /* VEX_LEN_3807_P_2 */
8625 { "vphsubsw", { XM, Vex128, EXx } },
8626 { "(bad)", { XX } },
8629 /* VEX_LEN_3808_P_2 */
8631 { "vpsignb", { XM, Vex128, EXx } },
8632 { "(bad)", { XX } },
8635 /* VEX_LEN_3809_P_2 */
8637 { "vpsignw", { XM, Vex128, EXx } },
8638 { "(bad)", { XX } },
8641 /* VEX_LEN_380A_P_2 */
8643 { "vpsignd", { XM, Vex128, EXx } },
8644 { "(bad)", { XX } },
8647 /* VEX_LEN_380B_P_2 */
8649 { "vpmulhrsw", { XM, Vex128, EXx } },
8650 { "(bad)", { XX } },
8653 /* VEX_LEN_3819_P_2_M_0 */
8655 { "(bad)", { XX } },
8656 { "vbroadcastsd", { XM, Mq } },
8659 /* VEX_LEN_381A_P_2_M_0 */
8661 { "(bad)", { XX } },
8662 { "vbroadcastf128", { XM, Mxmm } },
8665 /* VEX_LEN_381C_P_2 */
8667 { "vpabsb", { XM, EXx } },
8668 { "(bad)", { XX } },
8671 /* VEX_LEN_381D_P_2 */
8673 { "vpabsw", { XM, EXx } },
8674 { "(bad)", { XX } },
8677 /* VEX_LEN_381E_P_2 */
8679 { "vpabsd", { XM, EXx } },
8680 { "(bad)", { XX } },
8683 /* VEX_LEN_3820_P_2 */
8685 { "vpmovsxbw", { XM, EXq } },
8686 { "(bad)", { XX } },
8689 /* VEX_LEN_3821_P_2 */
8691 { "vpmovsxbd", { XM, EXd } },
8692 { "(bad)", { XX } },
8695 /* VEX_LEN_3822_P_2 */
8697 { "vpmovsxbq", { XM, EXw } },
8698 { "(bad)", { XX } },
8701 /* VEX_LEN_3823_P_2 */
8703 { "vpmovsxwd", { XM, EXq } },
8704 { "(bad)", { XX } },
8707 /* VEX_LEN_3824_P_2 */
8709 { "vpmovsxwq", { XM, EXd } },
8710 { "(bad)", { XX } },
8713 /* VEX_LEN_3825_P_2 */
8715 { "vpmovsxdq", { XM, EXq } },
8716 { "(bad)", { XX } },
8719 /* VEX_LEN_3828_P_2 */
8721 { "vpmuldq", { XM, Vex128, EXx } },
8722 { "(bad)", { XX } },
8725 /* VEX_LEN_3829_P_2 */
8727 { "vpcmpeqq", { XM, Vex128, EXx } },
8728 { "(bad)", { XX } },
8731 /* VEX_LEN_382A_P_2_M_0 */
8733 { "vmovntdqa", { XM, Mx } },
8734 { "(bad)", { XX } },
8737 /* VEX_LEN_382B_P_2 */
8739 { "vpackusdw", { XM, Vex128, EXx } },
8740 { "(bad)", { XX } },
8743 /* VEX_LEN_3830_P_2 */
8745 { "vpmovzxbw", { XM, EXq } },
8746 { "(bad)", { XX } },
8749 /* VEX_LEN_3831_P_2 */
8751 { "vpmovzxbd", { XM, EXd } },
8752 { "(bad)", { XX } },
8755 /* VEX_LEN_3832_P_2 */
8757 { "vpmovzxbq", { XM, EXw } },
8758 { "(bad)", { XX } },
8761 /* VEX_LEN_3833_P_2 */
8763 { "vpmovzxwd", { XM, EXq } },
8764 { "(bad)", { XX } },
8767 /* VEX_LEN_3834_P_2 */
8769 { "vpmovzxwq", { XM, EXd } },
8770 { "(bad)", { XX } },
8773 /* VEX_LEN_3835_P_2 */
8775 { "vpmovzxdq", { XM, EXq } },
8776 { "(bad)", { XX } },
8779 /* VEX_LEN_3837_P_2 */
8781 { "vpcmpgtq", { XM, Vex128, EXx } },
8782 { "(bad)", { XX } },
8785 /* VEX_LEN_3838_P_2 */
8787 { "vpminsb", { XM, Vex128, EXx } },
8788 { "(bad)", { XX } },
8791 /* VEX_LEN_3839_P_2 */
8793 { "vpminsd", { XM, Vex128, EXx } },
8794 { "(bad)", { XX } },
8797 /* VEX_LEN_383A_P_2 */
8799 { "vpminuw", { XM, Vex128, EXx } },
8800 { "(bad)", { XX } },
8803 /* VEX_LEN_383B_P_2 */
8805 { "vpminud", { XM, Vex128, EXx } },
8806 { "(bad)", { XX } },
8809 /* VEX_LEN_383C_P_2 */
8811 { "vpmaxsb", { XM, Vex128, EXx } },
8812 { "(bad)", { XX } },
8815 /* VEX_LEN_383D_P_2 */
8817 { "vpmaxsd", { XM, Vex128, EXx } },
8818 { "(bad)", { XX } },
8821 /* VEX_LEN_383E_P_2 */
8823 { "vpmaxuw", { XM, Vex128, EXx } },
8824 { "(bad)", { XX } },
8827 /* VEX_LEN_383F_P_2 */
8829 { "vpmaxud", { XM, Vex128, EXx } },
8830 { "(bad)", { XX } },
8833 /* VEX_LEN_3840_P_2 */
8835 { "vpmulld", { XM, Vex128, EXx } },
8836 { "(bad)", { XX } },
8839 /* VEX_LEN_3841_P_2 */
8841 { "vphminposuw", { XM, EXx } },
8842 { "(bad)", { XX } },
8845 /* VEX_LEN_38DB_P_2 */
8847 { "vaesimc", { XM, EXx } },
8848 { "(bad)", { XX } },
8851 /* VEX_LEN_38DC_P_2 */
8853 { "vaesenc", { XM, Vex128, EXx } },
8854 { "(bad)", { XX } },
8857 /* VEX_LEN_38DD_P_2 */
8859 { "vaesenclast", { XM, Vex128, EXx } },
8860 { "(bad)", { XX } },
8863 /* VEX_LEN_38DE_P_2 */
8865 { "vaesdec", { XM, Vex128, EXx } },
8866 { "(bad)", { XX } },
8869 /* VEX_LEN_38DF_P_2 */
8871 { "vaesdeclast", { XM, Vex128, EXx } },
8872 { "(bad)", { XX } },
8875 /* VEX_LEN_3A06_P_2 */
8877 { "(bad)", { XX } },
8878 { "vperm2f128", { XM, Vex256, EXx, Ib } },
8881 /* VEX_LEN_3A0A_P_2 */
8883 { "vroundss", { XM, Vex128, EXd, Ib } },
8884 { "(bad)", { XX } },
8887 /* VEX_LEN_3A0B_P_2 */
8889 { "vroundsd", { XM, Vex128, EXq, Ib } },
8890 { "(bad)", { XX } },
8893 /* VEX_LEN_3A0E_P_2 */
8895 { "vpblendw", { XM, Vex128, EXx, Ib } },
8896 { "(bad)", { XX } },
8899 /* VEX_LEN_3A0F_P_2 */
8901 { "vpalignr", { XM, Vex128, EXx, Ib } },
8902 { "(bad)", { XX } },
8905 /* VEX_LEN_3A14_P_2 */
8907 { "vpextrb", { Edqb, XM, Ib } },
8908 { "(bad)", { XX } },
8911 /* VEX_LEN_3A15_P_2 */
8913 { "vpextrw", { Edqw, XM, Ib } },
8914 { "(bad)", { XX } },
8917 /* VEX_LEN_3A16_P_2 */
8919 { "vpextrK", { Edq, XM, Ib } },
8920 { "(bad)", { XX } },
8923 /* VEX_LEN_3A17_P_2 */
8925 { "vextractps", { Edqd, XM, Ib } },
8926 { "(bad)", { XX } },
8929 /* VEX_LEN_3A18_P_2 */
8931 { "(bad)", { XX } },
8932 { "vinsertf128", { XM, Vex256, EXxmm, Ib } },
8935 /* VEX_LEN_3A19_P_2 */
8937 { "(bad)", { XX } },
8938 { "vextractf128", { EXxmm, XM, Ib } },
8941 /* VEX_LEN_3A20_P_2 */
8943 { "vpinsrb", { XM, Vex128, Edqb, Ib } },
8944 { "(bad)", { XX } },
8947 /* VEX_LEN_3A21_P_2 */
8949 { "vinsertps", { XM, Vex128, EXd, Ib } },
8950 { "(bad)", { XX } },
8953 /* VEX_LEN_3A22_P_2 */
8955 { "vpinsrK", { XM, Vex128, Edq, Ib } },
8956 { "(bad)", { XX } },
8959 /* VEX_LEN_3A41_P_2 */
8961 { "vdppd", { XM, Vex128, EXx, Ib } },
8962 { "(bad)", { XX } },
8965 /* VEX_LEN_3A42_P_2 */
8967 { "vmpsadbw", { XM, Vex128, EXx, Ib } },
8968 { "(bad)", { XX } },
8971 /* VEX_LEN_3A4C_P_2 */
8973 { "vpblendvb", { XM, Vex128, EXx, XMVexI4 } },
8974 { "(bad)", { XX } },
8977 /* VEX_LEN_3A60_P_2 */
8979 { "vpcmpestrm", { XM, EXx, Ib } },
8980 { "(bad)", { XX } },
8983 /* VEX_LEN_3A61_P_2 */
8985 { "vpcmpestri", { XM, EXx, Ib } },
8986 { "(bad)", { XX } },
8989 /* VEX_LEN_3A62_P_2 */
8991 { "vpcmpistrm", { XM, EXx, Ib } },
8992 { "(bad)", { XX } },
8995 /* VEX_LEN_3A63_P_2 */
8997 { "vpcmpistri", { XM, EXx, Ib } },
8998 { "(bad)", { XX } },
9001 /* VEX_LEN_3A6A_P_2 */
9003 { "vfmaddss", { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
9004 { "(bad)", { XX } },
9007 /* VEX_LEN_3A6B_P_2 */
9009 { "vfmaddsd", { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
9010 { "(bad)", { XX } },
9013 /* VEX_LEN_3A6E_P_2 */
9015 { "vfmsubss", { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
9016 { "(bad)", { XX } },
9019 /* VEX_LEN_3A6F_P_2 */
9021 { "vfmsubsd", { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
9022 { "(bad)", { XX } },
9025 /* VEX_LEN_3A7A_P_2 */
9027 { "vfnmaddss", { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
9028 { "(bad)", { XX } },
9031 /* VEX_LEN_3A7B_P_2 */
9033 { "vfnmaddsd", { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
9034 { "(bad)", { XX } },
9037 /* VEX_LEN_3A7E_P_2 */
9039 { "vfnmsubss", { XMVexW, Vex128FMA, EXdVexW, EXdVexW, VexI4 } },
9040 { "(bad)", { XX } },
9043 /* VEX_LEN_3A7F_P_2 */
9045 { "vfnmsubsd", { XMVexW, Vex128FMA, EXqVexW, EXqVexW, VexI4 } },
9046 { "(bad)", { XX } },
9049 /* VEX_LEN_3ADF_P_2 */
9051 { "vaeskeygenassist", { XM, EXx, Ib } },
9052 { "(bad)", { XX } },
9056 static const struct dis386 mod_table[][2] = {
9059 { "leaS", { Gv, M } },
9060 { "(bad)", { XX } },
9063 /* MOD_0F01_REG_0 */
9064 { X86_64_TABLE (X86_64_0F01_REG_0) },
9065 { RM_TABLE (RM_0F01_REG_0) },
9068 /* MOD_0F01_REG_1 */
9069 { X86_64_TABLE (X86_64_0F01_REG_1) },
9070 { RM_TABLE (RM_0F01_REG_1) },
9073 /* MOD_0F01_REG_2 */
9074 { X86_64_TABLE (X86_64_0F01_REG_2) },
9075 { RM_TABLE (RM_0F01_REG_2) },
9078 /* MOD_0F01_REG_3 */
9079 { X86_64_TABLE (X86_64_0F01_REG_3) },
9080 { RM_TABLE (RM_0F01_REG_3) },
9083 /* MOD_0F01_REG_7 */
9084 { "invlpg", { Mb } },
9085 { RM_TABLE (RM_0F01_REG_7) },
9088 /* MOD_0F12_PREFIX_0 */
9089 { "movlps", { XM, EXq } },
9090 { "movhlps", { XM, EXq } },
9094 { "movlpX", { EXq, XM } },
9095 { "(bad)", { XX } },
9098 /* MOD_0F16_PREFIX_0 */
9099 { "movhps", { XM, EXq } },
9100 { "movlhps", { XM, EXq } },
9104 { "movhpX", { EXq, XM } },
9105 { "(bad)", { XX } },
9108 /* MOD_0F18_REG_0 */
9109 { "prefetchnta", { Mb } },
9110 { "(bad)", { XX } },
9113 /* MOD_0F18_REG_1 */
9114 { "prefetcht0", { Mb } },
9115 { "(bad)", { XX } },
9118 /* MOD_0F18_REG_2 */
9119 { "prefetcht1", { Mb } },
9120 { "(bad)", { XX } },
9123 /* MOD_0F18_REG_3 */
9124 { "prefetcht2", { Mb } },
9125 { "(bad)", { XX } },
9129 { "(bad)", { XX } },
9130 { "movZ", { Rm, Cm } },
9134 { "(bad)", { XX } },
9135 { "movZ", { Rm, Dm } },
9139 { "(bad)", { XX } },
9140 { "movZ", { Cm, Rm } },
9144 { "(bad)", { XX } },
9145 { "movZ", { Dm, Rm } },
9149 { THREE_BYTE_TABLE (THREE_BYTE_0F24) },
9150 { "movL", { Rd, Td } },
9154 { "(bad)", { XX } },
9155 { "movL", { Td, Rd } },
9158 /* MOD_0F2B_PREFIX_0 */
9159 {"movntps", { Mx, XM } },
9160 { "(bad)", { XX } },
9163 /* MOD_0F2B_PREFIX_1 */
9164 {"movntss", { Md, XM } },
9165 { "(bad)", { XX } },
9168 /* MOD_0F2B_PREFIX_2 */
9169 {"movntpd", { Mx, XM } },
9170 { "(bad)", { XX } },
9173 /* MOD_0F2B_PREFIX_3 */
9174 {"movntsd", { Mq, XM } },
9175 { "(bad)", { XX } },
9179 { "(bad)", { XX } },
9180 { "movmskpX", { Gdq, XS } },
9183 /* MOD_0F71_REG_2 */
9184 { "(bad)", { XX } },
9185 { "psrlw", { MS, Ib } },
9188 /* MOD_0F71_REG_4 */
9189 { "(bad)", { XX } },
9190 { "psraw", { MS, Ib } },
9193 /* MOD_0F71_REG_6 */
9194 { "(bad)", { XX } },
9195 { "psllw", { MS, Ib } },
9198 /* MOD_0F72_REG_2 */
9199 { "(bad)", { XX } },
9200 { "psrld", { MS, Ib } },
9203 /* MOD_0F72_REG_4 */
9204 { "(bad)", { XX } },
9205 { "psrad", { MS, Ib } },
9208 /* MOD_0F72_REG_6 */
9209 { "(bad)", { XX } },
9210 { "pslld", { MS, Ib } },
9213 /* MOD_0F73_REG_2 */
9214 { "(bad)", { XX } },
9215 { "psrlq", { MS, Ib } },
9218 /* MOD_0F73_REG_3 */
9219 { "(bad)", { XX } },
9220 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
9223 /* MOD_0F73_REG_6 */
9224 { "(bad)", { XX } },
9225 { "psllq", { MS, Ib } },
9228 /* MOD_0F73_REG_7 */
9229 { "(bad)", { XX } },
9230 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
9233 /* MOD_0FAE_REG_0 */
9234 { "fxsave", { M } },
9235 { "(bad)", { XX } },
9238 /* MOD_0FAE_REG_1 */
9239 { "fxrstor", { M } },
9240 { "(bad)", { XX } },
9243 /* MOD_0FAE_REG_2 */
9244 { "ldmxcsr", { Md } },
9245 { "(bad)", { XX } },
9248 /* MOD_0FAE_REG_3 */
9249 { "stmxcsr", { Md } },
9250 { "(bad)", { XX } },
9253 /* MOD_0FAE_REG_4 */
9255 { "(bad)", { XX } },
9258 /* MOD_0FAE_REG_5 */
9259 { "xrstor", { M } },
9260 { RM_TABLE (RM_0FAE_REG_5) },
9263 /* MOD_0FAE_REG_6 */
9264 { "xsaveopt", { M } },
9265 { RM_TABLE (RM_0FAE_REG_6) },
9268 /* MOD_0FAE_REG_7 */
9269 { "clflush", { Mb } },
9270 { RM_TABLE (RM_0FAE_REG_7) },
9274 { "lssS", { Gv, Mp } },
9275 { "(bad)", { XX } },
9279 { "lfsS", { Gv, Mp } },
9280 { "(bad)", { XX } },
9284 { "lgsS", { Gv, Mp } },
9285 { "(bad)", { XX } },
9288 /* MOD_0FC7_REG_6 */
9289 { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
9290 { "(bad)", { XX } },
9293 /* MOD_0FC7_REG_7 */
9294 { "vmptrst", { Mq } },
9295 { "(bad)", { XX } },
9299 { "(bad)", { XX } },
9300 { "pmovmskb", { Gdq, MS } },
9303 /* MOD_0FE7_PREFIX_2 */
9304 { "movntdq", { Mx, XM } },
9305 { "(bad)", { XX } },
9308 /* MOD_0FF0_PREFIX_3 */
9309 { "lddqu", { XM, M } },
9310 { "(bad)", { XX } },
9313 /* MOD_0F382A_PREFIX_2 */
9314 { "movntdqa", { XM, Mx } },
9315 { "(bad)", { XX } },
9319 { "bound{S|}", { Gv, Ma } },
9320 { "(bad)", { XX } },
9324 { "lesS", { Gv, Mp } },
9325 { VEX_C4_TABLE (VEX_0F) },
9329 { "ldsS", { Gv, Mp } },
9330 { VEX_C5_TABLE (VEX_0F) },
9333 /* MOD_VEX_12_PREFIX_0 */
9334 { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_0) },
9335 { VEX_LEN_TABLE (VEX_LEN_12_P_0_M_1) },
9339 { VEX_LEN_TABLE (VEX_LEN_13_M_0) },
9340 { "(bad)", { XX } },
9343 /* MOD_VEX_16_PREFIX_0 */
9344 { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_0) },
9345 { VEX_LEN_TABLE (VEX_LEN_16_P_0_M_1) },
9349 { VEX_LEN_TABLE (VEX_LEN_17_M_0) },
9350 { "(bad)", { XX } },
9354 { VEX_LEN_TABLE (VEX_LEN_2B_M_0) },
9355 { "(bad)", { XX } },
9359 { "(bad)", { XX } },
9360 { "vmovmskpX", { Gdq, XS } },
9363 /* MOD_VEX_71_REG_2 */
9364 { "(bad)", { XX } },
9365 { PREFIX_TABLE (PREFIX_VEX_71_REG_2) },
9368 /* MOD_VEX_71_REG_4 */
9369 { "(bad)", { XX } },
9370 { PREFIX_TABLE (PREFIX_VEX_71_REG_4) },
9373 /* MOD_VEX_71_REG_6 */
9374 { "(bad)", { XX } },
9375 { PREFIX_TABLE (PREFIX_VEX_71_REG_6) },
9378 /* MOD_VEX_72_REG_2 */
9379 { "(bad)", { XX } },
9380 { PREFIX_TABLE (PREFIX_VEX_72_REG_2) },
9383 /* MOD_VEX_72_REG_4 */
9384 { "(bad)", { XX } },
9385 { PREFIX_TABLE (PREFIX_VEX_72_REG_4) },
9388 /* MOD_VEX_72_REG_6 */
9389 { "(bad)", { XX } },
9390 { PREFIX_TABLE (PREFIX_VEX_72_REG_6) },
9393 /* MOD_VEX_73_REG_2 */
9394 { "(bad)", { XX } },
9395 { PREFIX_TABLE (PREFIX_VEX_73_REG_2) },
9398 /* MOD_VEX_73_REG_3 */
9399 { "(bad)", { XX } },
9400 { PREFIX_TABLE (PREFIX_VEX_73_REG_3) },
9403 /* MOD_VEX_73_REG_6 */
9404 { "(bad)", { XX } },
9405 { PREFIX_TABLE (PREFIX_VEX_73_REG_6) },
9408 /* MOD_VEX_73_REG_7 */
9409 { "(bad)", { XX } },
9410 { PREFIX_TABLE (PREFIX_VEX_73_REG_7) },
9413 /* MOD_VEX_AE_REG_2 */
9414 { VEX_LEN_TABLE (VEX_LEN_AE_R_2_M_0) },
9415 { "(bad)", { XX } },
9418 /* MOD_VEX_AE_REG_3 */
9419 { VEX_LEN_TABLE (VEX_LEN_AE_R_3_M_0) },
9420 { "(bad)", { XX } },
9423 /* MOD_VEX_D7_PREFIX_2 */
9424 { "(bad)", { XX } },
9425 { VEX_LEN_TABLE (VEX_LEN_D7_P_2_M_1) },
9428 /* MOD_VEX_E7_PREFIX_2 */
9429 { VEX_LEN_TABLE (VEX_LEN_E7_P_2_M_0) },
9430 { "(bad)", { XX } },
9433 /* MOD_VEX_F0_PREFIX_3 */
9434 { "vlddqu", { XM, M } },
9435 { "(bad)", { XX } },
9438 /* MOD_VEX_3818_PREFIX_2 */
9439 { "vbroadcastss", { XM, Md } },
9440 { "(bad)", { XX } },
9443 /* MOD_VEX_3819_PREFIX_2 */
9444 { VEX_LEN_TABLE (VEX_LEN_3819_P_2_M_0) },
9445 { "(bad)", { XX } },
9448 /* MOD_VEX_381A_PREFIX_2 */
9449 { VEX_LEN_TABLE (VEX_LEN_381A_P_2_M_0) },
9450 { "(bad)", { XX } },
9453 /* MOD_VEX_382A_PREFIX_2 */
9454 { VEX_LEN_TABLE (VEX_LEN_382A_P_2_M_0) },
9455 { "(bad)", { XX } },
9458 /* MOD_VEX_382C_PREFIX_2 */
9459 { "vmaskmovps", { XM, Vex, Mx } },
9460 { "(bad)", { XX } },
9463 /* MOD_VEX_382D_PREFIX_2 */
9464 { "vmaskmovpd", { XM, Vex, Mx } },
9465 { "(bad)", { XX } },
9468 /* MOD_VEX_382E_PREFIX_2 */
9469 { "vmaskmovps", { Mx, Vex, XM } },
9470 { "(bad)", { XX } },
9473 /* MOD_VEX_382F_PREFIX_2 */
9474 { "vmaskmovpd", { Mx, Vex, XM } },
9475 { "(bad)", { XX } },
9479 static const struct dis386 rm_table[][8] = {
9482 { "(bad)", { XX } },
9483 { "vmcall", { Skip_MODRM } },
9484 { "vmlaunch", { Skip_MODRM } },
9485 { "vmresume", { Skip_MODRM } },
9486 { "vmxoff", { Skip_MODRM } },
9487 { "(bad)", { XX } },
9488 { "(bad)", { XX } },
9489 { "(bad)", { XX } },
9493 { "monitor", { { OP_Monitor, 0 } } },
9494 { "mwait", { { OP_Mwait, 0 } } },
9495 { "(bad)", { XX } },
9496 { "(bad)", { XX } },
9497 { "(bad)", { XX } },
9498 { "(bad)", { XX } },
9499 { "(bad)", { XX } },
9500 { "(bad)", { XX } },
9504 { "xgetbv", { Skip_MODRM } },
9505 { "xsetbv", { Skip_MODRM } },
9506 { "(bad)", { XX } },
9507 { "(bad)", { XX } },
9508 { "(bad)", { XX } },
9509 { "(bad)", { XX } },
9510 { "(bad)", { XX } },
9511 { "(bad)", { XX } },
9515 { "vmrun", { Skip_MODRM } },
9516 { "vmmcall", { Skip_MODRM } },
9517 { "vmload", { Skip_MODRM } },
9518 { "vmsave", { Skip_MODRM } },
9519 { "stgi", { Skip_MODRM } },
9520 { "clgi", { Skip_MODRM } },
9521 { "skinit", { Skip_MODRM } },
9522 { "invlpga", { Skip_MODRM } },
9526 { "swapgs", { Skip_MODRM } },
9527 { "rdtscp", { Skip_MODRM } },
9528 { "(bad)", { XX } },
9529 { "(bad)", { XX } },
9530 { "(bad)", { XX } },
9531 { "(bad)", { XX } },
9532 { "(bad)", { XX } },
9533 { "(bad)", { XX } },
9537 { "lfence", { Skip_MODRM } },
9538 { "(bad)", { XX } },
9539 { "(bad)", { XX } },
9540 { "(bad)", { XX } },
9541 { "(bad)", { XX } },
9542 { "(bad)", { XX } },
9543 { "(bad)", { XX } },
9544 { "(bad)", { XX } },
9548 { "mfence", { Skip_MODRM } },
9549 { "(bad)", { XX } },
9550 { "(bad)", { XX } },
9551 { "(bad)", { XX } },
9552 { "(bad)", { XX } },
9553 { "(bad)", { XX } },
9554 { "(bad)", { XX } },
9555 { "(bad)", { XX } },
9559 { "sfence", { Skip_MODRM } },
9560 { "(bad)", { XX } },
9561 { "(bad)", { XX } },
9562 { "(bad)", { XX } },
9563 { "(bad)", { XX } },
9564 { "(bad)", { XX } },
9565 { "(bad)", { XX } },
9566 { "(bad)", { XX } },
9570 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
9584 FETCH_DATA (the_info, codep + 1);
9588 /* REX prefixes family. */
9605 if (address_mode == mode_64bit)
9611 prefixes |= PREFIX_REPZ;
9614 prefixes |= PREFIX_REPNZ;
9617 prefixes |= PREFIX_LOCK;
9620 prefixes |= PREFIX_CS;
9623 prefixes |= PREFIX_SS;
9626 prefixes |= PREFIX_DS;
9629 prefixes |= PREFIX_ES;
9632 prefixes |= PREFIX_FS;
9635 prefixes |= PREFIX_GS;
9638 prefixes |= PREFIX_DATA;
9641 prefixes |= PREFIX_ADDR;
9644 /* fwait is really an instruction. If there are prefixes
9645 before the fwait, they belong to the fwait, *not* to the
9646 following instruction. */
9647 if (prefixes || rex)
9649 prefixes |= PREFIX_FWAIT;
9653 prefixes = PREFIX_FWAIT;
9658 /* Rex is ignored when followed by another prefix. */
9670 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
9674 prefix_name (int pref, int sizeflag)
9676 static const char *rexes [16] =
9681 "rex.XB", /* 0x43 */
9683 "rex.RB", /* 0x45 */
9684 "rex.RX", /* 0x46 */
9685 "rex.RXB", /* 0x47 */
9687 "rex.WB", /* 0x49 */
9688 "rex.WX", /* 0x4a */
9689 "rex.WXB", /* 0x4b */
9690 "rex.WR", /* 0x4c */
9691 "rex.WRB", /* 0x4d */
9692 "rex.WRX", /* 0x4e */
9693 "rex.WRXB", /* 0x4f */
9698 /* REX prefixes family. */
9715 return rexes [pref - 0x40];
9735 return (sizeflag & DFLAG) ? "data16" : "data32";
9737 if (address_mode == mode_64bit)
9738 return (sizeflag & AFLAG) ? "addr32" : "addr64";
9740 return (sizeflag & AFLAG) ? "addr16" : "addr32";
9748 static char op_out[MAX_OPERANDS][100];
9749 static int op_ad, op_index[MAX_OPERANDS];
9750 static int two_source_ops;
9751 static bfd_vma op_address[MAX_OPERANDS];
9752 static bfd_vma op_riprel[MAX_OPERANDS];
9753 static bfd_vma start_pc;
9756 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
9757 * (see topic "Redundant prefixes" in the "Differences from 8086"
9758 * section of the "Virtual 8086 Mode" chapter.)
9759 * 'pc' should be the address of this instruction, it will
9760 * be used to print the target address if this is a relative jump or call
9761 * The function returns the length of this instruction in bytes.
9764 static char intel_syntax;
9765 static char intel_mnemonic = !SYSV386_COMPAT;
9766 static char open_char;
9767 static char close_char;
9768 static char separator_char;
9769 static char scale_char;
9771 /* Here for backwards compatibility. When gdb stops using
9772 print_insn_i386_att and print_insn_i386_intel these functions can
9773 disappear, and print_insn_i386 be merged into print_insn. */
9775 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
9779 return print_insn (pc, info);
9783 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
9787 return print_insn (pc, info);
9791 print_insn_i386 (bfd_vma pc, disassemble_info *info)
9795 return print_insn (pc, info);
9799 print_i386_disassembler_options (FILE *stream)
9801 fprintf (stream, _("\n\
9802 The following i386/x86-64 specific disassembler options are supported for use\n\
9803 with the -M switch (multiple options should be separated by commas):\n"));
9805 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
9806 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
9807 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
9808 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
9809 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
9810 fprintf (stream, _(" att-mnemonic\n"
9811 " Display instruction in AT&T mnemonic\n"));
9812 fprintf (stream, _(" intel-mnemonic\n"
9813 " Display instruction in Intel mnemonic\n"));
9814 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
9815 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
9816 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
9817 fprintf (stream, _(" data32 Assume 32bit data size\n"));
9818 fprintf (stream, _(" data16 Assume 16bit data size\n"));
9819 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
9822 /* Get a pointer to struct dis386 with a valid name. */
9824 static const struct dis386 *
9825 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
9827 int index, vex_table_index;
9829 if (dp->name != NULL)
9832 switch (dp->op[0].bytemode)
9835 dp = ®_table[dp->op[1].bytemode][modrm.reg];
9839 index = modrm.mod == 0x3 ? 1 : 0;
9840 dp = &mod_table[dp->op[1].bytemode][index];
9844 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
9847 case USE_PREFIX_TABLE:
9850 /* The prefix in VEX is implicit. */
9856 case REPE_PREFIX_OPCODE:
9859 case DATA_PREFIX_OPCODE:
9862 case REPNE_PREFIX_OPCODE:
9873 used_prefixes |= (prefixes & PREFIX_REPZ);
9874 if (prefixes & PREFIX_REPZ)
9881 /* We should check PREFIX_REPNZ and PREFIX_REPZ before
9883 used_prefixes |= (prefixes & PREFIX_REPNZ);
9884 if (prefixes & PREFIX_REPNZ)
9887 repnz_prefix = NULL;
9891 used_prefixes |= (prefixes & PREFIX_DATA);
9892 if (prefixes & PREFIX_DATA)
9900 dp = &prefix_table[dp->op[1].bytemode][index];
9903 case USE_X86_64_TABLE:
9904 index = address_mode == mode_64bit ? 1 : 0;
9905 dp = &x86_64_table[dp->op[1].bytemode][index];
9908 case USE_3BYTE_TABLE:
9909 FETCH_DATA (info, codep + 2);
9911 dp = &three_byte_table[dp->op[1].bytemode][index];
9912 modrm.mod = (*codep >> 6) & 3;
9913 modrm.reg = (*codep >> 3) & 7;
9914 modrm.rm = *codep & 7;
9917 case USE_VEX_LEN_TABLE:
9934 dp = &vex_len_table[dp->op[1].bytemode][index];
9937 case USE_VEX_C4_TABLE:
9938 FETCH_DATA (info, codep + 3);
9939 /* All bits in the REX prefix are ignored. */
9941 rex = ~(*codep >> 5) & 0x7;
9942 switch ((*codep & 0x1f))
9947 vex_table_index = 0;
9950 vex_table_index = 1;
9953 vex_table_index = 2;
9957 vex.w = *codep & 0x80;
9958 if (vex.w && address_mode == mode_64bit)
9961 vex.register_specifier = (~(*codep >> 3)) & 0xf;
9962 if (address_mode != mode_64bit
9963 && vex.register_specifier > 0x7)
9966 vex.length = (*codep & 0x4) ? 256 : 128;
9967 switch ((*codep & 0x3))
9973 vex.prefix = DATA_PREFIX_OPCODE;
9976 vex.prefix = REPE_PREFIX_OPCODE;
9979 vex.prefix = REPNE_PREFIX_OPCODE;
9986 dp = &vex_table[vex_table_index][index];
9987 /* There is no MODRM byte for VEX [82|77]. */
9988 if (index != 0x77 && index != 0x82)
9990 FETCH_DATA (info, codep + 1);
9991 modrm.mod = (*codep >> 6) & 3;
9992 modrm.reg = (*codep >> 3) & 7;
9993 modrm.rm = *codep & 7;
9997 case USE_VEX_C5_TABLE:
9998 FETCH_DATA (info, codep + 2);
9999 /* All bits in the REX prefix are ignored. */
10001 rex = (*codep & 0x80) ? 0 : REX_R;
10003 vex.register_specifier = (~(*codep >> 3)) & 0xf;
10004 if (address_mode != mode_64bit
10005 && vex.register_specifier > 0x7)
10008 vex.length = (*codep & 0x4) ? 256 : 128;
10009 switch ((*codep & 0x3))
10015 vex.prefix = DATA_PREFIX_OPCODE;
10018 vex.prefix = REPE_PREFIX_OPCODE;
10021 vex.prefix = REPNE_PREFIX_OPCODE;
10028 dp = &vex_table[dp->op[1].bytemode][index];
10029 /* There is no MODRM byte for VEX [82|77]. */
10030 if (index != 0x77 && index != 0x82)
10032 FETCH_DATA (info, codep + 1);
10033 modrm.mod = (*codep >> 6) & 3;
10034 modrm.reg = (*codep >> 3) & 7;
10035 modrm.rm = *codep & 7;
10040 oappend (INTERNAL_DISASSEMBLER_ERROR);
10044 if (dp->name != NULL)
10047 return get_valid_dis386 (dp, info);
10051 print_insn (bfd_vma pc, disassemble_info *info)
10053 const struct dis386 *dp;
10055 char *op_txt[MAX_OPERANDS];
10059 struct dis_private priv;
10061 char prefix_obuf[32];
10062 char *prefix_obufp;
10064 if (info->mach == bfd_mach_x86_64_intel_syntax
10065 || info->mach == bfd_mach_x86_64)
10066 address_mode = mode_64bit;
10068 address_mode = mode_32bit;
10070 if (intel_syntax == (char) -1)
10071 intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax
10072 || info->mach == bfd_mach_x86_64_intel_syntax);
10074 if (info->mach == bfd_mach_i386_i386
10075 || info->mach == bfd_mach_x86_64
10076 || info->mach == bfd_mach_i386_i386_intel_syntax
10077 || info->mach == bfd_mach_x86_64_intel_syntax)
10078 priv.orig_sizeflag = AFLAG | DFLAG;
10079 else if (info->mach == bfd_mach_i386_i8086)
10080 priv.orig_sizeflag = 0;
10084 for (p = info->disassembler_options; p != NULL; )
10086 if (CONST_STRNEQ (p, "x86-64"))
10088 address_mode = mode_64bit;
10089 priv.orig_sizeflag = AFLAG | DFLAG;
10091 else if (CONST_STRNEQ (p, "i386"))
10093 address_mode = mode_32bit;
10094 priv.orig_sizeflag = AFLAG | DFLAG;
10096 else if (CONST_STRNEQ (p, "i8086"))
10098 address_mode = mode_16bit;
10099 priv.orig_sizeflag = 0;
10101 else if (CONST_STRNEQ (p, "intel"))
10104 if (CONST_STRNEQ (p + 5, "-mnemonic"))
10105 intel_mnemonic = 1;
10107 else if (CONST_STRNEQ (p, "att"))
10110 if (CONST_STRNEQ (p + 3, "-mnemonic"))
10111 intel_mnemonic = 0;
10113 else if (CONST_STRNEQ (p, "addr"))
10115 if (address_mode == mode_64bit)
10117 if (p[4] == '3' && p[5] == '2')
10118 priv.orig_sizeflag &= ~AFLAG;
10119 else if (p[4] == '6' && p[5] == '4')
10120 priv.orig_sizeflag |= AFLAG;
10124 if (p[4] == '1' && p[5] == '6')
10125 priv.orig_sizeflag &= ~AFLAG;
10126 else if (p[4] == '3' && p[5] == '2')
10127 priv.orig_sizeflag |= AFLAG;
10130 else if (CONST_STRNEQ (p, "data"))
10132 if (p[4] == '1' && p[5] == '6')
10133 priv.orig_sizeflag &= ~DFLAG;
10134 else if (p[4] == '3' && p[5] == '2')
10135 priv.orig_sizeflag |= DFLAG;
10137 else if (CONST_STRNEQ (p, "suffix"))
10138 priv.orig_sizeflag |= SUFFIX_ALWAYS;
10140 p = strchr (p, ',');
10147 names64 = intel_names64;
10148 names32 = intel_names32;
10149 names16 = intel_names16;
10150 names8 = intel_names8;
10151 names8rex = intel_names8rex;
10152 names_seg = intel_names_seg;
10153 index64 = intel_index64;
10154 index32 = intel_index32;
10155 index16 = intel_index16;
10158 separator_char = '+';
10163 names64 = att_names64;
10164 names32 = att_names32;
10165 names16 = att_names16;
10166 names8 = att_names8;
10167 names8rex = att_names8rex;
10168 names_seg = att_names_seg;
10169 index64 = att_index64;
10170 index32 = att_index32;
10171 index16 = att_index16;
10174 separator_char = ',';
10178 /* The output looks better if we put 7 bytes on a line, since that
10179 puts most long word instructions on a single line. */
10180 info->bytes_per_line = 7;
10182 info->private_data = &priv;
10183 priv.max_fetched = priv.the_buffer;
10184 priv.insn_start = pc;
10187 for (i = 0; i < MAX_OPERANDS; ++i)
10195 start_codep = priv.the_buffer;
10196 codep = priv.the_buffer;
10198 if (setjmp (priv.bailout) != 0)
10202 /* Getting here means we tried for data but didn't get it. That
10203 means we have an incomplete instruction of some sort. Just
10204 print the first byte as a prefix or a .byte pseudo-op. */
10205 if (codep > priv.the_buffer)
10207 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
10209 (*info->fprintf_func) (info->stream, "%s", name);
10212 /* Just print the first byte as a .byte instruction. */
10213 (*info->fprintf_func) (info->stream, ".byte 0x%x",
10214 (unsigned int) priv.the_buffer[0]);
10226 insn_codep = codep;
10227 sizeflag = priv.orig_sizeflag;
10229 FETCH_DATA (info, codep + 1);
10230 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
10232 if (((prefixes & PREFIX_FWAIT)
10233 && ((*codep < 0xd8) || (*codep > 0xdf)))
10234 || (rex && rex_used))
10238 /* fwait not followed by floating point instruction, or rex followed
10239 by other prefixes. Print the first prefix. */
10240 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
10242 name = INTERNAL_DISASSEMBLER_ERROR;
10243 (*info->fprintf_func) (info->stream, "%s", name);
10248 if (*codep == 0x0f)
10250 unsigned char threebyte;
10251 FETCH_DATA (info, codep + 2);
10252 threebyte = *++codep;
10253 dp = &dis386_twobyte[threebyte];
10254 need_modrm = twobyte_has_modrm[*codep];
10259 dp = &dis386[*codep];
10260 need_modrm = onebyte_has_modrm[*codep];
10264 if ((prefixes & PREFIX_REPZ))
10266 repz_prefix = "repz ";
10267 used_prefixes |= PREFIX_REPZ;
10270 repz_prefix = NULL;
10272 if ((prefixes & PREFIX_REPNZ))
10274 repnz_prefix = "repnz ";
10275 used_prefixes |= PREFIX_REPNZ;
10278 repnz_prefix = NULL;
10280 if ((prefixes & PREFIX_LOCK))
10282 lock_prefix = "lock ";
10283 used_prefixes |= PREFIX_LOCK;
10286 lock_prefix = NULL;
10288 addr_prefix = NULL;
10289 if (prefixes & PREFIX_ADDR)
10292 if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
10294 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
10295 addr_prefix = "addr32 ";
10297 addr_prefix = "addr16 ";
10298 used_prefixes |= PREFIX_ADDR;
10302 data_prefix = NULL;
10303 if ((prefixes & PREFIX_DATA))
10306 if (dp->op[2].bytemode == cond_jump_mode
10307 && dp->op[0].bytemode == v_mode
10310 if (sizeflag & DFLAG)
10311 data_prefix = "data32 ";
10313 data_prefix = "data16 ";
10314 used_prefixes |= PREFIX_DATA;
10320 FETCH_DATA (info, codep + 1);
10321 modrm.mod = (*codep >> 6) & 3;
10322 modrm.reg = (*codep >> 3) & 7;
10323 modrm.rm = *codep & 7;
10326 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
10328 dofloat (sizeflag);
10335 dp = get_valid_dis386 (dp, info);
10336 if (dp != NULL && putop (dp->name, sizeflag) == 0)
10338 for (i = 0; i < MAX_OPERANDS; ++i)
10341 op_ad = MAX_OPERANDS - 1 - i;
10343 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
10348 /* See if any prefixes were not used. If so, print the first one
10349 separately. If we don't do this, we'll wind up printing an
10350 instruction stream which does not precisely correspond to the
10351 bytes we are disassembling. */
10352 if ((prefixes & ~used_prefixes) != 0)
10356 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
10358 name = INTERNAL_DISASSEMBLER_ERROR;
10359 (*info->fprintf_func) (info->stream, "%s", name);
10362 if ((rex_original & ~rex_used) || rex_ignored)
10365 name = prefix_name (rex_original, priv.orig_sizeflag);
10367 name = INTERNAL_DISASSEMBLER_ERROR;
10368 (*info->fprintf_func) (info->stream, "%s ", name);
10371 prefix_obuf[0] = 0;
10372 prefix_obufp = prefix_obuf;
10374 prefix_obufp = stpcpy (prefix_obufp, lock_prefix);
10376 prefix_obufp = stpcpy (prefix_obufp, repz_prefix);
10378 prefix_obufp = stpcpy (prefix_obufp, repnz_prefix);
10380 prefix_obufp = stpcpy (prefix_obufp, addr_prefix);
10382 prefix_obufp = stpcpy (prefix_obufp, data_prefix);
10384 if (prefix_obuf[0] != 0)
10385 (*info->fprintf_func) (info->stream, "%s", prefix_obuf);
10387 obufp = mnemonicendp;
10388 for (i = strlen (obuf) + strlen (prefix_obuf); i < 6; i++)
10391 (*info->fprintf_func) (info->stream, "%s", obuf);
10393 /* The enter and bound instructions are printed with operands in the same
10394 order as the intel book; everything else is printed in reverse order. */
10395 if (intel_syntax || two_source_ops)
10399 for (i = 0; i < MAX_OPERANDS; ++i)
10400 op_txt[i] = op_out[i];
10402 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
10404 op_ad = op_index[i];
10405 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
10406 op_index[MAX_OPERANDS - 1 - i] = op_ad;
10407 riprel = op_riprel[i];
10408 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
10409 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
10414 for (i = 0; i < MAX_OPERANDS; ++i)
10415 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
10419 for (i = 0; i < MAX_OPERANDS; ++i)
10423 (*info->fprintf_func) (info->stream, ",");
10424 if (op_index[i] != -1 && !op_riprel[i])
10425 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
10427 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
10431 for (i = 0; i < MAX_OPERANDS; i++)
10432 if (op_index[i] != -1 && op_riprel[i])
10434 (*info->fprintf_func) (info->stream, " # ");
10435 (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
10436 + op_address[op_index[i]]), info);
10439 return codep - priv.the_buffer;
10442 static const char *float_mem[] = {
10517 static const unsigned char float_mem_mode[] = {
10592 #define ST { OP_ST, 0 }
10593 #define STi { OP_STi, 0 }
10595 #define FGRPd9_2 NULL, { { NULL, 0 } }
10596 #define FGRPd9_4 NULL, { { NULL, 1 } }
10597 #define FGRPd9_5 NULL, { { NULL, 2 } }
10598 #define FGRPd9_6 NULL, { { NULL, 3 } }
10599 #define FGRPd9_7 NULL, { { NULL, 4 } }
10600 #define FGRPda_5 NULL, { { NULL, 5 } }
10601 #define FGRPdb_4 NULL, { { NULL, 6 } }
10602 #define FGRPde_3 NULL, { { NULL, 7 } }
10603 #define FGRPdf_4 NULL, { { NULL, 8 } }
10605 static const struct dis386 float_reg[][8] = {
10608 { "fadd", { ST, STi } },
10609 { "fmul", { ST, STi } },
10610 { "fcom", { STi } },
10611 { "fcomp", { STi } },
10612 { "fsub", { ST, STi } },
10613 { "fsubr", { ST, STi } },
10614 { "fdiv", { ST, STi } },
10615 { "fdivr", { ST, STi } },
10619 { "fld", { STi } },
10620 { "fxch", { STi } },
10622 { "(bad)", { XX } },
10630 { "fcmovb", { ST, STi } },
10631 { "fcmove", { ST, STi } },
10632 { "fcmovbe",{ ST, STi } },
10633 { "fcmovu", { ST, STi } },
10634 { "(bad)", { XX } },
10636 { "(bad)", { XX } },
10637 { "(bad)", { XX } },
10641 { "fcmovnb",{ ST, STi } },
10642 { "fcmovne",{ ST, STi } },
10643 { "fcmovnbe",{ ST, STi } },
10644 { "fcmovnu",{ ST, STi } },
10646 { "fucomi", { ST, STi } },
10647 { "fcomi", { ST, STi } },
10648 { "(bad)", { XX } },
10652 { "fadd", { STi, ST } },
10653 { "fmul", { STi, ST } },
10654 { "(bad)", { XX } },
10655 { "(bad)", { XX } },
10656 { "fsub!M", { STi, ST } },
10657 { "fsubM", { STi, ST } },
10658 { "fdiv!M", { STi, ST } },
10659 { "fdivM", { STi, ST } },
10663 { "ffree", { STi } },
10664 { "(bad)", { XX } },
10665 { "fst", { STi } },
10666 { "fstp", { STi } },
10667 { "fucom", { STi } },
10668 { "fucomp", { STi } },
10669 { "(bad)", { XX } },
10670 { "(bad)", { XX } },
10674 { "faddp", { STi, ST } },
10675 { "fmulp", { STi, ST } },
10676 { "(bad)", { XX } },
10678 { "fsub!Mp", { STi, ST } },
10679 { "fsubMp", { STi, ST } },
10680 { "fdiv!Mp", { STi, ST } },
10681 { "fdivMp", { STi, ST } },
10685 { "ffreep", { STi } },
10686 { "(bad)", { XX } },
10687 { "(bad)", { XX } },
10688 { "(bad)", { XX } },
10690 { "fucomip", { ST, STi } },
10691 { "fcomip", { ST, STi } },
10692 { "(bad)", { XX } },
10696 static char *fgrps[][8] = {
10699 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10704 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10709 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10714 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10719 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10724 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10729 "feni(287 only)","fdisi(287 only)","fNclex","fNinit",
10730 "fNsetpm(287 only)","(bad)","(bad)","(bad)",
10735 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10740 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10745 swap_operand (void)
10747 mnemonicendp[0] = '.';
10748 mnemonicendp[1] = 's';
10753 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
10754 int sizeflag ATTRIBUTE_UNUSED)
10756 /* Skip mod/rm byte. */
10762 dofloat (int sizeflag)
10764 const struct dis386 *dp;
10765 unsigned char floatop;
10767 floatop = codep[-1];
10769 if (modrm.mod != 3)
10771 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
10773 putop (float_mem[fp_indx], sizeflag);
10776 OP_E (float_mem_mode[fp_indx], sizeflag);
10779 /* Skip mod/rm byte. */
10783 dp = &float_reg[floatop - 0xd8][modrm.reg];
10784 if (dp->name == NULL)
10786 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
10788 /* Instruction fnstsw is only one with strange arg. */
10789 if (floatop == 0xdf && codep[-1] == 0xe0)
10790 strcpy (op_out[0], names16[0]);
10794 putop (dp->name, sizeflag);
10799 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
10804 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
10809 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10811 oappend ("%st" + intel_syntax);
10815 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
10817 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
10818 oappend (scratchbuf + intel_syntax);
10821 /* Capital letters in template are macros. */
10823 putop (const char *template, int sizeflag)
10828 unsigned int l = 0, len = 1;
10831 #define SAVE_LAST(c) \
10832 if (l < len && l < sizeof (last)) \
10837 for (p = template; *p; p++)
10854 while (*++p != '|')
10855 if (*p == '}' || *p == '\0')
10858 /* Fall through. */
10863 while (*++p != '}')
10874 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
10880 if (sizeflag & SUFFIX_ALWAYS)
10884 if (intel_syntax && !alt)
10886 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10888 if (sizeflag & DFLAG)
10889 *obufp++ = intel_syntax ? 'd' : 'l';
10891 *obufp++ = intel_syntax ? 'w' : 's';
10892 used_prefixes |= (prefixes & PREFIX_DATA);
10896 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10899 if (modrm.mod == 3)
10903 else if (sizeflag & DFLAG)
10904 *obufp++ = intel_syntax ? 'd' : 'l';
10907 used_prefixes |= (prefixes & PREFIX_DATA);
10912 case 'E': /* For jcxz/jecxz */
10913 if (address_mode == mode_64bit)
10915 if (sizeflag & AFLAG)
10921 if (sizeflag & AFLAG)
10923 used_prefixes |= (prefixes & PREFIX_ADDR);
10928 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10930 if (sizeflag & AFLAG)
10931 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
10933 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
10934 used_prefixes |= (prefixes & PREFIX_ADDR);
10938 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
10940 if ((rex & REX_W) || (sizeflag & DFLAG))
10944 if (!(rex & REX_W))
10945 used_prefixes |= (prefixes & PREFIX_DATA);
10950 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10951 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10953 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
10956 if (prefixes & PREFIX_DS)
10977 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
10982 /* Fall through. */
10985 if (l != 0 || len != 1)
10993 if (sizeflag & SUFFIX_ALWAYS)
10997 if (intel_mnemonic != cond)
11001 if ((prefixes & PREFIX_FWAIT) == 0)
11004 used_prefixes |= PREFIX_FWAIT;
11010 else if (intel_syntax && (sizeflag & DFLAG))
11014 if (!(rex & REX_W))
11015 used_prefixes |= (prefixes & PREFIX_DATA);
11020 if (address_mode == mode_64bit && (sizeflag & DFLAG))
11025 /* Fall through. */
11029 if ((prefixes & PREFIX_DATA)
11031 || (sizeflag & SUFFIX_ALWAYS))
11038 if (sizeflag & DFLAG)
11043 used_prefixes |= (prefixes & PREFIX_DATA);
11049 if (address_mode == mode_64bit && (sizeflag & DFLAG))
11051 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
11055 /* Fall through. */
11058 if (l == 0 && len == 1)
11061 if (intel_syntax && !alt)
11064 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
11070 if (sizeflag & DFLAG)
11071 *obufp++ = intel_syntax ? 'd' : 'l';
11075 used_prefixes |= (prefixes & PREFIX_DATA);
11080 if (l != 1 || len != 2 || last[0] != 'L')
11086 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
11101 else if (sizeflag & DFLAG)
11110 if (intel_syntax && !p[1]
11111 && ((rex & REX_W) || (sizeflag & DFLAG)))
11113 if (!(rex & REX_W))
11114 used_prefixes |= (prefixes & PREFIX_DATA);
11119 if (address_mode == mode_64bit && (sizeflag & DFLAG))
11121 if (sizeflag & SUFFIX_ALWAYS)
11125 /* Fall through. */
11129 if (sizeflag & SUFFIX_ALWAYS)
11135 if (sizeflag & DFLAG)
11139 used_prefixes |= (prefixes & PREFIX_DATA);
11144 if (l != 0 || len != 1)
11149 if (need_vex && vex.prefix)
11151 if (vex.prefix == DATA_PREFIX_OPCODE)
11156 else if (prefixes & PREFIX_DATA)
11160 used_prefixes |= (prefixes & PREFIX_DATA);
11163 if (l == 0 && len == 1)
11165 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
11176 if (l != 1 || len != 2 || last[0] != 'X')
11184 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
11186 switch (vex.length)
11200 /* operand size flag for cwtl, cbtw */
11209 else if (sizeflag & DFLAG)
11213 if (!(rex & REX_W))
11214 used_prefixes |= (prefixes & PREFIX_DATA);
11220 mnemonicendp = obufp;
11225 oappend (const char *s)
11227 obufp = stpcpy (obufp, s);
11233 if (prefixes & PREFIX_CS)
11235 used_prefixes |= PREFIX_CS;
11236 oappend ("%cs:" + intel_syntax);
11238 if (prefixes & PREFIX_DS)
11240 used_prefixes |= PREFIX_DS;
11241 oappend ("%ds:" + intel_syntax);
11243 if (prefixes & PREFIX_SS)
11245 used_prefixes |= PREFIX_SS;
11246 oappend ("%ss:" + intel_syntax);
11248 if (prefixes & PREFIX_ES)
11250 used_prefixes |= PREFIX_ES;
11251 oappend ("%es:" + intel_syntax);
11253 if (prefixes & PREFIX_FS)
11255 used_prefixes |= PREFIX_FS;
11256 oappend ("%fs:" + intel_syntax);
11258 if (prefixes & PREFIX_GS)
11260 used_prefixes |= PREFIX_GS;
11261 oappend ("%gs:" + intel_syntax);
11266 OP_indirE (int bytemode, int sizeflag)
11270 OP_E (bytemode, sizeflag);
11274 print_operand_value (char *buf, int hex, bfd_vma disp)
11276 if (address_mode == mode_64bit)
11284 sprintf_vma (tmp, disp);
11285 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
11286 strcpy (buf + 2, tmp + i);
11290 bfd_signed_vma v = disp;
11297 /* Check for possible overflow on 0x8000000000000000. */
11300 strcpy (buf, "9223372036854775808");
11314 tmp[28 - i] = (v % 10) + '0';
11318 strcpy (buf, tmp + 29 - i);
11324 sprintf (buf, "0x%x", (unsigned int) disp);
11326 sprintf (buf, "%d", (int) disp);
11330 /* Put DISP in BUF as signed hex number. */
11333 print_displacement (char *buf, bfd_vma disp)
11335 bfd_signed_vma val = disp;
11344 /* Check for possible overflow. */
11347 switch (address_mode)
11350 strcpy (buf + j, "0x8000000000000000");
11353 strcpy (buf + j, "0x80000000");
11356 strcpy (buf + j, "0x8000");
11366 sprintf_vma (tmp, (bfd_vma) val);
11367 for (i = 0; tmp[i] == '0'; i++)
11369 if (tmp[i] == '\0')
11371 strcpy (buf + j, tmp + i);
11375 intel_operand_size (int bytemode, int sizeflag)
11382 oappend ("BYTE PTR ");
11386 oappend ("WORD PTR ");
11389 if (address_mode == mode_64bit && (sizeflag & DFLAG))
11391 oappend ("QWORD PTR ");
11392 used_prefixes |= (prefixes & PREFIX_DATA);
11401 oappend ("QWORD PTR ");
11402 else if ((sizeflag & DFLAG) || bytemode == dq_mode)
11403 oappend ("DWORD PTR ");
11405 oappend ("WORD PTR ");
11406 used_prefixes |= (prefixes & PREFIX_DATA);
11409 if ((rex & REX_W) || (sizeflag & DFLAG))
11411 oappend ("WORD PTR ");
11412 if (!(rex & REX_W))
11413 used_prefixes |= (prefixes & PREFIX_DATA);
11416 if (sizeflag & DFLAG)
11417 oappend ("QWORD PTR ");
11419 oappend ("DWORD PTR ");
11420 used_prefixes |= (prefixes & PREFIX_DATA);
11425 oappend ("DWORD PTR ");
11429 oappend ("QWORD PTR ");
11432 if (address_mode == mode_64bit)
11433 oappend ("QWORD PTR ");
11435 oappend ("DWORD PTR ");
11438 if (sizeflag & DFLAG)
11439 oappend ("FWORD PTR ");
11441 oappend ("DWORD PTR ");
11442 used_prefixes |= (prefixes & PREFIX_DATA);
11445 oappend ("TBYTE PTR ");
11451 switch (vex.length)
11454 oappend ("XMMWORD PTR ");
11457 oappend ("YMMWORD PTR ");
11464 oappend ("XMMWORD PTR ");
11467 oappend ("XMMWORD PTR ");
11473 switch (vex.length)
11476 oappend ("QWORD PTR ");
11479 oappend ("XMMWORD PTR ");
11489 switch (vex.length)
11492 oappend ("QWORD PTR ");
11495 oappend ("YMMWORD PTR ");
11502 oappend ("OWORD PTR ");
11510 OP_E_register (int bytemode, int sizeflag)
11512 int reg = modrm.rm;
11513 const char **names;
11519 if ((sizeflag & SUFFIX_ALWAYS)
11520 && (bytemode == b_swap_mode || bytemode == v_swap_mode))
11543 names = address_mode == mode_64bit ? names64 : names32;
11546 if (address_mode == mode_64bit && (sizeflag & DFLAG))
11549 used_prefixes |= (prefixes & PREFIX_DATA);
11563 else if ((sizeflag & DFLAG)
11564 || (bytemode != v_mode
11565 && bytemode != v_swap_mode))
11569 used_prefixes |= (prefixes & PREFIX_DATA);
11574 oappend (INTERNAL_DISASSEMBLER_ERROR);
11577 oappend (names[reg]);
11581 OP_E_memory (int bytemode, int sizeflag, int has_drex)
11584 int add = (rex & REX_B) ? 8 : 0;
11589 intel_operand_size (bytemode, sizeflag);
11592 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11594 /* 32/64 bit address mode */
11612 FETCH_DATA (the_info, codep + 1);
11613 index = (*codep >> 3) & 7;
11614 scale = (*codep >> 6) & 3;
11619 haveindex = index != 4;
11622 rbase = base + add;
11624 /* If we have a DREX byte, skip it now
11625 (it has already been handled) */
11628 FETCH_DATA (the_info, codep + 1);
11638 if (address_mode == mode_64bit && !havesib)
11644 FETCH_DATA (the_info, codep + 1);
11646 if ((disp & 0x80) != 0)
11654 /* In 32bit mode, we need index register to tell [offset] from
11655 [eiz*1 + offset]. */
11656 needindex = (havesib
11659 && address_mode == mode_32bit);
11660 havedisp = (havebase
11662 || (havesib && (haveindex || scale != 0)));
11665 if (modrm.mod != 0 || base == 5)
11667 if (havedisp || riprel)
11668 print_displacement (scratchbuf, disp);
11670 print_operand_value (scratchbuf, 1, disp);
11671 oappend (scratchbuf);
11675 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
11679 if (havebase || haveindex || riprel)
11680 used_prefixes |= PREFIX_ADDR;
11682 if (havedisp || (intel_syntax && riprel))
11684 *obufp++ = open_char;
11685 if (intel_syntax && riprel)
11688 oappend (sizeflag & AFLAG ? "rip" : "eip");
11692 oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
11693 ? names64[rbase] : names32[rbase]);
11696 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
11697 print index to tell base + index from base. */
11701 || (havebase && base != ESP_REG_NUM))
11703 if (!intel_syntax || havebase)
11705 *obufp++ = separator_char;
11709 oappend (address_mode == mode_64bit
11710 && (sizeflag & AFLAG)
11711 ? names64[index] : names32[index]);
11713 oappend (address_mode == mode_64bit
11714 && (sizeflag & AFLAG)
11715 ? index64 : index32);
11717 *obufp++ = scale_char;
11719 sprintf (scratchbuf, "%d", 1 << scale);
11720 oappend (scratchbuf);
11724 && (disp || modrm.mod != 0 || base == 5))
11726 if (!havedisp || (bfd_signed_vma) disp >= 0)
11731 else if (modrm.mod != 1)
11735 disp = - (bfd_signed_vma) disp;
11739 print_displacement (scratchbuf, disp);
11741 print_operand_value (scratchbuf, 1, disp);
11742 oappend (scratchbuf);
11745 *obufp++ = close_char;
11748 else if (intel_syntax)
11750 if (modrm.mod != 0 || base == 5)
11752 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11753 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
11757 oappend (names_seg[ds_reg - es_reg]);
11760 print_operand_value (scratchbuf, 1, disp);
11761 oappend (scratchbuf);
11766 { /* 16 bit address mode */
11773 if ((disp & 0x8000) != 0)
11778 FETCH_DATA (the_info, codep + 1);
11780 if ((disp & 0x80) != 0)
11785 if ((disp & 0x8000) != 0)
11791 if (modrm.mod != 0 || modrm.rm == 6)
11793 print_displacement (scratchbuf, disp);
11794 oappend (scratchbuf);
11797 if (modrm.mod != 0 || modrm.rm != 6)
11799 *obufp++ = open_char;
11801 oappend (index16[modrm.rm]);
11803 && (disp || modrm.mod != 0 || modrm.rm == 6))
11805 if ((bfd_signed_vma) disp >= 0)
11810 else if (modrm.mod != 1)
11814 disp = - (bfd_signed_vma) disp;
11817 print_displacement (scratchbuf, disp);
11818 oappend (scratchbuf);
11821 *obufp++ = close_char;
11824 else if (intel_syntax)
11826 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
11827 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
11831 oappend (names_seg[ds_reg - es_reg]);
11834 print_operand_value (scratchbuf, 1, disp & 0xffff);
11835 oappend (scratchbuf);
11841 OP_E_extended (int bytemode, int sizeflag, int has_drex)
11843 /* Skip mod/rm byte. */
11847 if (modrm.mod == 3)
11848 OP_E_register (bytemode, sizeflag);
11850 OP_E_memory (bytemode, sizeflag, has_drex);
11854 OP_E (int bytemode, int sizeflag)
11856 OP_E_extended (bytemode, sizeflag, 0);
11861 OP_G (int bytemode, int sizeflag)
11872 oappend (names8rex[modrm.reg + add]);
11874 oappend (names8[modrm.reg + add]);
11877 oappend (names16[modrm.reg + add]);
11880 oappend (names32[modrm.reg + add]);
11883 oappend (names64[modrm.reg + add]);
11892 oappend (names64[modrm.reg + add]);
11893 else if ((sizeflag & DFLAG) || bytemode != v_mode)
11894 oappend (names32[modrm.reg + add]);
11896 oappend (names16[modrm.reg + add]);
11897 used_prefixes |= (prefixes & PREFIX_DATA);
11900 if (address_mode == mode_64bit)
11901 oappend (names64[modrm.reg + add]);
11903 oappend (names32[modrm.reg + add]);
11906 oappend (INTERNAL_DISASSEMBLER_ERROR);
11919 FETCH_DATA (the_info, codep + 8);
11920 a = *codep++ & 0xff;
11921 a |= (*codep++ & 0xff) << 8;
11922 a |= (*codep++ & 0xff) << 16;
11923 a |= (*codep++ & 0xff) << 24;
11924 b = *codep++ & 0xff;
11925 b |= (*codep++ & 0xff) << 8;
11926 b |= (*codep++ & 0xff) << 16;
11927 b |= (*codep++ & 0xff) << 24;
11928 x = a + ((bfd_vma) b << 32);
11936 static bfd_signed_vma
11939 bfd_signed_vma x = 0;
11941 FETCH_DATA (the_info, codep + 4);
11942 x = *codep++ & (bfd_signed_vma) 0xff;
11943 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
11944 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
11945 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
11949 static bfd_signed_vma
11952 bfd_signed_vma x = 0;
11954 FETCH_DATA (the_info, codep + 4);
11955 x = *codep++ & (bfd_signed_vma) 0xff;
11956 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
11957 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
11958 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
11960 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
11970 FETCH_DATA (the_info, codep + 2);
11971 x = *codep++ & 0xff;
11972 x |= (*codep++ & 0xff) << 8;
11977 set_op (bfd_vma op, int riprel)
11979 op_index[op_ad] = op_ad;
11980 if (address_mode == mode_64bit)
11982 op_address[op_ad] = op;
11983 op_riprel[op_ad] = riprel;
11987 /* Mask to get a 32-bit address. */
11988 op_address[op_ad] = op & 0xffffffff;
11989 op_riprel[op_ad] = riprel & 0xffffffff;
11994 OP_REG (int code, int sizeflag)
12006 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12007 case sp_reg: case bp_reg: case si_reg: case di_reg:
12008 s = names16[code - ax_reg + add];
12010 case es_reg: case ss_reg: case cs_reg:
12011 case ds_reg: case fs_reg: case gs_reg:
12012 s = names_seg[code - es_reg + add];
12014 case al_reg: case ah_reg: case cl_reg: case ch_reg:
12015 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
12018 s = names8rex[code - al_reg + add];
12020 s = names8[code - al_reg];
12022 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12023 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12024 if (address_mode == mode_64bit && (sizeflag & DFLAG))
12026 s = names64[code - rAX_reg + add];
12029 code += eAX_reg - rAX_reg;
12030 /* Fall through. */
12031 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12032 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12035 s = names64[code - eAX_reg + add];
12036 else if (sizeflag & DFLAG)
12037 s = names32[code - eAX_reg + add];
12039 s = names16[code - eAX_reg + add];
12040 used_prefixes |= (prefixes & PREFIX_DATA);
12043 s = INTERNAL_DISASSEMBLER_ERROR;
12050 OP_IMREG (int code, int sizeflag)
12062 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12063 case sp_reg: case bp_reg: case si_reg: case di_reg:
12064 s = names16[code - ax_reg];
12066 case es_reg: case ss_reg: case cs_reg:
12067 case ds_reg: case fs_reg: case gs_reg:
12068 s = names_seg[code - es_reg];
12070 case al_reg: case ah_reg: case cl_reg: case ch_reg:
12071 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
12074 s = names8rex[code - al_reg];
12076 s = names8[code - al_reg];
12078 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12079 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12082 s = names64[code - eAX_reg];
12083 else if (sizeflag & DFLAG)
12084 s = names32[code - eAX_reg];
12086 s = names16[code - eAX_reg];
12087 used_prefixes |= (prefixes & PREFIX_DATA);
12089 case z_mode_ax_reg:
12090 if ((rex & REX_W) || (sizeflag & DFLAG))
12094 if (!(rex & REX_W))
12095 used_prefixes |= (prefixes & PREFIX_DATA);
12098 s = INTERNAL_DISASSEMBLER_ERROR;
12105 OP_I (int bytemode, int sizeflag)
12108 bfd_signed_vma mask = -1;
12113 FETCH_DATA (the_info, codep + 1);
12118 if (address_mode == mode_64bit)
12123 /* Fall through. */
12128 else if (sizeflag & DFLAG)
12138 used_prefixes |= (prefixes & PREFIX_DATA);
12149 oappend (INTERNAL_DISASSEMBLER_ERROR);
12154 scratchbuf[0] = '$';
12155 print_operand_value (scratchbuf + 1, 1, op);
12156 oappend (scratchbuf + intel_syntax);
12157 scratchbuf[0] = '\0';
12161 OP_I64 (int bytemode, int sizeflag)
12164 bfd_signed_vma mask = -1;
12166 if (address_mode != mode_64bit)
12168 OP_I (bytemode, sizeflag);
12175 FETCH_DATA (the_info, codep + 1);
12183 else if (sizeflag & DFLAG)
12193 used_prefixes |= (prefixes & PREFIX_DATA);
12200 oappend (INTERNAL_DISASSEMBLER_ERROR);
12205 scratchbuf[0] = '$';
12206 print_operand_value (scratchbuf + 1, 1, op);
12207 oappend (scratchbuf + intel_syntax);
12208 scratchbuf[0] = '\0';
12212 OP_sI (int bytemode, int sizeflag)
12215 bfd_signed_vma mask = -1;
12220 FETCH_DATA (the_info, codep + 1);
12222 if ((op & 0x80) != 0)
12230 else if (sizeflag & DFLAG)
12239 if ((op & 0x8000) != 0)
12242 used_prefixes |= (prefixes & PREFIX_DATA);
12247 if ((op & 0x8000) != 0)
12251 oappend (INTERNAL_DISASSEMBLER_ERROR);
12255 scratchbuf[0] = '$';
12256 print_operand_value (scratchbuf + 1, 1, op);
12257 oappend (scratchbuf + intel_syntax);
12261 OP_J (int bytemode, int sizeflag)
12265 bfd_vma segment = 0;
12270 FETCH_DATA (the_info, codep + 1);
12272 if ((disp & 0x80) != 0)
12276 if ((sizeflag & DFLAG) || (rex & REX_W))
12281 if ((disp & 0x8000) != 0)
12283 /* In 16bit mode, address is wrapped around at 64k within
12284 the same segment. Otherwise, a data16 prefix on a jump
12285 instruction means that the pc is masked to 16 bits after
12286 the displacement is added! */
12288 if ((prefixes & PREFIX_DATA) == 0)
12289 segment = ((start_pc + codep - start_codep)
12290 & ~((bfd_vma) 0xffff));
12292 used_prefixes |= (prefixes & PREFIX_DATA);
12295 oappend (INTERNAL_DISASSEMBLER_ERROR);
12298 disp = ((start_pc + codep - start_codep + disp) & mask) | segment;
12300 print_operand_value (scratchbuf, 1, disp);
12301 oappend (scratchbuf);
12305 OP_SEG (int bytemode, int sizeflag)
12307 if (bytemode == w_mode)
12308 oappend (names_seg[modrm.reg]);
12310 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12314 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
12318 if (sizeflag & DFLAG)
12328 used_prefixes |= (prefixes & PREFIX_DATA);
12330 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
12332 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
12333 oappend (scratchbuf);
12337 OP_OFF (int bytemode, int sizeflag)
12341 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12342 intel_operand_size (bytemode, sizeflag);
12345 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
12352 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
12353 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
12355 oappend (names_seg[ds_reg - es_reg]);
12359 print_operand_value (scratchbuf, 1, off);
12360 oappend (scratchbuf);
12364 OP_OFF64 (int bytemode, int sizeflag)
12368 if (address_mode != mode_64bit
12369 || (prefixes & PREFIX_ADDR))
12371 OP_OFF (bytemode, sizeflag);
12375 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12376 intel_operand_size (bytemode, sizeflag);
12383 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
12384 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
12386 oappend (names_seg[ds_reg - es_reg]);
12390 print_operand_value (scratchbuf, 1, off);
12391 oappend (scratchbuf);
12395 ptr_reg (int code, int sizeflag)
12399 *obufp++ = open_char;
12400 used_prefixes |= (prefixes & PREFIX_ADDR);
12401 if (address_mode == mode_64bit)
12403 if (!(sizeflag & AFLAG))
12404 s = names32[code - eAX_reg];
12406 s = names64[code - eAX_reg];
12408 else if (sizeflag & AFLAG)
12409 s = names32[code - eAX_reg];
12411 s = names16[code - eAX_reg];
12413 *obufp++ = close_char;
12418 OP_ESreg (int code, int sizeflag)
12424 case 0x6d: /* insw/insl */
12425 intel_operand_size (z_mode, sizeflag);
12427 case 0xa5: /* movsw/movsl/movsq */
12428 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12429 case 0xab: /* stosw/stosl */
12430 case 0xaf: /* scasw/scasl */
12431 intel_operand_size (v_mode, sizeflag);
12434 intel_operand_size (b_mode, sizeflag);
12437 oappend ("%es:" + intel_syntax);
12438 ptr_reg (code, sizeflag);
12442 OP_DSreg (int code, int sizeflag)
12448 case 0x6f: /* outsw/outsl */
12449 intel_operand_size (z_mode, sizeflag);
12451 case 0xa5: /* movsw/movsl/movsq */
12452 case 0xa7: /* cmpsw/cmpsl/cmpsq */
12453 case 0xad: /* lodsw/lodsl/lodsq */
12454 intel_operand_size (v_mode, sizeflag);
12457 intel_operand_size (b_mode, sizeflag);
12466 | PREFIX_GS)) == 0)
12467 prefixes |= PREFIX_DS;
12469 ptr_reg (code, sizeflag);
12473 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12481 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
12483 lock_prefix = NULL;
12484 used_prefixes |= PREFIX_LOCK;
12489 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
12490 oappend (scratchbuf + intel_syntax);
12494 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12503 sprintf (scratchbuf, "db%d", modrm.reg + add);
12505 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
12506 oappend (scratchbuf);
12510 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12512 sprintf (scratchbuf, "%%tr%d", modrm.reg);
12513 oappend (scratchbuf + intel_syntax);
12517 OP_R (int bytemode, int sizeflag)
12519 if (modrm.mod == 3)
12520 OP_E (bytemode, sizeflag);
12526 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12528 used_prefixes |= (prefixes & PREFIX_DATA);
12529 if (prefixes & PREFIX_DATA)
12537 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12540 sprintf (scratchbuf, "%%mm%d", modrm.reg);
12541 oappend (scratchbuf + intel_syntax);
12545 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12553 if (need_vex && bytemode != xmm_mode)
12555 switch (vex.length)
12558 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12561 sprintf (scratchbuf, "%%ymm%d", modrm.reg + add);
12568 sprintf (scratchbuf, "%%xmm%d", modrm.reg + add);
12569 oappend (scratchbuf + intel_syntax);
12573 OP_EM (int bytemode, int sizeflag)
12575 if (modrm.mod != 3)
12578 && (bytemode == v_mode || bytemode == v_swap_mode))
12580 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12581 used_prefixes |= (prefixes & PREFIX_DATA);
12583 OP_E (bytemode, sizeflag);
12587 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
12590 /* Skip mod/rm byte. */
12593 used_prefixes |= (prefixes & PREFIX_DATA);
12594 if (prefixes & PREFIX_DATA)
12603 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12606 sprintf (scratchbuf, "%%mm%d", modrm.rm);
12607 oappend (scratchbuf + intel_syntax);
12610 /* cvt* are the only instructions in sse2 which have
12611 both SSE and MMX operands and also have 0x66 prefix
12612 in their opcode. 0x66 was originally used to differentiate
12613 between SSE and MMX instruction(operands). So we have to handle the
12614 cvt* separately using OP_EMC and OP_MXC */
12616 OP_EMC (int bytemode, int sizeflag)
12618 if (modrm.mod != 3)
12620 if (intel_syntax && bytemode == v_mode)
12622 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
12623 used_prefixes |= (prefixes & PREFIX_DATA);
12625 OP_E (bytemode, sizeflag);
12629 /* Skip mod/rm byte. */
12632 used_prefixes |= (prefixes & PREFIX_DATA);
12633 sprintf (scratchbuf, "%%mm%d", modrm.rm);
12634 oappend (scratchbuf + intel_syntax);
12638 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12640 used_prefixes |= (prefixes & PREFIX_DATA);
12641 sprintf (scratchbuf, "%%mm%d", modrm.reg);
12642 oappend (scratchbuf + intel_syntax);
12646 OP_EX (int bytemode, int sizeflag)
12649 if (modrm.mod != 3)
12651 OP_E (bytemode, sizeflag);
12660 if ((sizeflag & SUFFIX_ALWAYS)
12661 && (bytemode == x_swap_mode
12662 || bytemode == d_swap_mode
12663 || bytemode == q_swap_mode))
12666 /* Skip mod/rm byte. */
12670 && bytemode != xmm_mode
12671 && bytemode != xmmq_mode)
12673 switch (vex.length)
12676 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12679 sprintf (scratchbuf, "%%ymm%d", modrm.rm + add);
12686 sprintf (scratchbuf, "%%xmm%d", modrm.rm + add);
12687 oappend (scratchbuf + intel_syntax);
12691 OP_MS (int bytemode, int sizeflag)
12693 if (modrm.mod == 3)
12694 OP_EM (bytemode, sizeflag);
12700 OP_XS (int bytemode, int sizeflag)
12702 if (modrm.mod == 3)
12703 OP_EX (bytemode, sizeflag);
12709 OP_M (int bytemode, int sizeflag)
12711 if (modrm.mod == 3)
12712 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
12715 OP_E (bytemode, sizeflag);
12719 OP_0f07 (int bytemode, int sizeflag)
12721 if (modrm.mod != 3 || modrm.rm != 0)
12724 OP_E (bytemode, sizeflag);
12727 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
12728 32bit mode and "xchg %rax,%rax" in 64bit mode. */
12731 NOP_Fixup1 (int bytemode, int sizeflag)
12733 if ((prefixes & PREFIX_DATA) != 0
12736 && address_mode == mode_64bit))
12737 OP_REG (bytemode, sizeflag);
12739 strcpy (obuf, "nop");
12743 NOP_Fixup2 (int bytemode, int sizeflag)
12745 if ((prefixes & PREFIX_DATA) != 0
12748 && address_mode == mode_64bit))
12749 OP_IMREG (bytemode, sizeflag);
12752 static const char *const Suffix3DNow[] = {
12753 /* 00 */ NULL, NULL, NULL, NULL,
12754 /* 04 */ NULL, NULL, NULL, NULL,
12755 /* 08 */ NULL, NULL, NULL, NULL,
12756 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
12757 /* 10 */ NULL, NULL, NULL, NULL,
12758 /* 14 */ NULL, NULL, NULL, NULL,
12759 /* 18 */ NULL, NULL, NULL, NULL,
12760 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
12761 /* 20 */ NULL, NULL, NULL, NULL,
12762 /* 24 */ NULL, NULL, NULL, NULL,
12763 /* 28 */ NULL, NULL, NULL, NULL,
12764 /* 2C */ NULL, NULL, NULL, NULL,
12765 /* 30 */ NULL, NULL, NULL, NULL,
12766 /* 34 */ NULL, NULL, NULL, NULL,
12767 /* 38 */ NULL, NULL, NULL, NULL,
12768 /* 3C */ NULL, NULL, NULL, NULL,
12769 /* 40 */ NULL, NULL, NULL, NULL,
12770 /* 44 */ NULL, NULL, NULL, NULL,
12771 /* 48 */ NULL, NULL, NULL, NULL,
12772 /* 4C */ NULL, NULL, NULL, NULL,
12773 /* 50 */ NULL, NULL, NULL, NULL,
12774 /* 54 */ NULL, NULL, NULL, NULL,
12775 /* 58 */ NULL, NULL, NULL, NULL,
12776 /* 5C */ NULL, NULL, NULL, NULL,
12777 /* 60 */ NULL, NULL, NULL, NULL,
12778 /* 64 */ NULL, NULL, NULL, NULL,
12779 /* 68 */ NULL, NULL, NULL, NULL,
12780 /* 6C */ NULL, NULL, NULL, NULL,
12781 /* 70 */ NULL, NULL, NULL, NULL,
12782 /* 74 */ NULL, NULL, NULL, NULL,
12783 /* 78 */ NULL, NULL, NULL, NULL,
12784 /* 7C */ NULL, NULL, NULL, NULL,
12785 /* 80 */ NULL, NULL, NULL, NULL,
12786 /* 84 */ NULL, NULL, NULL, NULL,
12787 /* 88 */ NULL, NULL, "pfnacc", NULL,
12788 /* 8C */ NULL, NULL, "pfpnacc", NULL,
12789 /* 90 */ "pfcmpge", NULL, NULL, NULL,
12790 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
12791 /* 98 */ NULL, NULL, "pfsub", NULL,
12792 /* 9C */ NULL, NULL, "pfadd", NULL,
12793 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
12794 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
12795 /* A8 */ NULL, NULL, "pfsubr", NULL,
12796 /* AC */ NULL, NULL, "pfacc", NULL,
12797 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
12798 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
12799 /* B8 */ NULL, NULL, NULL, "pswapd",
12800 /* BC */ NULL, NULL, NULL, "pavgusb",
12801 /* C0 */ NULL, NULL, NULL, NULL,
12802 /* C4 */ NULL, NULL, NULL, NULL,
12803 /* C8 */ NULL, NULL, NULL, NULL,
12804 /* CC */ NULL, NULL, NULL, NULL,
12805 /* D0 */ NULL, NULL, NULL, NULL,
12806 /* D4 */ NULL, NULL, NULL, NULL,
12807 /* D8 */ NULL, NULL, NULL, NULL,
12808 /* DC */ NULL, NULL, NULL, NULL,
12809 /* E0 */ NULL, NULL, NULL, NULL,
12810 /* E4 */ NULL, NULL, NULL, NULL,
12811 /* E8 */ NULL, NULL, NULL, NULL,
12812 /* EC */ NULL, NULL, NULL, NULL,
12813 /* F0 */ NULL, NULL, NULL, NULL,
12814 /* F4 */ NULL, NULL, NULL, NULL,
12815 /* F8 */ NULL, NULL, NULL, NULL,
12816 /* FC */ NULL, NULL, NULL, NULL,
12820 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12822 const char *mnemonic;
12824 FETCH_DATA (the_info, codep + 1);
12825 /* AMD 3DNow! instructions are specified by an opcode suffix in the
12826 place where an 8-bit immediate would normally go. ie. the last
12827 byte of the instruction. */
12828 obufp = mnemonicendp;
12829 mnemonic = Suffix3DNow[*codep++ & 0xff];
12831 oappend (mnemonic);
12834 /* Since a variable sized modrm/sib chunk is between the start
12835 of the opcode (0x0f0f) and the opcode suffix, we need to do
12836 all the modrm processing first, and don't know until now that
12837 we have a bad opcode. This necessitates some cleaning up. */
12838 op_out[0][0] = '\0';
12839 op_out[1][0] = '\0';
12842 mnemonicendp = obufp;
12845 static struct op simd_cmp_op[] =
12847 { STRING_COMMA_LEN ("eq") },
12848 { STRING_COMMA_LEN ("lt") },
12849 { STRING_COMMA_LEN ("le") },
12850 { STRING_COMMA_LEN ("unord") },
12851 { STRING_COMMA_LEN ("neq") },
12852 { STRING_COMMA_LEN ("nlt") },
12853 { STRING_COMMA_LEN ("nle") },
12854 { STRING_COMMA_LEN ("ord") }
12858 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12860 unsigned int cmp_type;
12862 FETCH_DATA (the_info, codep + 1);
12863 cmp_type = *codep++ & 0xff;
12864 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
12867 char *p = mnemonicendp - 2;
12871 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
12872 mnemonicendp += simd_cmp_op[cmp_type].len;
12876 /* We have a reserved extension byte. Output it directly. */
12877 scratchbuf[0] = '$';
12878 print_operand_value (scratchbuf + 1, 1, cmp_type);
12879 oappend (scratchbuf + intel_syntax);
12880 scratchbuf[0] = '\0';
12885 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
12886 int sizeflag ATTRIBUTE_UNUSED)
12888 /* mwait %eax,%ecx */
12891 const char **names = (address_mode == mode_64bit
12892 ? names64 : names32);
12893 strcpy (op_out[0], names[0]);
12894 strcpy (op_out[1], names[1]);
12895 two_source_ops = 1;
12897 /* Skip mod/rm byte. */
12903 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
12904 int sizeflag ATTRIBUTE_UNUSED)
12906 /* monitor %eax,%ecx,%edx" */
12909 const char **op1_names;
12910 const char **names = (address_mode == mode_64bit
12911 ? names64 : names32);
12913 if (!(prefixes & PREFIX_ADDR))
12914 op1_names = (address_mode == mode_16bit
12915 ? names16 : names);
12918 /* Remove "addr16/addr32". */
12919 addr_prefix = NULL;
12920 op1_names = (address_mode != mode_32bit
12921 ? names32 : names16);
12922 used_prefixes |= PREFIX_ADDR;
12924 strcpy (op_out[0], op1_names[0]);
12925 strcpy (op_out[1], names[1]);
12926 strcpy (op_out[2], names[2]);
12927 two_source_ops = 1;
12929 /* Skip mod/rm byte. */
12937 /* Throw away prefixes and 1st. opcode byte. */
12938 codep = insn_codep + 1;
12943 REP_Fixup (int bytemode, int sizeflag)
12945 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
12947 if (prefixes & PREFIX_REPZ)
12948 repz_prefix = "rep ";
12955 OP_IMREG (bytemode, sizeflag);
12958 OP_ESreg (bytemode, sizeflag);
12961 OP_DSreg (bytemode, sizeflag);
12970 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
12975 /* Change cmpxchg8b to cmpxchg16b. */
12976 char *p = mnemonicendp - 2;
12977 mnemonicendp = stpcpy (p, "16b");
12980 OP_M (bytemode, sizeflag);
12984 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
12988 switch (vex.length)
12991 sprintf (scratchbuf, "%%xmm%d", reg);
12994 sprintf (scratchbuf, "%%ymm%d", reg);
13001 sprintf (scratchbuf, "%%xmm%d", reg);
13002 oappend (scratchbuf + intel_syntax);
13006 CRC32_Fixup (int bytemode, int sizeflag)
13008 /* Add proper suffix to "crc32". */
13009 char *p = mnemonicendp;
13026 else if (sizeflag & DFLAG)
13030 used_prefixes |= (prefixes & PREFIX_DATA);
13033 oappend (INTERNAL_DISASSEMBLER_ERROR);
13040 if (modrm.mod == 3)
13044 /* Skip mod/rm byte. */
13049 add = (rex & REX_B) ? 8 : 0;
13050 if (bytemode == b_mode)
13054 oappend (names8rex[modrm.rm + add]);
13056 oappend (names8[modrm.rm + add]);
13062 oappend (names64[modrm.rm + add]);
13063 else if ((prefixes & PREFIX_DATA))
13064 oappend (names16[modrm.rm + add]);
13066 oappend (names32[modrm.rm + add]);
13070 OP_E (bytemode, sizeflag);
13073 /* Print a DREX argument as either a register or memory operation. */
13075 print_drex_arg (unsigned int reg, int bytemode, int sizeflag)
13077 if (reg == DREX_REG_UNKNOWN)
13080 else if (reg != DREX_REG_MEMORY)
13082 sprintf (scratchbuf, "%%xmm%d", reg);
13083 oappend (scratchbuf + intel_syntax);
13087 OP_E_extended (bytemode, sizeflag, 1);
13090 /* SSE5 instructions that have 4 arguments are encoded as:
13091 0f 24 <sub-opcode> <modrm> <optional-sib> <drex> <offset>.
13093 The <sub-opcode> byte has 1 bit (0x4) that is combined with 1 bit in
13094 the DREX field (0x8) to determine how the arguments are laid out.
13095 The destination register must be the same register as one of the
13096 inputs, and it is encoded in the DREX byte. No REX prefix is used
13097 for these instructions, since the DREX field contains the 3 extension
13098 bits provided by the REX prefix.
13100 The bytemode argument adds 2 extra bits for passing extra information:
13101 DREX_OC1 -- Set the OC1 bit to indicate dest == 1st arg
13102 DREX_NO_OC0 -- OC0 in DREX is invalid
13103 (but pretend it is set). */
13106 OP_DREX4 (int flag_bytemode, int sizeflag)
13108 unsigned int drex_byte;
13109 unsigned int regs[4];
13110 unsigned int modrm_regmem;
13111 unsigned int modrm_reg;
13112 unsigned int drex_reg;
13114 int rex_save = rex;
13115 int rex_used_save = rex_used;
13117 int oc1 = (flag_bytemode & DREX_OC1) ? 2 : 0;
13121 bytemode = flag_bytemode & ~ DREX_MASK;
13123 for (i = 0; i < 4; i++)
13124 regs[i] = DREX_REG_UNKNOWN;
13126 /* Determine if we have a SIB byte in addition to MODRM before the
13128 if (((sizeflag & AFLAG) || address_mode == mode_64bit)
13129 && (modrm.mod != 3)
13130 && (modrm.rm == 4))
13133 /* Get the DREX byte. */
13134 FETCH_DATA (the_info, codep + 2 + has_sib);
13135 drex_byte = codep[has_sib+1];
13136 drex_reg = DREX_XMM (drex_byte);
13137 modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0);
13139 /* Is OC0 legal? If not, hardwire oc0 == 1. */
13140 if (flag_bytemode & DREX_NO_OC0)
13143 if (DREX_OC0 (drex_byte))
13147 oc0 = DREX_OC0 (drex_byte);
13149 if (modrm.mod == 3)
13151 /* regmem == register */
13152 modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0);
13153 rex = rex_used = 0;
13154 /* skip modrm/drex since we don't call OP_E_extended */
13159 /* regmem == memory, fill in appropriate REX bits */
13160 modrm_regmem = DREX_REG_MEMORY;
13161 rex = drex_byte & (REX_B | REX_X | REX_R);
13167 /* Based on the OC1/OC0 bits, lay out the arguments in the correct
13176 regs[0] = modrm_regmem;
13177 regs[1] = modrm_reg;
13178 regs[2] = drex_reg;
13179 regs[3] = drex_reg;
13183 regs[0] = modrm_reg;
13184 regs[1] = modrm_regmem;
13185 regs[2] = drex_reg;
13186 regs[3] = drex_reg;
13190 regs[0] = drex_reg;
13191 regs[1] = modrm_regmem;
13192 regs[2] = modrm_reg;
13193 regs[3] = drex_reg;
13197 regs[0] = drex_reg;
13198 regs[1] = modrm_reg;
13199 regs[2] = modrm_regmem;
13200 regs[3] = drex_reg;
13204 /* Print out the arguments. */
13205 for (i = 0; i < 4; i++)
13207 int j = (intel_syntax) ? 3 - i : i;
13214 print_drex_arg (regs[j], bytemode, sizeflag);
13218 rex_used = rex_used_save;
13221 /* SSE5 instructions that have 3 arguments, and are encoded as:
13222 0f 24 <sub-opcode> <modrm> <optional-sib> <drex> <offset> (or)
13223 0f 25 <sub-opcode> <modrm> <optional-sib> <drex> <offset> <cmp-byte>
13225 The DREX field has 1 bit (0x8) to determine how the arguments are
13226 laid out. The destination register is encoded in the DREX byte.
13227 No REX prefix is used for these instructions, since the DREX field
13228 contains the 3 extension bits provided by the REX prefix. */
13231 OP_DREX3 (int flag_bytemode, int sizeflag)
13233 unsigned int drex_byte;
13234 unsigned int regs[3];
13235 unsigned int modrm_regmem;
13236 unsigned int modrm_reg;
13237 unsigned int drex_reg;
13239 int rex_save = rex;
13240 int rex_used_save = rex_used;
13245 bytemode = flag_bytemode & ~ DREX_MASK;
13247 for (i = 0; i < 3; i++)
13248 regs[i] = DREX_REG_UNKNOWN;
13250 /* Determine if we have a SIB byte in addition to MODRM before the
13252 if (((sizeflag & AFLAG) || address_mode == mode_64bit)
13253 && (modrm.mod != 3)
13254 && (modrm.rm == 4))
13257 /* Get the DREX byte. */
13258 FETCH_DATA (the_info, codep + 2 + has_sib);
13259 drex_byte = codep[has_sib+1];
13260 drex_reg = DREX_XMM (drex_byte);
13261 modrm_reg = modrm.reg + ((drex_byte & REX_R) ? 8 : 0);
13263 /* Is OC0 legal? If not, hardwire oc0 == 0 */
13264 oc0 = DREX_OC0 (drex_byte);
13265 if ((flag_bytemode & DREX_NO_OC0) && oc0)
13268 if (modrm.mod == 3)
13270 /* regmem == register */
13271 modrm_regmem = modrm.rm + ((drex_byte & REX_B) ? 8 : 0);
13272 rex = rex_used = 0;
13273 /* skip modrm/drex since we don't call OP_E_extended. */
13278 /* regmem == memory, fill in appropriate REX bits. */
13279 modrm_regmem = DREX_REG_MEMORY;
13280 rex = drex_byte & (REX_B | REX_X | REX_R);
13286 /* Based on the OC1/OC0 bits, lay out the arguments in the correct
13295 regs[0] = modrm_regmem;
13296 regs[1] = modrm_reg;
13297 regs[2] = drex_reg;
13301 regs[0] = modrm_reg;
13302 regs[1] = modrm_regmem;
13303 regs[2] = drex_reg;
13307 /* Print out the arguments. */
13308 for (i = 0; i < 3; i++)
13310 int j = (intel_syntax) ? 2 - i : i;
13317 print_drex_arg (regs[j], bytemode, sizeflag);
13321 rex_used = rex_used_save;
13324 /* Emit a floating point comparison for comp<xx> instructions. */
13327 OP_DREX_FCMP (int bytemode ATTRIBUTE_UNUSED,
13328 int sizeflag ATTRIBUTE_UNUSED)
13330 unsigned char byte;
13332 static const char *const cmp_test[] = {
13351 FETCH_DATA (the_info, codep + 1);
13352 byte = *codep & 0xff;
13354 if (byte >= ARRAY_SIZE (cmp_test)
13359 /* The instruction isn't one we know about, so just append the
13360 extension byte as a numeric value. */
13366 sprintf (scratchbuf, "com%s%s", cmp_test[byte], obuf+3);
13367 mnemonicendp = stpcpy (obuf, scratchbuf);
13372 /* Emit an integer point comparison for pcom<xx> instructions,
13373 rewriting the instruction to have the test inside of it. */
13376 OP_DREX_ICMP (int bytemode ATTRIBUTE_UNUSED,
13377 int sizeflag ATTRIBUTE_UNUSED)
13379 unsigned char byte;
13381 static const char *const cmp_test[] = {
13392 FETCH_DATA (the_info, codep + 1);
13393 byte = *codep & 0xff;
13395 if (byte >= ARRAY_SIZE (cmp_test)
13401 /* The instruction isn't one we know about, so just print the
13402 comparison test byte as a numeric value. */
13408 sprintf (scratchbuf, "pcom%s%s", cmp_test[byte], obuf+4);
13409 mnemonicendp = stpcpy (obuf, scratchbuf);
13414 /* Display the destination register operand for instructions with
13418 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13426 switch (vex.length)
13439 sprintf (scratchbuf, "%%xmm%d", vex.register_specifier);
13452 sprintf (scratchbuf, "%%ymm%d", vex.register_specifier);
13458 oappend (scratchbuf + intel_syntax);
13461 /* Get the VEX immediate byte without moving codep. */
13463 static unsigned char
13464 get_vex_imm8 (int sizeflag)
13466 int bytes_before_imm = 0;
13468 /* Skip mod/rm byte. */
13472 if (modrm.mod != 3)
13474 /* There are SIB/displacement bytes. */
13475 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13477 /* 32/64 bit address mode */
13478 int base = modrm.rm;
13480 /* Check SIB byte. */
13483 FETCH_DATA (the_info, codep + 1);
13485 bytes_before_imm++;
13491 /* When modrm.rm == 5 or modrm.rm == 4 and base in
13492 SIB == 5, there is a 4 byte displacement. */
13494 /* No displacement. */
13497 /* 4 byte displacement. */
13498 bytes_before_imm += 4;
13501 /* 1 byte displacement. */
13502 bytes_before_imm++;
13507 { /* 16 bit address mode */
13511 /* When modrm.rm == 6, there is a 2 byte displacement. */
13513 /* No displacement. */
13516 /* 2 byte displacement. */
13517 bytes_before_imm += 2;
13520 /* 1 byte displacement. */
13521 bytes_before_imm++;
13527 FETCH_DATA (the_info, codep + bytes_before_imm + 1);
13528 return codep [bytes_before_imm];
13532 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
13534 if (reg == -1 && modrm.mod != 3)
13536 OP_E_memory (bytemode, sizeflag, 0);
13548 else if (reg > 7 && address_mode != mode_64bit)
13552 switch (vex.length)
13555 sprintf (scratchbuf, "%%xmm%d", reg);
13558 sprintf (scratchbuf, "%%ymm%d", reg);
13563 oappend (scratchbuf + intel_syntax);
13567 OP_EX_VexImmW (int bytemode, int sizeflag)
13570 static unsigned char vex_imm8;
13574 vex_imm8 = get_vex_imm8 (sizeflag);
13576 reg = vex_imm8 >> 4;
13582 reg = vex_imm8 >> 4;
13585 OP_EX_VexReg (bytemode, sizeflag, reg);
13589 OP_EX_VexW (int bytemode, int sizeflag)
13597 reg = vex.register_specifier;
13602 reg = vex.register_specifier;
13605 OP_EX_VexReg (bytemode, sizeflag, reg);
13609 OP_VEX_FMA (int bytemode, int sizeflag)
13611 int reg = get_vex_imm8 (sizeflag) >> 4;
13613 if (reg > 7 && address_mode != mode_64bit)
13616 switch (vex.length)
13629 sprintf (scratchbuf, "%%xmm%d", reg);
13641 sprintf (scratchbuf, "%%ymm%d", reg);
13646 oappend (scratchbuf + intel_syntax);
13650 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
13651 int sizeflag ATTRIBUTE_UNUSED)
13653 /* Skip the immediate byte and check for invalid bits. */
13654 FETCH_DATA (the_info, codep + 1);
13655 if (*codep++ & 0xf)
13660 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13663 FETCH_DATA (the_info, codep + 1);
13666 if (bytemode != x_mode)
13673 if (reg > 7 && address_mode != mode_64bit)
13676 switch (vex.length)
13679 sprintf (scratchbuf, "%%xmm%d", reg);
13682 sprintf (scratchbuf, "%%ymm%d", reg);
13687 oappend (scratchbuf + intel_syntax);
13691 OP_XMM_VexW (int bytemode, int sizeflag)
13693 /* Turn off the REX.W bit since it is used for swapping operands
13696 OP_XMM (bytemode, sizeflag);
13700 OP_EX_Vex (int bytemode, int sizeflag)
13702 if (modrm.mod != 3)
13704 if (vex.register_specifier != 0)
13708 OP_EX (bytemode, sizeflag);
13712 OP_XMM_Vex (int bytemode, int sizeflag)
13714 if (modrm.mod != 3)
13716 if (vex.register_specifier != 0)
13720 OP_XMM (bytemode, sizeflag);
13724 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13726 switch (vex.length)
13729 mnemonicendp = stpcpy (obuf, "vzeroupper");
13732 mnemonicendp = stpcpy (obuf, "vzeroall");
13739 static struct op vex_cmp_op[] =
13741 { STRING_COMMA_LEN ("eq") },
13742 { STRING_COMMA_LEN ("lt") },
13743 { STRING_COMMA_LEN ("le") },
13744 { STRING_COMMA_LEN ("unord") },
13745 { STRING_COMMA_LEN ("neq") },
13746 { STRING_COMMA_LEN ("nlt") },
13747 { STRING_COMMA_LEN ("nle") },
13748 { STRING_COMMA_LEN ("ord") },
13749 { STRING_COMMA_LEN ("eq_uq") },
13750 { STRING_COMMA_LEN ("nge") },
13751 { STRING_COMMA_LEN ("ngt") },
13752 { STRING_COMMA_LEN ("false") },
13753 { STRING_COMMA_LEN ("neq_oq") },
13754 { STRING_COMMA_LEN ("ge") },
13755 { STRING_COMMA_LEN ("gt") },
13756 { STRING_COMMA_LEN ("true") },
13757 { STRING_COMMA_LEN ("eq_os") },
13758 { STRING_COMMA_LEN ("lt_oq") },
13759 { STRING_COMMA_LEN ("le_oq") },
13760 { STRING_COMMA_LEN ("unord_s") },
13761 { STRING_COMMA_LEN ("neq_us") },
13762 { STRING_COMMA_LEN ("nlt_uq") },
13763 { STRING_COMMA_LEN ("nle_uq") },
13764 { STRING_COMMA_LEN ("ord_s") },
13765 { STRING_COMMA_LEN ("eq_us") },
13766 { STRING_COMMA_LEN ("nge_uq") },
13767 { STRING_COMMA_LEN ("ngt_uq") },
13768 { STRING_COMMA_LEN ("false_os") },
13769 { STRING_COMMA_LEN ("neq_os") },
13770 { STRING_COMMA_LEN ("ge_oq") },
13771 { STRING_COMMA_LEN ("gt_oq") },
13772 { STRING_COMMA_LEN ("true_us") },
13776 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13778 unsigned int cmp_type;
13780 FETCH_DATA (the_info, codep + 1);
13781 cmp_type = *codep++ & 0xff;
13782 if (cmp_type < ARRAY_SIZE (vex_cmp_op))
13785 char *p = mnemonicendp - 2;
13789 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13790 mnemonicendp += vex_cmp_op[cmp_type].len;
13794 /* We have a reserved extension byte. Output it directly. */
13795 scratchbuf[0] = '$';
13796 print_operand_value (scratchbuf + 1, 1, cmp_type);
13797 oappend (scratchbuf + intel_syntax);
13798 scratchbuf[0] = '\0';
13802 static const struct op pclmul_op[] =
13804 { STRING_COMMA_LEN ("lql") },
13805 { STRING_COMMA_LEN ("hql") },
13806 { STRING_COMMA_LEN ("lqh") },
13807 { STRING_COMMA_LEN ("hqh") }
13811 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
13812 int sizeflag ATTRIBUTE_UNUSED)
13814 unsigned int pclmul_type;
13816 FETCH_DATA (the_info, codep + 1);
13817 pclmul_type = *codep++ & 0xff;
13818 switch (pclmul_type)
13829 if (pclmul_type < ARRAY_SIZE (pclmul_op))
13832 char *p = mnemonicendp - 3;
13837 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
13838 mnemonicendp += pclmul_op[pclmul_type].len;
13842 /* We have a reserved extension byte. Output it directly. */
13843 scratchbuf[0] = '$';
13844 print_operand_value (scratchbuf + 1, 1, pclmul_type);
13845 oappend (scratchbuf + intel_syntax);
13846 scratchbuf[0] = '\0';
13850 static const struct op vpermil2_op[] =
13852 { STRING_COMMA_LEN ("td") },
13853 { STRING_COMMA_LEN ("td") },
13854 { STRING_COMMA_LEN ("mo") },
13855 { STRING_COMMA_LEN ("mz") }
13859 VPERMIL2_Fixup (int bytemode ATTRIBUTE_UNUSED,
13860 int sizeflag ATTRIBUTE_UNUSED)
13862 unsigned int vpermil2_type;
13864 FETCH_DATA (the_info, codep + 1);
13865 vpermil2_type = *codep++ & 0xf;
13866 if (vpermil2_type < ARRAY_SIZE (vpermil2_op))
13869 char *p = mnemonicendp - 3;
13874 sprintf (p, "%s%s", vpermil2_op[vpermil2_type].name, suffix);
13875 mnemonicendp += vpermil2_op[vpermil2_type].len;
13879 /* We have a reserved extension byte. Output it directly. */
13880 scratchbuf[0] = '$';
13881 print_operand_value (scratchbuf + 1, 1, vpermil2_type);
13882 oappend (scratchbuf + intel_syntax);
13883 scratchbuf[0] = '\0';
13888 MOVBE_Fixup (int bytemode, int sizeflag)
13890 /* Add proper suffix to "movbe". */
13891 char *p = mnemonicendp;
13900 if (sizeflag & SUFFIX_ALWAYS)
13904 else if (sizeflag & DFLAG)
13909 used_prefixes |= (prefixes & PREFIX_DATA);
13912 oappend (INTERNAL_DISASSEMBLER_ERROR);
13919 OP_M (bytemode, sizeflag);