1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2019 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma, disassemble_info *);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma get64 (void);
58 static bfd_signed_vma get32 (void);
59 static bfd_signed_vma get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VCMP_Fixup (int, int);
99 static void VPCMP_Fixup (int, int);
100 static void VPCOM_Fixup (int, int);
101 static void OP_0f07 (int, int);
102 static void OP_Monitor (int, int);
103 static void OP_Mwait (int, int);
104 static void OP_Mwaitx (int, int);
105 static void NOP_Fixup1 (int, int);
106 static void NOP_Fixup2 (int, int);
107 static void OP_3DNowSuffix (int, int);
108 static void CMP_Fixup (int, int);
109 static void BadOp (void);
110 static void REP_Fixup (int, int);
111 static void BND_Fixup (int, int);
112 static void NOTRACK_Fixup (int, int);
113 static void HLE_Fixup1 (int, int);
114 static void HLE_Fixup2 (int, int);
115 static void HLE_Fixup3 (int, int);
116 static void CMPXCHG8B_Fixup (int, int);
117 static void XMM_Fixup (int, int);
118 static void CRC32_Fixup (int, int);
119 static void FXSAVE_Fixup (int, int);
120 static void PCMPESTR_Fixup (int, int);
121 static void OP_LWPCB_E (int, int);
122 static void OP_LWP_E (int, int);
123 static void OP_Vex_2src_1 (int, int);
124 static void OP_Vex_2src_2 (int, int);
126 static void MOVBE_Fixup (int, int);
128 static void OP_Mask (int, int);
131 /* Points to first byte not fetched. */
132 bfd_byte *max_fetched;
133 bfd_byte the_buffer[MAX_MNEM_SIZE];
136 OPCODES_SIGJMP_BUF bailout;
146 enum address_mode address_mode;
148 /* Flags for the prefixes for the current instruction. See below. */
151 /* REX prefix the current instruction. See below. */
153 /* Bits of REX we've already used. */
155 /* REX bits in original REX prefix ignored. */
156 static int rex_ignored;
157 /* Mark parts used in the REX prefix. When we are testing for
158 empty prefix (for 8bit register REX extension), just mask it
159 out. Otherwise test for REX bit is excuse for existence of REX
160 only in case value is nonzero. */
161 #define USED_REX(value) \
166 rex_used |= (value) | REX_OPCODE; \
169 rex_used |= REX_OPCODE; \
172 /* Flags for prefixes which we somehow handled when printing the
173 current instruction. */
174 static int used_prefixes;
176 /* Flags stored in PREFIXES. */
177 #define PREFIX_REPZ 1
178 #define PREFIX_REPNZ 2
179 #define PREFIX_LOCK 4
181 #define PREFIX_SS 0x10
182 #define PREFIX_DS 0x20
183 #define PREFIX_ES 0x40
184 #define PREFIX_FS 0x80
185 #define PREFIX_GS 0x100
186 #define PREFIX_DATA 0x200
187 #define PREFIX_ADDR 0x400
188 #define PREFIX_FWAIT 0x800
190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
191 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
193 #define FETCH_DATA(info, addr) \
194 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
195 ? 1 : fetch_data ((info), (addr)))
198 fetch_data (struct disassemble_info *info, bfd_byte *addr)
201 struct dis_private *priv = (struct dis_private *) info->private_data;
202 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
204 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
205 status = (*info->read_memory_func) (start,
207 addr - priv->max_fetched,
213 /* If we did manage to read at least one byte, then
214 print_insn_i386 will do something sensible. Otherwise, print
215 an error. We do that here because this is where we know
217 if (priv->max_fetched == priv->the_buffer)
218 (*info->memory_error_func) (status, start, info);
219 OPCODES_SIGLONGJMP (priv->bailout, 1);
222 priv->max_fetched = addr;
226 /* Possible values for prefix requirement. */
227 #define PREFIX_IGNORED_SHIFT 16
228 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
229 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
232 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
234 /* Opcode prefixes. */
235 #define PREFIX_OPCODE (PREFIX_REPZ \
239 /* Prefixes ignored. */
240 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
241 | PREFIX_IGNORED_REPNZ \
242 | PREFIX_IGNORED_DATA)
244 #define XX { NULL, 0 }
245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
247 #define Eb { OP_E, b_mode }
248 #define Ebnd { OP_E, bnd_mode }
249 #define EbS { OP_E, b_swap_mode }
250 #define EbndS { OP_E, bnd_swap_mode }
251 #define Ev { OP_E, v_mode }
252 #define Eva { OP_E, va_mode }
253 #define Ev_bnd { OP_E, v_bnd_mode }
254 #define EvS { OP_E, v_swap_mode }
255 #define Ed { OP_E, d_mode }
256 #define Edq { OP_E, dq_mode }
257 #define Edqw { OP_E, dqw_mode }
258 #define Edqb { OP_E, dqb_mode }
259 #define Edb { OP_E, db_mode }
260 #define Edw { OP_E, dw_mode }
261 #define Edqd { OP_E, dqd_mode }
262 #define Edqa { OP_E, dqa_mode }
263 #define Eq { OP_E, q_mode }
264 #define indirEv { OP_indirE, indir_v_mode }
265 #define indirEp { OP_indirE, f_mode }
266 #define stackEv { OP_E, stack_v_mode }
267 #define Em { OP_E, m_mode }
268 #define Ew { OP_E, w_mode }
269 #define M { OP_M, 0 } /* lea, lgdt, etc. */
270 #define Ma { OP_M, a_mode }
271 #define Mb { OP_M, b_mode }
272 #define Md { OP_M, d_mode }
273 #define Mo { OP_M, o_mode }
274 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
275 #define Mq { OP_M, q_mode }
276 #define Mv_bnd { OP_M, v_bndmk_mode }
277 #define Mx { OP_M, x_mode }
278 #define Mxmm { OP_M, xmm_mode }
279 #define Gb { OP_G, b_mode }
280 #define Gbnd { OP_G, bnd_mode }
281 #define Gv { OP_G, v_mode }
282 #define Gd { OP_G, d_mode }
283 #define Gdq { OP_G, dq_mode }
284 #define Gm { OP_G, m_mode }
285 #define Gva { OP_G, va_mode }
286 #define Gw { OP_G, w_mode }
287 #define Rd { OP_R, d_mode }
288 #define Rdq { OP_R, dq_mode }
289 #define Rm { OP_R, m_mode }
290 #define Ib { OP_I, b_mode }
291 #define sIb { OP_sI, b_mode } /* sign extened byte */
292 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
293 #define Iv { OP_I, v_mode }
294 #define sIv { OP_sI, v_mode }
295 #define Iq { OP_I, q_mode }
296 #define Iv64 { OP_I64, v_mode }
297 #define Iw { OP_I, w_mode }
298 #define I1 { OP_I, const_1_mode }
299 #define Jb { OP_J, b_mode }
300 #define Jv { OP_J, v_mode }
301 #define Cm { OP_C, m_mode }
302 #define Dm { OP_D, m_mode }
303 #define Td { OP_T, d_mode }
304 #define Skip_MODRM { OP_Skip_MODRM, 0 }
306 #define RMeAX { OP_REG, eAX_reg }
307 #define RMeBX { OP_REG, eBX_reg }
308 #define RMeCX { OP_REG, eCX_reg }
309 #define RMeDX { OP_REG, eDX_reg }
310 #define RMeSP { OP_REG, eSP_reg }
311 #define RMeBP { OP_REG, eBP_reg }
312 #define RMeSI { OP_REG, eSI_reg }
313 #define RMeDI { OP_REG, eDI_reg }
314 #define RMrAX { OP_REG, rAX_reg }
315 #define RMrBX { OP_REG, rBX_reg }
316 #define RMrCX { OP_REG, rCX_reg }
317 #define RMrDX { OP_REG, rDX_reg }
318 #define RMrSP { OP_REG, rSP_reg }
319 #define RMrBP { OP_REG, rBP_reg }
320 #define RMrSI { OP_REG, rSI_reg }
321 #define RMrDI { OP_REG, rDI_reg }
322 #define RMAL { OP_REG, al_reg }
323 #define RMCL { OP_REG, cl_reg }
324 #define RMDL { OP_REG, dl_reg }
325 #define RMBL { OP_REG, bl_reg }
326 #define RMAH { OP_REG, ah_reg }
327 #define RMCH { OP_REG, ch_reg }
328 #define RMDH { OP_REG, dh_reg }
329 #define RMBH { OP_REG, bh_reg }
330 #define RMAX { OP_REG, ax_reg }
331 #define RMDX { OP_REG, dx_reg }
333 #define eAX { OP_IMREG, eAX_reg }
334 #define eBX { OP_IMREG, eBX_reg }
335 #define eCX { OP_IMREG, eCX_reg }
336 #define eDX { OP_IMREG, eDX_reg }
337 #define eSP { OP_IMREG, eSP_reg }
338 #define eBP { OP_IMREG, eBP_reg }
339 #define eSI { OP_IMREG, eSI_reg }
340 #define eDI { OP_IMREG, eDI_reg }
341 #define AL { OP_IMREG, al_reg }
342 #define CL { OP_IMREG, cl_reg }
343 #define DL { OP_IMREG, dl_reg }
344 #define BL { OP_IMREG, bl_reg }
345 #define AH { OP_IMREG, ah_reg }
346 #define CH { OP_IMREG, ch_reg }
347 #define DH { OP_IMREG, dh_reg }
348 #define BH { OP_IMREG, bh_reg }
349 #define AX { OP_IMREG, ax_reg }
350 #define DX { OP_IMREG, dx_reg }
351 #define zAX { OP_IMREG, z_mode_ax_reg }
352 #define indirDX { OP_IMREG, indir_dx_reg }
354 #define Sw { OP_SEG, w_mode }
355 #define Sv { OP_SEG, v_mode }
356 #define Ap { OP_DIR, 0 }
357 #define Ob { OP_OFF64, b_mode }
358 #define Ov { OP_OFF64, v_mode }
359 #define Xb { OP_DSreg, eSI_reg }
360 #define Xv { OP_DSreg, eSI_reg }
361 #define Xz { OP_DSreg, eSI_reg }
362 #define Yb { OP_ESreg, eDI_reg }
363 #define Yv { OP_ESreg, eDI_reg }
364 #define DSBX { OP_DSreg, eBX_reg }
366 #define es { OP_REG, es_reg }
367 #define ss { OP_REG, ss_reg }
368 #define cs { OP_REG, cs_reg }
369 #define ds { OP_REG, ds_reg }
370 #define fs { OP_REG, fs_reg }
371 #define gs { OP_REG, gs_reg }
373 #define MX { OP_MMX, 0 }
374 #define XM { OP_XMM, 0 }
375 #define XMScalar { OP_XMM, scalar_mode }
376 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
377 #define XMM { OP_XMM, xmm_mode }
378 #define XMxmmq { OP_XMM, xmmq_mode }
379 #define EM { OP_EM, v_mode }
380 #define EMS { OP_EM, v_swap_mode }
381 #define EMd { OP_EM, d_mode }
382 #define EMx { OP_EM, x_mode }
383 #define EXbScalar { OP_EX, b_scalar_mode }
384 #define EXw { OP_EX, w_mode }
385 #define EXwScalar { OP_EX, w_scalar_mode }
386 #define EXd { OP_EX, d_mode }
387 #define EXdScalar { OP_EX, d_scalar_mode }
388 #define EXdS { OP_EX, d_swap_mode }
389 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
390 #define EXq { OP_EX, q_mode }
391 #define EXqScalar { OP_EX, q_scalar_mode }
392 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
393 #define EXqS { OP_EX, q_swap_mode }
394 #define EXx { OP_EX, x_mode }
395 #define EXxS { OP_EX, x_swap_mode }
396 #define EXxmm { OP_EX, xmm_mode }
397 #define EXymm { OP_EX, ymm_mode }
398 #define EXxmmq { OP_EX, xmmq_mode }
399 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
400 #define EXxmm_mb { OP_EX, xmm_mb_mode }
401 #define EXxmm_mw { OP_EX, xmm_mw_mode }
402 #define EXxmm_md { OP_EX, xmm_md_mode }
403 #define EXxmm_mq { OP_EX, xmm_mq_mode }
404 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
405 #define EXxmmdw { OP_EX, xmmdw_mode }
406 #define EXxmmqd { OP_EX, xmmqd_mode }
407 #define EXymmq { OP_EX, ymmq_mode }
408 #define EXVexWdq { OP_EX, vex_w_dq_mode }
409 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
410 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
411 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
412 #define MS { OP_MS, v_mode }
413 #define XS { OP_XS, v_mode }
414 #define EMCq { OP_EMC, q_mode }
415 #define MXC { OP_MXC, 0 }
416 #define OPSUF { OP_3DNowSuffix, 0 }
417 #define CMP { CMP_Fixup, 0 }
418 #define XMM0 { XMM_Fixup, 0 }
419 #define FXSAVE { FXSAVE_Fixup, 0 }
420 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
421 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
423 #define Vex { OP_VEX, vex_mode }
424 #define VexScalar { OP_VEX, vex_scalar_mode }
425 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
426 #define Vex128 { OP_VEX, vex128_mode }
427 #define Vex256 { OP_VEX, vex256_mode }
428 #define VexGdq { OP_VEX, dq_mode }
429 #define EXdVex { OP_EX_Vex, d_mode }
430 #define EXdVexS { OP_EX_Vex, d_swap_mode }
431 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
432 #define EXqVex { OP_EX_Vex, q_mode }
433 #define EXqVexS { OP_EX_Vex, q_swap_mode }
434 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
435 #define EXVexW { OP_EX_VexW, x_mode }
436 #define EXdVexW { OP_EX_VexW, d_mode }
437 #define EXqVexW { OP_EX_VexW, q_mode }
438 #define EXVexImmW { OP_EX_VexImmW, x_mode }
439 #define XMVex { OP_XMM_Vex, 0 }
440 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
441 #define XMVexW { OP_XMM_VexW, 0 }
442 #define XMVexI4 { OP_REG_VexI4, x_mode }
443 #define PCLMUL { PCLMUL_Fixup, 0 }
444 #define VCMP { VCMP_Fixup, 0 }
445 #define VPCMP { VPCMP_Fixup, 0 }
446 #define VPCOM { VPCOM_Fixup, 0 }
448 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
449 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
450 #define EXxEVexS { OP_Rounding, evex_sae_mode }
452 #define XMask { OP_Mask, mask_mode }
453 #define MaskG { OP_G, mask_mode }
454 #define MaskE { OP_E, mask_mode }
455 #define MaskBDE { OP_E, mask_bd_mode }
456 #define MaskR { OP_R, mask_mode }
457 #define MaskVex { OP_VEX, mask_mode }
459 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
460 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
461 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
462 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
464 /* Used handle "rep" prefix for string instructions. */
465 #define Xbr { REP_Fixup, eSI_reg }
466 #define Xvr { REP_Fixup, eSI_reg }
467 #define Ybr { REP_Fixup, eDI_reg }
468 #define Yvr { REP_Fixup, eDI_reg }
469 #define Yzr { REP_Fixup, eDI_reg }
470 #define indirDXr { REP_Fixup, indir_dx_reg }
471 #define ALr { REP_Fixup, al_reg }
472 #define eAXr { REP_Fixup, eAX_reg }
474 /* Used handle HLE prefix for lockable instructions. */
475 #define Ebh1 { HLE_Fixup1, b_mode }
476 #define Evh1 { HLE_Fixup1, v_mode }
477 #define Ebh2 { HLE_Fixup2, b_mode }
478 #define Evh2 { HLE_Fixup2, v_mode }
479 #define Ebh3 { HLE_Fixup3, b_mode }
480 #define Evh3 { HLE_Fixup3, v_mode }
482 #define BND { BND_Fixup, 0 }
483 #define NOTRACK { NOTRACK_Fixup, 0 }
485 #define cond_jump_flag { NULL, cond_jump_mode }
486 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
488 /* bits in sizeflag */
489 #define SUFFIX_ALWAYS 4
497 /* byte operand with operand swapped */
499 /* byte operand, sign extend like 'T' suffix */
501 /* operand size depends on prefixes */
503 /* operand size depends on prefixes with operand swapped */
505 /* operand size depends on address prefix */
509 /* double word operand */
511 /* double word operand with operand swapped */
513 /* quad word operand */
515 /* quad word operand with operand swapped */
517 /* ten-byte operand */
519 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
520 broadcast enabled. */
522 /* Similar to x_mode, but with different EVEX mem shifts. */
524 /* Similar to x_mode, but with disabled broadcast. */
526 /* Similar to x_mode, but with operands swapped and disabled broadcast
529 /* 16-byte XMM operand */
531 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
532 memory operand (depending on vector length). Broadcast isn't
535 /* Same as xmmq_mode, but broadcast is allowed. */
536 evex_half_bcst_xmmq_mode,
537 /* XMM register or byte memory operand */
539 /* XMM register or word memory operand */
541 /* XMM register or double word memory operand */
543 /* XMM register or quad word memory operand */
545 /* XMM register or double/quad word memory operand, depending on
548 /* 16-byte XMM, word, double word or quad word operand. */
550 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
552 /* 32-byte YMM operand */
554 /* quad word, ymmword or zmmword memory operand. */
556 /* 32-byte YMM or 16-byte word operand */
558 /* d_mode in 32bit, q_mode in 64bit mode. */
560 /* pair of v_mode operands */
565 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
567 /* operand size depends on REX prefixes. */
569 /* registers like dq_mode, memory like w_mode. */
573 /* bounds operand with operand swapped */
575 /* 4- or 6-byte pointer operand */
578 /* v_mode for indirect branch opcodes. */
580 /* v_mode for stack-related opcodes. */
582 /* non-quad operand size depends on prefixes */
584 /* 16-byte operand */
586 /* registers like dq_mode, memory like b_mode. */
588 /* registers like d_mode, memory like b_mode. */
590 /* registers like d_mode, memory like w_mode. */
592 /* registers like dq_mode, memory like d_mode. */
594 /* operand size depends on the W bit as well as address mode. */
596 /* normal vex mode */
598 /* 128bit vex mode */
600 /* 256bit vex mode */
602 /* operand size depends on the VEX.W bit. */
605 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
606 vex_vsib_d_w_dq_mode,
607 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
609 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
610 vex_vsib_q_w_dq_mode,
611 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
614 /* scalar, ignore vector length. */
616 /* like b_mode, ignore vector length. */
618 /* like w_mode, ignore vector length. */
620 /* like d_mode, ignore vector length. */
622 /* like d_swap_mode, ignore vector length. */
624 /* like q_mode, ignore vector length. */
626 /* like q_swap_mode, ignore vector length. */
628 /* like vex_mode, ignore vector length. */
630 /* like vex_w_dq_mode, ignore vector length. */
631 vex_scalar_w_dq_mode,
633 /* Static rounding. */
635 /* Static rounding, 64-bit mode only. */
636 evex_rounding_64_mode,
637 /* Supress all exceptions. */
640 /* Mask register operand. */
642 /* Mask register operand. */
710 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
712 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
713 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
714 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
715 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
716 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
717 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
718 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
719 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
720 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
721 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
722 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
723 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
724 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
725 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
726 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
727 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
855 MOD_VEX_0F12_PREFIX_0,
857 MOD_VEX_0F16_PREFIX_0,
860 MOD_VEX_W_0_0F41_P_0_LEN_1,
861 MOD_VEX_W_1_0F41_P_0_LEN_1,
862 MOD_VEX_W_0_0F41_P_2_LEN_1,
863 MOD_VEX_W_1_0F41_P_2_LEN_1,
864 MOD_VEX_W_0_0F42_P_0_LEN_1,
865 MOD_VEX_W_1_0F42_P_0_LEN_1,
866 MOD_VEX_W_0_0F42_P_2_LEN_1,
867 MOD_VEX_W_1_0F42_P_2_LEN_1,
868 MOD_VEX_W_0_0F44_P_0_LEN_1,
869 MOD_VEX_W_1_0F44_P_0_LEN_1,
870 MOD_VEX_W_0_0F44_P_2_LEN_1,
871 MOD_VEX_W_1_0F44_P_2_LEN_1,
872 MOD_VEX_W_0_0F45_P_0_LEN_1,
873 MOD_VEX_W_1_0F45_P_0_LEN_1,
874 MOD_VEX_W_0_0F45_P_2_LEN_1,
875 MOD_VEX_W_1_0F45_P_2_LEN_1,
876 MOD_VEX_W_0_0F46_P_0_LEN_1,
877 MOD_VEX_W_1_0F46_P_0_LEN_1,
878 MOD_VEX_W_0_0F46_P_2_LEN_1,
879 MOD_VEX_W_1_0F46_P_2_LEN_1,
880 MOD_VEX_W_0_0F47_P_0_LEN_1,
881 MOD_VEX_W_1_0F47_P_0_LEN_1,
882 MOD_VEX_W_0_0F47_P_2_LEN_1,
883 MOD_VEX_W_1_0F47_P_2_LEN_1,
884 MOD_VEX_W_0_0F4A_P_0_LEN_1,
885 MOD_VEX_W_1_0F4A_P_0_LEN_1,
886 MOD_VEX_W_0_0F4A_P_2_LEN_1,
887 MOD_VEX_W_1_0F4A_P_2_LEN_1,
888 MOD_VEX_W_0_0F4B_P_0_LEN_1,
889 MOD_VEX_W_1_0F4B_P_0_LEN_1,
890 MOD_VEX_W_0_0F4B_P_2_LEN_1,
902 MOD_VEX_W_0_0F91_P_0_LEN_0,
903 MOD_VEX_W_1_0F91_P_0_LEN_0,
904 MOD_VEX_W_0_0F91_P_2_LEN_0,
905 MOD_VEX_W_1_0F91_P_2_LEN_0,
906 MOD_VEX_W_0_0F92_P_0_LEN_0,
907 MOD_VEX_W_0_0F92_P_2_LEN_0,
908 MOD_VEX_0F92_P_3_LEN_0,
909 MOD_VEX_W_0_0F93_P_0_LEN_0,
910 MOD_VEX_W_0_0F93_P_2_LEN_0,
911 MOD_VEX_0F93_P_3_LEN_0,
912 MOD_VEX_W_0_0F98_P_0_LEN_0,
913 MOD_VEX_W_1_0F98_P_0_LEN_0,
914 MOD_VEX_W_0_0F98_P_2_LEN_0,
915 MOD_VEX_W_1_0F98_P_2_LEN_0,
916 MOD_VEX_W_0_0F99_P_0_LEN_0,
917 MOD_VEX_W_1_0F99_P_0_LEN_0,
918 MOD_VEX_W_0_0F99_P_2_LEN_0,
919 MOD_VEX_W_1_0F99_P_2_LEN_0,
922 MOD_VEX_0FD7_PREFIX_2,
923 MOD_VEX_0FE7_PREFIX_2,
924 MOD_VEX_0FF0_PREFIX_3,
925 MOD_VEX_0F381A_PREFIX_2,
926 MOD_VEX_0F382A_PREFIX_2,
927 MOD_VEX_0F382C_PREFIX_2,
928 MOD_VEX_0F382D_PREFIX_2,
929 MOD_VEX_0F382E_PREFIX_2,
930 MOD_VEX_0F382F_PREFIX_2,
931 MOD_VEX_0F385A_PREFIX_2,
932 MOD_VEX_0F388C_PREFIX_2,
933 MOD_VEX_0F388E_PREFIX_2,
934 MOD_VEX_W_0_0F3A30_P_2_LEN_0,
935 MOD_VEX_W_1_0F3A30_P_2_LEN_0,
936 MOD_VEX_W_0_0F3A31_P_2_LEN_0,
937 MOD_VEX_W_1_0F3A31_P_2_LEN_0,
938 MOD_VEX_W_0_0F3A32_P_2_LEN_0,
939 MOD_VEX_W_1_0F3A32_P_2_LEN_0,
940 MOD_VEX_W_0_0F3A33_P_2_LEN_0,
941 MOD_VEX_W_1_0F3A33_P_2_LEN_0,
943 MOD_EVEX_0F10_PREFIX_1,
944 MOD_EVEX_0F10_PREFIX_3,
945 MOD_EVEX_0F11_PREFIX_1,
946 MOD_EVEX_0F11_PREFIX_3,
947 MOD_EVEX_0F12_PREFIX_0,
948 MOD_EVEX_0F16_PREFIX_0,
949 MOD_EVEX_0F38C6_REG_1,
950 MOD_EVEX_0F38C6_REG_2,
951 MOD_EVEX_0F38C6_REG_5,
952 MOD_EVEX_0F38C6_REG_6,
953 MOD_EVEX_0F38C7_REG_1,
954 MOD_EVEX_0F38C7_REG_2,
955 MOD_EVEX_0F38C7_REG_5,
956 MOD_EVEX_0F38C7_REG_6
977 PREFIX_MOD_0_0F01_REG_5,
978 PREFIX_MOD_3_0F01_REG_5_RM_0,
979 PREFIX_MOD_3_0F01_REG_5_RM_2,
1025 PREFIX_MOD_0_0FAE_REG_4,
1026 PREFIX_MOD_3_0FAE_REG_4,
1027 PREFIX_MOD_0_0FAE_REG_5,
1028 PREFIX_MOD_3_0FAE_REG_5,
1029 PREFIX_MOD_0_0FAE_REG_6,
1030 PREFIX_MOD_1_0FAE_REG_6,
1037 PREFIX_MOD_0_0FC7_REG_6,
1038 PREFIX_MOD_3_0FC7_REG_6,
1039 PREFIX_MOD_3_0FC7_REG_7,
1169 PREFIX_VEX_0F71_REG_2,
1170 PREFIX_VEX_0F71_REG_4,
1171 PREFIX_VEX_0F71_REG_6,
1172 PREFIX_VEX_0F72_REG_2,
1173 PREFIX_VEX_0F72_REG_4,
1174 PREFIX_VEX_0F72_REG_6,
1175 PREFIX_VEX_0F73_REG_2,
1176 PREFIX_VEX_0F73_REG_3,
1177 PREFIX_VEX_0F73_REG_6,
1178 PREFIX_VEX_0F73_REG_7,
1351 PREFIX_VEX_0F38F3_REG_1,
1352 PREFIX_VEX_0F38F3_REG_2,
1353 PREFIX_VEX_0F38F3_REG_3,
1472 PREFIX_EVEX_0F71_REG_2,
1473 PREFIX_EVEX_0F71_REG_4,
1474 PREFIX_EVEX_0F71_REG_6,
1475 PREFIX_EVEX_0F72_REG_0,
1476 PREFIX_EVEX_0F72_REG_1,
1477 PREFIX_EVEX_0F72_REG_2,
1478 PREFIX_EVEX_0F72_REG_4,
1479 PREFIX_EVEX_0F72_REG_6,
1480 PREFIX_EVEX_0F73_REG_2,
1481 PREFIX_EVEX_0F73_REG_3,
1482 PREFIX_EVEX_0F73_REG_6,
1483 PREFIX_EVEX_0F73_REG_7,
1680 PREFIX_EVEX_0F38C6_REG_1,
1681 PREFIX_EVEX_0F38C6_REG_2,
1682 PREFIX_EVEX_0F38C6_REG_5,
1683 PREFIX_EVEX_0F38C6_REG_6,
1684 PREFIX_EVEX_0F38C7_REG_1,
1685 PREFIX_EVEX_0F38C7_REG_2,
1686 PREFIX_EVEX_0F38C7_REG_5,
1687 PREFIX_EVEX_0F38C7_REG_6,
1789 THREE_BYTE_0F38 = 0,
1816 VEX_LEN_0F12_P_0_M_0 = 0,
1817 VEX_LEN_0F12_P_0_M_1,
1820 VEX_LEN_0F16_P_0_M_0,
1821 VEX_LEN_0F16_P_0_M_1,
1864 VEX_LEN_0FAE_R_2_M_0,
1865 VEX_LEN_0FAE_R_3_M_0,
1872 VEX_LEN_0F381A_P_2_M_0,
1875 VEX_LEN_0F385A_P_2_M_0,
1878 VEX_LEN_0F38F3_R_1_P_0,
1879 VEX_LEN_0F38F3_R_2_P_0,
1880 VEX_LEN_0F38F3_R_3_P_0,
1923 VEX_LEN_0FXOP_08_CC,
1924 VEX_LEN_0FXOP_08_CD,
1925 VEX_LEN_0FXOP_08_CE,
1926 VEX_LEN_0FXOP_08_CF,
1927 VEX_LEN_0FXOP_08_EC,
1928 VEX_LEN_0FXOP_08_ED,
1929 VEX_LEN_0FXOP_08_EE,
1930 VEX_LEN_0FXOP_08_EF,
1931 VEX_LEN_0FXOP_09_80,
1937 EVEX_LEN_0F6E_P_2 = 0,
1941 EVEX_LEN_0F3819_P_2_W_0,
1942 EVEX_LEN_0F3819_P_2_W_1,
1943 EVEX_LEN_0F381A_P_2_W_0,
1944 EVEX_LEN_0F381A_P_2_W_1,
1945 EVEX_LEN_0F381B_P_2_W_0,
1946 EVEX_LEN_0F381B_P_2_W_1,
1947 EVEX_LEN_0F385A_P_2_W_0,
1948 EVEX_LEN_0F385A_P_2_W_1,
1949 EVEX_LEN_0F385B_P_2_W_0,
1950 EVEX_LEN_0F385B_P_2_W_1,
1951 EVEX_LEN_0F3A18_P_2_W_0,
1952 EVEX_LEN_0F3A18_P_2_W_1,
1953 EVEX_LEN_0F3A19_P_2_W_0,
1954 EVEX_LEN_0F3A19_P_2_W_1,
1955 EVEX_LEN_0F3A1A_P_2_W_0,
1956 EVEX_LEN_0F3A1A_P_2_W_1,
1957 EVEX_LEN_0F3A1B_P_2_W_0,
1958 EVEX_LEN_0F3A1B_P_2_W_1,
1959 EVEX_LEN_0F3A23_P_2_W_0,
1960 EVEX_LEN_0F3A23_P_2_W_1,
1961 EVEX_LEN_0F3A38_P_2_W_0,
1962 EVEX_LEN_0F3A38_P_2_W_1,
1963 EVEX_LEN_0F3A39_P_2_W_0,
1964 EVEX_LEN_0F3A39_P_2_W_1,
1965 EVEX_LEN_0F3A3A_P_2_W_0,
1966 EVEX_LEN_0F3A3A_P_2_W_1,
1967 EVEX_LEN_0F3A3B_P_2_W_0,
1968 EVEX_LEN_0F3A3B_P_2_W_1,
1969 EVEX_LEN_0F3A43_P_2_W_0,
1970 EVEX_LEN_0F3A43_P_2_W_1
1975 VEX_W_0F41_P_0_LEN_1 = 0,
1976 VEX_W_0F41_P_2_LEN_1,
1977 VEX_W_0F42_P_0_LEN_1,
1978 VEX_W_0F42_P_2_LEN_1,
1979 VEX_W_0F44_P_0_LEN_0,
1980 VEX_W_0F44_P_2_LEN_0,
1981 VEX_W_0F45_P_0_LEN_1,
1982 VEX_W_0F45_P_2_LEN_1,
1983 VEX_W_0F46_P_0_LEN_1,
1984 VEX_W_0F46_P_2_LEN_1,
1985 VEX_W_0F47_P_0_LEN_1,
1986 VEX_W_0F47_P_2_LEN_1,
1987 VEX_W_0F4A_P_0_LEN_1,
1988 VEX_W_0F4A_P_2_LEN_1,
1989 VEX_W_0F4B_P_0_LEN_1,
1990 VEX_W_0F4B_P_2_LEN_1,
1991 VEX_W_0F90_P_0_LEN_0,
1992 VEX_W_0F90_P_2_LEN_0,
1993 VEX_W_0F91_P_0_LEN_0,
1994 VEX_W_0F91_P_2_LEN_0,
1995 VEX_W_0F92_P_0_LEN_0,
1996 VEX_W_0F92_P_2_LEN_0,
1997 VEX_W_0F93_P_0_LEN_0,
1998 VEX_W_0F93_P_2_LEN_0,
1999 VEX_W_0F98_P_0_LEN_0,
2000 VEX_W_0F98_P_2_LEN_0,
2001 VEX_W_0F99_P_0_LEN_0,
2002 VEX_W_0F99_P_2_LEN_0,
2010 VEX_W_0F381A_P_2_M_0,
2011 VEX_W_0F382C_P_2_M_0,
2012 VEX_W_0F382D_P_2_M_0,
2013 VEX_W_0F382E_P_2_M_0,
2014 VEX_W_0F382F_P_2_M_0,
2019 VEX_W_0F385A_P_2_M_0,
2031 VEX_W_0F3A30_P_2_LEN_0,
2032 VEX_W_0F3A31_P_2_LEN_0,
2033 VEX_W_0F3A32_P_2_LEN_0,
2034 VEX_W_0F3A33_P_2_LEN_0,
2047 EVEX_W_0F10_P_1_M_0,
2048 EVEX_W_0F10_P_1_M_1,
2050 EVEX_W_0F10_P_3_M_0,
2051 EVEX_W_0F10_P_3_M_1,
2053 EVEX_W_0F11_P_1_M_0,
2054 EVEX_W_0F11_P_1_M_1,
2056 EVEX_W_0F11_P_3_M_0,
2057 EVEX_W_0F11_P_3_M_1,
2058 EVEX_W_0F12_P_0_M_0,
2059 EVEX_W_0F12_P_0_M_1,
2069 EVEX_W_0F16_P_0_M_0,
2070 EVEX_W_0F16_P_0_M_1,
2140 EVEX_W_0F72_R_2_P_2,
2141 EVEX_W_0F72_R_6_P_2,
2142 EVEX_W_0F73_R_2_P_2,
2143 EVEX_W_0F73_R_6_P_2,
2254 EVEX_W_0F38C7_R_1_P_2,
2255 EVEX_W_0F38C7_R_2_P_2,
2256 EVEX_W_0F38C7_R_5_P_2,
2257 EVEX_W_0F38C7_R_6_P_2,
2296 typedef void (*op_rtn) (int bytemode, int sizeflag);
2305 unsigned int prefix_requirement;
2308 /* Upper case letters in the instruction names here are macros.
2309 'A' => print 'b' if no register operands or suffix_always is true
2310 'B' => print 'b' if suffix_always is true
2311 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2313 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2314 suffix_always is true
2315 'E' => print 'e' if 32-bit form of jcxz
2316 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2317 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2318 'H' => print ",pt" or ",pn" branch hint
2319 'I' => honor following macro letter even in Intel mode (implemented only
2320 for some of the macro letters)
2322 'K' => print 'd' or 'q' if rex prefix is present.
2323 'L' => print 'l' if suffix_always is true
2324 'M' => print 'r' if intel_mnemonic is false.
2325 'N' => print 'n' if instruction has no wait "prefix"
2326 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2327 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2328 or suffix_always is true. print 'q' if rex prefix is present.
2329 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2331 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2332 'S' => print 'w', 'l' or 'q' if suffix_always is true
2333 'T' => print 'q' in 64bit mode if instruction has no operand size
2334 prefix and behave as 'P' otherwise
2335 'U' => print 'q' in 64bit mode if instruction has no operand size
2336 prefix and behave as 'Q' otherwise
2337 'V' => print 'q' in 64bit mode if instruction has no operand size
2338 prefix and behave as 'S' otherwise
2339 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2340 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2342 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2343 '!' => change condition from true to false or from false to true.
2344 '%' => add 1 upper case letter to the macro.
2345 '^' => print 'w' or 'l' depending on operand size prefix or
2346 suffix_always is true (lcall/ljmp).
2347 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2348 on operand size prefix.
2349 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2350 has no operand size prefix for AMD64 ISA, behave as 'P'
2353 2 upper case letter macros:
2354 "XY" => print 'x' or 'y' if suffix_always is true or no register
2355 operands and no broadcast.
2356 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2357 register operands and no broadcast.
2358 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2359 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2360 or suffix_always is true
2361 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2362 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2363 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2364 "LW" => print 'd', 'q' depending on the VEX.W bit
2365 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2366 an operand size prefix, or suffix_always is true. print
2367 'q' if rex prefix is present.
2369 Many of the above letters print nothing in Intel mode. See "putop"
2372 Braces '{' and '}', and vertical bars '|', indicate alternative
2373 mnemonic strings for AT&T and Intel. */
2375 static const struct dis386 dis386[] = {
2377 { "addB", { Ebh1, Gb }, 0 },
2378 { "addS", { Evh1, Gv }, 0 },
2379 { "addB", { Gb, EbS }, 0 },
2380 { "addS", { Gv, EvS }, 0 },
2381 { "addB", { AL, Ib }, 0 },
2382 { "addS", { eAX, Iv }, 0 },
2383 { X86_64_TABLE (X86_64_06) },
2384 { X86_64_TABLE (X86_64_07) },
2386 { "orB", { Ebh1, Gb }, 0 },
2387 { "orS", { Evh1, Gv }, 0 },
2388 { "orB", { Gb, EbS }, 0 },
2389 { "orS", { Gv, EvS }, 0 },
2390 { "orB", { AL, Ib }, 0 },
2391 { "orS", { eAX, Iv }, 0 },
2392 { X86_64_TABLE (X86_64_0D) },
2393 { Bad_Opcode }, /* 0x0f extended opcode escape */
2395 { "adcB", { Ebh1, Gb }, 0 },
2396 { "adcS", { Evh1, Gv }, 0 },
2397 { "adcB", { Gb, EbS }, 0 },
2398 { "adcS", { Gv, EvS }, 0 },
2399 { "adcB", { AL, Ib }, 0 },
2400 { "adcS", { eAX, Iv }, 0 },
2401 { X86_64_TABLE (X86_64_16) },
2402 { X86_64_TABLE (X86_64_17) },
2404 { "sbbB", { Ebh1, Gb }, 0 },
2405 { "sbbS", { Evh1, Gv }, 0 },
2406 { "sbbB", { Gb, EbS }, 0 },
2407 { "sbbS", { Gv, EvS }, 0 },
2408 { "sbbB", { AL, Ib }, 0 },
2409 { "sbbS", { eAX, Iv }, 0 },
2410 { X86_64_TABLE (X86_64_1E) },
2411 { X86_64_TABLE (X86_64_1F) },
2413 { "andB", { Ebh1, Gb }, 0 },
2414 { "andS", { Evh1, Gv }, 0 },
2415 { "andB", { Gb, EbS }, 0 },
2416 { "andS", { Gv, EvS }, 0 },
2417 { "andB", { AL, Ib }, 0 },
2418 { "andS", { eAX, Iv }, 0 },
2419 { Bad_Opcode }, /* SEG ES prefix */
2420 { X86_64_TABLE (X86_64_27) },
2422 { "subB", { Ebh1, Gb }, 0 },
2423 { "subS", { Evh1, Gv }, 0 },
2424 { "subB", { Gb, EbS }, 0 },
2425 { "subS", { Gv, EvS }, 0 },
2426 { "subB", { AL, Ib }, 0 },
2427 { "subS", { eAX, Iv }, 0 },
2428 { Bad_Opcode }, /* SEG CS prefix */
2429 { X86_64_TABLE (X86_64_2F) },
2431 { "xorB", { Ebh1, Gb }, 0 },
2432 { "xorS", { Evh1, Gv }, 0 },
2433 { "xorB", { Gb, EbS }, 0 },
2434 { "xorS", { Gv, EvS }, 0 },
2435 { "xorB", { AL, Ib }, 0 },
2436 { "xorS", { eAX, Iv }, 0 },
2437 { Bad_Opcode }, /* SEG SS prefix */
2438 { X86_64_TABLE (X86_64_37) },
2440 { "cmpB", { Eb, Gb }, 0 },
2441 { "cmpS", { Ev, Gv }, 0 },
2442 { "cmpB", { Gb, EbS }, 0 },
2443 { "cmpS", { Gv, EvS }, 0 },
2444 { "cmpB", { AL, Ib }, 0 },
2445 { "cmpS", { eAX, Iv }, 0 },
2446 { Bad_Opcode }, /* SEG DS prefix */
2447 { X86_64_TABLE (X86_64_3F) },
2449 { "inc{S|}", { RMeAX }, 0 },
2450 { "inc{S|}", { RMeCX }, 0 },
2451 { "inc{S|}", { RMeDX }, 0 },
2452 { "inc{S|}", { RMeBX }, 0 },
2453 { "inc{S|}", { RMeSP }, 0 },
2454 { "inc{S|}", { RMeBP }, 0 },
2455 { "inc{S|}", { RMeSI }, 0 },
2456 { "inc{S|}", { RMeDI }, 0 },
2458 { "dec{S|}", { RMeAX }, 0 },
2459 { "dec{S|}", { RMeCX }, 0 },
2460 { "dec{S|}", { RMeDX }, 0 },
2461 { "dec{S|}", { RMeBX }, 0 },
2462 { "dec{S|}", { RMeSP }, 0 },
2463 { "dec{S|}", { RMeBP }, 0 },
2464 { "dec{S|}", { RMeSI }, 0 },
2465 { "dec{S|}", { RMeDI }, 0 },
2467 { "pushV", { RMrAX }, 0 },
2468 { "pushV", { RMrCX }, 0 },
2469 { "pushV", { RMrDX }, 0 },
2470 { "pushV", { RMrBX }, 0 },
2471 { "pushV", { RMrSP }, 0 },
2472 { "pushV", { RMrBP }, 0 },
2473 { "pushV", { RMrSI }, 0 },
2474 { "pushV", { RMrDI }, 0 },
2476 { "popV", { RMrAX }, 0 },
2477 { "popV", { RMrCX }, 0 },
2478 { "popV", { RMrDX }, 0 },
2479 { "popV", { RMrBX }, 0 },
2480 { "popV", { RMrSP }, 0 },
2481 { "popV", { RMrBP }, 0 },
2482 { "popV", { RMrSI }, 0 },
2483 { "popV", { RMrDI }, 0 },
2485 { X86_64_TABLE (X86_64_60) },
2486 { X86_64_TABLE (X86_64_61) },
2487 { X86_64_TABLE (X86_64_62) },
2488 { X86_64_TABLE (X86_64_63) },
2489 { Bad_Opcode }, /* seg fs */
2490 { Bad_Opcode }, /* seg gs */
2491 { Bad_Opcode }, /* op size prefix */
2492 { Bad_Opcode }, /* adr size prefix */
2494 { "pushT", { sIv }, 0 },
2495 { "imulS", { Gv, Ev, Iv }, 0 },
2496 { "pushT", { sIbT }, 0 },
2497 { "imulS", { Gv, Ev, sIb }, 0 },
2498 { "ins{b|}", { Ybr, indirDX }, 0 },
2499 { X86_64_TABLE (X86_64_6D) },
2500 { "outs{b|}", { indirDXr, Xb }, 0 },
2501 { X86_64_TABLE (X86_64_6F) },
2503 { "joH", { Jb, BND, cond_jump_flag }, 0 },
2504 { "jnoH", { Jb, BND, cond_jump_flag }, 0 },
2505 { "jbH", { Jb, BND, cond_jump_flag }, 0 },
2506 { "jaeH", { Jb, BND, cond_jump_flag }, 0 },
2507 { "jeH", { Jb, BND, cond_jump_flag }, 0 },
2508 { "jneH", { Jb, BND, cond_jump_flag }, 0 },
2509 { "jbeH", { Jb, BND, cond_jump_flag }, 0 },
2510 { "jaH", { Jb, BND, cond_jump_flag }, 0 },
2512 { "jsH", { Jb, BND, cond_jump_flag }, 0 },
2513 { "jnsH", { Jb, BND, cond_jump_flag }, 0 },
2514 { "jpH", { Jb, BND, cond_jump_flag }, 0 },
2515 { "jnpH", { Jb, BND, cond_jump_flag }, 0 },
2516 { "jlH", { Jb, BND, cond_jump_flag }, 0 },
2517 { "jgeH", { Jb, BND, cond_jump_flag }, 0 },
2518 { "jleH", { Jb, BND, cond_jump_flag }, 0 },
2519 { "jgH", { Jb, BND, cond_jump_flag }, 0 },
2521 { REG_TABLE (REG_80) },
2522 { REG_TABLE (REG_81) },
2523 { X86_64_TABLE (X86_64_82) },
2524 { REG_TABLE (REG_83) },
2525 { "testB", { Eb, Gb }, 0 },
2526 { "testS", { Ev, Gv }, 0 },
2527 { "xchgB", { Ebh2, Gb }, 0 },
2528 { "xchgS", { Evh2, Gv }, 0 },
2530 { "movB", { Ebh3, Gb }, 0 },
2531 { "movS", { Evh3, Gv }, 0 },
2532 { "movB", { Gb, EbS }, 0 },
2533 { "movS", { Gv, EvS }, 0 },
2534 { "movD", { Sv, Sw }, 0 },
2535 { MOD_TABLE (MOD_8D) },
2536 { "movD", { Sw, Sv }, 0 },
2537 { REG_TABLE (REG_8F) },
2539 { PREFIX_TABLE (PREFIX_90) },
2540 { "xchgS", { RMeCX, eAX }, 0 },
2541 { "xchgS", { RMeDX, eAX }, 0 },
2542 { "xchgS", { RMeBX, eAX }, 0 },
2543 { "xchgS", { RMeSP, eAX }, 0 },
2544 { "xchgS", { RMeBP, eAX }, 0 },
2545 { "xchgS", { RMeSI, eAX }, 0 },
2546 { "xchgS", { RMeDI, eAX }, 0 },
2548 { "cW{t|}R", { XX }, 0 },
2549 { "cR{t|}O", { XX }, 0 },
2550 { X86_64_TABLE (X86_64_9A) },
2551 { Bad_Opcode }, /* fwait */
2552 { "pushfT", { XX }, 0 },
2553 { "popfT", { XX }, 0 },
2554 { "sahf", { XX }, 0 },
2555 { "lahf", { XX }, 0 },
2557 { "mov%LB", { AL, Ob }, 0 },
2558 { "mov%LS", { eAX, Ov }, 0 },
2559 { "mov%LB", { Ob, AL }, 0 },
2560 { "mov%LS", { Ov, eAX }, 0 },
2561 { "movs{b|}", { Ybr, Xb }, 0 },
2562 { "movs{R|}", { Yvr, Xv }, 0 },
2563 { "cmps{b|}", { Xb, Yb }, 0 },
2564 { "cmps{R|}", { Xv, Yv }, 0 },
2566 { "testB", { AL, Ib }, 0 },
2567 { "testS", { eAX, Iv }, 0 },
2568 { "stosB", { Ybr, AL }, 0 },
2569 { "stosS", { Yvr, eAX }, 0 },
2570 { "lodsB", { ALr, Xb }, 0 },
2571 { "lodsS", { eAXr, Xv }, 0 },
2572 { "scasB", { AL, Yb }, 0 },
2573 { "scasS", { eAX, Yv }, 0 },
2575 { "movB", { RMAL, Ib }, 0 },
2576 { "movB", { RMCL, Ib }, 0 },
2577 { "movB", { RMDL, Ib }, 0 },
2578 { "movB", { RMBL, Ib }, 0 },
2579 { "movB", { RMAH, Ib }, 0 },
2580 { "movB", { RMCH, Ib }, 0 },
2581 { "movB", { RMDH, Ib }, 0 },
2582 { "movB", { RMBH, Ib }, 0 },
2584 { "mov%LV", { RMeAX, Iv64 }, 0 },
2585 { "mov%LV", { RMeCX, Iv64 }, 0 },
2586 { "mov%LV", { RMeDX, Iv64 }, 0 },
2587 { "mov%LV", { RMeBX, Iv64 }, 0 },
2588 { "mov%LV", { RMeSP, Iv64 }, 0 },
2589 { "mov%LV", { RMeBP, Iv64 }, 0 },
2590 { "mov%LV", { RMeSI, Iv64 }, 0 },
2591 { "mov%LV", { RMeDI, Iv64 }, 0 },
2593 { REG_TABLE (REG_C0) },
2594 { REG_TABLE (REG_C1) },
2595 { "retT", { Iw, BND }, 0 },
2596 { "retT", { BND }, 0 },
2597 { X86_64_TABLE (X86_64_C4) },
2598 { X86_64_TABLE (X86_64_C5) },
2599 { REG_TABLE (REG_C6) },
2600 { REG_TABLE (REG_C7) },
2602 { "enterT", { Iw, Ib }, 0 },
2603 { "leaveT", { XX }, 0 },
2604 { "Jret{|f}P", { Iw }, 0 },
2605 { "Jret{|f}P", { XX }, 0 },
2606 { "int3", { XX }, 0 },
2607 { "int", { Ib }, 0 },
2608 { X86_64_TABLE (X86_64_CE) },
2609 { "iret%LP", { XX }, 0 },
2611 { REG_TABLE (REG_D0) },
2612 { REG_TABLE (REG_D1) },
2613 { REG_TABLE (REG_D2) },
2614 { REG_TABLE (REG_D3) },
2615 { X86_64_TABLE (X86_64_D4) },
2616 { X86_64_TABLE (X86_64_D5) },
2618 { "xlat", { DSBX }, 0 },
2629 { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 },
2630 { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 },
2631 { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 },
2632 { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 },
2633 { "inB", { AL, Ib }, 0 },
2634 { "inG", { zAX, Ib }, 0 },
2635 { "outB", { Ib, AL }, 0 },
2636 { "outG", { Ib, zAX }, 0 },
2638 { X86_64_TABLE (X86_64_E8) },
2639 { X86_64_TABLE (X86_64_E9) },
2640 { X86_64_TABLE (X86_64_EA) },
2641 { "jmp", { Jb, BND }, 0 },
2642 { "inB", { AL, indirDX }, 0 },
2643 { "inG", { zAX, indirDX }, 0 },
2644 { "outB", { indirDX, AL }, 0 },
2645 { "outG", { indirDX, zAX }, 0 },
2647 { Bad_Opcode }, /* lock prefix */
2648 { "icebp", { XX }, 0 },
2649 { Bad_Opcode }, /* repne */
2650 { Bad_Opcode }, /* repz */
2651 { "hlt", { XX }, 0 },
2652 { "cmc", { XX }, 0 },
2653 { REG_TABLE (REG_F6) },
2654 { REG_TABLE (REG_F7) },
2656 { "clc", { XX }, 0 },
2657 { "stc", { XX }, 0 },
2658 { "cli", { XX }, 0 },
2659 { "sti", { XX }, 0 },
2660 { "cld", { XX }, 0 },
2661 { "std", { XX }, 0 },
2662 { REG_TABLE (REG_FE) },
2663 { REG_TABLE (REG_FF) },
2666 static const struct dis386 dis386_twobyte[] = {
2668 { REG_TABLE (REG_0F00 ) },
2669 { REG_TABLE (REG_0F01 ) },
2670 { "larS", { Gv, Ew }, 0 },
2671 { "lslS", { Gv, Ew }, 0 },
2673 { "syscall", { XX }, 0 },
2674 { "clts", { XX }, 0 },
2675 { "sysret%LP", { XX }, 0 },
2677 { "invd", { XX }, 0 },
2678 { PREFIX_TABLE (PREFIX_0F09) },
2680 { "ud2", { XX }, 0 },
2682 { REG_TABLE (REG_0F0D) },
2683 { "femms", { XX }, 0 },
2684 { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */
2686 { PREFIX_TABLE (PREFIX_0F10) },
2687 { PREFIX_TABLE (PREFIX_0F11) },
2688 { PREFIX_TABLE (PREFIX_0F12) },
2689 { MOD_TABLE (MOD_0F13) },
2690 { "unpcklpX", { XM, EXx }, PREFIX_OPCODE },
2691 { "unpckhpX", { XM, EXx }, PREFIX_OPCODE },
2692 { PREFIX_TABLE (PREFIX_0F16) },
2693 { MOD_TABLE (MOD_0F17) },
2695 { REG_TABLE (REG_0F18) },
2696 { "nopQ", { Ev }, 0 },
2697 { PREFIX_TABLE (PREFIX_0F1A) },
2698 { PREFIX_TABLE (PREFIX_0F1B) },
2699 { PREFIX_TABLE (PREFIX_0F1C) },
2700 { "nopQ", { Ev }, 0 },
2701 { PREFIX_TABLE (PREFIX_0F1E) },
2702 { "nopQ", { Ev }, 0 },
2704 { "movZ", { Rm, Cm }, 0 },
2705 { "movZ", { Rm, Dm }, 0 },
2706 { "movZ", { Cm, Rm }, 0 },
2707 { "movZ", { Dm, Rm }, 0 },
2708 { MOD_TABLE (MOD_0F24) },
2710 { MOD_TABLE (MOD_0F26) },
2713 { "movapX", { XM, EXx }, PREFIX_OPCODE },
2714 { "movapX", { EXxS, XM }, PREFIX_OPCODE },
2715 { PREFIX_TABLE (PREFIX_0F2A) },
2716 { PREFIX_TABLE (PREFIX_0F2B) },
2717 { PREFIX_TABLE (PREFIX_0F2C) },
2718 { PREFIX_TABLE (PREFIX_0F2D) },
2719 { PREFIX_TABLE (PREFIX_0F2E) },
2720 { PREFIX_TABLE (PREFIX_0F2F) },
2722 { "wrmsr", { XX }, 0 },
2723 { "rdtsc", { XX }, 0 },
2724 { "rdmsr", { XX }, 0 },
2725 { "rdpmc", { XX }, 0 },
2726 { "sysenter", { XX }, 0 },
2727 { "sysexit", { XX }, 0 },
2729 { "getsec", { XX }, 0 },
2731 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2733 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2740 { "cmovoS", { Gv, Ev }, 0 },
2741 { "cmovnoS", { Gv, Ev }, 0 },
2742 { "cmovbS", { Gv, Ev }, 0 },
2743 { "cmovaeS", { Gv, Ev }, 0 },
2744 { "cmoveS", { Gv, Ev }, 0 },
2745 { "cmovneS", { Gv, Ev }, 0 },
2746 { "cmovbeS", { Gv, Ev }, 0 },
2747 { "cmovaS", { Gv, Ev }, 0 },
2749 { "cmovsS", { Gv, Ev }, 0 },
2750 { "cmovnsS", { Gv, Ev }, 0 },
2751 { "cmovpS", { Gv, Ev }, 0 },
2752 { "cmovnpS", { Gv, Ev }, 0 },
2753 { "cmovlS", { Gv, Ev }, 0 },
2754 { "cmovgeS", { Gv, Ev }, 0 },
2755 { "cmovleS", { Gv, Ev }, 0 },
2756 { "cmovgS", { Gv, Ev }, 0 },
2758 { MOD_TABLE (MOD_0F51) },
2759 { PREFIX_TABLE (PREFIX_0F51) },
2760 { PREFIX_TABLE (PREFIX_0F52) },
2761 { PREFIX_TABLE (PREFIX_0F53) },
2762 { "andpX", { XM, EXx }, PREFIX_OPCODE },
2763 { "andnpX", { XM, EXx }, PREFIX_OPCODE },
2764 { "orpX", { XM, EXx }, PREFIX_OPCODE },
2765 { "xorpX", { XM, EXx }, PREFIX_OPCODE },
2767 { PREFIX_TABLE (PREFIX_0F58) },
2768 { PREFIX_TABLE (PREFIX_0F59) },
2769 { PREFIX_TABLE (PREFIX_0F5A) },
2770 { PREFIX_TABLE (PREFIX_0F5B) },
2771 { PREFIX_TABLE (PREFIX_0F5C) },
2772 { PREFIX_TABLE (PREFIX_0F5D) },
2773 { PREFIX_TABLE (PREFIX_0F5E) },
2774 { PREFIX_TABLE (PREFIX_0F5F) },
2776 { PREFIX_TABLE (PREFIX_0F60) },
2777 { PREFIX_TABLE (PREFIX_0F61) },
2778 { PREFIX_TABLE (PREFIX_0F62) },
2779 { "packsswb", { MX, EM }, PREFIX_OPCODE },
2780 { "pcmpgtb", { MX, EM }, PREFIX_OPCODE },
2781 { "pcmpgtw", { MX, EM }, PREFIX_OPCODE },
2782 { "pcmpgtd", { MX, EM }, PREFIX_OPCODE },
2783 { "packuswb", { MX, EM }, PREFIX_OPCODE },
2785 { "punpckhbw", { MX, EM }, PREFIX_OPCODE },
2786 { "punpckhwd", { MX, EM }, PREFIX_OPCODE },
2787 { "punpckhdq", { MX, EM }, PREFIX_OPCODE },
2788 { "packssdw", { MX, EM }, PREFIX_OPCODE },
2789 { PREFIX_TABLE (PREFIX_0F6C) },
2790 { PREFIX_TABLE (PREFIX_0F6D) },
2791 { "movK", { MX, Edq }, PREFIX_OPCODE },
2792 { PREFIX_TABLE (PREFIX_0F6F) },
2794 { PREFIX_TABLE (PREFIX_0F70) },
2795 { REG_TABLE (REG_0F71) },
2796 { REG_TABLE (REG_0F72) },
2797 { REG_TABLE (REG_0F73) },
2798 { "pcmpeqb", { MX, EM }, PREFIX_OPCODE },
2799 { "pcmpeqw", { MX, EM }, PREFIX_OPCODE },
2800 { "pcmpeqd", { MX, EM }, PREFIX_OPCODE },
2801 { "emms", { XX }, PREFIX_OPCODE },
2803 { PREFIX_TABLE (PREFIX_0F78) },
2804 { PREFIX_TABLE (PREFIX_0F79) },
2807 { PREFIX_TABLE (PREFIX_0F7C) },
2808 { PREFIX_TABLE (PREFIX_0F7D) },
2809 { PREFIX_TABLE (PREFIX_0F7E) },
2810 { PREFIX_TABLE (PREFIX_0F7F) },
2812 { "joH", { Jv, BND, cond_jump_flag }, 0 },
2813 { "jnoH", { Jv, BND, cond_jump_flag }, 0 },
2814 { "jbH", { Jv, BND, cond_jump_flag }, 0 },
2815 { "jaeH", { Jv, BND, cond_jump_flag }, 0 },
2816 { "jeH", { Jv, BND, cond_jump_flag }, 0 },
2817 { "jneH", { Jv, BND, cond_jump_flag }, 0 },
2818 { "jbeH", { Jv, BND, cond_jump_flag }, 0 },
2819 { "jaH", { Jv, BND, cond_jump_flag }, 0 },
2821 { "jsH", { Jv, BND, cond_jump_flag }, 0 },
2822 { "jnsH", { Jv, BND, cond_jump_flag }, 0 },
2823 { "jpH", { Jv, BND, cond_jump_flag }, 0 },
2824 { "jnpH", { Jv, BND, cond_jump_flag }, 0 },
2825 { "jlH", { Jv, BND, cond_jump_flag }, 0 },
2826 { "jgeH", { Jv, BND, cond_jump_flag }, 0 },
2827 { "jleH", { Jv, BND, cond_jump_flag }, 0 },
2828 { "jgH", { Jv, BND, cond_jump_flag }, 0 },
2830 { "seto", { Eb }, 0 },
2831 { "setno", { Eb }, 0 },
2832 { "setb", { Eb }, 0 },
2833 { "setae", { Eb }, 0 },
2834 { "sete", { Eb }, 0 },
2835 { "setne", { Eb }, 0 },
2836 { "setbe", { Eb }, 0 },
2837 { "seta", { Eb }, 0 },
2839 { "sets", { Eb }, 0 },
2840 { "setns", { Eb }, 0 },
2841 { "setp", { Eb }, 0 },
2842 { "setnp", { Eb }, 0 },
2843 { "setl", { Eb }, 0 },
2844 { "setge", { Eb }, 0 },
2845 { "setle", { Eb }, 0 },
2846 { "setg", { Eb }, 0 },
2848 { "pushT", { fs }, 0 },
2849 { "popT", { fs }, 0 },
2850 { "cpuid", { XX }, 0 },
2851 { "btS", { Ev, Gv }, 0 },
2852 { "shldS", { Ev, Gv, Ib }, 0 },
2853 { "shldS", { Ev, Gv, CL }, 0 },
2854 { REG_TABLE (REG_0FA6) },
2855 { REG_TABLE (REG_0FA7) },
2857 { "pushT", { gs }, 0 },
2858 { "popT", { gs }, 0 },
2859 { "rsm", { XX }, 0 },
2860 { "btsS", { Evh1, Gv }, 0 },
2861 { "shrdS", { Ev, Gv, Ib }, 0 },
2862 { "shrdS", { Ev, Gv, CL }, 0 },
2863 { REG_TABLE (REG_0FAE) },
2864 { "imulS", { Gv, Ev }, 0 },
2866 { "cmpxchgB", { Ebh1, Gb }, 0 },
2867 { "cmpxchgS", { Evh1, Gv }, 0 },
2868 { MOD_TABLE (MOD_0FB2) },
2869 { "btrS", { Evh1, Gv }, 0 },
2870 { MOD_TABLE (MOD_0FB4) },
2871 { MOD_TABLE (MOD_0FB5) },
2872 { "movz{bR|x}", { Gv, Eb }, 0 },
2873 { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2875 { PREFIX_TABLE (PREFIX_0FB8) },
2876 { "ud1S", { Gv, Ev }, 0 },
2877 { REG_TABLE (REG_0FBA) },
2878 { "btcS", { Evh1, Gv }, 0 },
2879 { PREFIX_TABLE (PREFIX_0FBC) },
2880 { PREFIX_TABLE (PREFIX_0FBD) },
2881 { "movs{bR|x}", { Gv, Eb }, 0 },
2882 { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2884 { "xaddB", { Ebh1, Gb }, 0 },
2885 { "xaddS", { Evh1, Gv }, 0 },
2886 { PREFIX_TABLE (PREFIX_0FC2) },
2887 { MOD_TABLE (MOD_0FC3) },
2888 { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE },
2889 { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE },
2890 { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE },
2891 { REG_TABLE (REG_0FC7) },
2893 { "bswap", { RMeAX }, 0 },
2894 { "bswap", { RMeCX }, 0 },
2895 { "bswap", { RMeDX }, 0 },
2896 { "bswap", { RMeBX }, 0 },
2897 { "bswap", { RMeSP }, 0 },
2898 { "bswap", { RMeBP }, 0 },
2899 { "bswap", { RMeSI }, 0 },
2900 { "bswap", { RMeDI }, 0 },
2902 { PREFIX_TABLE (PREFIX_0FD0) },
2903 { "psrlw", { MX, EM }, PREFIX_OPCODE },
2904 { "psrld", { MX, EM }, PREFIX_OPCODE },
2905 { "psrlq", { MX, EM }, PREFIX_OPCODE },
2906 { "paddq", { MX, EM }, PREFIX_OPCODE },
2907 { "pmullw", { MX, EM }, PREFIX_OPCODE },
2908 { PREFIX_TABLE (PREFIX_0FD6) },
2909 { MOD_TABLE (MOD_0FD7) },
2911 { "psubusb", { MX, EM }, PREFIX_OPCODE },
2912 { "psubusw", { MX, EM }, PREFIX_OPCODE },
2913 { "pminub", { MX, EM }, PREFIX_OPCODE },
2914 { "pand", { MX, EM }, PREFIX_OPCODE },
2915 { "paddusb", { MX, EM }, PREFIX_OPCODE },
2916 { "paddusw", { MX, EM }, PREFIX_OPCODE },
2917 { "pmaxub", { MX, EM }, PREFIX_OPCODE },
2918 { "pandn", { MX, EM }, PREFIX_OPCODE },
2920 { "pavgb", { MX, EM }, PREFIX_OPCODE },
2921 { "psraw", { MX, EM }, PREFIX_OPCODE },
2922 { "psrad", { MX, EM }, PREFIX_OPCODE },
2923 { "pavgw", { MX, EM }, PREFIX_OPCODE },
2924 { "pmulhuw", { MX, EM }, PREFIX_OPCODE },
2925 { "pmulhw", { MX, EM }, PREFIX_OPCODE },
2926 { PREFIX_TABLE (PREFIX_0FE6) },
2927 { PREFIX_TABLE (PREFIX_0FE7) },
2929 { "psubsb", { MX, EM }, PREFIX_OPCODE },
2930 { "psubsw", { MX, EM }, PREFIX_OPCODE },
2931 { "pminsw", { MX, EM }, PREFIX_OPCODE },
2932 { "por", { MX, EM }, PREFIX_OPCODE },
2933 { "paddsb", { MX, EM }, PREFIX_OPCODE },
2934 { "paddsw", { MX, EM }, PREFIX_OPCODE },
2935 { "pmaxsw", { MX, EM }, PREFIX_OPCODE },
2936 { "pxor", { MX, EM }, PREFIX_OPCODE },
2938 { PREFIX_TABLE (PREFIX_0FF0) },
2939 { "psllw", { MX, EM }, PREFIX_OPCODE },
2940 { "pslld", { MX, EM }, PREFIX_OPCODE },
2941 { "psllq", { MX, EM }, PREFIX_OPCODE },
2942 { "pmuludq", { MX, EM }, PREFIX_OPCODE },
2943 { "pmaddwd", { MX, EM }, PREFIX_OPCODE },
2944 { "psadbw", { MX, EM }, PREFIX_OPCODE },
2945 { PREFIX_TABLE (PREFIX_0FF7) },
2947 { "psubb", { MX, EM }, PREFIX_OPCODE },
2948 { "psubw", { MX, EM }, PREFIX_OPCODE },
2949 { "psubd", { MX, EM }, PREFIX_OPCODE },
2950 { "psubq", { MX, EM }, PREFIX_OPCODE },
2951 { "paddb", { MX, EM }, PREFIX_OPCODE },
2952 { "paddw", { MX, EM }, PREFIX_OPCODE },
2953 { "paddd", { MX, EM }, PREFIX_OPCODE },
2954 { "ud0S", { Gv, Ev }, 0 },
2957 static const unsigned char onebyte_has_modrm[256] = {
2958 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2959 /* ------------------------------- */
2960 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2961 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2962 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2963 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2964 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2965 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2966 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2967 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2968 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2969 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2970 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2971 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2972 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2973 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2974 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2975 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2976 /* ------------------------------- */
2977 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2980 static const unsigned char twobyte_has_modrm[256] = {
2981 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2982 /* ------------------------------- */
2983 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2984 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2985 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2986 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2987 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2988 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2989 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2990 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2991 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2992 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2993 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2994 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2995 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2996 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2997 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2998 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
2999 /* ------------------------------- */
3000 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3003 static char obuf[100];
3005 static char *mnemonicendp;
3006 static char scratchbuf[100];
3007 static unsigned char *start_codep;
3008 static unsigned char *insn_codep;
3009 static unsigned char *codep;
3010 static unsigned char *end_codep;
3011 static int last_lock_prefix;
3012 static int last_repz_prefix;
3013 static int last_repnz_prefix;
3014 static int last_data_prefix;
3015 static int last_addr_prefix;
3016 static int last_rex_prefix;
3017 static int last_seg_prefix;
3018 static int fwait_prefix;
3019 /* The active segment register prefix. */
3020 static int active_seg_prefix;
3021 #define MAX_CODE_LENGTH 15
3022 /* We can up to 14 prefixes since the maximum instruction length is
3024 static int all_prefixes[MAX_CODE_LENGTH - 1];
3025 static disassemble_info *the_info;
3033 static unsigned char need_modrm;
3043 int register_specifier;
3050 int mask_register_specifier;
3056 static unsigned char need_vex;
3057 static unsigned char need_vex_reg;
3058 static unsigned char vex_w_done;
3066 /* If we are accessing mod/rm/reg without need_modrm set, then the
3067 values are stale. Hitting this abort likely indicates that you
3068 need to update onebyte_has_modrm or twobyte_has_modrm. */
3069 #define MODRM_CHECK if (!need_modrm) abort ()
3071 static const char **names64;
3072 static const char **names32;
3073 static const char **names16;
3074 static const char **names8;
3075 static const char **names8rex;
3076 static const char **names_seg;
3077 static const char *index64;
3078 static const char *index32;
3079 static const char **index16;
3080 static const char **names_bnd;
3082 static const char *intel_names64[] = {
3083 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3084 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3086 static const char *intel_names32[] = {
3087 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3088 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3090 static const char *intel_names16[] = {
3091 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3092 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3094 static const char *intel_names8[] = {
3095 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3097 static const char *intel_names8rex[] = {
3098 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3099 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3101 static const char *intel_names_seg[] = {
3102 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3104 static const char *intel_index64 = "riz";
3105 static const char *intel_index32 = "eiz";
3106 static const char *intel_index16[] = {
3107 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3110 static const char *att_names64[] = {
3111 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3112 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3114 static const char *att_names32[] = {
3115 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3116 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3118 static const char *att_names16[] = {
3119 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3120 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3122 static const char *att_names8[] = {
3123 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3125 static const char *att_names8rex[] = {
3126 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3127 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3129 static const char *att_names_seg[] = {
3130 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3132 static const char *att_index64 = "%riz";
3133 static const char *att_index32 = "%eiz";
3134 static const char *att_index16[] = {
3135 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3138 static const char **names_mm;
3139 static const char *intel_names_mm[] = {
3140 "mm0", "mm1", "mm2", "mm3",
3141 "mm4", "mm5", "mm6", "mm7"
3143 static const char *att_names_mm[] = {
3144 "%mm0", "%mm1", "%mm2", "%mm3",
3145 "%mm4", "%mm5", "%mm6", "%mm7"
3148 static const char *intel_names_bnd[] = {
3149 "bnd0", "bnd1", "bnd2", "bnd3"
3152 static const char *att_names_bnd[] = {
3153 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3156 static const char **names_xmm;
3157 static const char *intel_names_xmm[] = {
3158 "xmm0", "xmm1", "xmm2", "xmm3",
3159 "xmm4", "xmm5", "xmm6", "xmm7",
3160 "xmm8", "xmm9", "xmm10", "xmm11",
3161 "xmm12", "xmm13", "xmm14", "xmm15",
3162 "xmm16", "xmm17", "xmm18", "xmm19",
3163 "xmm20", "xmm21", "xmm22", "xmm23",
3164 "xmm24", "xmm25", "xmm26", "xmm27",
3165 "xmm28", "xmm29", "xmm30", "xmm31"
3167 static const char *att_names_xmm[] = {
3168 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3169 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3170 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3171 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3172 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3173 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3174 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3175 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3178 static const char **names_ymm;
3179 static const char *intel_names_ymm[] = {
3180 "ymm0", "ymm1", "ymm2", "ymm3",
3181 "ymm4", "ymm5", "ymm6", "ymm7",
3182 "ymm8", "ymm9", "ymm10", "ymm11",
3183 "ymm12", "ymm13", "ymm14", "ymm15",
3184 "ymm16", "ymm17", "ymm18", "ymm19",
3185 "ymm20", "ymm21", "ymm22", "ymm23",
3186 "ymm24", "ymm25", "ymm26", "ymm27",
3187 "ymm28", "ymm29", "ymm30", "ymm31"
3189 static const char *att_names_ymm[] = {
3190 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3191 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3192 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3193 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3194 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3195 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3196 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3197 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3200 static const char **names_zmm;
3201 static const char *intel_names_zmm[] = {
3202 "zmm0", "zmm1", "zmm2", "zmm3",
3203 "zmm4", "zmm5", "zmm6", "zmm7",
3204 "zmm8", "zmm9", "zmm10", "zmm11",
3205 "zmm12", "zmm13", "zmm14", "zmm15",
3206 "zmm16", "zmm17", "zmm18", "zmm19",
3207 "zmm20", "zmm21", "zmm22", "zmm23",
3208 "zmm24", "zmm25", "zmm26", "zmm27",
3209 "zmm28", "zmm29", "zmm30", "zmm31"
3211 static const char *att_names_zmm[] = {
3212 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3213 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3214 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3215 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3216 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3217 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3218 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3219 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3222 static const char **names_mask;
3223 static const char *intel_names_mask[] = {
3224 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3226 static const char *att_names_mask[] = {
3227 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3230 static const char *names_rounding[] =
3238 static const struct dis386 reg_table[][8] = {
3241 { "addA", { Ebh1, Ib }, 0 },
3242 { "orA", { Ebh1, Ib }, 0 },
3243 { "adcA", { Ebh1, Ib }, 0 },
3244 { "sbbA", { Ebh1, Ib }, 0 },
3245 { "andA", { Ebh1, Ib }, 0 },
3246 { "subA", { Ebh1, Ib }, 0 },
3247 { "xorA", { Ebh1, Ib }, 0 },
3248 { "cmpA", { Eb, Ib }, 0 },
3252 { "addQ", { Evh1, Iv }, 0 },
3253 { "orQ", { Evh1, Iv }, 0 },
3254 { "adcQ", { Evh1, Iv }, 0 },
3255 { "sbbQ", { Evh1, Iv }, 0 },
3256 { "andQ", { Evh1, Iv }, 0 },
3257 { "subQ", { Evh1, Iv }, 0 },
3258 { "xorQ", { Evh1, Iv }, 0 },
3259 { "cmpQ", { Ev, Iv }, 0 },
3263 { "addQ", { Evh1, sIb }, 0 },
3264 { "orQ", { Evh1, sIb }, 0 },
3265 { "adcQ", { Evh1, sIb }, 0 },
3266 { "sbbQ", { Evh1, sIb }, 0 },
3267 { "andQ", { Evh1, sIb }, 0 },
3268 { "subQ", { Evh1, sIb }, 0 },
3269 { "xorQ", { Evh1, sIb }, 0 },
3270 { "cmpQ", { Ev, sIb }, 0 },
3274 { "popU", { stackEv }, 0 },
3275 { XOP_8F_TABLE (XOP_09) },
3279 { XOP_8F_TABLE (XOP_09) },
3283 { "rolA", { Eb, Ib }, 0 },
3284 { "rorA", { Eb, Ib }, 0 },
3285 { "rclA", { Eb, Ib }, 0 },
3286 { "rcrA", { Eb, Ib }, 0 },
3287 { "shlA", { Eb, Ib }, 0 },
3288 { "shrA", { Eb, Ib }, 0 },
3289 { "shlA", { Eb, Ib }, 0 },
3290 { "sarA", { Eb, Ib }, 0 },
3294 { "rolQ", { Ev, Ib }, 0 },
3295 { "rorQ", { Ev, Ib }, 0 },
3296 { "rclQ", { Ev, Ib }, 0 },
3297 { "rcrQ", { Ev, Ib }, 0 },
3298 { "shlQ", { Ev, Ib }, 0 },
3299 { "shrQ", { Ev, Ib }, 0 },
3300 { "shlQ", { Ev, Ib }, 0 },
3301 { "sarQ", { Ev, Ib }, 0 },
3305 { "movA", { Ebh3, Ib }, 0 },
3312 { MOD_TABLE (MOD_C6_REG_7) },
3316 { "movQ", { Evh3, Iv }, 0 },
3323 { MOD_TABLE (MOD_C7_REG_7) },
3327 { "rolA", { Eb, I1 }, 0 },
3328 { "rorA", { Eb, I1 }, 0 },
3329 { "rclA", { Eb, I1 }, 0 },
3330 { "rcrA", { Eb, I1 }, 0 },
3331 { "shlA", { Eb, I1 }, 0 },
3332 { "shrA", { Eb, I1 }, 0 },
3333 { "shlA", { Eb, I1 }, 0 },
3334 { "sarA", { Eb, I1 }, 0 },
3338 { "rolQ", { Ev, I1 }, 0 },
3339 { "rorQ", { Ev, I1 }, 0 },
3340 { "rclQ", { Ev, I1 }, 0 },
3341 { "rcrQ", { Ev, I1 }, 0 },
3342 { "shlQ", { Ev, I1 }, 0 },
3343 { "shrQ", { Ev, I1 }, 0 },
3344 { "shlQ", { Ev, I1 }, 0 },
3345 { "sarQ", { Ev, I1 }, 0 },
3349 { "rolA", { Eb, CL }, 0 },
3350 { "rorA", { Eb, CL }, 0 },
3351 { "rclA", { Eb, CL }, 0 },
3352 { "rcrA", { Eb, CL }, 0 },
3353 { "shlA", { Eb, CL }, 0 },
3354 { "shrA", { Eb, CL }, 0 },
3355 { "shlA", { Eb, CL }, 0 },
3356 { "sarA", { Eb, CL }, 0 },
3360 { "rolQ", { Ev, CL }, 0 },
3361 { "rorQ", { Ev, CL }, 0 },
3362 { "rclQ", { Ev, CL }, 0 },
3363 { "rcrQ", { Ev, CL }, 0 },
3364 { "shlQ", { Ev, CL }, 0 },
3365 { "shrQ", { Ev, CL }, 0 },
3366 { "shlQ", { Ev, CL }, 0 },
3367 { "sarQ", { Ev, CL }, 0 },
3371 { "testA", { Eb, Ib }, 0 },
3372 { "testA", { Eb, Ib }, 0 },
3373 { "notA", { Ebh1 }, 0 },
3374 { "negA", { Ebh1 }, 0 },
3375 { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */
3376 { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */
3377 { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */
3378 { "idivA", { Eb }, 0 }, /* and idiv for consistency. */
3382 { "testQ", { Ev, Iv }, 0 },
3383 { "testQ", { Ev, Iv }, 0 },
3384 { "notQ", { Evh1 }, 0 },
3385 { "negQ", { Evh1 }, 0 },
3386 { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */
3387 { "imulQ", { Ev }, 0 },
3388 { "divQ", { Ev }, 0 },
3389 { "idivQ", { Ev }, 0 },
3393 { "incA", { Ebh1 }, 0 },
3394 { "decA", { Ebh1 }, 0 },
3398 { "incQ", { Evh1 }, 0 },
3399 { "decQ", { Evh1 }, 0 },
3400 { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3401 { MOD_TABLE (MOD_FF_REG_3) },
3402 { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3403 { MOD_TABLE (MOD_FF_REG_5) },
3404 { "pushU", { stackEv }, 0 },
3409 { "sldtD", { Sv }, 0 },
3410 { "strD", { Sv }, 0 },
3411 { "lldt", { Ew }, 0 },
3412 { "ltr", { Ew }, 0 },
3413 { "verr", { Ew }, 0 },
3414 { "verw", { Ew }, 0 },
3420 { MOD_TABLE (MOD_0F01_REG_0) },
3421 { MOD_TABLE (MOD_0F01_REG_1) },
3422 { MOD_TABLE (MOD_0F01_REG_2) },
3423 { MOD_TABLE (MOD_0F01_REG_3) },
3424 { "smswD", { Sv }, 0 },
3425 { MOD_TABLE (MOD_0F01_REG_5) },
3426 { "lmsw", { Ew }, 0 },
3427 { MOD_TABLE (MOD_0F01_REG_7) },
3431 { "prefetch", { Mb }, 0 },
3432 { "prefetchw", { Mb }, 0 },
3433 { "prefetchwt1", { Mb }, 0 },
3434 { "prefetch", { Mb }, 0 },
3435 { "prefetch", { Mb }, 0 },
3436 { "prefetch", { Mb }, 0 },
3437 { "prefetch", { Mb }, 0 },
3438 { "prefetch", { Mb }, 0 },
3442 { MOD_TABLE (MOD_0F18_REG_0) },
3443 { MOD_TABLE (MOD_0F18_REG_1) },
3444 { MOD_TABLE (MOD_0F18_REG_2) },
3445 { MOD_TABLE (MOD_0F18_REG_3) },
3446 { MOD_TABLE (MOD_0F18_REG_4) },
3447 { MOD_TABLE (MOD_0F18_REG_5) },
3448 { MOD_TABLE (MOD_0F18_REG_6) },
3449 { MOD_TABLE (MOD_0F18_REG_7) },
3451 /* REG_0F1C_MOD_0 */
3453 { "cldemote", { Mb }, 0 },
3454 { "nopQ", { Ev }, 0 },
3455 { "nopQ", { Ev }, 0 },
3456 { "nopQ", { Ev }, 0 },
3457 { "nopQ", { Ev }, 0 },
3458 { "nopQ", { Ev }, 0 },
3459 { "nopQ", { Ev }, 0 },
3460 { "nopQ", { Ev }, 0 },
3462 /* REG_0F1E_MOD_3 */
3464 { "nopQ", { Ev }, 0 },
3465 { "rdsspK", { Rdq }, PREFIX_OPCODE },
3466 { "nopQ", { Ev }, 0 },
3467 { "nopQ", { Ev }, 0 },
3468 { "nopQ", { Ev }, 0 },
3469 { "nopQ", { Ev }, 0 },
3470 { "nopQ", { Ev }, 0 },
3471 { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
3477 { MOD_TABLE (MOD_0F71_REG_2) },
3479 { MOD_TABLE (MOD_0F71_REG_4) },
3481 { MOD_TABLE (MOD_0F71_REG_6) },
3487 { MOD_TABLE (MOD_0F72_REG_2) },
3489 { MOD_TABLE (MOD_0F72_REG_4) },
3491 { MOD_TABLE (MOD_0F72_REG_6) },
3497 { MOD_TABLE (MOD_0F73_REG_2) },
3498 { MOD_TABLE (MOD_0F73_REG_3) },
3501 { MOD_TABLE (MOD_0F73_REG_6) },
3502 { MOD_TABLE (MOD_0F73_REG_7) },
3506 { "montmul", { { OP_0f07, 0 } }, 0 },
3507 { "xsha1", { { OP_0f07, 0 } }, 0 },
3508 { "xsha256", { { OP_0f07, 0 } }, 0 },
3512 { "xstore-rng", { { OP_0f07, 0 } }, 0 },
3513 { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 },
3514 { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 },
3515 { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 },
3516 { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 },
3517 { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 },
3521 { MOD_TABLE (MOD_0FAE_REG_0) },
3522 { MOD_TABLE (MOD_0FAE_REG_1) },
3523 { MOD_TABLE (MOD_0FAE_REG_2) },
3524 { MOD_TABLE (MOD_0FAE_REG_3) },
3525 { MOD_TABLE (MOD_0FAE_REG_4) },
3526 { MOD_TABLE (MOD_0FAE_REG_5) },
3527 { MOD_TABLE (MOD_0FAE_REG_6) },
3528 { MOD_TABLE (MOD_0FAE_REG_7) },
3536 { "btQ", { Ev, Ib }, 0 },
3537 { "btsQ", { Evh1, Ib }, 0 },
3538 { "btrQ", { Evh1, Ib }, 0 },
3539 { "btcQ", { Evh1, Ib }, 0 },
3544 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3546 { MOD_TABLE (MOD_0FC7_REG_3) },
3547 { MOD_TABLE (MOD_0FC7_REG_4) },
3548 { MOD_TABLE (MOD_0FC7_REG_5) },
3549 { MOD_TABLE (MOD_0FC7_REG_6) },
3550 { MOD_TABLE (MOD_0FC7_REG_7) },
3556 { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3558 { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3560 { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3566 { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3568 { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3570 { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3576 { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3577 { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3580 { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3581 { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3587 { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3588 { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3590 /* REG_VEX_0F38F3 */
3593 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3594 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3595 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3599 { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3600 { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3604 { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3605 { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3607 /* REG_XOP_TBM_01 */
3610 { "blcfill", { { OP_LWP_E, 0 }, Ev }, 0 },
3611 { "blsfill", { { OP_LWP_E, 0 }, Ev }, 0 },
3612 { "blcs", { { OP_LWP_E, 0 }, Ev }, 0 },
3613 { "tzmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3614 { "blcic", { { OP_LWP_E, 0 }, Ev }, 0 },
3615 { "blsic", { { OP_LWP_E, 0 }, Ev }, 0 },
3616 { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3618 /* REG_XOP_TBM_02 */
3621 { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3626 { "blci", { { OP_LWP_E, 0 }, Ev }, 0 },
3628 #define NEED_REG_TABLE
3629 #include "i386-dis-evex.h"
3630 #undef NEED_REG_TABLE
3633 static const struct dis386 prefix_table[][4] = {
3636 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3637 { "pause", { XX }, 0 },
3638 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3639 { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3642 /* PREFIX_MOD_0_0F01_REG_5 */
3645 { "rstorssp", { Mq }, PREFIX_OPCODE },
3648 /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3651 { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE },
3654 /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3657 { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE },
3662 { "wbinvd", { XX }, 0 },
3663 { "wbnoinvd", { XX }, 0 },
3668 { "movups", { XM, EXx }, PREFIX_OPCODE },
3669 { "movss", { XM, EXd }, PREFIX_OPCODE },
3670 { "movupd", { XM, EXx }, PREFIX_OPCODE },
3671 { "movsd", { XM, EXq }, PREFIX_OPCODE },
3676 { "movups", { EXxS, XM }, PREFIX_OPCODE },
3677 { "movss", { EXdS, XM }, PREFIX_OPCODE },
3678 { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3679 { "movsd", { EXqS, XM }, PREFIX_OPCODE },
3684 { MOD_TABLE (MOD_0F12_PREFIX_0) },
3685 { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3686 { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3687 { "movddup", { XM, EXq }, PREFIX_OPCODE },
3692 { MOD_TABLE (MOD_0F16_PREFIX_0) },
3693 { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3694 { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3699 { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3700 { "bndcl", { Gbnd, Ev_bnd }, 0 },
3701 { "bndmov", { Gbnd, Ebnd }, 0 },
3702 { "bndcu", { Gbnd, Ev_bnd }, 0 },
3707 { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3708 { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3709 { "bndmov", { EbndS, Gbnd }, 0 },
3710 { "bndcn", { Gbnd, Ev_bnd }, 0 },
3715 { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3716 { "nopQ", { Ev }, PREFIX_OPCODE },
3717 { "nopQ", { Ev }, PREFIX_OPCODE },
3718 { "nopQ", { Ev }, PREFIX_OPCODE },
3723 { "nopQ", { Ev }, PREFIX_OPCODE },
3724 { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3725 { "nopQ", { Ev }, PREFIX_OPCODE },
3726 { "nopQ", { Ev }, PREFIX_OPCODE },
3731 { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3732 { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3733 { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3734 { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3739 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3740 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3741 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3742 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3747 { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3748 { "cvttss2si", { Gv, EXd }, PREFIX_OPCODE },
3749 { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3750 { "cvttsd2si", { Gv, EXq }, PREFIX_OPCODE },
3755 { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3756 { "cvtss2si", { Gv, EXd }, PREFIX_OPCODE },
3757 { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3758 { "cvtsd2si", { Gv, EXq }, PREFIX_OPCODE },
3763 { "ucomiss",{ XM, EXd }, 0 },
3765 { "ucomisd",{ XM, EXq }, 0 },
3770 { "comiss", { XM, EXd }, 0 },
3772 { "comisd", { XM, EXq }, 0 },
3777 { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3778 { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3779 { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3780 { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3785 { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3786 { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3791 { "rcpps", { XM, EXx }, PREFIX_OPCODE },
3792 { "rcpss", { XM, EXd }, PREFIX_OPCODE },
3797 { "addps", { XM, EXx }, PREFIX_OPCODE },
3798 { "addss", { XM, EXd }, PREFIX_OPCODE },
3799 { "addpd", { XM, EXx }, PREFIX_OPCODE },
3800 { "addsd", { XM, EXq }, PREFIX_OPCODE },
3805 { "mulps", { XM, EXx }, PREFIX_OPCODE },
3806 { "mulss", { XM, EXd }, PREFIX_OPCODE },
3807 { "mulpd", { XM, EXx }, PREFIX_OPCODE },
3808 { "mulsd", { XM, EXq }, PREFIX_OPCODE },
3813 { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3814 { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3815 { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3816 { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3821 { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3822 { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3823 { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3828 { "subps", { XM, EXx }, PREFIX_OPCODE },
3829 { "subss", { XM, EXd }, PREFIX_OPCODE },
3830 { "subpd", { XM, EXx }, PREFIX_OPCODE },
3831 { "subsd", { XM, EXq }, PREFIX_OPCODE },
3836 { "minps", { XM, EXx }, PREFIX_OPCODE },
3837 { "minss", { XM, EXd }, PREFIX_OPCODE },
3838 { "minpd", { XM, EXx }, PREFIX_OPCODE },
3839 { "minsd", { XM, EXq }, PREFIX_OPCODE },
3844 { "divps", { XM, EXx }, PREFIX_OPCODE },
3845 { "divss", { XM, EXd }, PREFIX_OPCODE },
3846 { "divpd", { XM, EXx }, PREFIX_OPCODE },
3847 { "divsd", { XM, EXq }, PREFIX_OPCODE },
3852 { "maxps", { XM, EXx }, PREFIX_OPCODE },
3853 { "maxss", { XM, EXd }, PREFIX_OPCODE },
3854 { "maxpd", { XM, EXx }, PREFIX_OPCODE },
3855 { "maxsd", { XM, EXq }, PREFIX_OPCODE },
3860 { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3862 { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3867 { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3869 { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3874 { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3876 { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3883 { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3890 { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3895 { "movq", { MX, EM }, PREFIX_OPCODE },
3896 { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3897 { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3902 { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3903 { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3904 { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3905 { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3908 /* PREFIX_0F73_REG_3 */
3912 { "psrldq", { XS, Ib }, 0 },
3915 /* PREFIX_0F73_REG_7 */
3919 { "pslldq", { XS, Ib }, 0 },
3924 {"vmread", { Em, Gm }, 0 },
3926 {"extrq", { XS, Ib, Ib }, 0 },
3927 {"insertq", { XM, XS, Ib, Ib }, 0 },
3932 {"vmwrite", { Gm, Em }, 0 },
3934 {"extrq", { XM, XS }, 0 },
3935 {"insertq", { XM, XS }, 0 },
3942 { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3943 { "haddps", { XM, EXx }, PREFIX_OPCODE },
3950 { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3951 { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3956 { "movK", { Edq, MX }, PREFIX_OPCODE },
3957 { "movq", { XM, EXq }, PREFIX_OPCODE },
3958 { "movK", { Edq, XM }, PREFIX_OPCODE },
3963 { "movq", { EMS, MX }, PREFIX_OPCODE },
3964 { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3965 { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3968 /* PREFIX_0FAE_REG_0 */
3971 { "rdfsbase", { Ev }, 0 },
3974 /* PREFIX_0FAE_REG_1 */
3977 { "rdgsbase", { Ev }, 0 },
3980 /* PREFIX_0FAE_REG_2 */
3983 { "wrfsbase", { Ev }, 0 },
3986 /* PREFIX_0FAE_REG_3 */
3989 { "wrgsbase", { Ev }, 0 },
3992 /* PREFIX_MOD_0_0FAE_REG_4 */
3994 { "xsave", { FXSAVE }, 0 },
3995 { "ptwrite%LQ", { Edq }, 0 },
3998 /* PREFIX_MOD_3_0FAE_REG_4 */
4001 { "ptwrite%LQ", { Edq }, 0 },
4004 /* PREFIX_MOD_0_0FAE_REG_5 */
4006 { "xrstor", { FXSAVE }, PREFIX_OPCODE },
4009 /* PREFIX_MOD_3_0FAE_REG_5 */
4011 { "lfence", { Skip_MODRM }, 0 },
4012 { "incsspK", { Rdq }, PREFIX_OPCODE },
4015 /* PREFIX_MOD_0_0FAE_REG_6 */
4017 { "xsaveopt", { FXSAVE }, PREFIX_OPCODE },
4018 { "clrssbsy", { Mq }, PREFIX_OPCODE },
4019 { "clwb", { Mb }, PREFIX_OPCODE },
4022 /* PREFIX_MOD_1_0FAE_REG_6 */
4024 { RM_TABLE (RM_0FAE_REG_6) },
4025 { "umonitor", { Eva }, PREFIX_OPCODE },
4026 { "tpause", { Edq }, PREFIX_OPCODE },
4027 { "umwait", { Edq }, PREFIX_OPCODE },
4030 /* PREFIX_0FAE_REG_7 */
4032 { "clflush", { Mb }, 0 },
4034 { "clflushopt", { Mb }, 0 },
4040 { "popcntS", { Gv, Ev }, 0 },
4045 { "bsfS", { Gv, Ev }, 0 },
4046 { "tzcntS", { Gv, Ev }, 0 },
4047 { "bsfS", { Gv, Ev }, 0 },
4052 { "bsrS", { Gv, Ev }, 0 },
4053 { "lzcntS", { Gv, Ev }, 0 },
4054 { "bsrS", { Gv, Ev }, 0 },
4059 { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE },
4060 { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE },
4061 { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE },
4062 { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE },
4065 /* PREFIX_MOD_0_0FC3 */
4067 { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4070 /* PREFIX_MOD_0_0FC7_REG_6 */
4072 { "vmptrld",{ Mq }, 0 },
4073 { "vmxon", { Mq }, 0 },
4074 { "vmclear",{ Mq }, 0 },
4077 /* PREFIX_MOD_3_0FC7_REG_6 */
4079 { "rdrand", { Ev }, 0 },
4081 { "rdrand", { Ev }, 0 }
4084 /* PREFIX_MOD_3_0FC7_REG_7 */
4086 { "rdseed", { Ev }, 0 },
4087 { "rdpid", { Em }, 0 },
4088 { "rdseed", { Ev }, 0 },
4095 { "addsubpd", { XM, EXx }, 0 },
4096 { "addsubps", { XM, EXx }, 0 },
4102 { "movq2dq",{ XM, MS }, 0 },
4103 { "movq", { EXqS, XM }, 0 },
4104 { "movdq2q",{ MX, XS }, 0 },
4110 { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4111 { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4112 { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4117 { "movntq", { Mq, MX }, PREFIX_OPCODE },
4119 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4127 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4132 { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4134 { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4141 { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4148 { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4155 { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4162 { "ptest", { XM, EXx }, PREFIX_OPCODE },
4169 { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4176 { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4183 { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4190 { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4197 { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4204 { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4211 { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4218 { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4225 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4232 { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4239 { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4246 { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4253 { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4260 { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4267 { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4274 { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4281 { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4288 { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4295 { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4302 { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4309 { "pminud", { XM, EXx }, PREFIX_OPCODE },
4316 { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4323 { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4330 { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4337 { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4344 { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4351 { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4358 { "invept", { Gm, Mo }, PREFIX_OPCODE },
4365 { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4372 { "invpcid", { Gm, M }, PREFIX_OPCODE },
4377 { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4382 { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4387 { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4392 { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4397 { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4402 { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4409 { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4416 { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4423 { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4430 { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4437 { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4444 { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4449 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4451 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4452 { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4457 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4459 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4460 { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4467 { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4472 { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4473 { "adoxS", { Gdq, Edq}, PREFIX_OPCODE },
4474 { "adcxS", { Gdq, Edq}, PREFIX_OPCODE },
4481 { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
4482 { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4483 { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
4488 { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4495 { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4502 { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4509 { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4516 { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4523 { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4530 { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4537 { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4544 { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4551 { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4558 { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4565 { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4572 { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4579 { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4586 { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4593 { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE },
4600 { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE },
4607 { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4614 { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4621 { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4628 { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4635 { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4642 { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4647 { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4654 { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4661 { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4668 { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4671 /* PREFIX_VEX_0F10 */
4673 { "vmovups", { XM, EXx }, 0 },
4674 { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 },
4675 { "vmovupd", { XM, EXx }, 0 },
4676 { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 },
4679 /* PREFIX_VEX_0F11 */
4681 { "vmovups", { EXxS, XM }, 0 },
4682 { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4683 { "vmovupd", { EXxS, XM }, 0 },
4684 { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4687 /* PREFIX_VEX_0F12 */
4689 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4690 { "vmovsldup", { XM, EXx }, 0 },
4691 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4692 { "vmovddup", { XM, EXymmq }, 0 },
4695 /* PREFIX_VEX_0F16 */
4697 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4698 { "vmovshdup", { XM, EXx }, 0 },
4699 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4702 /* PREFIX_VEX_0F2A */
4705 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4707 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4710 /* PREFIX_VEX_0F2C */
4713 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4715 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4718 /* PREFIX_VEX_0F2D */
4721 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4723 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4726 /* PREFIX_VEX_0F2E */
4728 { "vucomiss", { XMScalar, EXdScalar }, 0 },
4730 { "vucomisd", { XMScalar, EXqScalar }, 0 },
4733 /* PREFIX_VEX_0F2F */
4735 { "vcomiss", { XMScalar, EXdScalar }, 0 },
4737 { "vcomisd", { XMScalar, EXqScalar }, 0 },
4740 /* PREFIX_VEX_0F41 */
4742 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4744 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4747 /* PREFIX_VEX_0F42 */
4749 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4751 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4754 /* PREFIX_VEX_0F44 */
4756 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4758 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4761 /* PREFIX_VEX_0F45 */
4763 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4765 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4768 /* PREFIX_VEX_0F46 */
4770 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4772 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4775 /* PREFIX_VEX_0F47 */
4777 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4779 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4782 /* PREFIX_VEX_0F4A */
4784 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4786 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4789 /* PREFIX_VEX_0F4B */
4791 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4793 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4796 /* PREFIX_VEX_0F51 */
4798 { "vsqrtps", { XM, EXx }, 0 },
4799 { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
4800 { "vsqrtpd", { XM, EXx }, 0 },
4801 { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 },
4804 /* PREFIX_VEX_0F52 */
4806 { "vrsqrtps", { XM, EXx }, 0 },
4807 { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
4810 /* PREFIX_VEX_0F53 */
4812 { "vrcpps", { XM, EXx }, 0 },
4813 { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 },
4816 /* PREFIX_VEX_0F58 */
4818 { "vaddps", { XM, Vex, EXx }, 0 },
4819 { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 },
4820 { "vaddpd", { XM, Vex, EXx }, 0 },
4821 { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 },
4824 /* PREFIX_VEX_0F59 */
4826 { "vmulps", { XM, Vex, EXx }, 0 },
4827 { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 },
4828 { "vmulpd", { XM, Vex, EXx }, 0 },
4829 { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 },
4832 /* PREFIX_VEX_0F5A */
4834 { "vcvtps2pd", { XM, EXxmmq }, 0 },
4835 { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 },
4836 { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4837 { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 },
4840 /* PREFIX_VEX_0F5B */
4842 { "vcvtdq2ps", { XM, EXx }, 0 },
4843 { "vcvttps2dq", { XM, EXx }, 0 },
4844 { "vcvtps2dq", { XM, EXx }, 0 },
4847 /* PREFIX_VEX_0F5C */
4849 { "vsubps", { XM, Vex, EXx }, 0 },
4850 { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 },
4851 { "vsubpd", { XM, Vex, EXx }, 0 },
4852 { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 },
4855 /* PREFIX_VEX_0F5D */
4857 { "vminps", { XM, Vex, EXx }, 0 },
4858 { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 },
4859 { "vminpd", { XM, Vex, EXx }, 0 },
4860 { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 },
4863 /* PREFIX_VEX_0F5E */
4865 { "vdivps", { XM, Vex, EXx }, 0 },
4866 { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 },
4867 { "vdivpd", { XM, Vex, EXx }, 0 },
4868 { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 },
4871 /* PREFIX_VEX_0F5F */
4873 { "vmaxps", { XM, Vex, EXx }, 0 },
4874 { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 },
4875 { "vmaxpd", { XM, Vex, EXx }, 0 },
4876 { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 },
4879 /* PREFIX_VEX_0F60 */
4883 { "vpunpcklbw", { XM, Vex, EXx }, 0 },
4886 /* PREFIX_VEX_0F61 */
4890 { "vpunpcklwd", { XM, Vex, EXx }, 0 },
4893 /* PREFIX_VEX_0F62 */
4897 { "vpunpckldq", { XM, Vex, EXx }, 0 },
4900 /* PREFIX_VEX_0F63 */
4904 { "vpacksswb", { XM, Vex, EXx }, 0 },
4907 /* PREFIX_VEX_0F64 */
4911 { "vpcmpgtb", { XM, Vex, EXx }, 0 },
4914 /* PREFIX_VEX_0F65 */
4918 { "vpcmpgtw", { XM, Vex, EXx }, 0 },
4921 /* PREFIX_VEX_0F66 */
4925 { "vpcmpgtd", { XM, Vex, EXx }, 0 },
4928 /* PREFIX_VEX_0F67 */
4932 { "vpackuswb", { XM, Vex, EXx }, 0 },
4935 /* PREFIX_VEX_0F68 */
4939 { "vpunpckhbw", { XM, Vex, EXx }, 0 },
4942 /* PREFIX_VEX_0F69 */
4946 { "vpunpckhwd", { XM, Vex, EXx }, 0 },
4949 /* PREFIX_VEX_0F6A */
4953 { "vpunpckhdq", { XM, Vex, EXx }, 0 },
4956 /* PREFIX_VEX_0F6B */
4960 { "vpackssdw", { XM, Vex, EXx }, 0 },
4963 /* PREFIX_VEX_0F6C */
4967 { "vpunpcklqdq", { XM, Vex, EXx }, 0 },
4970 /* PREFIX_VEX_0F6D */
4974 { "vpunpckhqdq", { XM, Vex, EXx }, 0 },
4977 /* PREFIX_VEX_0F6E */
4981 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4984 /* PREFIX_VEX_0F6F */
4987 { "vmovdqu", { XM, EXx }, 0 },
4988 { "vmovdqa", { XM, EXx }, 0 },
4991 /* PREFIX_VEX_0F70 */
4994 { "vpshufhw", { XM, EXx, Ib }, 0 },
4995 { "vpshufd", { XM, EXx, Ib }, 0 },
4996 { "vpshuflw", { XM, EXx, Ib }, 0 },
4999 /* PREFIX_VEX_0F71_REG_2 */
5003 { "vpsrlw", { Vex, XS, Ib }, 0 },
5006 /* PREFIX_VEX_0F71_REG_4 */
5010 { "vpsraw", { Vex, XS, Ib }, 0 },
5013 /* PREFIX_VEX_0F71_REG_6 */
5017 { "vpsllw", { Vex, XS, Ib }, 0 },
5020 /* PREFIX_VEX_0F72_REG_2 */
5024 { "vpsrld", { Vex, XS, Ib }, 0 },
5027 /* PREFIX_VEX_0F72_REG_4 */
5031 { "vpsrad", { Vex, XS, Ib }, 0 },
5034 /* PREFIX_VEX_0F72_REG_6 */
5038 { "vpslld", { Vex, XS, Ib }, 0 },
5041 /* PREFIX_VEX_0F73_REG_2 */
5045 { "vpsrlq", { Vex, XS, Ib }, 0 },
5048 /* PREFIX_VEX_0F73_REG_3 */
5052 { "vpsrldq", { Vex, XS, Ib }, 0 },
5055 /* PREFIX_VEX_0F73_REG_6 */
5059 { "vpsllq", { Vex, XS, Ib }, 0 },
5062 /* PREFIX_VEX_0F73_REG_7 */
5066 { "vpslldq", { Vex, XS, Ib }, 0 },
5069 /* PREFIX_VEX_0F74 */
5073 { "vpcmpeqb", { XM, Vex, EXx }, 0 },
5076 /* PREFIX_VEX_0F75 */
5080 { "vpcmpeqw", { XM, Vex, EXx }, 0 },
5083 /* PREFIX_VEX_0F76 */
5087 { "vpcmpeqd", { XM, Vex, EXx }, 0 },
5090 /* PREFIX_VEX_0F77 */
5092 { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
5095 /* PREFIX_VEX_0F7C */
5099 { "vhaddpd", { XM, Vex, EXx }, 0 },
5100 { "vhaddps", { XM, Vex, EXx }, 0 },
5103 /* PREFIX_VEX_0F7D */
5107 { "vhsubpd", { XM, Vex, EXx }, 0 },
5108 { "vhsubps", { XM, Vex, EXx }, 0 },
5111 /* PREFIX_VEX_0F7E */
5114 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5115 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5118 /* PREFIX_VEX_0F7F */
5121 { "vmovdqu", { EXxS, XM }, 0 },
5122 { "vmovdqa", { EXxS, XM }, 0 },
5125 /* PREFIX_VEX_0F90 */
5127 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5129 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5132 /* PREFIX_VEX_0F91 */
5134 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5136 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5139 /* PREFIX_VEX_0F92 */
5141 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5143 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5144 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5147 /* PREFIX_VEX_0F93 */
5149 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5151 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5152 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5155 /* PREFIX_VEX_0F98 */
5157 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5159 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5162 /* PREFIX_VEX_0F99 */
5164 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5166 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5169 /* PREFIX_VEX_0FC2 */
5171 { "vcmpps", { XM, Vex, EXx, VCMP }, 0 },
5172 { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
5173 { "vcmppd", { XM, Vex, EXx, VCMP }, 0 },
5174 { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
5177 /* PREFIX_VEX_0FC4 */
5181 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5184 /* PREFIX_VEX_0FC5 */
5188 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5191 /* PREFIX_VEX_0FD0 */
5195 { "vaddsubpd", { XM, Vex, EXx }, 0 },
5196 { "vaddsubps", { XM, Vex, EXx }, 0 },
5199 /* PREFIX_VEX_0FD1 */
5203 { "vpsrlw", { XM, Vex, EXxmm }, 0 },
5206 /* PREFIX_VEX_0FD2 */
5210 { "vpsrld", { XM, Vex, EXxmm }, 0 },
5213 /* PREFIX_VEX_0FD3 */
5217 { "vpsrlq", { XM, Vex, EXxmm }, 0 },
5220 /* PREFIX_VEX_0FD4 */
5224 { "vpaddq", { XM, Vex, EXx }, 0 },
5227 /* PREFIX_VEX_0FD5 */
5231 { "vpmullw", { XM, Vex, EXx }, 0 },
5234 /* PREFIX_VEX_0FD6 */
5238 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5241 /* PREFIX_VEX_0FD7 */
5245 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5248 /* PREFIX_VEX_0FD8 */
5252 { "vpsubusb", { XM, Vex, EXx }, 0 },
5255 /* PREFIX_VEX_0FD9 */
5259 { "vpsubusw", { XM, Vex, EXx }, 0 },
5262 /* PREFIX_VEX_0FDA */
5266 { "vpminub", { XM, Vex, EXx }, 0 },
5269 /* PREFIX_VEX_0FDB */
5273 { "vpand", { XM, Vex, EXx }, 0 },
5276 /* PREFIX_VEX_0FDC */
5280 { "vpaddusb", { XM, Vex, EXx }, 0 },
5283 /* PREFIX_VEX_0FDD */
5287 { "vpaddusw", { XM, Vex, EXx }, 0 },
5290 /* PREFIX_VEX_0FDE */
5294 { "vpmaxub", { XM, Vex, EXx }, 0 },
5297 /* PREFIX_VEX_0FDF */
5301 { "vpandn", { XM, Vex, EXx }, 0 },
5304 /* PREFIX_VEX_0FE0 */
5308 { "vpavgb", { XM, Vex, EXx }, 0 },
5311 /* PREFIX_VEX_0FE1 */
5315 { "vpsraw", { XM, Vex, EXxmm }, 0 },
5318 /* PREFIX_VEX_0FE2 */
5322 { "vpsrad", { XM, Vex, EXxmm }, 0 },
5325 /* PREFIX_VEX_0FE3 */
5329 { "vpavgw", { XM, Vex, EXx }, 0 },
5332 /* PREFIX_VEX_0FE4 */
5336 { "vpmulhuw", { XM, Vex, EXx }, 0 },
5339 /* PREFIX_VEX_0FE5 */
5343 { "vpmulhw", { XM, Vex, EXx }, 0 },
5346 /* PREFIX_VEX_0FE6 */
5349 { "vcvtdq2pd", { XM, EXxmmq }, 0 },
5350 { "vcvttpd2dq%XY", { XMM, EXx }, 0 },
5351 { "vcvtpd2dq%XY", { XMM, EXx }, 0 },
5354 /* PREFIX_VEX_0FE7 */
5358 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5361 /* PREFIX_VEX_0FE8 */
5365 { "vpsubsb", { XM, Vex, EXx }, 0 },
5368 /* PREFIX_VEX_0FE9 */
5372 { "vpsubsw", { XM, Vex, EXx }, 0 },
5375 /* PREFIX_VEX_0FEA */
5379 { "vpminsw", { XM, Vex, EXx }, 0 },
5382 /* PREFIX_VEX_0FEB */
5386 { "vpor", { XM, Vex, EXx }, 0 },
5389 /* PREFIX_VEX_0FEC */
5393 { "vpaddsb", { XM, Vex, EXx }, 0 },
5396 /* PREFIX_VEX_0FED */
5400 { "vpaddsw", { XM, Vex, EXx }, 0 },
5403 /* PREFIX_VEX_0FEE */
5407 { "vpmaxsw", { XM, Vex, EXx }, 0 },
5410 /* PREFIX_VEX_0FEF */
5414 { "vpxor", { XM, Vex, EXx }, 0 },
5417 /* PREFIX_VEX_0FF0 */
5422 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5425 /* PREFIX_VEX_0FF1 */
5429 { "vpsllw", { XM, Vex, EXxmm }, 0 },
5432 /* PREFIX_VEX_0FF2 */
5436 { "vpslld", { XM, Vex, EXxmm }, 0 },
5439 /* PREFIX_VEX_0FF3 */
5443 { "vpsllq", { XM, Vex, EXxmm }, 0 },
5446 /* PREFIX_VEX_0FF4 */
5450 { "vpmuludq", { XM, Vex, EXx }, 0 },
5453 /* PREFIX_VEX_0FF5 */
5457 { "vpmaddwd", { XM, Vex, EXx }, 0 },
5460 /* PREFIX_VEX_0FF6 */
5464 { "vpsadbw", { XM, Vex, EXx }, 0 },
5467 /* PREFIX_VEX_0FF7 */
5471 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5474 /* PREFIX_VEX_0FF8 */
5478 { "vpsubb", { XM, Vex, EXx }, 0 },
5481 /* PREFIX_VEX_0FF9 */
5485 { "vpsubw", { XM, Vex, EXx }, 0 },
5488 /* PREFIX_VEX_0FFA */
5492 { "vpsubd", { XM, Vex, EXx }, 0 },
5495 /* PREFIX_VEX_0FFB */
5499 { "vpsubq", { XM, Vex, EXx }, 0 },
5502 /* PREFIX_VEX_0FFC */
5506 { "vpaddb", { XM, Vex, EXx }, 0 },
5509 /* PREFIX_VEX_0FFD */
5513 { "vpaddw", { XM, Vex, EXx }, 0 },
5516 /* PREFIX_VEX_0FFE */
5520 { "vpaddd", { XM, Vex, EXx }, 0 },
5523 /* PREFIX_VEX_0F3800 */
5527 { "vpshufb", { XM, Vex, EXx }, 0 },
5530 /* PREFIX_VEX_0F3801 */
5534 { "vphaddw", { XM, Vex, EXx }, 0 },
5537 /* PREFIX_VEX_0F3802 */
5541 { "vphaddd", { XM, Vex, EXx }, 0 },
5544 /* PREFIX_VEX_0F3803 */
5548 { "vphaddsw", { XM, Vex, EXx }, 0 },
5551 /* PREFIX_VEX_0F3804 */
5555 { "vpmaddubsw", { XM, Vex, EXx }, 0 },
5558 /* PREFIX_VEX_0F3805 */
5562 { "vphsubw", { XM, Vex, EXx }, 0 },
5565 /* PREFIX_VEX_0F3806 */
5569 { "vphsubd", { XM, Vex, EXx }, 0 },
5572 /* PREFIX_VEX_0F3807 */
5576 { "vphsubsw", { XM, Vex, EXx }, 0 },
5579 /* PREFIX_VEX_0F3808 */
5583 { "vpsignb", { XM, Vex, EXx }, 0 },
5586 /* PREFIX_VEX_0F3809 */
5590 { "vpsignw", { XM, Vex, EXx }, 0 },
5593 /* PREFIX_VEX_0F380A */
5597 { "vpsignd", { XM, Vex, EXx }, 0 },
5600 /* PREFIX_VEX_0F380B */
5604 { "vpmulhrsw", { XM, Vex, EXx }, 0 },
5607 /* PREFIX_VEX_0F380C */
5611 { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5614 /* PREFIX_VEX_0F380D */
5618 { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5621 /* PREFIX_VEX_0F380E */
5625 { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5628 /* PREFIX_VEX_0F380F */
5632 { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5635 /* PREFIX_VEX_0F3813 */
5639 { "vcvtph2ps", { XM, EXxmmq }, 0 },
5642 /* PREFIX_VEX_0F3816 */
5646 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5649 /* PREFIX_VEX_0F3817 */
5653 { "vptest", { XM, EXx }, 0 },
5656 /* PREFIX_VEX_0F3818 */
5660 { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5663 /* PREFIX_VEX_0F3819 */
5667 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5670 /* PREFIX_VEX_0F381A */
5674 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5677 /* PREFIX_VEX_0F381C */
5681 { "vpabsb", { XM, EXx }, 0 },
5684 /* PREFIX_VEX_0F381D */
5688 { "vpabsw", { XM, EXx }, 0 },
5691 /* PREFIX_VEX_0F381E */
5695 { "vpabsd", { XM, EXx }, 0 },
5698 /* PREFIX_VEX_0F3820 */
5702 { "vpmovsxbw", { XM, EXxmmq }, 0 },
5705 /* PREFIX_VEX_0F3821 */
5709 { "vpmovsxbd", { XM, EXxmmqd }, 0 },
5712 /* PREFIX_VEX_0F3822 */
5716 { "vpmovsxbq", { XM, EXxmmdw }, 0 },
5719 /* PREFIX_VEX_0F3823 */
5723 { "vpmovsxwd", { XM, EXxmmq }, 0 },
5726 /* PREFIX_VEX_0F3824 */
5730 { "vpmovsxwq", { XM, EXxmmqd }, 0 },
5733 /* PREFIX_VEX_0F3825 */
5737 { "vpmovsxdq", { XM, EXxmmq }, 0 },
5740 /* PREFIX_VEX_0F3828 */
5744 { "vpmuldq", { XM, Vex, EXx }, 0 },
5747 /* PREFIX_VEX_0F3829 */
5751 { "vpcmpeqq", { XM, Vex, EXx }, 0 },
5754 /* PREFIX_VEX_0F382A */
5758 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5761 /* PREFIX_VEX_0F382B */
5765 { "vpackusdw", { XM, Vex, EXx }, 0 },
5768 /* PREFIX_VEX_0F382C */
5772 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5775 /* PREFIX_VEX_0F382D */
5779 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5782 /* PREFIX_VEX_0F382E */
5786 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5789 /* PREFIX_VEX_0F382F */
5793 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5796 /* PREFIX_VEX_0F3830 */
5800 { "vpmovzxbw", { XM, EXxmmq }, 0 },
5803 /* PREFIX_VEX_0F3831 */
5807 { "vpmovzxbd", { XM, EXxmmqd }, 0 },
5810 /* PREFIX_VEX_0F3832 */
5814 { "vpmovzxbq", { XM, EXxmmdw }, 0 },
5817 /* PREFIX_VEX_0F3833 */
5821 { "vpmovzxwd", { XM, EXxmmq }, 0 },
5824 /* PREFIX_VEX_0F3834 */
5828 { "vpmovzxwq", { XM, EXxmmqd }, 0 },
5831 /* PREFIX_VEX_0F3835 */
5835 { "vpmovzxdq", { XM, EXxmmq }, 0 },
5838 /* PREFIX_VEX_0F3836 */
5842 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5845 /* PREFIX_VEX_0F3837 */
5849 { "vpcmpgtq", { XM, Vex, EXx }, 0 },
5852 /* PREFIX_VEX_0F3838 */
5856 { "vpminsb", { XM, Vex, EXx }, 0 },
5859 /* PREFIX_VEX_0F3839 */
5863 { "vpminsd", { XM, Vex, EXx }, 0 },
5866 /* PREFIX_VEX_0F383A */
5870 { "vpminuw", { XM, Vex, EXx }, 0 },
5873 /* PREFIX_VEX_0F383B */
5877 { "vpminud", { XM, Vex, EXx }, 0 },
5880 /* PREFIX_VEX_0F383C */
5884 { "vpmaxsb", { XM, Vex, EXx }, 0 },
5887 /* PREFIX_VEX_0F383D */
5891 { "vpmaxsd", { XM, Vex, EXx }, 0 },
5894 /* PREFIX_VEX_0F383E */
5898 { "vpmaxuw", { XM, Vex, EXx }, 0 },
5901 /* PREFIX_VEX_0F383F */
5905 { "vpmaxud", { XM, Vex, EXx }, 0 },
5908 /* PREFIX_VEX_0F3840 */
5912 { "vpmulld", { XM, Vex, EXx }, 0 },
5915 /* PREFIX_VEX_0F3841 */
5919 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5922 /* PREFIX_VEX_0F3845 */
5926 { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5929 /* PREFIX_VEX_0F3846 */
5933 { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5936 /* PREFIX_VEX_0F3847 */
5940 { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5943 /* PREFIX_VEX_0F3858 */
5947 { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5950 /* PREFIX_VEX_0F3859 */
5954 { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5957 /* PREFIX_VEX_0F385A */
5961 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5964 /* PREFIX_VEX_0F3878 */
5968 { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5971 /* PREFIX_VEX_0F3879 */
5975 { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5978 /* PREFIX_VEX_0F388C */
5982 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5985 /* PREFIX_VEX_0F388E */
5989 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5992 /* PREFIX_VEX_0F3890 */
5996 { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5999 /* PREFIX_VEX_0F3891 */
6003 { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6006 /* PREFIX_VEX_0F3892 */
6010 { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6013 /* PREFIX_VEX_0F3893 */
6017 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6020 /* PREFIX_VEX_0F3896 */
6024 { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6027 /* PREFIX_VEX_0F3897 */
6031 { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6034 /* PREFIX_VEX_0F3898 */
6038 { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6041 /* PREFIX_VEX_0F3899 */
6045 { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6048 /* PREFIX_VEX_0F389A */
6052 { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6055 /* PREFIX_VEX_0F389B */
6059 { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6062 /* PREFIX_VEX_0F389C */
6066 { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6069 /* PREFIX_VEX_0F389D */
6073 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6076 /* PREFIX_VEX_0F389E */
6080 { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6083 /* PREFIX_VEX_0F389F */
6087 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6090 /* PREFIX_VEX_0F38A6 */
6094 { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6098 /* PREFIX_VEX_0F38A7 */
6102 { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6105 /* PREFIX_VEX_0F38A8 */
6109 { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6112 /* PREFIX_VEX_0F38A9 */
6116 { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6119 /* PREFIX_VEX_0F38AA */
6123 { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6126 /* PREFIX_VEX_0F38AB */
6130 { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6133 /* PREFIX_VEX_0F38AC */
6137 { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6140 /* PREFIX_VEX_0F38AD */
6144 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6147 /* PREFIX_VEX_0F38AE */
6151 { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6154 /* PREFIX_VEX_0F38AF */
6158 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6161 /* PREFIX_VEX_0F38B6 */
6165 { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6168 /* PREFIX_VEX_0F38B7 */
6172 { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6175 /* PREFIX_VEX_0F38B8 */
6179 { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6182 /* PREFIX_VEX_0F38B9 */
6186 { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6189 /* PREFIX_VEX_0F38BA */
6193 { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6196 /* PREFIX_VEX_0F38BB */
6200 { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6203 /* PREFIX_VEX_0F38BC */
6207 { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6210 /* PREFIX_VEX_0F38BD */
6214 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6217 /* PREFIX_VEX_0F38BE */
6221 { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6224 /* PREFIX_VEX_0F38BF */
6228 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6231 /* PREFIX_VEX_0F38CF */
6235 { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6238 /* PREFIX_VEX_0F38DB */
6242 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6245 /* PREFIX_VEX_0F38DC */
6249 { "vaesenc", { XM, Vex, EXx }, 0 },
6252 /* PREFIX_VEX_0F38DD */
6256 { "vaesenclast", { XM, Vex, EXx }, 0 },
6259 /* PREFIX_VEX_0F38DE */
6263 { "vaesdec", { XM, Vex, EXx }, 0 },
6266 /* PREFIX_VEX_0F38DF */
6270 { "vaesdeclast", { XM, Vex, EXx }, 0 },
6273 /* PREFIX_VEX_0F38F2 */
6275 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6278 /* PREFIX_VEX_0F38F3_REG_1 */
6280 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6283 /* PREFIX_VEX_0F38F3_REG_2 */
6285 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6288 /* PREFIX_VEX_0F38F3_REG_3 */
6290 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6293 /* PREFIX_VEX_0F38F5 */
6295 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6296 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6298 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6301 /* PREFIX_VEX_0F38F6 */
6306 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6309 /* PREFIX_VEX_0F38F7 */
6311 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6312 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6313 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6314 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6317 /* PREFIX_VEX_0F3A00 */
6321 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6324 /* PREFIX_VEX_0F3A01 */
6328 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6331 /* PREFIX_VEX_0F3A02 */
6335 { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6338 /* PREFIX_VEX_0F3A04 */
6342 { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6345 /* PREFIX_VEX_0F3A05 */
6349 { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6352 /* PREFIX_VEX_0F3A06 */
6356 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6359 /* PREFIX_VEX_0F3A08 */
6363 { "vroundps", { XM, EXx, Ib }, 0 },
6366 /* PREFIX_VEX_0F3A09 */
6370 { "vroundpd", { XM, EXx, Ib }, 0 },
6373 /* PREFIX_VEX_0F3A0A */
6377 { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
6380 /* PREFIX_VEX_0F3A0B */
6384 { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
6387 /* PREFIX_VEX_0F3A0C */
6391 { "vblendps", { XM, Vex, EXx, Ib }, 0 },
6394 /* PREFIX_VEX_0F3A0D */
6398 { "vblendpd", { XM, Vex, EXx, Ib }, 0 },
6401 /* PREFIX_VEX_0F3A0E */
6405 { "vpblendw", { XM, Vex, EXx, Ib }, 0 },
6408 /* PREFIX_VEX_0F3A0F */
6412 { "vpalignr", { XM, Vex, EXx, Ib }, 0 },
6415 /* PREFIX_VEX_0F3A14 */
6419 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6422 /* PREFIX_VEX_0F3A15 */
6426 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6429 /* PREFIX_VEX_0F3A16 */
6433 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6436 /* PREFIX_VEX_0F3A17 */
6440 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6443 /* PREFIX_VEX_0F3A18 */
6447 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6450 /* PREFIX_VEX_0F3A19 */
6454 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6457 /* PREFIX_VEX_0F3A1D */
6461 { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6464 /* PREFIX_VEX_0F3A20 */
6468 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6471 /* PREFIX_VEX_0F3A21 */
6475 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6478 /* PREFIX_VEX_0F3A22 */
6482 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6485 /* PREFIX_VEX_0F3A30 */
6489 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6492 /* PREFIX_VEX_0F3A31 */
6496 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6499 /* PREFIX_VEX_0F3A32 */
6503 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6506 /* PREFIX_VEX_0F3A33 */
6510 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6513 /* PREFIX_VEX_0F3A38 */
6517 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6520 /* PREFIX_VEX_0F3A39 */
6524 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6527 /* PREFIX_VEX_0F3A40 */
6531 { "vdpps", { XM, Vex, EXx, Ib }, 0 },
6534 /* PREFIX_VEX_0F3A41 */
6538 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6541 /* PREFIX_VEX_0F3A42 */
6545 { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 },
6548 /* PREFIX_VEX_0F3A44 */
6552 { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, 0 },
6555 /* PREFIX_VEX_0F3A46 */
6559 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6562 /* PREFIX_VEX_0F3A48 */
6566 { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6569 /* PREFIX_VEX_0F3A49 */
6573 { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6576 /* PREFIX_VEX_0F3A4A */
6580 { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6583 /* PREFIX_VEX_0F3A4B */
6587 { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6590 /* PREFIX_VEX_0F3A4C */
6594 { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6597 /* PREFIX_VEX_0F3A5C */
6601 { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6604 /* PREFIX_VEX_0F3A5D */
6608 { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6611 /* PREFIX_VEX_0F3A5E */
6615 { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6618 /* PREFIX_VEX_0F3A5F */
6622 { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6625 /* PREFIX_VEX_0F3A60 */
6629 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6633 /* PREFIX_VEX_0F3A61 */
6637 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6640 /* PREFIX_VEX_0F3A62 */
6644 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6647 /* PREFIX_VEX_0F3A63 */
6651 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6654 /* PREFIX_VEX_0F3A68 */
6658 { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6661 /* PREFIX_VEX_0F3A69 */
6665 { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6668 /* PREFIX_VEX_0F3A6A */
6672 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6675 /* PREFIX_VEX_0F3A6B */
6679 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6682 /* PREFIX_VEX_0F3A6C */
6686 { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6689 /* PREFIX_VEX_0F3A6D */
6693 { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6696 /* PREFIX_VEX_0F3A6E */
6700 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6703 /* PREFIX_VEX_0F3A6F */
6707 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6710 /* PREFIX_VEX_0F3A78 */
6714 { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6717 /* PREFIX_VEX_0F3A79 */
6721 { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6724 /* PREFIX_VEX_0F3A7A */
6728 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6731 /* PREFIX_VEX_0F3A7B */
6735 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6738 /* PREFIX_VEX_0F3A7C */
6742 { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6746 /* PREFIX_VEX_0F3A7D */
6750 { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6753 /* PREFIX_VEX_0F3A7E */
6757 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6760 /* PREFIX_VEX_0F3A7F */
6764 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6767 /* PREFIX_VEX_0F3ACE */
6771 { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6774 /* PREFIX_VEX_0F3ACF */
6778 { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6781 /* PREFIX_VEX_0F3ADF */
6785 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6788 /* PREFIX_VEX_0F3AF0 */
6793 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6796 #define NEED_PREFIX_TABLE
6797 #include "i386-dis-evex.h"
6798 #undef NEED_PREFIX_TABLE
6801 static const struct dis386 x86_64_table[][2] = {
6804 { "pushP", { es }, 0 },
6809 { "popP", { es }, 0 },
6814 { "pushP", { cs }, 0 },
6819 { "pushP", { ss }, 0 },
6824 { "popP", { ss }, 0 },
6829 { "pushP", { ds }, 0 },
6834 { "popP", { ds }, 0 },
6839 { "daa", { XX }, 0 },
6844 { "das", { XX }, 0 },
6849 { "aaa", { XX }, 0 },
6854 { "aas", { XX }, 0 },
6859 { "pushaP", { XX }, 0 },
6864 { "popaP", { XX }, 0 },
6869 { MOD_TABLE (MOD_62_32BIT) },
6870 { EVEX_TABLE (EVEX_0F) },
6875 { "arpl", { Ew, Gw }, 0 },
6876 { "movs{lq|xd}", { Gv, Ed }, 0 },
6881 { "ins{R|}", { Yzr, indirDX }, 0 },
6882 { "ins{G|}", { Yzr, indirDX }, 0 },
6887 { "outs{R|}", { indirDXr, Xz }, 0 },
6888 { "outs{G|}", { indirDXr, Xz }, 0 },
6893 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
6894 { REG_TABLE (REG_80) },
6899 { "Jcall{T|}", { Ap }, 0 },
6904 { MOD_TABLE (MOD_C4_32BIT) },
6905 { VEX_C4_TABLE (VEX_0F) },
6910 { MOD_TABLE (MOD_C5_32BIT) },
6911 { VEX_C5_TABLE (VEX_0F) },
6916 { "into", { XX }, 0 },
6921 { "aam", { Ib }, 0 },
6926 { "aad", { Ib }, 0 },
6931 { "callP", { Jv, BND }, 0 },
6932 { "call@", { Jv, BND }, 0 }
6937 { "jmpP", { Jv, BND }, 0 },
6938 { "jmp@", { Jv, BND }, 0 }
6943 { "Jjmp{T|}", { Ap }, 0 },
6946 /* X86_64_0F01_REG_0 */
6948 { "sgdt{Q|IQ}", { M }, 0 },
6949 { "sgdt", { M }, 0 },
6952 /* X86_64_0F01_REG_1 */
6954 { "sidt{Q|IQ}", { M }, 0 },
6955 { "sidt", { M }, 0 },
6958 /* X86_64_0F01_REG_2 */
6960 { "lgdt{Q|Q}", { M }, 0 },
6961 { "lgdt", { M }, 0 },
6964 /* X86_64_0F01_REG_3 */
6966 { "lidt{Q|Q}", { M }, 0 },
6967 { "lidt", { M }, 0 },
6971 static const struct dis386 three_byte_table[][256] = {
6973 /* THREE_BYTE_0F38 */
6976 { "pshufb", { MX, EM }, PREFIX_OPCODE },
6977 { "phaddw", { MX, EM }, PREFIX_OPCODE },
6978 { "phaddd", { MX, EM }, PREFIX_OPCODE },
6979 { "phaddsw", { MX, EM }, PREFIX_OPCODE },
6980 { "pmaddubsw", { MX, EM }, PREFIX_OPCODE },
6981 { "phsubw", { MX, EM }, PREFIX_OPCODE },
6982 { "phsubd", { MX, EM }, PREFIX_OPCODE },
6983 { "phsubsw", { MX, EM }, PREFIX_OPCODE },
6985 { "psignb", { MX, EM }, PREFIX_OPCODE },
6986 { "psignw", { MX, EM }, PREFIX_OPCODE },
6987 { "psignd", { MX, EM }, PREFIX_OPCODE },
6988 { "pmulhrsw", { MX, EM }, PREFIX_OPCODE },
6994 { PREFIX_TABLE (PREFIX_0F3810) },
6998 { PREFIX_TABLE (PREFIX_0F3814) },
6999 { PREFIX_TABLE (PREFIX_0F3815) },
7001 { PREFIX_TABLE (PREFIX_0F3817) },
7007 { "pabsb", { MX, EM }, PREFIX_OPCODE },
7008 { "pabsw", { MX, EM }, PREFIX_OPCODE },
7009 { "pabsd", { MX, EM }, PREFIX_OPCODE },
7012 { PREFIX_TABLE (PREFIX_0F3820) },
7013 { PREFIX_TABLE (PREFIX_0F3821) },
7014 { PREFIX_TABLE (PREFIX_0F3822) },
7015 { PREFIX_TABLE (PREFIX_0F3823) },
7016 { PREFIX_TABLE (PREFIX_0F3824) },
7017 { PREFIX_TABLE (PREFIX_0F3825) },
7021 { PREFIX_TABLE (PREFIX_0F3828) },
7022 { PREFIX_TABLE (PREFIX_0F3829) },
7023 { PREFIX_TABLE (PREFIX_0F382A) },
7024 { PREFIX_TABLE (PREFIX_0F382B) },
7030 { PREFIX_TABLE (PREFIX_0F3830) },
7031 { PREFIX_TABLE (PREFIX_0F3831) },
7032 { PREFIX_TABLE (PREFIX_0F3832) },
7033 { PREFIX_TABLE (PREFIX_0F3833) },
7034 { PREFIX_TABLE (PREFIX_0F3834) },
7035 { PREFIX_TABLE (PREFIX_0F3835) },
7037 { PREFIX_TABLE (PREFIX_0F3837) },
7039 { PREFIX_TABLE (PREFIX_0F3838) },
7040 { PREFIX_TABLE (PREFIX_0F3839) },
7041 { PREFIX_TABLE (PREFIX_0F383A) },
7042 { PREFIX_TABLE (PREFIX_0F383B) },
7043 { PREFIX_TABLE (PREFIX_0F383C) },
7044 { PREFIX_TABLE (PREFIX_0F383D) },
7045 { PREFIX_TABLE (PREFIX_0F383E) },
7046 { PREFIX_TABLE (PREFIX_0F383F) },
7048 { PREFIX_TABLE (PREFIX_0F3840) },
7049 { PREFIX_TABLE (PREFIX_0F3841) },
7120 { PREFIX_TABLE (PREFIX_0F3880) },
7121 { PREFIX_TABLE (PREFIX_0F3881) },
7122 { PREFIX_TABLE (PREFIX_0F3882) },
7201 { PREFIX_TABLE (PREFIX_0F38C8) },
7202 { PREFIX_TABLE (PREFIX_0F38C9) },
7203 { PREFIX_TABLE (PREFIX_0F38CA) },
7204 { PREFIX_TABLE (PREFIX_0F38CB) },
7205 { PREFIX_TABLE (PREFIX_0F38CC) },
7206 { PREFIX_TABLE (PREFIX_0F38CD) },
7208 { PREFIX_TABLE (PREFIX_0F38CF) },
7222 { PREFIX_TABLE (PREFIX_0F38DB) },
7223 { PREFIX_TABLE (PREFIX_0F38DC) },
7224 { PREFIX_TABLE (PREFIX_0F38DD) },
7225 { PREFIX_TABLE (PREFIX_0F38DE) },
7226 { PREFIX_TABLE (PREFIX_0F38DF) },
7246 { PREFIX_TABLE (PREFIX_0F38F0) },
7247 { PREFIX_TABLE (PREFIX_0F38F1) },
7251 { PREFIX_TABLE (PREFIX_0F38F5) },
7252 { PREFIX_TABLE (PREFIX_0F38F6) },
7255 { PREFIX_TABLE (PREFIX_0F38F8) },
7256 { PREFIX_TABLE (PREFIX_0F38F9) },
7264 /* THREE_BYTE_0F3A */
7276 { PREFIX_TABLE (PREFIX_0F3A08) },
7277 { PREFIX_TABLE (PREFIX_0F3A09) },
7278 { PREFIX_TABLE (PREFIX_0F3A0A) },
7279 { PREFIX_TABLE (PREFIX_0F3A0B) },
7280 { PREFIX_TABLE (PREFIX_0F3A0C) },
7281 { PREFIX_TABLE (PREFIX_0F3A0D) },
7282 { PREFIX_TABLE (PREFIX_0F3A0E) },
7283 { "palignr", { MX, EM, Ib }, PREFIX_OPCODE },
7289 { PREFIX_TABLE (PREFIX_0F3A14) },
7290 { PREFIX_TABLE (PREFIX_0F3A15) },
7291 { PREFIX_TABLE (PREFIX_0F3A16) },
7292 { PREFIX_TABLE (PREFIX_0F3A17) },
7303 { PREFIX_TABLE (PREFIX_0F3A20) },
7304 { PREFIX_TABLE (PREFIX_0F3A21) },
7305 { PREFIX_TABLE (PREFIX_0F3A22) },
7339 { PREFIX_TABLE (PREFIX_0F3A40) },
7340 { PREFIX_TABLE (PREFIX_0F3A41) },
7341 { PREFIX_TABLE (PREFIX_0F3A42) },
7343 { PREFIX_TABLE (PREFIX_0F3A44) },
7375 { PREFIX_TABLE (PREFIX_0F3A60) },
7376 { PREFIX_TABLE (PREFIX_0F3A61) },
7377 { PREFIX_TABLE (PREFIX_0F3A62) },
7378 { PREFIX_TABLE (PREFIX_0F3A63) },
7496 { PREFIX_TABLE (PREFIX_0F3ACC) },
7498 { PREFIX_TABLE (PREFIX_0F3ACE) },
7499 { PREFIX_TABLE (PREFIX_0F3ACF) },
7517 { PREFIX_TABLE (PREFIX_0F3ADF) },
7557 static const struct dis386 xop_table[][256] = {
7710 { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7711 { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7712 { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7720 { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7721 { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7728 { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7729 { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7730 { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7738 { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7739 { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7743 { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7744 { "vpperm", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7747 { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7765 { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7777 { "vprotb", { XM, Vex_2src_1, Ib }, 0 },
7778 { "vprotw", { XM, Vex_2src_1, Ib }, 0 },
7779 { "vprotd", { XM, Vex_2src_1, Ib }, 0 },
7780 { "vprotq", { XM, Vex_2src_1, Ib }, 0 },
7790 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7791 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7792 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7793 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7826 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7827 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7828 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7829 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7853 { REG_TABLE (REG_XOP_TBM_01) },
7854 { REG_TABLE (REG_XOP_TBM_02) },
7872 { REG_TABLE (REG_XOP_LWPCB) },
7996 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7997 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7998 { "vfrczss", { XM, EXd }, 0 },
7999 { "vfrczsd", { XM, EXq }, 0 },
8014 { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8015 { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8016 { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8017 { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8018 { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8019 { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8020 { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8021 { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8023 { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8024 { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8025 { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8026 { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8069 { "vphaddbw", { XM, EXxmm }, 0 },
8070 { "vphaddbd", { XM, EXxmm }, 0 },
8071 { "vphaddbq", { XM, EXxmm }, 0 },
8074 { "vphaddwd", { XM, EXxmm }, 0 },
8075 { "vphaddwq", { XM, EXxmm }, 0 },
8080 { "vphadddq", { XM, EXxmm }, 0 },
8087 { "vphaddubw", { XM, EXxmm }, 0 },
8088 { "vphaddubd", { XM, EXxmm }, 0 },
8089 { "vphaddubq", { XM, EXxmm }, 0 },
8092 { "vphadduwd", { XM, EXxmm }, 0 },
8093 { "vphadduwq", { XM, EXxmm }, 0 },
8098 { "vphaddudq", { XM, EXxmm }, 0 },
8105 { "vphsubbw", { XM, EXxmm }, 0 },
8106 { "vphsubwd", { XM, EXxmm }, 0 },
8107 { "vphsubdq", { XM, EXxmm }, 0 },
8161 { "bextr", { Gv, Ev, Iq }, 0 },
8163 { REG_TABLE (REG_XOP_LWP) },
8433 static const struct dis386 vex_table[][256] = {
8455 { PREFIX_TABLE (PREFIX_VEX_0F10) },
8456 { PREFIX_TABLE (PREFIX_VEX_0F11) },
8457 { PREFIX_TABLE (PREFIX_VEX_0F12) },
8458 { MOD_TABLE (MOD_VEX_0F13) },
8459 { "vunpcklpX", { XM, Vex, EXx }, 0 },
8460 { "vunpckhpX", { XM, Vex, EXx }, 0 },
8461 { PREFIX_TABLE (PREFIX_VEX_0F16) },
8462 { MOD_TABLE (MOD_VEX_0F17) },
8482 { "vmovapX", { XM, EXx }, 0 },
8483 { "vmovapX", { EXxS, XM }, 0 },
8484 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8485 { MOD_TABLE (MOD_VEX_0F2B) },
8486 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8487 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8488 { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8489 { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8510 { PREFIX_TABLE (PREFIX_VEX_0F41) },
8511 { PREFIX_TABLE (PREFIX_VEX_0F42) },
8513 { PREFIX_TABLE (PREFIX_VEX_0F44) },
8514 { PREFIX_TABLE (PREFIX_VEX_0F45) },
8515 { PREFIX_TABLE (PREFIX_VEX_0F46) },
8516 { PREFIX_TABLE (PREFIX_VEX_0F47) },
8520 { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8521 { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8527 { MOD_TABLE (MOD_VEX_0F50) },
8528 { PREFIX_TABLE (PREFIX_VEX_0F51) },
8529 { PREFIX_TABLE (PREFIX_VEX_0F52) },
8530 { PREFIX_TABLE (PREFIX_VEX_0F53) },
8531 { "vandpX", { XM, Vex, EXx }, 0 },
8532 { "vandnpX", { XM, Vex, EXx }, 0 },
8533 { "vorpX", { XM, Vex, EXx }, 0 },
8534 { "vxorpX", { XM, Vex, EXx }, 0 },
8536 { PREFIX_TABLE (PREFIX_VEX_0F58) },
8537 { PREFIX_TABLE (PREFIX_VEX_0F59) },
8538 { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8539 { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8540 { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8541 { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8542 { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8543 { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8545 { PREFIX_TABLE (PREFIX_VEX_0F60) },
8546 { PREFIX_TABLE (PREFIX_VEX_0F61) },
8547 { PREFIX_TABLE (PREFIX_VEX_0F62) },
8548 { PREFIX_TABLE (PREFIX_VEX_0F63) },
8549 { PREFIX_TABLE (PREFIX_VEX_0F64) },
8550 { PREFIX_TABLE (PREFIX_VEX_0F65) },
8551 { PREFIX_TABLE (PREFIX_VEX_0F66) },
8552 { PREFIX_TABLE (PREFIX_VEX_0F67) },
8554 { PREFIX_TABLE (PREFIX_VEX_0F68) },
8555 { PREFIX_TABLE (PREFIX_VEX_0F69) },
8556 { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8557 { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8558 { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8559 { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8560 { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8561 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8563 { PREFIX_TABLE (PREFIX_VEX_0F70) },
8564 { REG_TABLE (REG_VEX_0F71) },
8565 { REG_TABLE (REG_VEX_0F72) },
8566 { REG_TABLE (REG_VEX_0F73) },
8567 { PREFIX_TABLE (PREFIX_VEX_0F74) },
8568 { PREFIX_TABLE (PREFIX_VEX_0F75) },
8569 { PREFIX_TABLE (PREFIX_VEX_0F76) },
8570 { PREFIX_TABLE (PREFIX_VEX_0F77) },
8576 { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8577 { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8578 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8579 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8599 { PREFIX_TABLE (PREFIX_VEX_0F90) },
8600 { PREFIX_TABLE (PREFIX_VEX_0F91) },
8601 { PREFIX_TABLE (PREFIX_VEX_0F92) },
8602 { PREFIX_TABLE (PREFIX_VEX_0F93) },
8608 { PREFIX_TABLE (PREFIX_VEX_0F98) },
8609 { PREFIX_TABLE (PREFIX_VEX_0F99) },
8632 { REG_TABLE (REG_VEX_0FAE) },
8655 { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8657 { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8658 { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8659 { "vshufpX", { XM, Vex, EXx, Ib }, 0 },
8671 { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8672 { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8673 { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8674 { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8675 { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8676 { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8677 { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8678 { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8680 { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8681 { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8682 { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8683 { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8684 { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8685 { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8686 { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8687 { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8689 { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8690 { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8691 { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8692 { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8693 { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8694 { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8695 { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8696 { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8698 { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8699 { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8700 { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8701 { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8702 { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8703 { PREFIX_TABLE (PREFIX_VEX_0FED) },
8704 { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8705 { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8707 { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8708 { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8709 { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8710 { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8711 { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8712 { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8713 { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8714 { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8716 { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8717 { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8718 { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8719 { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8720 { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8721 { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8722 { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8728 { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8729 { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8730 { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8731 { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8732 { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8733 { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8734 { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8735 { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8737 { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8738 { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8739 { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8740 { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8741 { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8742 { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8743 { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8744 { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8749 { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8752 { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8753 { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8755 { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8756 { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8757 { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8759 { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8760 { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8761 { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8764 { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8765 { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8766 { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8767 { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8768 { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8769 { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8773 { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8774 { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8775 { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8776 { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8777 { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8778 { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8779 { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8780 { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8782 { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8783 { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8784 { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8785 { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8786 { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8787 { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8788 { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8789 { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8791 { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8792 { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8793 { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8794 { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8795 { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8796 { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8797 { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8798 { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8800 { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8801 { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8805 { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8806 { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8807 { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8827 { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8828 { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8829 { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8863 { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8864 { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8885 { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8887 { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8890 { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8891 { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8892 { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8893 { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8896 { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8897 { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8899 { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8900 { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8901 { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8902 { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8903 { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8904 { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8905 { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8906 { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8914 { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8915 { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8917 { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8918 { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8919 { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8920 { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8921 { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8922 { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8923 { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8924 { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8932 { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8933 { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8935 { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8936 { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8937 { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8938 { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8939 { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8940 { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8941 { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8942 { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8960 { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8974 { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8975 { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8976 { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8977 { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8978 { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9000 { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9001 { REG_TABLE (REG_VEX_0F38F3) },
9003 { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9004 { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9005 { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9019 { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9020 { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9021 { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9023 { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9024 { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9025 { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9028 { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9029 { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9030 { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9031 { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9032 { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9033 { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9034 { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9035 { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9041 { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9042 { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9043 { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9044 { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9046 { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9047 { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9051 { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9055 { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9056 { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9057 { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9073 { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9074 { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9075 { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9076 { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9082 { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9083 { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9091 { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9092 { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9093 { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9095 { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9097 { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9100 { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9101 { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9102 { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9103 { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9104 { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9122 { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9123 { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9124 { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9125 { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9127 { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9128 { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9129 { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9130 { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9136 { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9137 { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9138 { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9139 { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9140 { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9141 { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9142 { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9143 { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9154 { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9155 { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9156 { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9157 { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9158 { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9159 { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9160 { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9161 { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9250 { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9251 { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9269 { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9289 { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9309 #define NEED_OPCODE_TABLE
9310 #include "i386-dis-evex.h"
9311 #undef NEED_OPCODE_TABLE
9312 static const struct dis386 vex_len_table[][2] = {
9313 /* VEX_LEN_0F12_P_0_M_0 */
9315 { "vmovlps", { XM, Vex128, EXq }, 0 },
9318 /* VEX_LEN_0F12_P_0_M_1 */
9320 { "vmovhlps", { XM, Vex128, EXq }, 0 },
9323 /* VEX_LEN_0F12_P_2 */
9325 { "vmovlpd", { XM, Vex128, EXq }, 0 },
9328 /* VEX_LEN_0F13_M_0 */
9330 { "vmovlpX", { EXq, XM }, 0 },
9333 /* VEX_LEN_0F16_P_0_M_0 */
9335 { "vmovhps", { XM, Vex128, EXq }, 0 },
9338 /* VEX_LEN_0F16_P_0_M_1 */
9340 { "vmovlhps", { XM, Vex128, EXq }, 0 },
9343 /* VEX_LEN_0F16_P_2 */
9345 { "vmovhpd", { XM, Vex128, EXq }, 0 },
9348 /* VEX_LEN_0F17_M_0 */
9350 { "vmovhpX", { EXq, XM }, 0 },
9353 /* VEX_LEN_0F2A_P_1 */
9355 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
9356 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
9359 /* VEX_LEN_0F2A_P_3 */
9361 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
9362 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
9365 /* VEX_LEN_0F2C_P_1 */
9367 { "vcvttss2si", { Gv, EXdScalar }, 0 },
9368 { "vcvttss2si", { Gv, EXdScalar }, 0 },
9371 /* VEX_LEN_0F2C_P_3 */
9373 { "vcvttsd2si", { Gv, EXqScalar }, 0 },
9374 { "vcvttsd2si", { Gv, EXqScalar }, 0 },
9377 /* VEX_LEN_0F2D_P_1 */
9379 { "vcvtss2si", { Gv, EXdScalar }, 0 },
9380 { "vcvtss2si", { Gv, EXdScalar }, 0 },
9383 /* VEX_LEN_0F2D_P_3 */
9385 { "vcvtsd2si", { Gv, EXqScalar }, 0 },
9386 { "vcvtsd2si", { Gv, EXqScalar }, 0 },
9389 /* VEX_LEN_0F41_P_0 */
9392 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9394 /* VEX_LEN_0F41_P_2 */
9397 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9399 /* VEX_LEN_0F42_P_0 */
9402 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9404 /* VEX_LEN_0F42_P_2 */
9407 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9409 /* VEX_LEN_0F44_P_0 */
9411 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9413 /* VEX_LEN_0F44_P_2 */
9415 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9417 /* VEX_LEN_0F45_P_0 */
9420 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9422 /* VEX_LEN_0F45_P_2 */
9425 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9427 /* VEX_LEN_0F46_P_0 */
9430 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9432 /* VEX_LEN_0F46_P_2 */
9435 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9437 /* VEX_LEN_0F47_P_0 */
9440 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9442 /* VEX_LEN_0F47_P_2 */
9445 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9447 /* VEX_LEN_0F4A_P_0 */
9450 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9452 /* VEX_LEN_0F4A_P_2 */
9455 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9457 /* VEX_LEN_0F4B_P_0 */
9460 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9462 /* VEX_LEN_0F4B_P_2 */
9465 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9468 /* VEX_LEN_0F6E_P_2 */
9470 { "vmovK", { XMScalar, Edq }, 0 },
9473 /* VEX_LEN_0F77_P_1 */
9475 { "vzeroupper", { XX }, 0 },
9476 { "vzeroall", { XX }, 0 },
9479 /* VEX_LEN_0F7E_P_1 */
9481 { "vmovq", { XMScalar, EXqScalar }, 0 },
9484 /* VEX_LEN_0F7E_P_2 */
9486 { "vmovK", { Edq, XMScalar }, 0 },
9489 /* VEX_LEN_0F90_P_0 */
9491 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9494 /* VEX_LEN_0F90_P_2 */
9496 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9499 /* VEX_LEN_0F91_P_0 */
9501 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9504 /* VEX_LEN_0F91_P_2 */
9506 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9509 /* VEX_LEN_0F92_P_0 */
9511 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9514 /* VEX_LEN_0F92_P_2 */
9516 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9519 /* VEX_LEN_0F92_P_3 */
9521 { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
9524 /* VEX_LEN_0F93_P_0 */
9526 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9529 /* VEX_LEN_0F93_P_2 */
9531 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9534 /* VEX_LEN_0F93_P_3 */
9536 { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
9539 /* VEX_LEN_0F98_P_0 */
9541 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9544 /* VEX_LEN_0F98_P_2 */
9546 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9549 /* VEX_LEN_0F99_P_0 */
9551 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9554 /* VEX_LEN_0F99_P_2 */
9556 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9559 /* VEX_LEN_0FAE_R_2_M_0 */
9561 { "vldmxcsr", { Md }, 0 },
9564 /* VEX_LEN_0FAE_R_3_M_0 */
9566 { "vstmxcsr", { Md }, 0 },
9569 /* VEX_LEN_0FC4_P_2 */
9571 { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 },
9574 /* VEX_LEN_0FC5_P_2 */
9576 { "vpextrw", { Gdq, XS, Ib }, 0 },
9579 /* VEX_LEN_0FD6_P_2 */
9581 { "vmovq", { EXqScalarS, XMScalar }, 0 },
9584 /* VEX_LEN_0FF7_P_2 */
9586 { "vmaskmovdqu", { XM, XS }, 0 },
9589 /* VEX_LEN_0F3816_P_2 */
9592 { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9595 /* VEX_LEN_0F3819_P_2 */
9598 { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9601 /* VEX_LEN_0F381A_P_2_M_0 */
9604 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9607 /* VEX_LEN_0F3836_P_2 */
9610 { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9613 /* VEX_LEN_0F3841_P_2 */
9615 { "vphminposuw", { XM, EXx }, 0 },
9618 /* VEX_LEN_0F385A_P_2_M_0 */
9621 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9624 /* VEX_LEN_0F38DB_P_2 */
9626 { "vaesimc", { XM, EXx }, 0 },
9629 /* VEX_LEN_0F38F2_P_0 */
9631 { "andnS", { Gdq, VexGdq, Edq }, 0 },
9634 /* VEX_LEN_0F38F3_R_1_P_0 */
9636 { "blsrS", { VexGdq, Edq }, 0 },
9639 /* VEX_LEN_0F38F3_R_2_P_0 */
9641 { "blsmskS", { VexGdq, Edq }, 0 },
9644 /* VEX_LEN_0F38F3_R_3_P_0 */
9646 { "blsiS", { VexGdq, Edq }, 0 },
9649 /* VEX_LEN_0F38F5_P_0 */
9651 { "bzhiS", { Gdq, Edq, VexGdq }, 0 },
9654 /* VEX_LEN_0F38F5_P_1 */
9656 { "pextS", { Gdq, VexGdq, Edq }, 0 },
9659 /* VEX_LEN_0F38F5_P_3 */
9661 { "pdepS", { Gdq, VexGdq, Edq }, 0 },
9664 /* VEX_LEN_0F38F6_P_3 */
9666 { "mulxS", { Gdq, VexGdq, Edq }, 0 },
9669 /* VEX_LEN_0F38F7_P_0 */
9671 { "bextrS", { Gdq, Edq, VexGdq }, 0 },
9674 /* VEX_LEN_0F38F7_P_1 */
9676 { "sarxS", { Gdq, Edq, VexGdq }, 0 },
9679 /* VEX_LEN_0F38F7_P_2 */
9681 { "shlxS", { Gdq, Edq, VexGdq }, 0 },
9684 /* VEX_LEN_0F38F7_P_3 */
9686 { "shrxS", { Gdq, Edq, VexGdq }, 0 },
9689 /* VEX_LEN_0F3A00_P_2 */
9692 { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9695 /* VEX_LEN_0F3A01_P_2 */
9698 { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9701 /* VEX_LEN_0F3A06_P_2 */
9704 { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9707 /* VEX_LEN_0F3A14_P_2 */
9709 { "vpextrb", { Edqb, XM, Ib }, 0 },
9712 /* VEX_LEN_0F3A15_P_2 */
9714 { "vpextrw", { Edqw, XM, Ib }, 0 },
9717 /* VEX_LEN_0F3A16_P_2 */
9719 { "vpextrK", { Edq, XM, Ib }, 0 },
9722 /* VEX_LEN_0F3A17_P_2 */
9724 { "vextractps", { Edqd, XM, Ib }, 0 },
9727 /* VEX_LEN_0F3A18_P_2 */
9730 { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9733 /* VEX_LEN_0F3A19_P_2 */
9736 { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9739 /* VEX_LEN_0F3A20_P_2 */
9741 { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 },
9744 /* VEX_LEN_0F3A21_P_2 */
9746 { "vinsertps", { XM, Vex128, EXd, Ib }, 0 },
9749 /* VEX_LEN_0F3A22_P_2 */
9751 { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 },
9754 /* VEX_LEN_0F3A30_P_2 */
9756 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9759 /* VEX_LEN_0F3A31_P_2 */
9761 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9764 /* VEX_LEN_0F3A32_P_2 */
9766 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9769 /* VEX_LEN_0F3A33_P_2 */
9771 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9774 /* VEX_LEN_0F3A38_P_2 */
9777 { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9780 /* VEX_LEN_0F3A39_P_2 */
9783 { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9786 /* VEX_LEN_0F3A41_P_2 */
9788 { "vdppd", { XM, Vex128, EXx, Ib }, 0 },
9791 /* VEX_LEN_0F3A46_P_2 */
9794 { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9797 /* VEX_LEN_0F3A60_P_2 */
9799 { "vpcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9802 /* VEX_LEN_0F3A61_P_2 */
9804 { "vpcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9807 /* VEX_LEN_0F3A62_P_2 */
9809 { "vpcmpistrm", { XM, EXx, Ib }, 0 },
9812 /* VEX_LEN_0F3A63_P_2 */
9814 { "vpcmpistri", { XM, EXx, Ib }, 0 },
9817 /* VEX_LEN_0F3A6A_P_2 */
9819 { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9822 /* VEX_LEN_0F3A6B_P_2 */
9824 { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9827 /* VEX_LEN_0F3A6E_P_2 */
9829 { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9832 /* VEX_LEN_0F3A6F_P_2 */
9834 { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9837 /* VEX_LEN_0F3A7A_P_2 */
9839 { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9842 /* VEX_LEN_0F3A7B_P_2 */
9844 { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9847 /* VEX_LEN_0F3A7E_P_2 */
9849 { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9852 /* VEX_LEN_0F3A7F_P_2 */
9854 { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9857 /* VEX_LEN_0F3ADF_P_2 */
9859 { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9862 /* VEX_LEN_0F3AF0_P_3 */
9864 { "rorxS", { Gdq, Edq, Ib }, 0 },
9867 /* VEX_LEN_0FXOP_08_CC */
9869 { "vpcomb", { XM, Vex128, EXx, VPCOM }, 0 },
9872 /* VEX_LEN_0FXOP_08_CD */
9874 { "vpcomw", { XM, Vex128, EXx, VPCOM }, 0 },
9877 /* VEX_LEN_0FXOP_08_CE */
9879 { "vpcomd", { XM, Vex128, EXx, VPCOM }, 0 },
9882 /* VEX_LEN_0FXOP_08_CF */
9884 { "vpcomq", { XM, Vex128, EXx, VPCOM }, 0 },
9887 /* VEX_LEN_0FXOP_08_EC */
9889 { "vpcomub", { XM, Vex128, EXx, VPCOM }, 0 },
9892 /* VEX_LEN_0FXOP_08_ED */
9894 { "vpcomuw", { XM, Vex128, EXx, VPCOM }, 0 },
9897 /* VEX_LEN_0FXOP_08_EE */
9899 { "vpcomud", { XM, Vex128, EXx, VPCOM }, 0 },
9902 /* VEX_LEN_0FXOP_08_EF */
9904 { "vpcomuq", { XM, Vex128, EXx, VPCOM }, 0 },
9907 /* VEX_LEN_0FXOP_09_80 */
9909 { "vfrczps", { XM, EXxmm }, 0 },
9910 { "vfrczps", { XM, EXymmq }, 0 },
9913 /* VEX_LEN_0FXOP_09_81 */
9915 { "vfrczpd", { XM, EXxmm }, 0 },
9916 { "vfrczpd", { XM, EXymmq }, 0 },
9920 static const struct dis386 evex_len_table[][3] = {
9921 #define NEED_EVEX_LEN_TABLE
9922 #include "i386-dis-evex.h"
9923 #undef NEED_EVEX_LEN_TABLE
9926 static const struct dis386 vex_w_table[][2] = {
9928 /* VEX_W_0F41_P_0_LEN_1 */
9929 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
9930 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
9933 /* VEX_W_0F41_P_2_LEN_1 */
9934 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
9935 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
9938 /* VEX_W_0F42_P_0_LEN_1 */
9939 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
9940 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
9943 /* VEX_W_0F42_P_2_LEN_1 */
9944 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
9945 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
9948 /* VEX_W_0F44_P_0_LEN_0 */
9949 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
9950 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
9953 /* VEX_W_0F44_P_2_LEN_0 */
9954 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
9955 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
9958 /* VEX_W_0F45_P_0_LEN_1 */
9959 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
9960 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
9963 /* VEX_W_0F45_P_2_LEN_1 */
9964 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
9965 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
9968 /* VEX_W_0F46_P_0_LEN_1 */
9969 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
9970 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
9973 /* VEX_W_0F46_P_2_LEN_1 */
9974 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
9975 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
9978 /* VEX_W_0F47_P_0_LEN_1 */
9979 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
9980 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
9983 /* VEX_W_0F47_P_2_LEN_1 */
9984 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
9985 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
9988 /* VEX_W_0F4A_P_0_LEN_1 */
9989 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
9990 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
9993 /* VEX_W_0F4A_P_2_LEN_1 */
9994 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
9995 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
9998 /* VEX_W_0F4B_P_0_LEN_1 */
9999 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10000 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10003 /* VEX_W_0F4B_P_2_LEN_1 */
10004 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10007 /* VEX_W_0F90_P_0_LEN_0 */
10008 { "kmovw", { MaskG, MaskE }, 0 },
10009 { "kmovq", { MaskG, MaskE }, 0 },
10012 /* VEX_W_0F90_P_2_LEN_0 */
10013 { "kmovb", { MaskG, MaskBDE }, 0 },
10014 { "kmovd", { MaskG, MaskBDE }, 0 },
10017 /* VEX_W_0F91_P_0_LEN_0 */
10018 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10019 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10022 /* VEX_W_0F91_P_2_LEN_0 */
10023 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10024 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10027 /* VEX_W_0F92_P_0_LEN_0 */
10028 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10031 /* VEX_W_0F92_P_2_LEN_0 */
10032 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10035 /* VEX_W_0F93_P_0_LEN_0 */
10036 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10039 /* VEX_W_0F93_P_2_LEN_0 */
10040 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10043 /* VEX_W_0F98_P_0_LEN_0 */
10044 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10045 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10048 /* VEX_W_0F98_P_2_LEN_0 */
10049 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10050 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10053 /* VEX_W_0F99_P_0_LEN_0 */
10054 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10055 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10058 /* VEX_W_0F99_P_2_LEN_0 */
10059 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10060 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10063 /* VEX_W_0F380C_P_2 */
10064 { "vpermilps", { XM, Vex, EXx }, 0 },
10067 /* VEX_W_0F380D_P_2 */
10068 { "vpermilpd", { XM, Vex, EXx }, 0 },
10071 /* VEX_W_0F380E_P_2 */
10072 { "vtestps", { XM, EXx }, 0 },
10075 /* VEX_W_0F380F_P_2 */
10076 { "vtestpd", { XM, EXx }, 0 },
10079 /* VEX_W_0F3816_P_2 */
10080 { "vpermps", { XM, Vex, EXx }, 0 },
10083 /* VEX_W_0F3818_P_2 */
10084 { "vbroadcastss", { XM, EXxmm_md }, 0 },
10087 /* VEX_W_0F3819_P_2 */
10088 { "vbroadcastsd", { XM, EXxmm_mq }, 0 },
10091 /* VEX_W_0F381A_P_2_M_0 */
10092 { "vbroadcastf128", { XM, Mxmm }, 0 },
10095 /* VEX_W_0F382C_P_2_M_0 */
10096 { "vmaskmovps", { XM, Vex, Mx }, 0 },
10099 /* VEX_W_0F382D_P_2_M_0 */
10100 { "vmaskmovpd", { XM, Vex, Mx }, 0 },
10103 /* VEX_W_0F382E_P_2_M_0 */
10104 { "vmaskmovps", { Mx, Vex, XM }, 0 },
10107 /* VEX_W_0F382F_P_2_M_0 */
10108 { "vmaskmovpd", { Mx, Vex, XM }, 0 },
10111 /* VEX_W_0F3836_P_2 */
10112 { "vpermd", { XM, Vex, EXx }, 0 },
10115 /* VEX_W_0F3846_P_2 */
10116 { "vpsravd", { XM, Vex, EXx }, 0 },
10119 /* VEX_W_0F3858_P_2 */
10120 { "vpbroadcastd", { XM, EXxmm_md }, 0 },
10123 /* VEX_W_0F3859_P_2 */
10124 { "vpbroadcastq", { XM, EXxmm_mq }, 0 },
10127 /* VEX_W_0F385A_P_2_M_0 */
10128 { "vbroadcasti128", { XM, Mxmm }, 0 },
10131 /* VEX_W_0F3878_P_2 */
10132 { "vpbroadcastb", { XM, EXxmm_mb }, 0 },
10135 /* VEX_W_0F3879_P_2 */
10136 { "vpbroadcastw", { XM, EXxmm_mw }, 0 },
10139 /* VEX_W_0F38CF_P_2 */
10140 { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
10143 /* VEX_W_0F3A00_P_2 */
10145 { "vpermq", { XM, EXx, Ib }, 0 },
10148 /* VEX_W_0F3A01_P_2 */
10150 { "vpermpd", { XM, EXx, Ib }, 0 },
10153 /* VEX_W_0F3A02_P_2 */
10154 { "vpblendd", { XM, Vex, EXx, Ib }, 0 },
10157 /* VEX_W_0F3A04_P_2 */
10158 { "vpermilps", { XM, EXx, Ib }, 0 },
10161 /* VEX_W_0F3A05_P_2 */
10162 { "vpermilpd", { XM, EXx, Ib }, 0 },
10165 /* VEX_W_0F3A06_P_2 */
10166 { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 },
10169 /* VEX_W_0F3A18_P_2 */
10170 { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 },
10173 /* VEX_W_0F3A19_P_2 */
10174 { "vextractf128", { EXxmm, XM, Ib }, 0 },
10177 /* VEX_W_0F3A30_P_2_LEN_0 */
10178 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
10179 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
10182 /* VEX_W_0F3A31_P_2_LEN_0 */
10183 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10184 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10187 /* VEX_W_0F3A32_P_2_LEN_0 */
10188 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10189 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10192 /* VEX_W_0F3A33_P_2_LEN_0 */
10193 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10194 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10197 /* VEX_W_0F3A38_P_2 */
10198 { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 },
10201 /* VEX_W_0F3A39_P_2 */
10202 { "vextracti128", { EXxmm, XM, Ib }, 0 },
10205 /* VEX_W_0F3A46_P_2 */
10206 { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 },
10209 /* VEX_W_0F3A48_P_2 */
10210 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10211 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10214 /* VEX_W_0F3A49_P_2 */
10215 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10216 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10219 /* VEX_W_0F3A4A_P_2 */
10220 { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 },
10223 /* VEX_W_0F3A4B_P_2 */
10224 { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 },
10227 /* VEX_W_0F3A4C_P_2 */
10228 { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 },
10231 /* VEX_W_0F3ACE_P_2 */
10233 { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10236 /* VEX_W_0F3ACF_P_2 */
10238 { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, 0 },
10240 #define NEED_VEX_W_TABLE
10241 #include "i386-dis-evex.h"
10242 #undef NEED_VEX_W_TABLE
10245 static const struct dis386 mod_table[][2] = {
10248 { "leaS", { Gv, M }, 0 },
10253 { RM_TABLE (RM_C6_REG_7) },
10258 { RM_TABLE (RM_C7_REG_7) },
10262 { "Jcall^", { indirEp }, 0 },
10266 { "Jjmp^", { indirEp }, 0 },
10269 /* MOD_0F01_REG_0 */
10270 { X86_64_TABLE (X86_64_0F01_REG_0) },
10271 { RM_TABLE (RM_0F01_REG_0) },
10274 /* MOD_0F01_REG_1 */
10275 { X86_64_TABLE (X86_64_0F01_REG_1) },
10276 { RM_TABLE (RM_0F01_REG_1) },
10279 /* MOD_0F01_REG_2 */
10280 { X86_64_TABLE (X86_64_0F01_REG_2) },
10281 { RM_TABLE (RM_0F01_REG_2) },
10284 /* MOD_0F01_REG_3 */
10285 { X86_64_TABLE (X86_64_0F01_REG_3) },
10286 { RM_TABLE (RM_0F01_REG_3) },
10289 /* MOD_0F01_REG_5 */
10290 { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
10291 { RM_TABLE (RM_0F01_REG_5) },
10294 /* MOD_0F01_REG_7 */
10295 { "invlpg", { Mb }, 0 },
10296 { RM_TABLE (RM_0F01_REG_7) },
10299 /* MOD_0F12_PREFIX_0 */
10300 { "movlps", { XM, EXq }, PREFIX_OPCODE },
10301 { "movhlps", { XM, EXq }, PREFIX_OPCODE },
10305 { "movlpX", { EXq, XM }, PREFIX_OPCODE },
10308 /* MOD_0F16_PREFIX_0 */
10309 { "movhps", { XM, EXq }, 0 },
10310 { "movlhps", { XM, EXq }, 0 },
10314 { "movhpX", { EXq, XM }, PREFIX_OPCODE },
10317 /* MOD_0F18_REG_0 */
10318 { "prefetchnta", { Mb }, 0 },
10321 /* MOD_0F18_REG_1 */
10322 { "prefetcht0", { Mb }, 0 },
10325 /* MOD_0F18_REG_2 */
10326 { "prefetcht1", { Mb }, 0 },
10329 /* MOD_0F18_REG_3 */
10330 { "prefetcht2", { Mb }, 0 },
10333 /* MOD_0F18_REG_4 */
10334 { "nop/reserved", { Mb }, 0 },
10337 /* MOD_0F18_REG_5 */
10338 { "nop/reserved", { Mb }, 0 },
10341 /* MOD_0F18_REG_6 */
10342 { "nop/reserved", { Mb }, 0 },
10345 /* MOD_0F18_REG_7 */
10346 { "nop/reserved", { Mb }, 0 },
10349 /* MOD_0F1A_PREFIX_0 */
10350 { "bndldx", { Gbnd, Mv_bnd }, 0 },
10351 { "nopQ", { Ev }, 0 },
10354 /* MOD_0F1B_PREFIX_0 */
10355 { "bndstx", { Mv_bnd, Gbnd }, 0 },
10356 { "nopQ", { Ev }, 0 },
10359 /* MOD_0F1B_PREFIX_1 */
10360 { "bndmk", { Gbnd, Mv_bnd }, 0 },
10361 { "nopQ", { Ev }, 0 },
10364 /* MOD_0F1C_PREFIX_0 */
10365 { REG_TABLE (REG_0F1C_MOD_0) },
10366 { "nopQ", { Ev }, 0 },
10369 /* MOD_0F1E_PREFIX_1 */
10370 { "nopQ", { Ev }, 0 },
10371 { REG_TABLE (REG_0F1E_MOD_3) },
10376 { "movL", { Rd, Td }, 0 },
10381 { "movL", { Td, Rd }, 0 },
10384 /* MOD_0F2B_PREFIX_0 */
10385 {"movntps", { Mx, XM }, PREFIX_OPCODE },
10388 /* MOD_0F2B_PREFIX_1 */
10389 {"movntss", { Md, XM }, PREFIX_OPCODE },
10392 /* MOD_0F2B_PREFIX_2 */
10393 {"movntpd", { Mx, XM }, PREFIX_OPCODE },
10396 /* MOD_0F2B_PREFIX_3 */
10397 {"movntsd", { Mq, XM }, PREFIX_OPCODE },
10402 { "movmskpX", { Gdq, XS }, PREFIX_OPCODE },
10405 /* MOD_0F71_REG_2 */
10407 { "psrlw", { MS, Ib }, 0 },
10410 /* MOD_0F71_REG_4 */
10412 { "psraw", { MS, Ib }, 0 },
10415 /* MOD_0F71_REG_6 */
10417 { "psllw", { MS, Ib }, 0 },
10420 /* MOD_0F72_REG_2 */
10422 { "psrld", { MS, Ib }, 0 },
10425 /* MOD_0F72_REG_4 */
10427 { "psrad", { MS, Ib }, 0 },
10430 /* MOD_0F72_REG_6 */
10432 { "pslld", { MS, Ib }, 0 },
10435 /* MOD_0F73_REG_2 */
10437 { "psrlq", { MS, Ib }, 0 },
10440 /* MOD_0F73_REG_3 */
10442 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10445 /* MOD_0F73_REG_6 */
10447 { "psllq", { MS, Ib }, 0 },
10450 /* MOD_0F73_REG_7 */
10452 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10455 /* MOD_0FAE_REG_0 */
10456 { "fxsave", { FXSAVE }, 0 },
10457 { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
10460 /* MOD_0FAE_REG_1 */
10461 { "fxrstor", { FXSAVE }, 0 },
10462 { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
10465 /* MOD_0FAE_REG_2 */
10466 { "ldmxcsr", { Md }, 0 },
10467 { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
10470 /* MOD_0FAE_REG_3 */
10471 { "stmxcsr", { Md }, 0 },
10472 { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
10475 /* MOD_0FAE_REG_4 */
10476 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
10477 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
10480 /* MOD_0FAE_REG_5 */
10481 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
10482 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
10485 /* MOD_0FAE_REG_6 */
10486 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6) },
10487 { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6) },
10490 /* MOD_0FAE_REG_7 */
10491 { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
10492 { RM_TABLE (RM_0FAE_REG_7) },
10496 { "lssS", { Gv, Mp }, 0 },
10500 { "lfsS", { Gv, Mp }, 0 },
10504 { "lgsS", { Gv, Mp }, 0 },
10508 { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
10511 /* MOD_0FC7_REG_3 */
10512 { "xrstors", { FXSAVE }, 0 },
10515 /* MOD_0FC7_REG_4 */
10516 { "xsavec", { FXSAVE }, 0 },
10519 /* MOD_0FC7_REG_5 */
10520 { "xsaves", { FXSAVE }, 0 },
10523 /* MOD_0FC7_REG_6 */
10524 { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
10525 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
10528 /* MOD_0FC7_REG_7 */
10529 { "vmptrst", { Mq }, 0 },
10530 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
10535 { "pmovmskb", { Gdq, MS }, 0 },
10538 /* MOD_0FE7_PREFIX_2 */
10539 { "movntdq", { Mx, XM }, 0 },
10542 /* MOD_0FF0_PREFIX_3 */
10543 { "lddqu", { XM, M }, 0 },
10546 /* MOD_0F382A_PREFIX_2 */
10547 { "movntdqa", { XM, Mx }, 0 },
10550 /* MOD_0F38F5_PREFIX_2 */
10551 { "wrussK", { M, Gdq }, PREFIX_OPCODE },
10554 /* MOD_0F38F6_PREFIX_0 */
10555 { "wrssK", { M, Gdq }, PREFIX_OPCODE },
10558 /* MOD_0F38F8_PREFIX_1 */
10559 { "enqcmds", { Gva, M }, PREFIX_OPCODE },
10562 /* MOD_0F38F8_PREFIX_2 */
10563 { "movdir64b", { Gva, M }, PREFIX_OPCODE },
10566 /* MOD_0F38F8_PREFIX_3 */
10567 { "enqcmd", { Gva, M }, PREFIX_OPCODE },
10570 /* MOD_0F38F9_PREFIX_0 */
10571 { "movdiri", { Em, Gv }, PREFIX_OPCODE },
10575 { "bound{S|}", { Gv, Ma }, 0 },
10576 { EVEX_TABLE (EVEX_0F) },
10580 { "lesS", { Gv, Mp }, 0 },
10581 { VEX_C4_TABLE (VEX_0F) },
10585 { "ldsS", { Gv, Mp }, 0 },
10586 { VEX_C5_TABLE (VEX_0F) },
10589 /* MOD_VEX_0F12_PREFIX_0 */
10590 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10591 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10595 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10598 /* MOD_VEX_0F16_PREFIX_0 */
10599 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10600 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10604 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10608 { "vmovntpX", { Mx, XM }, 0 },
10611 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10613 { "kandw", { MaskG, MaskVex, MaskR }, 0 },
10616 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10618 { "kandq", { MaskG, MaskVex, MaskR }, 0 },
10621 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10623 { "kandb", { MaskG, MaskVex, MaskR }, 0 },
10626 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10628 { "kandd", { MaskG, MaskVex, MaskR }, 0 },
10631 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10633 { "kandnw", { MaskG, MaskVex, MaskR }, 0 },
10636 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10638 { "kandnq", { MaskG, MaskVex, MaskR }, 0 },
10641 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10643 { "kandnb", { MaskG, MaskVex, MaskR }, 0 },
10646 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10648 { "kandnd", { MaskG, MaskVex, MaskR }, 0 },
10651 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10653 { "knotw", { MaskG, MaskR }, 0 },
10656 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10658 { "knotq", { MaskG, MaskR }, 0 },
10661 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10663 { "knotb", { MaskG, MaskR }, 0 },
10666 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10668 { "knotd", { MaskG, MaskR }, 0 },
10671 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10673 { "korw", { MaskG, MaskVex, MaskR }, 0 },
10676 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10678 { "korq", { MaskG, MaskVex, MaskR }, 0 },
10681 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10683 { "korb", { MaskG, MaskVex, MaskR }, 0 },
10686 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10688 { "kord", { MaskG, MaskVex, MaskR }, 0 },
10691 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10693 { "kxnorw", { MaskG, MaskVex, MaskR }, 0 },
10696 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10698 { "kxnorq", { MaskG, MaskVex, MaskR }, 0 },
10701 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10703 { "kxnorb", { MaskG, MaskVex, MaskR }, 0 },
10706 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10708 { "kxnord", { MaskG, MaskVex, MaskR }, 0 },
10711 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10713 { "kxorw", { MaskG, MaskVex, MaskR }, 0 },
10716 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10718 { "kxorq", { MaskG, MaskVex, MaskR }, 0 },
10721 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10723 { "kxorb", { MaskG, MaskVex, MaskR }, 0 },
10726 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10728 { "kxord", { MaskG, MaskVex, MaskR }, 0 },
10731 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10733 { "kaddw", { MaskG, MaskVex, MaskR }, 0 },
10736 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10738 { "kaddq", { MaskG, MaskVex, MaskR }, 0 },
10741 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10743 { "kaddb", { MaskG, MaskVex, MaskR }, 0 },
10746 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10748 { "kaddd", { MaskG, MaskVex, MaskR }, 0 },
10751 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10753 { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 },
10756 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10758 { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 },
10761 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10763 { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 },
10768 { "vmovmskpX", { Gdq, XS }, 0 },
10771 /* MOD_VEX_0F71_REG_2 */
10773 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10776 /* MOD_VEX_0F71_REG_4 */
10778 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10781 /* MOD_VEX_0F71_REG_6 */
10783 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10786 /* MOD_VEX_0F72_REG_2 */
10788 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10791 /* MOD_VEX_0F72_REG_4 */
10793 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10796 /* MOD_VEX_0F72_REG_6 */
10798 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10801 /* MOD_VEX_0F73_REG_2 */
10803 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10806 /* MOD_VEX_0F73_REG_3 */
10808 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10811 /* MOD_VEX_0F73_REG_6 */
10813 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10816 /* MOD_VEX_0F73_REG_7 */
10818 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10821 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10822 { "kmovw", { Ew, MaskG }, 0 },
10826 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10827 { "kmovq", { Eq, MaskG }, 0 },
10831 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10832 { "kmovb", { Eb, MaskG }, 0 },
10836 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10837 { "kmovd", { Ed, MaskG }, 0 },
10841 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10843 { "kmovw", { MaskG, Rdq }, 0 },
10846 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10848 { "kmovb", { MaskG, Rdq }, 0 },
10851 /* MOD_VEX_0F92_P_3_LEN_0 */
10853 { "kmovK", { MaskG, Rdq }, 0 },
10856 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10858 { "kmovw", { Gdq, MaskR }, 0 },
10861 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10863 { "kmovb", { Gdq, MaskR }, 0 },
10866 /* MOD_VEX_0F93_P_3_LEN_0 */
10868 { "kmovK", { Gdq, MaskR }, 0 },
10871 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10873 { "kortestw", { MaskG, MaskR }, 0 },
10876 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10878 { "kortestq", { MaskG, MaskR }, 0 },
10881 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10883 { "kortestb", { MaskG, MaskR }, 0 },
10886 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10888 { "kortestd", { MaskG, MaskR }, 0 },
10891 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10893 { "ktestw", { MaskG, MaskR }, 0 },
10896 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10898 { "ktestq", { MaskG, MaskR }, 0 },
10901 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10903 { "ktestb", { MaskG, MaskR }, 0 },
10906 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10908 { "ktestd", { MaskG, MaskR }, 0 },
10911 /* MOD_VEX_0FAE_REG_2 */
10912 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10915 /* MOD_VEX_0FAE_REG_3 */
10916 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10919 /* MOD_VEX_0FD7_PREFIX_2 */
10921 { "vpmovmskb", { Gdq, XS }, 0 },
10924 /* MOD_VEX_0FE7_PREFIX_2 */
10925 { "vmovntdq", { Mx, XM }, 0 },
10928 /* MOD_VEX_0FF0_PREFIX_3 */
10929 { "vlddqu", { XM, M }, 0 },
10932 /* MOD_VEX_0F381A_PREFIX_2 */
10933 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10936 /* MOD_VEX_0F382A_PREFIX_2 */
10937 { "vmovntdqa", { XM, Mx }, 0 },
10940 /* MOD_VEX_0F382C_PREFIX_2 */
10941 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10944 /* MOD_VEX_0F382D_PREFIX_2 */
10945 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10948 /* MOD_VEX_0F382E_PREFIX_2 */
10949 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10952 /* MOD_VEX_0F382F_PREFIX_2 */
10953 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10956 /* MOD_VEX_0F385A_PREFIX_2 */
10957 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10960 /* MOD_VEX_0F388C_PREFIX_2 */
10961 { "vpmaskmov%LW", { XM, Vex, Mx }, 0 },
10964 /* MOD_VEX_0F388E_PREFIX_2 */
10965 { "vpmaskmov%LW", { Mx, Vex, XM }, 0 },
10968 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10970 { "kshiftrb", { MaskG, MaskR, Ib }, 0 },
10973 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10975 { "kshiftrw", { MaskG, MaskR, Ib }, 0 },
10978 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10980 { "kshiftrd", { MaskG, MaskR, Ib }, 0 },
10983 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10985 { "kshiftrq", { MaskG, MaskR, Ib }, 0 },
10988 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10990 { "kshiftlb", { MaskG, MaskR, Ib }, 0 },
10993 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10995 { "kshiftlw", { MaskG, MaskR, Ib }, 0 },
10998 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
11000 { "kshiftld", { MaskG, MaskR, Ib }, 0 },
11003 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
11005 { "kshiftlq", { MaskG, MaskR, Ib }, 0 },
11007 #define NEED_MOD_TABLE
11008 #include "i386-dis-evex.h"
11009 #undef NEED_MOD_TABLE
11012 static const struct dis386 rm_table[][8] = {
11015 { "xabort", { Skip_MODRM, Ib }, 0 },
11019 { "xbeginT", { Skip_MODRM, Jv }, 0 },
11022 /* RM_0F01_REG_0 */
11023 { "enclv", { Skip_MODRM }, 0 },
11024 { "vmcall", { Skip_MODRM }, 0 },
11025 { "vmlaunch", { Skip_MODRM }, 0 },
11026 { "vmresume", { Skip_MODRM }, 0 },
11027 { "vmxoff", { Skip_MODRM }, 0 },
11028 { "pconfig", { Skip_MODRM }, 0 },
11031 /* RM_0F01_REG_1 */
11032 { "monitor", { { OP_Monitor, 0 } }, 0 },
11033 { "mwait", { { OP_Mwait, 0 } }, 0 },
11034 { "clac", { Skip_MODRM }, 0 },
11035 { "stac", { Skip_MODRM }, 0 },
11039 { "encls", { Skip_MODRM }, 0 },
11042 /* RM_0F01_REG_2 */
11043 { "xgetbv", { Skip_MODRM }, 0 },
11044 { "xsetbv", { Skip_MODRM }, 0 },
11047 { "vmfunc", { Skip_MODRM }, 0 },
11048 { "xend", { Skip_MODRM }, 0 },
11049 { "xtest", { Skip_MODRM }, 0 },
11050 { "enclu", { Skip_MODRM }, 0 },
11053 /* RM_0F01_REG_3 */
11054 { "vmrun", { Skip_MODRM }, 0 },
11055 { "vmmcall", { Skip_MODRM }, 0 },
11056 { "vmload", { Skip_MODRM }, 0 },
11057 { "vmsave", { Skip_MODRM }, 0 },
11058 { "stgi", { Skip_MODRM }, 0 },
11059 { "clgi", { Skip_MODRM }, 0 },
11060 { "skinit", { Skip_MODRM }, 0 },
11061 { "invlpga", { Skip_MODRM }, 0 },
11064 /* RM_0F01_REG_5 */
11065 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
11067 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
11071 { "rdpkru", { Skip_MODRM }, 0 },
11072 { "wrpkru", { Skip_MODRM }, 0 },
11075 /* RM_0F01_REG_7 */
11076 { "swapgs", { Skip_MODRM }, 0 },
11077 { "rdtscp", { Skip_MODRM }, 0 },
11078 { "monitorx", { { OP_Monitor, 0 } }, 0 },
11079 { "mwaitx", { { OP_Mwaitx, 0 } }, 0 },
11080 { "clzero", { Skip_MODRM }, 0 },
11083 /* RM_0F1E_MOD_3_REG_7 */
11084 { "nopQ", { Ev }, 0 },
11085 { "nopQ", { Ev }, 0 },
11086 { "endbr64", { Skip_MODRM }, PREFIX_OPCODE },
11087 { "endbr32", { Skip_MODRM }, PREFIX_OPCODE },
11088 { "nopQ", { Ev }, 0 },
11089 { "nopQ", { Ev }, 0 },
11090 { "nopQ", { Ev }, 0 },
11091 { "nopQ", { Ev }, 0 },
11094 /* RM_0FAE_REG_6 */
11095 { "mfence", { Skip_MODRM }, 0 },
11098 /* RM_0FAE_REG_7 */
11099 { "sfence", { Skip_MODRM }, 0 },
11104 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11106 /* We use the high bit to indicate different name for the same
11108 #define REP_PREFIX (0xf3 | 0x100)
11109 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11110 #define XRELEASE_PREFIX (0xf3 | 0x400)
11111 #define BND_PREFIX (0xf2 | 0x400)
11112 #define NOTRACK_PREFIX (0x3e | 0x100)
11117 int newrex, i, length;
11123 last_lock_prefix = -1;
11124 last_repz_prefix = -1;
11125 last_repnz_prefix = -1;
11126 last_data_prefix = -1;
11127 last_addr_prefix = -1;
11128 last_rex_prefix = -1;
11129 last_seg_prefix = -1;
11131 active_seg_prefix = 0;
11132 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11133 all_prefixes[i] = 0;
11136 /* The maximum instruction length is 15bytes. */
11137 while (length < MAX_CODE_LENGTH - 1)
11139 FETCH_DATA (the_info, codep + 1);
11143 /* REX prefixes family. */
11160 if (address_mode == mode_64bit)
11164 last_rex_prefix = i;
11167 prefixes |= PREFIX_REPZ;
11168 last_repz_prefix = i;
11171 prefixes |= PREFIX_REPNZ;
11172 last_repnz_prefix = i;
11175 prefixes |= PREFIX_LOCK;
11176 last_lock_prefix = i;
11179 prefixes |= PREFIX_CS;
11180 last_seg_prefix = i;
11181 active_seg_prefix = PREFIX_CS;
11184 prefixes |= PREFIX_SS;
11185 last_seg_prefix = i;
11186 active_seg_prefix = PREFIX_SS;
11189 prefixes |= PREFIX_DS;
11190 last_seg_prefix = i;
11191 active_seg_prefix = PREFIX_DS;
11194 prefixes |= PREFIX_ES;
11195 last_seg_prefix = i;
11196 active_seg_prefix = PREFIX_ES;
11199 prefixes |= PREFIX_FS;
11200 last_seg_prefix = i;
11201 active_seg_prefix = PREFIX_FS;
11204 prefixes |= PREFIX_GS;
11205 last_seg_prefix = i;
11206 active_seg_prefix = PREFIX_GS;
11209 prefixes |= PREFIX_DATA;
11210 last_data_prefix = i;
11213 prefixes |= PREFIX_ADDR;
11214 last_addr_prefix = i;
11217 /* fwait is really an instruction. If there are prefixes
11218 before the fwait, they belong to the fwait, *not* to the
11219 following instruction. */
11221 if (prefixes || rex)
11223 prefixes |= PREFIX_FWAIT;
11225 /* This ensures that the previous REX prefixes are noticed
11226 as unused prefixes, as in the return case below. */
11230 prefixes = PREFIX_FWAIT;
11235 /* Rex is ignored when followed by another prefix. */
11241 if (*codep != FWAIT_OPCODE)
11242 all_prefixes[i++] = *codep;
11250 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11253 static const char *
11254 prefix_name (int pref, int sizeflag)
11256 static const char *rexes [16] =
11259 "rex.B", /* 0x41 */
11260 "rex.X", /* 0x42 */
11261 "rex.XB", /* 0x43 */
11262 "rex.R", /* 0x44 */
11263 "rex.RB", /* 0x45 */
11264 "rex.RX", /* 0x46 */
11265 "rex.RXB", /* 0x47 */
11266 "rex.W", /* 0x48 */
11267 "rex.WB", /* 0x49 */
11268 "rex.WX", /* 0x4a */
11269 "rex.WXB", /* 0x4b */
11270 "rex.WR", /* 0x4c */
11271 "rex.WRB", /* 0x4d */
11272 "rex.WRX", /* 0x4e */
11273 "rex.WRXB", /* 0x4f */
11278 /* REX prefixes family. */
11295 return rexes [pref - 0x40];
11315 return (sizeflag & DFLAG) ? "data16" : "data32";
11317 if (address_mode == mode_64bit)
11318 return (sizeflag & AFLAG) ? "addr32" : "addr64";
11320 return (sizeflag & AFLAG) ? "addr16" : "addr32";
11325 case XACQUIRE_PREFIX:
11327 case XRELEASE_PREFIX:
11331 case NOTRACK_PREFIX:
11338 static char op_out[MAX_OPERANDS][100];
11339 static int op_ad, op_index[MAX_OPERANDS];
11340 static int two_source_ops;
11341 static bfd_vma op_address[MAX_OPERANDS];
11342 static bfd_vma op_riprel[MAX_OPERANDS];
11343 static bfd_vma start_pc;
11346 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11347 * (see topic "Redundant prefixes" in the "Differences from 8086"
11348 * section of the "Virtual 8086 Mode" chapter.)
11349 * 'pc' should be the address of this instruction, it will
11350 * be used to print the target address if this is a relative jump or call
11351 * The function returns the length of this instruction in bytes.
11354 static char intel_syntax;
11355 static char intel_mnemonic = !SYSV386_COMPAT;
11356 static char open_char;
11357 static char close_char;
11358 static char separator_char;
11359 static char scale_char;
11367 static enum x86_64_isa isa64;
11369 /* Here for backwards compatibility. When gdb stops using
11370 print_insn_i386_att and print_insn_i386_intel these functions can
11371 disappear, and print_insn_i386 be merged into print_insn. */
11373 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11377 return print_insn (pc, info);
11381 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11385 return print_insn (pc, info);
11389 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11393 return print_insn (pc, info);
11397 print_i386_disassembler_options (FILE *stream)
11399 fprintf (stream, _("\n\
11400 The following i386/x86-64 specific disassembler options are supported for use\n\
11401 with the -M switch (multiple options should be separated by commas):\n"));
11403 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
11404 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
11405 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
11406 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
11407 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
11408 fprintf (stream, _(" att-mnemonic\n"
11409 " Display instruction in AT&T mnemonic\n"));
11410 fprintf (stream, _(" intel-mnemonic\n"
11411 " Display instruction in Intel mnemonic\n"));
11412 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
11413 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
11414 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
11415 fprintf (stream, _(" data32 Assume 32bit data size\n"));
11416 fprintf (stream, _(" data16 Assume 16bit data size\n"));
11417 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
11418 fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n"));
11419 fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n"));
11423 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11425 /* Get a pointer to struct dis386 with a valid name. */
11427 static const struct dis386 *
11428 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11430 int vindex, vex_table_index;
11432 if (dp->name != NULL)
11435 switch (dp->op[0].bytemode)
11437 case USE_REG_TABLE:
11438 dp = ®_table[dp->op[1].bytemode][modrm.reg];
11441 case USE_MOD_TABLE:
11442 vindex = modrm.mod == 0x3 ? 1 : 0;
11443 dp = &mod_table[dp->op[1].bytemode][vindex];
11447 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11450 case USE_PREFIX_TABLE:
11453 /* The prefix in VEX is implicit. */
11454 switch (vex.prefix)
11459 case REPE_PREFIX_OPCODE:
11462 case DATA_PREFIX_OPCODE:
11465 case REPNE_PREFIX_OPCODE:
11475 int last_prefix = -1;
11478 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11479 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11481 if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11483 if (last_repz_prefix > last_repnz_prefix)
11486 prefix = PREFIX_REPZ;
11487 last_prefix = last_repz_prefix;
11492 prefix = PREFIX_REPNZ;
11493 last_prefix = last_repnz_prefix;
11496 /* Check if prefix should be ignored. */
11497 if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
11498 & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
11503 if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
11506 prefix = PREFIX_DATA;
11507 last_prefix = last_data_prefix;
11512 used_prefixes |= prefix;
11513 all_prefixes[last_prefix] = 0;
11516 dp = &prefix_table[dp->op[1].bytemode][vindex];
11519 case USE_X86_64_TABLE:
11520 vindex = address_mode == mode_64bit ? 1 : 0;
11521 dp = &x86_64_table[dp->op[1].bytemode][vindex];
11524 case USE_3BYTE_TABLE:
11525 FETCH_DATA (info, codep + 2);
11527 dp = &three_byte_table[dp->op[1].bytemode][vindex];
11529 modrm.mod = (*codep >> 6) & 3;
11530 modrm.reg = (*codep >> 3) & 7;
11531 modrm.rm = *codep & 7;
11534 case USE_VEX_LEN_TABLE:
11538 switch (vex.length)
11551 dp = &vex_len_table[dp->op[1].bytemode][vindex];
11554 case USE_EVEX_LEN_TABLE:
11558 switch (vex.length)
11574 dp = &evex_len_table[dp->op[1].bytemode][vindex];
11577 case USE_XOP_8F_TABLE:
11578 FETCH_DATA (info, codep + 3);
11579 /* All bits in the REX prefix are ignored. */
11581 rex = ~(*codep >> 5) & 0x7;
11583 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
11584 switch ((*codep & 0x1f))
11590 vex_table_index = XOP_08;
11593 vex_table_index = XOP_09;
11596 vex_table_index = XOP_0A;
11600 vex.w = *codep & 0x80;
11601 if (vex.w && address_mode == mode_64bit)
11604 vex.register_specifier = (~(*codep >> 3)) & 0xf;
11605 if (address_mode != mode_64bit)
11607 /* In 16/32-bit mode REX_B is silently ignored. */
11611 vex.length = (*codep & 0x4) ? 256 : 128;
11612 switch ((*codep & 0x3))
11617 vex.prefix = DATA_PREFIX_OPCODE;
11620 vex.prefix = REPE_PREFIX_OPCODE;
11623 vex.prefix = REPNE_PREFIX_OPCODE;
11630 dp = &xop_table[vex_table_index][vindex];
11633 FETCH_DATA (info, codep + 1);
11634 modrm.mod = (*codep >> 6) & 3;
11635 modrm.reg = (*codep >> 3) & 7;
11636 modrm.rm = *codep & 7;
11639 case USE_VEX_C4_TABLE:
11641 FETCH_DATA (info, codep + 3);
11642 /* All bits in the REX prefix are ignored. */
11644 rex = ~(*codep >> 5) & 0x7;
11645 switch ((*codep & 0x1f))
11651 vex_table_index = VEX_0F;
11654 vex_table_index = VEX_0F38;
11657 vex_table_index = VEX_0F3A;
11661 vex.w = *codep & 0x80;
11662 if (address_mode == mode_64bit)
11669 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11670 is ignored, other REX bits are 0 and the highest bit in
11671 VEX.vvvv is also ignored (but we mustn't clear it here). */
11674 vex.register_specifier = (~(*codep >> 3)) & 0xf;
11675 vex.length = (*codep & 0x4) ? 256 : 128;
11676 switch ((*codep & 0x3))
11681 vex.prefix = DATA_PREFIX_OPCODE;
11684 vex.prefix = REPE_PREFIX_OPCODE;
11687 vex.prefix = REPNE_PREFIX_OPCODE;
11694 dp = &vex_table[vex_table_index][vindex];
11696 /* There is no MODRM byte for VEX0F 77. */
11697 if (vex_table_index != VEX_0F || vindex != 0x77)
11699 FETCH_DATA (info, codep + 1);
11700 modrm.mod = (*codep >> 6) & 3;
11701 modrm.reg = (*codep >> 3) & 7;
11702 modrm.rm = *codep & 7;
11706 case USE_VEX_C5_TABLE:
11708 FETCH_DATA (info, codep + 2);
11709 /* All bits in the REX prefix are ignored. */
11711 rex = (*codep & 0x80) ? 0 : REX_R;
11713 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11715 vex.register_specifier = (~(*codep >> 3)) & 0xf;
11716 vex.length = (*codep & 0x4) ? 256 : 128;
11717 switch ((*codep & 0x3))
11722 vex.prefix = DATA_PREFIX_OPCODE;
11725 vex.prefix = REPE_PREFIX_OPCODE;
11728 vex.prefix = REPNE_PREFIX_OPCODE;
11735 dp = &vex_table[dp->op[1].bytemode][vindex];
11737 /* There is no MODRM byte for VEX 77. */
11738 if (vindex != 0x77)
11740 FETCH_DATA (info, codep + 1);
11741 modrm.mod = (*codep >> 6) & 3;
11742 modrm.reg = (*codep >> 3) & 7;
11743 modrm.rm = *codep & 7;
11747 case USE_VEX_W_TABLE:
11751 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11754 case USE_EVEX_TABLE:
11755 two_source_ops = 0;
11758 FETCH_DATA (info, codep + 4);
11759 /* All bits in the REX prefix are ignored. */
11761 /* The first byte after 0x62. */
11762 rex = ~(*codep >> 5) & 0x7;
11763 vex.r = *codep & 0x10;
11764 switch ((*codep & 0xf))
11767 return &bad_opcode;
11769 vex_table_index = EVEX_0F;
11772 vex_table_index = EVEX_0F38;
11775 vex_table_index = EVEX_0F3A;
11779 /* The second byte after 0x62. */
11781 vex.w = *codep & 0x80;
11782 if (vex.w && address_mode == mode_64bit)
11785 vex.register_specifier = (~(*codep >> 3)) & 0xf;
11788 if (!(*codep & 0x4))
11789 return &bad_opcode;
11791 switch ((*codep & 0x3))
11796 vex.prefix = DATA_PREFIX_OPCODE;
11799 vex.prefix = REPE_PREFIX_OPCODE;
11802 vex.prefix = REPNE_PREFIX_OPCODE;
11806 /* The third byte after 0x62. */
11809 /* Remember the static rounding bits. */
11810 vex.ll = (*codep >> 5) & 3;
11811 vex.b = (*codep & 0x10) != 0;
11813 vex.v = *codep & 0x8;
11814 vex.mask_register_specifier = *codep & 0x7;
11815 vex.zeroing = *codep & 0x80;
11817 if (address_mode != mode_64bit)
11819 /* In 16/32-bit mode silently ignore following bits. */
11829 dp = &evex_table[vex_table_index][vindex];
11831 FETCH_DATA (info, codep + 1);
11832 modrm.mod = (*codep >> 6) & 3;
11833 modrm.reg = (*codep >> 3) & 7;
11834 modrm.rm = *codep & 7;
11836 /* Set vector length. */
11837 if (modrm.mod == 3 && vex.b)
11853 return &bad_opcode;
11866 if (dp->name != NULL)
11869 return get_valid_dis386 (dp, info);
11873 get_sib (disassemble_info *info, int sizeflag)
11875 /* If modrm.mod == 3, operand must be register. */
11877 && ((sizeflag & AFLAG) || address_mode == mode_64bit)
11881 FETCH_DATA (info, codep + 2);
11882 sib.index = (codep [1] >> 3) & 7;
11883 sib.scale = (codep [1] >> 6) & 3;
11884 sib.base = codep [1] & 7;
11889 print_insn (bfd_vma pc, disassemble_info *info)
11891 const struct dis386 *dp;
11893 char *op_txt[MAX_OPERANDS];
11895 int sizeflag, orig_sizeflag;
11897 struct dis_private priv;
11900 priv.orig_sizeflag = AFLAG | DFLAG;
11901 if ((info->mach & bfd_mach_i386_i386) != 0)
11902 address_mode = mode_32bit;
11903 else if (info->mach == bfd_mach_i386_i8086)
11905 address_mode = mode_16bit;
11906 priv.orig_sizeflag = 0;
11909 address_mode = mode_64bit;
11911 if (intel_syntax == (char) -1)
11912 intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11914 for (p = info->disassembler_options; p != NULL; )
11916 if (CONST_STRNEQ (p, "amd64"))
11918 else if (CONST_STRNEQ (p, "intel64"))
11920 else if (CONST_STRNEQ (p, "x86-64"))
11922 address_mode = mode_64bit;
11923 priv.orig_sizeflag = AFLAG | DFLAG;
11925 else if (CONST_STRNEQ (p, "i386"))
11927 address_mode = mode_32bit;
11928 priv.orig_sizeflag = AFLAG | DFLAG;
11930 else if (CONST_STRNEQ (p, "i8086"))
11932 address_mode = mode_16bit;
11933 priv.orig_sizeflag = 0;
11935 else if (CONST_STRNEQ (p, "intel"))
11938 if (CONST_STRNEQ (p + 5, "-mnemonic"))
11939 intel_mnemonic = 1;
11941 else if (CONST_STRNEQ (p, "att"))
11944 if (CONST_STRNEQ (p + 3, "-mnemonic"))
11945 intel_mnemonic = 0;
11947 else if (CONST_STRNEQ (p, "addr"))
11949 if (address_mode == mode_64bit)
11951 if (p[4] == '3' && p[5] == '2')
11952 priv.orig_sizeflag &= ~AFLAG;
11953 else if (p[4] == '6' && p[5] == '4')
11954 priv.orig_sizeflag |= AFLAG;
11958 if (p[4] == '1' && p[5] == '6')
11959 priv.orig_sizeflag &= ~AFLAG;
11960 else if (p[4] == '3' && p[5] == '2')
11961 priv.orig_sizeflag |= AFLAG;
11964 else if (CONST_STRNEQ (p, "data"))
11966 if (p[4] == '1' && p[5] == '6')
11967 priv.orig_sizeflag &= ~DFLAG;
11968 else if (p[4] == '3' && p[5] == '2')
11969 priv.orig_sizeflag |= DFLAG;
11971 else if (CONST_STRNEQ (p, "suffix"))
11972 priv.orig_sizeflag |= SUFFIX_ALWAYS;
11974 p = strchr (p, ',');
11979 if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
11981 (*info->fprintf_func) (info->stream,
11982 _("64-bit address is disabled"));
11988 names64 = intel_names64;
11989 names32 = intel_names32;
11990 names16 = intel_names16;
11991 names8 = intel_names8;
11992 names8rex = intel_names8rex;
11993 names_seg = intel_names_seg;
11994 names_mm = intel_names_mm;
11995 names_bnd = intel_names_bnd;
11996 names_xmm = intel_names_xmm;
11997 names_ymm = intel_names_ymm;
11998 names_zmm = intel_names_zmm;
11999 index64 = intel_index64;
12000 index32 = intel_index32;
12001 names_mask = intel_names_mask;
12002 index16 = intel_index16;
12005 separator_char = '+';
12010 names64 = att_names64;
12011 names32 = att_names32;
12012 names16 = att_names16;
12013 names8 = att_names8;
12014 names8rex = att_names8rex;
12015 names_seg = att_names_seg;
12016 names_mm = att_names_mm;
12017 names_bnd = att_names_bnd;
12018 names_xmm = att_names_xmm;
12019 names_ymm = att_names_ymm;
12020 names_zmm = att_names_zmm;
12021 index64 = att_index64;
12022 index32 = att_index32;
12023 names_mask = att_names_mask;
12024 index16 = att_index16;
12027 separator_char = ',';
12031 /* The output looks better if we put 7 bytes on a line, since that
12032 puts most long word instructions on a single line. Use 8 bytes
12034 if ((info->mach & bfd_mach_l1om) != 0)
12035 info->bytes_per_line = 8;
12037 info->bytes_per_line = 7;
12039 info->private_data = &priv;
12040 priv.max_fetched = priv.the_buffer;
12041 priv.insn_start = pc;
12044 for (i = 0; i < MAX_OPERANDS; ++i)
12052 start_codep = priv.the_buffer;
12053 codep = priv.the_buffer;
12055 if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12059 /* Getting here means we tried for data but didn't get it. That
12060 means we have an incomplete instruction of some sort. Just
12061 print the first byte as a prefix or a .byte pseudo-op. */
12062 if (codep > priv.the_buffer)
12064 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12066 (*info->fprintf_func) (info->stream, "%s", name);
12069 /* Just print the first byte as a .byte instruction. */
12070 (*info->fprintf_func) (info->stream, ".byte 0x%x",
12071 (unsigned int) priv.the_buffer[0]);
12081 sizeflag = priv.orig_sizeflag;
12083 if (!ckprefix () || rex_used)
12085 /* Too many prefixes or unused REX prefixes. */
12087 i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12089 (*info->fprintf_func) (info->stream, "%s%s",
12091 prefix_name (all_prefixes[i], sizeflag));
12095 insn_codep = codep;
12097 FETCH_DATA (info, codep + 1);
12098 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12100 if (((prefixes & PREFIX_FWAIT)
12101 && ((*codep < 0xd8) || (*codep > 0xdf))))
12103 /* Handle prefixes before fwait. */
12104 for (i = 0; i < fwait_prefix && all_prefixes[i];
12106 (*info->fprintf_func) (info->stream, "%s ",
12107 prefix_name (all_prefixes[i], sizeflag));
12108 (*info->fprintf_func) (info->stream, "fwait");
12112 if (*codep == 0x0f)
12114 unsigned char threebyte;
12117 FETCH_DATA (info, codep + 1);
12118 threebyte = *codep;
12119 dp = &dis386_twobyte[threebyte];
12120 need_modrm = twobyte_has_modrm[*codep];
12125 dp = &dis386[*codep];
12126 need_modrm = onebyte_has_modrm[*codep];
12130 /* Save sizeflag for printing the extra prefixes later before updating
12131 it for mnemonic and operand processing. The prefix names depend
12132 only on the address mode. */
12133 orig_sizeflag = sizeflag;
12134 if (prefixes & PREFIX_ADDR)
12136 if ((prefixes & PREFIX_DATA))
12142 FETCH_DATA (info, codep + 1);
12143 modrm.mod = (*codep >> 6) & 3;
12144 modrm.reg = (*codep >> 3) & 7;
12145 modrm.rm = *codep & 7;
12151 memset (&vex, 0, sizeof (vex));
12153 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12155 get_sib (info, sizeflag);
12156 dofloat (sizeflag);
12160 dp = get_valid_dis386 (dp, info);
12161 if (dp != NULL && putop (dp->name, sizeflag) == 0)
12163 get_sib (info, sizeflag);
12164 for (i = 0; i < MAX_OPERANDS; ++i)
12167 op_ad = MAX_OPERANDS - 1 - i;
12169 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12170 /* For EVEX instruction after the last operand masking
12171 should be printed. */
12172 if (i == 0 && vex.evex)
12174 /* Don't print {%k0}. */
12175 if (vex.mask_register_specifier)
12178 oappend (names_mask[vex.mask_register_specifier]);
12188 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12189 are all 0s in inverted form. */
12190 if (need_vex && vex.register_specifier != 0)
12192 (*info->fprintf_func) (info->stream, "(bad)");
12193 return end_codep - priv.the_buffer;
12196 /* Check if the REX prefix is used. */
12197 if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
12198 all_prefixes[last_rex_prefix] = 0;
12200 /* Check if the SEG prefix is used. */
12201 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12202 | PREFIX_FS | PREFIX_GS)) != 0
12203 && (used_prefixes & active_seg_prefix) != 0)
12204 all_prefixes[last_seg_prefix] = 0;
12206 /* Check if the ADDR prefix is used. */
12207 if ((prefixes & PREFIX_ADDR) != 0
12208 && (used_prefixes & PREFIX_ADDR) != 0)
12209 all_prefixes[last_addr_prefix] = 0;
12211 /* Check if the DATA prefix is used. */
12212 if ((prefixes & PREFIX_DATA) != 0
12213 && (used_prefixes & PREFIX_DATA) != 0)
12214 all_prefixes[last_data_prefix] = 0;
12216 /* Print the extra prefixes. */
12218 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12219 if (all_prefixes[i])
12222 name = prefix_name (all_prefixes[i], orig_sizeflag);
12225 prefix_length += strlen (name) + 1;
12226 (*info->fprintf_func) (info->stream, "%s ", name);
12229 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12230 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
12231 used by putop and MMX/SSE operand and may be overriden by the
12232 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12234 if (dp->prefix_requirement == PREFIX_OPCODE
12235 && dp != &bad_opcode
12237 & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
12239 & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12241 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12243 && (used_prefixes & PREFIX_DATA) == 0))))
12245 (*info->fprintf_func) (info->stream, "(bad)");
12246 return end_codep - priv.the_buffer;
12249 /* Check maximum code length. */
12250 if ((codep - start_codep) > MAX_CODE_LENGTH)
12252 (*info->fprintf_func) (info->stream, "(bad)");
12253 return MAX_CODE_LENGTH;
12256 obufp = mnemonicendp;
12257 for (i = strlen (obuf) + prefix_length; i < 6; i++)
12260 (*info->fprintf_func) (info->stream, "%s", obuf);
12262 /* The enter and bound instructions are printed with operands in the same
12263 order as the intel book; everything else is printed in reverse order. */
12264 if (intel_syntax || two_source_ops)
12268 for (i = 0; i < MAX_OPERANDS; ++i)
12269 op_txt[i] = op_out[i];
12271 if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12272 && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12274 op_txt[2] = op_out[3];
12275 op_txt[3] = op_out[2];
12278 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12280 op_ad = op_index[i];
12281 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12282 op_index[MAX_OPERANDS - 1 - i] = op_ad;
12283 riprel = op_riprel[i];
12284 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12285 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12290 for (i = 0; i < MAX_OPERANDS; ++i)
12291 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12295 for (i = 0; i < MAX_OPERANDS; ++i)
12299 (*info->fprintf_func) (info->stream, ",");
12300 if (op_index[i] != -1 && !op_riprel[i])
12301 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
12303 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12307 for (i = 0; i < MAX_OPERANDS; i++)
12308 if (op_index[i] != -1 && op_riprel[i])
12310 (*info->fprintf_func) (info->stream, " # ");
12311 (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12312 + op_address[op_index[i]]), info);
12315 return codep - priv.the_buffer;
12318 static const char *float_mem[] = {
12393 static const unsigned char float_mem_mode[] = {
12468 #define ST { OP_ST, 0 }
12469 #define STi { OP_STi, 0 }
12471 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12472 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12473 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12474 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12475 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12476 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12477 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12478 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12479 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12481 static const struct dis386 float_reg[][8] = {
12484 { "fadd", { ST, STi }, 0 },
12485 { "fmul", { ST, STi }, 0 },
12486 { "fcom", { STi }, 0 },
12487 { "fcomp", { STi }, 0 },
12488 { "fsub", { ST, STi }, 0 },
12489 { "fsubr", { ST, STi }, 0 },
12490 { "fdiv", { ST, STi }, 0 },
12491 { "fdivr", { ST, STi }, 0 },
12495 { "fld", { STi }, 0 },
12496 { "fxch", { STi }, 0 },
12506 { "fcmovb", { ST, STi }, 0 },
12507 { "fcmove", { ST, STi }, 0 },
12508 { "fcmovbe",{ ST, STi }, 0 },
12509 { "fcmovu", { ST, STi }, 0 },
12517 { "fcmovnb",{ ST, STi }, 0 },
12518 { "fcmovne",{ ST, STi }, 0 },
12519 { "fcmovnbe",{ ST, STi }, 0 },
12520 { "fcmovnu",{ ST, STi }, 0 },
12522 { "fucomi", { ST, STi }, 0 },
12523 { "fcomi", { ST, STi }, 0 },
12528 { "fadd", { STi, ST }, 0 },
12529 { "fmul", { STi, ST }, 0 },
12532 { "fsub{!M|r}", { STi, ST }, 0 },
12533 { "fsub{M|}", { STi, ST }, 0 },
12534 { "fdiv{!M|r}", { STi, ST }, 0 },
12535 { "fdiv{M|}", { STi, ST }, 0 },
12539 { "ffree", { STi }, 0 },
12541 { "fst", { STi }, 0 },
12542 { "fstp", { STi }, 0 },
12543 { "fucom", { STi }, 0 },
12544 { "fucomp", { STi }, 0 },
12550 { "faddp", { STi, ST }, 0 },
12551 { "fmulp", { STi, ST }, 0 },
12554 { "fsub{!M|r}p", { STi, ST }, 0 },
12555 { "fsub{M|}p", { STi, ST }, 0 },
12556 { "fdiv{!M|r}p", { STi, ST }, 0 },
12557 { "fdiv{M|}p", { STi, ST }, 0 },
12561 { "ffreep", { STi }, 0 },
12566 { "fucomip", { ST, STi }, 0 },
12567 { "fcomip", { ST, STi }, 0 },
12572 static char *fgrps[][8] = {
12575 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12580 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12585 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12590 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12595 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12600 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12605 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12610 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12611 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12616 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12621 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12626 swap_operand (void)
12628 mnemonicendp[0] = '.';
12629 mnemonicendp[1] = 's';
12634 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12635 int sizeflag ATTRIBUTE_UNUSED)
12637 /* Skip mod/rm byte. */
12643 dofloat (int sizeflag)
12645 const struct dis386 *dp;
12646 unsigned char floatop;
12648 floatop = codep[-1];
12650 if (modrm.mod != 3)
12652 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12654 putop (float_mem[fp_indx], sizeflag);
12657 OP_E (float_mem_mode[fp_indx], sizeflag);
12660 /* Skip mod/rm byte. */
12664 dp = &float_reg[floatop - 0xd8][modrm.reg];
12665 if (dp->name == NULL)
12667 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12669 /* Instruction fnstsw is only one with strange arg. */
12670 if (floatop == 0xdf && codep[-1] == 0xe0)
12671 strcpy (op_out[0], names16[0]);
12675 putop (dp->name, sizeflag);
12680 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12685 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12689 /* Like oappend (below), but S is a string starting with '%'.
12690 In Intel syntax, the '%' is elided. */
12692 oappend_maybe_intel (const char *s)
12694 oappend (s + intel_syntax);
12698 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12700 oappend_maybe_intel ("%st");
12704 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12706 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12707 oappend_maybe_intel (scratchbuf);
12710 /* Capital letters in template are macros. */
12712 putop (const char *in_template, int sizeflag)
12717 unsigned int l = 0, len = 1;
12720 #define SAVE_LAST(c) \
12721 if (l < len && l < sizeof (last)) \
12726 for (p = in_template; *p; p++)
12742 while (*++p != '|')
12743 if (*p == '}' || *p == '\0')
12746 /* Fall through. */
12751 while (*++p != '}')
12762 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12766 if (l == 0 && len == 1)
12771 if (sizeflag & SUFFIX_ALWAYS)
12784 if (address_mode == mode_64bit
12785 && !(prefixes & PREFIX_ADDR))
12796 if (intel_syntax && !alt)
12798 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12800 if (sizeflag & DFLAG)
12801 *obufp++ = intel_syntax ? 'd' : 'l';
12803 *obufp++ = intel_syntax ? 'w' : 's';
12804 used_prefixes |= (prefixes & PREFIX_DATA);
12808 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12811 if (modrm.mod == 3)
12817 if (sizeflag & DFLAG)
12818 *obufp++ = intel_syntax ? 'd' : 'l';
12821 used_prefixes |= (prefixes & PREFIX_DATA);
12827 case 'E': /* For jcxz/jecxz */
12828 if (address_mode == mode_64bit)
12830 if (sizeflag & AFLAG)
12836 if (sizeflag & AFLAG)
12838 used_prefixes |= (prefixes & PREFIX_ADDR);
12843 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12845 if (sizeflag & AFLAG)
12846 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12848 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12849 used_prefixes |= (prefixes & PREFIX_ADDR);
12853 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12855 if ((rex & REX_W) || (sizeflag & DFLAG))
12859 if (!(rex & REX_W))
12860 used_prefixes |= (prefixes & PREFIX_DATA);
12865 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12866 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12868 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12871 if (prefixes & PREFIX_DS)
12890 if (l != 0 || len != 1)
12892 if (l != 1 || len != 2 || last[0] != 'X')
12897 if (!need_vex || !vex.evex)
12900 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
12902 switch (vex.length)
12920 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12925 /* Fall through. */
12928 if (l != 0 || len != 1)
12936 if (sizeflag & SUFFIX_ALWAYS)
12940 if (intel_mnemonic != cond)
12944 if ((prefixes & PREFIX_FWAIT) == 0)
12947 used_prefixes |= PREFIX_FWAIT;
12953 else if (intel_syntax && (sizeflag & DFLAG))
12957 if (!(rex & REX_W))
12958 used_prefixes |= (prefixes & PREFIX_DATA);
12962 && address_mode == mode_64bit
12963 && isa64 == intel64)
12968 /* Fall through. */
12971 && address_mode == mode_64bit
12972 && ((sizeflag & DFLAG) || (rex & REX_W)))
12977 /* Fall through. */
12980 if (l == 0 && len == 1)
12985 if ((rex & REX_W) == 0
12986 && (prefixes & PREFIX_DATA))
12988 if ((sizeflag & DFLAG) == 0)
12990 used_prefixes |= (prefixes & PREFIX_DATA);
12994 if ((prefixes & PREFIX_DATA)
12996 || (sizeflag & SUFFIX_ALWAYS))
13003 if (sizeflag & DFLAG)
13007 used_prefixes |= (prefixes & PREFIX_DATA);
13013 if (l != 1 || len != 2 || last[0] != 'L')
13019 if ((prefixes & PREFIX_DATA)
13021 || (sizeflag & SUFFIX_ALWAYS))
13028 if (sizeflag & DFLAG)
13029 *obufp++ = intel_syntax ? 'd' : 'l';
13032 used_prefixes |= (prefixes & PREFIX_DATA);
13040 if (address_mode == mode_64bit
13041 && ((sizeflag & DFLAG) || (rex & REX_W)))
13043 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13047 /* Fall through. */
13050 if (l == 0 && len == 1)
13053 if (intel_syntax && !alt)
13056 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13062 if (sizeflag & DFLAG)
13063 *obufp++ = intel_syntax ? 'd' : 'l';
13066 used_prefixes |= (prefixes & PREFIX_DATA);
13072 if (l != 1 || len != 2 || last[0] != 'L')
13078 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13093 else if (sizeflag & DFLAG)
13102 if (intel_syntax && !p[1]
13103 && ((rex & REX_W) || (sizeflag & DFLAG)))
13105 if (!(rex & REX_W))
13106 used_prefixes |= (prefixes & PREFIX_DATA);
13109 if (l == 0 && len == 1)
13113 if (address_mode == mode_64bit
13114 && ((sizeflag & DFLAG) || (rex & REX_W)))
13116 if (sizeflag & SUFFIX_ALWAYS)
13138 /* Fall through. */
13141 if (l == 0 && len == 1)
13146 if (sizeflag & SUFFIX_ALWAYS)
13152 if (sizeflag & DFLAG)
13156 used_prefixes |= (prefixes & PREFIX_DATA);
13170 if (address_mode == mode_64bit
13171 && !(prefixes & PREFIX_ADDR))
13182 if (l != 0 || len != 1)
13187 if (need_vex && vex.prefix)
13189 if (vex.prefix == DATA_PREFIX_OPCODE)
13196 if (prefixes & PREFIX_DATA)
13200 used_prefixes |= (prefixes & PREFIX_DATA);
13204 if (l == 0 && len == 1)
13208 if (l != 1 || len != 2 || last[0] != 'X')
13216 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13218 switch (vex.length)
13234 if (l == 0 && len == 1)
13236 /* operand size flag for cwtl, cbtw */
13245 else if (sizeflag & DFLAG)
13249 if (!(rex & REX_W))
13250 used_prefixes |= (prefixes & PREFIX_DATA);
13257 && last[0] != 'L'))
13264 if (last[0] == 'X')
13265 *obufp++ = vex.w ? 'd': 's';
13267 *obufp++ = vex.w ? 'q': 'd';
13273 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13275 if (sizeflag & DFLAG)
13279 used_prefixes |= (prefixes & PREFIX_DATA);
13285 if (address_mode == mode_64bit
13286 && (isa64 == intel64
13287 || ((sizeflag & DFLAG) || (rex & REX_W))))
13289 else if ((prefixes & PREFIX_DATA))
13291 if (!(sizeflag & DFLAG))
13293 used_prefixes |= (prefixes & PREFIX_DATA);
13300 mnemonicendp = obufp;
13305 oappend (const char *s)
13307 obufp = stpcpy (obufp, s);
13313 /* Only print the active segment register. */
13314 if (!active_seg_prefix)
13317 used_prefixes |= active_seg_prefix;
13318 switch (active_seg_prefix)
13321 oappend_maybe_intel ("%cs:");
13324 oappend_maybe_intel ("%ds:");
13327 oappend_maybe_intel ("%ss:");
13330 oappend_maybe_intel ("%es:");
13333 oappend_maybe_intel ("%fs:");
13336 oappend_maybe_intel ("%gs:");
13344 OP_indirE (int bytemode, int sizeflag)
13348 OP_E (bytemode, sizeflag);
13352 print_operand_value (char *buf, int hex, bfd_vma disp)
13354 if (address_mode == mode_64bit)
13362 sprintf_vma (tmp, disp);
13363 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13364 strcpy (buf + 2, tmp + i);
13368 bfd_signed_vma v = disp;
13375 /* Check for possible overflow on 0x8000000000000000. */
13378 strcpy (buf, "9223372036854775808");
13392 tmp[28 - i] = (v % 10) + '0';
13396 strcpy (buf, tmp + 29 - i);
13402 sprintf (buf, "0x%x", (unsigned int) disp);
13404 sprintf (buf, "%d", (int) disp);
13408 /* Put DISP in BUF as signed hex number. */
13411 print_displacement (char *buf, bfd_vma disp)
13413 bfd_signed_vma val = disp;
13422 /* Check for possible overflow. */
13425 switch (address_mode)
13428 strcpy (buf + j, "0x8000000000000000");
13431 strcpy (buf + j, "0x80000000");
13434 strcpy (buf + j, "0x8000");
13444 sprintf_vma (tmp, (bfd_vma) val);
13445 for (i = 0; tmp[i] == '0'; i++)
13447 if (tmp[i] == '\0')
13449 strcpy (buf + j, tmp + i);
13453 intel_operand_size (int bytemode, int sizeflag)
13457 && (bytemode == x_mode
13458 || bytemode == evex_half_bcst_xmmq_mode))
13461 oappend ("QWORD PTR ");
13463 oappend ("DWORD PTR ");
13472 oappend ("BYTE PTR ");
13477 oappend ("WORD PTR ");
13480 if (address_mode == mode_64bit && isa64 == intel64)
13482 oappend ("QWORD PTR ");
13485 /* Fall through. */
13487 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13489 oappend ("QWORD PTR ");
13492 /* Fall through. */
13498 oappend ("QWORD PTR ");
13501 if ((sizeflag & DFLAG) || bytemode == dq_mode)
13502 oappend ("DWORD PTR ");
13504 oappend ("WORD PTR ");
13505 used_prefixes |= (prefixes & PREFIX_DATA);
13509 if ((rex & REX_W) || (sizeflag & DFLAG))
13511 oappend ("WORD PTR ");
13512 if (!(rex & REX_W))
13513 used_prefixes |= (prefixes & PREFIX_DATA);
13516 if (sizeflag & DFLAG)
13517 oappend ("QWORD PTR ");
13519 oappend ("DWORD PTR ");
13520 used_prefixes |= (prefixes & PREFIX_DATA);
13523 case d_scalar_mode:
13524 case d_scalar_swap_mode:
13527 oappend ("DWORD PTR ");
13530 case q_scalar_mode:
13531 case q_scalar_swap_mode:
13533 oappend ("QWORD PTR ");
13537 if (address_mode == mode_64bit)
13538 oappend ("QWORD PTR ");
13540 oappend ("DWORD PTR ");
13543 if (sizeflag & DFLAG)
13544 oappend ("FWORD PTR ");
13546 oappend ("DWORD PTR ");
13547 used_prefixes |= (prefixes & PREFIX_DATA);
13550 oappend ("TBYTE PTR ");
13554 case evex_x_gscat_mode:
13555 case evex_x_nobcst_mode:
13556 case b_scalar_mode:
13557 case w_scalar_mode:
13560 switch (vex.length)
13563 oappend ("XMMWORD PTR ");
13566 oappend ("YMMWORD PTR ");
13569 oappend ("ZMMWORD PTR ");
13576 oappend ("XMMWORD PTR ");
13579 oappend ("XMMWORD PTR ");
13582 oappend ("YMMWORD PTR ");
13585 case evex_half_bcst_xmmq_mode:
13589 switch (vex.length)
13592 oappend ("QWORD PTR ");
13595 oappend ("XMMWORD PTR ");
13598 oappend ("YMMWORD PTR ");
13608 switch (vex.length)
13613 oappend ("BYTE PTR ");
13623 switch (vex.length)
13628 oappend ("WORD PTR ");
13638 switch (vex.length)
13643 oappend ("DWORD PTR ");
13653 switch (vex.length)
13658 oappend ("QWORD PTR ");
13668 switch (vex.length)
13671 oappend ("WORD PTR ");
13674 oappend ("DWORD PTR ");
13677 oappend ("QWORD PTR ");
13687 switch (vex.length)
13690 oappend ("DWORD PTR ");
13693 oappend ("QWORD PTR ");
13696 oappend ("XMMWORD PTR ");
13706 switch (vex.length)
13709 oappend ("QWORD PTR ");
13712 oappend ("YMMWORD PTR ");
13715 oappend ("ZMMWORD PTR ");
13725 switch (vex.length)
13729 oappend ("XMMWORD PTR ");
13736 oappend ("OWORD PTR ");
13739 case vex_w_dq_mode:
13740 case vex_scalar_w_dq_mode:
13745 oappend ("QWORD PTR ");
13747 oappend ("DWORD PTR ");
13749 case vex_vsib_d_w_dq_mode:
13750 case vex_vsib_q_w_dq_mode:
13757 oappend ("QWORD PTR ");
13759 oappend ("DWORD PTR ");
13763 switch (vex.length)
13766 oappend ("XMMWORD PTR ");
13769 oappend ("YMMWORD PTR ");
13772 oappend ("ZMMWORD PTR ");
13779 case vex_vsib_q_w_d_mode:
13780 case vex_vsib_d_w_d_mode:
13781 if (!need_vex || !vex.evex)
13784 switch (vex.length)
13787 oappend ("QWORD PTR ");
13790 oappend ("XMMWORD PTR ");
13793 oappend ("YMMWORD PTR ");
13801 if (!need_vex || vex.length != 128)
13804 oappend ("DWORD PTR ");
13806 oappend ("BYTE PTR ");
13812 oappend ("QWORD PTR ");
13814 oappend ("WORD PTR ");
13824 OP_E_register (int bytemode, int sizeflag)
13826 int reg = modrm.rm;
13827 const char **names;
13833 if ((sizeflag & SUFFIX_ALWAYS)
13834 && (bytemode == b_swap_mode
13835 || bytemode == bnd_swap_mode
13836 || bytemode == v_swap_mode))
13862 names = address_mode == mode_64bit ? names64 : names32;
13865 case bnd_swap_mode:
13874 if (address_mode == mode_64bit && isa64 == intel64)
13879 /* Fall through. */
13881 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13887 /* Fall through. */
13900 if ((sizeflag & DFLAG)
13901 || (bytemode != v_mode
13902 && bytemode != v_swap_mode))
13906 used_prefixes |= (prefixes & PREFIX_DATA);
13910 names = (address_mode == mode_64bit
13911 ? names64 : names32);
13912 if (!(prefixes & PREFIX_ADDR))
13913 names = (address_mode == mode_16bit
13914 ? names16 : names);
13917 /* Remove "addr16/addr32". */
13918 all_prefixes[last_addr_prefix] = 0;
13919 names = (address_mode != mode_32bit
13920 ? names32 : names16);
13921 used_prefixes |= PREFIX_ADDR;
13931 names = names_mask;
13936 oappend (INTERNAL_DISASSEMBLER_ERROR);
13939 oappend (names[reg]);
13943 OP_E_memory (int bytemode, int sizeflag)
13946 int add = (rex & REX_B) ? 8 : 0;
13952 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
13954 && bytemode != x_mode
13955 && bytemode != xmmq_mode
13956 && bytemode != evex_half_bcst_xmmq_mode)
13972 if (address_mode != mode_64bit)
13978 case vex_vsib_d_w_dq_mode:
13979 case vex_vsib_d_w_d_mode:
13980 case vex_vsib_q_w_dq_mode:
13981 case vex_vsib_q_w_d_mode:
13982 case evex_x_gscat_mode:
13984 shift = vex.w ? 3 : 2;
13987 case evex_half_bcst_xmmq_mode:
13991 shift = vex.w ? 3 : 2;
13994 /* Fall through. */
13998 case evex_x_nobcst_mode:
14000 switch (vex.length)
14023 case q_scalar_mode:
14025 case q_scalar_swap_mode:
14031 case d_scalar_mode:
14033 case d_scalar_swap_mode:
14036 case w_scalar_mode:
14040 case b_scalar_mode:
14045 shift = address_mode == mode_64bit ? 3 : 2;
14050 /* Make necessary corrections to shift for modes that need it.
14051 For these modes we currently have shift 4, 5 or 6 depending on
14052 vex.length (it corresponds to xmmword, ymmword or zmmword
14053 operand). We might want to make it 3, 4 or 5 (e.g. for
14054 xmmq_mode). In case of broadcast enabled the corrections
14055 aren't needed, as element size is always 32 or 64 bits. */
14057 && (bytemode == xmmq_mode
14058 || bytemode == evex_half_bcst_xmmq_mode))
14060 else if (bytemode == xmmqd_mode)
14062 else if (bytemode == xmmdw_mode)
14064 else if (bytemode == ymmq_mode && vex.length == 128)
14072 intel_operand_size (bytemode, sizeflag);
14075 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14077 /* 32/64 bit address mode */
14087 int addr32flag = !((sizeflag & AFLAG)
14088 || bytemode == v_bnd_mode
14089 || bytemode == v_bndmk_mode
14090 || bytemode == bnd_mode
14091 || bytemode == bnd_swap_mode);
14092 const char **indexes64 = names64;
14093 const char **indexes32 = names32;
14103 vindex = sib.index;
14109 case vex_vsib_d_w_dq_mode:
14110 case vex_vsib_d_w_d_mode:
14111 case vex_vsib_q_w_dq_mode:
14112 case vex_vsib_q_w_d_mode:
14122 switch (vex.length)
14125 indexes64 = indexes32 = names_xmm;
14129 || bytemode == vex_vsib_q_w_dq_mode
14130 || bytemode == vex_vsib_q_w_d_mode)
14131 indexes64 = indexes32 = names_ymm;
14133 indexes64 = indexes32 = names_xmm;
14137 || bytemode == vex_vsib_q_w_dq_mode
14138 || bytemode == vex_vsib_q_w_d_mode)
14139 indexes64 = indexes32 = names_zmm;
14141 indexes64 = indexes32 = names_ymm;
14148 haveindex = vindex != 4;
14155 rbase = base + add;
14163 if (address_mode == mode_64bit && !havesib)
14166 if (riprel && bytemode == v_bndmk_mode)
14174 FETCH_DATA (the_info, codep + 1);
14176 if ((disp & 0x80) != 0)
14178 if (vex.evex && shift > 0)
14191 && address_mode != mode_16bit)
14193 if (address_mode == mode_64bit)
14195 /* Display eiz instead of addr32. */
14196 needindex = addr32flag;
14201 /* In 32-bit mode, we need index register to tell [offset]
14202 from [eiz*1 + offset]. */
14207 havedisp = (havebase
14209 || (havesib && (haveindex || scale != 0)));
14212 if (modrm.mod != 0 || base == 5)
14214 if (havedisp || riprel)
14215 print_displacement (scratchbuf, disp);
14217 print_operand_value (scratchbuf, 1, disp);
14218 oappend (scratchbuf);
14222 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14226 if ((havebase || haveindex || needaddr32 || riprel)
14227 && (bytemode != v_bnd_mode)
14228 && (bytemode != v_bndmk_mode)
14229 && (bytemode != bnd_mode)
14230 && (bytemode != bnd_swap_mode))
14231 used_prefixes |= PREFIX_ADDR;
14233 if (havedisp || (intel_syntax && riprel))
14235 *obufp++ = open_char;
14236 if (intel_syntax && riprel)
14239 oappend (!addr32flag ? "rip" : "eip");
14243 oappend (address_mode == mode_64bit && !addr32flag
14244 ? names64[rbase] : names32[rbase]);
14247 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
14248 print index to tell base + index from base. */
14252 || (havebase && base != ESP_REG_NUM))
14254 if (!intel_syntax || havebase)
14256 *obufp++ = separator_char;
14260 oappend (address_mode == mode_64bit && !addr32flag
14261 ? indexes64[vindex] : indexes32[vindex]);
14263 oappend (address_mode == mode_64bit && !addr32flag
14264 ? index64 : index32);
14266 *obufp++ = scale_char;
14268 sprintf (scratchbuf, "%d", 1 << scale);
14269 oappend (scratchbuf);
14273 && (disp || modrm.mod != 0 || base == 5))
14275 if (!havedisp || (bfd_signed_vma) disp >= 0)
14280 else if (modrm.mod != 1 && disp != -disp)
14284 disp = - (bfd_signed_vma) disp;
14288 print_displacement (scratchbuf, disp);
14290 print_operand_value (scratchbuf, 1, disp);
14291 oappend (scratchbuf);
14294 *obufp++ = close_char;
14297 else if (intel_syntax)
14299 if (modrm.mod != 0 || base == 5)
14301 if (!active_seg_prefix)
14303 oappend (names_seg[ds_reg - es_reg]);
14306 print_operand_value (scratchbuf, 1, disp);
14307 oappend (scratchbuf);
14313 /* 16 bit address mode */
14314 used_prefixes |= prefixes & PREFIX_ADDR;
14321 if ((disp & 0x8000) != 0)
14326 FETCH_DATA (the_info, codep + 1);
14328 if ((disp & 0x80) != 0)
14330 if (vex.evex && shift > 0)
14335 if ((disp & 0x8000) != 0)
14341 if (modrm.mod != 0 || modrm.rm == 6)
14343 print_displacement (scratchbuf, disp);
14344 oappend (scratchbuf);
14347 if (modrm.mod != 0 || modrm.rm != 6)
14349 *obufp++ = open_char;
14351 oappend (index16[modrm.rm]);
14353 && (disp || modrm.mod != 0 || modrm.rm == 6))
14355 if ((bfd_signed_vma) disp >= 0)
14360 else if (modrm.mod != 1)
14364 disp = - (bfd_signed_vma) disp;
14367 print_displacement (scratchbuf, disp);
14368 oappend (scratchbuf);
14371 *obufp++ = close_char;
14374 else if (intel_syntax)
14376 if (!active_seg_prefix)
14378 oappend (names_seg[ds_reg - es_reg]);
14381 print_operand_value (scratchbuf, 1, disp & 0xffff);
14382 oappend (scratchbuf);
14385 if (vex.evex && vex.b
14386 && (bytemode == x_mode
14387 || bytemode == xmmq_mode
14388 || bytemode == evex_half_bcst_xmmq_mode))
14391 || bytemode == xmmq_mode
14392 || bytemode == evex_half_bcst_xmmq_mode)
14394 switch (vex.length)
14397 oappend ("{1to2}");
14400 oappend ("{1to4}");
14403 oappend ("{1to8}");
14411 switch (vex.length)
14414 oappend ("{1to4}");
14417 oappend ("{1to8}");
14420 oappend ("{1to16}");
14430 OP_E (int bytemode, int sizeflag)
14432 /* Skip mod/rm byte. */
14436 if (modrm.mod == 3)
14437 OP_E_register (bytemode, sizeflag);
14439 OP_E_memory (bytemode, sizeflag);
14443 OP_G (int bytemode, int sizeflag)
14446 const char **names;
14455 oappend (names8rex[modrm.reg + add]);
14457 oappend (names8[modrm.reg + add]);
14460 oappend (names16[modrm.reg + add]);
14465 oappend (names32[modrm.reg + add]);
14468 oappend (names64[modrm.reg + add]);
14471 if (modrm.reg > 0x3)
14476 oappend (names_bnd[modrm.reg]);
14485 oappend (names64[modrm.reg + add]);
14488 if ((sizeflag & DFLAG) || bytemode != v_mode)
14489 oappend (names32[modrm.reg + add]);
14491 oappend (names16[modrm.reg + add]);
14492 used_prefixes |= (prefixes & PREFIX_DATA);
14496 names = (address_mode == mode_64bit
14497 ? names64 : names32);
14498 if (!(prefixes & PREFIX_ADDR))
14500 if (address_mode == mode_16bit)
14505 /* Remove "addr16/addr32". */
14506 all_prefixes[last_addr_prefix] = 0;
14507 names = (address_mode != mode_32bit
14508 ? names32 : names16);
14509 used_prefixes |= PREFIX_ADDR;
14511 oappend (names[modrm.reg + add]);
14514 if (address_mode == mode_64bit)
14515 oappend (names64[modrm.reg + add]);
14517 oappend (names32[modrm.reg + add]);
14521 if ((modrm.reg + add) > 0x7)
14526 oappend (names_mask[modrm.reg + add]);
14529 oappend (INTERNAL_DISASSEMBLER_ERROR);
14542 FETCH_DATA (the_info, codep + 8);
14543 a = *codep++ & 0xff;
14544 a |= (*codep++ & 0xff) << 8;
14545 a |= (*codep++ & 0xff) << 16;
14546 a |= (*codep++ & 0xffu) << 24;
14547 b = *codep++ & 0xff;
14548 b |= (*codep++ & 0xff) << 8;
14549 b |= (*codep++ & 0xff) << 16;
14550 b |= (*codep++ & 0xffu) << 24;
14551 x = a + ((bfd_vma) b << 32);
14559 static bfd_signed_vma
14562 bfd_signed_vma x = 0;
14564 FETCH_DATA (the_info, codep + 4);
14565 x = *codep++ & (bfd_signed_vma) 0xff;
14566 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14567 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14568 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14572 static bfd_signed_vma
14575 bfd_signed_vma x = 0;
14577 FETCH_DATA (the_info, codep + 4);
14578 x = *codep++ & (bfd_signed_vma) 0xff;
14579 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14580 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14581 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14583 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14593 FETCH_DATA (the_info, codep + 2);
14594 x = *codep++ & 0xff;
14595 x |= (*codep++ & 0xff) << 8;
14600 set_op (bfd_vma op, int riprel)
14602 op_index[op_ad] = op_ad;
14603 if (address_mode == mode_64bit)
14605 op_address[op_ad] = op;
14606 op_riprel[op_ad] = riprel;
14610 /* Mask to get a 32-bit address. */
14611 op_address[op_ad] = op & 0xffffffff;
14612 op_riprel[op_ad] = riprel & 0xffffffff;
14617 OP_REG (int code, int sizeflag)
14624 case es_reg: case ss_reg: case cs_reg:
14625 case ds_reg: case fs_reg: case gs_reg:
14626 oappend (names_seg[code - es_reg]);
14638 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14639 case sp_reg: case bp_reg: case si_reg: case di_reg:
14640 s = names16[code - ax_reg + add];
14642 case al_reg: case ah_reg: case cl_reg: case ch_reg:
14643 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14646 s = names8rex[code - al_reg + add];
14648 s = names8[code - al_reg];
14650 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14651 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14652 if (address_mode == mode_64bit
14653 && ((sizeflag & DFLAG) || (rex & REX_W)))
14655 s = names64[code - rAX_reg + add];
14658 code += eAX_reg - rAX_reg;
14659 /* Fall through. */
14660 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14661 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14664 s = names64[code - eAX_reg + add];
14667 if (sizeflag & DFLAG)
14668 s = names32[code - eAX_reg + add];
14670 s = names16[code - eAX_reg + add];
14671 used_prefixes |= (prefixes & PREFIX_DATA);
14675 s = INTERNAL_DISASSEMBLER_ERROR;
14682 OP_IMREG (int code, int sizeflag)
14694 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14695 case sp_reg: case bp_reg: case si_reg: case di_reg:
14696 s = names16[code - ax_reg];
14698 case es_reg: case ss_reg: case cs_reg:
14699 case ds_reg: case fs_reg: case gs_reg:
14700 s = names_seg[code - es_reg];
14702 case al_reg: case ah_reg: case cl_reg: case ch_reg:
14703 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14706 s = names8rex[code - al_reg];
14708 s = names8[code - al_reg];
14710 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14711 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14714 s = names64[code - eAX_reg];
14717 if (sizeflag & DFLAG)
14718 s = names32[code - eAX_reg];
14720 s = names16[code - eAX_reg];
14721 used_prefixes |= (prefixes & PREFIX_DATA);
14724 case z_mode_ax_reg:
14725 if ((rex & REX_W) || (sizeflag & DFLAG))
14729 if (!(rex & REX_W))
14730 used_prefixes |= (prefixes & PREFIX_DATA);
14733 s = INTERNAL_DISASSEMBLER_ERROR;
14740 OP_I (int bytemode, int sizeflag)
14743 bfd_signed_vma mask = -1;
14748 FETCH_DATA (the_info, codep + 1);
14753 if (address_mode == mode_64bit)
14758 /* Fall through. */
14765 if (sizeflag & DFLAG)
14775 used_prefixes |= (prefixes & PREFIX_DATA);
14787 oappend (INTERNAL_DISASSEMBLER_ERROR);
14792 scratchbuf[0] = '$';
14793 print_operand_value (scratchbuf + 1, 1, op);
14794 oappend_maybe_intel (scratchbuf);
14795 scratchbuf[0] = '\0';
14799 OP_I64 (int bytemode, int sizeflag)
14802 bfd_signed_vma mask = -1;
14804 if (address_mode != mode_64bit)
14806 OP_I (bytemode, sizeflag);
14813 FETCH_DATA (the_info, codep + 1);
14823 if (sizeflag & DFLAG)
14833 used_prefixes |= (prefixes & PREFIX_DATA);
14841 oappend (INTERNAL_DISASSEMBLER_ERROR);
14846 scratchbuf[0] = '$';
14847 print_operand_value (scratchbuf + 1, 1, op);
14848 oappend_maybe_intel (scratchbuf);
14849 scratchbuf[0] = '\0';
14853 OP_sI (int bytemode, int sizeflag)
14861 FETCH_DATA (the_info, codep + 1);
14863 if ((op & 0x80) != 0)
14865 if (bytemode == b_T_mode)
14867 if (address_mode != mode_64bit
14868 || !((sizeflag & DFLAG) || (rex & REX_W)))
14870 /* The operand-size prefix is overridden by a REX prefix. */
14871 if ((sizeflag & DFLAG) || (rex & REX_W))
14879 if (!(rex & REX_W))
14881 if (sizeflag & DFLAG)
14889 /* The operand-size prefix is overridden by a REX prefix. */
14890 if ((sizeflag & DFLAG) || (rex & REX_W))
14896 oappend (INTERNAL_DISASSEMBLER_ERROR);
14900 scratchbuf[0] = '$';
14901 print_operand_value (scratchbuf + 1, 1, op);
14902 oappend_maybe_intel (scratchbuf);
14906 OP_J (int bytemode, int sizeflag)
14910 bfd_vma segment = 0;
14915 FETCH_DATA (the_info, codep + 1);
14917 if ((disp & 0x80) != 0)
14921 if (isa64 == amd64)
14923 if ((sizeflag & DFLAG)
14924 || (address_mode == mode_64bit
14925 && (isa64 != amd64 || (rex & REX_W))))
14930 if ((disp & 0x8000) != 0)
14932 /* In 16bit mode, address is wrapped around at 64k within
14933 the same segment. Otherwise, a data16 prefix on a jump
14934 instruction means that the pc is masked to 16 bits after
14935 the displacement is added! */
14937 if ((prefixes & PREFIX_DATA) == 0)
14938 segment = ((start_pc + (codep - start_codep))
14939 & ~((bfd_vma) 0xffff));
14941 if (address_mode != mode_64bit
14942 || (isa64 == amd64 && !(rex & REX_W)))
14943 used_prefixes |= (prefixes & PREFIX_DATA);
14946 oappend (INTERNAL_DISASSEMBLER_ERROR);
14949 disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
14951 print_operand_value (scratchbuf, 1, disp);
14952 oappend (scratchbuf);
14956 OP_SEG (int bytemode, int sizeflag)
14958 if (bytemode == w_mode)
14959 oappend (names_seg[modrm.reg]);
14961 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
14965 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
14969 if (sizeflag & DFLAG)
14979 used_prefixes |= (prefixes & PREFIX_DATA);
14981 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
14983 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
14984 oappend (scratchbuf);
14988 OP_OFF (int bytemode, int sizeflag)
14992 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14993 intel_operand_size (bytemode, sizeflag);
14996 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15003 if (!active_seg_prefix)
15005 oappend (names_seg[ds_reg - es_reg]);
15009 print_operand_value (scratchbuf, 1, off);
15010 oappend (scratchbuf);
15014 OP_OFF64 (int bytemode, int sizeflag)
15018 if (address_mode != mode_64bit
15019 || (prefixes & PREFIX_ADDR))
15021 OP_OFF (bytemode, sizeflag);
15025 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
15026 intel_operand_size (bytemode, sizeflag);
15033 if (!active_seg_prefix)
15035 oappend (names_seg[ds_reg - es_reg]);
15039 print_operand_value (scratchbuf, 1, off);
15040 oappend (scratchbuf);
15044 ptr_reg (int code, int sizeflag)
15048 *obufp++ = open_char;
15049 used_prefixes |= (prefixes & PREFIX_ADDR);
15050 if (address_mode == mode_64bit)
15052 if (!(sizeflag & AFLAG))
15053 s = names32[code - eAX_reg];
15055 s = names64[code - eAX_reg];
15057 else if (sizeflag & AFLAG)
15058 s = names32[code - eAX_reg];
15060 s = names16[code - eAX_reg];
15062 *obufp++ = close_char;
15067 OP_ESreg (int code, int sizeflag)
15073 case 0x6d: /* insw/insl */
15074 intel_operand_size (z_mode, sizeflag);
15076 case 0xa5: /* movsw/movsl/movsq */
15077 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15078 case 0xab: /* stosw/stosl */
15079 case 0xaf: /* scasw/scasl */
15080 intel_operand_size (v_mode, sizeflag);
15083 intel_operand_size (b_mode, sizeflag);
15086 oappend_maybe_intel ("%es:");
15087 ptr_reg (code, sizeflag);
15091 OP_DSreg (int code, int sizeflag)
15097 case 0x6f: /* outsw/outsl */
15098 intel_operand_size (z_mode, sizeflag);
15100 case 0xa5: /* movsw/movsl/movsq */
15101 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15102 case 0xad: /* lodsw/lodsl/lodsq */
15103 intel_operand_size (v_mode, sizeflag);
15106 intel_operand_size (b_mode, sizeflag);
15109 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15110 default segment register DS is printed. */
15111 if (!active_seg_prefix)
15112 active_seg_prefix = PREFIX_DS;
15114 ptr_reg (code, sizeflag);
15118 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15126 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15128 all_prefixes[last_lock_prefix] = 0;
15129 used_prefixes |= PREFIX_LOCK;
15134 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15135 oappend_maybe_intel (scratchbuf);
15139 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15148 sprintf (scratchbuf, "db%d", modrm.reg + add);
15150 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15151 oappend (scratchbuf);
15155 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15157 sprintf (scratchbuf, "%%tr%d", modrm.reg);
15158 oappend_maybe_intel (scratchbuf);
15162 OP_R (int bytemode, int sizeflag)
15164 /* Skip mod/rm byte. */
15167 OP_E_register (bytemode, sizeflag);
15171 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15173 int reg = modrm.reg;
15174 const char **names;
15176 used_prefixes |= (prefixes & PREFIX_DATA);
15177 if (prefixes & PREFIX_DATA)
15186 oappend (names[reg]);
15190 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15192 int reg = modrm.reg;
15193 const char **names;
15205 && bytemode != xmm_mode
15206 && bytemode != xmmq_mode
15207 && bytemode != evex_half_bcst_xmmq_mode
15208 && bytemode != ymm_mode
15209 && bytemode != scalar_mode)
15211 switch (vex.length)
15218 || (bytemode != vex_vsib_q_w_dq_mode
15219 && bytemode != vex_vsib_q_w_d_mode))
15231 else if (bytemode == xmmq_mode
15232 || bytemode == evex_half_bcst_xmmq_mode)
15234 switch (vex.length)
15247 else if (bytemode == ymm_mode)
15251 oappend (names[reg]);
15255 OP_EM (int bytemode, int sizeflag)
15258 const char **names;
15260 if (modrm.mod != 3)
15263 && (bytemode == v_mode || bytemode == v_swap_mode))
15265 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15266 used_prefixes |= (prefixes & PREFIX_DATA);
15268 OP_E (bytemode, sizeflag);
15272 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15275 /* Skip mod/rm byte. */
15278 used_prefixes |= (prefixes & PREFIX_DATA);
15280 if (prefixes & PREFIX_DATA)
15289 oappend (names[reg]);
15292 /* cvt* are the only instructions in sse2 which have
15293 both SSE and MMX operands and also have 0x66 prefix
15294 in their opcode. 0x66 was originally used to differentiate
15295 between SSE and MMX instruction(operands). So we have to handle the
15296 cvt* separately using OP_EMC and OP_MXC */
15298 OP_EMC (int bytemode, int sizeflag)
15300 if (modrm.mod != 3)
15302 if (intel_syntax && bytemode == v_mode)
15304 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15305 used_prefixes |= (prefixes & PREFIX_DATA);
15307 OP_E (bytemode, sizeflag);
15311 /* Skip mod/rm byte. */
15314 used_prefixes |= (prefixes & PREFIX_DATA);
15315 oappend (names_mm[modrm.rm]);
15319 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15321 used_prefixes |= (prefixes & PREFIX_DATA);
15322 oappend (names_mm[modrm.reg]);
15326 OP_EX (int bytemode, int sizeflag)
15329 const char **names;
15331 /* Skip mod/rm byte. */
15335 if (modrm.mod != 3)
15337 OP_E_memory (bytemode, sizeflag);
15352 if ((sizeflag & SUFFIX_ALWAYS)
15353 && (bytemode == x_swap_mode
15354 || bytemode == d_swap_mode
15355 || bytemode == d_scalar_swap_mode
15356 || bytemode == q_swap_mode
15357 || bytemode == q_scalar_swap_mode))
15361 && bytemode != xmm_mode
15362 && bytemode != xmmdw_mode
15363 && bytemode != xmmqd_mode
15364 && bytemode != xmm_mb_mode
15365 && bytemode != xmm_mw_mode
15366 && bytemode != xmm_md_mode
15367 && bytemode != xmm_mq_mode
15368 && bytemode != xmm_mdq_mode
15369 && bytemode != xmmq_mode
15370 && bytemode != evex_half_bcst_xmmq_mode
15371 && bytemode != ymm_mode
15372 && bytemode != d_scalar_mode
15373 && bytemode != d_scalar_swap_mode
15374 && bytemode != q_scalar_mode
15375 && bytemode != q_scalar_swap_mode
15376 && bytemode != vex_scalar_w_dq_mode)
15378 switch (vex.length)
15393 else if (bytemode == xmmq_mode
15394 || bytemode == evex_half_bcst_xmmq_mode)
15396 switch (vex.length)
15409 else if (bytemode == ymm_mode)
15413 oappend (names[reg]);
15417 OP_MS (int bytemode, int sizeflag)
15419 if (modrm.mod == 3)
15420 OP_EM (bytemode, sizeflag);
15426 OP_XS (int bytemode, int sizeflag)
15428 if (modrm.mod == 3)
15429 OP_EX (bytemode, sizeflag);
15435 OP_M (int bytemode, int sizeflag)
15437 if (modrm.mod == 3)
15438 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15441 OP_E (bytemode, sizeflag);
15445 OP_0f07 (int bytemode, int sizeflag)
15447 if (modrm.mod != 3 || modrm.rm != 0)
15450 OP_E (bytemode, sizeflag);
15453 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15454 32bit mode and "xchg %rax,%rax" in 64bit mode. */
15457 NOP_Fixup1 (int bytemode, int sizeflag)
15459 if ((prefixes & PREFIX_DATA) != 0
15462 && address_mode == mode_64bit))
15463 OP_REG (bytemode, sizeflag);
15465 strcpy (obuf, "nop");
15469 NOP_Fixup2 (int bytemode, int sizeflag)
15471 if ((prefixes & PREFIX_DATA) != 0
15474 && address_mode == mode_64bit))
15475 OP_IMREG (bytemode, sizeflag);
15478 static const char *const Suffix3DNow[] = {
15479 /* 00 */ NULL, NULL, NULL, NULL,
15480 /* 04 */ NULL, NULL, NULL, NULL,
15481 /* 08 */ NULL, NULL, NULL, NULL,
15482 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
15483 /* 10 */ NULL, NULL, NULL, NULL,
15484 /* 14 */ NULL, NULL, NULL, NULL,
15485 /* 18 */ NULL, NULL, NULL, NULL,
15486 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
15487 /* 20 */ NULL, NULL, NULL, NULL,
15488 /* 24 */ NULL, NULL, NULL, NULL,
15489 /* 28 */ NULL, NULL, NULL, NULL,
15490 /* 2C */ NULL, NULL, NULL, NULL,
15491 /* 30 */ NULL, NULL, NULL, NULL,
15492 /* 34 */ NULL, NULL, NULL, NULL,
15493 /* 38 */ NULL, NULL, NULL, NULL,
15494 /* 3C */ NULL, NULL, NULL, NULL,
15495 /* 40 */ NULL, NULL, NULL, NULL,
15496 /* 44 */ NULL, NULL, NULL, NULL,
15497 /* 48 */ NULL, NULL, NULL, NULL,
15498 /* 4C */ NULL, NULL, NULL, NULL,
15499 /* 50 */ NULL, NULL, NULL, NULL,
15500 /* 54 */ NULL, NULL, NULL, NULL,
15501 /* 58 */ NULL, NULL, NULL, NULL,
15502 /* 5C */ NULL, NULL, NULL, NULL,
15503 /* 60 */ NULL, NULL, NULL, NULL,
15504 /* 64 */ NULL, NULL, NULL, NULL,
15505 /* 68 */ NULL, NULL, NULL, NULL,
15506 /* 6C */ NULL, NULL, NULL, NULL,
15507 /* 70 */ NULL, NULL, NULL, NULL,
15508 /* 74 */ NULL, NULL, NULL, NULL,
15509 /* 78 */ NULL, NULL, NULL, NULL,
15510 /* 7C */ NULL, NULL, NULL, NULL,
15511 /* 80 */ NULL, NULL, NULL, NULL,
15512 /* 84 */ NULL, NULL, NULL, NULL,
15513 /* 88 */ NULL, NULL, "pfnacc", NULL,
15514 /* 8C */ NULL, NULL, "pfpnacc", NULL,
15515 /* 90 */ "pfcmpge", NULL, NULL, NULL,
15516 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
15517 /* 98 */ NULL, NULL, "pfsub", NULL,
15518 /* 9C */ NULL, NULL, "pfadd", NULL,
15519 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
15520 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
15521 /* A8 */ NULL, NULL, "pfsubr", NULL,
15522 /* AC */ NULL, NULL, "pfacc", NULL,
15523 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
15524 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
15525 /* B8 */ NULL, NULL, NULL, "pswapd",
15526 /* BC */ NULL, NULL, NULL, "pavgusb",
15527 /* C0 */ NULL, NULL, NULL, NULL,
15528 /* C4 */ NULL, NULL, NULL, NULL,
15529 /* C8 */ NULL, NULL, NULL, NULL,
15530 /* CC */ NULL, NULL, NULL, NULL,
15531 /* D0 */ NULL, NULL, NULL, NULL,
15532 /* D4 */ NULL, NULL, NULL, NULL,
15533 /* D8 */ NULL, NULL, NULL, NULL,
15534 /* DC */ NULL, NULL, NULL, NULL,
15535 /* E0 */ NULL, NULL, NULL, NULL,
15536 /* E4 */ NULL, NULL, NULL, NULL,
15537 /* E8 */ NULL, NULL, NULL, NULL,
15538 /* EC */ NULL, NULL, NULL, NULL,
15539 /* F0 */ NULL, NULL, NULL, NULL,
15540 /* F4 */ NULL, NULL, NULL, NULL,
15541 /* F8 */ NULL, NULL, NULL, NULL,
15542 /* FC */ NULL, NULL, NULL, NULL,
15546 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15548 const char *mnemonic;
15550 FETCH_DATA (the_info, codep + 1);
15551 /* AMD 3DNow! instructions are specified by an opcode suffix in the
15552 place where an 8-bit immediate would normally go. ie. the last
15553 byte of the instruction. */
15554 obufp = mnemonicendp;
15555 mnemonic = Suffix3DNow[*codep++ & 0xff];
15557 oappend (mnemonic);
15560 /* Since a variable sized modrm/sib chunk is between the start
15561 of the opcode (0x0f0f) and the opcode suffix, we need to do
15562 all the modrm processing first, and don't know until now that
15563 we have a bad opcode. This necessitates some cleaning up. */
15564 op_out[0][0] = '\0';
15565 op_out[1][0] = '\0';
15568 mnemonicendp = obufp;
15571 static struct op simd_cmp_op[] =
15573 { STRING_COMMA_LEN ("eq") },
15574 { STRING_COMMA_LEN ("lt") },
15575 { STRING_COMMA_LEN ("le") },
15576 { STRING_COMMA_LEN ("unord") },
15577 { STRING_COMMA_LEN ("neq") },
15578 { STRING_COMMA_LEN ("nlt") },
15579 { STRING_COMMA_LEN ("nle") },
15580 { STRING_COMMA_LEN ("ord") }
15584 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15586 unsigned int cmp_type;
15588 FETCH_DATA (the_info, codep + 1);
15589 cmp_type = *codep++ & 0xff;
15590 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15593 char *p = mnemonicendp - 2;
15597 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15598 mnemonicendp += simd_cmp_op[cmp_type].len;
15602 /* We have a reserved extension byte. Output it directly. */
15603 scratchbuf[0] = '$';
15604 print_operand_value (scratchbuf + 1, 1, cmp_type);
15605 oappend_maybe_intel (scratchbuf);
15606 scratchbuf[0] = '\0';
15611 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
15612 int sizeflag ATTRIBUTE_UNUSED)
15614 /* mwaitx %eax,%ecx,%ebx */
15617 const char **names = (address_mode == mode_64bit
15618 ? names64 : names32);
15619 strcpy (op_out[0], names[0]);
15620 strcpy (op_out[1], names[1]);
15621 strcpy (op_out[2], names[3]);
15622 two_source_ops = 1;
15624 /* Skip mod/rm byte. */
15630 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
15631 int sizeflag ATTRIBUTE_UNUSED)
15633 /* mwait %eax,%ecx */
15636 const char **names = (address_mode == mode_64bit
15637 ? names64 : names32);
15638 strcpy (op_out[0], names[0]);
15639 strcpy (op_out[1], names[1]);
15640 two_source_ops = 1;
15642 /* Skip mod/rm byte. */
15648 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15649 int sizeflag ATTRIBUTE_UNUSED)
15651 /* monitor %eax,%ecx,%edx" */
15654 const char **op1_names;
15655 const char **names = (address_mode == mode_64bit
15656 ? names64 : names32);
15658 if (!(prefixes & PREFIX_ADDR))
15659 op1_names = (address_mode == mode_16bit
15660 ? names16 : names);
15663 /* Remove "addr16/addr32". */
15664 all_prefixes[last_addr_prefix] = 0;
15665 op1_names = (address_mode != mode_32bit
15666 ? names32 : names16);
15667 used_prefixes |= PREFIX_ADDR;
15669 strcpy (op_out[0], op1_names[0]);
15670 strcpy (op_out[1], names[1]);
15671 strcpy (op_out[2], names[2]);
15672 two_source_ops = 1;
15674 /* Skip mod/rm byte. */
15682 /* Throw away prefixes and 1st. opcode byte. */
15683 codep = insn_codep + 1;
15688 REP_Fixup (int bytemode, int sizeflag)
15690 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15692 if (prefixes & PREFIX_REPZ)
15693 all_prefixes[last_repz_prefix] = REP_PREFIX;
15700 OP_IMREG (bytemode, sizeflag);
15703 OP_ESreg (bytemode, sizeflag);
15706 OP_DSreg (bytemode, sizeflag);
15714 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15718 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15720 if (prefixes & PREFIX_REPNZ)
15721 all_prefixes[last_repnz_prefix] = BND_PREFIX;
15724 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15728 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
15729 int sizeflag ATTRIBUTE_UNUSED)
15731 if (active_seg_prefix == PREFIX_DS
15732 && (address_mode != mode_64bit || last_data_prefix < 0))
15734 /* NOTRACK prefix is only valid on indirect branch instructions.
15735 NB: DATA prefix is unsupported for Intel64. */
15736 active_seg_prefix = 0;
15737 all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
15741 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15742 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15746 HLE_Fixup1 (int bytemode, int sizeflag)
15749 && (prefixes & PREFIX_LOCK) != 0)
15751 if (prefixes & PREFIX_REPZ)
15752 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15753 if (prefixes & PREFIX_REPNZ)
15754 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15757 OP_E (bytemode, sizeflag);
15760 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15761 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
15765 HLE_Fixup2 (int bytemode, int sizeflag)
15767 if (modrm.mod != 3)
15769 if (prefixes & PREFIX_REPZ)
15770 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15771 if (prefixes & PREFIX_REPNZ)
15772 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15775 OP_E (bytemode, sizeflag);
15778 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
15779 "xrelease" for memory operand. No check for LOCK prefix. */
15782 HLE_Fixup3 (int bytemode, int sizeflag)
15785 && last_repz_prefix > last_repnz_prefix
15786 && (prefixes & PREFIX_REPZ) != 0)
15787 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15789 OP_E (bytemode, sizeflag);
15793 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15798 /* Change cmpxchg8b to cmpxchg16b. */
15799 char *p = mnemonicendp - 2;
15800 mnemonicendp = stpcpy (p, "16b");
15803 else if ((prefixes & PREFIX_LOCK) != 0)
15805 if (prefixes & PREFIX_REPZ)
15806 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15807 if (prefixes & PREFIX_REPNZ)
15808 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15811 OP_M (bytemode, sizeflag);
15815 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15817 const char **names;
15821 switch (vex.length)
15835 oappend (names[reg]);
15839 CRC32_Fixup (int bytemode, int sizeflag)
15841 /* Add proper suffix to "crc32". */
15842 char *p = mnemonicendp;
15861 if (sizeflag & DFLAG)
15865 used_prefixes |= (prefixes & PREFIX_DATA);
15869 oappend (INTERNAL_DISASSEMBLER_ERROR);
15876 if (modrm.mod == 3)
15880 /* Skip mod/rm byte. */
15885 add = (rex & REX_B) ? 8 : 0;
15886 if (bytemode == b_mode)
15890 oappend (names8rex[modrm.rm + add]);
15892 oappend (names8[modrm.rm + add]);
15898 oappend (names64[modrm.rm + add]);
15899 else if ((prefixes & PREFIX_DATA))
15900 oappend (names16[modrm.rm + add]);
15902 oappend (names32[modrm.rm + add]);
15906 OP_E (bytemode, sizeflag);
15910 FXSAVE_Fixup (int bytemode, int sizeflag)
15912 /* Add proper suffix to "fxsave" and "fxrstor". */
15916 char *p = mnemonicendp;
15922 OP_M (bytemode, sizeflag);
15926 PCMPESTR_Fixup (int bytemode, int sizeflag)
15928 /* Add proper suffix to "{,v}pcmpestr{i,m}". */
15931 char *p = mnemonicendp;
15936 else if (sizeflag & SUFFIX_ALWAYS)
15943 OP_EX (bytemode, sizeflag);
15946 /* Display the destination register operand for instructions with
15950 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15953 const char **names;
15961 reg = vex.register_specifier;
15962 vex.register_specifier = 0;
15963 if (address_mode != mode_64bit)
15965 else if (vex.evex && !vex.v)
15968 if (bytemode == vex_scalar_mode)
15970 oappend (names_xmm[reg]);
15974 switch (vex.length)
15981 case vex_vsib_q_w_dq_mode:
15982 case vex_vsib_q_w_d_mode:
15998 names = names_mask;
16012 case vex_vsib_q_w_dq_mode:
16013 case vex_vsib_q_w_d_mode:
16014 names = vex.w ? names_ymm : names_xmm;
16023 names = names_mask;
16026 /* See PR binutils/20893 for a reproducer. */
16038 oappend (names[reg]);
16041 /* Get the VEX immediate byte without moving codep. */
16043 static unsigned char
16044 get_vex_imm8 (int sizeflag, int opnum)
16046 int bytes_before_imm = 0;
16048 if (modrm.mod != 3)
16050 /* There are SIB/displacement bytes. */
16051 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16053 /* 32/64 bit address mode */
16054 int base = modrm.rm;
16056 /* Check SIB byte. */
16059 FETCH_DATA (the_info, codep + 1);
16061 /* When decoding the third source, don't increase
16062 bytes_before_imm as this has already been incremented
16063 by one in OP_E_memory while decoding the second
16066 bytes_before_imm++;
16069 /* Don't increase bytes_before_imm when decoding the third source,
16070 it has already been incremented by OP_E_memory while decoding
16071 the second source operand. */
16077 /* When modrm.rm == 5 or modrm.rm == 4 and base in
16078 SIB == 5, there is a 4 byte displacement. */
16080 /* No displacement. */
16082 /* Fall through. */
16084 /* 4 byte displacement. */
16085 bytes_before_imm += 4;
16088 /* 1 byte displacement. */
16089 bytes_before_imm++;
16096 /* 16 bit address mode */
16097 /* Don't increase bytes_before_imm when decoding the third source,
16098 it has already been incremented by OP_E_memory while decoding
16099 the second source operand. */
16105 /* When modrm.rm == 6, there is a 2 byte displacement. */
16107 /* No displacement. */
16109 /* Fall through. */
16111 /* 2 byte displacement. */
16112 bytes_before_imm += 2;
16115 /* 1 byte displacement: when decoding the third source,
16116 don't increase bytes_before_imm as this has already
16117 been incremented by one in OP_E_memory while decoding
16118 the second source operand. */
16120 bytes_before_imm++;
16128 FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16129 return codep [bytes_before_imm];
16133 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16135 const char **names;
16137 if (reg == -1 && modrm.mod != 3)
16139 OP_E_memory (bytemode, sizeflag);
16151 if (address_mode != mode_64bit)
16155 switch (vex.length)
16166 oappend (names[reg]);
16170 OP_EX_VexImmW (int bytemode, int sizeflag)
16173 static unsigned char vex_imm8;
16175 if (vex_w_done == 0)
16179 /* Skip mod/rm byte. */
16183 vex_imm8 = get_vex_imm8 (sizeflag, 0);
16186 reg = vex_imm8 >> 4;
16188 OP_EX_VexReg (bytemode, sizeflag, reg);
16190 else if (vex_w_done == 1)
16195 reg = vex_imm8 >> 4;
16197 OP_EX_VexReg (bytemode, sizeflag, reg);
16201 /* Output the imm8 directly. */
16202 scratchbuf[0] = '$';
16203 print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16204 oappend_maybe_intel (scratchbuf);
16205 scratchbuf[0] = '\0';
16211 OP_Vex_2src (int bytemode, int sizeflag)
16213 if (modrm.mod == 3)
16215 int reg = modrm.rm;
16219 oappend (names_xmm[reg]);
16224 && (bytemode == v_mode || bytemode == v_swap_mode))
16226 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16227 used_prefixes |= (prefixes & PREFIX_DATA);
16229 OP_E (bytemode, sizeflag);
16234 OP_Vex_2src_1 (int bytemode, int sizeflag)
16236 if (modrm.mod == 3)
16238 /* Skip mod/rm byte. */
16245 unsigned int reg = vex.register_specifier;
16246 vex.register_specifier = 0;
16248 if (address_mode != mode_64bit)
16250 oappend (names_xmm[reg]);
16253 OP_Vex_2src (bytemode, sizeflag);
16257 OP_Vex_2src_2 (int bytemode, int sizeflag)
16260 OP_Vex_2src (bytemode, sizeflag);
16263 unsigned int reg = vex.register_specifier;
16264 vex.register_specifier = 0;
16266 if (address_mode != mode_64bit)
16268 oappend (names_xmm[reg]);
16273 OP_EX_VexW (int bytemode, int sizeflag)
16279 /* Skip mod/rm byte. */
16284 reg = get_vex_imm8 (sizeflag, 0) >> 4;
16289 reg = get_vex_imm8 (sizeflag, 1) >> 4;
16292 OP_EX_VexReg (bytemode, sizeflag, reg);
16300 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16303 const char **names;
16305 FETCH_DATA (the_info, codep + 1);
16308 if (bytemode != x_mode)
16312 if (address_mode != mode_64bit)
16315 switch (vex.length)
16326 oappend (names[reg]);
16330 OP_XMM_VexW (int bytemode, int sizeflag)
16332 /* Turn off the REX.W bit since it is used for swapping operands
16335 OP_XMM (bytemode, sizeflag);
16339 OP_EX_Vex (int bytemode, int sizeflag)
16341 if (modrm.mod != 3)
16343 OP_EX (bytemode, sizeflag);
16347 OP_XMM_Vex (int bytemode, int sizeflag)
16349 if (modrm.mod != 3)
16351 OP_XMM (bytemode, sizeflag);
16354 static struct op vex_cmp_op[] =
16356 { STRING_COMMA_LEN ("eq") },
16357 { STRING_COMMA_LEN ("lt") },
16358 { STRING_COMMA_LEN ("le") },
16359 { STRING_COMMA_LEN ("unord") },
16360 { STRING_COMMA_LEN ("neq") },
16361 { STRING_COMMA_LEN ("nlt") },
16362 { STRING_COMMA_LEN ("nle") },
16363 { STRING_COMMA_LEN ("ord") },
16364 { STRING_COMMA_LEN ("eq_uq") },
16365 { STRING_COMMA_LEN ("nge") },
16366 { STRING_COMMA_LEN ("ngt") },
16367 { STRING_COMMA_LEN ("false") },
16368 { STRING_COMMA_LEN ("neq_oq") },
16369 { STRING_COMMA_LEN ("ge") },
16370 { STRING_COMMA_LEN ("gt") },
16371 { STRING_COMMA_LEN ("true") },
16372 { STRING_COMMA_LEN ("eq_os") },
16373 { STRING_COMMA_LEN ("lt_oq") },
16374 { STRING_COMMA_LEN ("le_oq") },
16375 { STRING_COMMA_LEN ("unord_s") },
16376 { STRING_COMMA_LEN ("neq_us") },
16377 { STRING_COMMA_LEN ("nlt_uq") },
16378 { STRING_COMMA_LEN ("nle_uq") },
16379 { STRING_COMMA_LEN ("ord_s") },
16380 { STRING_COMMA_LEN ("eq_us") },
16381 { STRING_COMMA_LEN ("nge_uq") },
16382 { STRING_COMMA_LEN ("ngt_uq") },
16383 { STRING_COMMA_LEN ("false_os") },
16384 { STRING_COMMA_LEN ("neq_os") },
16385 { STRING_COMMA_LEN ("ge_oq") },
16386 { STRING_COMMA_LEN ("gt_oq") },
16387 { STRING_COMMA_LEN ("true_us") },
16391 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16393 unsigned int cmp_type;
16395 FETCH_DATA (the_info, codep + 1);
16396 cmp_type = *codep++ & 0xff;
16397 if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16400 char *p = mnemonicendp - 2;
16404 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16405 mnemonicendp += vex_cmp_op[cmp_type].len;
16409 /* We have a reserved extension byte. Output it directly. */
16410 scratchbuf[0] = '$';
16411 print_operand_value (scratchbuf + 1, 1, cmp_type);
16412 oappend_maybe_intel (scratchbuf);
16413 scratchbuf[0] = '\0';
16418 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16419 int sizeflag ATTRIBUTE_UNUSED)
16421 unsigned int cmp_type;
16426 FETCH_DATA (the_info, codep + 1);
16427 cmp_type = *codep++ & 0xff;
16428 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16429 If it's the case, print suffix, otherwise - print the immediate. */
16430 if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16435 char *p = mnemonicendp - 2;
16437 /* vpcmp* can have both one- and two-lettered suffix. */
16451 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16452 mnemonicendp += simd_cmp_op[cmp_type].len;
16456 /* We have a reserved extension byte. Output it directly. */
16457 scratchbuf[0] = '$';
16458 print_operand_value (scratchbuf + 1, 1, cmp_type);
16459 oappend_maybe_intel (scratchbuf);
16460 scratchbuf[0] = '\0';
16464 static const struct op xop_cmp_op[] =
16466 { STRING_COMMA_LEN ("lt") },
16467 { STRING_COMMA_LEN ("le") },
16468 { STRING_COMMA_LEN ("gt") },
16469 { STRING_COMMA_LEN ("ge") },
16470 { STRING_COMMA_LEN ("eq") },
16471 { STRING_COMMA_LEN ("neq") },
16472 { STRING_COMMA_LEN ("false") },
16473 { STRING_COMMA_LEN ("true") }
16477 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16478 int sizeflag ATTRIBUTE_UNUSED)
16480 unsigned int cmp_type;
16482 FETCH_DATA (the_info, codep + 1);
16483 cmp_type = *codep++ & 0xff;
16484 if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16487 char *p = mnemonicendp - 2;
16489 /* vpcom* can have both one- and two-lettered suffix. */
16503 sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16504 mnemonicendp += xop_cmp_op[cmp_type].len;
16508 /* We have a reserved extension byte. Output it directly. */
16509 scratchbuf[0] = '$';
16510 print_operand_value (scratchbuf + 1, 1, cmp_type);
16511 oappend_maybe_intel (scratchbuf);
16512 scratchbuf[0] = '\0';
16516 static const struct op pclmul_op[] =
16518 { STRING_COMMA_LEN ("lql") },
16519 { STRING_COMMA_LEN ("hql") },
16520 { STRING_COMMA_LEN ("lqh") },
16521 { STRING_COMMA_LEN ("hqh") }
16525 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16526 int sizeflag ATTRIBUTE_UNUSED)
16528 unsigned int pclmul_type;
16530 FETCH_DATA (the_info, codep + 1);
16531 pclmul_type = *codep++ & 0xff;
16532 switch (pclmul_type)
16543 if (pclmul_type < ARRAY_SIZE (pclmul_op))
16546 char *p = mnemonicendp - 3;
16551 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16552 mnemonicendp += pclmul_op[pclmul_type].len;
16556 /* We have a reserved extension byte. Output it directly. */
16557 scratchbuf[0] = '$';
16558 print_operand_value (scratchbuf + 1, 1, pclmul_type);
16559 oappend_maybe_intel (scratchbuf);
16560 scratchbuf[0] = '\0';
16565 MOVBE_Fixup (int bytemode, int sizeflag)
16567 /* Add proper suffix to "movbe". */
16568 char *p = mnemonicendp;
16577 if (sizeflag & SUFFIX_ALWAYS)
16583 if (sizeflag & DFLAG)
16587 used_prefixes |= (prefixes & PREFIX_DATA);
16592 oappend (INTERNAL_DISASSEMBLER_ERROR);
16599 OP_M (bytemode, sizeflag);
16603 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16606 const char **names;
16608 /* Skip mod/rm byte. */
16622 oappend (names[reg]);
16626 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16628 const char **names;
16629 unsigned int reg = vex.register_specifier;
16630 vex.register_specifier = 0;
16637 if (address_mode != mode_64bit)
16639 oappend (names[reg]);
16643 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16646 || (bytemode != mask_mode && bytemode != mask_bd_mode))
16650 if ((rex & REX_R) != 0 || !vex.r)
16656 oappend (names_mask [modrm.reg]);
16660 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16663 || (bytemode != evex_rounding_mode
16664 && bytemode != evex_rounding_64_mode
16665 && bytemode != evex_sae_mode))
16667 if (modrm.mod == 3 && vex.b)
16670 case evex_rounding_64_mode:
16671 if (address_mode != mode_64bit)
16676 /* Fall through. */
16677 case evex_rounding_mode:
16678 oappend (names_rounding[vex.ll]);
16680 case evex_sae_mode: