1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2019 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma, disassemble_info *);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma get64 (void);
58 static bfd_signed_vma get32 (void);
59 static bfd_signed_vma get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VCMP_Fixup (int, int);
99 static void VPCMP_Fixup (int, int);
100 static void VPCOM_Fixup (int, int);
101 static void OP_0f07 (int, int);
102 static void OP_Monitor (int, int);
103 static void OP_Mwait (int, int);
104 static void OP_Mwaitx (int, int);
105 static void NOP_Fixup1 (int, int);
106 static void NOP_Fixup2 (int, int);
107 static void OP_3DNowSuffix (int, int);
108 static void CMP_Fixup (int, int);
109 static void BadOp (void);
110 static void REP_Fixup (int, int);
111 static void BND_Fixup (int, int);
112 static void NOTRACK_Fixup (int, int);
113 static void HLE_Fixup1 (int, int);
114 static void HLE_Fixup2 (int, int);
115 static void HLE_Fixup3 (int, int);
116 static void CMPXCHG8B_Fixup (int, int);
117 static void XMM_Fixup (int, int);
118 static void CRC32_Fixup (int, int);
119 static void FXSAVE_Fixup (int, int);
120 static void PCMPESTR_Fixup (int, int);
121 static void OP_LWPCB_E (int, int);
122 static void OP_LWP_E (int, int);
123 static void OP_Vex_2src_1 (int, int);
124 static void OP_Vex_2src_2 (int, int);
126 static void MOVBE_Fixup (int, int);
128 static void OP_Mask (int, int);
131 /* Points to first byte not fetched. */
132 bfd_byte *max_fetched;
133 bfd_byte the_buffer[MAX_MNEM_SIZE];
136 OPCODES_SIGJMP_BUF bailout;
146 enum address_mode address_mode;
148 /* Flags for the prefixes for the current instruction. See below. */
151 /* REX prefix the current instruction. See below. */
153 /* Bits of REX we've already used. */
155 /* REX bits in original REX prefix ignored. */
156 static int rex_ignored;
157 /* Mark parts used in the REX prefix. When we are testing for
158 empty prefix (for 8bit register REX extension), just mask it
159 out. Otherwise test for REX bit is excuse for existence of REX
160 only in case value is nonzero. */
161 #define USED_REX(value) \
166 rex_used |= (value) | REX_OPCODE; \
169 rex_used |= REX_OPCODE; \
172 /* Flags for prefixes which we somehow handled when printing the
173 current instruction. */
174 static int used_prefixes;
176 /* Flags stored in PREFIXES. */
177 #define PREFIX_REPZ 1
178 #define PREFIX_REPNZ 2
179 #define PREFIX_LOCK 4
181 #define PREFIX_SS 0x10
182 #define PREFIX_DS 0x20
183 #define PREFIX_ES 0x40
184 #define PREFIX_FS 0x80
185 #define PREFIX_GS 0x100
186 #define PREFIX_DATA 0x200
187 #define PREFIX_ADDR 0x400
188 #define PREFIX_FWAIT 0x800
190 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
191 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
193 #define FETCH_DATA(info, addr) \
194 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
195 ? 1 : fetch_data ((info), (addr)))
198 fetch_data (struct disassemble_info *info, bfd_byte *addr)
201 struct dis_private *priv = (struct dis_private *) info->private_data;
202 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
204 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
205 status = (*info->read_memory_func) (start,
207 addr - priv->max_fetched,
213 /* If we did manage to read at least one byte, then
214 print_insn_i386 will do something sensible. Otherwise, print
215 an error. We do that here because this is where we know
217 if (priv->max_fetched == priv->the_buffer)
218 (*info->memory_error_func) (status, start, info);
219 OPCODES_SIGLONGJMP (priv->bailout, 1);
222 priv->max_fetched = addr;
226 /* Possible values for prefix requirement. */
227 #define PREFIX_IGNORED_SHIFT 16
228 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
229 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
232 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
234 /* Opcode prefixes. */
235 #define PREFIX_OPCODE (PREFIX_REPZ \
239 /* Prefixes ignored. */
240 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
241 | PREFIX_IGNORED_REPNZ \
242 | PREFIX_IGNORED_DATA)
244 #define XX { NULL, 0 }
245 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
247 #define Eb { OP_E, b_mode }
248 #define Ebnd { OP_E, bnd_mode }
249 #define EbS { OP_E, b_swap_mode }
250 #define EbndS { OP_E, bnd_swap_mode }
251 #define Ev { OP_E, v_mode }
252 #define Eva { OP_E, va_mode }
253 #define Ev_bnd { OP_E, v_bnd_mode }
254 #define EvS { OP_E, v_swap_mode }
255 #define Ed { OP_E, d_mode }
256 #define Edq { OP_E, dq_mode }
257 #define Edqw { OP_E, dqw_mode }
258 #define Edqb { OP_E, dqb_mode }
259 #define Edb { OP_E, db_mode }
260 #define Edw { OP_E, dw_mode }
261 #define Edqd { OP_E, dqd_mode }
262 #define Eq { OP_E, q_mode }
263 #define indirEv { OP_indirE, indir_v_mode }
264 #define indirEp { OP_indirE, f_mode }
265 #define stackEv { OP_E, stack_v_mode }
266 #define Em { OP_E, m_mode }
267 #define Ew { OP_E, w_mode }
268 #define M { OP_M, 0 } /* lea, lgdt, etc. */
269 #define Ma { OP_M, a_mode }
270 #define Mb { OP_M, b_mode }
271 #define Md { OP_M, d_mode }
272 #define Mo { OP_M, o_mode }
273 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
274 #define Mq { OP_M, q_mode }
275 #define Mv_bnd { OP_M, v_bndmk_mode }
276 #define Mx { OP_M, x_mode }
277 #define Mxmm { OP_M, xmm_mode }
278 #define Gb { OP_G, b_mode }
279 #define Gbnd { OP_G, bnd_mode }
280 #define Gv { OP_G, v_mode }
281 #define Gd { OP_G, d_mode }
282 #define Gdq { OP_G, dq_mode }
283 #define Gm { OP_G, m_mode }
284 #define Gva { OP_G, va_mode }
285 #define Gw { OP_G, w_mode }
286 #define Rd { OP_R, d_mode }
287 #define Rdq { OP_R, dq_mode }
288 #define Rm { OP_R, m_mode }
289 #define Ib { OP_I, b_mode }
290 #define sIb { OP_sI, b_mode } /* sign extened byte */
291 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
292 #define Iv { OP_I, v_mode }
293 #define sIv { OP_sI, v_mode }
294 #define Iv64 { OP_I64, v_mode }
295 #define Id { OP_I, d_mode }
296 #define Iw { OP_I, w_mode }
297 #define I1 { OP_I, const_1_mode }
298 #define Jb { OP_J, b_mode }
299 #define Jv { OP_J, v_mode }
300 #define Cm { OP_C, m_mode }
301 #define Dm { OP_D, m_mode }
302 #define Td { OP_T, d_mode }
303 #define Skip_MODRM { OP_Skip_MODRM, 0 }
305 #define RMeAX { OP_REG, eAX_reg }
306 #define RMeBX { OP_REG, eBX_reg }
307 #define RMeCX { OP_REG, eCX_reg }
308 #define RMeDX { OP_REG, eDX_reg }
309 #define RMeSP { OP_REG, eSP_reg }
310 #define RMeBP { OP_REG, eBP_reg }
311 #define RMeSI { OP_REG, eSI_reg }
312 #define RMeDI { OP_REG, eDI_reg }
313 #define RMrAX { OP_REG, rAX_reg }
314 #define RMrBX { OP_REG, rBX_reg }
315 #define RMrCX { OP_REG, rCX_reg }
316 #define RMrDX { OP_REG, rDX_reg }
317 #define RMrSP { OP_REG, rSP_reg }
318 #define RMrBP { OP_REG, rBP_reg }
319 #define RMrSI { OP_REG, rSI_reg }
320 #define RMrDI { OP_REG, rDI_reg }
321 #define RMAL { OP_REG, al_reg }
322 #define RMCL { OP_REG, cl_reg }
323 #define RMDL { OP_REG, dl_reg }
324 #define RMBL { OP_REG, bl_reg }
325 #define RMAH { OP_REG, ah_reg }
326 #define RMCH { OP_REG, ch_reg }
327 #define RMDH { OP_REG, dh_reg }
328 #define RMBH { OP_REG, bh_reg }
329 #define RMAX { OP_REG, ax_reg }
330 #define RMDX { OP_REG, dx_reg }
332 #define eAX { OP_IMREG, eAX_reg }
333 #define eBX { OP_IMREG, eBX_reg }
334 #define eCX { OP_IMREG, eCX_reg }
335 #define eDX { OP_IMREG, eDX_reg }
336 #define eSP { OP_IMREG, eSP_reg }
337 #define eBP { OP_IMREG, eBP_reg }
338 #define eSI { OP_IMREG, eSI_reg }
339 #define eDI { OP_IMREG, eDI_reg }
340 #define AL { OP_IMREG, al_reg }
341 #define CL { OP_IMREG, cl_reg }
342 #define DL { OP_IMREG, dl_reg }
343 #define BL { OP_IMREG, bl_reg }
344 #define AH { OP_IMREG, ah_reg }
345 #define CH { OP_IMREG, ch_reg }
346 #define DH { OP_IMREG, dh_reg }
347 #define BH { OP_IMREG, bh_reg }
348 #define AX { OP_IMREG, ax_reg }
349 #define DX { OP_IMREG, dx_reg }
350 #define zAX { OP_IMREG, z_mode_ax_reg }
351 #define indirDX { OP_IMREG, indir_dx_reg }
353 #define Sw { OP_SEG, w_mode }
354 #define Sv { OP_SEG, v_mode }
355 #define Ap { OP_DIR, 0 }
356 #define Ob { OP_OFF64, b_mode }
357 #define Ov { OP_OFF64, v_mode }
358 #define Xb { OP_DSreg, eSI_reg }
359 #define Xv { OP_DSreg, eSI_reg }
360 #define Xz { OP_DSreg, eSI_reg }
361 #define Yb { OP_ESreg, eDI_reg }
362 #define Yv { OP_ESreg, eDI_reg }
363 #define DSBX { OP_DSreg, eBX_reg }
365 #define es { OP_REG, es_reg }
366 #define ss { OP_REG, ss_reg }
367 #define cs { OP_REG, cs_reg }
368 #define ds { OP_REG, ds_reg }
369 #define fs { OP_REG, fs_reg }
370 #define gs { OP_REG, gs_reg }
372 #define MX { OP_MMX, 0 }
373 #define XM { OP_XMM, 0 }
374 #define XMScalar { OP_XMM, scalar_mode }
375 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
376 #define XMM { OP_XMM, xmm_mode }
377 #define XMxmmq { OP_XMM, xmmq_mode }
378 #define EM { OP_EM, v_mode }
379 #define EMS { OP_EM, v_swap_mode }
380 #define EMd { OP_EM, d_mode }
381 #define EMx { OP_EM, x_mode }
382 #define EXbScalar { OP_EX, b_scalar_mode }
383 #define EXw { OP_EX, w_mode }
384 #define EXwScalar { OP_EX, w_scalar_mode }
385 #define EXd { OP_EX, d_mode }
386 #define EXdScalar { OP_EX, d_scalar_mode }
387 #define EXdS { OP_EX, d_swap_mode }
388 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
389 #define EXq { OP_EX, q_mode }
390 #define EXqScalar { OP_EX, q_scalar_mode }
391 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
392 #define EXqS { OP_EX, q_swap_mode }
393 #define EXx { OP_EX, x_mode }
394 #define EXxS { OP_EX, x_swap_mode }
395 #define EXxmm { OP_EX, xmm_mode }
396 #define EXymm { OP_EX, ymm_mode }
397 #define EXxmmq { OP_EX, xmmq_mode }
398 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
399 #define EXxmm_mb { OP_EX, xmm_mb_mode }
400 #define EXxmm_mw { OP_EX, xmm_mw_mode }
401 #define EXxmm_md { OP_EX, xmm_md_mode }
402 #define EXxmm_mq { OP_EX, xmm_mq_mode }
403 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
404 #define EXxmmdw { OP_EX, xmmdw_mode }
405 #define EXxmmqd { OP_EX, xmmqd_mode }
406 #define EXymmq { OP_EX, ymmq_mode }
407 #define EXVexWdq { OP_EX, vex_w_dq_mode }
408 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
409 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
410 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
411 #define MS { OP_MS, v_mode }
412 #define XS { OP_XS, v_mode }
413 #define EMCq { OP_EMC, q_mode }
414 #define MXC { OP_MXC, 0 }
415 #define OPSUF { OP_3DNowSuffix, 0 }
416 #define CMP { CMP_Fixup, 0 }
417 #define XMM0 { XMM_Fixup, 0 }
418 #define FXSAVE { FXSAVE_Fixup, 0 }
419 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
420 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
422 #define Vex { OP_VEX, vex_mode }
423 #define VexScalar { OP_VEX, vex_scalar_mode }
424 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
425 #define Vex128 { OP_VEX, vex128_mode }
426 #define Vex256 { OP_VEX, vex256_mode }
427 #define VexGdq { OP_VEX, dq_mode }
428 #define EXdVex { OP_EX_Vex, d_mode }
429 #define EXdVexS { OP_EX_Vex, d_swap_mode }
430 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
431 #define EXqVex { OP_EX_Vex, q_mode }
432 #define EXqVexS { OP_EX_Vex, q_swap_mode }
433 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
434 #define EXVexW { OP_EX_VexW, x_mode }
435 #define EXdVexW { OP_EX_VexW, d_mode }
436 #define EXqVexW { OP_EX_VexW, q_mode }
437 #define EXVexImmW { OP_EX_VexImmW, x_mode }
438 #define XMVex { OP_XMM_Vex, 0 }
439 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
440 #define XMVexW { OP_XMM_VexW, 0 }
441 #define XMVexI4 { OP_REG_VexI4, x_mode }
442 #define PCLMUL { PCLMUL_Fixup, 0 }
443 #define VCMP { VCMP_Fixup, 0 }
444 #define VPCMP { VPCMP_Fixup, 0 }
445 #define VPCOM { VPCOM_Fixup, 0 }
447 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
448 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
449 #define EXxEVexS { OP_Rounding, evex_sae_mode }
451 #define XMask { OP_Mask, mask_mode }
452 #define MaskG { OP_G, mask_mode }
453 #define MaskE { OP_E, mask_mode }
454 #define MaskBDE { OP_E, mask_bd_mode }
455 #define MaskR { OP_R, mask_mode }
456 #define MaskVex { OP_VEX, mask_mode }
458 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
459 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
460 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
461 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
463 /* Used handle "rep" prefix for string instructions. */
464 #define Xbr { REP_Fixup, eSI_reg }
465 #define Xvr { REP_Fixup, eSI_reg }
466 #define Ybr { REP_Fixup, eDI_reg }
467 #define Yvr { REP_Fixup, eDI_reg }
468 #define Yzr { REP_Fixup, eDI_reg }
469 #define indirDXr { REP_Fixup, indir_dx_reg }
470 #define ALr { REP_Fixup, al_reg }
471 #define eAXr { REP_Fixup, eAX_reg }
473 /* Used handle HLE prefix for lockable instructions. */
474 #define Ebh1 { HLE_Fixup1, b_mode }
475 #define Evh1 { HLE_Fixup1, v_mode }
476 #define Ebh2 { HLE_Fixup2, b_mode }
477 #define Evh2 { HLE_Fixup2, v_mode }
478 #define Ebh3 { HLE_Fixup3, b_mode }
479 #define Evh3 { HLE_Fixup3, v_mode }
481 #define BND { BND_Fixup, 0 }
482 #define NOTRACK { NOTRACK_Fixup, 0 }
484 #define cond_jump_flag { NULL, cond_jump_mode }
485 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
487 /* bits in sizeflag */
488 #define SUFFIX_ALWAYS 4
496 /* byte operand with operand swapped */
498 /* byte operand, sign extend like 'T' suffix */
500 /* operand size depends on prefixes */
502 /* operand size depends on prefixes with operand swapped */
504 /* operand size depends on address prefix */
508 /* double word operand */
510 /* double word operand with operand swapped */
512 /* quad word operand */
514 /* quad word operand with operand swapped */
516 /* ten-byte operand */
518 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
519 broadcast enabled. */
521 /* Similar to x_mode, but with different EVEX mem shifts. */
523 /* Similar to x_mode, but with disabled broadcast. */
525 /* Similar to x_mode, but with operands swapped and disabled broadcast
528 /* 16-byte XMM operand */
530 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
531 memory operand (depending on vector length). Broadcast isn't
534 /* Same as xmmq_mode, but broadcast is allowed. */
535 evex_half_bcst_xmmq_mode,
536 /* XMM register or byte memory operand */
538 /* XMM register or word memory operand */
540 /* XMM register or double word memory operand */
542 /* XMM register or quad word memory operand */
544 /* XMM register or double/quad word memory operand, depending on
547 /* 16-byte XMM, word, double word or quad word operand. */
549 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
551 /* 32-byte YMM operand */
553 /* quad word, ymmword or zmmword memory operand. */
555 /* 32-byte YMM or 16-byte word operand */
557 /* d_mode in 32bit, q_mode in 64bit mode. */
559 /* pair of v_mode operands */
564 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
566 /* operand size depends on REX prefixes. */
568 /* registers like dq_mode, memory like w_mode. */
572 /* bounds operand with operand swapped */
574 /* 4- or 6-byte pointer operand */
577 /* v_mode for indirect branch opcodes. */
579 /* v_mode for stack-related opcodes. */
581 /* non-quad operand size depends on prefixes */
583 /* 16-byte operand */
585 /* registers like dq_mode, memory like b_mode. */
587 /* registers like d_mode, memory like b_mode. */
589 /* registers like d_mode, memory like w_mode. */
591 /* registers like dq_mode, memory like d_mode. */
593 /* normal vex mode */
595 /* 128bit vex mode */
597 /* 256bit vex mode */
599 /* operand size depends on the VEX.W bit. */
602 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
603 vex_vsib_d_w_dq_mode,
604 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
606 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
607 vex_vsib_q_w_dq_mode,
608 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
611 /* scalar, ignore vector length. */
613 /* like b_mode, ignore vector length. */
615 /* like w_mode, ignore vector length. */
617 /* like d_mode, ignore vector length. */
619 /* like d_swap_mode, ignore vector length. */
621 /* like q_mode, ignore vector length. */
623 /* like q_swap_mode, ignore vector length. */
625 /* like vex_mode, ignore vector length. */
627 /* like vex_w_dq_mode, ignore vector length. */
628 vex_scalar_w_dq_mode,
630 /* Static rounding. */
632 /* Static rounding, 64-bit mode only. */
633 evex_rounding_64_mode,
634 /* Supress all exceptions. */
637 /* Mask register operand. */
639 /* Mask register operand. */
707 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
709 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
710 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
711 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
712 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
713 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
714 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
715 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
716 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
717 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
718 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
719 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
720 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
721 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
722 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
723 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
724 #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
852 MOD_VEX_0F12_PREFIX_0,
854 MOD_VEX_0F16_PREFIX_0,
857 MOD_VEX_W_0_0F41_P_0_LEN_1,
858 MOD_VEX_W_1_0F41_P_0_LEN_1,
859 MOD_VEX_W_0_0F41_P_2_LEN_1,
860 MOD_VEX_W_1_0F41_P_2_LEN_1,
861 MOD_VEX_W_0_0F42_P_0_LEN_1,
862 MOD_VEX_W_1_0F42_P_0_LEN_1,
863 MOD_VEX_W_0_0F42_P_2_LEN_1,
864 MOD_VEX_W_1_0F42_P_2_LEN_1,
865 MOD_VEX_W_0_0F44_P_0_LEN_1,
866 MOD_VEX_W_1_0F44_P_0_LEN_1,
867 MOD_VEX_W_0_0F44_P_2_LEN_1,
868 MOD_VEX_W_1_0F44_P_2_LEN_1,
869 MOD_VEX_W_0_0F45_P_0_LEN_1,
870 MOD_VEX_W_1_0F45_P_0_LEN_1,
871 MOD_VEX_W_0_0F45_P_2_LEN_1,
872 MOD_VEX_W_1_0F45_P_2_LEN_1,
873 MOD_VEX_W_0_0F46_P_0_LEN_1,
874 MOD_VEX_W_1_0F46_P_0_LEN_1,
875 MOD_VEX_W_0_0F46_P_2_LEN_1,
876 MOD_VEX_W_1_0F46_P_2_LEN_1,
877 MOD_VEX_W_0_0F47_P_0_LEN_1,
878 MOD_VEX_W_1_0F47_P_0_LEN_1,
879 MOD_VEX_W_0_0F47_P_2_LEN_1,
880 MOD_VEX_W_1_0F47_P_2_LEN_1,
881 MOD_VEX_W_0_0F4A_P_0_LEN_1,
882 MOD_VEX_W_1_0F4A_P_0_LEN_1,
883 MOD_VEX_W_0_0F4A_P_2_LEN_1,
884 MOD_VEX_W_1_0F4A_P_2_LEN_1,
885 MOD_VEX_W_0_0F4B_P_0_LEN_1,
886 MOD_VEX_W_1_0F4B_P_0_LEN_1,
887 MOD_VEX_W_0_0F4B_P_2_LEN_1,
899 MOD_VEX_W_0_0F91_P_0_LEN_0,
900 MOD_VEX_W_1_0F91_P_0_LEN_0,
901 MOD_VEX_W_0_0F91_P_2_LEN_0,
902 MOD_VEX_W_1_0F91_P_2_LEN_0,
903 MOD_VEX_W_0_0F92_P_0_LEN_0,
904 MOD_VEX_W_0_0F92_P_2_LEN_0,
905 MOD_VEX_0F92_P_3_LEN_0,
906 MOD_VEX_W_0_0F93_P_0_LEN_0,
907 MOD_VEX_W_0_0F93_P_2_LEN_0,
908 MOD_VEX_0F93_P_3_LEN_0,
909 MOD_VEX_W_0_0F98_P_0_LEN_0,
910 MOD_VEX_W_1_0F98_P_0_LEN_0,
911 MOD_VEX_W_0_0F98_P_2_LEN_0,
912 MOD_VEX_W_1_0F98_P_2_LEN_0,
913 MOD_VEX_W_0_0F99_P_0_LEN_0,
914 MOD_VEX_W_1_0F99_P_0_LEN_0,
915 MOD_VEX_W_0_0F99_P_2_LEN_0,
916 MOD_VEX_W_1_0F99_P_2_LEN_0,
919 MOD_VEX_0FD7_PREFIX_2,
920 MOD_VEX_0FE7_PREFIX_2,
921 MOD_VEX_0FF0_PREFIX_3,
922 MOD_VEX_0F381A_PREFIX_2,
923 MOD_VEX_0F382A_PREFIX_2,
924 MOD_VEX_0F382C_PREFIX_2,
925 MOD_VEX_0F382D_PREFIX_2,
926 MOD_VEX_0F382E_PREFIX_2,
927 MOD_VEX_0F382F_PREFIX_2,
928 MOD_VEX_0F385A_PREFIX_2,
929 MOD_VEX_0F388C_PREFIX_2,
930 MOD_VEX_0F388E_PREFIX_2,
931 MOD_VEX_W_0_0F3A30_P_2_LEN_0,
932 MOD_VEX_W_1_0F3A30_P_2_LEN_0,
933 MOD_VEX_W_0_0F3A31_P_2_LEN_0,
934 MOD_VEX_W_1_0F3A31_P_2_LEN_0,
935 MOD_VEX_W_0_0F3A32_P_2_LEN_0,
936 MOD_VEX_W_1_0F3A32_P_2_LEN_0,
937 MOD_VEX_W_0_0F3A33_P_2_LEN_0,
938 MOD_VEX_W_1_0F3A33_P_2_LEN_0,
940 MOD_EVEX_0F10_PREFIX_1,
941 MOD_EVEX_0F10_PREFIX_3,
942 MOD_EVEX_0F11_PREFIX_1,
943 MOD_EVEX_0F11_PREFIX_3,
944 MOD_EVEX_0F12_PREFIX_0,
945 MOD_EVEX_0F16_PREFIX_0,
946 MOD_EVEX_0F38C6_REG_1,
947 MOD_EVEX_0F38C6_REG_2,
948 MOD_EVEX_0F38C6_REG_5,
949 MOD_EVEX_0F38C6_REG_6,
950 MOD_EVEX_0F38C7_REG_1,
951 MOD_EVEX_0F38C7_REG_2,
952 MOD_EVEX_0F38C7_REG_5,
953 MOD_EVEX_0F38C7_REG_6
974 PREFIX_MOD_0_0F01_REG_5,
975 PREFIX_MOD_3_0F01_REG_5_RM_0,
976 PREFIX_MOD_3_0F01_REG_5_RM_2,
1022 PREFIX_MOD_0_0FAE_REG_4,
1023 PREFIX_MOD_3_0FAE_REG_4,
1024 PREFIX_MOD_0_0FAE_REG_5,
1025 PREFIX_MOD_3_0FAE_REG_5,
1026 PREFIX_MOD_0_0FAE_REG_6,
1027 PREFIX_MOD_1_0FAE_REG_6,
1034 PREFIX_MOD_0_0FC7_REG_6,
1035 PREFIX_MOD_3_0FC7_REG_6,
1036 PREFIX_MOD_3_0FC7_REG_7,
1166 PREFIX_VEX_0F71_REG_2,
1167 PREFIX_VEX_0F71_REG_4,
1168 PREFIX_VEX_0F71_REG_6,
1169 PREFIX_VEX_0F72_REG_2,
1170 PREFIX_VEX_0F72_REG_4,
1171 PREFIX_VEX_0F72_REG_6,
1172 PREFIX_VEX_0F73_REG_2,
1173 PREFIX_VEX_0F73_REG_3,
1174 PREFIX_VEX_0F73_REG_6,
1175 PREFIX_VEX_0F73_REG_7,
1348 PREFIX_VEX_0F38F3_REG_1,
1349 PREFIX_VEX_0F38F3_REG_2,
1350 PREFIX_VEX_0F38F3_REG_3,
1469 PREFIX_EVEX_0F71_REG_2,
1470 PREFIX_EVEX_0F71_REG_4,
1471 PREFIX_EVEX_0F71_REG_6,
1472 PREFIX_EVEX_0F72_REG_0,
1473 PREFIX_EVEX_0F72_REG_1,
1474 PREFIX_EVEX_0F72_REG_2,
1475 PREFIX_EVEX_0F72_REG_4,
1476 PREFIX_EVEX_0F72_REG_6,
1477 PREFIX_EVEX_0F73_REG_2,
1478 PREFIX_EVEX_0F73_REG_3,
1479 PREFIX_EVEX_0F73_REG_6,
1480 PREFIX_EVEX_0F73_REG_7,
1677 PREFIX_EVEX_0F38C6_REG_1,
1678 PREFIX_EVEX_0F38C6_REG_2,
1679 PREFIX_EVEX_0F38C6_REG_5,
1680 PREFIX_EVEX_0F38C6_REG_6,
1681 PREFIX_EVEX_0F38C7_REG_1,
1682 PREFIX_EVEX_0F38C7_REG_2,
1683 PREFIX_EVEX_0F38C7_REG_5,
1684 PREFIX_EVEX_0F38C7_REG_6,
1786 THREE_BYTE_0F38 = 0,
1813 VEX_LEN_0F12_P_0_M_0 = 0,
1814 VEX_LEN_0F12_P_0_M_1,
1817 VEX_LEN_0F16_P_0_M_0,
1818 VEX_LEN_0F16_P_0_M_1,
1855 VEX_LEN_0FAE_R_2_M_0,
1856 VEX_LEN_0FAE_R_3_M_0,
1863 VEX_LEN_0F381A_P_2_M_0,
1866 VEX_LEN_0F385A_P_2_M_0,
1869 VEX_LEN_0F38F3_R_1_P_0,
1870 VEX_LEN_0F38F3_R_2_P_0,
1871 VEX_LEN_0F38F3_R_3_P_0,
1914 VEX_LEN_0FXOP_08_CC,
1915 VEX_LEN_0FXOP_08_CD,
1916 VEX_LEN_0FXOP_08_CE,
1917 VEX_LEN_0FXOP_08_CF,
1918 VEX_LEN_0FXOP_08_EC,
1919 VEX_LEN_0FXOP_08_ED,
1920 VEX_LEN_0FXOP_08_EE,
1921 VEX_LEN_0FXOP_08_EF,
1922 VEX_LEN_0FXOP_09_80,
1928 EVEX_LEN_0F6E_P_2 = 0,
1932 EVEX_LEN_0F3819_P_2_W_0,
1933 EVEX_LEN_0F3819_P_2_W_1,
1934 EVEX_LEN_0F381A_P_2_W_0,
1935 EVEX_LEN_0F381A_P_2_W_1,
1936 EVEX_LEN_0F381B_P_2_W_0,
1937 EVEX_LEN_0F381B_P_2_W_1,
1938 EVEX_LEN_0F385A_P_2_W_0,
1939 EVEX_LEN_0F385A_P_2_W_1,
1940 EVEX_LEN_0F385B_P_2_W_0,
1941 EVEX_LEN_0F385B_P_2_W_1,
1942 EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1943 EVEX_LEN_0F38C6_REG_2_PREFIX_2,
1944 EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1945 EVEX_LEN_0F38C6_REG_6_PREFIX_2,
1946 EVEX_LEN_0F38C7_R_1_P_2_W_0,
1947 EVEX_LEN_0F38C7_R_1_P_2_W_1,
1948 EVEX_LEN_0F38C7_R_2_P_2_W_0,
1949 EVEX_LEN_0F38C7_R_2_P_2_W_1,
1950 EVEX_LEN_0F38C7_R_5_P_2_W_0,
1951 EVEX_LEN_0F38C7_R_5_P_2_W_1,
1952 EVEX_LEN_0F38C7_R_6_P_2_W_0,
1953 EVEX_LEN_0F38C7_R_6_P_2_W_1,
1954 EVEX_LEN_0F3A18_P_2_W_0,
1955 EVEX_LEN_0F3A18_P_2_W_1,
1956 EVEX_LEN_0F3A19_P_2_W_0,
1957 EVEX_LEN_0F3A19_P_2_W_1,
1958 EVEX_LEN_0F3A1A_P_2_W_0,
1959 EVEX_LEN_0F3A1A_P_2_W_1,
1960 EVEX_LEN_0F3A1B_P_2_W_0,
1961 EVEX_LEN_0F3A1B_P_2_W_1,
1962 EVEX_LEN_0F3A23_P_2_W_0,
1963 EVEX_LEN_0F3A23_P_2_W_1,
1964 EVEX_LEN_0F3A38_P_2_W_0,
1965 EVEX_LEN_0F3A38_P_2_W_1,
1966 EVEX_LEN_0F3A39_P_2_W_0,
1967 EVEX_LEN_0F3A39_P_2_W_1,
1968 EVEX_LEN_0F3A3A_P_2_W_0,
1969 EVEX_LEN_0F3A3A_P_2_W_1,
1970 EVEX_LEN_0F3A3B_P_2_W_0,
1971 EVEX_LEN_0F3A3B_P_2_W_1,
1972 EVEX_LEN_0F3A43_P_2_W_0,
1973 EVEX_LEN_0F3A43_P_2_W_1
1978 VEX_W_0F41_P_0_LEN_1 = 0,
1979 VEX_W_0F41_P_2_LEN_1,
1980 VEX_W_0F42_P_0_LEN_1,
1981 VEX_W_0F42_P_2_LEN_1,
1982 VEX_W_0F44_P_0_LEN_0,
1983 VEX_W_0F44_P_2_LEN_0,
1984 VEX_W_0F45_P_0_LEN_1,
1985 VEX_W_0F45_P_2_LEN_1,
1986 VEX_W_0F46_P_0_LEN_1,
1987 VEX_W_0F46_P_2_LEN_1,
1988 VEX_W_0F47_P_0_LEN_1,
1989 VEX_W_0F47_P_2_LEN_1,
1990 VEX_W_0F4A_P_0_LEN_1,
1991 VEX_W_0F4A_P_2_LEN_1,
1992 VEX_W_0F4B_P_0_LEN_1,
1993 VEX_W_0F4B_P_2_LEN_1,
1994 VEX_W_0F90_P_0_LEN_0,
1995 VEX_W_0F90_P_2_LEN_0,
1996 VEX_W_0F91_P_0_LEN_0,
1997 VEX_W_0F91_P_2_LEN_0,
1998 VEX_W_0F92_P_0_LEN_0,
1999 VEX_W_0F92_P_2_LEN_0,
2000 VEX_W_0F93_P_0_LEN_0,
2001 VEX_W_0F93_P_2_LEN_0,
2002 VEX_W_0F98_P_0_LEN_0,
2003 VEX_W_0F98_P_2_LEN_0,
2004 VEX_W_0F99_P_0_LEN_0,
2005 VEX_W_0F99_P_2_LEN_0,
2013 VEX_W_0F381A_P_2_M_0,
2014 VEX_W_0F382C_P_2_M_0,
2015 VEX_W_0F382D_P_2_M_0,
2016 VEX_W_0F382E_P_2_M_0,
2017 VEX_W_0F382F_P_2_M_0,
2022 VEX_W_0F385A_P_2_M_0,
2034 VEX_W_0F3A30_P_2_LEN_0,
2035 VEX_W_0F3A31_P_2_LEN_0,
2036 VEX_W_0F3A32_P_2_LEN_0,
2037 VEX_W_0F3A33_P_2_LEN_0,
2050 EVEX_W_0F10_P_1_M_0,
2051 EVEX_W_0F10_P_1_M_1,
2053 EVEX_W_0F10_P_3_M_0,
2054 EVEX_W_0F10_P_3_M_1,
2056 EVEX_W_0F11_P_1_M_0,
2057 EVEX_W_0F11_P_1_M_1,
2059 EVEX_W_0F11_P_3_M_0,
2060 EVEX_W_0F11_P_3_M_1,
2061 EVEX_W_0F12_P_0_M_0,
2062 EVEX_W_0F12_P_0_M_1,
2072 EVEX_W_0F16_P_0_M_0,
2073 EVEX_W_0F16_P_0_M_1,
2142 EVEX_W_0F72_R_2_P_2,
2143 EVEX_W_0F72_R_6_P_2,
2144 EVEX_W_0F73_R_2_P_2,
2145 EVEX_W_0F73_R_6_P_2,
2255 EVEX_W_0F38C7_R_1_P_2,
2256 EVEX_W_0F38C7_R_2_P_2,
2257 EVEX_W_0F38C7_R_5_P_2,
2258 EVEX_W_0F38C7_R_6_P_2,
2297 typedef void (*op_rtn) (int bytemode, int sizeflag);
2306 unsigned int prefix_requirement;
2309 /* Upper case letters in the instruction names here are macros.
2310 'A' => print 'b' if no register operands or suffix_always is true
2311 'B' => print 'b' if suffix_always is true
2312 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2314 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2315 suffix_always is true
2316 'E' => print 'e' if 32-bit form of jcxz
2317 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2318 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2319 'H' => print ",pt" or ",pn" branch hint
2320 'I' => honor following macro letter even in Intel mode (implemented only
2321 for some of the macro letters)
2323 'K' => print 'd' or 'q' if rex prefix is present.
2324 'L' => print 'l' if suffix_always is true
2325 'M' => print 'r' if intel_mnemonic is false.
2326 'N' => print 'n' if instruction has no wait "prefix"
2327 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2328 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2329 or suffix_always is true. print 'q' if rex prefix is present.
2330 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2332 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2333 'S' => print 'w', 'l' or 'q' if suffix_always is true
2334 'T' => print 'q' in 64bit mode if instruction has no operand size
2335 prefix and behave as 'P' otherwise
2336 'U' => print 'q' in 64bit mode if instruction has no operand size
2337 prefix and behave as 'Q' otherwise
2338 'V' => print 'q' in 64bit mode if instruction has no operand size
2339 prefix and behave as 'S' otherwise
2340 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2341 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2343 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2344 '!' => change condition from true to false or from false to true.
2345 '%' => add 1 upper case letter to the macro.
2346 '^' => print 'w' or 'l' depending on operand size prefix or
2347 suffix_always is true (lcall/ljmp).
2348 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2349 on operand size prefix.
2350 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2351 has no operand size prefix for AMD64 ISA, behave as 'P'
2354 2 upper case letter macros:
2355 "XY" => print 'x' or 'y' if suffix_always is true or no register
2356 operands and no broadcast.
2357 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2358 register operands and no broadcast.
2359 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2360 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2361 or suffix_always is true
2362 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2363 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2364 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2365 "LW" => print 'd', 'q' depending on the VEX.W bit
2366 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2367 an operand size prefix, or suffix_always is true. print
2368 'q' if rex prefix is present.
2370 Many of the above letters print nothing in Intel mode. See "putop"
2373 Braces '{' and '}', and vertical bars '|', indicate alternative
2374 mnemonic strings for AT&T and Intel. */
2376 static const struct dis386 dis386[] = {
2378 { "addB", { Ebh1, Gb }, 0 },
2379 { "addS", { Evh1, Gv }, 0 },
2380 { "addB", { Gb, EbS }, 0 },
2381 { "addS", { Gv, EvS }, 0 },
2382 { "addB", { AL, Ib }, 0 },
2383 { "addS", { eAX, Iv }, 0 },
2384 { X86_64_TABLE (X86_64_06) },
2385 { X86_64_TABLE (X86_64_07) },
2387 { "orB", { Ebh1, Gb }, 0 },
2388 { "orS", { Evh1, Gv }, 0 },
2389 { "orB", { Gb, EbS }, 0 },
2390 { "orS", { Gv, EvS }, 0 },
2391 { "orB", { AL, Ib }, 0 },
2392 { "orS", { eAX, Iv }, 0 },
2393 { X86_64_TABLE (X86_64_0D) },
2394 { Bad_Opcode }, /* 0x0f extended opcode escape */
2396 { "adcB", { Ebh1, Gb }, 0 },
2397 { "adcS", { Evh1, Gv }, 0 },
2398 { "adcB", { Gb, EbS }, 0 },
2399 { "adcS", { Gv, EvS }, 0 },
2400 { "adcB", { AL, Ib }, 0 },
2401 { "adcS", { eAX, Iv }, 0 },
2402 { X86_64_TABLE (X86_64_16) },
2403 { X86_64_TABLE (X86_64_17) },
2405 { "sbbB", { Ebh1, Gb }, 0 },
2406 { "sbbS", { Evh1, Gv }, 0 },
2407 { "sbbB", { Gb, EbS }, 0 },
2408 { "sbbS", { Gv, EvS }, 0 },
2409 { "sbbB", { AL, Ib }, 0 },
2410 { "sbbS", { eAX, Iv }, 0 },
2411 { X86_64_TABLE (X86_64_1E) },
2412 { X86_64_TABLE (X86_64_1F) },
2414 { "andB", { Ebh1, Gb }, 0 },
2415 { "andS", { Evh1, Gv }, 0 },
2416 { "andB", { Gb, EbS }, 0 },
2417 { "andS", { Gv, EvS }, 0 },
2418 { "andB", { AL, Ib }, 0 },
2419 { "andS", { eAX, Iv }, 0 },
2420 { Bad_Opcode }, /* SEG ES prefix */
2421 { X86_64_TABLE (X86_64_27) },
2423 { "subB", { Ebh1, Gb }, 0 },
2424 { "subS", { Evh1, Gv }, 0 },
2425 { "subB", { Gb, EbS }, 0 },
2426 { "subS", { Gv, EvS }, 0 },
2427 { "subB", { AL, Ib }, 0 },
2428 { "subS", { eAX, Iv }, 0 },
2429 { Bad_Opcode }, /* SEG CS prefix */
2430 { X86_64_TABLE (X86_64_2F) },
2432 { "xorB", { Ebh1, Gb }, 0 },
2433 { "xorS", { Evh1, Gv }, 0 },
2434 { "xorB", { Gb, EbS }, 0 },
2435 { "xorS", { Gv, EvS }, 0 },
2436 { "xorB", { AL, Ib }, 0 },
2437 { "xorS", { eAX, Iv }, 0 },
2438 { Bad_Opcode }, /* SEG SS prefix */
2439 { X86_64_TABLE (X86_64_37) },
2441 { "cmpB", { Eb, Gb }, 0 },
2442 { "cmpS", { Ev, Gv }, 0 },
2443 { "cmpB", { Gb, EbS }, 0 },
2444 { "cmpS", { Gv, EvS }, 0 },
2445 { "cmpB", { AL, Ib }, 0 },
2446 { "cmpS", { eAX, Iv }, 0 },
2447 { Bad_Opcode }, /* SEG DS prefix */
2448 { X86_64_TABLE (X86_64_3F) },
2450 { "inc{S|}", { RMeAX }, 0 },
2451 { "inc{S|}", { RMeCX }, 0 },
2452 { "inc{S|}", { RMeDX }, 0 },
2453 { "inc{S|}", { RMeBX }, 0 },
2454 { "inc{S|}", { RMeSP }, 0 },
2455 { "inc{S|}", { RMeBP }, 0 },
2456 { "inc{S|}", { RMeSI }, 0 },
2457 { "inc{S|}", { RMeDI }, 0 },
2459 { "dec{S|}", { RMeAX }, 0 },
2460 { "dec{S|}", { RMeCX }, 0 },
2461 { "dec{S|}", { RMeDX }, 0 },
2462 { "dec{S|}", { RMeBX }, 0 },
2463 { "dec{S|}", { RMeSP }, 0 },
2464 { "dec{S|}", { RMeBP }, 0 },
2465 { "dec{S|}", { RMeSI }, 0 },
2466 { "dec{S|}", { RMeDI }, 0 },
2468 { "pushV", { RMrAX }, 0 },
2469 { "pushV", { RMrCX }, 0 },
2470 { "pushV", { RMrDX }, 0 },
2471 { "pushV", { RMrBX }, 0 },
2472 { "pushV", { RMrSP }, 0 },
2473 { "pushV", { RMrBP }, 0 },
2474 { "pushV", { RMrSI }, 0 },
2475 { "pushV", { RMrDI }, 0 },
2477 { "popV", { RMrAX }, 0 },
2478 { "popV", { RMrCX }, 0 },
2479 { "popV", { RMrDX }, 0 },
2480 { "popV", { RMrBX }, 0 },
2481 { "popV", { RMrSP }, 0 },
2482 { "popV", { RMrBP }, 0 },
2483 { "popV", { RMrSI }, 0 },
2484 { "popV", { RMrDI }, 0 },
2486 { X86_64_TABLE (X86_64_60) },
2487 { X86_64_TABLE (X86_64_61) },
2488 { X86_64_TABLE (X86_64_62) },
2489 { X86_64_TABLE (X86_64_63) },
2490 { Bad_Opcode }, /* seg fs */
2491 { Bad_Opcode }, /* seg gs */
2492 { Bad_Opcode }, /* op size prefix */
2493 { Bad_Opcode }, /* adr size prefix */
2495 { "pushT", { sIv }, 0 },
2496 { "imulS", { Gv, Ev, Iv }, 0 },
2497 { "pushT", { sIbT }, 0 },
2498 { "imulS", { Gv, Ev, sIb }, 0 },
2499 { "ins{b|}", { Ybr, indirDX }, 0 },
2500 { X86_64_TABLE (X86_64_6D) },
2501 { "outs{b|}", { indirDXr, Xb }, 0 },
2502 { X86_64_TABLE (X86_64_6F) },
2504 { "joH", { Jb, BND, cond_jump_flag }, 0 },
2505 { "jnoH", { Jb, BND, cond_jump_flag }, 0 },
2506 { "jbH", { Jb, BND, cond_jump_flag }, 0 },
2507 { "jaeH", { Jb, BND, cond_jump_flag }, 0 },
2508 { "jeH", { Jb, BND, cond_jump_flag }, 0 },
2509 { "jneH", { Jb, BND, cond_jump_flag }, 0 },
2510 { "jbeH", { Jb, BND, cond_jump_flag }, 0 },
2511 { "jaH", { Jb, BND, cond_jump_flag }, 0 },
2513 { "jsH", { Jb, BND, cond_jump_flag }, 0 },
2514 { "jnsH", { Jb, BND, cond_jump_flag }, 0 },
2515 { "jpH", { Jb, BND, cond_jump_flag }, 0 },
2516 { "jnpH", { Jb, BND, cond_jump_flag }, 0 },
2517 { "jlH", { Jb, BND, cond_jump_flag }, 0 },
2518 { "jgeH", { Jb, BND, cond_jump_flag }, 0 },
2519 { "jleH", { Jb, BND, cond_jump_flag }, 0 },
2520 { "jgH", { Jb, BND, cond_jump_flag }, 0 },
2522 { REG_TABLE (REG_80) },
2523 { REG_TABLE (REG_81) },
2524 { X86_64_TABLE (X86_64_82) },
2525 { REG_TABLE (REG_83) },
2526 { "testB", { Eb, Gb }, 0 },
2527 { "testS", { Ev, Gv }, 0 },
2528 { "xchgB", { Ebh2, Gb }, 0 },
2529 { "xchgS", { Evh2, Gv }, 0 },
2531 { "movB", { Ebh3, Gb }, 0 },
2532 { "movS", { Evh3, Gv }, 0 },
2533 { "movB", { Gb, EbS }, 0 },
2534 { "movS", { Gv, EvS }, 0 },
2535 { "movD", { Sv, Sw }, 0 },
2536 { MOD_TABLE (MOD_8D) },
2537 { "movD", { Sw, Sv }, 0 },
2538 { REG_TABLE (REG_8F) },
2540 { PREFIX_TABLE (PREFIX_90) },
2541 { "xchgS", { RMeCX, eAX }, 0 },
2542 { "xchgS", { RMeDX, eAX }, 0 },
2543 { "xchgS", { RMeBX, eAX }, 0 },
2544 { "xchgS", { RMeSP, eAX }, 0 },
2545 { "xchgS", { RMeBP, eAX }, 0 },
2546 { "xchgS", { RMeSI, eAX }, 0 },
2547 { "xchgS", { RMeDI, eAX }, 0 },
2549 { "cW{t|}R", { XX }, 0 },
2550 { "cR{t|}O", { XX }, 0 },
2551 { X86_64_TABLE (X86_64_9A) },
2552 { Bad_Opcode }, /* fwait */
2553 { "pushfT", { XX }, 0 },
2554 { "popfT", { XX }, 0 },
2555 { "sahf", { XX }, 0 },
2556 { "lahf", { XX }, 0 },
2558 { "mov%LB", { AL, Ob }, 0 },
2559 { "mov%LS", { eAX, Ov }, 0 },
2560 { "mov%LB", { Ob, AL }, 0 },
2561 { "mov%LS", { Ov, eAX }, 0 },
2562 { "movs{b|}", { Ybr, Xb }, 0 },
2563 { "movs{R|}", { Yvr, Xv }, 0 },
2564 { "cmps{b|}", { Xb, Yb }, 0 },
2565 { "cmps{R|}", { Xv, Yv }, 0 },
2567 { "testB", { AL, Ib }, 0 },
2568 { "testS", { eAX, Iv }, 0 },
2569 { "stosB", { Ybr, AL }, 0 },
2570 { "stosS", { Yvr, eAX }, 0 },
2571 { "lodsB", { ALr, Xb }, 0 },
2572 { "lodsS", { eAXr, Xv }, 0 },
2573 { "scasB", { AL, Yb }, 0 },
2574 { "scasS", { eAX, Yv }, 0 },
2576 { "movB", { RMAL, Ib }, 0 },
2577 { "movB", { RMCL, Ib }, 0 },
2578 { "movB", { RMDL, Ib }, 0 },
2579 { "movB", { RMBL, Ib }, 0 },
2580 { "movB", { RMAH, Ib }, 0 },
2581 { "movB", { RMCH, Ib }, 0 },
2582 { "movB", { RMDH, Ib }, 0 },
2583 { "movB", { RMBH, Ib }, 0 },
2585 { "mov%LV", { RMeAX, Iv64 }, 0 },
2586 { "mov%LV", { RMeCX, Iv64 }, 0 },
2587 { "mov%LV", { RMeDX, Iv64 }, 0 },
2588 { "mov%LV", { RMeBX, Iv64 }, 0 },
2589 { "mov%LV", { RMeSP, Iv64 }, 0 },
2590 { "mov%LV", { RMeBP, Iv64 }, 0 },
2591 { "mov%LV", { RMeSI, Iv64 }, 0 },
2592 { "mov%LV", { RMeDI, Iv64 }, 0 },
2594 { REG_TABLE (REG_C0) },
2595 { REG_TABLE (REG_C1) },
2596 { "retT", { Iw, BND }, 0 },
2597 { "retT", { BND }, 0 },
2598 { X86_64_TABLE (X86_64_C4) },
2599 { X86_64_TABLE (X86_64_C5) },
2600 { REG_TABLE (REG_C6) },
2601 { REG_TABLE (REG_C7) },
2603 { "enterT", { Iw, Ib }, 0 },
2604 { "leaveT", { XX }, 0 },
2605 { "Jret{|f}P", { Iw }, 0 },
2606 { "Jret{|f}P", { XX }, 0 },
2607 { "int3", { XX }, 0 },
2608 { "int", { Ib }, 0 },
2609 { X86_64_TABLE (X86_64_CE) },
2610 { "iret%LP", { XX }, 0 },
2612 { REG_TABLE (REG_D0) },
2613 { REG_TABLE (REG_D1) },
2614 { REG_TABLE (REG_D2) },
2615 { REG_TABLE (REG_D3) },
2616 { X86_64_TABLE (X86_64_D4) },
2617 { X86_64_TABLE (X86_64_D5) },
2619 { "xlat", { DSBX }, 0 },
2630 { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 },
2631 { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 },
2632 { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 },
2633 { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 },
2634 { "inB", { AL, Ib }, 0 },
2635 { "inG", { zAX, Ib }, 0 },
2636 { "outB", { Ib, AL }, 0 },
2637 { "outG", { Ib, zAX }, 0 },
2639 { X86_64_TABLE (X86_64_E8) },
2640 { X86_64_TABLE (X86_64_E9) },
2641 { X86_64_TABLE (X86_64_EA) },
2642 { "jmp", { Jb, BND }, 0 },
2643 { "inB", { AL, indirDX }, 0 },
2644 { "inG", { zAX, indirDX }, 0 },
2645 { "outB", { indirDX, AL }, 0 },
2646 { "outG", { indirDX, zAX }, 0 },
2648 { Bad_Opcode }, /* lock prefix */
2649 { "icebp", { XX }, 0 },
2650 { Bad_Opcode }, /* repne */
2651 { Bad_Opcode }, /* repz */
2652 { "hlt", { XX }, 0 },
2653 { "cmc", { XX }, 0 },
2654 { REG_TABLE (REG_F6) },
2655 { REG_TABLE (REG_F7) },
2657 { "clc", { XX }, 0 },
2658 { "stc", { XX }, 0 },
2659 { "cli", { XX }, 0 },
2660 { "sti", { XX }, 0 },
2661 { "cld", { XX }, 0 },
2662 { "std", { XX }, 0 },
2663 { REG_TABLE (REG_FE) },
2664 { REG_TABLE (REG_FF) },
2667 static const struct dis386 dis386_twobyte[] = {
2669 { REG_TABLE (REG_0F00 ) },
2670 { REG_TABLE (REG_0F01 ) },
2671 { "larS", { Gv, Ew }, 0 },
2672 { "lslS", { Gv, Ew }, 0 },
2674 { "syscall", { XX }, 0 },
2675 { "clts", { XX }, 0 },
2676 { "sysret%LP", { XX }, 0 },
2678 { "invd", { XX }, 0 },
2679 { PREFIX_TABLE (PREFIX_0F09) },
2681 { "ud2", { XX }, 0 },
2683 { REG_TABLE (REG_0F0D) },
2684 { "femms", { XX }, 0 },
2685 { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */
2687 { PREFIX_TABLE (PREFIX_0F10) },
2688 { PREFIX_TABLE (PREFIX_0F11) },
2689 { PREFIX_TABLE (PREFIX_0F12) },
2690 { MOD_TABLE (MOD_0F13) },
2691 { "unpcklpX", { XM, EXx }, PREFIX_OPCODE },
2692 { "unpckhpX", { XM, EXx }, PREFIX_OPCODE },
2693 { PREFIX_TABLE (PREFIX_0F16) },
2694 { MOD_TABLE (MOD_0F17) },
2696 { REG_TABLE (REG_0F18) },
2697 { "nopQ", { Ev }, 0 },
2698 { PREFIX_TABLE (PREFIX_0F1A) },
2699 { PREFIX_TABLE (PREFIX_0F1B) },
2700 { PREFIX_TABLE (PREFIX_0F1C) },
2701 { "nopQ", { Ev }, 0 },
2702 { PREFIX_TABLE (PREFIX_0F1E) },
2703 { "nopQ", { Ev }, 0 },
2705 { "movZ", { Rm, Cm }, 0 },
2706 { "movZ", { Rm, Dm }, 0 },
2707 { "movZ", { Cm, Rm }, 0 },
2708 { "movZ", { Dm, Rm }, 0 },
2709 { MOD_TABLE (MOD_0F24) },
2711 { MOD_TABLE (MOD_0F26) },
2714 { "movapX", { XM, EXx }, PREFIX_OPCODE },
2715 { "movapX", { EXxS, XM }, PREFIX_OPCODE },
2716 { PREFIX_TABLE (PREFIX_0F2A) },
2717 { PREFIX_TABLE (PREFIX_0F2B) },
2718 { PREFIX_TABLE (PREFIX_0F2C) },
2719 { PREFIX_TABLE (PREFIX_0F2D) },
2720 { PREFIX_TABLE (PREFIX_0F2E) },
2721 { PREFIX_TABLE (PREFIX_0F2F) },
2723 { "wrmsr", { XX }, 0 },
2724 { "rdtsc", { XX }, 0 },
2725 { "rdmsr", { XX }, 0 },
2726 { "rdpmc", { XX }, 0 },
2727 { "sysenter", { XX }, 0 },
2728 { "sysexit", { XX }, 0 },
2730 { "getsec", { XX }, 0 },
2732 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2734 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2741 { "cmovoS", { Gv, Ev }, 0 },
2742 { "cmovnoS", { Gv, Ev }, 0 },
2743 { "cmovbS", { Gv, Ev }, 0 },
2744 { "cmovaeS", { Gv, Ev }, 0 },
2745 { "cmoveS", { Gv, Ev }, 0 },
2746 { "cmovneS", { Gv, Ev }, 0 },
2747 { "cmovbeS", { Gv, Ev }, 0 },
2748 { "cmovaS", { Gv, Ev }, 0 },
2750 { "cmovsS", { Gv, Ev }, 0 },
2751 { "cmovnsS", { Gv, Ev }, 0 },
2752 { "cmovpS", { Gv, Ev }, 0 },
2753 { "cmovnpS", { Gv, Ev }, 0 },
2754 { "cmovlS", { Gv, Ev }, 0 },
2755 { "cmovgeS", { Gv, Ev }, 0 },
2756 { "cmovleS", { Gv, Ev }, 0 },
2757 { "cmovgS", { Gv, Ev }, 0 },
2759 { MOD_TABLE (MOD_0F51) },
2760 { PREFIX_TABLE (PREFIX_0F51) },
2761 { PREFIX_TABLE (PREFIX_0F52) },
2762 { PREFIX_TABLE (PREFIX_0F53) },
2763 { "andpX", { XM, EXx }, PREFIX_OPCODE },
2764 { "andnpX", { XM, EXx }, PREFIX_OPCODE },
2765 { "orpX", { XM, EXx }, PREFIX_OPCODE },
2766 { "xorpX", { XM, EXx }, PREFIX_OPCODE },
2768 { PREFIX_TABLE (PREFIX_0F58) },
2769 { PREFIX_TABLE (PREFIX_0F59) },
2770 { PREFIX_TABLE (PREFIX_0F5A) },
2771 { PREFIX_TABLE (PREFIX_0F5B) },
2772 { PREFIX_TABLE (PREFIX_0F5C) },
2773 { PREFIX_TABLE (PREFIX_0F5D) },
2774 { PREFIX_TABLE (PREFIX_0F5E) },
2775 { PREFIX_TABLE (PREFIX_0F5F) },
2777 { PREFIX_TABLE (PREFIX_0F60) },
2778 { PREFIX_TABLE (PREFIX_0F61) },
2779 { PREFIX_TABLE (PREFIX_0F62) },
2780 { "packsswb", { MX, EM }, PREFIX_OPCODE },
2781 { "pcmpgtb", { MX, EM }, PREFIX_OPCODE },
2782 { "pcmpgtw", { MX, EM }, PREFIX_OPCODE },
2783 { "pcmpgtd", { MX, EM }, PREFIX_OPCODE },
2784 { "packuswb", { MX, EM }, PREFIX_OPCODE },
2786 { "punpckhbw", { MX, EM }, PREFIX_OPCODE },
2787 { "punpckhwd", { MX, EM }, PREFIX_OPCODE },
2788 { "punpckhdq", { MX, EM }, PREFIX_OPCODE },
2789 { "packssdw", { MX, EM }, PREFIX_OPCODE },
2790 { PREFIX_TABLE (PREFIX_0F6C) },
2791 { PREFIX_TABLE (PREFIX_0F6D) },
2792 { "movK", { MX, Edq }, PREFIX_OPCODE },
2793 { PREFIX_TABLE (PREFIX_0F6F) },
2795 { PREFIX_TABLE (PREFIX_0F70) },
2796 { REG_TABLE (REG_0F71) },
2797 { REG_TABLE (REG_0F72) },
2798 { REG_TABLE (REG_0F73) },
2799 { "pcmpeqb", { MX, EM }, PREFIX_OPCODE },
2800 { "pcmpeqw", { MX, EM }, PREFIX_OPCODE },
2801 { "pcmpeqd", { MX, EM }, PREFIX_OPCODE },
2802 { "emms", { XX }, PREFIX_OPCODE },
2804 { PREFIX_TABLE (PREFIX_0F78) },
2805 { PREFIX_TABLE (PREFIX_0F79) },
2808 { PREFIX_TABLE (PREFIX_0F7C) },
2809 { PREFIX_TABLE (PREFIX_0F7D) },
2810 { PREFIX_TABLE (PREFIX_0F7E) },
2811 { PREFIX_TABLE (PREFIX_0F7F) },
2813 { "joH", { Jv, BND, cond_jump_flag }, 0 },
2814 { "jnoH", { Jv, BND, cond_jump_flag }, 0 },
2815 { "jbH", { Jv, BND, cond_jump_flag }, 0 },
2816 { "jaeH", { Jv, BND, cond_jump_flag }, 0 },
2817 { "jeH", { Jv, BND, cond_jump_flag }, 0 },
2818 { "jneH", { Jv, BND, cond_jump_flag }, 0 },
2819 { "jbeH", { Jv, BND, cond_jump_flag }, 0 },
2820 { "jaH", { Jv, BND, cond_jump_flag }, 0 },
2822 { "jsH", { Jv, BND, cond_jump_flag }, 0 },
2823 { "jnsH", { Jv, BND, cond_jump_flag }, 0 },
2824 { "jpH", { Jv, BND, cond_jump_flag }, 0 },
2825 { "jnpH", { Jv, BND, cond_jump_flag }, 0 },
2826 { "jlH", { Jv, BND, cond_jump_flag }, 0 },
2827 { "jgeH", { Jv, BND, cond_jump_flag }, 0 },
2828 { "jleH", { Jv, BND, cond_jump_flag }, 0 },
2829 { "jgH", { Jv, BND, cond_jump_flag }, 0 },
2831 { "seto", { Eb }, 0 },
2832 { "setno", { Eb }, 0 },
2833 { "setb", { Eb }, 0 },
2834 { "setae", { Eb }, 0 },
2835 { "sete", { Eb }, 0 },
2836 { "setne", { Eb }, 0 },
2837 { "setbe", { Eb }, 0 },
2838 { "seta", { Eb }, 0 },
2840 { "sets", { Eb }, 0 },
2841 { "setns", { Eb }, 0 },
2842 { "setp", { Eb }, 0 },
2843 { "setnp", { Eb }, 0 },
2844 { "setl", { Eb }, 0 },
2845 { "setge", { Eb }, 0 },
2846 { "setle", { Eb }, 0 },
2847 { "setg", { Eb }, 0 },
2849 { "pushT", { fs }, 0 },
2850 { "popT", { fs }, 0 },
2851 { "cpuid", { XX }, 0 },
2852 { "btS", { Ev, Gv }, 0 },
2853 { "shldS", { Ev, Gv, Ib }, 0 },
2854 { "shldS", { Ev, Gv, CL }, 0 },
2855 { REG_TABLE (REG_0FA6) },
2856 { REG_TABLE (REG_0FA7) },
2858 { "pushT", { gs }, 0 },
2859 { "popT", { gs }, 0 },
2860 { "rsm", { XX }, 0 },
2861 { "btsS", { Evh1, Gv }, 0 },
2862 { "shrdS", { Ev, Gv, Ib }, 0 },
2863 { "shrdS", { Ev, Gv, CL }, 0 },
2864 { REG_TABLE (REG_0FAE) },
2865 { "imulS", { Gv, Ev }, 0 },
2867 { "cmpxchgB", { Ebh1, Gb }, 0 },
2868 { "cmpxchgS", { Evh1, Gv }, 0 },
2869 { MOD_TABLE (MOD_0FB2) },
2870 { "btrS", { Evh1, Gv }, 0 },
2871 { MOD_TABLE (MOD_0FB4) },
2872 { MOD_TABLE (MOD_0FB5) },
2873 { "movz{bR|x}", { Gv, Eb }, 0 },
2874 { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2876 { PREFIX_TABLE (PREFIX_0FB8) },
2877 { "ud1S", { Gv, Ev }, 0 },
2878 { REG_TABLE (REG_0FBA) },
2879 { "btcS", { Evh1, Gv }, 0 },
2880 { PREFIX_TABLE (PREFIX_0FBC) },
2881 { PREFIX_TABLE (PREFIX_0FBD) },
2882 { "movs{bR|x}", { Gv, Eb }, 0 },
2883 { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2885 { "xaddB", { Ebh1, Gb }, 0 },
2886 { "xaddS", { Evh1, Gv }, 0 },
2887 { PREFIX_TABLE (PREFIX_0FC2) },
2888 { MOD_TABLE (MOD_0FC3) },
2889 { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE },
2890 { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE },
2891 { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE },
2892 { REG_TABLE (REG_0FC7) },
2894 { "bswap", { RMeAX }, 0 },
2895 { "bswap", { RMeCX }, 0 },
2896 { "bswap", { RMeDX }, 0 },
2897 { "bswap", { RMeBX }, 0 },
2898 { "bswap", { RMeSP }, 0 },
2899 { "bswap", { RMeBP }, 0 },
2900 { "bswap", { RMeSI }, 0 },
2901 { "bswap", { RMeDI }, 0 },
2903 { PREFIX_TABLE (PREFIX_0FD0) },
2904 { "psrlw", { MX, EM }, PREFIX_OPCODE },
2905 { "psrld", { MX, EM }, PREFIX_OPCODE },
2906 { "psrlq", { MX, EM }, PREFIX_OPCODE },
2907 { "paddq", { MX, EM }, PREFIX_OPCODE },
2908 { "pmullw", { MX, EM }, PREFIX_OPCODE },
2909 { PREFIX_TABLE (PREFIX_0FD6) },
2910 { MOD_TABLE (MOD_0FD7) },
2912 { "psubusb", { MX, EM }, PREFIX_OPCODE },
2913 { "psubusw", { MX, EM }, PREFIX_OPCODE },
2914 { "pminub", { MX, EM }, PREFIX_OPCODE },
2915 { "pand", { MX, EM }, PREFIX_OPCODE },
2916 { "paddusb", { MX, EM }, PREFIX_OPCODE },
2917 { "paddusw", { MX, EM }, PREFIX_OPCODE },
2918 { "pmaxub", { MX, EM }, PREFIX_OPCODE },
2919 { "pandn", { MX, EM }, PREFIX_OPCODE },
2921 { "pavgb", { MX, EM }, PREFIX_OPCODE },
2922 { "psraw", { MX, EM }, PREFIX_OPCODE },
2923 { "psrad", { MX, EM }, PREFIX_OPCODE },
2924 { "pavgw", { MX, EM }, PREFIX_OPCODE },
2925 { "pmulhuw", { MX, EM }, PREFIX_OPCODE },
2926 { "pmulhw", { MX, EM }, PREFIX_OPCODE },
2927 { PREFIX_TABLE (PREFIX_0FE6) },
2928 { PREFIX_TABLE (PREFIX_0FE7) },
2930 { "psubsb", { MX, EM }, PREFIX_OPCODE },
2931 { "psubsw", { MX, EM }, PREFIX_OPCODE },
2932 { "pminsw", { MX, EM }, PREFIX_OPCODE },
2933 { "por", { MX, EM }, PREFIX_OPCODE },
2934 { "paddsb", { MX, EM }, PREFIX_OPCODE },
2935 { "paddsw", { MX, EM }, PREFIX_OPCODE },
2936 { "pmaxsw", { MX, EM }, PREFIX_OPCODE },
2937 { "pxor", { MX, EM }, PREFIX_OPCODE },
2939 { PREFIX_TABLE (PREFIX_0FF0) },
2940 { "psllw", { MX, EM }, PREFIX_OPCODE },
2941 { "pslld", { MX, EM }, PREFIX_OPCODE },
2942 { "psllq", { MX, EM }, PREFIX_OPCODE },
2943 { "pmuludq", { MX, EM }, PREFIX_OPCODE },
2944 { "pmaddwd", { MX, EM }, PREFIX_OPCODE },
2945 { "psadbw", { MX, EM }, PREFIX_OPCODE },
2946 { PREFIX_TABLE (PREFIX_0FF7) },
2948 { "psubb", { MX, EM }, PREFIX_OPCODE },
2949 { "psubw", { MX, EM }, PREFIX_OPCODE },
2950 { "psubd", { MX, EM }, PREFIX_OPCODE },
2951 { "psubq", { MX, EM }, PREFIX_OPCODE },
2952 { "paddb", { MX, EM }, PREFIX_OPCODE },
2953 { "paddw", { MX, EM }, PREFIX_OPCODE },
2954 { "paddd", { MX, EM }, PREFIX_OPCODE },
2955 { "ud0S", { Gv, Ev }, 0 },
2958 static const unsigned char onebyte_has_modrm[256] = {
2959 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2960 /* ------------------------------- */
2961 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2962 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2963 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2964 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2965 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2966 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2967 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2968 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2969 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2970 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2971 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2972 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2973 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2974 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2975 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2976 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2977 /* ------------------------------- */
2978 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2981 static const unsigned char twobyte_has_modrm[256] = {
2982 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2983 /* ------------------------------- */
2984 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2985 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2986 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2987 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2988 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2989 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2990 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2991 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2992 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2993 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2994 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2995 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2996 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2997 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2998 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2999 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
3000 /* ------------------------------- */
3001 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3004 static char obuf[100];
3006 static char *mnemonicendp;
3007 static char scratchbuf[100];
3008 static unsigned char *start_codep;
3009 static unsigned char *insn_codep;
3010 static unsigned char *codep;
3011 static unsigned char *end_codep;
3012 static int last_lock_prefix;
3013 static int last_repz_prefix;
3014 static int last_repnz_prefix;
3015 static int last_data_prefix;
3016 static int last_addr_prefix;
3017 static int last_rex_prefix;
3018 static int last_seg_prefix;
3019 static int fwait_prefix;
3020 /* The active segment register prefix. */
3021 static int active_seg_prefix;
3022 #define MAX_CODE_LENGTH 15
3023 /* We can up to 14 prefixes since the maximum instruction length is
3025 static int all_prefixes[MAX_CODE_LENGTH - 1];
3026 static disassemble_info *the_info;
3034 static unsigned char need_modrm;
3044 int register_specifier;
3051 int mask_register_specifier;
3057 static unsigned char need_vex;
3058 static unsigned char need_vex_reg;
3059 static unsigned char vex_w_done;
3067 /* If we are accessing mod/rm/reg without need_modrm set, then the
3068 values are stale. Hitting this abort likely indicates that you
3069 need to update onebyte_has_modrm or twobyte_has_modrm. */
3070 #define MODRM_CHECK if (!need_modrm) abort ()
3072 static const char **names64;
3073 static const char **names32;
3074 static const char **names16;
3075 static const char **names8;
3076 static const char **names8rex;
3077 static const char **names_seg;
3078 static const char *index64;
3079 static const char *index32;
3080 static const char **index16;
3081 static const char **names_bnd;
3083 static const char *intel_names64[] = {
3084 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3085 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3087 static const char *intel_names32[] = {
3088 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3089 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3091 static const char *intel_names16[] = {
3092 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3093 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3095 static const char *intel_names8[] = {
3096 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3098 static const char *intel_names8rex[] = {
3099 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3100 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3102 static const char *intel_names_seg[] = {
3103 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3105 static const char *intel_index64 = "riz";
3106 static const char *intel_index32 = "eiz";
3107 static const char *intel_index16[] = {
3108 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3111 static const char *att_names64[] = {
3112 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3113 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3115 static const char *att_names32[] = {
3116 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3117 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3119 static const char *att_names16[] = {
3120 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3121 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3123 static const char *att_names8[] = {
3124 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3126 static const char *att_names8rex[] = {
3127 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3128 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3130 static const char *att_names_seg[] = {
3131 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3133 static const char *att_index64 = "%riz";
3134 static const char *att_index32 = "%eiz";
3135 static const char *att_index16[] = {
3136 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3139 static const char **names_mm;
3140 static const char *intel_names_mm[] = {
3141 "mm0", "mm1", "mm2", "mm3",
3142 "mm4", "mm5", "mm6", "mm7"
3144 static const char *att_names_mm[] = {
3145 "%mm0", "%mm1", "%mm2", "%mm3",
3146 "%mm4", "%mm5", "%mm6", "%mm7"
3149 static const char *intel_names_bnd[] = {
3150 "bnd0", "bnd1", "bnd2", "bnd3"
3153 static const char *att_names_bnd[] = {
3154 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3157 static const char **names_xmm;
3158 static const char *intel_names_xmm[] = {
3159 "xmm0", "xmm1", "xmm2", "xmm3",
3160 "xmm4", "xmm5", "xmm6", "xmm7",
3161 "xmm8", "xmm9", "xmm10", "xmm11",
3162 "xmm12", "xmm13", "xmm14", "xmm15",
3163 "xmm16", "xmm17", "xmm18", "xmm19",
3164 "xmm20", "xmm21", "xmm22", "xmm23",
3165 "xmm24", "xmm25", "xmm26", "xmm27",
3166 "xmm28", "xmm29", "xmm30", "xmm31"
3168 static const char *att_names_xmm[] = {
3169 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3170 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3171 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3172 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3173 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3174 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3175 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3176 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3179 static const char **names_ymm;
3180 static const char *intel_names_ymm[] = {
3181 "ymm0", "ymm1", "ymm2", "ymm3",
3182 "ymm4", "ymm5", "ymm6", "ymm7",
3183 "ymm8", "ymm9", "ymm10", "ymm11",
3184 "ymm12", "ymm13", "ymm14", "ymm15",
3185 "ymm16", "ymm17", "ymm18", "ymm19",
3186 "ymm20", "ymm21", "ymm22", "ymm23",
3187 "ymm24", "ymm25", "ymm26", "ymm27",
3188 "ymm28", "ymm29", "ymm30", "ymm31"
3190 static const char *att_names_ymm[] = {
3191 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3192 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3193 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3194 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3195 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3196 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3197 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3198 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3201 static const char **names_zmm;
3202 static const char *intel_names_zmm[] = {
3203 "zmm0", "zmm1", "zmm2", "zmm3",
3204 "zmm4", "zmm5", "zmm6", "zmm7",
3205 "zmm8", "zmm9", "zmm10", "zmm11",
3206 "zmm12", "zmm13", "zmm14", "zmm15",
3207 "zmm16", "zmm17", "zmm18", "zmm19",
3208 "zmm20", "zmm21", "zmm22", "zmm23",
3209 "zmm24", "zmm25", "zmm26", "zmm27",
3210 "zmm28", "zmm29", "zmm30", "zmm31"
3212 static const char *att_names_zmm[] = {
3213 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3214 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3215 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3216 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3217 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3218 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3219 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3220 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3223 static const char **names_mask;
3224 static const char *intel_names_mask[] = {
3225 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3227 static const char *att_names_mask[] = {
3228 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3231 static const char *names_rounding[] =
3239 static const struct dis386 reg_table[][8] = {
3242 { "addA", { Ebh1, Ib }, 0 },
3243 { "orA", { Ebh1, Ib }, 0 },
3244 { "adcA", { Ebh1, Ib }, 0 },
3245 { "sbbA", { Ebh1, Ib }, 0 },
3246 { "andA", { Ebh1, Ib }, 0 },
3247 { "subA", { Ebh1, Ib }, 0 },
3248 { "xorA", { Ebh1, Ib }, 0 },
3249 { "cmpA", { Eb, Ib }, 0 },
3253 { "addQ", { Evh1, Iv }, 0 },
3254 { "orQ", { Evh1, Iv }, 0 },
3255 { "adcQ", { Evh1, Iv }, 0 },
3256 { "sbbQ", { Evh1, Iv }, 0 },
3257 { "andQ", { Evh1, Iv }, 0 },
3258 { "subQ", { Evh1, Iv }, 0 },
3259 { "xorQ", { Evh1, Iv }, 0 },
3260 { "cmpQ", { Ev, Iv }, 0 },
3264 { "addQ", { Evh1, sIb }, 0 },
3265 { "orQ", { Evh1, sIb }, 0 },
3266 { "adcQ", { Evh1, sIb }, 0 },
3267 { "sbbQ", { Evh1, sIb }, 0 },
3268 { "andQ", { Evh1, sIb }, 0 },
3269 { "subQ", { Evh1, sIb }, 0 },
3270 { "xorQ", { Evh1, sIb }, 0 },
3271 { "cmpQ", { Ev, sIb }, 0 },
3275 { "popU", { stackEv }, 0 },
3276 { XOP_8F_TABLE (XOP_09) },
3280 { XOP_8F_TABLE (XOP_09) },
3284 { "rolA", { Eb, Ib }, 0 },
3285 { "rorA", { Eb, Ib }, 0 },
3286 { "rclA", { Eb, Ib }, 0 },
3287 { "rcrA", { Eb, Ib }, 0 },
3288 { "shlA", { Eb, Ib }, 0 },
3289 { "shrA", { Eb, Ib }, 0 },
3290 { "shlA", { Eb, Ib }, 0 },
3291 { "sarA", { Eb, Ib }, 0 },
3295 { "rolQ", { Ev, Ib }, 0 },
3296 { "rorQ", { Ev, Ib }, 0 },
3297 { "rclQ", { Ev, Ib }, 0 },
3298 { "rcrQ", { Ev, Ib }, 0 },
3299 { "shlQ", { Ev, Ib }, 0 },
3300 { "shrQ", { Ev, Ib }, 0 },
3301 { "shlQ", { Ev, Ib }, 0 },
3302 { "sarQ", { Ev, Ib }, 0 },
3306 { "movA", { Ebh3, Ib }, 0 },
3313 { MOD_TABLE (MOD_C6_REG_7) },
3317 { "movQ", { Evh3, Iv }, 0 },
3324 { MOD_TABLE (MOD_C7_REG_7) },
3328 { "rolA", { Eb, I1 }, 0 },
3329 { "rorA", { Eb, I1 }, 0 },
3330 { "rclA", { Eb, I1 }, 0 },
3331 { "rcrA", { Eb, I1 }, 0 },
3332 { "shlA", { Eb, I1 }, 0 },
3333 { "shrA", { Eb, I1 }, 0 },
3334 { "shlA", { Eb, I1 }, 0 },
3335 { "sarA", { Eb, I1 }, 0 },
3339 { "rolQ", { Ev, I1 }, 0 },
3340 { "rorQ", { Ev, I1 }, 0 },
3341 { "rclQ", { Ev, I1 }, 0 },
3342 { "rcrQ", { Ev, I1 }, 0 },
3343 { "shlQ", { Ev, I1 }, 0 },
3344 { "shrQ", { Ev, I1 }, 0 },
3345 { "shlQ", { Ev, I1 }, 0 },
3346 { "sarQ", { Ev, I1 }, 0 },
3350 { "rolA", { Eb, CL }, 0 },
3351 { "rorA", { Eb, CL }, 0 },
3352 { "rclA", { Eb, CL }, 0 },
3353 { "rcrA", { Eb, CL }, 0 },
3354 { "shlA", { Eb, CL }, 0 },
3355 { "shrA", { Eb, CL }, 0 },
3356 { "shlA", { Eb, CL }, 0 },
3357 { "sarA", { Eb, CL }, 0 },
3361 { "rolQ", { Ev, CL }, 0 },
3362 { "rorQ", { Ev, CL }, 0 },
3363 { "rclQ", { Ev, CL }, 0 },
3364 { "rcrQ", { Ev, CL }, 0 },
3365 { "shlQ", { Ev, CL }, 0 },
3366 { "shrQ", { Ev, CL }, 0 },
3367 { "shlQ", { Ev, CL }, 0 },
3368 { "sarQ", { Ev, CL }, 0 },
3372 { "testA", { Eb, Ib }, 0 },
3373 { "testA", { Eb, Ib }, 0 },
3374 { "notA", { Ebh1 }, 0 },
3375 { "negA", { Ebh1 }, 0 },
3376 { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */
3377 { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */
3378 { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */
3379 { "idivA", { Eb }, 0 }, /* and idiv for consistency. */
3383 { "testQ", { Ev, Iv }, 0 },
3384 { "testQ", { Ev, Iv }, 0 },
3385 { "notQ", { Evh1 }, 0 },
3386 { "negQ", { Evh1 }, 0 },
3387 { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */
3388 { "imulQ", { Ev }, 0 },
3389 { "divQ", { Ev }, 0 },
3390 { "idivQ", { Ev }, 0 },
3394 { "incA", { Ebh1 }, 0 },
3395 { "decA", { Ebh1 }, 0 },
3399 { "incQ", { Evh1 }, 0 },
3400 { "decQ", { Evh1 }, 0 },
3401 { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3402 { MOD_TABLE (MOD_FF_REG_3) },
3403 { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3404 { MOD_TABLE (MOD_FF_REG_5) },
3405 { "pushU", { stackEv }, 0 },
3410 { "sldtD", { Sv }, 0 },
3411 { "strD", { Sv }, 0 },
3412 { "lldt", { Ew }, 0 },
3413 { "ltr", { Ew }, 0 },
3414 { "verr", { Ew }, 0 },
3415 { "verw", { Ew }, 0 },
3421 { MOD_TABLE (MOD_0F01_REG_0) },
3422 { MOD_TABLE (MOD_0F01_REG_1) },
3423 { MOD_TABLE (MOD_0F01_REG_2) },
3424 { MOD_TABLE (MOD_0F01_REG_3) },
3425 { "smswD", { Sv }, 0 },
3426 { MOD_TABLE (MOD_0F01_REG_5) },
3427 { "lmsw", { Ew }, 0 },
3428 { MOD_TABLE (MOD_0F01_REG_7) },
3432 { "prefetch", { Mb }, 0 },
3433 { "prefetchw", { Mb }, 0 },
3434 { "prefetchwt1", { Mb }, 0 },
3435 { "prefetch", { Mb }, 0 },
3436 { "prefetch", { Mb }, 0 },
3437 { "prefetch", { Mb }, 0 },
3438 { "prefetch", { Mb }, 0 },
3439 { "prefetch", { Mb }, 0 },
3443 { MOD_TABLE (MOD_0F18_REG_0) },
3444 { MOD_TABLE (MOD_0F18_REG_1) },
3445 { MOD_TABLE (MOD_0F18_REG_2) },
3446 { MOD_TABLE (MOD_0F18_REG_3) },
3447 { MOD_TABLE (MOD_0F18_REG_4) },
3448 { MOD_TABLE (MOD_0F18_REG_5) },
3449 { MOD_TABLE (MOD_0F18_REG_6) },
3450 { MOD_TABLE (MOD_0F18_REG_7) },
3452 /* REG_0F1C_MOD_0 */
3454 { "cldemote", { Mb }, 0 },
3455 { "nopQ", { Ev }, 0 },
3456 { "nopQ", { Ev }, 0 },
3457 { "nopQ", { Ev }, 0 },
3458 { "nopQ", { Ev }, 0 },
3459 { "nopQ", { Ev }, 0 },
3460 { "nopQ", { Ev }, 0 },
3461 { "nopQ", { Ev }, 0 },
3463 /* REG_0F1E_MOD_3 */
3465 { "nopQ", { Ev }, 0 },
3466 { "rdsspK", { Rdq }, PREFIX_OPCODE },
3467 { "nopQ", { Ev }, 0 },
3468 { "nopQ", { Ev }, 0 },
3469 { "nopQ", { Ev }, 0 },
3470 { "nopQ", { Ev }, 0 },
3471 { "nopQ", { Ev }, 0 },
3472 { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
3478 { MOD_TABLE (MOD_0F71_REG_2) },
3480 { MOD_TABLE (MOD_0F71_REG_4) },
3482 { MOD_TABLE (MOD_0F71_REG_6) },
3488 { MOD_TABLE (MOD_0F72_REG_2) },
3490 { MOD_TABLE (MOD_0F72_REG_4) },
3492 { MOD_TABLE (MOD_0F72_REG_6) },
3498 { MOD_TABLE (MOD_0F73_REG_2) },
3499 { MOD_TABLE (MOD_0F73_REG_3) },
3502 { MOD_TABLE (MOD_0F73_REG_6) },
3503 { MOD_TABLE (MOD_0F73_REG_7) },
3507 { "montmul", { { OP_0f07, 0 } }, 0 },
3508 { "xsha1", { { OP_0f07, 0 } }, 0 },
3509 { "xsha256", { { OP_0f07, 0 } }, 0 },
3513 { "xstore-rng", { { OP_0f07, 0 } }, 0 },
3514 { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 },
3515 { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 },
3516 { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 },
3517 { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 },
3518 { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 },
3522 { MOD_TABLE (MOD_0FAE_REG_0) },
3523 { MOD_TABLE (MOD_0FAE_REG_1) },
3524 { MOD_TABLE (MOD_0FAE_REG_2) },
3525 { MOD_TABLE (MOD_0FAE_REG_3) },
3526 { MOD_TABLE (MOD_0FAE_REG_4) },
3527 { MOD_TABLE (MOD_0FAE_REG_5) },
3528 { MOD_TABLE (MOD_0FAE_REG_6) },
3529 { MOD_TABLE (MOD_0FAE_REG_7) },
3537 { "btQ", { Ev, Ib }, 0 },
3538 { "btsQ", { Evh1, Ib }, 0 },
3539 { "btrQ", { Evh1, Ib }, 0 },
3540 { "btcQ", { Evh1, Ib }, 0 },
3545 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3547 { MOD_TABLE (MOD_0FC7_REG_3) },
3548 { MOD_TABLE (MOD_0FC7_REG_4) },
3549 { MOD_TABLE (MOD_0FC7_REG_5) },
3550 { MOD_TABLE (MOD_0FC7_REG_6) },
3551 { MOD_TABLE (MOD_0FC7_REG_7) },
3557 { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3559 { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3561 { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3567 { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3569 { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3571 { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3577 { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3578 { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3581 { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3582 { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3588 { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3589 { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3591 /* REG_VEX_0F38F3 */
3594 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3595 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3596 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3600 { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3601 { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3605 { "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3606 { "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
3608 /* REG_XOP_TBM_01 */
3611 { "blcfill", { { OP_LWP_E, 0 }, Edq }, 0 },
3612 { "blsfill", { { OP_LWP_E, 0 }, Edq }, 0 },
3613 { "blcs", { { OP_LWP_E, 0 }, Edq }, 0 },
3614 { "tzmsk", { { OP_LWP_E, 0 }, Edq }, 0 },
3615 { "blcic", { { OP_LWP_E, 0 }, Edq }, 0 },
3616 { "blsic", { { OP_LWP_E, 0 }, Edq }, 0 },
3617 { "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 },
3619 /* REG_XOP_TBM_02 */
3622 { "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 },
3627 { "blci", { { OP_LWP_E, 0 }, Edq }, 0 },
3630 #include "i386-dis-evex-reg.h"
3633 static const struct dis386 prefix_table[][4] = {
3636 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3637 { "pause", { XX }, 0 },
3638 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3639 { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3642 /* PREFIX_MOD_0_0F01_REG_5 */
3645 { "rstorssp", { Mq }, PREFIX_OPCODE },
3648 /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3651 { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE },
3654 /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3657 { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE },
3662 { "wbinvd", { XX }, 0 },
3663 { "wbnoinvd", { XX }, 0 },
3668 { "movups", { XM, EXx }, PREFIX_OPCODE },
3669 { "movss", { XM, EXd }, PREFIX_OPCODE },
3670 { "movupd", { XM, EXx }, PREFIX_OPCODE },
3671 { "movsd", { XM, EXq }, PREFIX_OPCODE },
3676 { "movups", { EXxS, XM }, PREFIX_OPCODE },
3677 { "movss", { EXdS, XM }, PREFIX_OPCODE },
3678 { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3679 { "movsd", { EXqS, XM }, PREFIX_OPCODE },
3684 { MOD_TABLE (MOD_0F12_PREFIX_0) },
3685 { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3686 { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3687 { "movddup", { XM, EXq }, PREFIX_OPCODE },
3692 { MOD_TABLE (MOD_0F16_PREFIX_0) },
3693 { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3694 { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3699 { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3700 { "bndcl", { Gbnd, Ev_bnd }, 0 },
3701 { "bndmov", { Gbnd, Ebnd }, 0 },
3702 { "bndcu", { Gbnd, Ev_bnd }, 0 },
3707 { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3708 { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3709 { "bndmov", { EbndS, Gbnd }, 0 },
3710 { "bndcn", { Gbnd, Ev_bnd }, 0 },
3715 { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3716 { "nopQ", { Ev }, PREFIX_OPCODE },
3717 { "nopQ", { Ev }, PREFIX_OPCODE },
3718 { "nopQ", { Ev }, PREFIX_OPCODE },
3723 { "nopQ", { Ev }, PREFIX_OPCODE },
3724 { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3725 { "nopQ", { Ev }, PREFIX_OPCODE },
3726 { "nopQ", { Ev }, PREFIX_OPCODE },
3731 { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3732 { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE },
3733 { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3734 { "cvtsi2sd%LQ", { XM, Edq }, 0 },
3739 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3740 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3741 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3742 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3747 { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3748 { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3749 { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3750 { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3755 { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3756 { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3757 { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3758 { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3763 { "ucomiss",{ XM, EXd }, 0 },
3765 { "ucomisd",{ XM, EXq }, 0 },
3770 { "comiss", { XM, EXd }, 0 },
3772 { "comisd", { XM, EXq }, 0 },
3777 { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3778 { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3779 { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3780 { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
3785 { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
3786 { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
3791 { "rcpps", { XM, EXx }, PREFIX_OPCODE },
3792 { "rcpss", { XM, EXd }, PREFIX_OPCODE },
3797 { "addps", { XM, EXx }, PREFIX_OPCODE },
3798 { "addss", { XM, EXd }, PREFIX_OPCODE },
3799 { "addpd", { XM, EXx }, PREFIX_OPCODE },
3800 { "addsd", { XM, EXq }, PREFIX_OPCODE },
3805 { "mulps", { XM, EXx }, PREFIX_OPCODE },
3806 { "mulss", { XM, EXd }, PREFIX_OPCODE },
3807 { "mulpd", { XM, EXx }, PREFIX_OPCODE },
3808 { "mulsd", { XM, EXq }, PREFIX_OPCODE },
3813 { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
3814 { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
3815 { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
3816 { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
3821 { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
3822 { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
3823 { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
3828 { "subps", { XM, EXx }, PREFIX_OPCODE },
3829 { "subss", { XM, EXd }, PREFIX_OPCODE },
3830 { "subpd", { XM, EXx }, PREFIX_OPCODE },
3831 { "subsd", { XM, EXq }, PREFIX_OPCODE },
3836 { "minps", { XM, EXx }, PREFIX_OPCODE },
3837 { "minss", { XM, EXd }, PREFIX_OPCODE },
3838 { "minpd", { XM, EXx }, PREFIX_OPCODE },
3839 { "minsd", { XM, EXq }, PREFIX_OPCODE },
3844 { "divps", { XM, EXx }, PREFIX_OPCODE },
3845 { "divss", { XM, EXd }, PREFIX_OPCODE },
3846 { "divpd", { XM, EXx }, PREFIX_OPCODE },
3847 { "divsd", { XM, EXq }, PREFIX_OPCODE },
3852 { "maxps", { XM, EXx }, PREFIX_OPCODE },
3853 { "maxss", { XM, EXd }, PREFIX_OPCODE },
3854 { "maxpd", { XM, EXx }, PREFIX_OPCODE },
3855 { "maxsd", { XM, EXq }, PREFIX_OPCODE },
3860 { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3862 { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3867 { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3869 { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3874 { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3876 { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3883 { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
3890 { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
3895 { "movq", { MX, EM }, PREFIX_OPCODE },
3896 { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3897 { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3902 { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3903 { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3904 { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3905 { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3908 /* PREFIX_0F73_REG_3 */
3912 { "psrldq", { XS, Ib }, 0 },
3915 /* PREFIX_0F73_REG_7 */
3919 { "pslldq", { XS, Ib }, 0 },
3924 {"vmread", { Em, Gm }, 0 },
3926 {"extrq", { XS, Ib, Ib }, 0 },
3927 {"insertq", { XM, XS, Ib, Ib }, 0 },
3932 {"vmwrite", { Gm, Em }, 0 },
3934 {"extrq", { XM, XS }, 0 },
3935 {"insertq", { XM, XS }, 0 },
3942 { "haddpd", { XM, EXx }, PREFIX_OPCODE },
3943 { "haddps", { XM, EXx }, PREFIX_OPCODE },
3950 { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
3951 { "hsubps", { XM, EXx }, PREFIX_OPCODE },
3956 { "movK", { Edq, MX }, PREFIX_OPCODE },
3957 { "movq", { XM, EXq }, PREFIX_OPCODE },
3958 { "movK", { Edq, XM }, PREFIX_OPCODE },
3963 { "movq", { EMS, MX }, PREFIX_OPCODE },
3964 { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3965 { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3968 /* PREFIX_0FAE_REG_0 */
3971 { "rdfsbase", { Ev }, 0 },
3974 /* PREFIX_0FAE_REG_1 */
3977 { "rdgsbase", { Ev }, 0 },
3980 /* PREFIX_0FAE_REG_2 */
3983 { "wrfsbase", { Ev }, 0 },
3986 /* PREFIX_0FAE_REG_3 */
3989 { "wrgsbase", { Ev }, 0 },
3992 /* PREFIX_MOD_0_0FAE_REG_4 */
3994 { "xsave", { FXSAVE }, 0 },
3995 { "ptwrite%LQ", { Edq }, 0 },
3998 /* PREFIX_MOD_3_0FAE_REG_4 */
4001 { "ptwrite%LQ", { Edq }, 0 },
4004 /* PREFIX_MOD_0_0FAE_REG_5 */
4006 { "xrstor", { FXSAVE }, PREFIX_OPCODE },
4009 /* PREFIX_MOD_3_0FAE_REG_5 */
4011 { "lfence", { Skip_MODRM }, 0 },
4012 { "incsspK", { Rdq }, PREFIX_OPCODE },
4015 /* PREFIX_MOD_0_0FAE_REG_6 */
4017 { "xsaveopt", { FXSAVE }, PREFIX_OPCODE },
4018 { "clrssbsy", { Mq }, PREFIX_OPCODE },
4019 { "clwb", { Mb }, PREFIX_OPCODE },
4022 /* PREFIX_MOD_1_0FAE_REG_6 */
4024 { RM_TABLE (RM_0FAE_REG_6) },
4025 { "umonitor", { Eva }, PREFIX_OPCODE },
4026 { "tpause", { Edq }, PREFIX_OPCODE },
4027 { "umwait", { Edq }, PREFIX_OPCODE },
4030 /* PREFIX_0FAE_REG_7 */
4032 { "clflush", { Mb }, 0 },
4034 { "clflushopt", { Mb }, 0 },
4040 { "popcntS", { Gv, Ev }, 0 },
4045 { "bsfS", { Gv, Ev }, 0 },
4046 { "tzcntS", { Gv, Ev }, 0 },
4047 { "bsfS", { Gv, Ev }, 0 },
4052 { "bsrS", { Gv, Ev }, 0 },
4053 { "lzcntS", { Gv, Ev }, 0 },
4054 { "bsrS", { Gv, Ev }, 0 },
4059 { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE },
4060 { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE },
4061 { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE },
4062 { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE },
4065 /* PREFIX_MOD_0_0FC3 */
4067 { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
4070 /* PREFIX_MOD_0_0FC7_REG_6 */
4072 { "vmptrld",{ Mq }, 0 },
4073 { "vmxon", { Mq }, 0 },
4074 { "vmclear",{ Mq }, 0 },
4077 /* PREFIX_MOD_3_0FC7_REG_6 */
4079 { "rdrand", { Ev }, 0 },
4081 { "rdrand", { Ev }, 0 }
4084 /* PREFIX_MOD_3_0FC7_REG_7 */
4086 { "rdseed", { Ev }, 0 },
4087 { "rdpid", { Em }, 0 },
4088 { "rdseed", { Ev }, 0 },
4095 { "addsubpd", { XM, EXx }, 0 },
4096 { "addsubps", { XM, EXx }, 0 },
4102 { "movq2dq",{ XM, MS }, 0 },
4103 { "movq", { EXqS, XM }, 0 },
4104 { "movdq2q",{ MX, XS }, 0 },
4110 { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4111 { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4112 { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4117 { "movntq", { Mq, MX }, PREFIX_OPCODE },
4119 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4127 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4132 { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4134 { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4141 { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4148 { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4155 { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4162 { "ptest", { XM, EXx }, PREFIX_OPCODE },
4169 { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4176 { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4183 { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4190 { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4197 { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4204 { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4211 { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4218 { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4225 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4232 { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4239 { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4246 { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4253 { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4260 { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4267 { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4274 { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4281 { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4288 { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4295 { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4302 { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4309 { "pminud", { XM, EXx }, PREFIX_OPCODE },
4316 { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4323 { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4330 { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4337 { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4344 { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4351 { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4358 { "invept", { Gm, Mo }, PREFIX_OPCODE },
4365 { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4372 { "invpcid", { Gm, M }, PREFIX_OPCODE },
4377 { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4382 { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4387 { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4392 { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4397 { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4402 { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4409 { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4416 { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4423 { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4430 { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4437 { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4444 { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4449 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4451 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4452 { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4457 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4459 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4460 { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4467 { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4472 { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4473 { "adoxS", { Gdq, Edq}, PREFIX_OPCODE },
4474 { "adcxS", { Gdq, Edq}, PREFIX_OPCODE },
4481 { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
4482 { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4483 { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
4488 { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4495 { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4502 { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4509 { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4516 { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4523 { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4530 { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4537 { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4544 { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4551 { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4558 { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4565 { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4572 { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4579 { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4586 { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4593 { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE },
4600 { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE },
4607 { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4614 { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4621 { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4628 { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4635 { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4642 { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4647 { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4654 { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4661 { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4668 { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4671 /* PREFIX_VEX_0F10 */
4673 { "vmovups", { XM, EXx }, 0 },
4674 { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 },
4675 { "vmovupd", { XM, EXx }, 0 },
4676 { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 },
4679 /* PREFIX_VEX_0F11 */
4681 { "vmovups", { EXxS, XM }, 0 },
4682 { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 },
4683 { "vmovupd", { EXxS, XM }, 0 },
4684 { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 },
4687 /* PREFIX_VEX_0F12 */
4689 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4690 { "vmovsldup", { XM, EXx }, 0 },
4691 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4692 { "vmovddup", { XM, EXymmq }, 0 },
4695 /* PREFIX_VEX_0F16 */
4697 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4698 { "vmovshdup", { XM, EXx }, 0 },
4699 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4702 /* PREFIX_VEX_0F2A */
4705 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Edq }, 0 },
4707 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Edq }, 0 },
4710 /* PREFIX_VEX_0F2C */
4713 { "vcvttss2si", { Gdq, EXdScalar }, 0 },
4715 { "vcvttsd2si", { Gdq, EXqScalar }, 0 },
4718 /* PREFIX_VEX_0F2D */
4721 { "vcvtss2si", { Gdq, EXdScalar }, 0 },
4723 { "vcvtsd2si", { Gdq, EXqScalar }, 0 },
4726 /* PREFIX_VEX_0F2E */
4728 { "vucomiss", { XMScalar, EXdScalar }, 0 },
4730 { "vucomisd", { XMScalar, EXqScalar }, 0 },
4733 /* PREFIX_VEX_0F2F */
4735 { "vcomiss", { XMScalar, EXdScalar }, 0 },
4737 { "vcomisd", { XMScalar, EXqScalar }, 0 },
4740 /* PREFIX_VEX_0F41 */
4742 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4744 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4747 /* PREFIX_VEX_0F42 */
4749 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4751 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4754 /* PREFIX_VEX_0F44 */
4756 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4758 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4761 /* PREFIX_VEX_0F45 */
4763 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4765 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4768 /* PREFIX_VEX_0F46 */
4770 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4772 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4775 /* PREFIX_VEX_0F47 */
4777 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4779 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4782 /* PREFIX_VEX_0F4A */
4784 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
4786 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
4789 /* PREFIX_VEX_0F4B */
4791 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
4793 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
4796 /* PREFIX_VEX_0F51 */
4798 { "vsqrtps", { XM, EXx }, 0 },
4799 { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
4800 { "vsqrtpd", { XM, EXx }, 0 },
4801 { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 },
4804 /* PREFIX_VEX_0F52 */
4806 { "vrsqrtps", { XM, EXx }, 0 },
4807 { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
4810 /* PREFIX_VEX_0F53 */
4812 { "vrcpps", { XM, EXx }, 0 },
4813 { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 },
4816 /* PREFIX_VEX_0F58 */
4818 { "vaddps", { XM, Vex, EXx }, 0 },
4819 { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 },
4820 { "vaddpd", { XM, Vex, EXx }, 0 },
4821 { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 },
4824 /* PREFIX_VEX_0F59 */
4826 { "vmulps", { XM, Vex, EXx }, 0 },
4827 { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 },
4828 { "vmulpd", { XM, Vex, EXx }, 0 },
4829 { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 },
4832 /* PREFIX_VEX_0F5A */
4834 { "vcvtps2pd", { XM, EXxmmq }, 0 },
4835 { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 },
4836 { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
4837 { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 },
4840 /* PREFIX_VEX_0F5B */
4842 { "vcvtdq2ps", { XM, EXx }, 0 },
4843 { "vcvttps2dq", { XM, EXx }, 0 },
4844 { "vcvtps2dq", { XM, EXx }, 0 },
4847 /* PREFIX_VEX_0F5C */
4849 { "vsubps", { XM, Vex, EXx }, 0 },
4850 { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 },
4851 { "vsubpd", { XM, Vex, EXx }, 0 },
4852 { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 },
4855 /* PREFIX_VEX_0F5D */
4857 { "vminps", { XM, Vex, EXx }, 0 },
4858 { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 },
4859 { "vminpd", { XM, Vex, EXx }, 0 },
4860 { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 },
4863 /* PREFIX_VEX_0F5E */
4865 { "vdivps", { XM, Vex, EXx }, 0 },
4866 { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 },
4867 { "vdivpd", { XM, Vex, EXx }, 0 },
4868 { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 },
4871 /* PREFIX_VEX_0F5F */
4873 { "vmaxps", { XM, Vex, EXx }, 0 },
4874 { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 },
4875 { "vmaxpd", { XM, Vex, EXx }, 0 },
4876 { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 },
4879 /* PREFIX_VEX_0F60 */
4883 { "vpunpcklbw", { XM, Vex, EXx }, 0 },
4886 /* PREFIX_VEX_0F61 */
4890 { "vpunpcklwd", { XM, Vex, EXx }, 0 },
4893 /* PREFIX_VEX_0F62 */
4897 { "vpunpckldq", { XM, Vex, EXx }, 0 },
4900 /* PREFIX_VEX_0F63 */
4904 { "vpacksswb", { XM, Vex, EXx }, 0 },
4907 /* PREFIX_VEX_0F64 */
4911 { "vpcmpgtb", { XM, Vex, EXx }, 0 },
4914 /* PREFIX_VEX_0F65 */
4918 { "vpcmpgtw", { XM, Vex, EXx }, 0 },
4921 /* PREFIX_VEX_0F66 */
4925 { "vpcmpgtd", { XM, Vex, EXx }, 0 },
4928 /* PREFIX_VEX_0F67 */
4932 { "vpackuswb", { XM, Vex, EXx }, 0 },
4935 /* PREFIX_VEX_0F68 */
4939 { "vpunpckhbw", { XM, Vex, EXx }, 0 },
4942 /* PREFIX_VEX_0F69 */
4946 { "vpunpckhwd", { XM, Vex, EXx }, 0 },
4949 /* PREFIX_VEX_0F6A */
4953 { "vpunpckhdq", { XM, Vex, EXx }, 0 },
4956 /* PREFIX_VEX_0F6B */
4960 { "vpackssdw", { XM, Vex, EXx }, 0 },
4963 /* PREFIX_VEX_0F6C */
4967 { "vpunpcklqdq", { XM, Vex, EXx }, 0 },
4970 /* PREFIX_VEX_0F6D */
4974 { "vpunpckhqdq", { XM, Vex, EXx }, 0 },
4977 /* PREFIX_VEX_0F6E */
4981 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
4984 /* PREFIX_VEX_0F6F */
4987 { "vmovdqu", { XM, EXx }, 0 },
4988 { "vmovdqa", { XM, EXx }, 0 },
4991 /* PREFIX_VEX_0F70 */
4994 { "vpshufhw", { XM, EXx, Ib }, 0 },
4995 { "vpshufd", { XM, EXx, Ib }, 0 },
4996 { "vpshuflw", { XM, EXx, Ib }, 0 },
4999 /* PREFIX_VEX_0F71_REG_2 */
5003 { "vpsrlw", { Vex, XS, Ib }, 0 },
5006 /* PREFIX_VEX_0F71_REG_4 */
5010 { "vpsraw", { Vex, XS, Ib }, 0 },
5013 /* PREFIX_VEX_0F71_REG_6 */
5017 { "vpsllw", { Vex, XS, Ib }, 0 },
5020 /* PREFIX_VEX_0F72_REG_2 */
5024 { "vpsrld", { Vex, XS, Ib }, 0 },
5027 /* PREFIX_VEX_0F72_REG_4 */
5031 { "vpsrad", { Vex, XS, Ib }, 0 },
5034 /* PREFIX_VEX_0F72_REG_6 */
5038 { "vpslld", { Vex, XS, Ib }, 0 },
5041 /* PREFIX_VEX_0F73_REG_2 */
5045 { "vpsrlq", { Vex, XS, Ib }, 0 },
5048 /* PREFIX_VEX_0F73_REG_3 */
5052 { "vpsrldq", { Vex, XS, Ib }, 0 },
5055 /* PREFIX_VEX_0F73_REG_6 */
5059 { "vpsllq", { Vex, XS, Ib }, 0 },
5062 /* PREFIX_VEX_0F73_REG_7 */
5066 { "vpslldq", { Vex, XS, Ib }, 0 },
5069 /* PREFIX_VEX_0F74 */
5073 { "vpcmpeqb", { XM, Vex, EXx }, 0 },
5076 /* PREFIX_VEX_0F75 */
5080 { "vpcmpeqw", { XM, Vex, EXx }, 0 },
5083 /* PREFIX_VEX_0F76 */
5087 { "vpcmpeqd", { XM, Vex, EXx }, 0 },
5090 /* PREFIX_VEX_0F77 */
5092 { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
5095 /* PREFIX_VEX_0F7C */
5099 { "vhaddpd", { XM, Vex, EXx }, 0 },
5100 { "vhaddps", { XM, Vex, EXx }, 0 },
5103 /* PREFIX_VEX_0F7D */
5107 { "vhsubpd", { XM, Vex, EXx }, 0 },
5108 { "vhsubps", { XM, Vex, EXx }, 0 },
5111 /* PREFIX_VEX_0F7E */
5114 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5115 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5118 /* PREFIX_VEX_0F7F */
5121 { "vmovdqu", { EXxS, XM }, 0 },
5122 { "vmovdqa", { EXxS, XM }, 0 },
5125 /* PREFIX_VEX_0F90 */
5127 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5129 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5132 /* PREFIX_VEX_0F91 */
5134 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5136 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5139 /* PREFIX_VEX_0F92 */
5141 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5143 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5144 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5147 /* PREFIX_VEX_0F93 */
5149 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5151 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5152 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5155 /* PREFIX_VEX_0F98 */
5157 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5159 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5162 /* PREFIX_VEX_0F99 */
5164 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5166 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5169 /* PREFIX_VEX_0FC2 */
5171 { "vcmpps", { XM, Vex, EXx, VCMP }, 0 },
5172 { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
5173 { "vcmppd", { XM, Vex, EXx, VCMP }, 0 },
5174 { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
5177 /* PREFIX_VEX_0FC4 */
5181 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5184 /* PREFIX_VEX_0FC5 */
5188 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5191 /* PREFIX_VEX_0FD0 */
5195 { "vaddsubpd", { XM, Vex, EXx }, 0 },
5196 { "vaddsubps", { XM, Vex, EXx }, 0 },
5199 /* PREFIX_VEX_0FD1 */
5203 { "vpsrlw", { XM, Vex, EXxmm }, 0 },
5206 /* PREFIX_VEX_0FD2 */
5210 { "vpsrld", { XM, Vex, EXxmm }, 0 },
5213 /* PREFIX_VEX_0FD3 */
5217 { "vpsrlq", { XM, Vex, EXxmm }, 0 },
5220 /* PREFIX_VEX_0FD4 */
5224 { "vpaddq", { XM, Vex, EXx }, 0 },
5227 /* PREFIX_VEX_0FD5 */
5231 { "vpmullw", { XM, Vex, EXx }, 0 },
5234 /* PREFIX_VEX_0FD6 */
5238 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5241 /* PREFIX_VEX_0FD7 */
5245 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5248 /* PREFIX_VEX_0FD8 */
5252 { "vpsubusb", { XM, Vex, EXx }, 0 },
5255 /* PREFIX_VEX_0FD9 */
5259 { "vpsubusw", { XM, Vex, EXx }, 0 },
5262 /* PREFIX_VEX_0FDA */
5266 { "vpminub", { XM, Vex, EXx }, 0 },
5269 /* PREFIX_VEX_0FDB */
5273 { "vpand", { XM, Vex, EXx }, 0 },
5276 /* PREFIX_VEX_0FDC */
5280 { "vpaddusb", { XM, Vex, EXx }, 0 },
5283 /* PREFIX_VEX_0FDD */
5287 { "vpaddusw", { XM, Vex, EXx }, 0 },
5290 /* PREFIX_VEX_0FDE */
5294 { "vpmaxub", { XM, Vex, EXx }, 0 },
5297 /* PREFIX_VEX_0FDF */
5301 { "vpandn", { XM, Vex, EXx }, 0 },
5304 /* PREFIX_VEX_0FE0 */
5308 { "vpavgb", { XM, Vex, EXx }, 0 },
5311 /* PREFIX_VEX_0FE1 */
5315 { "vpsraw", { XM, Vex, EXxmm }, 0 },
5318 /* PREFIX_VEX_0FE2 */
5322 { "vpsrad", { XM, Vex, EXxmm }, 0 },
5325 /* PREFIX_VEX_0FE3 */
5329 { "vpavgw", { XM, Vex, EXx }, 0 },
5332 /* PREFIX_VEX_0FE4 */
5336 { "vpmulhuw", { XM, Vex, EXx }, 0 },
5339 /* PREFIX_VEX_0FE5 */
5343 { "vpmulhw", { XM, Vex, EXx }, 0 },
5346 /* PREFIX_VEX_0FE6 */
5349 { "vcvtdq2pd", { XM, EXxmmq }, 0 },
5350 { "vcvttpd2dq%XY", { XMM, EXx }, 0 },
5351 { "vcvtpd2dq%XY", { XMM, EXx }, 0 },
5354 /* PREFIX_VEX_0FE7 */
5358 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5361 /* PREFIX_VEX_0FE8 */
5365 { "vpsubsb", { XM, Vex, EXx }, 0 },
5368 /* PREFIX_VEX_0FE9 */
5372 { "vpsubsw", { XM, Vex, EXx }, 0 },
5375 /* PREFIX_VEX_0FEA */
5379 { "vpminsw", { XM, Vex, EXx }, 0 },
5382 /* PREFIX_VEX_0FEB */
5386 { "vpor", { XM, Vex, EXx }, 0 },
5389 /* PREFIX_VEX_0FEC */
5393 { "vpaddsb", { XM, Vex, EXx }, 0 },
5396 /* PREFIX_VEX_0FED */
5400 { "vpaddsw", { XM, Vex, EXx }, 0 },
5403 /* PREFIX_VEX_0FEE */
5407 { "vpmaxsw", { XM, Vex, EXx }, 0 },
5410 /* PREFIX_VEX_0FEF */
5414 { "vpxor", { XM, Vex, EXx }, 0 },
5417 /* PREFIX_VEX_0FF0 */
5422 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5425 /* PREFIX_VEX_0FF1 */
5429 { "vpsllw", { XM, Vex, EXxmm }, 0 },
5432 /* PREFIX_VEX_0FF2 */
5436 { "vpslld", { XM, Vex, EXxmm }, 0 },
5439 /* PREFIX_VEX_0FF3 */
5443 { "vpsllq", { XM, Vex, EXxmm }, 0 },
5446 /* PREFIX_VEX_0FF4 */
5450 { "vpmuludq", { XM, Vex, EXx }, 0 },
5453 /* PREFIX_VEX_0FF5 */
5457 { "vpmaddwd", { XM, Vex, EXx }, 0 },
5460 /* PREFIX_VEX_0FF6 */
5464 { "vpsadbw", { XM, Vex, EXx }, 0 },
5467 /* PREFIX_VEX_0FF7 */
5471 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5474 /* PREFIX_VEX_0FF8 */
5478 { "vpsubb", { XM, Vex, EXx }, 0 },
5481 /* PREFIX_VEX_0FF9 */
5485 { "vpsubw", { XM, Vex, EXx }, 0 },
5488 /* PREFIX_VEX_0FFA */
5492 { "vpsubd", { XM, Vex, EXx }, 0 },
5495 /* PREFIX_VEX_0FFB */
5499 { "vpsubq", { XM, Vex, EXx }, 0 },
5502 /* PREFIX_VEX_0FFC */
5506 { "vpaddb", { XM, Vex, EXx }, 0 },
5509 /* PREFIX_VEX_0FFD */
5513 { "vpaddw", { XM, Vex, EXx }, 0 },
5516 /* PREFIX_VEX_0FFE */
5520 { "vpaddd", { XM, Vex, EXx }, 0 },
5523 /* PREFIX_VEX_0F3800 */
5527 { "vpshufb", { XM, Vex, EXx }, 0 },
5530 /* PREFIX_VEX_0F3801 */
5534 { "vphaddw", { XM, Vex, EXx }, 0 },
5537 /* PREFIX_VEX_0F3802 */
5541 { "vphaddd", { XM, Vex, EXx }, 0 },
5544 /* PREFIX_VEX_0F3803 */
5548 { "vphaddsw", { XM, Vex, EXx }, 0 },
5551 /* PREFIX_VEX_0F3804 */
5555 { "vpmaddubsw", { XM, Vex, EXx }, 0 },
5558 /* PREFIX_VEX_0F3805 */
5562 { "vphsubw", { XM, Vex, EXx }, 0 },
5565 /* PREFIX_VEX_0F3806 */
5569 { "vphsubd", { XM, Vex, EXx }, 0 },
5572 /* PREFIX_VEX_0F3807 */
5576 { "vphsubsw", { XM, Vex, EXx }, 0 },
5579 /* PREFIX_VEX_0F3808 */
5583 { "vpsignb", { XM, Vex, EXx }, 0 },
5586 /* PREFIX_VEX_0F3809 */
5590 { "vpsignw", { XM, Vex, EXx }, 0 },
5593 /* PREFIX_VEX_0F380A */
5597 { "vpsignd", { XM, Vex, EXx }, 0 },
5600 /* PREFIX_VEX_0F380B */
5604 { "vpmulhrsw", { XM, Vex, EXx }, 0 },
5607 /* PREFIX_VEX_0F380C */
5611 { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5614 /* PREFIX_VEX_0F380D */
5618 { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5621 /* PREFIX_VEX_0F380E */
5625 { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5628 /* PREFIX_VEX_0F380F */
5632 { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5635 /* PREFIX_VEX_0F3813 */
5639 { "vcvtph2ps", { XM, EXxmmq }, 0 },
5642 /* PREFIX_VEX_0F3816 */
5646 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5649 /* PREFIX_VEX_0F3817 */
5653 { "vptest", { XM, EXx }, 0 },
5656 /* PREFIX_VEX_0F3818 */
5660 { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5663 /* PREFIX_VEX_0F3819 */
5667 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5670 /* PREFIX_VEX_0F381A */
5674 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5677 /* PREFIX_VEX_0F381C */
5681 { "vpabsb", { XM, EXx }, 0 },
5684 /* PREFIX_VEX_0F381D */
5688 { "vpabsw", { XM, EXx }, 0 },
5691 /* PREFIX_VEX_0F381E */
5695 { "vpabsd", { XM, EXx }, 0 },
5698 /* PREFIX_VEX_0F3820 */
5702 { "vpmovsxbw", { XM, EXxmmq }, 0 },
5705 /* PREFIX_VEX_0F3821 */
5709 { "vpmovsxbd", { XM, EXxmmqd }, 0 },
5712 /* PREFIX_VEX_0F3822 */
5716 { "vpmovsxbq", { XM, EXxmmdw }, 0 },
5719 /* PREFIX_VEX_0F3823 */
5723 { "vpmovsxwd", { XM, EXxmmq }, 0 },
5726 /* PREFIX_VEX_0F3824 */
5730 { "vpmovsxwq", { XM, EXxmmqd }, 0 },
5733 /* PREFIX_VEX_0F3825 */
5737 { "vpmovsxdq", { XM, EXxmmq }, 0 },
5740 /* PREFIX_VEX_0F3828 */
5744 { "vpmuldq", { XM, Vex, EXx }, 0 },
5747 /* PREFIX_VEX_0F3829 */
5751 { "vpcmpeqq", { XM, Vex, EXx }, 0 },
5754 /* PREFIX_VEX_0F382A */
5758 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5761 /* PREFIX_VEX_0F382B */
5765 { "vpackusdw", { XM, Vex, EXx }, 0 },
5768 /* PREFIX_VEX_0F382C */
5772 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5775 /* PREFIX_VEX_0F382D */
5779 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5782 /* PREFIX_VEX_0F382E */
5786 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
5789 /* PREFIX_VEX_0F382F */
5793 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
5796 /* PREFIX_VEX_0F3830 */
5800 { "vpmovzxbw", { XM, EXxmmq }, 0 },
5803 /* PREFIX_VEX_0F3831 */
5807 { "vpmovzxbd", { XM, EXxmmqd }, 0 },
5810 /* PREFIX_VEX_0F3832 */
5814 { "vpmovzxbq", { XM, EXxmmdw }, 0 },
5817 /* PREFIX_VEX_0F3833 */
5821 { "vpmovzxwd", { XM, EXxmmq }, 0 },
5824 /* PREFIX_VEX_0F3834 */
5828 { "vpmovzxwq", { XM, EXxmmqd }, 0 },
5831 /* PREFIX_VEX_0F3835 */
5835 { "vpmovzxdq", { XM, EXxmmq }, 0 },
5838 /* PREFIX_VEX_0F3836 */
5842 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
5845 /* PREFIX_VEX_0F3837 */
5849 { "vpcmpgtq", { XM, Vex, EXx }, 0 },
5852 /* PREFIX_VEX_0F3838 */
5856 { "vpminsb", { XM, Vex, EXx }, 0 },
5859 /* PREFIX_VEX_0F3839 */
5863 { "vpminsd", { XM, Vex, EXx }, 0 },
5866 /* PREFIX_VEX_0F383A */
5870 { "vpminuw", { XM, Vex, EXx }, 0 },
5873 /* PREFIX_VEX_0F383B */
5877 { "vpminud", { XM, Vex, EXx }, 0 },
5880 /* PREFIX_VEX_0F383C */
5884 { "vpmaxsb", { XM, Vex, EXx }, 0 },
5887 /* PREFIX_VEX_0F383D */
5891 { "vpmaxsd", { XM, Vex, EXx }, 0 },
5894 /* PREFIX_VEX_0F383E */
5898 { "vpmaxuw", { XM, Vex, EXx }, 0 },
5901 /* PREFIX_VEX_0F383F */
5905 { "vpmaxud", { XM, Vex, EXx }, 0 },
5908 /* PREFIX_VEX_0F3840 */
5912 { "vpmulld", { XM, Vex, EXx }, 0 },
5915 /* PREFIX_VEX_0F3841 */
5919 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
5922 /* PREFIX_VEX_0F3845 */
5926 { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
5929 /* PREFIX_VEX_0F3846 */
5933 { VEX_W_TABLE (VEX_W_0F3846_P_2) },
5936 /* PREFIX_VEX_0F3847 */
5940 { "vpsllv%LW", { XM, Vex, EXx }, 0 },
5943 /* PREFIX_VEX_0F3858 */
5947 { VEX_W_TABLE (VEX_W_0F3858_P_2) },
5950 /* PREFIX_VEX_0F3859 */
5954 { VEX_W_TABLE (VEX_W_0F3859_P_2) },
5957 /* PREFIX_VEX_0F385A */
5961 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
5964 /* PREFIX_VEX_0F3878 */
5968 { VEX_W_TABLE (VEX_W_0F3878_P_2) },
5971 /* PREFIX_VEX_0F3879 */
5975 { VEX_W_TABLE (VEX_W_0F3879_P_2) },
5978 /* PREFIX_VEX_0F388C */
5982 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
5985 /* PREFIX_VEX_0F388E */
5989 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
5992 /* PREFIX_VEX_0F3890 */
5996 { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
5999 /* PREFIX_VEX_0F3891 */
6003 { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6006 /* PREFIX_VEX_0F3892 */
6010 { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6013 /* PREFIX_VEX_0F3893 */
6017 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6020 /* PREFIX_VEX_0F3896 */
6024 { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6027 /* PREFIX_VEX_0F3897 */
6031 { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6034 /* PREFIX_VEX_0F3898 */
6038 { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6041 /* PREFIX_VEX_0F3899 */
6045 { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6048 /* PREFIX_VEX_0F389A */
6052 { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6055 /* PREFIX_VEX_0F389B */
6059 { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6062 /* PREFIX_VEX_0F389C */
6066 { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6069 /* PREFIX_VEX_0F389D */
6073 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6076 /* PREFIX_VEX_0F389E */
6080 { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6083 /* PREFIX_VEX_0F389F */
6087 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6090 /* PREFIX_VEX_0F38A6 */
6094 { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6098 /* PREFIX_VEX_0F38A7 */
6102 { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6105 /* PREFIX_VEX_0F38A8 */
6109 { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6112 /* PREFIX_VEX_0F38A9 */
6116 { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6119 /* PREFIX_VEX_0F38AA */
6123 { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6126 /* PREFIX_VEX_0F38AB */
6130 { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6133 /* PREFIX_VEX_0F38AC */
6137 { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6140 /* PREFIX_VEX_0F38AD */
6144 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6147 /* PREFIX_VEX_0F38AE */
6151 { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6154 /* PREFIX_VEX_0F38AF */
6158 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6161 /* PREFIX_VEX_0F38B6 */
6165 { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6168 /* PREFIX_VEX_0F38B7 */
6172 { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6175 /* PREFIX_VEX_0F38B8 */
6179 { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6182 /* PREFIX_VEX_0F38B9 */
6186 { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6189 /* PREFIX_VEX_0F38BA */
6193 { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6196 /* PREFIX_VEX_0F38BB */
6200 { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6203 /* PREFIX_VEX_0F38BC */
6207 { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6210 /* PREFIX_VEX_0F38BD */
6214 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6217 /* PREFIX_VEX_0F38BE */
6221 { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6224 /* PREFIX_VEX_0F38BF */
6228 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6231 /* PREFIX_VEX_0F38CF */
6235 { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6238 /* PREFIX_VEX_0F38DB */
6242 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6245 /* PREFIX_VEX_0F38DC */
6249 { "vaesenc", { XM, Vex, EXx }, 0 },
6252 /* PREFIX_VEX_0F38DD */
6256 { "vaesenclast", { XM, Vex, EXx }, 0 },
6259 /* PREFIX_VEX_0F38DE */
6263 { "vaesdec", { XM, Vex, EXx }, 0 },
6266 /* PREFIX_VEX_0F38DF */
6270 { "vaesdeclast", { XM, Vex, EXx }, 0 },
6273 /* PREFIX_VEX_0F38F2 */
6275 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6278 /* PREFIX_VEX_0F38F3_REG_1 */
6280 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6283 /* PREFIX_VEX_0F38F3_REG_2 */
6285 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6288 /* PREFIX_VEX_0F38F3_REG_3 */
6290 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6293 /* PREFIX_VEX_0F38F5 */
6295 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6296 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6298 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6301 /* PREFIX_VEX_0F38F6 */
6306 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6309 /* PREFIX_VEX_0F38F7 */
6311 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6312 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6313 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6314 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6317 /* PREFIX_VEX_0F3A00 */
6321 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6324 /* PREFIX_VEX_0F3A01 */
6328 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6331 /* PREFIX_VEX_0F3A02 */
6335 { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6338 /* PREFIX_VEX_0F3A04 */
6342 { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6345 /* PREFIX_VEX_0F3A05 */
6349 { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6352 /* PREFIX_VEX_0F3A06 */
6356 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6359 /* PREFIX_VEX_0F3A08 */
6363 { "vroundps", { XM, EXx, Ib }, 0 },
6366 /* PREFIX_VEX_0F3A09 */
6370 { "vroundpd", { XM, EXx, Ib }, 0 },
6373 /* PREFIX_VEX_0F3A0A */
6377 { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
6380 /* PREFIX_VEX_0F3A0B */
6384 { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
6387 /* PREFIX_VEX_0F3A0C */
6391 { "vblendps", { XM, Vex, EXx, Ib }, 0 },
6394 /* PREFIX_VEX_0F3A0D */
6398 { "vblendpd", { XM, Vex, EXx, Ib }, 0 },
6401 /* PREFIX_VEX_0F3A0E */
6405 { "vpblendw", { XM, Vex, EXx, Ib }, 0 },
6408 /* PREFIX_VEX_0F3A0F */
6412 { "vpalignr", { XM, Vex, EXx, Ib }, 0 },
6415 /* PREFIX_VEX_0F3A14 */
6419 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6422 /* PREFIX_VEX_0F3A15 */
6426 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6429 /* PREFIX_VEX_0F3A16 */
6433 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6436 /* PREFIX_VEX_0F3A17 */
6440 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6443 /* PREFIX_VEX_0F3A18 */
6447 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6450 /* PREFIX_VEX_0F3A19 */
6454 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6457 /* PREFIX_VEX_0F3A1D */
6461 { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6464 /* PREFIX_VEX_0F3A20 */
6468 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6471 /* PREFIX_VEX_0F3A21 */
6475 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6478 /* PREFIX_VEX_0F3A22 */
6482 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6485 /* PREFIX_VEX_0F3A30 */
6489 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6492 /* PREFIX_VEX_0F3A31 */
6496 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6499 /* PREFIX_VEX_0F3A32 */
6503 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6506 /* PREFIX_VEX_0F3A33 */
6510 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6513 /* PREFIX_VEX_0F3A38 */
6517 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6520 /* PREFIX_VEX_0F3A39 */
6524 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6527 /* PREFIX_VEX_0F3A40 */
6531 { "vdpps", { XM, Vex, EXx, Ib }, 0 },
6534 /* PREFIX_VEX_0F3A41 */
6538 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6541 /* PREFIX_VEX_0F3A42 */
6545 { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 },
6548 /* PREFIX_VEX_0F3A44 */
6552 { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, 0 },
6555 /* PREFIX_VEX_0F3A46 */
6559 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6562 /* PREFIX_VEX_0F3A48 */
6566 { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6569 /* PREFIX_VEX_0F3A49 */
6573 { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6576 /* PREFIX_VEX_0F3A4A */
6580 { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6583 /* PREFIX_VEX_0F3A4B */
6587 { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6590 /* PREFIX_VEX_0F3A4C */
6594 { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6597 /* PREFIX_VEX_0F3A5C */
6601 { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6604 /* PREFIX_VEX_0F3A5D */
6608 { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6611 /* PREFIX_VEX_0F3A5E */
6615 { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6618 /* PREFIX_VEX_0F3A5F */
6622 { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6625 /* PREFIX_VEX_0F3A60 */
6629 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6633 /* PREFIX_VEX_0F3A61 */
6637 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6640 /* PREFIX_VEX_0F3A62 */
6644 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6647 /* PREFIX_VEX_0F3A63 */
6651 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6654 /* PREFIX_VEX_0F3A68 */
6658 { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6661 /* PREFIX_VEX_0F3A69 */
6665 { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6668 /* PREFIX_VEX_0F3A6A */
6672 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6675 /* PREFIX_VEX_0F3A6B */
6679 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6682 /* PREFIX_VEX_0F3A6C */
6686 { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6689 /* PREFIX_VEX_0F3A6D */
6693 { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6696 /* PREFIX_VEX_0F3A6E */
6700 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6703 /* PREFIX_VEX_0F3A6F */
6707 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6710 /* PREFIX_VEX_0F3A78 */
6714 { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6717 /* PREFIX_VEX_0F3A79 */
6721 { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6724 /* PREFIX_VEX_0F3A7A */
6728 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6731 /* PREFIX_VEX_0F3A7B */
6735 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6738 /* PREFIX_VEX_0F3A7C */
6742 { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6746 /* PREFIX_VEX_0F3A7D */
6750 { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6753 /* PREFIX_VEX_0F3A7E */
6757 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6760 /* PREFIX_VEX_0F3A7F */
6764 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6767 /* PREFIX_VEX_0F3ACE */
6771 { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6774 /* PREFIX_VEX_0F3ACF */
6778 { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6781 /* PREFIX_VEX_0F3ADF */
6785 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
6788 /* PREFIX_VEX_0F3AF0 */
6793 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
6796 #include "i386-dis-evex-prefix.h"
6799 static const struct dis386 x86_64_table[][2] = {
6802 { "pushP", { es }, 0 },
6807 { "popP", { es }, 0 },
6812 { "pushP", { cs }, 0 },
6817 { "pushP", { ss }, 0 },
6822 { "popP", { ss }, 0 },
6827 { "pushP", { ds }, 0 },
6832 { "popP", { ds }, 0 },
6837 { "daa", { XX }, 0 },
6842 { "das", { XX }, 0 },
6847 { "aaa", { XX }, 0 },
6852 { "aas", { XX }, 0 },
6857 { "pushaP", { XX }, 0 },
6862 { "popaP", { XX }, 0 },
6867 { MOD_TABLE (MOD_62_32BIT) },
6868 { EVEX_TABLE (EVEX_0F) },
6873 { "arpl", { Ew, Gw }, 0 },
6874 { "movs{lq|xd}", { Gv, Ed }, 0 },
6879 { "ins{R|}", { Yzr, indirDX }, 0 },
6880 { "ins{G|}", { Yzr, indirDX }, 0 },
6885 { "outs{R|}", { indirDXr, Xz }, 0 },
6886 { "outs{G|}", { indirDXr, Xz }, 0 },
6891 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
6892 { REG_TABLE (REG_80) },
6897 { "Jcall{T|}", { Ap }, 0 },
6902 { MOD_TABLE (MOD_C4_32BIT) },
6903 { VEX_C4_TABLE (VEX_0F) },
6908 { MOD_TABLE (MOD_C5_32BIT) },
6909 { VEX_C5_TABLE (VEX_0F) },
6914 { "into", { XX }, 0 },
6919 { "aam", { Ib }, 0 },
6924 { "aad", { Ib }, 0 },
6929 { "callP", { Jv, BND }, 0 },
6930 { "call@", { Jv, BND }, 0 }
6935 { "jmpP", { Jv, BND }, 0 },
6936 { "jmp@", { Jv, BND }, 0 }
6941 { "Jjmp{T|}", { Ap }, 0 },
6944 /* X86_64_0F01_REG_0 */
6946 { "sgdt{Q|IQ}", { M }, 0 },
6947 { "sgdt", { M }, 0 },
6950 /* X86_64_0F01_REG_1 */
6952 { "sidt{Q|IQ}", { M }, 0 },
6953 { "sidt", { M }, 0 },
6956 /* X86_64_0F01_REG_2 */
6958 { "lgdt{Q|Q}", { M }, 0 },
6959 { "lgdt", { M }, 0 },
6962 /* X86_64_0F01_REG_3 */
6964 { "lidt{Q|Q}", { M }, 0 },
6965 { "lidt", { M }, 0 },
6969 static const struct dis386 three_byte_table[][256] = {
6971 /* THREE_BYTE_0F38 */
6974 { "pshufb", { MX, EM }, PREFIX_OPCODE },
6975 { "phaddw", { MX, EM }, PREFIX_OPCODE },
6976 { "phaddd", { MX, EM }, PREFIX_OPCODE },
6977 { "phaddsw", { MX, EM }, PREFIX_OPCODE },
6978 { "pmaddubsw", { MX, EM }, PREFIX_OPCODE },
6979 { "phsubw", { MX, EM }, PREFIX_OPCODE },
6980 { "phsubd", { MX, EM }, PREFIX_OPCODE },
6981 { "phsubsw", { MX, EM }, PREFIX_OPCODE },
6983 { "psignb", { MX, EM }, PREFIX_OPCODE },
6984 { "psignw", { MX, EM }, PREFIX_OPCODE },
6985 { "psignd", { MX, EM }, PREFIX_OPCODE },
6986 { "pmulhrsw", { MX, EM }, PREFIX_OPCODE },
6992 { PREFIX_TABLE (PREFIX_0F3810) },
6996 { PREFIX_TABLE (PREFIX_0F3814) },
6997 { PREFIX_TABLE (PREFIX_0F3815) },
6999 { PREFIX_TABLE (PREFIX_0F3817) },
7005 { "pabsb", { MX, EM }, PREFIX_OPCODE },
7006 { "pabsw", { MX, EM }, PREFIX_OPCODE },
7007 { "pabsd", { MX, EM }, PREFIX_OPCODE },
7010 { PREFIX_TABLE (PREFIX_0F3820) },
7011 { PREFIX_TABLE (PREFIX_0F3821) },
7012 { PREFIX_TABLE (PREFIX_0F3822) },
7013 { PREFIX_TABLE (PREFIX_0F3823) },
7014 { PREFIX_TABLE (PREFIX_0F3824) },
7015 { PREFIX_TABLE (PREFIX_0F3825) },
7019 { PREFIX_TABLE (PREFIX_0F3828) },
7020 { PREFIX_TABLE (PREFIX_0F3829) },
7021 { PREFIX_TABLE (PREFIX_0F382A) },
7022 { PREFIX_TABLE (PREFIX_0F382B) },
7028 { PREFIX_TABLE (PREFIX_0F3830) },
7029 { PREFIX_TABLE (PREFIX_0F3831) },
7030 { PREFIX_TABLE (PREFIX_0F3832) },
7031 { PREFIX_TABLE (PREFIX_0F3833) },
7032 { PREFIX_TABLE (PREFIX_0F3834) },
7033 { PREFIX_TABLE (PREFIX_0F3835) },
7035 { PREFIX_TABLE (PREFIX_0F3837) },
7037 { PREFIX_TABLE (PREFIX_0F3838) },
7038 { PREFIX_TABLE (PREFIX_0F3839) },
7039 { PREFIX_TABLE (PREFIX_0F383A) },
7040 { PREFIX_TABLE (PREFIX_0F383B) },
7041 { PREFIX_TABLE (PREFIX_0F383C) },
7042 { PREFIX_TABLE (PREFIX_0F383D) },
7043 { PREFIX_TABLE (PREFIX_0F383E) },
7044 { PREFIX_TABLE (PREFIX_0F383F) },
7046 { PREFIX_TABLE (PREFIX_0F3840) },
7047 { PREFIX_TABLE (PREFIX_0F3841) },
7118 { PREFIX_TABLE (PREFIX_0F3880) },
7119 { PREFIX_TABLE (PREFIX_0F3881) },
7120 { PREFIX_TABLE (PREFIX_0F3882) },
7199 { PREFIX_TABLE (PREFIX_0F38C8) },
7200 { PREFIX_TABLE (PREFIX_0F38C9) },
7201 { PREFIX_TABLE (PREFIX_0F38CA) },
7202 { PREFIX_TABLE (PREFIX_0F38CB) },
7203 { PREFIX_TABLE (PREFIX_0F38CC) },
7204 { PREFIX_TABLE (PREFIX_0F38CD) },
7206 { PREFIX_TABLE (PREFIX_0F38CF) },
7220 { PREFIX_TABLE (PREFIX_0F38DB) },
7221 { PREFIX_TABLE (PREFIX_0F38DC) },
7222 { PREFIX_TABLE (PREFIX_0F38DD) },
7223 { PREFIX_TABLE (PREFIX_0F38DE) },
7224 { PREFIX_TABLE (PREFIX_0F38DF) },
7244 { PREFIX_TABLE (PREFIX_0F38F0) },
7245 { PREFIX_TABLE (PREFIX_0F38F1) },
7249 { PREFIX_TABLE (PREFIX_0F38F5) },
7250 { PREFIX_TABLE (PREFIX_0F38F6) },
7253 { PREFIX_TABLE (PREFIX_0F38F8) },
7254 { PREFIX_TABLE (PREFIX_0F38F9) },
7262 /* THREE_BYTE_0F3A */
7274 { PREFIX_TABLE (PREFIX_0F3A08) },
7275 { PREFIX_TABLE (PREFIX_0F3A09) },
7276 { PREFIX_TABLE (PREFIX_0F3A0A) },
7277 { PREFIX_TABLE (PREFIX_0F3A0B) },
7278 { PREFIX_TABLE (PREFIX_0F3A0C) },
7279 { PREFIX_TABLE (PREFIX_0F3A0D) },
7280 { PREFIX_TABLE (PREFIX_0F3A0E) },
7281 { "palignr", { MX, EM, Ib }, PREFIX_OPCODE },
7287 { PREFIX_TABLE (PREFIX_0F3A14) },
7288 { PREFIX_TABLE (PREFIX_0F3A15) },
7289 { PREFIX_TABLE (PREFIX_0F3A16) },
7290 { PREFIX_TABLE (PREFIX_0F3A17) },
7301 { PREFIX_TABLE (PREFIX_0F3A20) },
7302 { PREFIX_TABLE (PREFIX_0F3A21) },
7303 { PREFIX_TABLE (PREFIX_0F3A22) },
7337 { PREFIX_TABLE (PREFIX_0F3A40) },
7338 { PREFIX_TABLE (PREFIX_0F3A41) },
7339 { PREFIX_TABLE (PREFIX_0F3A42) },
7341 { PREFIX_TABLE (PREFIX_0F3A44) },
7373 { PREFIX_TABLE (PREFIX_0F3A60) },
7374 { PREFIX_TABLE (PREFIX_0F3A61) },
7375 { PREFIX_TABLE (PREFIX_0F3A62) },
7376 { PREFIX_TABLE (PREFIX_0F3A63) },
7494 { PREFIX_TABLE (PREFIX_0F3ACC) },
7496 { PREFIX_TABLE (PREFIX_0F3ACE) },
7497 { PREFIX_TABLE (PREFIX_0F3ACF) },
7515 { PREFIX_TABLE (PREFIX_0F3ADF) },
7555 static const struct dis386 xop_table[][256] = {
7708 { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7709 { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7710 { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7718 { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7719 { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7726 { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7727 { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7728 { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7736 { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7737 { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7741 { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7742 { "vpperm", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7745 { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7763 { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7775 { "vprotb", { XM, Vex_2src_1, Ib }, 0 },
7776 { "vprotw", { XM, Vex_2src_1, Ib }, 0 },
7777 { "vprotd", { XM, Vex_2src_1, Ib }, 0 },
7778 { "vprotq", { XM, Vex_2src_1, Ib }, 0 },
7788 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
7789 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
7790 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
7791 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
7824 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
7825 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
7826 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
7827 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
7851 { REG_TABLE (REG_XOP_TBM_01) },
7852 { REG_TABLE (REG_XOP_TBM_02) },
7870 { REG_TABLE (REG_XOP_LWPCB) },
7994 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7995 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7996 { "vfrczss", { XM, EXd }, 0 },
7997 { "vfrczsd", { XM, EXq }, 0 },
8012 { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8013 { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8014 { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8015 { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8016 { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8017 { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8018 { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8019 { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8021 { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8022 { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8023 { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8024 { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8067 { "vphaddbw", { XM, EXxmm }, 0 },
8068 { "vphaddbd", { XM, EXxmm }, 0 },
8069 { "vphaddbq", { XM, EXxmm }, 0 },
8072 { "vphaddwd", { XM, EXxmm }, 0 },
8073 { "vphaddwq", { XM, EXxmm }, 0 },
8078 { "vphadddq", { XM, EXxmm }, 0 },
8085 { "vphaddubw", { XM, EXxmm }, 0 },
8086 { "vphaddubd", { XM, EXxmm }, 0 },
8087 { "vphaddubq", { XM, EXxmm }, 0 },
8090 { "vphadduwd", { XM, EXxmm }, 0 },
8091 { "vphadduwq", { XM, EXxmm }, 0 },
8096 { "vphaddudq", { XM, EXxmm }, 0 },
8103 { "vphsubbw", { XM, EXxmm }, 0 },
8104 { "vphsubwd", { XM, EXxmm }, 0 },
8105 { "vphsubdq", { XM, EXxmm }, 0 },
8159 { "bextrS", { Gdq, Edq, Id }, 0 },
8161 { REG_TABLE (REG_XOP_LWP) },
8431 static const struct dis386 vex_table[][256] = {
8453 { PREFIX_TABLE (PREFIX_VEX_0F10) },
8454 { PREFIX_TABLE (PREFIX_VEX_0F11) },
8455 { PREFIX_TABLE (PREFIX_VEX_0F12) },
8456 { MOD_TABLE (MOD_VEX_0F13) },
8457 { "vunpcklpX", { XM, Vex, EXx }, 0 },
8458 { "vunpckhpX", { XM, Vex, EXx }, 0 },
8459 { PREFIX_TABLE (PREFIX_VEX_0F16) },
8460 { MOD_TABLE (MOD_VEX_0F17) },
8480 { "vmovapX", { XM, EXx }, 0 },
8481 { "vmovapX", { EXxS, XM }, 0 },
8482 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8483 { MOD_TABLE (MOD_VEX_0F2B) },
8484 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8485 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8486 { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8487 { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8508 { PREFIX_TABLE (PREFIX_VEX_0F41) },
8509 { PREFIX_TABLE (PREFIX_VEX_0F42) },
8511 { PREFIX_TABLE (PREFIX_VEX_0F44) },
8512 { PREFIX_TABLE (PREFIX_VEX_0F45) },
8513 { PREFIX_TABLE (PREFIX_VEX_0F46) },
8514 { PREFIX_TABLE (PREFIX_VEX_0F47) },
8518 { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8519 { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8525 { MOD_TABLE (MOD_VEX_0F50) },
8526 { PREFIX_TABLE (PREFIX_VEX_0F51) },
8527 { PREFIX_TABLE (PREFIX_VEX_0F52) },
8528 { PREFIX_TABLE (PREFIX_VEX_0F53) },
8529 { "vandpX", { XM, Vex, EXx }, 0 },
8530 { "vandnpX", { XM, Vex, EXx }, 0 },
8531 { "vorpX", { XM, Vex, EXx }, 0 },
8532 { "vxorpX", { XM, Vex, EXx }, 0 },
8534 { PREFIX_TABLE (PREFIX_VEX_0F58) },
8535 { PREFIX_TABLE (PREFIX_VEX_0F59) },
8536 { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8537 { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8538 { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8539 { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8540 { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8541 { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8543 { PREFIX_TABLE (PREFIX_VEX_0F60) },
8544 { PREFIX_TABLE (PREFIX_VEX_0F61) },
8545 { PREFIX_TABLE (PREFIX_VEX_0F62) },
8546 { PREFIX_TABLE (PREFIX_VEX_0F63) },
8547 { PREFIX_TABLE (PREFIX_VEX_0F64) },
8548 { PREFIX_TABLE (PREFIX_VEX_0F65) },
8549 { PREFIX_TABLE (PREFIX_VEX_0F66) },
8550 { PREFIX_TABLE (PREFIX_VEX_0F67) },
8552 { PREFIX_TABLE (PREFIX_VEX_0F68) },
8553 { PREFIX_TABLE (PREFIX_VEX_0F69) },
8554 { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8555 { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8556 { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8557 { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8558 { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8559 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8561 { PREFIX_TABLE (PREFIX_VEX_0F70) },
8562 { REG_TABLE (REG_VEX_0F71) },
8563 { REG_TABLE (REG_VEX_0F72) },
8564 { REG_TABLE (REG_VEX_0F73) },
8565 { PREFIX_TABLE (PREFIX_VEX_0F74) },
8566 { PREFIX_TABLE (PREFIX_VEX_0F75) },
8567 { PREFIX_TABLE (PREFIX_VEX_0F76) },
8568 { PREFIX_TABLE (PREFIX_VEX_0F77) },
8574 { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8575 { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8576 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8577 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8597 { PREFIX_TABLE (PREFIX_VEX_0F90) },
8598 { PREFIX_TABLE (PREFIX_VEX_0F91) },
8599 { PREFIX_TABLE (PREFIX_VEX_0F92) },
8600 { PREFIX_TABLE (PREFIX_VEX_0F93) },
8606 { PREFIX_TABLE (PREFIX_VEX_0F98) },
8607 { PREFIX_TABLE (PREFIX_VEX_0F99) },
8630 { REG_TABLE (REG_VEX_0FAE) },
8653 { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8655 { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8656 { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8657 { "vshufpX", { XM, Vex, EXx, Ib }, 0 },
8669 { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8670 { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8671 { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8672 { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8673 { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8674 { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8675 { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8676 { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8678 { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8679 { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8680 { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8681 { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8682 { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8683 { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8684 { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8685 { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8687 { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8688 { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8689 { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8690 { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8691 { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8692 { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8693 { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8694 { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8696 { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8697 { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8698 { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8699 { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8700 { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8701 { PREFIX_TABLE (PREFIX_VEX_0FED) },
8702 { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8703 { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8705 { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8706 { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8707 { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8708 { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8709 { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8710 { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8711 { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8712 { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8714 { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8715 { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8716 { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8717 { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8718 { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8719 { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8720 { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8726 { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8727 { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8728 { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8729 { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8730 { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8731 { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8732 { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8733 { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8735 { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8736 { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8737 { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8738 { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8739 { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8740 { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8741 { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8742 { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8747 { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8750 { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8751 { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8753 { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8754 { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8755 { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8757 { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8758 { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8759 { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8762 { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8763 { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8764 { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8765 { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8766 { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8767 { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8771 { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8772 { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8773 { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8774 { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8775 { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8776 { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8777 { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8778 { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8780 { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8781 { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8782 { PREFIX_TABLE (PREFIX_VEX_0F3832) },
8783 { PREFIX_TABLE (PREFIX_VEX_0F3833) },
8784 { PREFIX_TABLE (PREFIX_VEX_0F3834) },
8785 { PREFIX_TABLE (PREFIX_VEX_0F3835) },
8786 { PREFIX_TABLE (PREFIX_VEX_0F3836) },
8787 { PREFIX_TABLE (PREFIX_VEX_0F3837) },
8789 { PREFIX_TABLE (PREFIX_VEX_0F3838) },
8790 { PREFIX_TABLE (PREFIX_VEX_0F3839) },
8791 { PREFIX_TABLE (PREFIX_VEX_0F383A) },
8792 { PREFIX_TABLE (PREFIX_VEX_0F383B) },
8793 { PREFIX_TABLE (PREFIX_VEX_0F383C) },
8794 { PREFIX_TABLE (PREFIX_VEX_0F383D) },
8795 { PREFIX_TABLE (PREFIX_VEX_0F383E) },
8796 { PREFIX_TABLE (PREFIX_VEX_0F383F) },
8798 { PREFIX_TABLE (PREFIX_VEX_0F3840) },
8799 { PREFIX_TABLE (PREFIX_VEX_0F3841) },
8803 { PREFIX_TABLE (PREFIX_VEX_0F3845) },
8804 { PREFIX_TABLE (PREFIX_VEX_0F3846) },
8805 { PREFIX_TABLE (PREFIX_VEX_0F3847) },
8825 { PREFIX_TABLE (PREFIX_VEX_0F3858) },
8826 { PREFIX_TABLE (PREFIX_VEX_0F3859) },
8827 { PREFIX_TABLE (PREFIX_VEX_0F385A) },
8861 { PREFIX_TABLE (PREFIX_VEX_0F3878) },
8862 { PREFIX_TABLE (PREFIX_VEX_0F3879) },
8883 { PREFIX_TABLE (PREFIX_VEX_0F388C) },
8885 { PREFIX_TABLE (PREFIX_VEX_0F388E) },
8888 { PREFIX_TABLE (PREFIX_VEX_0F3890) },
8889 { PREFIX_TABLE (PREFIX_VEX_0F3891) },
8890 { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8891 { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8894 { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8895 { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8897 { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8898 { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8899 { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8900 { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8901 { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8902 { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8903 { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8904 { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8912 { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8913 { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8915 { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8916 { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8917 { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8918 { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8919 { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8920 { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8921 { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8922 { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8930 { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8931 { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8933 { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8934 { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8935 { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8936 { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8937 { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8938 { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8939 { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8940 { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8958 { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
8972 { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8973 { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8974 { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8975 { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8976 { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8998 { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8999 { REG_TABLE (REG_VEX_0F38F3) },
9001 { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9002 { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9003 { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9017 { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9018 { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9019 { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9021 { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9022 { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9023 { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9026 { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9027 { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9028 { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9029 { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9030 { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9031 { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9032 { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9033 { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9039 { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9040 { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9041 { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9042 { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9044 { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9045 { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9049 { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9053 { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9054 { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9055 { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9071 { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9072 { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9073 { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9074 { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9080 { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9081 { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9089 { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9090 { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9091 { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9093 { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9095 { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9098 { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9099 { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9100 { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9101 { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9102 { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9120 { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9121 { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9122 { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9123 { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9125 { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9126 { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9127 { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9128 { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9134 { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9135 { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9136 { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9137 { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9138 { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9139 { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9140 { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9141 { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9152 { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9153 { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9154 { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9155 { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9156 { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9157 { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9158 { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9159 { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9248 { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9249 { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9267 { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9287 { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9307 #include "i386-dis-evex.h"
9309 static const struct dis386 vex_len_table[][2] = {
9310 /* VEX_LEN_0F12_P_0_M_0 */
9312 { "vmovlps", { XM, Vex128, EXq }, 0 },
9315 /* VEX_LEN_0F12_P_0_M_1 */
9317 { "vmovhlps", { XM, Vex128, EXq }, 0 },
9320 /* VEX_LEN_0F12_P_2 */
9322 { "vmovlpd", { XM, Vex128, EXq }, 0 },
9325 /* VEX_LEN_0F13_M_0 */
9327 { "vmovlpX", { EXq, XM }, 0 },
9330 /* VEX_LEN_0F16_P_0_M_0 */
9332 { "vmovhps", { XM, Vex128, EXq }, 0 },
9335 /* VEX_LEN_0F16_P_0_M_1 */
9337 { "vmovlhps", { XM, Vex128, EXq }, 0 },
9340 /* VEX_LEN_0F16_P_2 */
9342 { "vmovhpd", { XM, Vex128, EXq }, 0 },
9345 /* VEX_LEN_0F17_M_0 */
9347 { "vmovhpX", { EXq, XM }, 0 },
9350 /* VEX_LEN_0F41_P_0 */
9353 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9355 /* VEX_LEN_0F41_P_2 */
9358 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9360 /* VEX_LEN_0F42_P_0 */
9363 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9365 /* VEX_LEN_0F42_P_2 */
9368 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9370 /* VEX_LEN_0F44_P_0 */
9372 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9374 /* VEX_LEN_0F44_P_2 */
9376 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9378 /* VEX_LEN_0F45_P_0 */
9381 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9383 /* VEX_LEN_0F45_P_2 */
9386 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9388 /* VEX_LEN_0F46_P_0 */
9391 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9393 /* VEX_LEN_0F46_P_2 */
9396 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9398 /* VEX_LEN_0F47_P_0 */
9401 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9403 /* VEX_LEN_0F47_P_2 */
9406 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9408 /* VEX_LEN_0F4A_P_0 */
9411 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9413 /* VEX_LEN_0F4A_P_2 */
9416 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9418 /* VEX_LEN_0F4B_P_0 */
9421 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9423 /* VEX_LEN_0F4B_P_2 */
9426 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9429 /* VEX_LEN_0F6E_P_2 */
9431 { "vmovK", { XMScalar, Edq }, 0 },
9434 /* VEX_LEN_0F77_P_1 */
9436 { "vzeroupper", { XX }, 0 },
9437 { "vzeroall", { XX }, 0 },
9440 /* VEX_LEN_0F7E_P_1 */
9442 { "vmovq", { XMScalar, EXqScalar }, 0 },
9445 /* VEX_LEN_0F7E_P_2 */
9447 { "vmovK", { Edq, XMScalar }, 0 },
9450 /* VEX_LEN_0F90_P_0 */
9452 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9455 /* VEX_LEN_0F90_P_2 */
9457 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9460 /* VEX_LEN_0F91_P_0 */
9462 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9465 /* VEX_LEN_0F91_P_2 */
9467 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9470 /* VEX_LEN_0F92_P_0 */
9472 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9475 /* VEX_LEN_0F92_P_2 */
9477 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9480 /* VEX_LEN_0F92_P_3 */
9482 { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
9485 /* VEX_LEN_0F93_P_0 */
9487 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9490 /* VEX_LEN_0F93_P_2 */
9492 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9495 /* VEX_LEN_0F93_P_3 */
9497 { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
9500 /* VEX_LEN_0F98_P_0 */
9502 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9505 /* VEX_LEN_0F98_P_2 */
9507 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9510 /* VEX_LEN_0F99_P_0 */
9512 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9515 /* VEX_LEN_0F99_P_2 */
9517 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9520 /* VEX_LEN_0FAE_R_2_M_0 */
9522 { "vldmxcsr", { Md }, 0 },
9525 /* VEX_LEN_0FAE_R_3_M_0 */
9527 { "vstmxcsr", { Md }, 0 },
9530 /* VEX_LEN_0FC4_P_2 */
9532 { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 },
9535 /* VEX_LEN_0FC5_P_2 */
9537 { "vpextrw", { Gdq, XS, Ib }, 0 },
9540 /* VEX_LEN_0FD6_P_2 */
9542 { "vmovq", { EXqScalarS, XMScalar }, 0 },
9545 /* VEX_LEN_0FF7_P_2 */
9547 { "vmaskmovdqu", { XM, XS }, 0 },
9550 /* VEX_LEN_0F3816_P_2 */
9553 { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9556 /* VEX_LEN_0F3819_P_2 */
9559 { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9562 /* VEX_LEN_0F381A_P_2_M_0 */
9565 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9568 /* VEX_LEN_0F3836_P_2 */
9571 { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9574 /* VEX_LEN_0F3841_P_2 */
9576 { "vphminposuw", { XM, EXx }, 0 },
9579 /* VEX_LEN_0F385A_P_2_M_0 */
9582 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
9585 /* VEX_LEN_0F38DB_P_2 */
9587 { "vaesimc", { XM, EXx }, 0 },
9590 /* VEX_LEN_0F38F2_P_0 */
9592 { "andnS", { Gdq, VexGdq, Edq }, 0 },
9595 /* VEX_LEN_0F38F3_R_1_P_0 */
9597 { "blsrS", { VexGdq, Edq }, 0 },
9600 /* VEX_LEN_0F38F3_R_2_P_0 */
9602 { "blsmskS", { VexGdq, Edq }, 0 },
9605 /* VEX_LEN_0F38F3_R_3_P_0 */
9607 { "blsiS", { VexGdq, Edq }, 0 },
9610 /* VEX_LEN_0F38F5_P_0 */
9612 { "bzhiS", { Gdq, Edq, VexGdq }, 0 },
9615 /* VEX_LEN_0F38F5_P_1 */
9617 { "pextS", { Gdq, VexGdq, Edq }, 0 },
9620 /* VEX_LEN_0F38F5_P_3 */
9622 { "pdepS", { Gdq, VexGdq, Edq }, 0 },
9625 /* VEX_LEN_0F38F6_P_3 */
9627 { "mulxS", { Gdq, VexGdq, Edq }, 0 },
9630 /* VEX_LEN_0F38F7_P_0 */
9632 { "bextrS", { Gdq, Edq, VexGdq }, 0 },
9635 /* VEX_LEN_0F38F7_P_1 */
9637 { "sarxS", { Gdq, Edq, VexGdq }, 0 },
9640 /* VEX_LEN_0F38F7_P_2 */
9642 { "shlxS", { Gdq, Edq, VexGdq }, 0 },
9645 /* VEX_LEN_0F38F7_P_3 */
9647 { "shrxS", { Gdq, Edq, VexGdq }, 0 },
9650 /* VEX_LEN_0F3A00_P_2 */
9653 { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
9656 /* VEX_LEN_0F3A01_P_2 */
9659 { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
9662 /* VEX_LEN_0F3A06_P_2 */
9665 { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
9668 /* VEX_LEN_0F3A14_P_2 */
9670 { "vpextrb", { Edqb, XM, Ib }, 0 },
9673 /* VEX_LEN_0F3A15_P_2 */
9675 { "vpextrw", { Edqw, XM, Ib }, 0 },
9678 /* VEX_LEN_0F3A16_P_2 */
9680 { "vpextrK", { Edq, XM, Ib }, 0 },
9683 /* VEX_LEN_0F3A17_P_2 */
9685 { "vextractps", { Edqd, XM, Ib }, 0 },
9688 /* VEX_LEN_0F3A18_P_2 */
9691 { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
9694 /* VEX_LEN_0F3A19_P_2 */
9697 { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
9700 /* VEX_LEN_0F3A20_P_2 */
9702 { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 },
9705 /* VEX_LEN_0F3A21_P_2 */
9707 { "vinsertps", { XM, Vex128, EXd, Ib }, 0 },
9710 /* VEX_LEN_0F3A22_P_2 */
9712 { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 },
9715 /* VEX_LEN_0F3A30_P_2 */
9717 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
9720 /* VEX_LEN_0F3A31_P_2 */
9722 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
9725 /* VEX_LEN_0F3A32_P_2 */
9727 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
9730 /* VEX_LEN_0F3A33_P_2 */
9732 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
9735 /* VEX_LEN_0F3A38_P_2 */
9738 { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
9741 /* VEX_LEN_0F3A39_P_2 */
9744 { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
9747 /* VEX_LEN_0F3A41_P_2 */
9749 { "vdppd", { XM, Vex128, EXx, Ib }, 0 },
9752 /* VEX_LEN_0F3A46_P_2 */
9755 { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
9758 /* VEX_LEN_0F3A60_P_2 */
9760 { "vpcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9763 /* VEX_LEN_0F3A61_P_2 */
9765 { "vpcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
9768 /* VEX_LEN_0F3A62_P_2 */
9770 { "vpcmpistrm", { XM, EXx, Ib }, 0 },
9773 /* VEX_LEN_0F3A63_P_2 */
9775 { "vpcmpistri", { XM, EXx, Ib }, 0 },
9778 /* VEX_LEN_0F3A6A_P_2 */
9780 { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9783 /* VEX_LEN_0F3A6B_P_2 */
9785 { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9788 /* VEX_LEN_0F3A6E_P_2 */
9790 { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9793 /* VEX_LEN_0F3A6F_P_2 */
9795 { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9798 /* VEX_LEN_0F3A7A_P_2 */
9800 { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9803 /* VEX_LEN_0F3A7B_P_2 */
9805 { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9808 /* VEX_LEN_0F3A7E_P_2 */
9810 { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
9813 /* VEX_LEN_0F3A7F_P_2 */
9815 { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
9818 /* VEX_LEN_0F3ADF_P_2 */
9820 { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
9823 /* VEX_LEN_0F3AF0_P_3 */
9825 { "rorxS", { Gdq, Edq, Ib }, 0 },
9828 /* VEX_LEN_0FXOP_08_CC */
9830 { "vpcomb", { XM, Vex128, EXx, VPCOM }, 0 },
9833 /* VEX_LEN_0FXOP_08_CD */
9835 { "vpcomw", { XM, Vex128, EXx, VPCOM }, 0 },
9838 /* VEX_LEN_0FXOP_08_CE */
9840 { "vpcomd", { XM, Vex128, EXx, VPCOM }, 0 },
9843 /* VEX_LEN_0FXOP_08_CF */
9845 { "vpcomq", { XM, Vex128, EXx, VPCOM }, 0 },
9848 /* VEX_LEN_0FXOP_08_EC */
9850 { "vpcomub", { XM, Vex128, EXx, VPCOM }, 0 },
9853 /* VEX_LEN_0FXOP_08_ED */
9855 { "vpcomuw", { XM, Vex128, EXx, VPCOM }, 0 },
9858 /* VEX_LEN_0FXOP_08_EE */
9860 { "vpcomud", { XM, Vex128, EXx, VPCOM }, 0 },
9863 /* VEX_LEN_0FXOP_08_EF */
9865 { "vpcomuq", { XM, Vex128, EXx, VPCOM }, 0 },
9868 /* VEX_LEN_0FXOP_09_80 */
9870 { "vfrczps", { XM, EXxmm }, 0 },
9871 { "vfrczps", { XM, EXymmq }, 0 },
9874 /* VEX_LEN_0FXOP_09_81 */
9876 { "vfrczpd", { XM, EXxmm }, 0 },
9877 { "vfrczpd", { XM, EXymmq }, 0 },
9881 #include "i386-dis-evex-len.h"
9883 static const struct dis386 vex_w_table[][2] = {
9885 /* VEX_W_0F41_P_0_LEN_1 */
9886 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
9887 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
9890 /* VEX_W_0F41_P_2_LEN_1 */
9891 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
9892 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
9895 /* VEX_W_0F42_P_0_LEN_1 */
9896 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
9897 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
9900 /* VEX_W_0F42_P_2_LEN_1 */
9901 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
9902 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
9905 /* VEX_W_0F44_P_0_LEN_0 */
9906 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
9907 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
9910 /* VEX_W_0F44_P_2_LEN_0 */
9911 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
9912 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
9915 /* VEX_W_0F45_P_0_LEN_1 */
9916 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
9917 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
9920 /* VEX_W_0F45_P_2_LEN_1 */
9921 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
9922 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
9925 /* VEX_W_0F46_P_0_LEN_1 */
9926 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
9927 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
9930 /* VEX_W_0F46_P_2_LEN_1 */
9931 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
9932 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
9935 /* VEX_W_0F47_P_0_LEN_1 */
9936 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
9937 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
9940 /* VEX_W_0F47_P_2_LEN_1 */
9941 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
9942 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
9945 /* VEX_W_0F4A_P_0_LEN_1 */
9946 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
9947 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
9950 /* VEX_W_0F4A_P_2_LEN_1 */
9951 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
9952 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
9955 /* VEX_W_0F4B_P_0_LEN_1 */
9956 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
9957 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
9960 /* VEX_W_0F4B_P_2_LEN_1 */
9961 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
9964 /* VEX_W_0F90_P_0_LEN_0 */
9965 { "kmovw", { MaskG, MaskE }, 0 },
9966 { "kmovq", { MaskG, MaskE }, 0 },
9969 /* VEX_W_0F90_P_2_LEN_0 */
9970 { "kmovb", { MaskG, MaskBDE }, 0 },
9971 { "kmovd", { MaskG, MaskBDE }, 0 },
9974 /* VEX_W_0F91_P_0_LEN_0 */
9975 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
9976 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
9979 /* VEX_W_0F91_P_2_LEN_0 */
9980 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
9981 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
9984 /* VEX_W_0F92_P_0_LEN_0 */
9985 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
9988 /* VEX_W_0F92_P_2_LEN_0 */
9989 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
9992 /* VEX_W_0F93_P_0_LEN_0 */
9993 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
9996 /* VEX_W_0F93_P_2_LEN_0 */
9997 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10000 /* VEX_W_0F98_P_0_LEN_0 */
10001 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10002 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10005 /* VEX_W_0F98_P_2_LEN_0 */
10006 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10007 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10010 /* VEX_W_0F99_P_0_LEN_0 */
10011 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10012 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10015 /* VEX_W_0F99_P_2_LEN_0 */
10016 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10017 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10020 /* VEX_W_0F380C_P_2 */
10021 { "vpermilps", { XM, Vex, EXx }, 0 },
10024 /* VEX_W_0F380D_P_2 */
10025 { "vpermilpd", { XM, Vex, EXx }, 0 },
10028 /* VEX_W_0F380E_P_2 */
10029 { "vtestps", { XM, EXx }, 0 },
10032 /* VEX_W_0F380F_P_2 */
10033 { "vtestpd", { XM, EXx }, 0 },
10036 /* VEX_W_0F3816_P_2 */
10037 { "vpermps", { XM, Vex, EXx }, 0 },
10040 /* VEX_W_0F3818_P_2 */
10041 { "vbroadcastss", { XM, EXxmm_md }, 0 },
10044 /* VEX_W_0F3819_P_2 */
10045 { "vbroadcastsd", { XM, EXxmm_mq }, 0 },
10048 /* VEX_W_0F381A_P_2_M_0 */
10049 { "vbroadcastf128", { XM, Mxmm }, 0 },
10052 /* VEX_W_0F382C_P_2_M_0 */
10053 { "vmaskmovps", { XM, Vex, Mx }, 0 },
10056 /* VEX_W_0F382D_P_2_M_0 */
10057 { "vmaskmovpd", { XM, Vex, Mx }, 0 },
10060 /* VEX_W_0F382E_P_2_M_0 */
10061 { "vmaskmovps", { Mx, Vex, XM }, 0 },
10064 /* VEX_W_0F382F_P_2_M_0 */
10065 { "vmaskmovpd", { Mx, Vex, XM }, 0 },
10068 /* VEX_W_0F3836_P_2 */
10069 { "vpermd", { XM, Vex, EXx }, 0 },
10072 /* VEX_W_0F3846_P_2 */
10073 { "vpsravd", { XM, Vex, EXx }, 0 },
10076 /* VEX_W_0F3858_P_2 */
10077 { "vpbroadcastd", { XM, EXxmm_md }, 0 },
10080 /* VEX_W_0F3859_P_2 */
10081 { "vpbroadcastq", { XM, EXxmm_mq }, 0 },
10084 /* VEX_W_0F385A_P_2_M_0 */
10085 { "vbroadcasti128", { XM, Mxmm }, 0 },
10088 /* VEX_W_0F3878_P_2 */
10089 { "vpbroadcastb", { XM, EXxmm_mb }, 0 },
10092 /* VEX_W_0F3879_P_2 */
10093 { "vpbroadcastw", { XM, EXxmm_mw }, 0 },
10096 /* VEX_W_0F38CF_P_2 */
10097 { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
10100 /* VEX_W_0F3A00_P_2 */
10102 { "vpermq", { XM, EXx, Ib }, 0 },
10105 /* VEX_W_0F3A01_P_2 */
10107 { "vpermpd", { XM, EXx, Ib }, 0 },
10110 /* VEX_W_0F3A02_P_2 */
10111 { "vpblendd", { XM, Vex, EXx, Ib }, 0 },
10114 /* VEX_W_0F3A04_P_2 */
10115 { "vpermilps", { XM, EXx, Ib }, 0 },
10118 /* VEX_W_0F3A05_P_2 */
10119 { "vpermilpd", { XM, EXx, Ib }, 0 },
10122 /* VEX_W_0F3A06_P_2 */
10123 { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 },
10126 /* VEX_W_0F3A18_P_2 */
10127 { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 },
10130 /* VEX_W_0F3A19_P_2 */
10131 { "vextractf128", { EXxmm, XM, Ib }, 0 },
10134 /* VEX_W_0F3A30_P_2_LEN_0 */
10135 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
10136 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
10139 /* VEX_W_0F3A31_P_2_LEN_0 */
10140 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
10141 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
10144 /* VEX_W_0F3A32_P_2_LEN_0 */
10145 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
10146 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
10149 /* VEX_W_0F3A33_P_2_LEN_0 */
10150 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
10151 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
10154 /* VEX_W_0F3A38_P_2 */
10155 { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 },
10158 /* VEX_W_0F3A39_P_2 */
10159 { "vextracti128", { EXxmm, XM, Ib }, 0 },
10162 /* VEX_W_0F3A46_P_2 */
10163 { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 },
10166 /* VEX_W_0F3A48_P_2 */
10167 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10168 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10171 /* VEX_W_0F3A49_P_2 */
10172 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10173 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
10176 /* VEX_W_0F3A4A_P_2 */
10177 { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 },
10180 /* VEX_W_0F3A4B_P_2 */
10181 { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 },
10184 /* VEX_W_0F3A4C_P_2 */
10185 { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 },
10188 /* VEX_W_0F3ACE_P_2 */
10190 { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
10193 /* VEX_W_0F3ACF_P_2 */
10195 { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, 0 },
10198 #include "i386-dis-evex-w.h"
10201 static const struct dis386 mod_table[][2] = {
10204 { "leaS", { Gv, M }, 0 },
10209 { RM_TABLE (RM_C6_REG_7) },
10214 { RM_TABLE (RM_C7_REG_7) },
10218 { "Jcall^", { indirEp }, 0 },
10222 { "Jjmp^", { indirEp }, 0 },
10225 /* MOD_0F01_REG_0 */
10226 { X86_64_TABLE (X86_64_0F01_REG_0) },
10227 { RM_TABLE (RM_0F01_REG_0) },
10230 /* MOD_0F01_REG_1 */
10231 { X86_64_TABLE (X86_64_0F01_REG_1) },
10232 { RM_TABLE (RM_0F01_REG_1) },
10235 /* MOD_0F01_REG_2 */
10236 { X86_64_TABLE (X86_64_0F01_REG_2) },
10237 { RM_TABLE (RM_0F01_REG_2) },
10240 /* MOD_0F01_REG_3 */
10241 { X86_64_TABLE (X86_64_0F01_REG_3) },
10242 { RM_TABLE (RM_0F01_REG_3) },
10245 /* MOD_0F01_REG_5 */
10246 { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
10247 { RM_TABLE (RM_0F01_REG_5) },
10250 /* MOD_0F01_REG_7 */
10251 { "invlpg", { Mb }, 0 },
10252 { RM_TABLE (RM_0F01_REG_7) },
10255 /* MOD_0F12_PREFIX_0 */
10256 { "movlps", { XM, EXq }, PREFIX_OPCODE },
10257 { "movhlps", { XM, EXq }, PREFIX_OPCODE },
10261 { "movlpX", { EXq, XM }, PREFIX_OPCODE },
10264 /* MOD_0F16_PREFIX_0 */
10265 { "movhps", { XM, EXq }, 0 },
10266 { "movlhps", { XM, EXq }, 0 },
10270 { "movhpX", { EXq, XM }, PREFIX_OPCODE },
10273 /* MOD_0F18_REG_0 */
10274 { "prefetchnta", { Mb }, 0 },
10277 /* MOD_0F18_REG_1 */
10278 { "prefetcht0", { Mb }, 0 },
10281 /* MOD_0F18_REG_2 */
10282 { "prefetcht1", { Mb }, 0 },
10285 /* MOD_0F18_REG_3 */
10286 { "prefetcht2", { Mb }, 0 },
10289 /* MOD_0F18_REG_4 */
10290 { "nop/reserved", { Mb }, 0 },
10293 /* MOD_0F18_REG_5 */
10294 { "nop/reserved", { Mb }, 0 },
10297 /* MOD_0F18_REG_6 */
10298 { "nop/reserved", { Mb }, 0 },
10301 /* MOD_0F18_REG_7 */
10302 { "nop/reserved", { Mb }, 0 },
10305 /* MOD_0F1A_PREFIX_0 */
10306 { "bndldx", { Gbnd, Mv_bnd }, 0 },
10307 { "nopQ", { Ev }, 0 },
10310 /* MOD_0F1B_PREFIX_0 */
10311 { "bndstx", { Mv_bnd, Gbnd }, 0 },
10312 { "nopQ", { Ev }, 0 },
10315 /* MOD_0F1B_PREFIX_1 */
10316 { "bndmk", { Gbnd, Mv_bnd }, 0 },
10317 { "nopQ", { Ev }, 0 },
10320 /* MOD_0F1C_PREFIX_0 */
10321 { REG_TABLE (REG_0F1C_MOD_0) },
10322 { "nopQ", { Ev }, 0 },
10325 /* MOD_0F1E_PREFIX_1 */
10326 { "nopQ", { Ev }, 0 },
10327 { REG_TABLE (REG_0F1E_MOD_3) },
10332 { "movL", { Rd, Td }, 0 },
10337 { "movL", { Td, Rd }, 0 },
10340 /* MOD_0F2B_PREFIX_0 */
10341 {"movntps", { Mx, XM }, PREFIX_OPCODE },
10344 /* MOD_0F2B_PREFIX_1 */
10345 {"movntss", { Md, XM }, PREFIX_OPCODE },
10348 /* MOD_0F2B_PREFIX_2 */
10349 {"movntpd", { Mx, XM }, PREFIX_OPCODE },
10352 /* MOD_0F2B_PREFIX_3 */
10353 {"movntsd", { Mq, XM }, PREFIX_OPCODE },
10358 { "movmskpX", { Gdq, XS }, PREFIX_OPCODE },
10361 /* MOD_0F71_REG_2 */
10363 { "psrlw", { MS, Ib }, 0 },
10366 /* MOD_0F71_REG_4 */
10368 { "psraw", { MS, Ib }, 0 },
10371 /* MOD_0F71_REG_6 */
10373 { "psllw", { MS, Ib }, 0 },
10376 /* MOD_0F72_REG_2 */
10378 { "psrld", { MS, Ib }, 0 },
10381 /* MOD_0F72_REG_4 */
10383 { "psrad", { MS, Ib }, 0 },
10386 /* MOD_0F72_REG_6 */
10388 { "pslld", { MS, Ib }, 0 },
10391 /* MOD_0F73_REG_2 */
10393 { "psrlq", { MS, Ib }, 0 },
10396 /* MOD_0F73_REG_3 */
10398 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10401 /* MOD_0F73_REG_6 */
10403 { "psllq", { MS, Ib }, 0 },
10406 /* MOD_0F73_REG_7 */
10408 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10411 /* MOD_0FAE_REG_0 */
10412 { "fxsave", { FXSAVE }, 0 },
10413 { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
10416 /* MOD_0FAE_REG_1 */
10417 { "fxrstor", { FXSAVE }, 0 },
10418 { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
10421 /* MOD_0FAE_REG_2 */
10422 { "ldmxcsr", { Md }, 0 },
10423 { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
10426 /* MOD_0FAE_REG_3 */
10427 { "stmxcsr", { Md }, 0 },
10428 { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
10431 /* MOD_0FAE_REG_4 */
10432 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
10433 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
10436 /* MOD_0FAE_REG_5 */
10437 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
10438 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
10441 /* MOD_0FAE_REG_6 */
10442 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6) },
10443 { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6) },
10446 /* MOD_0FAE_REG_7 */
10447 { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
10448 { RM_TABLE (RM_0FAE_REG_7) },
10452 { "lssS", { Gv, Mp }, 0 },
10456 { "lfsS", { Gv, Mp }, 0 },
10460 { "lgsS", { Gv, Mp }, 0 },
10464 { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
10467 /* MOD_0FC7_REG_3 */
10468 { "xrstors", { FXSAVE }, 0 },
10471 /* MOD_0FC7_REG_4 */
10472 { "xsavec", { FXSAVE }, 0 },
10475 /* MOD_0FC7_REG_5 */
10476 { "xsaves", { FXSAVE }, 0 },
10479 /* MOD_0FC7_REG_6 */
10480 { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
10481 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
10484 /* MOD_0FC7_REG_7 */
10485 { "vmptrst", { Mq }, 0 },
10486 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
10491 { "pmovmskb", { Gdq, MS }, 0 },
10494 /* MOD_0FE7_PREFIX_2 */
10495 { "movntdq", { Mx, XM }, 0 },
10498 /* MOD_0FF0_PREFIX_3 */
10499 { "lddqu", { XM, M }, 0 },
10502 /* MOD_0F382A_PREFIX_2 */
10503 { "movntdqa", { XM, Mx }, 0 },
10506 /* MOD_0F38F5_PREFIX_2 */
10507 { "wrussK", { M, Gdq }, PREFIX_OPCODE },
10510 /* MOD_0F38F6_PREFIX_0 */
10511 { "wrssK", { M, Gdq }, PREFIX_OPCODE },
10514 /* MOD_0F38F8_PREFIX_1 */
10515 { "enqcmds", { Gva, M }, PREFIX_OPCODE },
10518 /* MOD_0F38F8_PREFIX_2 */
10519 { "movdir64b", { Gva, M }, PREFIX_OPCODE },
10522 /* MOD_0F38F8_PREFIX_3 */
10523 { "enqcmd", { Gva, M }, PREFIX_OPCODE },
10526 /* MOD_0F38F9_PREFIX_0 */
10527 { "movdiri", { Em, Gv }, PREFIX_OPCODE },
10531 { "bound{S|}", { Gv, Ma }, 0 },
10532 { EVEX_TABLE (EVEX_0F) },
10536 { "lesS", { Gv, Mp }, 0 },
10537 { VEX_C4_TABLE (VEX_0F) },
10541 { "ldsS", { Gv, Mp }, 0 },
10542 { VEX_C5_TABLE (VEX_0F) },
10545 /* MOD_VEX_0F12_PREFIX_0 */
10546 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10547 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10551 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10554 /* MOD_VEX_0F16_PREFIX_0 */
10555 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10556 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10560 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10564 { "vmovntpX", { Mx, XM }, 0 },
10567 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
10569 { "kandw", { MaskG, MaskVex, MaskR }, 0 },
10572 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
10574 { "kandq", { MaskG, MaskVex, MaskR }, 0 },
10577 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
10579 { "kandb", { MaskG, MaskVex, MaskR }, 0 },
10582 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
10584 { "kandd", { MaskG, MaskVex, MaskR }, 0 },
10587 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
10589 { "kandnw", { MaskG, MaskVex, MaskR }, 0 },
10592 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
10594 { "kandnq", { MaskG, MaskVex, MaskR }, 0 },
10597 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
10599 { "kandnb", { MaskG, MaskVex, MaskR }, 0 },
10602 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
10604 { "kandnd", { MaskG, MaskVex, MaskR }, 0 },
10607 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
10609 { "knotw", { MaskG, MaskR }, 0 },
10612 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
10614 { "knotq", { MaskG, MaskR }, 0 },
10617 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
10619 { "knotb", { MaskG, MaskR }, 0 },
10622 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
10624 { "knotd", { MaskG, MaskR }, 0 },
10627 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
10629 { "korw", { MaskG, MaskVex, MaskR }, 0 },
10632 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
10634 { "korq", { MaskG, MaskVex, MaskR }, 0 },
10637 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
10639 { "korb", { MaskG, MaskVex, MaskR }, 0 },
10642 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
10644 { "kord", { MaskG, MaskVex, MaskR }, 0 },
10647 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
10649 { "kxnorw", { MaskG, MaskVex, MaskR }, 0 },
10652 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
10654 { "kxnorq", { MaskG, MaskVex, MaskR }, 0 },
10657 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
10659 { "kxnorb", { MaskG, MaskVex, MaskR }, 0 },
10662 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
10664 { "kxnord", { MaskG, MaskVex, MaskR }, 0 },
10667 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
10669 { "kxorw", { MaskG, MaskVex, MaskR }, 0 },
10672 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
10674 { "kxorq", { MaskG, MaskVex, MaskR }, 0 },
10677 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
10679 { "kxorb", { MaskG, MaskVex, MaskR }, 0 },
10682 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
10684 { "kxord", { MaskG, MaskVex, MaskR }, 0 },
10687 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
10689 { "kaddw", { MaskG, MaskVex, MaskR }, 0 },
10692 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
10694 { "kaddq", { MaskG, MaskVex, MaskR }, 0 },
10697 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
10699 { "kaddb", { MaskG, MaskVex, MaskR }, 0 },
10702 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
10704 { "kaddd", { MaskG, MaskVex, MaskR }, 0 },
10707 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
10709 { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 },
10712 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
10714 { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 },
10717 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
10719 { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 },
10724 { "vmovmskpX", { Gdq, XS }, 0 },
10727 /* MOD_VEX_0F71_REG_2 */
10729 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10732 /* MOD_VEX_0F71_REG_4 */
10734 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10737 /* MOD_VEX_0F71_REG_6 */
10739 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10742 /* MOD_VEX_0F72_REG_2 */
10744 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10747 /* MOD_VEX_0F72_REG_4 */
10749 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10752 /* MOD_VEX_0F72_REG_6 */
10754 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10757 /* MOD_VEX_0F73_REG_2 */
10759 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10762 /* MOD_VEX_0F73_REG_3 */
10764 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10767 /* MOD_VEX_0F73_REG_6 */
10769 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10772 /* MOD_VEX_0F73_REG_7 */
10774 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10777 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10778 { "kmovw", { Ew, MaskG }, 0 },
10782 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
10783 { "kmovq", { Eq, MaskG }, 0 },
10787 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10788 { "kmovb", { Eb, MaskG }, 0 },
10792 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
10793 { "kmovd", { Ed, MaskG }, 0 },
10797 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
10799 { "kmovw", { MaskG, Rdq }, 0 },
10802 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
10804 { "kmovb", { MaskG, Rdq }, 0 },
10807 /* MOD_VEX_0F92_P_3_LEN_0 */
10809 { "kmovK", { MaskG, Rdq }, 0 },
10812 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
10814 { "kmovw", { Gdq, MaskR }, 0 },
10817 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
10819 { "kmovb", { Gdq, MaskR }, 0 },
10822 /* MOD_VEX_0F93_P_3_LEN_0 */
10824 { "kmovK", { Gdq, MaskR }, 0 },
10827 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
10829 { "kortestw", { MaskG, MaskR }, 0 },
10832 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
10834 { "kortestq", { MaskG, MaskR }, 0 },
10837 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
10839 { "kortestb", { MaskG, MaskR }, 0 },
10842 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
10844 { "kortestd", { MaskG, MaskR }, 0 },
10847 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
10849 { "ktestw", { MaskG, MaskR }, 0 },
10852 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
10854 { "ktestq", { MaskG, MaskR }, 0 },
10857 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
10859 { "ktestb", { MaskG, MaskR }, 0 },
10862 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
10864 { "ktestd", { MaskG, MaskR }, 0 },
10867 /* MOD_VEX_0FAE_REG_2 */
10868 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10871 /* MOD_VEX_0FAE_REG_3 */
10872 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10875 /* MOD_VEX_0FD7_PREFIX_2 */
10877 { "vpmovmskb", { Gdq, XS }, 0 },
10880 /* MOD_VEX_0FE7_PREFIX_2 */
10881 { "vmovntdq", { Mx, XM }, 0 },
10884 /* MOD_VEX_0FF0_PREFIX_3 */
10885 { "vlddqu", { XM, M }, 0 },
10888 /* MOD_VEX_0F381A_PREFIX_2 */
10889 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10892 /* MOD_VEX_0F382A_PREFIX_2 */
10893 { "vmovntdqa", { XM, Mx }, 0 },
10896 /* MOD_VEX_0F382C_PREFIX_2 */
10897 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10900 /* MOD_VEX_0F382D_PREFIX_2 */
10901 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10904 /* MOD_VEX_0F382E_PREFIX_2 */
10905 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10908 /* MOD_VEX_0F382F_PREFIX_2 */
10909 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10912 /* MOD_VEX_0F385A_PREFIX_2 */
10913 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10916 /* MOD_VEX_0F388C_PREFIX_2 */
10917 { "vpmaskmov%LW", { XM, Vex, Mx }, 0 },
10920 /* MOD_VEX_0F388E_PREFIX_2 */
10921 { "vpmaskmov%LW", { Mx, Vex, XM }, 0 },
10924 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
10926 { "kshiftrb", { MaskG, MaskR, Ib }, 0 },
10929 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
10931 { "kshiftrw", { MaskG, MaskR, Ib }, 0 },
10934 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
10936 { "kshiftrd", { MaskG, MaskR, Ib }, 0 },
10939 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
10941 { "kshiftrq", { MaskG, MaskR, Ib }, 0 },
10944 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
10946 { "kshiftlb", { MaskG, MaskR, Ib }, 0 },
10949 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
10951 { "kshiftlw", { MaskG, MaskR, Ib }, 0 },
10954 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
10956 { "kshiftld", { MaskG, MaskR, Ib }, 0 },
10959 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
10961 { "kshiftlq", { MaskG, MaskR, Ib }, 0 },
10964 #include "i386-dis-evex-mod.h"
10967 static const struct dis386 rm_table[][8] = {
10970 { "xabort", { Skip_MODRM, Ib }, 0 },
10974 { "xbeginT", { Skip_MODRM, Jv }, 0 },
10977 /* RM_0F01_REG_0 */
10978 { "enclv", { Skip_MODRM }, 0 },
10979 { "vmcall", { Skip_MODRM }, 0 },
10980 { "vmlaunch", { Skip_MODRM }, 0 },
10981 { "vmresume", { Skip_MODRM }, 0 },
10982 { "vmxoff", { Skip_MODRM }, 0 },
10983 { "pconfig", { Skip_MODRM }, 0 },
10986 /* RM_0F01_REG_1 */
10987 { "monitor", { { OP_Monitor, 0 } }, 0 },
10988 { "mwait", { { OP_Mwait, 0 } }, 0 },
10989 { "clac", { Skip_MODRM }, 0 },
10990 { "stac", { Skip_MODRM }, 0 },
10994 { "encls", { Skip_MODRM }, 0 },
10997 /* RM_0F01_REG_2 */
10998 { "xgetbv", { Skip_MODRM }, 0 },
10999 { "xsetbv", { Skip_MODRM }, 0 },
11002 { "vmfunc", { Skip_MODRM }, 0 },
11003 { "xend", { Skip_MODRM }, 0 },
11004 { "xtest", { Skip_MODRM }, 0 },
11005 { "enclu", { Skip_MODRM }, 0 },
11008 /* RM_0F01_REG_3 */
11009 { "vmrun", { Skip_MODRM }, 0 },
11010 { "vmmcall", { Skip_MODRM }, 0 },
11011 { "vmload", { Skip_MODRM }, 0 },
11012 { "vmsave", { Skip_MODRM }, 0 },
11013 { "stgi", { Skip_MODRM }, 0 },
11014 { "clgi", { Skip_MODRM }, 0 },
11015 { "skinit", { Skip_MODRM }, 0 },
11016 { "invlpga", { Skip_MODRM }, 0 },
11019 /* RM_0F01_REG_5 */
11020 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
11022 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
11026 { "rdpkru", { Skip_MODRM }, 0 },
11027 { "wrpkru", { Skip_MODRM }, 0 },
11030 /* RM_0F01_REG_7 */
11031 { "swapgs", { Skip_MODRM }, 0 },
11032 { "rdtscp", { Skip_MODRM }, 0 },
11033 { "monitorx", { { OP_Monitor, 0 } }, 0 },
11034 { "mwaitx", { { OP_Mwaitx, 0 } }, 0 },
11035 { "clzero", { Skip_MODRM }, 0 },
11038 /* RM_0F1E_MOD_3_REG_7 */
11039 { "nopQ", { Ev }, 0 },
11040 { "nopQ", { Ev }, 0 },
11041 { "endbr64", { Skip_MODRM }, PREFIX_OPCODE },
11042 { "endbr32", { Skip_MODRM }, PREFIX_OPCODE },
11043 { "nopQ", { Ev }, 0 },
11044 { "nopQ", { Ev }, 0 },
11045 { "nopQ", { Ev }, 0 },
11046 { "nopQ", { Ev }, 0 },
11049 /* RM_0FAE_REG_6 */
11050 { "mfence", { Skip_MODRM }, 0 },
11053 /* RM_0FAE_REG_7 */
11054 { "sfence", { Skip_MODRM }, 0 },
11059 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
11061 /* We use the high bit to indicate different name for the same
11063 #define REP_PREFIX (0xf3 | 0x100)
11064 #define XACQUIRE_PREFIX (0xf2 | 0x200)
11065 #define XRELEASE_PREFIX (0xf3 | 0x400)
11066 #define BND_PREFIX (0xf2 | 0x400)
11067 #define NOTRACK_PREFIX (0x3e | 0x100)
11072 int newrex, i, length;
11078 last_lock_prefix = -1;
11079 last_repz_prefix = -1;
11080 last_repnz_prefix = -1;
11081 last_data_prefix = -1;
11082 last_addr_prefix = -1;
11083 last_rex_prefix = -1;
11084 last_seg_prefix = -1;
11086 active_seg_prefix = 0;
11087 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11088 all_prefixes[i] = 0;
11091 /* The maximum instruction length is 15bytes. */
11092 while (length < MAX_CODE_LENGTH - 1)
11094 FETCH_DATA (the_info, codep + 1);
11098 /* REX prefixes family. */
11115 if (address_mode == mode_64bit)
11119 last_rex_prefix = i;
11122 prefixes |= PREFIX_REPZ;
11123 last_repz_prefix = i;
11126 prefixes |= PREFIX_REPNZ;
11127 last_repnz_prefix = i;
11130 prefixes |= PREFIX_LOCK;
11131 last_lock_prefix = i;
11134 prefixes |= PREFIX_CS;
11135 last_seg_prefix = i;
11136 active_seg_prefix = PREFIX_CS;
11139 prefixes |= PREFIX_SS;
11140 last_seg_prefix = i;
11141 active_seg_prefix = PREFIX_SS;
11144 prefixes |= PREFIX_DS;
11145 last_seg_prefix = i;
11146 active_seg_prefix = PREFIX_DS;
11149 prefixes |= PREFIX_ES;
11150 last_seg_prefix = i;
11151 active_seg_prefix = PREFIX_ES;
11154 prefixes |= PREFIX_FS;
11155 last_seg_prefix = i;
11156 active_seg_prefix = PREFIX_FS;
11159 prefixes |= PREFIX_GS;
11160 last_seg_prefix = i;
11161 active_seg_prefix = PREFIX_GS;
11164 prefixes |= PREFIX_DATA;
11165 last_data_prefix = i;
11168 prefixes |= PREFIX_ADDR;
11169 last_addr_prefix = i;
11172 /* fwait is really an instruction. If there are prefixes
11173 before the fwait, they belong to the fwait, *not* to the
11174 following instruction. */
11176 if (prefixes || rex)
11178 prefixes |= PREFIX_FWAIT;
11180 /* This ensures that the previous REX prefixes are noticed
11181 as unused prefixes, as in the return case below. */
11185 prefixes = PREFIX_FWAIT;
11190 /* Rex is ignored when followed by another prefix. */
11196 if (*codep != FWAIT_OPCODE)
11197 all_prefixes[i++] = *codep;
11205 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
11208 static const char *
11209 prefix_name (int pref, int sizeflag)
11211 static const char *rexes [16] =
11214 "rex.B", /* 0x41 */
11215 "rex.X", /* 0x42 */
11216 "rex.XB", /* 0x43 */
11217 "rex.R", /* 0x44 */
11218 "rex.RB", /* 0x45 */
11219 "rex.RX", /* 0x46 */
11220 "rex.RXB", /* 0x47 */
11221 "rex.W", /* 0x48 */
11222 "rex.WB", /* 0x49 */
11223 "rex.WX", /* 0x4a */
11224 "rex.WXB", /* 0x4b */
11225 "rex.WR", /* 0x4c */
11226 "rex.WRB", /* 0x4d */
11227 "rex.WRX", /* 0x4e */
11228 "rex.WRXB", /* 0x4f */
11233 /* REX prefixes family. */
11250 return rexes [pref - 0x40];
11270 return (sizeflag & DFLAG) ? "data16" : "data32";
11272 if (address_mode == mode_64bit)
11273 return (sizeflag & AFLAG) ? "addr32" : "addr64";
11275 return (sizeflag & AFLAG) ? "addr16" : "addr32";
11280 case XACQUIRE_PREFIX:
11282 case XRELEASE_PREFIX:
11286 case NOTRACK_PREFIX:
11293 static char op_out[MAX_OPERANDS][100];
11294 static int op_ad, op_index[MAX_OPERANDS];
11295 static int two_source_ops;
11296 static bfd_vma op_address[MAX_OPERANDS];
11297 static bfd_vma op_riprel[MAX_OPERANDS];
11298 static bfd_vma start_pc;
11301 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
11302 * (see topic "Redundant prefixes" in the "Differences from 8086"
11303 * section of the "Virtual 8086 Mode" chapter.)
11304 * 'pc' should be the address of this instruction, it will
11305 * be used to print the target address if this is a relative jump or call
11306 * The function returns the length of this instruction in bytes.
11309 static char intel_syntax;
11310 static char intel_mnemonic = !SYSV386_COMPAT;
11311 static char open_char;
11312 static char close_char;
11313 static char separator_char;
11314 static char scale_char;
11322 static enum x86_64_isa isa64;
11324 /* Here for backwards compatibility. When gdb stops using
11325 print_insn_i386_att and print_insn_i386_intel these functions can
11326 disappear, and print_insn_i386 be merged into print_insn. */
11328 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
11332 return print_insn (pc, info);
11336 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
11340 return print_insn (pc, info);
11344 print_insn_i386 (bfd_vma pc, disassemble_info *info)
11348 return print_insn (pc, info);
11352 print_i386_disassembler_options (FILE *stream)
11354 fprintf (stream, _("\n\
11355 The following i386/x86-64 specific disassembler options are supported for use\n\
11356 with the -M switch (multiple options should be separated by commas):\n"));
11358 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
11359 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
11360 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
11361 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
11362 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
11363 fprintf (stream, _(" att-mnemonic\n"
11364 " Display instruction in AT&T mnemonic\n"));
11365 fprintf (stream, _(" intel-mnemonic\n"
11366 " Display instruction in Intel mnemonic\n"));
11367 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
11368 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
11369 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
11370 fprintf (stream, _(" data32 Assume 32bit data size\n"));
11371 fprintf (stream, _(" data16 Assume 16bit data size\n"));
11372 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
11373 fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n"));
11374 fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n"));
11378 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
11380 /* Get a pointer to struct dis386 with a valid name. */
11382 static const struct dis386 *
11383 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
11385 int vindex, vex_table_index;
11387 if (dp->name != NULL)
11390 switch (dp->op[0].bytemode)
11392 case USE_REG_TABLE:
11393 dp = ®_table[dp->op[1].bytemode][modrm.reg];
11396 case USE_MOD_TABLE:
11397 vindex = modrm.mod == 0x3 ? 1 : 0;
11398 dp = &mod_table[dp->op[1].bytemode][vindex];
11402 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
11405 case USE_PREFIX_TABLE:
11408 /* The prefix in VEX is implicit. */
11409 switch (vex.prefix)
11414 case REPE_PREFIX_OPCODE:
11417 case DATA_PREFIX_OPCODE:
11420 case REPNE_PREFIX_OPCODE:
11430 int last_prefix = -1;
11433 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
11434 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
11436 if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
11438 if (last_repz_prefix > last_repnz_prefix)
11441 prefix = PREFIX_REPZ;
11442 last_prefix = last_repz_prefix;
11447 prefix = PREFIX_REPNZ;
11448 last_prefix = last_repnz_prefix;
11451 /* Check if prefix should be ignored. */
11452 if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
11453 & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
11458 if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
11461 prefix = PREFIX_DATA;
11462 last_prefix = last_data_prefix;
11467 used_prefixes |= prefix;
11468 all_prefixes[last_prefix] = 0;
11471 dp = &prefix_table[dp->op[1].bytemode][vindex];
11474 case USE_X86_64_TABLE:
11475 vindex = address_mode == mode_64bit ? 1 : 0;
11476 dp = &x86_64_table[dp->op[1].bytemode][vindex];
11479 case USE_3BYTE_TABLE:
11480 FETCH_DATA (info, codep + 2);
11482 dp = &three_byte_table[dp->op[1].bytemode][vindex];
11484 modrm.mod = (*codep >> 6) & 3;
11485 modrm.reg = (*codep >> 3) & 7;
11486 modrm.rm = *codep & 7;
11489 case USE_VEX_LEN_TABLE:
11493 switch (vex.length)
11506 dp = &vex_len_table[dp->op[1].bytemode][vindex];
11509 case USE_EVEX_LEN_TABLE:
11513 switch (vex.length)
11529 dp = &evex_len_table[dp->op[1].bytemode][vindex];
11532 case USE_XOP_8F_TABLE:
11533 FETCH_DATA (info, codep + 3);
11534 /* All bits in the REX prefix are ignored. */
11536 rex = ~(*codep >> 5) & 0x7;
11538 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
11539 switch ((*codep & 0x1f))
11545 vex_table_index = XOP_08;
11548 vex_table_index = XOP_09;
11551 vex_table_index = XOP_0A;
11555 vex.w = *codep & 0x80;
11556 if (vex.w && address_mode == mode_64bit)
11559 vex.register_specifier = (~(*codep >> 3)) & 0xf;
11560 if (address_mode != mode_64bit)
11562 /* In 16/32-bit mode REX_B is silently ignored. */
11566 vex.length = (*codep & 0x4) ? 256 : 128;
11567 switch ((*codep & 0x3))
11572 vex.prefix = DATA_PREFIX_OPCODE;
11575 vex.prefix = REPE_PREFIX_OPCODE;
11578 vex.prefix = REPNE_PREFIX_OPCODE;
11585 dp = &xop_table[vex_table_index][vindex];
11588 FETCH_DATA (info, codep + 1);
11589 modrm.mod = (*codep >> 6) & 3;
11590 modrm.reg = (*codep >> 3) & 7;
11591 modrm.rm = *codep & 7;
11594 case USE_VEX_C4_TABLE:
11596 FETCH_DATA (info, codep + 3);
11597 /* All bits in the REX prefix are ignored. */
11599 rex = ~(*codep >> 5) & 0x7;
11600 switch ((*codep & 0x1f))
11606 vex_table_index = VEX_0F;
11609 vex_table_index = VEX_0F38;
11612 vex_table_index = VEX_0F3A;
11616 vex.w = *codep & 0x80;
11617 if (address_mode == mode_64bit)
11624 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
11625 is ignored, other REX bits are 0 and the highest bit in
11626 VEX.vvvv is also ignored (but we mustn't clear it here). */
11629 vex.register_specifier = (~(*codep >> 3)) & 0xf;
11630 vex.length = (*codep & 0x4) ? 256 : 128;
11631 switch ((*codep & 0x3))
11636 vex.prefix = DATA_PREFIX_OPCODE;
11639 vex.prefix = REPE_PREFIX_OPCODE;
11642 vex.prefix = REPNE_PREFIX_OPCODE;
11649 dp = &vex_table[vex_table_index][vindex];
11651 /* There is no MODRM byte for VEX0F 77. */
11652 if (vex_table_index != VEX_0F || vindex != 0x77)
11654 FETCH_DATA (info, codep + 1);
11655 modrm.mod = (*codep >> 6) & 3;
11656 modrm.reg = (*codep >> 3) & 7;
11657 modrm.rm = *codep & 7;
11661 case USE_VEX_C5_TABLE:
11663 FETCH_DATA (info, codep + 2);
11664 /* All bits in the REX prefix are ignored. */
11666 rex = (*codep & 0x80) ? 0 : REX_R;
11668 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
11670 vex.register_specifier = (~(*codep >> 3)) & 0xf;
11671 vex.length = (*codep & 0x4) ? 256 : 128;
11672 switch ((*codep & 0x3))
11677 vex.prefix = DATA_PREFIX_OPCODE;
11680 vex.prefix = REPE_PREFIX_OPCODE;
11683 vex.prefix = REPNE_PREFIX_OPCODE;
11690 dp = &vex_table[dp->op[1].bytemode][vindex];
11692 /* There is no MODRM byte for VEX 77. */
11693 if (vindex != 0x77)
11695 FETCH_DATA (info, codep + 1);
11696 modrm.mod = (*codep >> 6) & 3;
11697 modrm.reg = (*codep >> 3) & 7;
11698 modrm.rm = *codep & 7;
11702 case USE_VEX_W_TABLE:
11706 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11709 case USE_EVEX_TABLE:
11710 two_source_ops = 0;
11713 FETCH_DATA (info, codep + 4);
11714 /* All bits in the REX prefix are ignored. */
11716 /* The first byte after 0x62. */
11717 rex = ~(*codep >> 5) & 0x7;
11718 vex.r = *codep & 0x10;
11719 switch ((*codep & 0xf))
11722 return &bad_opcode;
11724 vex_table_index = EVEX_0F;
11727 vex_table_index = EVEX_0F38;
11730 vex_table_index = EVEX_0F3A;
11734 /* The second byte after 0x62. */
11736 vex.w = *codep & 0x80;
11737 if (vex.w && address_mode == mode_64bit)
11740 vex.register_specifier = (~(*codep >> 3)) & 0xf;
11743 if (!(*codep & 0x4))
11744 return &bad_opcode;
11746 switch ((*codep & 0x3))
11751 vex.prefix = DATA_PREFIX_OPCODE;
11754 vex.prefix = REPE_PREFIX_OPCODE;
11757 vex.prefix = REPNE_PREFIX_OPCODE;
11761 /* The third byte after 0x62. */
11764 /* Remember the static rounding bits. */
11765 vex.ll = (*codep >> 5) & 3;
11766 vex.b = (*codep & 0x10) != 0;
11768 vex.v = *codep & 0x8;
11769 vex.mask_register_specifier = *codep & 0x7;
11770 vex.zeroing = *codep & 0x80;
11772 if (address_mode != mode_64bit)
11774 /* In 16/32-bit mode silently ignore following bits. */
11784 dp = &evex_table[vex_table_index][vindex];
11786 FETCH_DATA (info, codep + 1);
11787 modrm.mod = (*codep >> 6) & 3;
11788 modrm.reg = (*codep >> 3) & 7;
11789 modrm.rm = *codep & 7;
11791 /* Set vector length. */
11792 if (modrm.mod == 3 && vex.b)
11808 return &bad_opcode;
11821 if (dp->name != NULL)
11824 return get_valid_dis386 (dp, info);
11828 get_sib (disassemble_info *info, int sizeflag)
11830 /* If modrm.mod == 3, operand must be register. */
11832 && ((sizeflag & AFLAG) || address_mode == mode_64bit)
11836 FETCH_DATA (info, codep + 2);
11837 sib.index = (codep [1] >> 3) & 7;
11838 sib.scale = (codep [1] >> 6) & 3;
11839 sib.base = codep [1] & 7;
11844 print_insn (bfd_vma pc, disassemble_info *info)
11846 const struct dis386 *dp;
11848 char *op_txt[MAX_OPERANDS];
11850 int sizeflag, orig_sizeflag;
11852 struct dis_private priv;
11855 priv.orig_sizeflag = AFLAG | DFLAG;
11856 if ((info->mach & bfd_mach_i386_i386) != 0)
11857 address_mode = mode_32bit;
11858 else if (info->mach == bfd_mach_i386_i8086)
11860 address_mode = mode_16bit;
11861 priv.orig_sizeflag = 0;
11864 address_mode = mode_64bit;
11866 if (intel_syntax == (char) -1)
11867 intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11869 for (p = info->disassembler_options; p != NULL; )
11871 if (CONST_STRNEQ (p, "amd64"))
11873 else if (CONST_STRNEQ (p, "intel64"))
11875 else if (CONST_STRNEQ (p, "x86-64"))
11877 address_mode = mode_64bit;
11878 priv.orig_sizeflag = AFLAG | DFLAG;
11880 else if (CONST_STRNEQ (p, "i386"))
11882 address_mode = mode_32bit;
11883 priv.orig_sizeflag = AFLAG | DFLAG;
11885 else if (CONST_STRNEQ (p, "i8086"))
11887 address_mode = mode_16bit;
11888 priv.orig_sizeflag = 0;
11890 else if (CONST_STRNEQ (p, "intel"))
11893 if (CONST_STRNEQ (p + 5, "-mnemonic"))
11894 intel_mnemonic = 1;
11896 else if (CONST_STRNEQ (p, "att"))
11899 if (CONST_STRNEQ (p + 3, "-mnemonic"))
11900 intel_mnemonic = 0;
11902 else if (CONST_STRNEQ (p, "addr"))
11904 if (address_mode == mode_64bit)
11906 if (p[4] == '3' && p[5] == '2')
11907 priv.orig_sizeflag &= ~AFLAG;
11908 else if (p[4] == '6' && p[5] == '4')
11909 priv.orig_sizeflag |= AFLAG;
11913 if (p[4] == '1' && p[5] == '6')
11914 priv.orig_sizeflag &= ~AFLAG;
11915 else if (p[4] == '3' && p[5] == '2')
11916 priv.orig_sizeflag |= AFLAG;
11919 else if (CONST_STRNEQ (p, "data"))
11921 if (p[4] == '1' && p[5] == '6')
11922 priv.orig_sizeflag &= ~DFLAG;
11923 else if (p[4] == '3' && p[5] == '2')
11924 priv.orig_sizeflag |= DFLAG;
11926 else if (CONST_STRNEQ (p, "suffix"))
11927 priv.orig_sizeflag |= SUFFIX_ALWAYS;
11929 p = strchr (p, ',');
11934 if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
11936 (*info->fprintf_func) (info->stream,
11937 _("64-bit address is disabled"));
11943 names64 = intel_names64;
11944 names32 = intel_names32;
11945 names16 = intel_names16;
11946 names8 = intel_names8;
11947 names8rex = intel_names8rex;
11948 names_seg = intel_names_seg;
11949 names_mm = intel_names_mm;
11950 names_bnd = intel_names_bnd;
11951 names_xmm = intel_names_xmm;
11952 names_ymm = intel_names_ymm;
11953 names_zmm = intel_names_zmm;
11954 index64 = intel_index64;
11955 index32 = intel_index32;
11956 names_mask = intel_names_mask;
11957 index16 = intel_index16;
11960 separator_char = '+';
11965 names64 = att_names64;
11966 names32 = att_names32;
11967 names16 = att_names16;
11968 names8 = att_names8;
11969 names8rex = att_names8rex;
11970 names_seg = att_names_seg;
11971 names_mm = att_names_mm;
11972 names_bnd = att_names_bnd;
11973 names_xmm = att_names_xmm;
11974 names_ymm = att_names_ymm;
11975 names_zmm = att_names_zmm;
11976 index64 = att_index64;
11977 index32 = att_index32;
11978 names_mask = att_names_mask;
11979 index16 = att_index16;
11982 separator_char = ',';
11986 /* The output looks better if we put 7 bytes on a line, since that
11987 puts most long word instructions on a single line. Use 8 bytes
11989 if ((info->mach & bfd_mach_l1om) != 0)
11990 info->bytes_per_line = 8;
11992 info->bytes_per_line = 7;
11994 info->private_data = &priv;
11995 priv.max_fetched = priv.the_buffer;
11996 priv.insn_start = pc;
11999 for (i = 0; i < MAX_OPERANDS; ++i)
12007 start_codep = priv.the_buffer;
12008 codep = priv.the_buffer;
12010 if (OPCODES_SIGSETJMP (priv.bailout) != 0)
12014 /* Getting here means we tried for data but didn't get it. That
12015 means we have an incomplete instruction of some sort. Just
12016 print the first byte as a prefix or a .byte pseudo-op. */
12017 if (codep > priv.the_buffer)
12019 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
12021 (*info->fprintf_func) (info->stream, "%s", name);
12024 /* Just print the first byte as a .byte instruction. */
12025 (*info->fprintf_func) (info->stream, ".byte 0x%x",
12026 (unsigned int) priv.the_buffer[0]);
12036 sizeflag = priv.orig_sizeflag;
12038 if (!ckprefix () || rex_used)
12040 /* Too many prefixes or unused REX prefixes. */
12042 i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
12044 (*info->fprintf_func) (info->stream, "%s%s",
12046 prefix_name (all_prefixes[i], sizeflag));
12050 insn_codep = codep;
12052 FETCH_DATA (info, codep + 1);
12053 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
12055 if (((prefixes & PREFIX_FWAIT)
12056 && ((*codep < 0xd8) || (*codep > 0xdf))))
12058 /* Handle prefixes before fwait. */
12059 for (i = 0; i < fwait_prefix && all_prefixes[i];
12061 (*info->fprintf_func) (info->stream, "%s ",
12062 prefix_name (all_prefixes[i], sizeflag));
12063 (*info->fprintf_func) (info->stream, "fwait");
12067 if (*codep == 0x0f)
12069 unsigned char threebyte;
12072 FETCH_DATA (info, codep + 1);
12073 threebyte = *codep;
12074 dp = &dis386_twobyte[threebyte];
12075 need_modrm = twobyte_has_modrm[*codep];
12080 dp = &dis386[*codep];
12081 need_modrm = onebyte_has_modrm[*codep];
12085 /* Save sizeflag for printing the extra prefixes later before updating
12086 it for mnemonic and operand processing. The prefix names depend
12087 only on the address mode. */
12088 orig_sizeflag = sizeflag;
12089 if (prefixes & PREFIX_ADDR)
12091 if ((prefixes & PREFIX_DATA))
12097 FETCH_DATA (info, codep + 1);
12098 modrm.mod = (*codep >> 6) & 3;
12099 modrm.reg = (*codep >> 3) & 7;
12100 modrm.rm = *codep & 7;
12106 memset (&vex, 0, sizeof (vex));
12108 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
12110 get_sib (info, sizeflag);
12111 dofloat (sizeflag);
12115 dp = get_valid_dis386 (dp, info);
12116 if (dp != NULL && putop (dp->name, sizeflag) == 0)
12118 get_sib (info, sizeflag);
12119 for (i = 0; i < MAX_OPERANDS; ++i)
12122 op_ad = MAX_OPERANDS - 1 - i;
12124 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
12125 /* For EVEX instruction after the last operand masking
12126 should be printed. */
12127 if (i == 0 && vex.evex)
12129 /* Don't print {%k0}. */
12130 if (vex.mask_register_specifier)
12133 oappend (names_mask[vex.mask_register_specifier]);
12143 /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
12144 are all 0s in inverted form. */
12145 if (need_vex && vex.register_specifier != 0)
12147 (*info->fprintf_func) (info->stream, "(bad)");
12148 return end_codep - priv.the_buffer;
12151 /* Check if the REX prefix is used. */
12152 if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
12153 all_prefixes[last_rex_prefix] = 0;
12155 /* Check if the SEG prefix is used. */
12156 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
12157 | PREFIX_FS | PREFIX_GS)) != 0
12158 && (used_prefixes & active_seg_prefix) != 0)
12159 all_prefixes[last_seg_prefix] = 0;
12161 /* Check if the ADDR prefix is used. */
12162 if ((prefixes & PREFIX_ADDR) != 0
12163 && (used_prefixes & PREFIX_ADDR) != 0)
12164 all_prefixes[last_addr_prefix] = 0;
12166 /* Check if the DATA prefix is used. */
12167 if ((prefixes & PREFIX_DATA) != 0
12168 && (used_prefixes & PREFIX_DATA) != 0)
12169 all_prefixes[last_data_prefix] = 0;
12171 /* Print the extra prefixes. */
12173 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12174 if (all_prefixes[i])
12177 name = prefix_name (all_prefixes[i], orig_sizeflag);
12180 prefix_length += strlen (name) + 1;
12181 (*info->fprintf_func) (info->stream, "%s ", name);
12184 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
12185 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
12186 used by putop and MMX/SSE operand and may be overriden by the
12187 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
12189 if (dp->prefix_requirement == PREFIX_OPCODE
12190 && dp != &bad_opcode
12192 & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
12194 & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
12196 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
12198 && (used_prefixes & PREFIX_DATA) == 0))))
12200 (*info->fprintf_func) (info->stream, "(bad)");
12201 return end_codep - priv.the_buffer;
12204 /* Check maximum code length. */
12205 if ((codep - start_codep) > MAX_CODE_LENGTH)
12207 (*info->fprintf_func) (info->stream, "(bad)");
12208 return MAX_CODE_LENGTH;
12211 obufp = mnemonicendp;
12212 for (i = strlen (obuf) + prefix_length; i < 6; i++)
12215 (*info->fprintf_func) (info->stream, "%s", obuf);
12217 /* The enter and bound instructions are printed with operands in the same
12218 order as the intel book; everything else is printed in reverse order. */
12219 if (intel_syntax || two_source_ops)
12223 for (i = 0; i < MAX_OPERANDS; ++i)
12224 op_txt[i] = op_out[i];
12226 if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
12227 && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
12229 op_txt[2] = op_out[3];
12230 op_txt[3] = op_out[2];
12233 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
12235 op_ad = op_index[i];
12236 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
12237 op_index[MAX_OPERANDS - 1 - i] = op_ad;
12238 riprel = op_riprel[i];
12239 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
12240 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
12245 for (i = 0; i < MAX_OPERANDS; ++i)
12246 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
12250 for (i = 0; i < MAX_OPERANDS; ++i)
12254 (*info->fprintf_func) (info->stream, ",");
12255 if (op_index[i] != -1 && !op_riprel[i])
12256 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
12258 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
12262 for (i = 0; i < MAX_OPERANDS; i++)
12263 if (op_index[i] != -1 && op_riprel[i])
12265 (*info->fprintf_func) (info->stream, " # ");
12266 (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
12267 + op_address[op_index[i]]), info);
12270 return codep - priv.the_buffer;
12273 static const char *float_mem[] = {
12348 static const unsigned char float_mem_mode[] = {
12423 #define ST { OP_ST, 0 }
12424 #define STi { OP_STi, 0 }
12426 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
12427 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
12428 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
12429 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
12430 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
12431 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
12432 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
12433 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
12434 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
12436 static const struct dis386 float_reg[][8] = {
12439 { "fadd", { ST, STi }, 0 },
12440 { "fmul", { ST, STi }, 0 },
12441 { "fcom", { STi }, 0 },
12442 { "fcomp", { STi }, 0 },
12443 { "fsub", { ST, STi }, 0 },
12444 { "fsubr", { ST, STi }, 0 },
12445 { "fdiv", { ST, STi }, 0 },
12446 { "fdivr", { ST, STi }, 0 },
12450 { "fld", { STi }, 0 },
12451 { "fxch", { STi }, 0 },
12461 { "fcmovb", { ST, STi }, 0 },
12462 { "fcmove", { ST, STi }, 0 },
12463 { "fcmovbe",{ ST, STi }, 0 },
12464 { "fcmovu", { ST, STi }, 0 },
12472 { "fcmovnb",{ ST, STi }, 0 },
12473 { "fcmovne",{ ST, STi }, 0 },
12474 { "fcmovnbe",{ ST, STi }, 0 },
12475 { "fcmovnu",{ ST, STi }, 0 },
12477 { "fucomi", { ST, STi }, 0 },
12478 { "fcomi", { ST, STi }, 0 },
12483 { "fadd", { STi, ST }, 0 },
12484 { "fmul", { STi, ST }, 0 },
12487 { "fsub{!M|r}", { STi, ST }, 0 },
12488 { "fsub{M|}", { STi, ST }, 0 },
12489 { "fdiv{!M|r}", { STi, ST }, 0 },
12490 { "fdiv{M|}", { STi, ST }, 0 },
12494 { "ffree", { STi }, 0 },
12496 { "fst", { STi }, 0 },
12497 { "fstp", { STi }, 0 },
12498 { "fucom", { STi }, 0 },
12499 { "fucomp", { STi }, 0 },
12505 { "faddp", { STi, ST }, 0 },
12506 { "fmulp", { STi, ST }, 0 },
12509 { "fsub{!M|r}p", { STi, ST }, 0 },
12510 { "fsub{M|}p", { STi, ST }, 0 },
12511 { "fdiv{!M|r}p", { STi, ST }, 0 },
12512 { "fdiv{M|}p", { STi, ST }, 0 },
12516 { "ffreep", { STi }, 0 },
12521 { "fucomip", { ST, STi }, 0 },
12522 { "fcomip", { ST, STi }, 0 },
12527 static char *fgrps[][8] = {
12530 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12535 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12540 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
12545 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
12550 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
12555 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
12560 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12565 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
12566 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
12571 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12576 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
12581 swap_operand (void)
12583 mnemonicendp[0] = '.';
12584 mnemonicendp[1] = 's';
12589 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
12590 int sizeflag ATTRIBUTE_UNUSED)
12592 /* Skip mod/rm byte. */
12598 dofloat (int sizeflag)
12600 const struct dis386 *dp;
12601 unsigned char floatop;
12603 floatop = codep[-1];
12605 if (modrm.mod != 3)
12607 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
12609 putop (float_mem[fp_indx], sizeflag);
12612 OP_E (float_mem_mode[fp_indx], sizeflag);
12615 /* Skip mod/rm byte. */
12619 dp = &float_reg[floatop - 0xd8][modrm.reg];
12620 if (dp->name == NULL)
12622 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
12624 /* Instruction fnstsw is only one with strange arg. */
12625 if (floatop == 0xdf && codep[-1] == 0xe0)
12626 strcpy (op_out[0], names16[0]);
12630 putop (dp->name, sizeflag);
12635 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
12640 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
12644 /* Like oappend (below), but S is a string starting with '%'.
12645 In Intel syntax, the '%' is elided. */
12647 oappend_maybe_intel (const char *s)
12649 oappend (s + intel_syntax);
12653 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12655 oappend_maybe_intel ("%st");
12659 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12661 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12662 oappend_maybe_intel (scratchbuf);
12665 /* Capital letters in template are macros. */
12667 putop (const char *in_template, int sizeflag)
12672 unsigned int l = 0, len = 1;
12675 #define SAVE_LAST(c) \
12676 if (l < len && l < sizeof (last)) \
12681 for (p = in_template; *p; p++)
12697 while (*++p != '|')
12698 if (*p == '}' || *p == '\0')
12701 /* Fall through. */
12706 while (*++p != '}')
12717 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12721 if (l == 0 && len == 1)
12726 if (sizeflag & SUFFIX_ALWAYS)
12739 if (address_mode == mode_64bit
12740 && !(prefixes & PREFIX_ADDR))
12751 if (intel_syntax && !alt)
12753 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12755 if (sizeflag & DFLAG)
12756 *obufp++ = intel_syntax ? 'd' : 'l';
12758 *obufp++ = intel_syntax ? 'w' : 's';
12759 used_prefixes |= (prefixes & PREFIX_DATA);
12763 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12766 if (modrm.mod == 3)
12772 if (sizeflag & DFLAG)
12773 *obufp++ = intel_syntax ? 'd' : 'l';
12776 used_prefixes |= (prefixes & PREFIX_DATA);
12782 case 'E': /* For jcxz/jecxz */
12783 if (address_mode == mode_64bit)
12785 if (sizeflag & AFLAG)
12791 if (sizeflag & AFLAG)
12793 used_prefixes |= (prefixes & PREFIX_ADDR);
12798 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12800 if (sizeflag & AFLAG)
12801 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12803 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12804 used_prefixes |= (prefixes & PREFIX_ADDR);
12808 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12810 if ((rex & REX_W) || (sizeflag & DFLAG))
12814 if (!(rex & REX_W))
12815 used_prefixes |= (prefixes & PREFIX_DATA);
12820 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12821 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12823 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12826 if (prefixes & PREFIX_DS)
12845 if (l != 0 || len != 1)
12847 if (l != 1 || len != 2 || last[0] != 'X')
12852 if (!need_vex || !vex.evex)
12855 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
12857 switch (vex.length)
12875 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12880 /* Fall through. */
12883 if (l != 0 || len != 1)
12891 if (sizeflag & SUFFIX_ALWAYS)
12895 if (intel_mnemonic != cond)
12899 if ((prefixes & PREFIX_FWAIT) == 0)
12902 used_prefixes |= PREFIX_FWAIT;
12908 else if (intel_syntax && (sizeflag & DFLAG))
12912 if (!(rex & REX_W))
12913 used_prefixes |= (prefixes & PREFIX_DATA);
12917 && address_mode == mode_64bit
12918 && isa64 == intel64)
12923 /* Fall through. */
12926 && address_mode == mode_64bit
12927 && ((sizeflag & DFLAG) || (rex & REX_W)))
12932 /* Fall through. */
12935 if (l == 0 && len == 1)
12940 if ((rex & REX_W) == 0
12941 && (prefixes & PREFIX_DATA))
12943 if ((sizeflag & DFLAG) == 0)
12945 used_prefixes |= (prefixes & PREFIX_DATA);
12949 if ((prefixes & PREFIX_DATA)
12951 || (sizeflag & SUFFIX_ALWAYS))
12958 if (sizeflag & DFLAG)
12962 used_prefixes |= (prefixes & PREFIX_DATA);
12968 if (l != 1 || len != 2 || last[0] != 'L')
12974 if ((prefixes & PREFIX_DATA)
12976 || (sizeflag & SUFFIX_ALWAYS))
12983 if (sizeflag & DFLAG)
12984 *obufp++ = intel_syntax ? 'd' : 'l';
12987 used_prefixes |= (prefixes & PREFIX_DATA);
12995 if (address_mode == mode_64bit
12996 && ((sizeflag & DFLAG) || (rex & REX_W)))
12998 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13002 /* Fall through. */
13005 if (l == 0 && len == 1)
13008 if (intel_syntax && !alt)
13011 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
13017 if (sizeflag & DFLAG)
13018 *obufp++ = intel_syntax ? 'd' : 'l';
13021 used_prefixes |= (prefixes & PREFIX_DATA);
13027 if (l != 1 || len != 2 || last[0] != 'L')
13033 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
13048 else if (sizeflag & DFLAG)
13057 if (intel_syntax && !p[1]
13058 && ((rex & REX_W) || (sizeflag & DFLAG)))
13060 if (!(rex & REX_W))
13061 used_prefixes |= (prefixes & PREFIX_DATA);
13064 if (l == 0 && len == 1)
13068 if (address_mode == mode_64bit
13069 && ((sizeflag & DFLAG) || (rex & REX_W)))
13071 if (sizeflag & SUFFIX_ALWAYS)
13093 /* Fall through. */
13096 if (l == 0 && len == 1)
13101 if (sizeflag & SUFFIX_ALWAYS)
13107 if (sizeflag & DFLAG)
13111 used_prefixes |= (prefixes & PREFIX_DATA);
13125 if (address_mode == mode_64bit
13126 && !(prefixes & PREFIX_ADDR))
13137 if (l != 0 || len != 1)
13142 if (need_vex && vex.prefix)
13144 if (vex.prefix == DATA_PREFIX_OPCODE)
13151 if (prefixes & PREFIX_DATA)
13155 used_prefixes |= (prefixes & PREFIX_DATA);
13159 if (l == 0 && len == 1)
13163 if (l != 1 || len != 2 || last[0] != 'X')
13171 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
13173 switch (vex.length)
13189 if (l == 0 && len == 1)
13191 /* operand size flag for cwtl, cbtw */
13200 else if (sizeflag & DFLAG)
13204 if (!(rex & REX_W))
13205 used_prefixes |= (prefixes & PREFIX_DATA);
13212 && last[0] != 'L'))
13219 if (last[0] == 'X')
13220 *obufp++ = vex.w ? 'd': 's';
13222 *obufp++ = vex.w ? 'q': 'd';
13228 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
13230 if (sizeflag & DFLAG)
13234 used_prefixes |= (prefixes & PREFIX_DATA);
13240 if (address_mode == mode_64bit
13241 && (isa64 == intel64
13242 || ((sizeflag & DFLAG) || (rex & REX_W))))
13244 else if ((prefixes & PREFIX_DATA))
13246 if (!(sizeflag & DFLAG))
13248 used_prefixes |= (prefixes & PREFIX_DATA);
13255 mnemonicendp = obufp;
13260 oappend (const char *s)
13262 obufp = stpcpy (obufp, s);
13268 /* Only print the active segment register. */
13269 if (!active_seg_prefix)
13272 used_prefixes |= active_seg_prefix;
13273 switch (active_seg_prefix)
13276 oappend_maybe_intel ("%cs:");
13279 oappend_maybe_intel ("%ds:");
13282 oappend_maybe_intel ("%ss:");
13285 oappend_maybe_intel ("%es:");
13288 oappend_maybe_intel ("%fs:");
13291 oappend_maybe_intel ("%gs:");
13299 OP_indirE (int bytemode, int sizeflag)
13303 OP_E (bytemode, sizeflag);
13307 print_operand_value (char *buf, int hex, bfd_vma disp)
13309 if (address_mode == mode_64bit)
13317 sprintf_vma (tmp, disp);
13318 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
13319 strcpy (buf + 2, tmp + i);
13323 bfd_signed_vma v = disp;
13330 /* Check for possible overflow on 0x8000000000000000. */
13333 strcpy (buf, "9223372036854775808");
13347 tmp[28 - i] = (v % 10) + '0';
13351 strcpy (buf, tmp + 29 - i);
13357 sprintf (buf, "0x%x", (unsigned int) disp);
13359 sprintf (buf, "%d", (int) disp);
13363 /* Put DISP in BUF as signed hex number. */
13366 print_displacement (char *buf, bfd_vma disp)
13368 bfd_signed_vma val = disp;
13377 /* Check for possible overflow. */
13380 switch (address_mode)
13383 strcpy (buf + j, "0x8000000000000000");
13386 strcpy (buf + j, "0x80000000");
13389 strcpy (buf + j, "0x8000");
13399 sprintf_vma (tmp, (bfd_vma) val);
13400 for (i = 0; tmp[i] == '0'; i++)
13402 if (tmp[i] == '\0')
13404 strcpy (buf + j, tmp + i);
13408 intel_operand_size (int bytemode, int sizeflag)
13412 && (bytemode == x_mode
13413 || bytemode == evex_half_bcst_xmmq_mode))
13416 oappend ("QWORD PTR ");
13418 oappend ("DWORD PTR ");
13427 oappend ("BYTE PTR ");
13432 oappend ("WORD PTR ");
13435 if (address_mode == mode_64bit && isa64 == intel64)
13437 oappend ("QWORD PTR ");
13440 /* Fall through. */
13442 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13444 oappend ("QWORD PTR ");
13447 /* Fall through. */
13453 oappend ("QWORD PTR ");
13456 if ((sizeflag & DFLAG) || bytemode == dq_mode)
13457 oappend ("DWORD PTR ");
13459 oappend ("WORD PTR ");
13460 used_prefixes |= (prefixes & PREFIX_DATA);
13464 if ((rex & REX_W) || (sizeflag & DFLAG))
13466 oappend ("WORD PTR ");
13467 if (!(rex & REX_W))
13468 used_prefixes |= (prefixes & PREFIX_DATA);
13471 if (sizeflag & DFLAG)
13472 oappend ("QWORD PTR ");
13474 oappend ("DWORD PTR ");
13475 used_prefixes |= (prefixes & PREFIX_DATA);
13478 case d_scalar_mode:
13479 case d_scalar_swap_mode:
13482 oappend ("DWORD PTR ");
13485 case q_scalar_mode:
13486 case q_scalar_swap_mode:
13488 oappend ("QWORD PTR ");
13491 if (address_mode == mode_64bit)
13492 oappend ("QWORD PTR ");
13494 oappend ("DWORD PTR ");
13497 if (sizeflag & DFLAG)
13498 oappend ("FWORD PTR ");
13500 oappend ("DWORD PTR ");
13501 used_prefixes |= (prefixes & PREFIX_DATA);
13504 oappend ("TBYTE PTR ");
13508 case evex_x_gscat_mode:
13509 case evex_x_nobcst_mode:
13510 case b_scalar_mode:
13511 case w_scalar_mode:
13514 switch (vex.length)
13517 oappend ("XMMWORD PTR ");
13520 oappend ("YMMWORD PTR ");
13523 oappend ("ZMMWORD PTR ");
13530 oappend ("XMMWORD PTR ");
13533 oappend ("XMMWORD PTR ");
13536 oappend ("YMMWORD PTR ");
13539 case evex_half_bcst_xmmq_mode:
13543 switch (vex.length)
13546 oappend ("QWORD PTR ");
13549 oappend ("XMMWORD PTR ");
13552 oappend ("YMMWORD PTR ");
13562 switch (vex.length)
13567 oappend ("BYTE PTR ");
13577 switch (vex.length)
13582 oappend ("WORD PTR ");
13592 switch (vex.length)
13597 oappend ("DWORD PTR ");
13607 switch (vex.length)
13612 oappend ("QWORD PTR ");
13622 switch (vex.length)
13625 oappend ("WORD PTR ");
13628 oappend ("DWORD PTR ");
13631 oappend ("QWORD PTR ");
13641 switch (vex.length)
13644 oappend ("DWORD PTR ");
13647 oappend ("QWORD PTR ");
13650 oappend ("XMMWORD PTR ");
13660 switch (vex.length)
13663 oappend ("QWORD PTR ");
13666 oappend ("YMMWORD PTR ");
13669 oappend ("ZMMWORD PTR ");
13679 switch (vex.length)
13683 oappend ("XMMWORD PTR ");
13690 oappend ("OWORD PTR ");
13693 case vex_w_dq_mode:
13694 case vex_scalar_w_dq_mode:
13699 oappend ("QWORD PTR ");
13701 oappend ("DWORD PTR ");
13703 case vex_vsib_d_w_dq_mode:
13704 case vex_vsib_q_w_dq_mode:
13711 oappend ("QWORD PTR ");
13713 oappend ("DWORD PTR ");
13717 switch (vex.length)
13720 oappend ("XMMWORD PTR ");
13723 oappend ("YMMWORD PTR ");
13726 oappend ("ZMMWORD PTR ");
13733 case vex_vsib_q_w_d_mode:
13734 case vex_vsib_d_w_d_mode:
13735 if (!need_vex || !vex.evex)
13738 switch (vex.length)
13741 oappend ("QWORD PTR ");
13744 oappend ("XMMWORD PTR ");
13747 oappend ("YMMWORD PTR ");
13755 if (!need_vex || vex.length != 128)
13758 oappend ("DWORD PTR ");
13760 oappend ("BYTE PTR ");
13766 oappend ("QWORD PTR ");
13768 oappend ("WORD PTR ");
13778 OP_E_register (int bytemode, int sizeflag)
13780 int reg = modrm.rm;
13781 const char **names;
13787 if ((sizeflag & SUFFIX_ALWAYS)
13788 && (bytemode == b_swap_mode
13789 || bytemode == bnd_swap_mode
13790 || bytemode == v_swap_mode))
13816 names = address_mode == mode_64bit ? names64 : names32;
13819 case bnd_swap_mode:
13828 if (address_mode == mode_64bit && isa64 == intel64)
13833 /* Fall through. */
13835 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
13841 /* Fall through. */
13853 if ((sizeflag & DFLAG)
13854 || (bytemode != v_mode
13855 && bytemode != v_swap_mode))
13859 used_prefixes |= (prefixes & PREFIX_DATA);
13863 names = (address_mode == mode_64bit
13864 ? names64 : names32);
13865 if (!(prefixes & PREFIX_ADDR))
13866 names = (address_mode == mode_16bit
13867 ? names16 : names);
13870 /* Remove "addr16/addr32". */
13871 all_prefixes[last_addr_prefix] = 0;
13872 names = (address_mode != mode_32bit
13873 ? names32 : names16);
13874 used_prefixes |= PREFIX_ADDR;
13884 names = names_mask;
13889 oappend (INTERNAL_DISASSEMBLER_ERROR);
13892 oappend (names[reg]);
13896 OP_E_memory (int bytemode, int sizeflag)
13899 int add = (rex & REX_B) ? 8 : 0;
13905 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
13907 && bytemode != x_mode
13908 && bytemode != xmmq_mode
13909 && bytemode != evex_half_bcst_xmmq_mode)
13925 if (address_mode != mode_64bit)
13931 case vex_vsib_d_w_dq_mode:
13932 case vex_vsib_d_w_d_mode:
13933 case vex_vsib_q_w_dq_mode:
13934 case vex_vsib_q_w_d_mode:
13935 case evex_x_gscat_mode:
13937 shift = vex.w ? 3 : 2;
13940 case evex_half_bcst_xmmq_mode:
13944 shift = vex.w ? 3 : 2;
13947 /* Fall through. */
13951 case evex_x_nobcst_mode:
13953 switch (vex.length)
13976 case q_scalar_mode:
13978 case q_scalar_swap_mode:
13984 case d_scalar_mode:
13986 case d_scalar_swap_mode:
13989 case w_scalar_mode:
13993 case b_scalar_mode:
14000 /* Make necessary corrections to shift for modes that need it.
14001 For these modes we currently have shift 4, 5 or 6 depending on
14002 vex.length (it corresponds to xmmword, ymmword or zmmword
14003 operand). We might want to make it 3, 4 or 5 (e.g. for
14004 xmmq_mode). In case of broadcast enabled the corrections
14005 aren't needed, as element size is always 32 or 64 bits. */
14007 && (bytemode == xmmq_mode
14008 || bytemode == evex_half_bcst_xmmq_mode))
14010 else if (bytemode == xmmqd_mode)
14012 else if (bytemode == xmmdw_mode)
14014 else if (bytemode == ymmq_mode && vex.length == 128)
14022 intel_operand_size (bytemode, sizeflag);
14025 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14027 /* 32/64 bit address mode */
14037 int addr32flag = !((sizeflag & AFLAG)
14038 || bytemode == v_bnd_mode
14039 || bytemode == v_bndmk_mode
14040 || bytemode == bnd_mode
14041 || bytemode == bnd_swap_mode);
14042 const char **indexes64 = names64;
14043 const char **indexes32 = names32;
14053 vindex = sib.index;
14059 case vex_vsib_d_w_dq_mode:
14060 case vex_vsib_d_w_d_mode:
14061 case vex_vsib_q_w_dq_mode:
14062 case vex_vsib_q_w_d_mode:
14072 switch (vex.length)
14075 indexes64 = indexes32 = names_xmm;
14079 || bytemode == vex_vsib_q_w_dq_mode
14080 || bytemode == vex_vsib_q_w_d_mode)
14081 indexes64 = indexes32 = names_ymm;
14083 indexes64 = indexes32 = names_xmm;
14087 || bytemode == vex_vsib_q_w_dq_mode
14088 || bytemode == vex_vsib_q_w_d_mode)
14089 indexes64 = indexes32 = names_zmm;
14091 indexes64 = indexes32 = names_ymm;
14098 haveindex = vindex != 4;
14105 rbase = base + add;
14113 if (address_mode == mode_64bit && !havesib)
14116 if (riprel && bytemode == v_bndmk_mode)
14124 FETCH_DATA (the_info, codep + 1);
14126 if ((disp & 0x80) != 0)
14128 if (vex.evex && shift > 0)
14141 && address_mode != mode_16bit)
14143 if (address_mode == mode_64bit)
14145 /* Display eiz instead of addr32. */
14146 needindex = addr32flag;
14151 /* In 32-bit mode, we need index register to tell [offset]
14152 from [eiz*1 + offset]. */
14157 havedisp = (havebase
14159 || (havesib && (haveindex || scale != 0)));
14162 if (modrm.mod != 0 || base == 5)
14164 if (havedisp || riprel)
14165 print_displacement (scratchbuf, disp);
14167 print_operand_value (scratchbuf, 1, disp);
14168 oappend (scratchbuf);
14172 oappend (!addr32flag ? "(%rip)" : "(%eip)");
14176 if ((havebase || haveindex || needindex || needaddr32 || riprel)
14177 && (bytemode != v_bnd_mode)
14178 && (bytemode != v_bndmk_mode)
14179 && (bytemode != bnd_mode)
14180 && (bytemode != bnd_swap_mode))
14181 used_prefixes |= PREFIX_ADDR;
14183 if (havedisp || (intel_syntax && riprel))
14185 *obufp++ = open_char;
14186 if (intel_syntax && riprel)
14189 oappend (!addr32flag ? "rip" : "eip");
14193 oappend (address_mode == mode_64bit && !addr32flag
14194 ? names64[rbase] : names32[rbase]);
14197 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
14198 print index to tell base + index from base. */
14202 || (havebase && base != ESP_REG_NUM))
14204 if (!intel_syntax || havebase)
14206 *obufp++ = separator_char;
14210 oappend (address_mode == mode_64bit && !addr32flag
14211 ? indexes64[vindex] : indexes32[vindex]);
14213 oappend (address_mode == mode_64bit && !addr32flag
14214 ? index64 : index32);
14216 *obufp++ = scale_char;
14218 sprintf (scratchbuf, "%d", 1 << scale);
14219 oappend (scratchbuf);
14223 && (disp || modrm.mod != 0 || base == 5))
14225 if (!havedisp || (bfd_signed_vma) disp >= 0)
14230 else if (modrm.mod != 1 && disp != -disp)
14234 disp = - (bfd_signed_vma) disp;
14238 print_displacement (scratchbuf, disp);
14240 print_operand_value (scratchbuf, 1, disp);
14241 oappend (scratchbuf);
14244 *obufp++ = close_char;
14247 else if (intel_syntax)
14249 if (modrm.mod != 0 || base == 5)
14251 if (!active_seg_prefix)
14253 oappend (names_seg[ds_reg - es_reg]);
14256 print_operand_value (scratchbuf, 1, disp);
14257 oappend (scratchbuf);
14263 /* 16 bit address mode */
14264 used_prefixes |= prefixes & PREFIX_ADDR;
14271 if ((disp & 0x8000) != 0)
14276 FETCH_DATA (the_info, codep + 1);
14278 if ((disp & 0x80) != 0)
14280 if (vex.evex && shift > 0)
14285 if ((disp & 0x8000) != 0)
14291 if (modrm.mod != 0 || modrm.rm == 6)
14293 print_displacement (scratchbuf, disp);
14294 oappend (scratchbuf);
14297 if (modrm.mod != 0 || modrm.rm != 6)
14299 *obufp++ = open_char;
14301 oappend (index16[modrm.rm]);
14303 && (disp || modrm.mod != 0 || modrm.rm == 6))
14305 if ((bfd_signed_vma) disp >= 0)
14310 else if (modrm.mod != 1)
14314 disp = - (bfd_signed_vma) disp;
14317 print_displacement (scratchbuf, disp);
14318 oappend (scratchbuf);
14321 *obufp++ = close_char;
14324 else if (intel_syntax)
14326 if (!active_seg_prefix)
14328 oappend (names_seg[ds_reg - es_reg]);
14331 print_operand_value (scratchbuf, 1, disp & 0xffff);
14332 oappend (scratchbuf);
14335 if (vex.evex && vex.b
14336 && (bytemode == x_mode
14337 || bytemode == xmmq_mode
14338 || bytemode == evex_half_bcst_xmmq_mode))
14341 || bytemode == xmmq_mode
14342 || bytemode == evex_half_bcst_xmmq_mode)
14344 switch (vex.length)
14347 oappend ("{1to2}");
14350 oappend ("{1to4}");
14353 oappend ("{1to8}");
14361 switch (vex.length)
14364 oappend ("{1to4}");
14367 oappend ("{1to8}");
14370 oappend ("{1to16}");
14380 OP_E (int bytemode, int sizeflag)
14382 /* Skip mod/rm byte. */
14386 if (modrm.mod == 3)
14387 OP_E_register (bytemode, sizeflag);
14389 OP_E_memory (bytemode, sizeflag);
14393 OP_G (int bytemode, int sizeflag)
14396 const char **names;
14405 oappend (names8rex[modrm.reg + add]);
14407 oappend (names8[modrm.reg + add]);
14410 oappend (names16[modrm.reg + add]);
14415 oappend (names32[modrm.reg + add]);
14418 oappend (names64[modrm.reg + add]);
14421 if (modrm.reg > 0x3)
14426 oappend (names_bnd[modrm.reg]);
14435 oappend (names64[modrm.reg + add]);
14438 if ((sizeflag & DFLAG) || bytemode != v_mode)
14439 oappend (names32[modrm.reg + add]);
14441 oappend (names16[modrm.reg + add]);
14442 used_prefixes |= (prefixes & PREFIX_DATA);
14446 names = (address_mode == mode_64bit
14447 ? names64 : names32);
14448 if (!(prefixes & PREFIX_ADDR))
14450 if (address_mode == mode_16bit)
14455 /* Remove "addr16/addr32". */
14456 all_prefixes[last_addr_prefix] = 0;
14457 names = (address_mode != mode_32bit
14458 ? names32 : names16);
14459 used_prefixes |= PREFIX_ADDR;
14461 oappend (names[modrm.reg + add]);
14464 if (address_mode == mode_64bit)
14465 oappend (names64[modrm.reg + add]);
14467 oappend (names32[modrm.reg + add]);
14471 if ((modrm.reg + add) > 0x7)
14476 oappend (names_mask[modrm.reg + add]);
14479 oappend (INTERNAL_DISASSEMBLER_ERROR);
14492 FETCH_DATA (the_info, codep + 8);
14493 a = *codep++ & 0xff;
14494 a |= (*codep++ & 0xff) << 8;
14495 a |= (*codep++ & 0xff) << 16;
14496 a |= (*codep++ & 0xffu) << 24;
14497 b = *codep++ & 0xff;
14498 b |= (*codep++ & 0xff) << 8;
14499 b |= (*codep++ & 0xff) << 16;
14500 b |= (*codep++ & 0xffu) << 24;
14501 x = a + ((bfd_vma) b << 32);
14509 static bfd_signed_vma
14512 bfd_signed_vma x = 0;
14514 FETCH_DATA (the_info, codep + 4);
14515 x = *codep++ & (bfd_signed_vma) 0xff;
14516 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14517 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14518 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14522 static bfd_signed_vma
14525 bfd_signed_vma x = 0;
14527 FETCH_DATA (the_info, codep + 4);
14528 x = *codep++ & (bfd_signed_vma) 0xff;
14529 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
14530 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
14531 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
14533 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
14543 FETCH_DATA (the_info, codep + 2);
14544 x = *codep++ & 0xff;
14545 x |= (*codep++ & 0xff) << 8;
14550 set_op (bfd_vma op, int riprel)
14552 op_index[op_ad] = op_ad;
14553 if (address_mode == mode_64bit)
14555 op_address[op_ad] = op;
14556 op_riprel[op_ad] = riprel;
14560 /* Mask to get a 32-bit address. */
14561 op_address[op_ad] = op & 0xffffffff;
14562 op_riprel[op_ad] = riprel & 0xffffffff;
14567 OP_REG (int code, int sizeflag)
14574 case es_reg: case ss_reg: case cs_reg:
14575 case ds_reg: case fs_reg: case gs_reg:
14576 oappend (names_seg[code - es_reg]);
14588 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14589 case sp_reg: case bp_reg: case si_reg: case di_reg:
14590 s = names16[code - ax_reg + add];
14592 case al_reg: case ah_reg: case cl_reg: case ch_reg:
14593 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14596 s = names8rex[code - al_reg + add];
14598 s = names8[code - al_reg];
14600 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
14601 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
14602 if (address_mode == mode_64bit
14603 && ((sizeflag & DFLAG) || (rex & REX_W)))
14605 s = names64[code - rAX_reg + add];
14608 code += eAX_reg - rAX_reg;
14609 /* Fall through. */
14610 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14611 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14614 s = names64[code - eAX_reg + add];
14617 if (sizeflag & DFLAG)
14618 s = names32[code - eAX_reg + add];
14620 s = names16[code - eAX_reg + add];
14621 used_prefixes |= (prefixes & PREFIX_DATA);
14625 s = INTERNAL_DISASSEMBLER_ERROR;
14632 OP_IMREG (int code, int sizeflag)
14644 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
14645 case sp_reg: case bp_reg: case si_reg: case di_reg:
14646 s = names16[code - ax_reg];
14648 case es_reg: case ss_reg: case cs_reg:
14649 case ds_reg: case fs_reg: case gs_reg:
14650 s = names_seg[code - es_reg];
14652 case al_reg: case ah_reg: case cl_reg: case ch_reg:
14653 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
14656 s = names8rex[code - al_reg];
14658 s = names8[code - al_reg];
14660 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
14661 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
14664 s = names64[code - eAX_reg];
14667 if (sizeflag & DFLAG)
14668 s = names32[code - eAX_reg];
14670 s = names16[code - eAX_reg];
14671 used_prefixes |= (prefixes & PREFIX_DATA);
14674 case z_mode_ax_reg:
14675 if ((rex & REX_W) || (sizeflag & DFLAG))
14679 if (!(rex & REX_W))
14680 used_prefixes |= (prefixes & PREFIX_DATA);
14683 s = INTERNAL_DISASSEMBLER_ERROR;
14690 OP_I (int bytemode, int sizeflag)
14693 bfd_signed_vma mask = -1;
14698 FETCH_DATA (the_info, codep + 1);
14708 if (sizeflag & DFLAG)
14718 used_prefixes |= (prefixes & PREFIX_DATA);
14734 oappend (INTERNAL_DISASSEMBLER_ERROR);
14739 scratchbuf[0] = '$';
14740 print_operand_value (scratchbuf + 1, 1, op);
14741 oappend_maybe_intel (scratchbuf);
14742 scratchbuf[0] = '\0';
14746 OP_I64 (int bytemode, int sizeflag)
14748 if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
14750 OP_I (bytemode, sizeflag);
14756 scratchbuf[0] = '$';
14757 print_operand_value (scratchbuf + 1, 1, get64 ());
14758 oappend_maybe_intel (scratchbuf);
14759 scratchbuf[0] = '\0';
14763 OP_sI (int bytemode, int sizeflag)
14771 FETCH_DATA (the_info, codep + 1);
14773 if ((op & 0x80) != 0)
14775 if (bytemode == b_T_mode)
14777 if (address_mode != mode_64bit
14778 || !((sizeflag & DFLAG) || (rex & REX_W)))
14780 /* The operand-size prefix is overridden by a REX prefix. */
14781 if ((sizeflag & DFLAG) || (rex & REX_W))
14789 if (!(rex & REX_W))
14791 if (sizeflag & DFLAG)
14799 /* The operand-size prefix is overridden by a REX prefix. */
14800 if ((sizeflag & DFLAG) || (rex & REX_W))
14806 oappend (INTERNAL_DISASSEMBLER_ERROR);
14810 scratchbuf[0] = '$';
14811 print_operand_value (scratchbuf + 1, 1, op);
14812 oappend_maybe_intel (scratchbuf);
14816 OP_J (int bytemode, int sizeflag)
14820 bfd_vma segment = 0;
14825 FETCH_DATA (the_info, codep + 1);
14827 if ((disp & 0x80) != 0)
14831 if (isa64 == amd64)
14833 if ((sizeflag & DFLAG)
14834 || (address_mode == mode_64bit
14835 && (isa64 != amd64 || (rex & REX_W))))
14840 if ((disp & 0x8000) != 0)
14842 /* In 16bit mode, address is wrapped around at 64k within
14843 the same segment. Otherwise, a data16 prefix on a jump
14844 instruction means that the pc is masked to 16 bits after
14845 the displacement is added! */
14847 if ((prefixes & PREFIX_DATA) == 0)
14848 segment = ((start_pc + (codep - start_codep))
14849 & ~((bfd_vma) 0xffff));
14851 if (address_mode != mode_64bit
14852 || (isa64 == amd64 && !(rex & REX_W)))
14853 used_prefixes |= (prefixes & PREFIX_DATA);
14856 oappend (INTERNAL_DISASSEMBLER_ERROR);
14859 disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
14861 print_operand_value (scratchbuf, 1, disp);
14862 oappend (scratchbuf);
14866 OP_SEG (int bytemode, int sizeflag)
14868 if (bytemode == w_mode)
14869 oappend (names_seg[modrm.reg]);
14871 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
14875 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
14879 if (sizeflag & DFLAG)
14889 used_prefixes |= (prefixes & PREFIX_DATA);
14891 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
14893 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
14894 oappend (scratchbuf);
14898 OP_OFF (int bytemode, int sizeflag)
14902 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14903 intel_operand_size (bytemode, sizeflag);
14906 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14913 if (!active_seg_prefix)
14915 oappend (names_seg[ds_reg - es_reg]);
14919 print_operand_value (scratchbuf, 1, off);
14920 oappend (scratchbuf);
14924 OP_OFF64 (int bytemode, int sizeflag)
14928 if (address_mode != mode_64bit
14929 || (prefixes & PREFIX_ADDR))
14931 OP_OFF (bytemode, sizeflag);
14935 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
14936 intel_operand_size (bytemode, sizeflag);
14943 if (!active_seg_prefix)
14945 oappend (names_seg[ds_reg - es_reg]);
14949 print_operand_value (scratchbuf, 1, off);
14950 oappend (scratchbuf);
14954 ptr_reg (int code, int sizeflag)
14958 *obufp++ = open_char;
14959 used_prefixes |= (prefixes & PREFIX_ADDR);
14960 if (address_mode == mode_64bit)
14962 if (!(sizeflag & AFLAG))
14963 s = names32[code - eAX_reg];
14965 s = names64[code - eAX_reg];
14967 else if (sizeflag & AFLAG)
14968 s = names32[code - eAX_reg];
14970 s = names16[code - eAX_reg];
14972 *obufp++ = close_char;
14977 OP_ESreg (int code, int sizeflag)
14983 case 0x6d: /* insw/insl */
14984 intel_operand_size (z_mode, sizeflag);
14986 case 0xa5: /* movsw/movsl/movsq */
14987 case 0xa7: /* cmpsw/cmpsl/cmpsq */
14988 case 0xab: /* stosw/stosl */
14989 case 0xaf: /* scasw/scasl */
14990 intel_operand_size (v_mode, sizeflag);
14993 intel_operand_size (b_mode, sizeflag);
14996 oappend_maybe_intel ("%es:");
14997 ptr_reg (code, sizeflag);
15001 OP_DSreg (int code, int sizeflag)
15007 case 0x6f: /* outsw/outsl */
15008 intel_operand_size (z_mode, sizeflag);
15010 case 0xa5: /* movsw/movsl/movsq */
15011 case 0xa7: /* cmpsw/cmpsl/cmpsq */
15012 case 0xad: /* lodsw/lodsl/lodsq */
15013 intel_operand_size (v_mode, sizeflag);
15016 intel_operand_size (b_mode, sizeflag);
15019 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
15020 default segment register DS is printed. */
15021 if (!active_seg_prefix)
15022 active_seg_prefix = PREFIX_DS;
15024 ptr_reg (code, sizeflag);
15028 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15036 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
15038 all_prefixes[last_lock_prefix] = 0;
15039 used_prefixes |= PREFIX_LOCK;
15044 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
15045 oappend_maybe_intel (scratchbuf);
15049 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15058 sprintf (scratchbuf, "db%d", modrm.reg + add);
15060 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
15061 oappend (scratchbuf);
15065 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15067 sprintf (scratchbuf, "%%tr%d", modrm.reg);
15068 oappend_maybe_intel (scratchbuf);
15072 OP_R (int bytemode, int sizeflag)
15074 /* Skip mod/rm byte. */
15077 OP_E_register (bytemode, sizeflag);
15081 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15083 int reg = modrm.reg;
15084 const char **names;
15086 used_prefixes |= (prefixes & PREFIX_DATA);
15087 if (prefixes & PREFIX_DATA)
15096 oappend (names[reg]);
15100 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15102 int reg = modrm.reg;
15103 const char **names;
15115 && bytemode != xmm_mode
15116 && bytemode != xmmq_mode
15117 && bytemode != evex_half_bcst_xmmq_mode
15118 && bytemode != ymm_mode
15119 && bytemode != scalar_mode)
15121 switch (vex.length)
15128 || (bytemode != vex_vsib_q_w_dq_mode
15129 && bytemode != vex_vsib_q_w_d_mode))
15141 else if (bytemode == xmmq_mode
15142 || bytemode == evex_half_bcst_xmmq_mode)
15144 switch (vex.length)
15157 else if (bytemode == ymm_mode)
15161 oappend (names[reg]);
15165 OP_EM (int bytemode, int sizeflag)
15168 const char **names;
15170 if (modrm.mod != 3)
15173 && (bytemode == v_mode || bytemode == v_swap_mode))
15175 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15176 used_prefixes |= (prefixes & PREFIX_DATA);
15178 OP_E (bytemode, sizeflag);
15182 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
15185 /* Skip mod/rm byte. */
15188 used_prefixes |= (prefixes & PREFIX_DATA);
15190 if (prefixes & PREFIX_DATA)
15199 oappend (names[reg]);
15202 /* cvt* are the only instructions in sse2 which have
15203 both SSE and MMX operands and also have 0x66 prefix
15204 in their opcode. 0x66 was originally used to differentiate
15205 between SSE and MMX instruction(operands). So we have to handle the
15206 cvt* separately using OP_EMC and OP_MXC */
15208 OP_EMC (int bytemode, int sizeflag)
15210 if (modrm.mod != 3)
15212 if (intel_syntax && bytemode == v_mode)
15214 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
15215 used_prefixes |= (prefixes & PREFIX_DATA);
15217 OP_E (bytemode, sizeflag);
15221 /* Skip mod/rm byte. */
15224 used_prefixes |= (prefixes & PREFIX_DATA);
15225 oappend (names_mm[modrm.rm]);
15229 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15231 used_prefixes |= (prefixes & PREFIX_DATA);
15232 oappend (names_mm[modrm.reg]);
15236 OP_EX (int bytemode, int sizeflag)
15239 const char **names;
15241 /* Skip mod/rm byte. */
15245 if (modrm.mod != 3)
15247 OP_E_memory (bytemode, sizeflag);
15262 if ((sizeflag & SUFFIX_ALWAYS)
15263 && (bytemode == x_swap_mode
15264 || bytemode == d_swap_mode
15265 || bytemode == d_scalar_swap_mode
15266 || bytemode == q_swap_mode
15267 || bytemode == q_scalar_swap_mode))
15271 && bytemode != xmm_mode
15272 && bytemode != xmmdw_mode
15273 && bytemode != xmmqd_mode
15274 && bytemode != xmm_mb_mode
15275 && bytemode != xmm_mw_mode
15276 && bytemode != xmm_md_mode
15277 && bytemode != xmm_mq_mode
15278 && bytemode != xmm_mdq_mode
15279 && bytemode != xmmq_mode
15280 && bytemode != evex_half_bcst_xmmq_mode
15281 && bytemode != ymm_mode
15282 && bytemode != d_scalar_mode
15283 && bytemode != d_scalar_swap_mode
15284 && bytemode != q_scalar_mode
15285 && bytemode != q_scalar_swap_mode
15286 && bytemode != vex_scalar_w_dq_mode)
15288 switch (vex.length)
15303 else if (bytemode == xmmq_mode
15304 || bytemode == evex_half_bcst_xmmq_mode)
15306 switch (vex.length)
15319 else if (bytemode == ymm_mode)
15323 oappend (names[reg]);
15327 OP_MS (int bytemode, int sizeflag)
15329 if (modrm.mod == 3)
15330 OP_EM (bytemode, sizeflag);
15336 OP_XS (int bytemode, int sizeflag)
15338 if (modrm.mod == 3)
15339 OP_EX (bytemode, sizeflag);
15345 OP_M (int bytemode, int sizeflag)
15347 if (modrm.mod == 3)
15348 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
15351 OP_E (bytemode, sizeflag);
15355 OP_0f07 (int bytemode, int sizeflag)
15357 if (modrm.mod != 3 || modrm.rm != 0)
15360 OP_E (bytemode, sizeflag);
15363 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
15364 32bit mode and "xchg %rax,%rax" in 64bit mode. */
15367 NOP_Fixup1 (int bytemode, int sizeflag)
15369 if ((prefixes & PREFIX_DATA) != 0
15372 && address_mode == mode_64bit))
15373 OP_REG (bytemode, sizeflag);
15375 strcpy (obuf, "nop");
15379 NOP_Fixup2 (int bytemode, int sizeflag)
15381 if ((prefixes & PREFIX_DATA) != 0
15384 && address_mode == mode_64bit))
15385 OP_IMREG (bytemode, sizeflag);
15388 static const char *const Suffix3DNow[] = {
15389 /* 00 */ NULL, NULL, NULL, NULL,
15390 /* 04 */ NULL, NULL, NULL, NULL,
15391 /* 08 */ NULL, NULL, NULL, NULL,
15392 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
15393 /* 10 */ NULL, NULL, NULL, NULL,
15394 /* 14 */ NULL, NULL, NULL, NULL,
15395 /* 18 */ NULL, NULL, NULL, NULL,
15396 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
15397 /* 20 */ NULL, NULL, NULL, NULL,
15398 /* 24 */ NULL, NULL, NULL, NULL,
15399 /* 28 */ NULL, NULL, NULL, NULL,
15400 /* 2C */ NULL, NULL, NULL, NULL,
15401 /* 30 */ NULL, NULL, NULL, NULL,
15402 /* 34 */ NULL, NULL, NULL, NULL,
15403 /* 38 */ NULL, NULL, NULL, NULL,
15404 /* 3C */ NULL, NULL, NULL, NULL,
15405 /* 40 */ NULL, NULL, NULL, NULL,
15406 /* 44 */ NULL, NULL, NULL, NULL,
15407 /* 48 */ NULL, NULL, NULL, NULL,
15408 /* 4C */ NULL, NULL, NULL, NULL,
15409 /* 50 */ NULL, NULL, NULL, NULL,
15410 /* 54 */ NULL, NULL, NULL, NULL,
15411 /* 58 */ NULL, NULL, NULL, NULL,
15412 /* 5C */ NULL, NULL, NULL, NULL,
15413 /* 60 */ NULL, NULL, NULL, NULL,
15414 /* 64 */ NULL, NULL, NULL, NULL,
15415 /* 68 */ NULL, NULL, NULL, NULL,
15416 /* 6C */ NULL, NULL, NULL, NULL,
15417 /* 70 */ NULL, NULL, NULL, NULL,
15418 /* 74 */ NULL, NULL, NULL, NULL,
15419 /* 78 */ NULL, NULL, NULL, NULL,
15420 /* 7C */ NULL, NULL, NULL, NULL,
15421 /* 80 */ NULL, NULL, NULL, NULL,
15422 /* 84 */ NULL, NULL, NULL, NULL,
15423 /* 88 */ NULL, NULL, "pfnacc", NULL,
15424 /* 8C */ NULL, NULL, "pfpnacc", NULL,
15425 /* 90 */ "pfcmpge", NULL, NULL, NULL,
15426 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
15427 /* 98 */ NULL, NULL, "pfsub", NULL,
15428 /* 9C */ NULL, NULL, "pfadd", NULL,
15429 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
15430 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
15431 /* A8 */ NULL, NULL, "pfsubr", NULL,
15432 /* AC */ NULL, NULL, "pfacc", NULL,
15433 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
15434 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
15435 /* B8 */ NULL, NULL, NULL, "pswapd",
15436 /* BC */ NULL, NULL, NULL, "pavgusb",
15437 /* C0 */ NULL, NULL, NULL, NULL,
15438 /* C4 */ NULL, NULL, NULL, NULL,
15439 /* C8 */ NULL, NULL, NULL, NULL,
15440 /* CC */ NULL, NULL, NULL, NULL,
15441 /* D0 */ NULL, NULL, NULL, NULL,
15442 /* D4 */ NULL, NULL, NULL, NULL,
15443 /* D8 */ NULL, NULL, NULL, NULL,
15444 /* DC */ NULL, NULL, NULL, NULL,
15445 /* E0 */ NULL, NULL, NULL, NULL,
15446 /* E4 */ NULL, NULL, NULL, NULL,
15447 /* E8 */ NULL, NULL, NULL, NULL,
15448 /* EC */ NULL, NULL, NULL, NULL,
15449 /* F0 */ NULL, NULL, NULL, NULL,
15450 /* F4 */ NULL, NULL, NULL, NULL,
15451 /* F8 */ NULL, NULL, NULL, NULL,
15452 /* FC */ NULL, NULL, NULL, NULL,
15456 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15458 const char *mnemonic;
15460 FETCH_DATA (the_info, codep + 1);
15461 /* AMD 3DNow! instructions are specified by an opcode suffix in the
15462 place where an 8-bit immediate would normally go. ie. the last
15463 byte of the instruction. */
15464 obufp = mnemonicendp;
15465 mnemonic = Suffix3DNow[*codep++ & 0xff];
15467 oappend (mnemonic);
15470 /* Since a variable sized modrm/sib chunk is between the start
15471 of the opcode (0x0f0f) and the opcode suffix, we need to do
15472 all the modrm processing first, and don't know until now that
15473 we have a bad opcode. This necessitates some cleaning up. */
15474 op_out[0][0] = '\0';
15475 op_out[1][0] = '\0';
15478 mnemonicendp = obufp;
15481 static struct op simd_cmp_op[] =
15483 { STRING_COMMA_LEN ("eq") },
15484 { STRING_COMMA_LEN ("lt") },
15485 { STRING_COMMA_LEN ("le") },
15486 { STRING_COMMA_LEN ("unord") },
15487 { STRING_COMMA_LEN ("neq") },
15488 { STRING_COMMA_LEN ("nlt") },
15489 { STRING_COMMA_LEN ("nle") },
15490 { STRING_COMMA_LEN ("ord") }
15494 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15496 unsigned int cmp_type;
15498 FETCH_DATA (the_info, codep + 1);
15499 cmp_type = *codep++ & 0xff;
15500 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
15503 char *p = mnemonicendp - 2;
15507 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
15508 mnemonicendp += simd_cmp_op[cmp_type].len;
15512 /* We have a reserved extension byte. Output it directly. */
15513 scratchbuf[0] = '$';
15514 print_operand_value (scratchbuf + 1, 1, cmp_type);
15515 oappend_maybe_intel (scratchbuf);
15516 scratchbuf[0] = '\0';
15521 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
15522 int sizeflag ATTRIBUTE_UNUSED)
15524 /* mwaitx %eax,%ecx,%ebx */
15527 const char **names = (address_mode == mode_64bit
15528 ? names64 : names32);
15529 strcpy (op_out[0], names[0]);
15530 strcpy (op_out[1], names[1]);
15531 strcpy (op_out[2], names[3]);
15532 two_source_ops = 1;
15534 /* Skip mod/rm byte. */
15540 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
15541 int sizeflag ATTRIBUTE_UNUSED)
15543 /* mwait %eax,%ecx */
15546 const char **names = (address_mode == mode_64bit
15547 ? names64 : names32);
15548 strcpy (op_out[0], names[0]);
15549 strcpy (op_out[1], names[1]);
15550 two_source_ops = 1;
15552 /* Skip mod/rm byte. */
15558 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
15559 int sizeflag ATTRIBUTE_UNUSED)
15561 /* monitor %eax,%ecx,%edx" */
15564 const char **op1_names;
15565 const char **names = (address_mode == mode_64bit
15566 ? names64 : names32);
15568 if (!(prefixes & PREFIX_ADDR))
15569 op1_names = (address_mode == mode_16bit
15570 ? names16 : names);
15573 /* Remove "addr16/addr32". */
15574 all_prefixes[last_addr_prefix] = 0;
15575 op1_names = (address_mode != mode_32bit
15576 ? names32 : names16);
15577 used_prefixes |= PREFIX_ADDR;
15579 strcpy (op_out[0], op1_names[0]);
15580 strcpy (op_out[1], names[1]);
15581 strcpy (op_out[2], names[2]);
15582 two_source_ops = 1;
15584 /* Skip mod/rm byte. */
15592 /* Throw away prefixes and 1st. opcode byte. */
15593 codep = insn_codep + 1;
15598 REP_Fixup (int bytemode, int sizeflag)
15600 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
15602 if (prefixes & PREFIX_REPZ)
15603 all_prefixes[last_repz_prefix] = REP_PREFIX;
15610 OP_IMREG (bytemode, sizeflag);
15613 OP_ESreg (bytemode, sizeflag);
15616 OP_DSreg (bytemode, sizeflag);
15624 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
15628 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15630 if (prefixes & PREFIX_REPNZ)
15631 all_prefixes[last_repnz_prefix] = BND_PREFIX;
15634 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
15638 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
15639 int sizeflag ATTRIBUTE_UNUSED)
15641 if (active_seg_prefix == PREFIX_DS
15642 && (address_mode != mode_64bit || last_data_prefix < 0))
15644 /* NOTRACK prefix is only valid on indirect branch instructions.
15645 NB: DATA prefix is unsupported for Intel64. */
15646 active_seg_prefix = 0;
15647 all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
15651 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15652 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
15656 HLE_Fixup1 (int bytemode, int sizeflag)
15659 && (prefixes & PREFIX_LOCK) != 0)
15661 if (prefixes & PREFIX_REPZ)
15662 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15663 if (prefixes & PREFIX_REPNZ)
15664 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15667 OP_E (bytemode, sizeflag);
15670 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
15671 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
15675 HLE_Fixup2 (int bytemode, int sizeflag)
15677 if (modrm.mod != 3)
15679 if (prefixes & PREFIX_REPZ)
15680 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15681 if (prefixes & PREFIX_REPNZ)
15682 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15685 OP_E (bytemode, sizeflag);
15688 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
15689 "xrelease" for memory operand. No check for LOCK prefix. */
15692 HLE_Fixup3 (int bytemode, int sizeflag)
15695 && last_repz_prefix > last_repnz_prefix
15696 && (prefixes & PREFIX_REPZ) != 0)
15697 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15699 OP_E (bytemode, sizeflag);
15703 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
15708 /* Change cmpxchg8b to cmpxchg16b. */
15709 char *p = mnemonicendp - 2;
15710 mnemonicendp = stpcpy (p, "16b");
15713 else if ((prefixes & PREFIX_LOCK) != 0)
15715 if (prefixes & PREFIX_REPZ)
15716 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
15717 if (prefixes & PREFIX_REPNZ)
15718 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
15721 OP_M (bytemode, sizeflag);
15725 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
15727 const char **names;
15731 switch (vex.length)
15745 oappend (names[reg]);
15749 CRC32_Fixup (int bytemode, int sizeflag)
15751 /* Add proper suffix to "crc32". */
15752 char *p = mnemonicendp;
15771 if (sizeflag & DFLAG)
15775 used_prefixes |= (prefixes & PREFIX_DATA);
15779 oappend (INTERNAL_DISASSEMBLER_ERROR);
15786 if (modrm.mod == 3)
15790 /* Skip mod/rm byte. */
15795 add = (rex & REX_B) ? 8 : 0;
15796 if (bytemode == b_mode)
15800 oappend (names8rex[modrm.rm + add]);
15802 oappend (names8[modrm.rm + add]);
15808 oappend (names64[modrm.rm + add]);
15809 else if ((prefixes & PREFIX_DATA))
15810 oappend (names16[modrm.rm + add]);
15812 oappend (names32[modrm.rm + add]);
15816 OP_E (bytemode, sizeflag);
15820 FXSAVE_Fixup (int bytemode, int sizeflag)
15822 /* Add proper suffix to "fxsave" and "fxrstor". */
15826 char *p = mnemonicendp;
15832 OP_M (bytemode, sizeflag);
15836 PCMPESTR_Fixup (int bytemode, int sizeflag)
15838 /* Add proper suffix to "{,v}pcmpestr{i,m}". */
15841 char *p = mnemonicendp;
15846 else if (sizeflag & SUFFIX_ALWAYS)
15853 OP_EX (bytemode, sizeflag);
15856 /* Display the destination register operand for instructions with
15860 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
15863 const char **names;
15871 reg = vex.register_specifier;
15872 vex.register_specifier = 0;
15873 if (address_mode != mode_64bit)
15875 else if (vex.evex && !vex.v)
15878 if (bytemode == vex_scalar_mode)
15880 oappend (names_xmm[reg]);
15884 switch (vex.length)
15891 case vex_vsib_q_w_dq_mode:
15892 case vex_vsib_q_w_d_mode:
15908 names = names_mask;
15922 case vex_vsib_q_w_dq_mode:
15923 case vex_vsib_q_w_d_mode:
15924 names = vex.w ? names_ymm : names_xmm;
15933 names = names_mask;
15936 /* See PR binutils/20893 for a reproducer. */
15948 oappend (names[reg]);
15951 /* Get the VEX immediate byte without moving codep. */
15953 static unsigned char
15954 get_vex_imm8 (int sizeflag, int opnum)
15956 int bytes_before_imm = 0;
15958 if (modrm.mod != 3)
15960 /* There are SIB/displacement bytes. */
15961 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15963 /* 32/64 bit address mode */
15964 int base = modrm.rm;
15966 /* Check SIB byte. */
15969 FETCH_DATA (the_info, codep + 1);
15971 /* When decoding the third source, don't increase
15972 bytes_before_imm as this has already been incremented
15973 by one in OP_E_memory while decoding the second
15976 bytes_before_imm++;
15979 /* Don't increase bytes_before_imm when decoding the third source,
15980 it has already been incremented by OP_E_memory while decoding
15981 the second source operand. */
15987 /* When modrm.rm == 5 or modrm.rm == 4 and base in
15988 SIB == 5, there is a 4 byte displacement. */
15990 /* No displacement. */
15992 /* Fall through. */
15994 /* 4 byte displacement. */
15995 bytes_before_imm += 4;
15998 /* 1 byte displacement. */
15999 bytes_before_imm++;
16006 /* 16 bit address mode */
16007 /* Don't increase bytes_before_imm when decoding the third source,
16008 it has already been incremented by OP_E_memory while decoding
16009 the second source operand. */
16015 /* When modrm.rm == 6, there is a 2 byte displacement. */
16017 /* No displacement. */
16019 /* Fall through. */
16021 /* 2 byte displacement. */
16022 bytes_before_imm += 2;
16025 /* 1 byte displacement: when decoding the third source,
16026 don't increase bytes_before_imm as this has already
16027 been incremented by one in OP_E_memory while decoding
16028 the second source operand. */
16030 bytes_before_imm++;
16038 FETCH_DATA (the_info, codep + bytes_before_imm + 1);
16039 return codep [bytes_before_imm];
16043 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
16045 const char **names;
16047 if (reg == -1 && modrm.mod != 3)
16049 OP_E_memory (bytemode, sizeflag);
16061 if (address_mode != mode_64bit)
16065 switch (vex.length)
16076 oappend (names[reg]);
16080 OP_EX_VexImmW (int bytemode, int sizeflag)
16083 static unsigned char vex_imm8;
16085 if (vex_w_done == 0)
16089 /* Skip mod/rm byte. */
16093 vex_imm8 = get_vex_imm8 (sizeflag, 0);
16096 reg = vex_imm8 >> 4;
16098 OP_EX_VexReg (bytemode, sizeflag, reg);
16100 else if (vex_w_done == 1)
16105 reg = vex_imm8 >> 4;
16107 OP_EX_VexReg (bytemode, sizeflag, reg);
16111 /* Output the imm8 directly. */
16112 scratchbuf[0] = '$';
16113 print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
16114 oappend_maybe_intel (scratchbuf);
16115 scratchbuf[0] = '\0';
16121 OP_Vex_2src (int bytemode, int sizeflag)
16123 if (modrm.mod == 3)
16125 int reg = modrm.rm;
16129 oappend (names_xmm[reg]);
16134 && (bytemode == v_mode || bytemode == v_swap_mode))
16136 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16137 used_prefixes |= (prefixes & PREFIX_DATA);
16139 OP_E (bytemode, sizeflag);
16144 OP_Vex_2src_1 (int bytemode, int sizeflag)
16146 if (modrm.mod == 3)
16148 /* Skip mod/rm byte. */
16155 unsigned int reg = vex.register_specifier;
16156 vex.register_specifier = 0;
16158 if (address_mode != mode_64bit)
16160 oappend (names_xmm[reg]);
16163 OP_Vex_2src (bytemode, sizeflag);
16167 OP_Vex_2src_2 (int bytemode, int sizeflag)
16170 OP_Vex_2src (bytemode, sizeflag);
16173 unsigned int reg = vex.register_specifier;
16174 vex.register_specifier = 0;
16176 if (address_mode != mode_64bit)
16178 oappend (names_xmm[reg]);
16183 OP_EX_VexW (int bytemode, int sizeflag)
16189 /* Skip mod/rm byte. */
16194 reg = get_vex_imm8 (sizeflag, 0) >> 4;
16199 reg = get_vex_imm8 (sizeflag, 1) >> 4;
16202 OP_EX_VexReg (bytemode, sizeflag, reg);
16210 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16213 const char **names;
16215 FETCH_DATA (the_info, codep + 1);
16218 if (bytemode != x_mode)
16222 if (address_mode != mode_64bit)
16225 switch (vex.length)
16236 oappend (names[reg]);
16240 OP_XMM_VexW (int bytemode, int sizeflag)
16242 /* Turn off the REX.W bit since it is used for swapping operands
16245 OP_XMM (bytemode, sizeflag);
16249 OP_EX_Vex (int bytemode, int sizeflag)
16251 if (modrm.mod != 3)
16253 OP_EX (bytemode, sizeflag);
16257 OP_XMM_Vex (int bytemode, int sizeflag)
16259 if (modrm.mod != 3)
16261 OP_XMM (bytemode, sizeflag);
16264 static struct op vex_cmp_op[] =
16266 { STRING_COMMA_LEN ("eq") },
16267 { STRING_COMMA_LEN ("lt") },
16268 { STRING_COMMA_LEN ("le") },
16269 { STRING_COMMA_LEN ("unord") },
16270 { STRING_COMMA_LEN ("neq") },
16271 { STRING_COMMA_LEN ("nlt") },
16272 { STRING_COMMA_LEN ("nle") },
16273 { STRING_COMMA_LEN ("ord") },
16274 { STRING_COMMA_LEN ("eq_uq") },
16275 { STRING_COMMA_LEN ("nge") },
16276 { STRING_COMMA_LEN ("ngt") },
16277 { STRING_COMMA_LEN ("false") },
16278 { STRING_COMMA_LEN ("neq_oq") },
16279 { STRING_COMMA_LEN ("ge") },
16280 { STRING_COMMA_LEN ("gt") },
16281 { STRING_COMMA_LEN ("true") },
16282 { STRING_COMMA_LEN ("eq_os") },
16283 { STRING_COMMA_LEN ("lt_oq") },
16284 { STRING_COMMA_LEN ("le_oq") },
16285 { STRING_COMMA_LEN ("unord_s") },
16286 { STRING_COMMA_LEN ("neq_us") },
16287 { STRING_COMMA_LEN ("nlt_uq") },
16288 { STRING_COMMA_LEN ("nle_uq") },
16289 { STRING_COMMA_LEN ("ord_s") },
16290 { STRING_COMMA_LEN ("eq_us") },
16291 { STRING_COMMA_LEN ("nge_uq") },
16292 { STRING_COMMA_LEN ("ngt_uq") },
16293 { STRING_COMMA_LEN ("false_os") },
16294 { STRING_COMMA_LEN ("neq_os") },
16295 { STRING_COMMA_LEN ("ge_oq") },
16296 { STRING_COMMA_LEN ("gt_oq") },
16297 { STRING_COMMA_LEN ("true_us") },
16301 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16303 unsigned int cmp_type;
16305 FETCH_DATA (the_info, codep + 1);
16306 cmp_type = *codep++ & 0xff;
16307 if (cmp_type < ARRAY_SIZE (vex_cmp_op))
16310 char *p = mnemonicendp - 2;
16314 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
16315 mnemonicendp += vex_cmp_op[cmp_type].len;
16319 /* We have a reserved extension byte. Output it directly. */
16320 scratchbuf[0] = '$';
16321 print_operand_value (scratchbuf + 1, 1, cmp_type);
16322 oappend_maybe_intel (scratchbuf);
16323 scratchbuf[0] = '\0';
16328 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
16329 int sizeflag ATTRIBUTE_UNUSED)
16331 unsigned int cmp_type;
16336 FETCH_DATA (the_info, codep + 1);
16337 cmp_type = *codep++ & 0xff;
16338 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
16339 If it's the case, print suffix, otherwise - print the immediate. */
16340 if (cmp_type < ARRAY_SIZE (simd_cmp_op)
16345 char *p = mnemonicendp - 2;
16347 /* vpcmp* can have both one- and two-lettered suffix. */
16361 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16362 mnemonicendp += simd_cmp_op[cmp_type].len;
16366 /* We have a reserved extension byte. Output it directly. */
16367 scratchbuf[0] = '$';
16368 print_operand_value (scratchbuf + 1, 1, cmp_type);
16369 oappend_maybe_intel (scratchbuf);
16370 scratchbuf[0] = '\0';
16374 static const struct op xop_cmp_op[] =
16376 { STRING_COMMA_LEN ("lt") },
16377 { STRING_COMMA_LEN ("le") },
16378 { STRING_COMMA_LEN ("gt") },
16379 { STRING_COMMA_LEN ("ge") },
16380 { STRING_COMMA_LEN ("eq") },
16381 { STRING_COMMA_LEN ("neq") },
16382 { STRING_COMMA_LEN ("false") },
16383 { STRING_COMMA_LEN ("true") }
16387 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
16388 int sizeflag ATTRIBUTE_UNUSED)
16390 unsigned int cmp_type;
16392 FETCH_DATA (the_info, codep + 1);
16393 cmp_type = *codep++ & 0xff;
16394 if (cmp_type < ARRAY_SIZE (xop_cmp_op))
16397 char *p = mnemonicendp - 2;
16399 /* vpcom* can have both one- and two-lettered suffix. */
16413 sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
16414 mnemonicendp += xop_cmp_op[cmp_type].len;
16418 /* We have a reserved extension byte. Output it directly. */
16419 scratchbuf[0] = '$';
16420 print_operand_value (scratchbuf + 1, 1, cmp_type);
16421 oappend_maybe_intel (scratchbuf);
16422 scratchbuf[0] = '\0';
16426 static const struct op pclmul_op[] =
16428 { STRING_COMMA_LEN ("lql") },
16429 { STRING_COMMA_LEN ("hql") },
16430 { STRING_COMMA_LEN ("lqh") },
16431 { STRING_COMMA_LEN ("hqh") }
16435 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
16436 int sizeflag ATTRIBUTE_UNUSED)
16438 unsigned int pclmul_type;
16440 FETCH_DATA (the_info, codep + 1);
16441 pclmul_type = *codep++ & 0xff;
16442 switch (pclmul_type)
16453 if (pclmul_type < ARRAY_SIZE (pclmul_op))
16456 char *p = mnemonicendp - 3;
16461 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
16462 mnemonicendp += pclmul_op[pclmul_type].len;
16466 /* We have a reserved extension byte. Output it directly. */
16467 scratchbuf[0] = '$';
16468 print_operand_value (scratchbuf + 1, 1, pclmul_type);
16469 oappend_maybe_intel (scratchbuf);
16470 scratchbuf[0] = '\0';
16475 MOVBE_Fixup (int bytemode, int sizeflag)
16477 /* Add proper suffix to "movbe". */
16478 char *p = mnemonicendp;
16487 if (sizeflag & SUFFIX_ALWAYS)
16493 if (sizeflag & DFLAG)
16497 used_prefixes |= (prefixes & PREFIX_DATA);
16502 oappend (INTERNAL_DISASSEMBLER_ERROR);
16509 OP_M (bytemode, sizeflag);
16513 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16516 const char **names;
16518 /* Skip mod/rm byte. */
16532 oappend (names[reg]);
16536 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16538 const char **names;
16539 unsigned int reg = vex.register_specifier;
16540 vex.register_specifier = 0;
16547 if (address_mode != mode_64bit)
16549 oappend (names[reg]);
16553 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16556 || (bytemode != mask_mode && bytemode != mask_bd_mode))
16560 if ((rex & REX_R) != 0 || !vex.r)
16566 oappend (names_mask [modrm.reg]);
16570 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16573 || (bytemode != evex_rounding_mode
16574 && bytemode != evex_rounding_64_mode
16575 && bytemode != evex_sae_mode))
16577 if (modrm.mod == 3 && vex.b)
16580 case evex_rounding_64_mode:
16581 if (address_mode != mode_64bit)
16586 /* Fall through. */
16587 case evex_rounding_mode:
16588 oappend (names_rounding[vex.ll]);
16590 case evex_sae_mode: