1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
6 This file is part of the GNU opcodes library.
8 This library is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
24 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
26 modified by John Hassey (hassey@dg-rtp.dg.com)
27 x86-64 support added by Jan Hubicka (jh@suse.cz)
28 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
30 /* The main tables describing the instructions is essentially a copy
31 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
32 Programmers Manual. Usually, there is a capital letter, followed
33 by a small letter. The capital letter tell the addressing mode,
34 and the small letter tells about the operand size. Refer to
35 the Intel manual for details. */
40 #include "opcode/i386.h"
41 #include "libiberty.h"
45 static int print_insn (bfd_vma, disassemble_info *);
46 static void dofloat (int);
47 static void OP_ST (int, int);
48 static void OP_STi (int, int);
49 static int putop (const char *, int);
50 static void oappend (const char *);
51 static void append_seg (void);
52 static void OP_indirE (int, int);
53 static void print_operand_value (char *, int, bfd_vma);
54 static void OP_E_register (int, int);
55 static void OP_E_memory (int, int);
56 static void print_displacement (char *, bfd_vma);
57 static void OP_E (int, int);
58 static void OP_G (int, int);
59 static bfd_vma get64 (void);
60 static bfd_signed_vma get32 (void);
61 static bfd_signed_vma get32s (void);
62 static int get16 (void);
63 static void set_op (bfd_vma, int);
64 static void OP_Skip_MODRM (int, int);
65 static void OP_REG (int, int);
66 static void OP_IMREG (int, int);
67 static void OP_I (int, int);
68 static void OP_I64 (int, int);
69 static void OP_sI (int, int);
70 static void OP_J (int, int);
71 static void OP_SEG (int, int);
72 static void OP_DIR (int, int);
73 static void OP_OFF (int, int);
74 static void OP_OFF64 (int, int);
75 static void ptr_reg (int, int);
76 static void OP_ESreg (int, int);
77 static void OP_DSreg (int, int);
78 static void OP_C (int, int);
79 static void OP_D (int, int);
80 static void OP_T (int, int);
81 static void OP_R (int, int);
82 static void OP_MMX (int, int);
83 static void OP_XMM (int, int);
84 static void OP_EM (int, int);
85 static void OP_EX (int, int);
86 static void OP_EMC (int,int);
87 static void OP_MXC (int,int);
88 static void OP_MS (int, int);
89 static void OP_XS (int, int);
90 static void OP_M (int, int);
91 static void OP_VEX (int, int);
92 static void OP_EX_Vex (int, int);
93 static void OP_EX_VexW (int, int);
94 static void OP_EX_VexImmW (int, int);
95 static void OP_XMM_Vex (int, int);
96 static void OP_XMM_VexW (int, int);
97 static void OP_REG_VexI4 (int, int);
98 static void PCLMUL_Fixup (int, int);
99 static void VEXI4_Fixup (int, int);
100 static void VZERO_Fixup (int, int);
101 static void VCMP_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void NOP_Fixup1 (int, int);
106 static void NOP_Fixup2 (int, int);
107 static void OP_3DNowSuffix (int, int);
108 static void CMP_Fixup (int, int);
109 static void BadOp (void);
110 static void REP_Fixup (int, int);
111 static void HLE_Fixup1 (int, int);
112 static void HLE_Fixup2 (int, int);
113 static void HLE_Fixup3 (int, int);
114 static void CMPXCHG8B_Fixup (int, int);
115 static void XMM_Fixup (int, int);
116 static void CRC32_Fixup (int, int);
117 static void FXSAVE_Fixup (int, int);
118 static void OP_LWPCB_E (int, int);
119 static void OP_LWP_E (int, int);
120 static void OP_Vex_2src_1 (int, int);
121 static void OP_Vex_2src_2 (int, int);
123 static void MOVBE_Fixup (int, int);
126 /* Points to first byte not fetched. */
127 bfd_byte *max_fetched;
128 bfd_byte the_buffer[MAX_MNEM_SIZE];
141 enum address_mode address_mode;
143 /* Flags for the prefixes for the current instruction. See below. */
146 /* REX prefix the current instruction. See below. */
148 /* Bits of REX we've already used. */
150 /* REX bits in original REX prefix ignored. */
151 static int rex_ignored;
152 /* Mark parts used in the REX prefix. When we are testing for
153 empty prefix (for 8bit register REX extension), just mask it
154 out. Otherwise test for REX bit is excuse for existence of REX
155 only in case value is nonzero. */
156 #define USED_REX(value) \
161 rex_used |= (value) | REX_OPCODE; \
164 rex_used |= REX_OPCODE; \
167 /* Flags for prefixes which we somehow handled when printing the
168 current instruction. */
169 static int used_prefixes;
171 /* Flags stored in PREFIXES. */
172 #define PREFIX_REPZ 1
173 #define PREFIX_REPNZ 2
174 #define PREFIX_LOCK 4
176 #define PREFIX_SS 0x10
177 #define PREFIX_DS 0x20
178 #define PREFIX_ES 0x40
179 #define PREFIX_FS 0x80
180 #define PREFIX_GS 0x100
181 #define PREFIX_DATA 0x200
182 #define PREFIX_ADDR 0x400
183 #define PREFIX_FWAIT 0x800
185 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
186 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
188 #define FETCH_DATA(info, addr) \
189 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
190 ? 1 : fetch_data ((info), (addr)))
193 fetch_data (struct disassemble_info *info, bfd_byte *addr)
196 struct dis_private *priv = (struct dis_private *) info->private_data;
197 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
199 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
200 status = (*info->read_memory_func) (start,
202 addr - priv->max_fetched,
208 /* If we did manage to read at least one byte, then
209 print_insn_i386 will do something sensible. Otherwise, print
210 an error. We do that here because this is where we know
212 if (priv->max_fetched == priv->the_buffer)
213 (*info->memory_error_func) (status, start, info);
214 longjmp (priv->bailout, 1);
217 priv->max_fetched = addr;
221 #define XX { NULL, 0 }
222 #define Bad_Opcode NULL, { { NULL, 0 } }
224 #define Eb { OP_E, b_mode }
225 #define EbS { OP_E, b_swap_mode }
226 #define Ev { OP_E, v_mode }
227 #define EvS { OP_E, v_swap_mode }
228 #define Ed { OP_E, d_mode }
229 #define Edq { OP_E, dq_mode }
230 #define Edqw { OP_E, dqw_mode }
231 #define Edqb { OP_E, dqb_mode }
232 #define Edqd { OP_E, dqd_mode }
233 #define Eq { OP_E, q_mode }
234 #define indirEv { OP_indirE, stack_v_mode }
235 #define indirEp { OP_indirE, f_mode }
236 #define stackEv { OP_E, stack_v_mode }
237 #define Em { OP_E, m_mode }
238 #define Ew { OP_E, w_mode }
239 #define M { OP_M, 0 } /* lea, lgdt, etc. */
240 #define Ma { OP_M, a_mode }
241 #define Mb { OP_M, b_mode }
242 #define Md { OP_M, d_mode }
243 #define Mo { OP_M, o_mode }
244 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
245 #define Mq { OP_M, q_mode }
246 #define Mx { OP_M, x_mode }
247 #define Mxmm { OP_M, xmm_mode }
248 #define Gb { OP_G, b_mode }
249 #define Gv { OP_G, v_mode }
250 #define Gd { OP_G, d_mode }
251 #define Gdq { OP_G, dq_mode }
252 #define Gm { OP_G, m_mode }
253 #define Gw { OP_G, w_mode }
254 #define Rd { OP_R, d_mode }
255 #define Rm { OP_R, m_mode }
256 #define Ib { OP_I, b_mode }
257 #define sIb { OP_sI, b_mode } /* sign extened byte */
258 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
259 #define Iv { OP_I, v_mode }
260 #define sIv { OP_sI, v_mode }
261 #define Iq { OP_I, q_mode }
262 #define Iv64 { OP_I64, v_mode }
263 #define Iw { OP_I, w_mode }
264 #define I1 { OP_I, const_1_mode }
265 #define Jb { OP_J, b_mode }
266 #define Jv { OP_J, v_mode }
267 #define Cm { OP_C, m_mode }
268 #define Dm { OP_D, m_mode }
269 #define Td { OP_T, d_mode }
270 #define Skip_MODRM { OP_Skip_MODRM, 0 }
272 #define RMeAX { OP_REG, eAX_reg }
273 #define RMeBX { OP_REG, eBX_reg }
274 #define RMeCX { OP_REG, eCX_reg }
275 #define RMeDX { OP_REG, eDX_reg }
276 #define RMeSP { OP_REG, eSP_reg }
277 #define RMeBP { OP_REG, eBP_reg }
278 #define RMeSI { OP_REG, eSI_reg }
279 #define RMeDI { OP_REG, eDI_reg }
280 #define RMrAX { OP_REG, rAX_reg }
281 #define RMrBX { OP_REG, rBX_reg }
282 #define RMrCX { OP_REG, rCX_reg }
283 #define RMrDX { OP_REG, rDX_reg }
284 #define RMrSP { OP_REG, rSP_reg }
285 #define RMrBP { OP_REG, rBP_reg }
286 #define RMrSI { OP_REG, rSI_reg }
287 #define RMrDI { OP_REG, rDI_reg }
288 #define RMAL { OP_REG, al_reg }
289 #define RMCL { OP_REG, cl_reg }
290 #define RMDL { OP_REG, dl_reg }
291 #define RMBL { OP_REG, bl_reg }
292 #define RMAH { OP_REG, ah_reg }
293 #define RMCH { OP_REG, ch_reg }
294 #define RMDH { OP_REG, dh_reg }
295 #define RMBH { OP_REG, bh_reg }
296 #define RMAX { OP_REG, ax_reg }
297 #define RMDX { OP_REG, dx_reg }
299 #define eAX { OP_IMREG, eAX_reg }
300 #define eBX { OP_IMREG, eBX_reg }
301 #define eCX { OP_IMREG, eCX_reg }
302 #define eDX { OP_IMREG, eDX_reg }
303 #define eSP { OP_IMREG, eSP_reg }
304 #define eBP { OP_IMREG, eBP_reg }
305 #define eSI { OP_IMREG, eSI_reg }
306 #define eDI { OP_IMREG, eDI_reg }
307 #define AL { OP_IMREG, al_reg }
308 #define CL { OP_IMREG, cl_reg }
309 #define DL { OP_IMREG, dl_reg }
310 #define BL { OP_IMREG, bl_reg }
311 #define AH { OP_IMREG, ah_reg }
312 #define CH { OP_IMREG, ch_reg }
313 #define DH { OP_IMREG, dh_reg }
314 #define BH { OP_IMREG, bh_reg }
315 #define AX { OP_IMREG, ax_reg }
316 #define DX { OP_IMREG, dx_reg }
317 #define zAX { OP_IMREG, z_mode_ax_reg }
318 #define indirDX { OP_IMREG, indir_dx_reg }
320 #define Sw { OP_SEG, w_mode }
321 #define Sv { OP_SEG, v_mode }
322 #define Ap { OP_DIR, 0 }
323 #define Ob { OP_OFF64, b_mode }
324 #define Ov { OP_OFF64, v_mode }
325 #define Xb { OP_DSreg, eSI_reg }
326 #define Xv { OP_DSreg, eSI_reg }
327 #define Xz { OP_DSreg, eSI_reg }
328 #define Yb { OP_ESreg, eDI_reg }
329 #define Yv { OP_ESreg, eDI_reg }
330 #define DSBX { OP_DSreg, eBX_reg }
332 #define es { OP_REG, es_reg }
333 #define ss { OP_REG, ss_reg }
334 #define cs { OP_REG, cs_reg }
335 #define ds { OP_REG, ds_reg }
336 #define fs { OP_REG, fs_reg }
337 #define gs { OP_REG, gs_reg }
339 #define MX { OP_MMX, 0 }
340 #define XM { OP_XMM, 0 }
341 #define XMScalar { OP_XMM, scalar_mode }
342 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
343 #define XMM { OP_XMM, xmm_mode }
344 #define EM { OP_EM, v_mode }
345 #define EMS { OP_EM, v_swap_mode }
346 #define EMd { OP_EM, d_mode }
347 #define EMx { OP_EM, x_mode }
348 #define EXw { OP_EX, w_mode }
349 #define EXd { OP_EX, d_mode }
350 #define EXdScalar { OP_EX, d_scalar_mode }
351 #define EXdS { OP_EX, d_swap_mode }
352 #define EXq { OP_EX, q_mode }
353 #define EXqScalar { OP_EX, q_scalar_mode }
354 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
355 #define EXqS { OP_EX, q_swap_mode }
356 #define EXx { OP_EX, x_mode }
357 #define EXxS { OP_EX, x_swap_mode }
358 #define EXxmm { OP_EX, xmm_mode }
359 #define EXxmmq { OP_EX, xmmq_mode }
360 #define EXxmm_mb { OP_EX, xmm_mb_mode }
361 #define EXxmm_mw { OP_EX, xmm_mw_mode }
362 #define EXxmm_md { OP_EX, xmm_md_mode }
363 #define EXxmm_mq { OP_EX, xmm_mq_mode }
364 #define EXxmmdw { OP_EX, xmmdw_mode }
365 #define EXxmmqd { OP_EX, xmmqd_mode }
366 #define EXymmq { OP_EX, ymmq_mode }
367 #define EXVexWdq { OP_EX, vex_w_dq_mode }
368 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
369 #define MS { OP_MS, v_mode }
370 #define XS { OP_XS, v_mode }
371 #define EMCq { OP_EMC, q_mode }
372 #define MXC { OP_MXC, 0 }
373 #define OPSUF { OP_3DNowSuffix, 0 }
374 #define CMP { CMP_Fixup, 0 }
375 #define XMM0 { XMM_Fixup, 0 }
376 #define FXSAVE { FXSAVE_Fixup, 0 }
377 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
378 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
380 #define Vex { OP_VEX, vex_mode }
381 #define VexScalar { OP_VEX, vex_scalar_mode }
382 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
383 #define Vex128 { OP_VEX, vex128_mode }
384 #define Vex256 { OP_VEX, vex256_mode }
385 #define VexGdq { OP_VEX, dq_mode }
386 #define VexI4 { VEXI4_Fixup, 0}
387 #define EXdVex { OP_EX_Vex, d_mode }
388 #define EXdVexS { OP_EX_Vex, d_swap_mode }
389 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
390 #define EXqVex { OP_EX_Vex, q_mode }
391 #define EXqVexS { OP_EX_Vex, q_swap_mode }
392 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
393 #define EXVexW { OP_EX_VexW, x_mode }
394 #define EXdVexW { OP_EX_VexW, d_mode }
395 #define EXqVexW { OP_EX_VexW, q_mode }
396 #define EXVexImmW { OP_EX_VexImmW, x_mode }
397 #define XMVex { OP_XMM_Vex, 0 }
398 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
399 #define XMVexW { OP_XMM_VexW, 0 }
400 #define XMVexI4 { OP_REG_VexI4, x_mode }
401 #define PCLMUL { PCLMUL_Fixup, 0 }
402 #define VZERO { VZERO_Fixup, 0 }
403 #define VCMP { VCMP_Fixup, 0 }
405 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
406 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
408 /* Used handle "rep" prefix for string instructions. */
409 #define Xbr { REP_Fixup, eSI_reg }
410 #define Xvr { REP_Fixup, eSI_reg }
411 #define Ybr { REP_Fixup, eDI_reg }
412 #define Yvr { REP_Fixup, eDI_reg }
413 #define Yzr { REP_Fixup, eDI_reg }
414 #define indirDXr { REP_Fixup, indir_dx_reg }
415 #define ALr { REP_Fixup, al_reg }
416 #define eAXr { REP_Fixup, eAX_reg }
418 /* Used handle HLE prefix for lockable instructions. */
419 #define Ebh1 { HLE_Fixup1, b_mode }
420 #define Evh1 { HLE_Fixup1, v_mode }
421 #define Ebh2 { HLE_Fixup2, b_mode }
422 #define Evh2 { HLE_Fixup2, v_mode }
423 #define Ebh3 { HLE_Fixup3, b_mode }
424 #define Evh3 { HLE_Fixup3, v_mode }
426 #define cond_jump_flag { NULL, cond_jump_mode }
427 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
429 /* bits in sizeflag */
430 #define SUFFIX_ALWAYS 4
438 /* byte operand with operand swapped */
440 /* byte operand, sign extend like 'T' suffix */
442 /* operand size depends on prefixes */
444 /* operand size depends on prefixes with operand swapped */
448 /* double word operand */
450 /* double word operand with operand swapped */
452 /* quad word operand */
454 /* quad word operand with operand swapped */
456 /* ten-byte operand */
458 /* 16-byte XMM or 32-byte YMM operand */
460 /* 16-byte XMM or 32-byte YMM operand with operand swapped */
462 /* 16-byte XMM operand */
464 /* 16-byte XMM or quad word operand */
466 /* XMM register or byte memory operand */
468 /* XMM register or word memory operand */
470 /* XMM register or double word memory operand */
472 /* XMM register or quad word memory operand */
474 /* 16-byte XMM, word or double word operand */
476 /* 16-byte XMM, double word or quad word operand */
478 /* 32-byte YMM or quad word operand */
480 /* 32-byte YMM or 16-byte word operand */
482 /* d_mode in 32bit, q_mode in 64bit mode. */
484 /* pair of v_mode operands */
488 /* operand size depends on REX prefixes. */
490 /* registers like dq_mode, memory like w_mode. */
492 /* 4- or 6-byte pointer operand */
495 /* v_mode for stack-related opcodes. */
497 /* non-quad operand size depends on prefixes */
499 /* 16-byte operand */
501 /* registers like dq_mode, memory like b_mode. */
503 /* registers like dq_mode, memory like d_mode. */
505 /* normal vex mode */
507 /* 128bit vex mode */
509 /* 256bit vex mode */
511 /* operand size depends on the VEX.W bit. */
514 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
515 vex_vsib_d_w_dq_mode,
516 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
517 vex_vsib_q_w_dq_mode,
519 /* scalar, ignore vector length. */
521 /* like d_mode, ignore vector length. */
523 /* like d_swap_mode, ignore vector length. */
525 /* like q_mode, ignore vector length. */
527 /* like q_swap_mode, ignore vector length. */
529 /* like vex_mode, ignore vector length. */
531 /* like vex_w_dq_mode, ignore vector length. */
532 vex_scalar_w_dq_mode,
597 #define FLOAT NULL, { { NULL, FLOATCODE } }
599 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }
600 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
601 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
602 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
603 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
604 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
605 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
606 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
607 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
608 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
609 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
610 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
712 MOD_VEX_0F12_PREFIX_0,
714 MOD_VEX_0F16_PREFIX_0,
730 MOD_VEX_0FD7_PREFIX_2,
731 MOD_VEX_0FE7_PREFIX_2,
732 MOD_VEX_0FF0_PREFIX_3,
733 MOD_VEX_0F381A_PREFIX_2,
734 MOD_VEX_0F382A_PREFIX_2,
735 MOD_VEX_0F382C_PREFIX_2,
736 MOD_VEX_0F382D_PREFIX_2,
737 MOD_VEX_0F382E_PREFIX_2,
738 MOD_VEX_0F382F_PREFIX_2,
739 MOD_VEX_0F385A_PREFIX_2,
740 MOD_VEX_0F388C_PREFIX_2,
741 MOD_VEX_0F388E_PREFIX_2,
915 PREFIX_VEX_0F71_REG_2,
916 PREFIX_VEX_0F71_REG_4,
917 PREFIX_VEX_0F71_REG_6,
918 PREFIX_VEX_0F72_REG_2,
919 PREFIX_VEX_0F72_REG_4,
920 PREFIX_VEX_0F72_REG_6,
921 PREFIX_VEX_0F73_REG_2,
922 PREFIX_VEX_0F73_REG_3,
923 PREFIX_VEX_0F73_REG_6,
924 PREFIX_VEX_0F73_REG_7,
1090 PREFIX_VEX_0F38F3_REG_1,
1091 PREFIX_VEX_0F38F3_REG_2,
1092 PREFIX_VEX_0F38F3_REG_3,
1194 THREE_BYTE_0F38 = 0,
1215 VEX_LEN_0F10_P_1 = 0,
1219 VEX_LEN_0F12_P_0_M_0,
1220 VEX_LEN_0F12_P_0_M_1,
1223 VEX_LEN_0F16_P_0_M_0,
1224 VEX_LEN_0F16_P_0_M_1,
1258 VEX_LEN_0FAE_R_2_M_0,
1259 VEX_LEN_0FAE_R_3_M_0,
1268 VEX_LEN_0F381A_P_2_M_0,
1271 VEX_LEN_0F385A_P_2_M_0,
1278 VEX_LEN_0F38F3_R_1_P_0,
1279 VEX_LEN_0F38F3_R_2_P_0,
1280 VEX_LEN_0F38F3_R_3_P_0,
1322 VEX_LEN_0FXOP_09_80,
1513 VEX_W_0F381A_P_2_M_0,
1525 VEX_W_0F382A_P_2_M_0,
1527 VEX_W_0F382C_P_2_M_0,
1528 VEX_W_0F382D_P_2_M_0,
1529 VEX_W_0F382E_P_2_M_0,
1530 VEX_W_0F382F_P_2_M_0,
1552 VEX_W_0F385A_P_2_M_0,
1599 typedef void (*op_rtn) (int bytemode, int sizeflag);
1610 /* Upper case letters in the instruction names here are macros.
1611 'A' => print 'b' if no register operands or suffix_always is true
1612 'B' => print 'b' if suffix_always is true
1613 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1615 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1616 suffix_always is true
1617 'E' => print 'e' if 32-bit form of jcxz
1618 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1619 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1620 'H' => print ",pt" or ",pn" branch hint
1621 'I' => honor following macro letter even in Intel mode (implemented only
1622 for some of the macro letters)
1624 'K' => print 'd' or 'q' if rex prefix is present.
1625 'L' => print 'l' if suffix_always is true
1626 'M' => print 'r' if intel_mnemonic is false.
1627 'N' => print 'n' if instruction has no wait "prefix"
1628 'O' => print 'd' or 'o' (or 'q' in Intel mode)
1629 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
1630 or suffix_always is true. print 'q' if rex prefix is present.
1631 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1633 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1634 'S' => print 'w', 'l' or 'q' if suffix_always is true
1635 'T' => print 'q' in 64bit mode and behave as 'P' otherwise
1636 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise
1637 'V' => print 'q' in 64bit mode and behave as 'S' otherwise
1638 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1639 'X' => print 's', 'd' depending on data16 prefix (for XMM)
1640 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
1641 suffix_always is true.
1642 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
1643 '!' => change condition from true to false or from false to true.
1644 '%' => add 1 upper case letter to the macro.
1646 2 upper case letter macros:
1647 "XY" => print 'x' or 'y' if no register operands or suffix_always
1649 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1650 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
1651 or suffix_always is true
1652 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1653 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1654 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1655 "LW" => print 'd', 'q' depending on the VEX.W bit
1657 Many of the above letters print nothing in Intel mode. See "putop"
1660 Braces '{' and '}', and vertical bars '|', indicate alternative
1661 mnemonic strings for AT&T and Intel. */
1663 static const struct dis386 dis386[] = {
1665 { "addB", { Ebh1, Gb } },
1666 { "addS", { Evh1, Gv } },
1667 { "addB", { Gb, EbS } },
1668 { "addS", { Gv, EvS } },
1669 { "addB", { AL, Ib } },
1670 { "addS", { eAX, Iv } },
1671 { X86_64_TABLE (X86_64_06) },
1672 { X86_64_TABLE (X86_64_07) },
1674 { "orB", { Ebh1, Gb } },
1675 { "orS", { Evh1, Gv } },
1676 { "orB", { Gb, EbS } },
1677 { "orS", { Gv, EvS } },
1678 { "orB", { AL, Ib } },
1679 { "orS", { eAX, Iv } },
1680 { X86_64_TABLE (X86_64_0D) },
1681 { Bad_Opcode }, /* 0x0f extended opcode escape */
1683 { "adcB", { Ebh1, Gb } },
1684 { "adcS", { Evh1, Gv } },
1685 { "adcB", { Gb, EbS } },
1686 { "adcS", { Gv, EvS } },
1687 { "adcB", { AL, Ib } },
1688 { "adcS", { eAX, Iv } },
1689 { X86_64_TABLE (X86_64_16) },
1690 { X86_64_TABLE (X86_64_17) },
1692 { "sbbB", { Ebh1, Gb } },
1693 { "sbbS", { Evh1, Gv } },
1694 { "sbbB", { Gb, EbS } },
1695 { "sbbS", { Gv, EvS } },
1696 { "sbbB", { AL, Ib } },
1697 { "sbbS", { eAX, Iv } },
1698 { X86_64_TABLE (X86_64_1E) },
1699 { X86_64_TABLE (X86_64_1F) },
1701 { "andB", { Ebh1, Gb } },
1702 { "andS", { Evh1, Gv } },
1703 { "andB", { Gb, EbS } },
1704 { "andS", { Gv, EvS } },
1705 { "andB", { AL, Ib } },
1706 { "andS", { eAX, Iv } },
1707 { Bad_Opcode }, /* SEG ES prefix */
1708 { X86_64_TABLE (X86_64_27) },
1710 { "subB", { Ebh1, Gb } },
1711 { "subS", { Evh1, Gv } },
1712 { "subB", { Gb, EbS } },
1713 { "subS", { Gv, EvS } },
1714 { "subB", { AL, Ib } },
1715 { "subS", { eAX, Iv } },
1716 { Bad_Opcode }, /* SEG CS prefix */
1717 { X86_64_TABLE (X86_64_2F) },
1719 { "xorB", { Ebh1, Gb } },
1720 { "xorS", { Evh1, Gv } },
1721 { "xorB", { Gb, EbS } },
1722 { "xorS", { Gv, EvS } },
1723 { "xorB", { AL, Ib } },
1724 { "xorS", { eAX, Iv } },
1725 { Bad_Opcode }, /* SEG SS prefix */
1726 { X86_64_TABLE (X86_64_37) },
1728 { "cmpB", { Eb, Gb } },
1729 { "cmpS", { Ev, Gv } },
1730 { "cmpB", { Gb, EbS } },
1731 { "cmpS", { Gv, EvS } },
1732 { "cmpB", { AL, Ib } },
1733 { "cmpS", { eAX, Iv } },
1734 { Bad_Opcode }, /* SEG DS prefix */
1735 { X86_64_TABLE (X86_64_3F) },
1737 { "inc{S|}", { RMeAX } },
1738 { "inc{S|}", { RMeCX } },
1739 { "inc{S|}", { RMeDX } },
1740 { "inc{S|}", { RMeBX } },
1741 { "inc{S|}", { RMeSP } },
1742 { "inc{S|}", { RMeBP } },
1743 { "inc{S|}", { RMeSI } },
1744 { "inc{S|}", { RMeDI } },
1746 { "dec{S|}", { RMeAX } },
1747 { "dec{S|}", { RMeCX } },
1748 { "dec{S|}", { RMeDX } },
1749 { "dec{S|}", { RMeBX } },
1750 { "dec{S|}", { RMeSP } },
1751 { "dec{S|}", { RMeBP } },
1752 { "dec{S|}", { RMeSI } },
1753 { "dec{S|}", { RMeDI } },
1755 { "pushV", { RMrAX } },
1756 { "pushV", { RMrCX } },
1757 { "pushV", { RMrDX } },
1758 { "pushV", { RMrBX } },
1759 { "pushV", { RMrSP } },
1760 { "pushV", { RMrBP } },
1761 { "pushV", { RMrSI } },
1762 { "pushV", { RMrDI } },
1764 { "popV", { RMrAX } },
1765 { "popV", { RMrCX } },
1766 { "popV", { RMrDX } },
1767 { "popV", { RMrBX } },
1768 { "popV", { RMrSP } },
1769 { "popV", { RMrBP } },
1770 { "popV", { RMrSI } },
1771 { "popV", { RMrDI } },
1773 { X86_64_TABLE (X86_64_60) },
1774 { X86_64_TABLE (X86_64_61) },
1775 { X86_64_TABLE (X86_64_62) },
1776 { X86_64_TABLE (X86_64_63) },
1777 { Bad_Opcode }, /* seg fs */
1778 { Bad_Opcode }, /* seg gs */
1779 { Bad_Opcode }, /* op size prefix */
1780 { Bad_Opcode }, /* adr size prefix */
1782 { "pushT", { sIv } },
1783 { "imulS", { Gv, Ev, Iv } },
1784 { "pushT", { sIbT } },
1785 { "imulS", { Gv, Ev, sIb } },
1786 { "ins{b|}", { Ybr, indirDX } },
1787 { X86_64_TABLE (X86_64_6D) },
1788 { "outs{b|}", { indirDXr, Xb } },
1789 { X86_64_TABLE (X86_64_6F) },
1791 { "joH", { Jb, XX, cond_jump_flag } },
1792 { "jnoH", { Jb, XX, cond_jump_flag } },
1793 { "jbH", { Jb, XX, cond_jump_flag } },
1794 { "jaeH", { Jb, XX, cond_jump_flag } },
1795 { "jeH", { Jb, XX, cond_jump_flag } },
1796 { "jneH", { Jb, XX, cond_jump_flag } },
1797 { "jbeH", { Jb, XX, cond_jump_flag } },
1798 { "jaH", { Jb, XX, cond_jump_flag } },
1800 { "jsH", { Jb, XX, cond_jump_flag } },
1801 { "jnsH", { Jb, XX, cond_jump_flag } },
1802 { "jpH", { Jb, XX, cond_jump_flag } },
1803 { "jnpH", { Jb, XX, cond_jump_flag } },
1804 { "jlH", { Jb, XX, cond_jump_flag } },
1805 { "jgeH", { Jb, XX, cond_jump_flag } },
1806 { "jleH", { Jb, XX, cond_jump_flag } },
1807 { "jgH", { Jb, XX, cond_jump_flag } },
1809 { REG_TABLE (REG_80) },
1810 { REG_TABLE (REG_81) },
1812 { REG_TABLE (REG_82) },
1813 { "testB", { Eb, Gb } },
1814 { "testS", { Ev, Gv } },
1815 { "xchgB", { Ebh2, Gb } },
1816 { "xchgS", { Evh2, Gv } },
1818 { "movB", { Ebh3, Gb } },
1819 { "movS", { Evh3, Gv } },
1820 { "movB", { Gb, EbS } },
1821 { "movS", { Gv, EvS } },
1822 { "movD", { Sv, Sw } },
1823 { MOD_TABLE (MOD_8D) },
1824 { "movD", { Sw, Sv } },
1825 { REG_TABLE (REG_8F) },
1827 { PREFIX_TABLE (PREFIX_90) },
1828 { "xchgS", { RMeCX, eAX } },
1829 { "xchgS", { RMeDX, eAX } },
1830 { "xchgS", { RMeBX, eAX } },
1831 { "xchgS", { RMeSP, eAX } },
1832 { "xchgS", { RMeBP, eAX } },
1833 { "xchgS", { RMeSI, eAX } },
1834 { "xchgS", { RMeDI, eAX } },
1836 { "cW{t|}R", { XX } },
1837 { "cR{t|}O", { XX } },
1838 { X86_64_TABLE (X86_64_9A) },
1839 { Bad_Opcode }, /* fwait */
1840 { "pushfT", { XX } },
1841 { "popfT", { XX } },
1845 { "mov%LB", { AL, Ob } },
1846 { "mov%LS", { eAX, Ov } },
1847 { "mov%LB", { Ob, AL } },
1848 { "mov%LS", { Ov, eAX } },
1849 { "movs{b|}", { Ybr, Xb } },
1850 { "movs{R|}", { Yvr, Xv } },
1851 { "cmps{b|}", { Xb, Yb } },
1852 { "cmps{R|}", { Xv, Yv } },
1854 { "testB", { AL, Ib } },
1855 { "testS", { eAX, Iv } },
1856 { "stosB", { Ybr, AL } },
1857 { "stosS", { Yvr, eAX } },
1858 { "lodsB", { ALr, Xb } },
1859 { "lodsS", { eAXr, Xv } },
1860 { "scasB", { AL, Yb } },
1861 { "scasS", { eAX, Yv } },
1863 { "movB", { RMAL, Ib } },
1864 { "movB", { RMCL, Ib } },
1865 { "movB", { RMDL, Ib } },
1866 { "movB", { RMBL, Ib } },
1867 { "movB", { RMAH, Ib } },
1868 { "movB", { RMCH, Ib } },
1869 { "movB", { RMDH, Ib } },
1870 { "movB", { RMBH, Ib } },
1872 { "mov%LV", { RMeAX, Iv64 } },
1873 { "mov%LV", { RMeCX, Iv64 } },
1874 { "mov%LV", { RMeDX, Iv64 } },
1875 { "mov%LV", { RMeBX, Iv64 } },
1876 { "mov%LV", { RMeSP, Iv64 } },
1877 { "mov%LV", { RMeBP, Iv64 } },
1878 { "mov%LV", { RMeSI, Iv64 } },
1879 { "mov%LV", { RMeDI, Iv64 } },
1881 { REG_TABLE (REG_C0) },
1882 { REG_TABLE (REG_C1) },
1885 { X86_64_TABLE (X86_64_C4) },
1886 { X86_64_TABLE (X86_64_C5) },
1887 { REG_TABLE (REG_C6) },
1888 { REG_TABLE (REG_C7) },
1890 { "enterT", { Iw, Ib } },
1891 { "leaveT", { XX } },
1892 { "Jret{|f}P", { Iw } },
1893 { "Jret{|f}P", { XX } },
1896 { X86_64_TABLE (X86_64_CE) },
1897 { "iretP", { XX } },
1899 { REG_TABLE (REG_D0) },
1900 { REG_TABLE (REG_D1) },
1901 { REG_TABLE (REG_D2) },
1902 { REG_TABLE (REG_D3) },
1903 { X86_64_TABLE (X86_64_D4) },
1904 { X86_64_TABLE (X86_64_D5) },
1906 { "xlat", { DSBX } },
1917 { "loopneFH", { Jb, XX, loop_jcxz_flag } },
1918 { "loopeFH", { Jb, XX, loop_jcxz_flag } },
1919 { "loopFH", { Jb, XX, loop_jcxz_flag } },
1920 { "jEcxzH", { Jb, XX, loop_jcxz_flag } },
1921 { "inB", { AL, Ib } },
1922 { "inG", { zAX, Ib } },
1923 { "outB", { Ib, AL } },
1924 { "outG", { Ib, zAX } },
1926 { "callT", { Jv } },
1928 { X86_64_TABLE (X86_64_EA) },
1930 { "inB", { AL, indirDX } },
1931 { "inG", { zAX, indirDX } },
1932 { "outB", { indirDX, AL } },
1933 { "outG", { indirDX, zAX } },
1935 { Bad_Opcode }, /* lock prefix */
1936 { "icebp", { XX } },
1937 { Bad_Opcode }, /* repne */
1938 { Bad_Opcode }, /* repz */
1941 { REG_TABLE (REG_F6) },
1942 { REG_TABLE (REG_F7) },
1950 { REG_TABLE (REG_FE) },
1951 { REG_TABLE (REG_FF) },
1954 static const struct dis386 dis386_twobyte[] = {
1956 { REG_TABLE (REG_0F00 ) },
1957 { REG_TABLE (REG_0F01 ) },
1958 { "larS", { Gv, Ew } },
1959 { "lslS", { Gv, Ew } },
1961 { "syscall", { XX } },
1963 { "sysretP", { XX } },
1966 { "wbinvd", { XX } },
1970 { REG_TABLE (REG_0F0D) },
1971 { "femms", { XX } },
1972 { "", { MX, EM, OPSUF } }, /* See OP_3DNowSuffix. */
1974 { PREFIX_TABLE (PREFIX_0F10) },
1975 { PREFIX_TABLE (PREFIX_0F11) },
1976 { PREFIX_TABLE (PREFIX_0F12) },
1977 { MOD_TABLE (MOD_0F13) },
1978 { "unpcklpX", { XM, EXx } },
1979 { "unpckhpX", { XM, EXx } },
1980 { PREFIX_TABLE (PREFIX_0F16) },
1981 { MOD_TABLE (MOD_0F17) },
1983 { REG_TABLE (REG_0F18) },
1992 { MOD_TABLE (MOD_0F20) },
1993 { MOD_TABLE (MOD_0F21) },
1994 { MOD_TABLE (MOD_0F22) },
1995 { MOD_TABLE (MOD_0F23) },
1996 { MOD_TABLE (MOD_0F24) },
1998 { MOD_TABLE (MOD_0F26) },
2001 { "movapX", { XM, EXx } },
2002 { "movapX", { EXxS, XM } },
2003 { PREFIX_TABLE (PREFIX_0F2A) },
2004 { PREFIX_TABLE (PREFIX_0F2B) },
2005 { PREFIX_TABLE (PREFIX_0F2C) },
2006 { PREFIX_TABLE (PREFIX_0F2D) },
2007 { PREFIX_TABLE (PREFIX_0F2E) },
2008 { PREFIX_TABLE (PREFIX_0F2F) },
2010 { "wrmsr", { XX } },
2011 { "rdtsc", { XX } },
2012 { "rdmsr", { XX } },
2013 { "rdpmc", { XX } },
2014 { "sysenter", { XX } },
2015 { "sysexit", { XX } },
2017 { "getsec", { XX } },
2019 { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2021 { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2028 { "cmovoS", { Gv, Ev } },
2029 { "cmovnoS", { Gv, Ev } },
2030 { "cmovbS", { Gv, Ev } },
2031 { "cmovaeS", { Gv, Ev } },
2032 { "cmoveS", { Gv, Ev } },
2033 { "cmovneS", { Gv, Ev } },
2034 { "cmovbeS", { Gv, Ev } },
2035 { "cmovaS", { Gv, Ev } },
2037 { "cmovsS", { Gv, Ev } },
2038 { "cmovnsS", { Gv, Ev } },
2039 { "cmovpS", { Gv, Ev } },
2040 { "cmovnpS", { Gv, Ev } },
2041 { "cmovlS", { Gv, Ev } },
2042 { "cmovgeS", { Gv, Ev } },
2043 { "cmovleS", { Gv, Ev } },
2044 { "cmovgS", { Gv, Ev } },
2046 { MOD_TABLE (MOD_0F51) },
2047 { PREFIX_TABLE (PREFIX_0F51) },
2048 { PREFIX_TABLE (PREFIX_0F52) },
2049 { PREFIX_TABLE (PREFIX_0F53) },
2050 { "andpX", { XM, EXx } },
2051 { "andnpX", { XM, EXx } },
2052 { "orpX", { XM, EXx } },
2053 { "xorpX", { XM, EXx } },
2055 { PREFIX_TABLE (PREFIX_0F58) },
2056 { PREFIX_TABLE (PREFIX_0F59) },
2057 { PREFIX_TABLE (PREFIX_0F5A) },
2058 { PREFIX_TABLE (PREFIX_0F5B) },
2059 { PREFIX_TABLE (PREFIX_0F5C) },
2060 { PREFIX_TABLE (PREFIX_0F5D) },
2061 { PREFIX_TABLE (PREFIX_0F5E) },
2062 { PREFIX_TABLE (PREFIX_0F5F) },
2064 { PREFIX_TABLE (PREFIX_0F60) },
2065 { PREFIX_TABLE (PREFIX_0F61) },
2066 { PREFIX_TABLE (PREFIX_0F62) },
2067 { "packsswb", { MX, EM } },
2068 { "pcmpgtb", { MX, EM } },
2069 { "pcmpgtw", { MX, EM } },
2070 { "pcmpgtd", { MX, EM } },
2071 { "packuswb", { MX, EM } },
2073 { "punpckhbw", { MX, EM } },
2074 { "punpckhwd", { MX, EM } },
2075 { "punpckhdq", { MX, EM } },
2076 { "packssdw", { MX, EM } },
2077 { PREFIX_TABLE (PREFIX_0F6C) },
2078 { PREFIX_TABLE (PREFIX_0F6D) },
2079 { "movK", { MX, Edq } },
2080 { PREFIX_TABLE (PREFIX_0F6F) },
2082 { PREFIX_TABLE (PREFIX_0F70) },
2083 { REG_TABLE (REG_0F71) },
2084 { REG_TABLE (REG_0F72) },
2085 { REG_TABLE (REG_0F73) },
2086 { "pcmpeqb", { MX, EM } },
2087 { "pcmpeqw", { MX, EM } },
2088 { "pcmpeqd", { MX, EM } },
2091 { PREFIX_TABLE (PREFIX_0F78) },
2092 { PREFIX_TABLE (PREFIX_0F79) },
2093 { THREE_BYTE_TABLE (THREE_BYTE_0F7A) },
2095 { PREFIX_TABLE (PREFIX_0F7C) },
2096 { PREFIX_TABLE (PREFIX_0F7D) },
2097 { PREFIX_TABLE (PREFIX_0F7E) },
2098 { PREFIX_TABLE (PREFIX_0F7F) },
2100 { "joH", { Jv, XX, cond_jump_flag } },
2101 { "jnoH", { Jv, XX, cond_jump_flag } },
2102 { "jbH", { Jv, XX, cond_jump_flag } },
2103 { "jaeH", { Jv, XX, cond_jump_flag } },
2104 { "jeH", { Jv, XX, cond_jump_flag } },
2105 { "jneH", { Jv, XX, cond_jump_flag } },
2106 { "jbeH", { Jv, XX, cond_jump_flag } },
2107 { "jaH", { Jv, XX, cond_jump_flag } },
2109 { "jsH", { Jv, XX, cond_jump_flag } },
2110 { "jnsH", { Jv, XX, cond_jump_flag } },
2111 { "jpH", { Jv, XX, cond_jump_flag } },
2112 { "jnpH", { Jv, XX, cond_jump_flag } },
2113 { "jlH", { Jv, XX, cond_jump_flag } },
2114 { "jgeH", { Jv, XX, cond_jump_flag } },
2115 { "jleH", { Jv, XX, cond_jump_flag } },
2116 { "jgH", { Jv, XX, cond_jump_flag } },
2119 { "setno", { Eb } },
2121 { "setae", { Eb } },
2123 { "setne", { Eb } },
2124 { "setbe", { Eb } },
2128 { "setns", { Eb } },
2130 { "setnp", { Eb } },
2132 { "setge", { Eb } },
2133 { "setle", { Eb } },
2136 { "pushT", { fs } },
2138 { "cpuid", { XX } },
2139 { "btS", { Ev, Gv } },
2140 { "shldS", { Ev, Gv, Ib } },
2141 { "shldS", { Ev, Gv, CL } },
2142 { REG_TABLE (REG_0FA6) },
2143 { REG_TABLE (REG_0FA7) },
2145 { "pushT", { gs } },
2148 { "btsS", { Evh1, Gv } },
2149 { "shrdS", { Ev, Gv, Ib } },
2150 { "shrdS", { Ev, Gv, CL } },
2151 { REG_TABLE (REG_0FAE) },
2152 { "imulS", { Gv, Ev } },
2154 { "cmpxchgB", { Ebh1, Gb } },
2155 { "cmpxchgS", { Evh1, Gv } },
2156 { MOD_TABLE (MOD_0FB2) },
2157 { "btrS", { Evh1, Gv } },
2158 { MOD_TABLE (MOD_0FB4) },
2159 { MOD_TABLE (MOD_0FB5) },
2160 { "movz{bR|x}", { Gv, Eb } },
2161 { "movz{wR|x}", { Gv, Ew } }, /* yes, there really is movzww ! */
2163 { PREFIX_TABLE (PREFIX_0FB8) },
2165 { REG_TABLE (REG_0FBA) },
2166 { "btcS", { Evh1, Gv } },
2167 { PREFIX_TABLE (PREFIX_0FBC) },
2168 { PREFIX_TABLE (PREFIX_0FBD) },
2169 { "movs{bR|x}", { Gv, Eb } },
2170 { "movs{wR|x}", { Gv, Ew } }, /* yes, there really is movsww ! */
2172 { "xaddB", { Ebh1, Gb } },
2173 { "xaddS", { Evh1, Gv } },
2174 { PREFIX_TABLE (PREFIX_0FC2) },
2175 { PREFIX_TABLE (PREFIX_0FC3) },
2176 { "pinsrw", { MX, Edqw, Ib } },
2177 { "pextrw", { Gdq, MS, Ib } },
2178 { "shufpX", { XM, EXx, Ib } },
2179 { REG_TABLE (REG_0FC7) },
2181 { "bswap", { RMeAX } },
2182 { "bswap", { RMeCX } },
2183 { "bswap", { RMeDX } },
2184 { "bswap", { RMeBX } },
2185 { "bswap", { RMeSP } },
2186 { "bswap", { RMeBP } },
2187 { "bswap", { RMeSI } },
2188 { "bswap", { RMeDI } },
2190 { PREFIX_TABLE (PREFIX_0FD0) },
2191 { "psrlw", { MX, EM } },
2192 { "psrld", { MX, EM } },
2193 { "psrlq", { MX, EM } },
2194 { "paddq", { MX, EM } },
2195 { "pmullw", { MX, EM } },
2196 { PREFIX_TABLE (PREFIX_0FD6) },
2197 { MOD_TABLE (MOD_0FD7) },
2199 { "psubusb", { MX, EM } },
2200 { "psubusw", { MX, EM } },
2201 { "pminub", { MX, EM } },
2202 { "pand", { MX, EM } },
2203 { "paddusb", { MX, EM } },
2204 { "paddusw", { MX, EM } },
2205 { "pmaxub", { MX, EM } },
2206 { "pandn", { MX, EM } },
2208 { "pavgb", { MX, EM } },
2209 { "psraw", { MX, EM } },
2210 { "psrad", { MX, EM } },
2211 { "pavgw", { MX, EM } },
2212 { "pmulhuw", { MX, EM } },
2213 { "pmulhw", { MX, EM } },
2214 { PREFIX_TABLE (PREFIX_0FE6) },
2215 { PREFIX_TABLE (PREFIX_0FE7) },
2217 { "psubsb", { MX, EM } },
2218 { "psubsw", { MX, EM } },
2219 { "pminsw", { MX, EM } },
2220 { "por", { MX, EM } },
2221 { "paddsb", { MX, EM } },
2222 { "paddsw", { MX, EM } },
2223 { "pmaxsw", { MX, EM } },
2224 { "pxor", { MX, EM } },
2226 { PREFIX_TABLE (PREFIX_0FF0) },
2227 { "psllw", { MX, EM } },
2228 { "pslld", { MX, EM } },
2229 { "psllq", { MX, EM } },
2230 { "pmuludq", { MX, EM } },
2231 { "pmaddwd", { MX, EM } },
2232 { "psadbw", { MX, EM } },
2233 { PREFIX_TABLE (PREFIX_0FF7) },
2235 { "psubb", { MX, EM } },
2236 { "psubw", { MX, EM } },
2237 { "psubd", { MX, EM } },
2238 { "psubq", { MX, EM } },
2239 { "paddb", { MX, EM } },
2240 { "paddw", { MX, EM } },
2241 { "paddd", { MX, EM } },
2245 static const unsigned char onebyte_has_modrm[256] = {
2246 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2247 /* ------------------------------- */
2248 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2249 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2250 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2251 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2252 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2253 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2254 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2255 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2256 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2257 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2258 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2259 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2260 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2261 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2262 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2263 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
2264 /* ------------------------------- */
2265 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2268 static const unsigned char twobyte_has_modrm[256] = {
2269 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2270 /* ------------------------------- */
2271 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2272 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2273 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2274 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2275 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2276 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2277 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2278 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2279 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2280 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2281 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2282 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
2283 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2284 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2285 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2286 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
2287 /* ------------------------------- */
2288 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
2291 static char obuf[100];
2293 static char *mnemonicendp;
2294 static char scratchbuf[100];
2295 static unsigned char *start_codep;
2296 static unsigned char *insn_codep;
2297 static unsigned char *codep;
2298 static int last_lock_prefix;
2299 static int last_repz_prefix;
2300 static int last_repnz_prefix;
2301 static int last_data_prefix;
2302 static int last_addr_prefix;
2303 static int last_rex_prefix;
2304 static int last_seg_prefix;
2305 #define MAX_CODE_LENGTH 15
2306 /* We can up to 14 prefixes since the maximum instruction length is
2308 static int all_prefixes[MAX_CODE_LENGTH - 1];
2309 static disassemble_info *the_info;
2317 static unsigned char need_modrm;
2327 int register_specifier;
2333 static unsigned char need_vex;
2334 static unsigned char need_vex_reg;
2335 static unsigned char vex_w_done;
2343 /* If we are accessing mod/rm/reg without need_modrm set, then the
2344 values are stale. Hitting this abort likely indicates that you
2345 need to update onebyte_has_modrm or twobyte_has_modrm. */
2346 #define MODRM_CHECK if (!need_modrm) abort ()
2348 static const char **names64;
2349 static const char **names32;
2350 static const char **names16;
2351 static const char **names8;
2352 static const char **names8rex;
2353 static const char **names_seg;
2354 static const char *index64;
2355 static const char *index32;
2356 static const char **index16;
2358 static const char *intel_names64[] = {
2359 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
2360 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2362 static const char *intel_names32[] = {
2363 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
2364 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
2366 static const char *intel_names16[] = {
2367 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
2368 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
2370 static const char *intel_names8[] = {
2371 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
2373 static const char *intel_names8rex[] = {
2374 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
2375 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
2377 static const char *intel_names_seg[] = {
2378 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
2380 static const char *intel_index64 = "riz";
2381 static const char *intel_index32 = "eiz";
2382 static const char *intel_index16[] = {
2383 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2386 static const char *att_names64[] = {
2387 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2388 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
2390 static const char *att_names32[] = {
2391 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2392 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
2394 static const char *att_names16[] = {
2395 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2396 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
2398 static const char *att_names8[] = {
2399 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2401 static const char *att_names8rex[] = {
2402 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2403 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
2405 static const char *att_names_seg[] = {
2406 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2408 static const char *att_index64 = "%riz";
2409 static const char *att_index32 = "%eiz";
2410 static const char *att_index16[] = {
2411 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2414 static const char **names_mm;
2415 static const char *intel_names_mm[] = {
2416 "mm0", "mm1", "mm2", "mm3",
2417 "mm4", "mm5", "mm6", "mm7"
2419 static const char *att_names_mm[] = {
2420 "%mm0", "%mm1", "%mm2", "%mm3",
2421 "%mm4", "%mm5", "%mm6", "%mm7"
2424 static const char **names_xmm;
2425 static const char *intel_names_xmm[] = {
2426 "xmm0", "xmm1", "xmm2", "xmm3",
2427 "xmm4", "xmm5", "xmm6", "xmm7",
2428 "xmm8", "xmm9", "xmm10", "xmm11",
2429 "xmm12", "xmm13", "xmm14", "xmm15"
2431 static const char *att_names_xmm[] = {
2432 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2433 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2434 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2435 "%xmm12", "%xmm13", "%xmm14", "%xmm15"
2438 static const char **names_ymm;
2439 static const char *intel_names_ymm[] = {
2440 "ymm0", "ymm1", "ymm2", "ymm3",
2441 "ymm4", "ymm5", "ymm6", "ymm7",
2442 "ymm8", "ymm9", "ymm10", "ymm11",
2443 "ymm12", "ymm13", "ymm14", "ymm15"
2445 static const char *att_names_ymm[] = {
2446 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2447 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2448 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2449 "%ymm12", "%ymm13", "%ymm14", "%ymm15"
2452 static const struct dis386 reg_table[][8] = {
2455 { "addA", { Ebh1, Ib } },
2456 { "orA", { Ebh1, Ib } },
2457 { "adcA", { Ebh1, Ib } },
2458 { "sbbA", { Ebh1, Ib } },
2459 { "andA", { Ebh1, Ib } },
2460 { "subA", { Ebh1, Ib } },
2461 { "xorA", { Ebh1, Ib } },
2462 { "cmpA", { Eb, Ib } },
2466 { "addQ", { Evh1, Iv } },
2467 { "orQ", { Evh1, Iv } },
2468 { "adcQ", { Evh1, Iv } },
2469 { "sbbQ", { Evh1, Iv } },
2470 { "andQ", { Evh1, Iv } },
2471 { "subQ", { Evh1, Iv } },
2472 { "xorQ", { Evh1, Iv } },
2473 { "cmpQ", { Ev, Iv } },
2477 { "addQ", { Evh1, sIb } },
2478 { "orQ", { Evh1, sIb } },
2479 { "adcQ", { Evh1, sIb } },
2480 { "sbbQ", { Evh1, sIb } },
2481 { "andQ", { Evh1, sIb } },
2482 { "subQ", { Evh1, sIb } },
2483 { "xorQ", { Evh1, sIb } },
2484 { "cmpQ", { Ev, sIb } },
2488 { "popU", { stackEv } },
2489 { XOP_8F_TABLE (XOP_09) },
2493 { XOP_8F_TABLE (XOP_09) },
2497 { "rolA", { Eb, Ib } },
2498 { "rorA", { Eb, Ib } },
2499 { "rclA", { Eb, Ib } },
2500 { "rcrA", { Eb, Ib } },
2501 { "shlA", { Eb, Ib } },
2502 { "shrA", { Eb, Ib } },
2504 { "sarA", { Eb, Ib } },
2508 { "rolQ", { Ev, Ib } },
2509 { "rorQ", { Ev, Ib } },
2510 { "rclQ", { Ev, Ib } },
2511 { "rcrQ", { Ev, Ib } },
2512 { "shlQ", { Ev, Ib } },
2513 { "shrQ", { Ev, Ib } },
2515 { "sarQ", { Ev, Ib } },
2519 { "movA", { Ebh3, Ib } },
2526 { MOD_TABLE (MOD_C6_REG_7) },
2530 { "movQ", { Evh3, Iv } },
2537 { MOD_TABLE (MOD_C7_REG_7) },
2541 { "rolA", { Eb, I1 } },
2542 { "rorA", { Eb, I1 } },
2543 { "rclA", { Eb, I1 } },
2544 { "rcrA", { Eb, I1 } },
2545 { "shlA", { Eb, I1 } },
2546 { "shrA", { Eb, I1 } },
2548 { "sarA", { Eb, I1 } },
2552 { "rolQ", { Ev, I1 } },
2553 { "rorQ", { Ev, I1 } },
2554 { "rclQ", { Ev, I1 } },
2555 { "rcrQ", { Ev, I1 } },
2556 { "shlQ", { Ev, I1 } },
2557 { "shrQ", { Ev, I1 } },
2559 { "sarQ", { Ev, I1 } },
2563 { "rolA", { Eb, CL } },
2564 { "rorA", { Eb, CL } },
2565 { "rclA", { Eb, CL } },
2566 { "rcrA", { Eb, CL } },
2567 { "shlA", { Eb, CL } },
2568 { "shrA", { Eb, CL } },
2570 { "sarA", { Eb, CL } },
2574 { "rolQ", { Ev, CL } },
2575 { "rorQ", { Ev, CL } },
2576 { "rclQ", { Ev, CL } },
2577 { "rcrQ", { Ev, CL } },
2578 { "shlQ", { Ev, CL } },
2579 { "shrQ", { Ev, CL } },
2581 { "sarQ", { Ev, CL } },
2585 { "testA", { Eb, Ib } },
2587 { "notA", { Ebh1 } },
2588 { "negA", { Ebh1 } },
2589 { "mulA", { Eb } }, /* Don't print the implicit %al register, */
2590 { "imulA", { Eb } }, /* to distinguish these opcodes from other */
2591 { "divA", { Eb } }, /* mul/imul opcodes. Do the same for div */
2592 { "idivA", { Eb } }, /* and idiv for consistency. */
2596 { "testQ", { Ev, Iv } },
2598 { "notQ", { Evh1 } },
2599 { "negQ", { Evh1 } },
2600 { "mulQ", { Ev } }, /* Don't print the implicit register. */
2601 { "imulQ", { Ev } },
2603 { "idivQ", { Ev } },
2607 { "incA", { Ebh1 } },
2608 { "decA", { Ebh1 } },
2612 { "incQ", { Evh1 } },
2613 { "decQ", { Evh1 } },
2614 { "call{T|}", { indirEv } },
2615 { "Jcall{T|}", { indirEp } },
2616 { "jmp{T|}", { indirEv } },
2617 { "Jjmp{T|}", { indirEp } },
2618 { "pushU", { stackEv } },
2623 { "sldtD", { Sv } },
2634 { MOD_TABLE (MOD_0F01_REG_0) },
2635 { MOD_TABLE (MOD_0F01_REG_1) },
2636 { MOD_TABLE (MOD_0F01_REG_2) },
2637 { MOD_TABLE (MOD_0F01_REG_3) },
2638 { "smswD", { Sv } },
2641 { MOD_TABLE (MOD_0F01_REG_7) },
2645 { "prefetch", { Mb } },
2646 { "prefetchw", { Mb } },
2650 { MOD_TABLE (MOD_0F18_REG_0) },
2651 { MOD_TABLE (MOD_0F18_REG_1) },
2652 { MOD_TABLE (MOD_0F18_REG_2) },
2653 { MOD_TABLE (MOD_0F18_REG_3) },
2659 { MOD_TABLE (MOD_0F71_REG_2) },
2661 { MOD_TABLE (MOD_0F71_REG_4) },
2663 { MOD_TABLE (MOD_0F71_REG_6) },
2669 { MOD_TABLE (MOD_0F72_REG_2) },
2671 { MOD_TABLE (MOD_0F72_REG_4) },
2673 { MOD_TABLE (MOD_0F72_REG_6) },
2679 { MOD_TABLE (MOD_0F73_REG_2) },
2680 { MOD_TABLE (MOD_0F73_REG_3) },
2683 { MOD_TABLE (MOD_0F73_REG_6) },
2684 { MOD_TABLE (MOD_0F73_REG_7) },
2688 { "montmul", { { OP_0f07, 0 } } },
2689 { "xsha1", { { OP_0f07, 0 } } },
2690 { "xsha256", { { OP_0f07, 0 } } },
2694 { "xstore-rng", { { OP_0f07, 0 } } },
2695 { "xcrypt-ecb", { { OP_0f07, 0 } } },
2696 { "xcrypt-cbc", { { OP_0f07, 0 } } },
2697 { "xcrypt-ctr", { { OP_0f07, 0 } } },
2698 { "xcrypt-cfb", { { OP_0f07, 0 } } },
2699 { "xcrypt-ofb", { { OP_0f07, 0 } } },
2703 { MOD_TABLE (MOD_0FAE_REG_0) },
2704 { MOD_TABLE (MOD_0FAE_REG_1) },
2705 { MOD_TABLE (MOD_0FAE_REG_2) },
2706 { MOD_TABLE (MOD_0FAE_REG_3) },
2707 { MOD_TABLE (MOD_0FAE_REG_4) },
2708 { MOD_TABLE (MOD_0FAE_REG_5) },
2709 { MOD_TABLE (MOD_0FAE_REG_6) },
2710 { MOD_TABLE (MOD_0FAE_REG_7) },
2718 { "btQ", { Ev, Ib } },
2719 { "btsQ", { Evh1, Ib } },
2720 { "btrQ", { Evh1, Ib } },
2721 { "btcQ", { Evh1, Ib } },
2726 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
2731 { MOD_TABLE (MOD_0FC7_REG_6) },
2732 { MOD_TABLE (MOD_0FC7_REG_7) },
2738 { MOD_TABLE (MOD_VEX_0F71_REG_2) },
2740 { MOD_TABLE (MOD_VEX_0F71_REG_4) },
2742 { MOD_TABLE (MOD_VEX_0F71_REG_6) },
2748 { MOD_TABLE (MOD_VEX_0F72_REG_2) },
2750 { MOD_TABLE (MOD_VEX_0F72_REG_4) },
2752 { MOD_TABLE (MOD_VEX_0F72_REG_6) },
2758 { MOD_TABLE (MOD_VEX_0F73_REG_2) },
2759 { MOD_TABLE (MOD_VEX_0F73_REG_3) },
2762 { MOD_TABLE (MOD_VEX_0F73_REG_6) },
2763 { MOD_TABLE (MOD_VEX_0F73_REG_7) },
2769 { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
2770 { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
2772 /* REG_VEX_0F38F3 */
2775 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
2776 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
2777 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
2781 { "llwpcb", { { OP_LWPCB_E, 0 } } },
2782 { "slwpcb", { { OP_LWPCB_E, 0 } } },
2786 { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
2787 { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } },
2789 /* REG_XOP_TBM_01 */
2792 { "blcfill", { { OP_LWP_E, 0 }, Ev } },
2793 { "blsfill", { { OP_LWP_E, 0 }, Ev } },
2794 { "blcs", { { OP_LWP_E, 0 }, Ev } },
2795 { "tzmsk", { { OP_LWP_E, 0 }, Ev } },
2796 { "blcic", { { OP_LWP_E, 0 }, Ev } },
2797 { "blsic", { { OP_LWP_E, 0 }, Ev } },
2798 { "t1mskc", { { OP_LWP_E, 0 }, Ev } },
2800 /* REG_XOP_TBM_02 */
2803 { "blcmsk", { { OP_LWP_E, 0 }, Ev } },
2808 { "blci", { { OP_LWP_E, 0 }, Ev } },
2812 static const struct dis386 prefix_table[][4] = {
2815 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2816 { "pause", { XX } },
2817 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } } },
2822 { "movups", { XM, EXx } },
2823 { "movss", { XM, EXd } },
2824 { "movupd", { XM, EXx } },
2825 { "movsd", { XM, EXq } },
2830 { "movups", { EXxS, XM } },
2831 { "movss", { EXdS, XM } },
2832 { "movupd", { EXxS, XM } },
2833 { "movsd", { EXqS, XM } },
2838 { MOD_TABLE (MOD_0F12_PREFIX_0) },
2839 { "movsldup", { XM, EXx } },
2840 { "movlpd", { XM, EXq } },
2841 { "movddup", { XM, EXq } },
2846 { MOD_TABLE (MOD_0F16_PREFIX_0) },
2847 { "movshdup", { XM, EXx } },
2848 { "movhpd", { XM, EXq } },
2853 { "cvtpi2ps", { XM, EMCq } },
2854 { "cvtsi2ss%LQ", { XM, Ev } },
2855 { "cvtpi2pd", { XM, EMCq } },
2856 { "cvtsi2sd%LQ", { XM, Ev } },
2861 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
2862 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
2863 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
2864 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
2869 { "cvttps2pi", { MXC, EXq } },
2870 { "cvttss2siY", { Gv, EXd } },
2871 { "cvttpd2pi", { MXC, EXx } },
2872 { "cvttsd2siY", { Gv, EXq } },
2877 { "cvtps2pi", { MXC, EXq } },
2878 { "cvtss2siY", { Gv, EXd } },
2879 { "cvtpd2pi", { MXC, EXx } },
2880 { "cvtsd2siY", { Gv, EXq } },
2885 { "ucomiss",{ XM, EXd } },
2887 { "ucomisd",{ XM, EXq } },
2892 { "comiss", { XM, EXd } },
2894 { "comisd", { XM, EXq } },
2899 { "sqrtps", { XM, EXx } },
2900 { "sqrtss", { XM, EXd } },
2901 { "sqrtpd", { XM, EXx } },
2902 { "sqrtsd", { XM, EXq } },
2907 { "rsqrtps",{ XM, EXx } },
2908 { "rsqrtss",{ XM, EXd } },
2913 { "rcpps", { XM, EXx } },
2914 { "rcpss", { XM, EXd } },
2919 { "addps", { XM, EXx } },
2920 { "addss", { XM, EXd } },
2921 { "addpd", { XM, EXx } },
2922 { "addsd", { XM, EXq } },
2927 { "mulps", { XM, EXx } },
2928 { "mulss", { XM, EXd } },
2929 { "mulpd", { XM, EXx } },
2930 { "mulsd", { XM, EXq } },
2935 { "cvtps2pd", { XM, EXq } },
2936 { "cvtss2sd", { XM, EXd } },
2937 { "cvtpd2ps", { XM, EXx } },
2938 { "cvtsd2ss", { XM, EXq } },
2943 { "cvtdq2ps", { XM, EXx } },
2944 { "cvttps2dq", { XM, EXx } },
2945 { "cvtps2dq", { XM, EXx } },
2950 { "subps", { XM, EXx } },
2951 { "subss", { XM, EXd } },
2952 { "subpd", { XM, EXx } },
2953 { "subsd", { XM, EXq } },
2958 { "minps", { XM, EXx } },
2959 { "minss", { XM, EXd } },
2960 { "minpd", { XM, EXx } },
2961 { "minsd", { XM, EXq } },
2966 { "divps", { XM, EXx } },
2967 { "divss", { XM, EXd } },
2968 { "divpd", { XM, EXx } },
2969 { "divsd", { XM, EXq } },
2974 { "maxps", { XM, EXx } },
2975 { "maxss", { XM, EXd } },
2976 { "maxpd", { XM, EXx } },
2977 { "maxsd", { XM, EXq } },
2982 { "punpcklbw",{ MX, EMd } },
2984 { "punpcklbw",{ MX, EMx } },
2989 { "punpcklwd",{ MX, EMd } },
2991 { "punpcklwd",{ MX, EMx } },
2996 { "punpckldq",{ MX, EMd } },
2998 { "punpckldq",{ MX, EMx } },
3005 { "punpcklqdq", { XM, EXx } },
3012 { "punpckhqdq", { XM, EXx } },
3017 { "movq", { MX, EM } },
3018 { "movdqu", { XM, EXx } },
3019 { "movdqa", { XM, EXx } },
3024 { "pshufw", { MX, EM, Ib } },
3025 { "pshufhw",{ XM, EXx, Ib } },
3026 { "pshufd", { XM, EXx, Ib } },
3027 { "pshuflw",{ XM, EXx, Ib } },
3030 /* PREFIX_0F73_REG_3 */
3034 { "psrldq", { XS, Ib } },
3037 /* PREFIX_0F73_REG_7 */
3041 { "pslldq", { XS, Ib } },
3046 {"vmread", { Em, Gm } },
3048 {"extrq", { XS, Ib, Ib } },
3049 {"insertq", { XM, XS, Ib, Ib } },
3054 {"vmwrite", { Gm, Em } },
3056 {"extrq", { XM, XS } },
3057 {"insertq", { XM, XS } },
3064 { "haddpd", { XM, EXx } },
3065 { "haddps", { XM, EXx } },
3072 { "hsubpd", { XM, EXx } },
3073 { "hsubps", { XM, EXx } },
3078 { "movK", { Edq, MX } },
3079 { "movq", { XM, EXq } },
3080 { "movK", { Edq, XM } },
3085 { "movq", { EMS, MX } },
3086 { "movdqu", { EXxS, XM } },
3087 { "movdqa", { EXxS, XM } },
3090 /* PREFIX_0FAE_REG_0 */
3093 { "rdfsbase", { Ev } },
3096 /* PREFIX_0FAE_REG_1 */
3099 { "rdgsbase", { Ev } },
3102 /* PREFIX_0FAE_REG_2 */
3105 { "wrfsbase", { Ev } },
3108 /* PREFIX_0FAE_REG_3 */
3111 { "wrgsbase", { Ev } },
3117 { "popcntS", { Gv, Ev } },
3122 { "bsfS", { Gv, Ev } },
3123 { "tzcntS", { Gv, Ev } },
3124 { "bsfS", { Gv, Ev } },
3129 { "bsrS", { Gv, Ev } },
3130 { "lzcntS", { Gv, Ev } },
3131 { "bsrS", { Gv, Ev } },
3136 { "cmpps", { XM, EXx, CMP } },
3137 { "cmpss", { XM, EXd, CMP } },
3138 { "cmppd", { XM, EXx, CMP } },
3139 { "cmpsd", { XM, EXq, CMP } },
3144 { "movntiS", { Ma, Gv } },
3147 /* PREFIX_0FC7_REG_6 */
3149 { "vmptrld",{ Mq } },
3150 { "vmxon", { Mq } },
3151 { "vmclear",{ Mq } },
3158 { "addsubpd", { XM, EXx } },
3159 { "addsubps", { XM, EXx } },
3165 { "movq2dq",{ XM, MS } },
3166 { "movq", { EXqS, XM } },
3167 { "movdq2q",{ MX, XS } },
3173 { "cvtdq2pd", { XM, EXq } },
3174 { "cvttpd2dq", { XM, EXx } },
3175 { "cvtpd2dq", { XM, EXx } },
3180 { "movntq", { Mq, MX } },
3182 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
3190 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
3195 { "maskmovq", { MX, MS } },
3197 { "maskmovdqu", { XM, XS } },
3204 { "pblendvb", { XM, EXx, XMM0 } },
3211 { "blendvps", { XM, EXx, XMM0 } },
3218 { "blendvpd", { XM, EXx, XMM0 } },
3225 { "ptest", { XM, EXx } },
3232 { "pmovsxbw", { XM, EXq } },
3239 { "pmovsxbd", { XM, EXd } },
3246 { "pmovsxbq", { XM, EXw } },
3253 { "pmovsxwd", { XM, EXq } },
3260 { "pmovsxwq", { XM, EXd } },
3267 { "pmovsxdq", { XM, EXq } },
3274 { "pmuldq", { XM, EXx } },
3281 { "pcmpeqq", { XM, EXx } },
3288 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
3295 { "packusdw", { XM, EXx } },
3302 { "pmovzxbw", { XM, EXq } },
3309 { "pmovzxbd", { XM, EXd } },
3316 { "pmovzxbq", { XM, EXw } },
3323 { "pmovzxwd", { XM, EXq } },
3330 { "pmovzxwq", { XM, EXd } },
3337 { "pmovzxdq", { XM, EXq } },
3344 { "pcmpgtq", { XM, EXx } },
3351 { "pminsb", { XM, EXx } },
3358 { "pminsd", { XM, EXx } },
3365 { "pminuw", { XM, EXx } },
3372 { "pminud", { XM, EXx } },
3379 { "pmaxsb", { XM, EXx } },
3386 { "pmaxsd", { XM, EXx } },
3393 { "pmaxuw", { XM, EXx } },
3400 { "pmaxud", { XM, EXx } },
3407 { "pmulld", { XM, EXx } },
3414 { "phminposuw", { XM, EXx } },
3421 { "invept", { Gm, Mo } },
3428 { "invvpid", { Gm, Mo } },
3435 { "invpcid", { Gm, M } },
3442 { "aesimc", { XM, EXx } },
3449 { "aesenc", { XM, EXx } },
3456 { "aesenclast", { XM, EXx } },
3463 { "aesdec", { XM, EXx } },
3470 { "aesdeclast", { XM, EXx } },
3475 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3477 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } } },
3478 { "crc32", { Gdq, { CRC32_Fixup, b_mode } } },
3483 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3485 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
3486 { "crc32", { Gdq, { CRC32_Fixup, v_mode } } },
3492 { "adoxS", { Gdq, Edq} },
3493 { "adcxS", { Gdq, Edq} },
3501 { "roundps", { XM, EXx, Ib } },
3508 { "roundpd", { XM, EXx, Ib } },
3515 { "roundss", { XM, EXd, Ib } },
3522 { "roundsd", { XM, EXq, Ib } },
3529 { "blendps", { XM, EXx, Ib } },
3536 { "blendpd", { XM, EXx, Ib } },
3543 { "pblendw", { XM, EXx, Ib } },
3550 { "pextrb", { Edqb, XM, Ib } },
3557 { "pextrw", { Edqw, XM, Ib } },
3564 { "pextrK", { Edq, XM, Ib } },
3571 { "extractps", { Edqd, XM, Ib } },
3578 { "pinsrb", { XM, Edqb, Ib } },
3585 { "insertps", { XM, EXd, Ib } },
3592 { "pinsrK", { XM, Edq, Ib } },
3599 { "dpps", { XM, EXx, Ib } },
3606 { "dppd", { XM, EXx, Ib } },
3613 { "mpsadbw", { XM, EXx, Ib } },
3620 { "pclmulqdq", { XM, EXx, PCLMUL } },
3627 { "pcmpestrm", { XM, EXx, Ib } },
3634 { "pcmpestri", { XM, EXx, Ib } },
3641 { "pcmpistrm", { XM, EXx, Ib } },
3648 { "pcmpistri", { XM, EXx, Ib } },
3655 { "aeskeygenassist", { XM, EXx, Ib } },
3658 /* PREFIX_VEX_0F10 */
3660 { VEX_W_TABLE (VEX_W_0F10_P_0) },
3661 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
3662 { VEX_W_TABLE (VEX_W_0F10_P_2) },
3663 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
3666 /* PREFIX_VEX_0F11 */
3668 { VEX_W_TABLE (VEX_W_0F11_P_0) },
3669 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
3670 { VEX_W_TABLE (VEX_W_0F11_P_2) },
3671 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
3674 /* PREFIX_VEX_0F12 */
3676 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
3677 { VEX_W_TABLE (VEX_W_0F12_P_1) },
3678 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
3679 { VEX_W_TABLE (VEX_W_0F12_P_3) },
3682 /* PREFIX_VEX_0F16 */
3684 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
3685 { VEX_W_TABLE (VEX_W_0F16_P_1) },
3686 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
3689 /* PREFIX_VEX_0F2A */
3692 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
3694 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
3697 /* PREFIX_VEX_0F2C */
3700 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
3702 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
3705 /* PREFIX_VEX_0F2D */
3708 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
3710 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
3713 /* PREFIX_VEX_0F2E */
3715 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
3717 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
3720 /* PREFIX_VEX_0F2F */
3722 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
3724 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
3727 /* PREFIX_VEX_0F51 */
3729 { VEX_W_TABLE (VEX_W_0F51_P_0) },
3730 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
3731 { VEX_W_TABLE (VEX_W_0F51_P_2) },
3732 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
3735 /* PREFIX_VEX_0F52 */
3737 { VEX_W_TABLE (VEX_W_0F52_P_0) },
3738 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
3741 /* PREFIX_VEX_0F53 */
3743 { VEX_W_TABLE (VEX_W_0F53_P_0) },
3744 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
3747 /* PREFIX_VEX_0F58 */
3749 { VEX_W_TABLE (VEX_W_0F58_P_0) },
3750 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
3751 { VEX_W_TABLE (VEX_W_0F58_P_2) },
3752 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
3755 /* PREFIX_VEX_0F59 */
3757 { VEX_W_TABLE (VEX_W_0F59_P_0) },
3758 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
3759 { VEX_W_TABLE (VEX_W_0F59_P_2) },
3760 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
3763 /* PREFIX_VEX_0F5A */
3765 { VEX_W_TABLE (VEX_W_0F5A_P_0) },
3766 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
3767 { "vcvtpd2ps%XY", { XMM, EXx } },
3768 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
3771 /* PREFIX_VEX_0F5B */
3773 { VEX_W_TABLE (VEX_W_0F5B_P_0) },
3774 { VEX_W_TABLE (VEX_W_0F5B_P_1) },
3775 { VEX_W_TABLE (VEX_W_0F5B_P_2) },
3778 /* PREFIX_VEX_0F5C */
3780 { VEX_W_TABLE (VEX_W_0F5C_P_0) },
3781 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
3782 { VEX_W_TABLE (VEX_W_0F5C_P_2) },
3783 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
3786 /* PREFIX_VEX_0F5D */
3788 { VEX_W_TABLE (VEX_W_0F5D_P_0) },
3789 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
3790 { VEX_W_TABLE (VEX_W_0F5D_P_2) },
3791 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
3794 /* PREFIX_VEX_0F5E */
3796 { VEX_W_TABLE (VEX_W_0F5E_P_0) },
3797 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
3798 { VEX_W_TABLE (VEX_W_0F5E_P_2) },
3799 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
3802 /* PREFIX_VEX_0F5F */
3804 { VEX_W_TABLE (VEX_W_0F5F_P_0) },
3805 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
3806 { VEX_W_TABLE (VEX_W_0F5F_P_2) },
3807 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
3810 /* PREFIX_VEX_0F60 */
3814 { VEX_W_TABLE (VEX_W_0F60_P_2) },
3817 /* PREFIX_VEX_0F61 */
3821 { VEX_W_TABLE (VEX_W_0F61_P_2) },
3824 /* PREFIX_VEX_0F62 */
3828 { VEX_W_TABLE (VEX_W_0F62_P_2) },
3831 /* PREFIX_VEX_0F63 */
3835 { VEX_W_TABLE (VEX_W_0F63_P_2) },
3838 /* PREFIX_VEX_0F64 */
3842 { VEX_W_TABLE (VEX_W_0F64_P_2) },
3845 /* PREFIX_VEX_0F65 */
3849 { VEX_W_TABLE (VEX_W_0F65_P_2) },
3852 /* PREFIX_VEX_0F66 */
3856 { VEX_W_TABLE (VEX_W_0F66_P_2) },
3859 /* PREFIX_VEX_0F67 */
3863 { VEX_W_TABLE (VEX_W_0F67_P_2) },
3866 /* PREFIX_VEX_0F68 */
3870 { VEX_W_TABLE (VEX_W_0F68_P_2) },
3873 /* PREFIX_VEX_0F69 */
3877 { VEX_W_TABLE (VEX_W_0F69_P_2) },
3880 /* PREFIX_VEX_0F6A */
3884 { VEX_W_TABLE (VEX_W_0F6A_P_2) },
3887 /* PREFIX_VEX_0F6B */
3891 { VEX_W_TABLE (VEX_W_0F6B_P_2) },
3894 /* PREFIX_VEX_0F6C */
3898 { VEX_W_TABLE (VEX_W_0F6C_P_2) },
3901 /* PREFIX_VEX_0F6D */
3905 { VEX_W_TABLE (VEX_W_0F6D_P_2) },
3908 /* PREFIX_VEX_0F6E */
3912 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
3915 /* PREFIX_VEX_0F6F */
3918 { VEX_W_TABLE (VEX_W_0F6F_P_1) },
3919 { VEX_W_TABLE (VEX_W_0F6F_P_2) },
3922 /* PREFIX_VEX_0F70 */
3925 { VEX_W_TABLE (VEX_W_0F70_P_1) },
3926 { VEX_W_TABLE (VEX_W_0F70_P_2) },
3927 { VEX_W_TABLE (VEX_W_0F70_P_3) },
3930 /* PREFIX_VEX_0F71_REG_2 */
3934 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
3937 /* PREFIX_VEX_0F71_REG_4 */
3941 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
3944 /* PREFIX_VEX_0F71_REG_6 */
3948 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
3951 /* PREFIX_VEX_0F72_REG_2 */
3955 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
3958 /* PREFIX_VEX_0F72_REG_4 */
3962 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
3965 /* PREFIX_VEX_0F72_REG_6 */
3969 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
3972 /* PREFIX_VEX_0F73_REG_2 */
3976 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
3979 /* PREFIX_VEX_0F73_REG_3 */
3983 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
3986 /* PREFIX_VEX_0F73_REG_6 */
3990 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
3993 /* PREFIX_VEX_0F73_REG_7 */
3997 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
4000 /* PREFIX_VEX_0F74 */
4004 { VEX_W_TABLE (VEX_W_0F74_P_2) },
4007 /* PREFIX_VEX_0F75 */
4011 { VEX_W_TABLE (VEX_W_0F75_P_2) },
4014 /* PREFIX_VEX_0F76 */
4018 { VEX_W_TABLE (VEX_W_0F76_P_2) },
4021 /* PREFIX_VEX_0F77 */
4023 { VEX_W_TABLE (VEX_W_0F77_P_0) },
4026 /* PREFIX_VEX_0F7C */
4030 { VEX_W_TABLE (VEX_W_0F7C_P_2) },
4031 { VEX_W_TABLE (VEX_W_0F7C_P_3) },
4034 /* PREFIX_VEX_0F7D */
4038 { VEX_W_TABLE (VEX_W_0F7D_P_2) },
4039 { VEX_W_TABLE (VEX_W_0F7D_P_3) },
4042 /* PREFIX_VEX_0F7E */
4045 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
4046 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
4049 /* PREFIX_VEX_0F7F */
4052 { VEX_W_TABLE (VEX_W_0F7F_P_1) },
4053 { VEX_W_TABLE (VEX_W_0F7F_P_2) },
4056 /* PREFIX_VEX_0FC2 */
4058 { VEX_W_TABLE (VEX_W_0FC2_P_0) },
4059 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
4060 { VEX_W_TABLE (VEX_W_0FC2_P_2) },
4061 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
4064 /* PREFIX_VEX_0FC4 */
4068 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
4071 /* PREFIX_VEX_0FC5 */
4075 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
4078 /* PREFIX_VEX_0FD0 */
4082 { VEX_W_TABLE (VEX_W_0FD0_P_2) },
4083 { VEX_W_TABLE (VEX_W_0FD0_P_3) },
4086 /* PREFIX_VEX_0FD1 */
4090 { VEX_W_TABLE (VEX_W_0FD1_P_2) },
4093 /* PREFIX_VEX_0FD2 */
4097 { VEX_W_TABLE (VEX_W_0FD2_P_2) },
4100 /* PREFIX_VEX_0FD3 */
4104 { VEX_W_TABLE (VEX_W_0FD3_P_2) },
4107 /* PREFIX_VEX_0FD4 */
4111 { VEX_W_TABLE (VEX_W_0FD4_P_2) },
4114 /* PREFIX_VEX_0FD5 */
4118 { VEX_W_TABLE (VEX_W_0FD5_P_2) },
4121 /* PREFIX_VEX_0FD6 */
4125 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
4128 /* PREFIX_VEX_0FD7 */
4132 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
4135 /* PREFIX_VEX_0FD8 */
4139 { VEX_W_TABLE (VEX_W_0FD8_P_2) },
4142 /* PREFIX_VEX_0FD9 */
4146 { VEX_W_TABLE (VEX_W_0FD9_P_2) },
4149 /* PREFIX_VEX_0FDA */
4153 { VEX_W_TABLE (VEX_W_0FDA_P_2) },
4156 /* PREFIX_VEX_0FDB */
4160 { VEX_W_TABLE (VEX_W_0FDB_P_2) },
4163 /* PREFIX_VEX_0FDC */
4167 { VEX_W_TABLE (VEX_W_0FDC_P_2) },
4170 /* PREFIX_VEX_0FDD */
4174 { VEX_W_TABLE (VEX_W_0FDD_P_2) },
4177 /* PREFIX_VEX_0FDE */
4181 { VEX_W_TABLE (VEX_W_0FDE_P_2) },
4184 /* PREFIX_VEX_0FDF */
4188 { VEX_W_TABLE (VEX_W_0FDF_P_2) },
4191 /* PREFIX_VEX_0FE0 */
4195 { VEX_W_TABLE (VEX_W_0FE0_P_2) },
4198 /* PREFIX_VEX_0FE1 */
4202 { VEX_W_TABLE (VEX_W_0FE1_P_2) },
4205 /* PREFIX_VEX_0FE2 */
4209 { VEX_W_TABLE (VEX_W_0FE2_P_2) },
4212 /* PREFIX_VEX_0FE3 */
4216 { VEX_W_TABLE (VEX_W_0FE3_P_2) },
4219 /* PREFIX_VEX_0FE4 */
4223 { VEX_W_TABLE (VEX_W_0FE4_P_2) },
4226 /* PREFIX_VEX_0FE5 */
4230 { VEX_W_TABLE (VEX_W_0FE5_P_2) },
4233 /* PREFIX_VEX_0FE6 */
4236 { VEX_W_TABLE (VEX_W_0FE6_P_1) },
4237 { VEX_W_TABLE (VEX_W_0FE6_P_2) },
4238 { VEX_W_TABLE (VEX_W_0FE6_P_3) },
4241 /* PREFIX_VEX_0FE7 */
4245 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
4248 /* PREFIX_VEX_0FE8 */
4252 { VEX_W_TABLE (VEX_W_0FE8_P_2) },
4255 /* PREFIX_VEX_0FE9 */
4259 { VEX_W_TABLE (VEX_W_0FE9_P_2) },
4262 /* PREFIX_VEX_0FEA */
4266 { VEX_W_TABLE (VEX_W_0FEA_P_2) },
4269 /* PREFIX_VEX_0FEB */
4273 { VEX_W_TABLE (VEX_W_0FEB_P_2) },
4276 /* PREFIX_VEX_0FEC */
4280 { VEX_W_TABLE (VEX_W_0FEC_P_2) },
4283 /* PREFIX_VEX_0FED */
4287 { VEX_W_TABLE (VEX_W_0FED_P_2) },
4290 /* PREFIX_VEX_0FEE */
4294 { VEX_W_TABLE (VEX_W_0FEE_P_2) },
4297 /* PREFIX_VEX_0FEF */
4301 { VEX_W_TABLE (VEX_W_0FEF_P_2) },
4304 /* PREFIX_VEX_0FF0 */
4309 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
4312 /* PREFIX_VEX_0FF1 */
4316 { VEX_W_TABLE (VEX_W_0FF1_P_2) },
4319 /* PREFIX_VEX_0FF2 */
4323 { VEX_W_TABLE (VEX_W_0FF2_P_2) },
4326 /* PREFIX_VEX_0FF3 */
4330 { VEX_W_TABLE (VEX_W_0FF3_P_2) },
4333 /* PREFIX_VEX_0FF4 */
4337 { VEX_W_TABLE (VEX_W_0FF4_P_2) },
4340 /* PREFIX_VEX_0FF5 */
4344 { VEX_W_TABLE (VEX_W_0FF5_P_2) },
4347 /* PREFIX_VEX_0FF6 */
4351 { VEX_W_TABLE (VEX_W_0FF6_P_2) },
4354 /* PREFIX_VEX_0FF7 */
4358 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
4361 /* PREFIX_VEX_0FF8 */
4365 { VEX_W_TABLE (VEX_W_0FF8_P_2) },
4368 /* PREFIX_VEX_0FF9 */
4372 { VEX_W_TABLE (VEX_W_0FF9_P_2) },
4375 /* PREFIX_VEX_0FFA */
4379 { VEX_W_TABLE (VEX_W_0FFA_P_2) },
4382 /* PREFIX_VEX_0FFB */
4386 { VEX_W_TABLE (VEX_W_0FFB_P_2) },
4389 /* PREFIX_VEX_0FFC */
4393 { VEX_W_TABLE (VEX_W_0FFC_P_2) },
4396 /* PREFIX_VEX_0FFD */
4400 { VEX_W_TABLE (VEX_W_0FFD_P_2) },
4403 /* PREFIX_VEX_0FFE */
4407 { VEX_W_TABLE (VEX_W_0FFE_P_2) },
4410 /* PREFIX_VEX_0F3800 */
4414 { VEX_W_TABLE (VEX_W_0F3800_P_2) },
4417 /* PREFIX_VEX_0F3801 */
4421 { VEX_W_TABLE (VEX_W_0F3801_P_2) },
4424 /* PREFIX_VEX_0F3802 */
4428 { VEX_W_TABLE (VEX_W_0F3802_P_2) },
4431 /* PREFIX_VEX_0F3803 */
4435 { VEX_W_TABLE (VEX_W_0F3803_P_2) },
4438 /* PREFIX_VEX_0F3804 */
4442 { VEX_W_TABLE (VEX_W_0F3804_P_2) },
4445 /* PREFIX_VEX_0F3805 */
4449 { VEX_W_TABLE (VEX_W_0F3805_P_2) },
4452 /* PREFIX_VEX_0F3806 */
4456 { VEX_W_TABLE (VEX_W_0F3806_P_2) },
4459 /* PREFIX_VEX_0F3807 */
4463 { VEX_W_TABLE (VEX_W_0F3807_P_2) },
4466 /* PREFIX_VEX_0F3808 */
4470 { VEX_W_TABLE (VEX_W_0F3808_P_2) },
4473 /* PREFIX_VEX_0F3809 */
4477 { VEX_W_TABLE (VEX_W_0F3809_P_2) },
4480 /* PREFIX_VEX_0F380A */
4484 { VEX_W_TABLE (VEX_W_0F380A_P_2) },
4487 /* PREFIX_VEX_0F380B */
4491 { VEX_W_TABLE (VEX_W_0F380B_P_2) },
4494 /* PREFIX_VEX_0F380C */
4498 { VEX_W_TABLE (VEX_W_0F380C_P_2) },
4501 /* PREFIX_VEX_0F380D */
4505 { VEX_W_TABLE (VEX_W_0F380D_P_2) },
4508 /* PREFIX_VEX_0F380E */
4512 { VEX_W_TABLE (VEX_W_0F380E_P_2) },
4515 /* PREFIX_VEX_0F380F */
4519 { VEX_W_TABLE (VEX_W_0F380F_P_2) },
4522 /* PREFIX_VEX_0F3813 */
4526 { "vcvtph2ps", { XM, EXxmmq } },
4529 /* PREFIX_VEX_0F3816 */
4533 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
4536 /* PREFIX_VEX_0F3817 */
4540 { VEX_W_TABLE (VEX_W_0F3817_P_2) },
4543 /* PREFIX_VEX_0F3818 */
4547 { VEX_W_TABLE (VEX_W_0F3818_P_2) },
4550 /* PREFIX_VEX_0F3819 */
4554 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
4557 /* PREFIX_VEX_0F381A */
4561 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
4564 /* PREFIX_VEX_0F381C */
4568 { VEX_W_TABLE (VEX_W_0F381C_P_2) },
4571 /* PREFIX_VEX_0F381D */
4575 { VEX_W_TABLE (VEX_W_0F381D_P_2) },
4578 /* PREFIX_VEX_0F381E */
4582 { VEX_W_TABLE (VEX_W_0F381E_P_2) },
4585 /* PREFIX_VEX_0F3820 */
4589 { VEX_W_TABLE (VEX_W_0F3820_P_2) },
4592 /* PREFIX_VEX_0F3821 */
4596 { VEX_W_TABLE (VEX_W_0F3821_P_2) },
4599 /* PREFIX_VEX_0F3822 */
4603 { VEX_W_TABLE (VEX_W_0F3822_P_2) },
4606 /* PREFIX_VEX_0F3823 */
4610 { VEX_W_TABLE (VEX_W_0F3823_P_2) },
4613 /* PREFIX_VEX_0F3824 */
4617 { VEX_W_TABLE (VEX_W_0F3824_P_2) },
4620 /* PREFIX_VEX_0F3825 */
4624 { VEX_W_TABLE (VEX_W_0F3825_P_2) },
4627 /* PREFIX_VEX_0F3828 */
4631 { VEX_W_TABLE (VEX_W_0F3828_P_2) },
4634 /* PREFIX_VEX_0F3829 */
4638 { VEX_W_TABLE (VEX_W_0F3829_P_2) },
4641 /* PREFIX_VEX_0F382A */
4645 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
4648 /* PREFIX_VEX_0F382B */
4652 { VEX_W_TABLE (VEX_W_0F382B_P_2) },
4655 /* PREFIX_VEX_0F382C */
4659 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
4662 /* PREFIX_VEX_0F382D */
4666 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
4669 /* PREFIX_VEX_0F382E */
4673 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
4676 /* PREFIX_VEX_0F382F */
4680 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
4683 /* PREFIX_VEX_0F3830 */
4687 { VEX_W_TABLE (VEX_W_0F3830_P_2) },
4690 /* PREFIX_VEX_0F3831 */
4694 { VEX_W_TABLE (VEX_W_0F3831_P_2) },
4697 /* PREFIX_VEX_0F3832 */
4701 { VEX_W_TABLE (VEX_W_0F3832_P_2) },
4704 /* PREFIX_VEX_0F3833 */
4708 { VEX_W_TABLE (VEX_W_0F3833_P_2) },
4711 /* PREFIX_VEX_0F3834 */
4715 { VEX_W_TABLE (VEX_W_0F3834_P_2) },
4718 /* PREFIX_VEX_0F3835 */
4722 { VEX_W_TABLE (VEX_W_0F3835_P_2) },
4725 /* PREFIX_VEX_0F3836 */
4729 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
4732 /* PREFIX_VEX_0F3837 */
4736 { VEX_W_TABLE (VEX_W_0F3837_P_2) },
4739 /* PREFIX_VEX_0F3838 */
4743 { VEX_W_TABLE (VEX_W_0F3838_P_2) },
4746 /* PREFIX_VEX_0F3839 */
4750 { VEX_W_TABLE (VEX_W_0F3839_P_2) },
4753 /* PREFIX_VEX_0F383A */
4757 { VEX_W_TABLE (VEX_W_0F383A_P_2) },
4760 /* PREFIX_VEX_0F383B */
4764 { VEX_W_TABLE (VEX_W_0F383B_P_2) },
4767 /* PREFIX_VEX_0F383C */
4771 { VEX_W_TABLE (VEX_W_0F383C_P_2) },
4774 /* PREFIX_VEX_0F383D */
4778 { VEX_W_TABLE (VEX_W_0F383D_P_2) },
4781 /* PREFIX_VEX_0F383E */
4785 { VEX_W_TABLE (VEX_W_0F383E_P_2) },
4788 /* PREFIX_VEX_0F383F */
4792 { VEX_W_TABLE (VEX_W_0F383F_P_2) },
4795 /* PREFIX_VEX_0F3840 */
4799 { VEX_W_TABLE (VEX_W_0F3840_P_2) },
4802 /* PREFIX_VEX_0F3841 */
4806 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
4809 /* PREFIX_VEX_0F3845 */
4813 { "vpsrlv%LW", { XM, Vex, EXx } },
4816 /* PREFIX_VEX_0F3846 */
4820 { VEX_W_TABLE (VEX_W_0F3846_P_2) },
4823 /* PREFIX_VEX_0F3847 */
4827 { "vpsllv%LW", { XM, Vex, EXx } },
4830 /* PREFIX_VEX_0F3858 */
4834 { VEX_W_TABLE (VEX_W_0F3858_P_2) },
4837 /* PREFIX_VEX_0F3859 */
4841 { VEX_W_TABLE (VEX_W_0F3859_P_2) },
4844 /* PREFIX_VEX_0F385A */
4848 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
4851 /* PREFIX_VEX_0F3878 */
4855 { VEX_W_TABLE (VEX_W_0F3878_P_2) },
4858 /* PREFIX_VEX_0F3879 */
4862 { VEX_W_TABLE (VEX_W_0F3879_P_2) },
4865 /* PREFIX_VEX_0F388C */
4869 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
4872 /* PREFIX_VEX_0F388E */
4876 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
4879 /* PREFIX_VEX_0F3890 */
4883 { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex } },
4886 /* PREFIX_VEX_0F3891 */
4890 { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
4893 /* PREFIX_VEX_0F3892 */
4897 { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex } },
4900 /* PREFIX_VEX_0F3893 */
4904 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ } },
4907 /* PREFIX_VEX_0F3896 */
4911 { "vfmaddsub132p%XW", { XM, Vex, EXx } },
4914 /* PREFIX_VEX_0F3897 */
4918 { "vfmsubadd132p%XW", { XM, Vex, EXx } },
4921 /* PREFIX_VEX_0F3898 */
4925 { "vfmadd132p%XW", { XM, Vex, EXx } },
4928 /* PREFIX_VEX_0F3899 */
4932 { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4935 /* PREFIX_VEX_0F389A */
4939 { "vfmsub132p%XW", { XM, Vex, EXx } },
4942 /* PREFIX_VEX_0F389B */
4946 { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4949 /* PREFIX_VEX_0F389C */
4953 { "vfnmadd132p%XW", { XM, Vex, EXx } },
4956 /* PREFIX_VEX_0F389D */
4960 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4963 /* PREFIX_VEX_0F389E */
4967 { "vfnmsub132p%XW", { XM, Vex, EXx } },
4970 /* PREFIX_VEX_0F389F */
4974 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
4977 /* PREFIX_VEX_0F38A6 */
4981 { "vfmaddsub213p%XW", { XM, Vex, EXx } },
4985 /* PREFIX_VEX_0F38A7 */
4989 { "vfmsubadd213p%XW", { XM, Vex, EXx } },
4992 /* PREFIX_VEX_0F38A8 */
4996 { "vfmadd213p%XW", { XM, Vex, EXx } },
4999 /* PREFIX_VEX_0F38A9 */
5003 { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5006 /* PREFIX_VEX_0F38AA */
5010 { "vfmsub213p%XW", { XM, Vex, EXx } },
5013 /* PREFIX_VEX_0F38AB */
5017 { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5020 /* PREFIX_VEX_0F38AC */
5024 { "vfnmadd213p%XW", { XM, Vex, EXx } },
5027 /* PREFIX_VEX_0F38AD */
5031 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5034 /* PREFIX_VEX_0F38AE */
5038 { "vfnmsub213p%XW", { XM, Vex, EXx } },
5041 /* PREFIX_VEX_0F38AF */
5045 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5048 /* PREFIX_VEX_0F38B6 */
5052 { "vfmaddsub231p%XW", { XM, Vex, EXx } },
5055 /* PREFIX_VEX_0F38B7 */
5059 { "vfmsubadd231p%XW", { XM, Vex, EXx } },
5062 /* PREFIX_VEX_0F38B8 */
5066 { "vfmadd231p%XW", { XM, Vex, EXx } },
5069 /* PREFIX_VEX_0F38B9 */
5073 { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5076 /* PREFIX_VEX_0F38BA */
5080 { "vfmsub231p%XW", { XM, Vex, EXx } },
5083 /* PREFIX_VEX_0F38BB */
5087 { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5090 /* PREFIX_VEX_0F38BC */
5094 { "vfnmadd231p%XW", { XM, Vex, EXx } },
5097 /* PREFIX_VEX_0F38BD */
5101 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5104 /* PREFIX_VEX_0F38BE */
5108 { "vfnmsub231p%XW", { XM, Vex, EXx } },
5111 /* PREFIX_VEX_0F38BF */
5115 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar } },
5118 /* PREFIX_VEX_0F38DB */
5122 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
5125 /* PREFIX_VEX_0F38DC */
5129 { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) },
5132 /* PREFIX_VEX_0F38DD */
5136 { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) },
5139 /* PREFIX_VEX_0F38DE */
5143 { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) },
5146 /* PREFIX_VEX_0F38DF */
5150 { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) },
5153 /* PREFIX_VEX_0F38F2 */
5155 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
5158 /* PREFIX_VEX_0F38F3_REG_1 */
5160 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
5163 /* PREFIX_VEX_0F38F3_REG_2 */
5165 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
5168 /* PREFIX_VEX_0F38F3_REG_3 */
5170 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
5173 /* PREFIX_VEX_0F38F5 */
5175 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
5176 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
5178 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
5181 /* PREFIX_VEX_0F38F6 */
5186 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
5189 /* PREFIX_VEX_0F38F7 */
5191 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
5192 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
5193 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
5194 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
5197 /* PREFIX_VEX_0F3A00 */
5201 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
5204 /* PREFIX_VEX_0F3A01 */
5208 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
5211 /* PREFIX_VEX_0F3A02 */
5215 { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
5218 /* PREFIX_VEX_0F3A04 */
5222 { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
5225 /* PREFIX_VEX_0F3A05 */
5229 { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
5232 /* PREFIX_VEX_0F3A06 */
5236 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
5239 /* PREFIX_VEX_0F3A08 */
5243 { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
5246 /* PREFIX_VEX_0F3A09 */
5250 { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
5253 /* PREFIX_VEX_0F3A0A */
5257 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
5260 /* PREFIX_VEX_0F3A0B */
5264 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
5267 /* PREFIX_VEX_0F3A0C */
5271 { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
5274 /* PREFIX_VEX_0F3A0D */
5278 { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
5281 /* PREFIX_VEX_0F3A0E */
5285 { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
5288 /* PREFIX_VEX_0F3A0F */
5292 { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
5295 /* PREFIX_VEX_0F3A14 */
5299 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
5302 /* PREFIX_VEX_0F3A15 */
5306 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
5309 /* PREFIX_VEX_0F3A16 */
5313 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
5316 /* PREFIX_VEX_0F3A17 */
5320 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
5323 /* PREFIX_VEX_0F3A18 */
5327 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
5330 /* PREFIX_VEX_0F3A19 */
5334 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
5337 /* PREFIX_VEX_0F3A1D */
5341 { "vcvtps2ph", { EXxmmq, XM, Ib } },
5344 /* PREFIX_VEX_0F3A20 */
5348 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
5351 /* PREFIX_VEX_0F3A21 */
5355 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
5358 /* PREFIX_VEX_0F3A22 */
5362 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
5365 /* PREFIX_VEX_0F3A38 */
5369 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
5372 /* PREFIX_VEX_0F3A39 */
5376 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
5379 /* PREFIX_VEX_0F3A40 */
5383 { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
5386 /* PREFIX_VEX_0F3A41 */
5390 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
5393 /* PREFIX_VEX_0F3A42 */
5397 { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
5400 /* PREFIX_VEX_0F3A44 */
5404 { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) },
5407 /* PREFIX_VEX_0F3A46 */
5411 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
5414 /* PREFIX_VEX_0F3A48 */
5418 { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
5421 /* PREFIX_VEX_0F3A49 */
5425 { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
5428 /* PREFIX_VEX_0F3A4A */
5432 { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
5435 /* PREFIX_VEX_0F3A4B */
5439 { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
5442 /* PREFIX_VEX_0F3A4C */
5446 { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
5449 /* PREFIX_VEX_0F3A5C */
5453 { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5456 /* PREFIX_VEX_0F3A5D */
5460 { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5463 /* PREFIX_VEX_0F3A5E */
5467 { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5470 /* PREFIX_VEX_0F3A5F */
5474 { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5477 /* PREFIX_VEX_0F3A60 */
5481 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
5485 /* PREFIX_VEX_0F3A61 */
5489 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
5492 /* PREFIX_VEX_0F3A62 */
5496 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
5499 /* PREFIX_VEX_0F3A63 */
5503 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
5506 /* PREFIX_VEX_0F3A68 */
5510 { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5513 /* PREFIX_VEX_0F3A69 */
5517 { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5520 /* PREFIX_VEX_0F3A6A */
5524 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
5527 /* PREFIX_VEX_0F3A6B */
5531 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
5534 /* PREFIX_VEX_0F3A6C */
5538 { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5541 /* PREFIX_VEX_0F3A6D */
5545 { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5548 /* PREFIX_VEX_0F3A6E */
5552 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
5555 /* PREFIX_VEX_0F3A6F */
5559 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
5562 /* PREFIX_VEX_0F3A78 */
5566 { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5569 /* PREFIX_VEX_0F3A79 */
5573 { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5576 /* PREFIX_VEX_0F3A7A */
5580 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
5583 /* PREFIX_VEX_0F3A7B */
5587 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
5590 /* PREFIX_VEX_0F3A7C */
5594 { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5598 /* PREFIX_VEX_0F3A7D */
5602 { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
5605 /* PREFIX_VEX_0F3A7E */
5609 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
5612 /* PREFIX_VEX_0F3A7F */
5616 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
5619 /* PREFIX_VEX_0F3ADF */
5623 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
5626 /* PREFIX_VEX_0F3AF0 */
5631 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
5635 static const struct dis386 x86_64_table[][2] = {
5638 { "pushP", { es } },
5648 { "pushP", { cs } },
5653 { "pushP", { ss } },
5663 { "pushP", { ds } },
5693 { "pushaP", { XX } },
5698 { "popaP", { XX } },
5703 { MOD_TABLE (MOD_62_32BIT) },
5708 { "arpl", { Ew, Gw } },
5709 { "movs{lq|xd}", { Gv, Ed } },
5714 { "ins{R|}", { Yzr, indirDX } },
5715 { "ins{G|}", { Yzr, indirDX } },
5720 { "outs{R|}", { indirDXr, Xz } },
5721 { "outs{G|}", { indirDXr, Xz } },
5726 { "Jcall{T|}", { Ap } },
5731 { MOD_TABLE (MOD_C4_32BIT) },
5732 { VEX_C4_TABLE (VEX_0F) },
5737 { MOD_TABLE (MOD_C5_32BIT) },
5738 { VEX_C5_TABLE (VEX_0F) },
5758 { "Jjmp{T|}", { Ap } },
5761 /* X86_64_0F01_REG_0 */
5763 { "sgdt{Q|IQ}", { M } },
5767 /* X86_64_0F01_REG_1 */
5769 { "sidt{Q|IQ}", { M } },
5773 /* X86_64_0F01_REG_2 */
5775 { "lgdt{Q|Q}", { M } },
5779 /* X86_64_0F01_REG_3 */
5781 { "lidt{Q|Q}", { M } },
5786 static const struct dis386 three_byte_table[][256] = {
5788 /* THREE_BYTE_0F38 */
5791 { "pshufb", { MX, EM } },
5792 { "phaddw", { MX, EM } },
5793 { "phaddd", { MX, EM } },
5794 { "phaddsw", { MX, EM } },
5795 { "pmaddubsw", { MX, EM } },
5796 { "phsubw", { MX, EM } },
5797 { "phsubd", { MX, EM } },
5798 { "phsubsw", { MX, EM } },
5800 { "psignb", { MX, EM } },
5801 { "psignw", { MX, EM } },
5802 { "psignd", { MX, EM } },
5803 { "pmulhrsw", { MX, EM } },
5809 { PREFIX_TABLE (PREFIX_0F3810) },
5813 { PREFIX_TABLE (PREFIX_0F3814) },
5814 { PREFIX_TABLE (PREFIX_0F3815) },
5816 { PREFIX_TABLE (PREFIX_0F3817) },
5822 { "pabsb", { MX, EM } },
5823 { "pabsw", { MX, EM } },
5824 { "pabsd", { MX, EM } },
5827 { PREFIX_TABLE (PREFIX_0F3820) },
5828 { PREFIX_TABLE (PREFIX_0F3821) },
5829 { PREFIX_TABLE (PREFIX_0F3822) },
5830 { PREFIX_TABLE (PREFIX_0F3823) },
5831 { PREFIX_TABLE (PREFIX_0F3824) },
5832 { PREFIX_TABLE (PREFIX_0F3825) },
5836 { PREFIX_TABLE (PREFIX_0F3828) },
5837 { PREFIX_TABLE (PREFIX_0F3829) },
5838 { PREFIX_TABLE (PREFIX_0F382A) },
5839 { PREFIX_TABLE (PREFIX_0F382B) },
5845 { PREFIX_TABLE (PREFIX_0F3830) },
5846 { PREFIX_TABLE (PREFIX_0F3831) },
5847 { PREFIX_TABLE (PREFIX_0F3832) },
5848 { PREFIX_TABLE (PREFIX_0F3833) },
5849 { PREFIX_TABLE (PREFIX_0F3834) },
5850 { PREFIX_TABLE (PREFIX_0F3835) },
5852 { PREFIX_TABLE (PREFIX_0F3837) },
5854 { PREFIX_TABLE (PREFIX_0F3838) },
5855 { PREFIX_TABLE (PREFIX_0F3839) },
5856 { PREFIX_TABLE (PREFIX_0F383A) },
5857 { PREFIX_TABLE (PREFIX_0F383B) },
5858 { PREFIX_TABLE (PREFIX_0F383C) },
5859 { PREFIX_TABLE (PREFIX_0F383D) },
5860 { PREFIX_TABLE (PREFIX_0F383E) },
5861 { PREFIX_TABLE (PREFIX_0F383F) },
5863 { PREFIX_TABLE (PREFIX_0F3840) },
5864 { PREFIX_TABLE (PREFIX_0F3841) },
5935 { PREFIX_TABLE (PREFIX_0F3880) },
5936 { PREFIX_TABLE (PREFIX_0F3881) },
5937 { PREFIX_TABLE (PREFIX_0F3882) },
6037 { PREFIX_TABLE (PREFIX_0F38DB) },
6038 { PREFIX_TABLE (PREFIX_0F38DC) },
6039 { PREFIX_TABLE (PREFIX_0F38DD) },
6040 { PREFIX_TABLE (PREFIX_0F38DE) },
6041 { PREFIX_TABLE (PREFIX_0F38DF) },
6061 { PREFIX_TABLE (PREFIX_0F38F0) },
6062 { PREFIX_TABLE (PREFIX_0F38F1) },
6067 { PREFIX_TABLE (PREFIX_0F38F6) },
6079 /* THREE_BYTE_0F3A */
6091 { PREFIX_TABLE (PREFIX_0F3A08) },
6092 { PREFIX_TABLE (PREFIX_0F3A09) },
6093 { PREFIX_TABLE (PREFIX_0F3A0A) },
6094 { PREFIX_TABLE (PREFIX_0F3A0B) },
6095 { PREFIX_TABLE (PREFIX_0F3A0C) },
6096 { PREFIX_TABLE (PREFIX_0F3A0D) },
6097 { PREFIX_TABLE (PREFIX_0F3A0E) },
6098 { "palignr", { MX, EM, Ib } },
6104 { PREFIX_TABLE (PREFIX_0F3A14) },
6105 { PREFIX_TABLE (PREFIX_0F3A15) },
6106 { PREFIX_TABLE (PREFIX_0F3A16) },
6107 { PREFIX_TABLE (PREFIX_0F3A17) },
6118 { PREFIX_TABLE (PREFIX_0F3A20) },
6119 { PREFIX_TABLE (PREFIX_0F3A21) },
6120 { PREFIX_TABLE (PREFIX_0F3A22) },
6154 { PREFIX_TABLE (PREFIX_0F3A40) },
6155 { PREFIX_TABLE (PREFIX_0F3A41) },
6156 { PREFIX_TABLE (PREFIX_0F3A42) },
6158 { PREFIX_TABLE (PREFIX_0F3A44) },
6190 { PREFIX_TABLE (PREFIX_0F3A60) },
6191 { PREFIX_TABLE (PREFIX_0F3A61) },
6192 { PREFIX_TABLE (PREFIX_0F3A62) },
6193 { PREFIX_TABLE (PREFIX_0F3A63) },
6332 { PREFIX_TABLE (PREFIX_0F3ADF) },
6371 /* THREE_BYTE_0F7A */
6410 { "ptest", { XX } },
6447 { "phaddbw", { XM, EXq } },
6448 { "phaddbd", { XM, EXq } },
6449 { "phaddbq", { XM, EXq } },
6452 { "phaddwd", { XM, EXq } },
6453 { "phaddwq", { XM, EXq } },
6458 { "phadddq", { XM, EXq } },
6465 { "phaddubw", { XM, EXq } },
6466 { "phaddubd", { XM, EXq } },
6467 { "phaddubq", { XM, EXq } },
6470 { "phadduwd", { XM, EXq } },
6471 { "phadduwq", { XM, EXq } },
6476 { "phaddudq", { XM, EXq } },
6483 { "phsubbw", { XM, EXq } },
6484 { "phsubbd", { XM, EXq } },
6485 { "phsubbq", { XM, EXq } },
6664 static const struct dis386 xop_table[][256] = {
6817 { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6818 { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6819 { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6827 { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6828 { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6835 { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6836 { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6837 { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6845 { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6846 { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6850 { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6851 { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6854 { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6872 { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 } },
6884 { "vprotb", { XM, Vex_2src_1, Ib } },
6885 { "vprotw", { XM, Vex_2src_1, Ib } },
6886 { "vprotd", { XM, Vex_2src_1, Ib } },
6887 { "vprotq", { XM, Vex_2src_1, Ib } },
6897 { "vpcomb", { XM, Vex128, EXx, Ib } },
6898 { "vpcomw", { XM, Vex128, EXx, Ib } },
6899 { "vpcomd", { XM, Vex128, EXx, Ib } },
6900 { "vpcomq", { XM, Vex128, EXx, Ib } },
6933 { "vpcomub", { XM, Vex128, EXx, Ib } },
6934 { "vpcomuw", { XM, Vex128, EXx, Ib } },
6935 { "vpcomud", { XM, Vex128, EXx, Ib } },
6936 { "vpcomuq", { XM, Vex128, EXx, Ib } },
6960 { REG_TABLE (REG_XOP_TBM_01) },
6961 { REG_TABLE (REG_XOP_TBM_02) },
6979 { REG_TABLE (REG_XOP_LWPCB) },
7103 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
7104 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
7105 { "vfrczss", { XM, EXd } },
7106 { "vfrczsd", { XM, EXq } },
7121 { "vprotb", { XM, Vex_2src_1, Vex_2src_2 } },
7122 { "vprotw", { XM, Vex_2src_1, Vex_2src_2 } },
7123 { "vprotd", { XM, Vex_2src_1, Vex_2src_2 } },
7124 { "vprotq", { XM, Vex_2src_1, Vex_2src_2 } },
7125 { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 } },
7126 { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 } },
7127 { "vpshld", { XM, Vex_2src_1, Vex_2src_2 } },
7128 { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 } },
7130 { "vpshab", { XM, Vex_2src_1, Vex_2src_2 } },
7131 { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 } },
7132 { "vpshad", { XM, Vex_2src_1, Vex_2src_2 } },
7133 { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 } },
7176 { "vphaddbw", { XM, EXxmm } },
7177 { "vphaddbd", { XM, EXxmm } },
7178 { "vphaddbq", { XM, EXxmm } },
7181 { "vphaddwd", { XM, EXxmm } },
7182 { "vphaddwq", { XM, EXxmm } },
7187 { "vphadddq", { XM, EXxmm } },
7194 { "vphaddubw", { XM, EXxmm } },
7195 { "vphaddubd", { XM, EXxmm } },
7196 { "vphaddubq", { XM, EXxmm } },
7199 { "vphadduwd", { XM, EXxmm } },
7200 { "vphadduwq", { XM, EXxmm } },
7205 { "vphaddudq", { XM, EXxmm } },
7212 { "vphsubbw", { XM, EXxmm } },
7213 { "vphsubwd", { XM, EXxmm } },
7214 { "vphsubdq", { XM, EXxmm } },
7268 { "bextr", { Gv, Ev, Iq } },
7270 { REG_TABLE (REG_XOP_LWP) },
7540 static const struct dis386 vex_table[][256] = {
7562 { PREFIX_TABLE (PREFIX_VEX_0F10) },
7563 { PREFIX_TABLE (PREFIX_VEX_0F11) },
7564 { PREFIX_TABLE (PREFIX_VEX_0F12) },
7565 { MOD_TABLE (MOD_VEX_0F13) },
7566 { VEX_W_TABLE (VEX_W_0F14) },
7567 { VEX_W_TABLE (VEX_W_0F15) },
7568 { PREFIX_TABLE (PREFIX_VEX_0F16) },
7569 { MOD_TABLE (MOD_VEX_0F17) },
7589 { VEX_W_TABLE (VEX_W_0F28) },
7590 { VEX_W_TABLE (VEX_W_0F29) },
7591 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
7592 { MOD_TABLE (MOD_VEX_0F2B) },
7593 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
7594 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
7595 { PREFIX_TABLE (PREFIX_VEX_0F2E) },
7596 { PREFIX_TABLE (PREFIX_VEX_0F2F) },
7634 { MOD_TABLE (MOD_VEX_0F50) },
7635 { PREFIX_TABLE (PREFIX_VEX_0F51) },
7636 { PREFIX_TABLE (PREFIX_VEX_0F52) },
7637 { PREFIX_TABLE (PREFIX_VEX_0F53) },
7638 { "vandpX", { XM, Vex, EXx } },
7639 { "vandnpX", { XM, Vex, EXx } },
7640 { "vorpX", { XM, Vex, EXx } },
7641 { "vxorpX", { XM, Vex, EXx } },
7643 { PREFIX_TABLE (PREFIX_VEX_0F58) },
7644 { PREFIX_TABLE (PREFIX_VEX_0F59) },
7645 { PREFIX_TABLE (PREFIX_VEX_0F5A) },
7646 { PREFIX_TABLE (PREFIX_VEX_0F5B) },
7647 { PREFIX_TABLE (PREFIX_VEX_0F5C) },
7648 { PREFIX_TABLE (PREFIX_VEX_0F5D) },
7649 { PREFIX_TABLE (PREFIX_VEX_0F5E) },
7650 { PREFIX_TABLE (PREFIX_VEX_0F5F) },
7652 { PREFIX_TABLE (PREFIX_VEX_0F60) },
7653 { PREFIX_TABLE (PREFIX_VEX_0F61) },
7654 { PREFIX_TABLE (PREFIX_VEX_0F62) },
7655 { PREFIX_TABLE (PREFIX_VEX_0F63) },
7656 { PREFIX_TABLE (PREFIX_VEX_0F64) },
7657 { PREFIX_TABLE (PREFIX_VEX_0F65) },
7658 { PREFIX_TABLE (PREFIX_VEX_0F66) },
7659 { PREFIX_TABLE (PREFIX_VEX_0F67) },
7661 { PREFIX_TABLE (PREFIX_VEX_0F68) },
7662 { PREFIX_TABLE (PREFIX_VEX_0F69) },
7663 { PREFIX_TABLE (PREFIX_VEX_0F6A) },
7664 { PREFIX_TABLE (PREFIX_VEX_0F6B) },
7665 { PREFIX_TABLE (PREFIX_VEX_0F6C) },
7666 { PREFIX_TABLE (PREFIX_VEX_0F6D) },
7667 { PREFIX_TABLE (PREFIX_VEX_0F6E) },
7668 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
7670 { PREFIX_TABLE (PREFIX_VEX_0F70) },
7671 { REG_TABLE (REG_VEX_0F71) },
7672 { REG_TABLE (REG_VEX_0F72) },
7673 { REG_TABLE (REG_VEX_0F73) },
7674 { PREFIX_TABLE (PREFIX_VEX_0F74) },
7675 { PREFIX_TABLE (PREFIX_VEX_0F75) },
7676 { PREFIX_TABLE (PREFIX_VEX_0F76) },
7677 { PREFIX_TABLE (PREFIX_VEX_0F77) },
7683 { PREFIX_TABLE (PREFIX_VEX_0F7C) },
7684 { PREFIX_TABLE (PREFIX_VEX_0F7D) },
7685 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
7686 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
7739 { REG_TABLE (REG_VEX_0FAE) },
7762 { PREFIX_TABLE (PREFIX_VEX_0FC2) },
7764 { PREFIX_TABLE (PREFIX_VEX_0FC4) },
7765 { PREFIX_TABLE (PREFIX_VEX_0FC5) },
7766 { "vshufpX", { XM, Vex, EXx, Ib } },
7778 { PREFIX_TABLE (PREFIX_VEX_0FD0) },
7779 { PREFIX_TABLE (PREFIX_VEX_0FD1) },
7780 { PREFIX_TABLE (PREFIX_VEX_0FD2) },
7781 { PREFIX_TABLE (PREFIX_VEX_0FD3) },
7782 { PREFIX_TABLE (PREFIX_VEX_0FD4) },
7783 { PREFIX_TABLE (PREFIX_VEX_0FD5) },
7784 { PREFIX_TABLE (PREFIX_VEX_0FD6) },
7785 { PREFIX_TABLE (PREFIX_VEX_0FD7) },
7787 { PREFIX_TABLE (PREFIX_VEX_0FD8) },
7788 { PREFIX_TABLE (PREFIX_VEX_0FD9) },
7789 { PREFIX_TABLE (PREFIX_VEX_0FDA) },
7790 { PREFIX_TABLE (PREFIX_VEX_0FDB) },
7791 { PREFIX_TABLE (PREFIX_VEX_0FDC) },
7792 { PREFIX_TABLE (PREFIX_VEX_0FDD) },
7793 { PREFIX_TABLE (PREFIX_VEX_0FDE) },
7794 { PREFIX_TABLE (PREFIX_VEX_0FDF) },
7796 { PREFIX_TABLE (PREFIX_VEX_0FE0) },
7797 { PREFIX_TABLE (PREFIX_VEX_0FE1) },
7798 { PREFIX_TABLE (PREFIX_VEX_0FE2) },
7799 { PREFIX_TABLE (PREFIX_VEX_0FE3) },
7800 { PREFIX_TABLE (PREFIX_VEX_0FE4) },
7801 { PREFIX_TABLE (PREFIX_VEX_0FE5) },
7802 { PREFIX_TABLE (PREFIX_VEX_0FE6) },
7803 { PREFIX_TABLE (PREFIX_VEX_0FE7) },
7805 { PREFIX_TABLE (PREFIX_VEX_0FE8) },
7806 { PREFIX_TABLE (PREFIX_VEX_0FE9) },
7807 { PREFIX_TABLE (PREFIX_VEX_0FEA) },
7808 { PREFIX_TABLE (PREFIX_VEX_0FEB) },
7809 { PREFIX_TABLE (PREFIX_VEX_0FEC) },
7810 { PREFIX_TABLE (PREFIX_VEX_0FED) },
7811 { PREFIX_TABLE (PREFIX_VEX_0FEE) },
7812 { PREFIX_TABLE (PREFIX_VEX_0FEF) },
7814 { PREFIX_TABLE (PREFIX_VEX_0FF0) },
7815 { PREFIX_TABLE (PREFIX_VEX_0FF1) },
7816 { PREFIX_TABLE (PREFIX_VEX_0FF2) },
7817 { PREFIX_TABLE (PREFIX_VEX_0FF3) },
7818 { PREFIX_TABLE (PREFIX_VEX_0FF4) },
7819 { PREFIX_TABLE (PREFIX_VEX_0FF5) },
7820 { PREFIX_TABLE (PREFIX_VEX_0FF6) },
7821 { PREFIX_TABLE (PREFIX_VEX_0FF7) },
7823 { PREFIX_TABLE (PREFIX_VEX_0FF8) },
7824 { PREFIX_TABLE (PREFIX_VEX_0FF9) },
7825 { PREFIX_TABLE (PREFIX_VEX_0FFA) },
7826 { PREFIX_TABLE (PREFIX_VEX_0FFB) },
7827 { PREFIX_TABLE (PREFIX_VEX_0FFC) },
7828 { PREFIX_TABLE (PREFIX_VEX_0FFD) },
7829 { PREFIX_TABLE (PREFIX_VEX_0FFE) },
7835 { PREFIX_TABLE (PREFIX_VEX_0F3800) },
7836 { PREFIX_TABLE (PREFIX_VEX_0F3801) },
7837 { PREFIX_TABLE (PREFIX_VEX_0F3802) },
7838 { PREFIX_TABLE (PREFIX_VEX_0F3803) },
7839 { PREFIX_TABLE (PREFIX_VEX_0F3804) },
7840 { PREFIX_TABLE (PREFIX_VEX_0F3805) },
7841 { PREFIX_TABLE (PREFIX_VEX_0F3806) },
7842 { PREFIX_TABLE (PREFIX_VEX_0F3807) },
7844 { PREFIX_TABLE (PREFIX_VEX_0F3808) },
7845 { PREFIX_TABLE (PREFIX_VEX_0F3809) },
7846 { PREFIX_TABLE (PREFIX_VEX_0F380A) },
7847 { PREFIX_TABLE (PREFIX_VEX_0F380B) },
7848 { PREFIX_TABLE (PREFIX_VEX_0F380C) },
7849 { PREFIX_TABLE (PREFIX_VEX_0F380D) },
7850 { PREFIX_TABLE (PREFIX_VEX_0F380E) },
7851 { PREFIX_TABLE (PREFIX_VEX_0F380F) },
7856 { PREFIX_TABLE (PREFIX_VEX_0F3813) },
7859 { PREFIX_TABLE (PREFIX_VEX_0F3816) },
7860 { PREFIX_TABLE (PREFIX_VEX_0F3817) },
7862 { PREFIX_TABLE (PREFIX_VEX_0F3818) },
7863 { PREFIX_TABLE (PREFIX_VEX_0F3819) },
7864 { PREFIX_TABLE (PREFIX_VEX_0F381A) },
7866 { PREFIX_TABLE (PREFIX_VEX_0F381C) },
7867 { PREFIX_TABLE (PREFIX_VEX_0F381D) },
7868 { PREFIX_TABLE (PREFIX_VEX_0F381E) },
7871 { PREFIX_TABLE (PREFIX_VEX_0F3820) },
7872 { PREFIX_TABLE (PREFIX_VEX_0F3821) },
7873 { PREFIX_TABLE (PREFIX_VEX_0F3822) },
7874 { PREFIX_TABLE (PREFIX_VEX_0F3823) },
7875 { PREFIX_TABLE (PREFIX_VEX_0F3824) },
7876 { PREFIX_TABLE (PREFIX_VEX_0F3825) },
7880 { PREFIX_TABLE (PREFIX_VEX_0F3828) },
7881 { PREFIX_TABLE (PREFIX_VEX_0F3829) },
7882 { PREFIX_TABLE (PREFIX_VEX_0F382A) },
7883 { PREFIX_TABLE (PREFIX_VEX_0F382B) },
7884 { PREFIX_TABLE (PREFIX_VEX_0F382C) },
7885 { PREFIX_TABLE (PREFIX_VEX_0F382D) },
7886 { PREFIX_TABLE (PREFIX_VEX_0F382E) },
7887 { PREFIX_TABLE (PREFIX_VEX_0F382F) },
7889 { PREFIX_TABLE (PREFIX_VEX_0F3830) },
7890 { PREFIX_TABLE (PREFIX_VEX_0F3831) },
7891 { PREFIX_TABLE (PREFIX_VEX_0F3832) },
7892 { PREFIX_TABLE (PREFIX_VEX_0F3833) },
7893 { PREFIX_TABLE (PREFIX_VEX_0F3834) },
7894 { PREFIX_TABLE (PREFIX_VEX_0F3835) },
7895 { PREFIX_TABLE (PREFIX_VEX_0F3836) },
7896 { PREFIX_TABLE (PREFIX_VEX_0F3837) },
7898 { PREFIX_TABLE (PREFIX_VEX_0F3838) },
7899 { PREFIX_TABLE (PREFIX_VEX_0F3839) },
7900 { PREFIX_TABLE (PREFIX_VEX_0F383A) },
7901 { PREFIX_TABLE (PREFIX_VEX_0F383B) },
7902 { PREFIX_TABLE (PREFIX_VEX_0F383C) },
7903 { PREFIX_TABLE (PREFIX_VEX_0F383D) },
7904 { PREFIX_TABLE (PREFIX_VEX_0F383E) },
7905 { PREFIX_TABLE (PREFIX_VEX_0F383F) },
7907 { PREFIX_TABLE (PREFIX_VEX_0F3840) },
7908 { PREFIX_TABLE (PREFIX_VEX_0F3841) },
7912 { PREFIX_TABLE (PREFIX_VEX_0F3845) },
7913 { PREFIX_TABLE (PREFIX_VEX_0F3846) },
7914 { PREFIX_TABLE (PREFIX_VEX_0F3847) },
7934 { PREFIX_TABLE (PREFIX_VEX_0F3858) },
7935 { PREFIX_TABLE (PREFIX_VEX_0F3859) },
7936 { PREFIX_TABLE (PREFIX_VEX_0F385A) },
7970 { PREFIX_TABLE (PREFIX_VEX_0F3878) },
7971 { PREFIX_TABLE (PREFIX_VEX_0F3879) },
7992 { PREFIX_TABLE (PREFIX_VEX_0F388C) },
7994 { PREFIX_TABLE (PREFIX_VEX_0F388E) },
7997 { PREFIX_TABLE (PREFIX_VEX_0F3890) },
7998 { PREFIX_TABLE (PREFIX_VEX_0F3891) },
7999 { PREFIX_TABLE (PREFIX_VEX_0F3892) },
8000 { PREFIX_TABLE (PREFIX_VEX_0F3893) },
8003 { PREFIX_TABLE (PREFIX_VEX_0F3896) },
8004 { PREFIX_TABLE (PREFIX_VEX_0F3897) },
8006 { PREFIX_TABLE (PREFIX_VEX_0F3898) },
8007 { PREFIX_TABLE (PREFIX_VEX_0F3899) },
8008 { PREFIX_TABLE (PREFIX_VEX_0F389A) },
8009 { PREFIX_TABLE (PREFIX_VEX_0F389B) },
8010 { PREFIX_TABLE (PREFIX_VEX_0F389C) },
8011 { PREFIX_TABLE (PREFIX_VEX_0F389D) },
8012 { PREFIX_TABLE (PREFIX_VEX_0F389E) },
8013 { PREFIX_TABLE (PREFIX_VEX_0F389F) },
8021 { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
8022 { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
8024 { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
8025 { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
8026 { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
8027 { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
8028 { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
8029 { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
8030 { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
8031 { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
8039 { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
8040 { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
8042 { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
8043 { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
8044 { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
8045 { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
8046 { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
8047 { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
8048 { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
8049 { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
8081 { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
8082 { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
8083 { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
8084 { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
8085 { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
8107 { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
8108 { REG_TABLE (REG_VEX_0F38F3) },
8110 { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
8111 { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
8112 { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
8126 { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
8127 { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
8128 { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
8130 { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
8131 { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
8132 { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
8135 { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
8136 { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
8137 { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
8138 { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
8139 { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
8140 { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
8141 { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
8142 { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
8148 { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
8149 { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
8150 { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
8151 { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
8153 { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
8154 { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
8158 { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
8162 { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
8163 { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
8164 { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
8189 { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
8190 { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
8198 { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
8199 { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
8200 { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
8202 { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
8204 { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
8207 { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
8208 { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
8209 { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
8210 { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
8211 { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
8229 { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
8230 { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
8231 { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
8232 { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
8234 { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
8235 { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
8236 { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
8237 { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
8243 { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
8244 { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
8245 { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
8246 { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
8247 { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
8248 { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
8249 { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
8250 { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
8261 { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
8262 { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
8263 { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
8264 { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
8265 { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
8266 { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
8267 { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
8268 { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
8376 { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
8396 { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
8416 static const struct dis386 vex_len_table[][2] = {
8417 /* VEX_LEN_0F10_P_1 */
8419 { VEX_W_TABLE (VEX_W_0F10_P_1) },
8420 { VEX_W_TABLE (VEX_W_0F10_P_1) },
8423 /* VEX_LEN_0F10_P_3 */
8425 { VEX_W_TABLE (VEX_W_0F10_P_3) },
8426 { VEX_W_TABLE (VEX_W_0F10_P_3) },
8429 /* VEX_LEN_0F11_P_1 */
8431 { VEX_W_TABLE (VEX_W_0F11_P_1) },
8432 { VEX_W_TABLE (VEX_W_0F11_P_1) },
8435 /* VEX_LEN_0F11_P_3 */
8437 { VEX_W_TABLE (VEX_W_0F11_P_3) },
8438 { VEX_W_TABLE (VEX_W_0F11_P_3) },
8441 /* VEX_LEN_0F12_P_0_M_0 */
8443 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
8446 /* VEX_LEN_0F12_P_0_M_1 */
8448 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
8451 /* VEX_LEN_0F12_P_2 */
8453 { VEX_W_TABLE (VEX_W_0F12_P_2) },
8456 /* VEX_LEN_0F13_M_0 */
8458 { VEX_W_TABLE (VEX_W_0F13_M_0) },
8461 /* VEX_LEN_0F16_P_0_M_0 */
8463 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
8466 /* VEX_LEN_0F16_P_0_M_1 */
8468 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
8471 /* VEX_LEN_0F16_P_2 */
8473 { VEX_W_TABLE (VEX_W_0F16_P_2) },
8476 /* VEX_LEN_0F17_M_0 */
8478 { VEX_W_TABLE (VEX_W_0F17_M_0) },
8481 /* VEX_LEN_0F2A_P_1 */
8483 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } },
8484 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev } },
8487 /* VEX_LEN_0F2A_P_3 */
8489 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } },
8490 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev } },
8493 /* VEX_LEN_0F2C_P_1 */
8495 { "vcvttss2siY", { Gv, EXdScalar } },
8496 { "vcvttss2siY", { Gv, EXdScalar } },
8499 /* VEX_LEN_0F2C_P_3 */
8501 { "vcvttsd2siY", { Gv, EXqScalar } },
8502 { "vcvttsd2siY", { Gv, EXqScalar } },
8505 /* VEX_LEN_0F2D_P_1 */
8507 { "vcvtss2siY", { Gv, EXdScalar } },
8508 { "vcvtss2siY", { Gv, EXdScalar } },
8511 /* VEX_LEN_0F2D_P_3 */
8513 { "vcvtsd2siY", { Gv, EXqScalar } },
8514 { "vcvtsd2siY", { Gv, EXqScalar } },
8517 /* VEX_LEN_0F2E_P_0 */
8519 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
8520 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
8523 /* VEX_LEN_0F2E_P_2 */
8525 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
8526 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
8529 /* VEX_LEN_0F2F_P_0 */
8531 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
8532 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
8535 /* VEX_LEN_0F2F_P_2 */
8537 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
8538 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
8541 /* VEX_LEN_0F51_P_1 */
8543 { VEX_W_TABLE (VEX_W_0F51_P_1) },
8544 { VEX_W_TABLE (VEX_W_0F51_P_1) },
8547 /* VEX_LEN_0F51_P_3 */
8549 { VEX_W_TABLE (VEX_W_0F51_P_3) },
8550 { VEX_W_TABLE (VEX_W_0F51_P_3) },
8553 /* VEX_LEN_0F52_P_1 */
8555 { VEX_W_TABLE (VEX_W_0F52_P_1) },
8556 { VEX_W_TABLE (VEX_W_0F52_P_1) },
8559 /* VEX_LEN_0F53_P_1 */
8561 { VEX_W_TABLE (VEX_W_0F53_P_1) },
8562 { VEX_W_TABLE (VEX_W_0F53_P_1) },
8565 /* VEX_LEN_0F58_P_1 */
8567 { VEX_W_TABLE (VEX_W_0F58_P_1) },
8568 { VEX_W_TABLE (VEX_W_0F58_P_1) },
8571 /* VEX_LEN_0F58_P_3 */
8573 { VEX_W_TABLE (VEX_W_0F58_P_3) },
8574 { VEX_W_TABLE (VEX_W_0F58_P_3) },
8577 /* VEX_LEN_0F59_P_1 */
8579 { VEX_W_TABLE (VEX_W_0F59_P_1) },
8580 { VEX_W_TABLE (VEX_W_0F59_P_1) },
8583 /* VEX_LEN_0F59_P_3 */
8585 { VEX_W_TABLE (VEX_W_0F59_P_3) },
8586 { VEX_W_TABLE (VEX_W_0F59_P_3) },
8589 /* VEX_LEN_0F5A_P_1 */
8591 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
8592 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
8595 /* VEX_LEN_0F5A_P_3 */
8597 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
8598 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
8601 /* VEX_LEN_0F5C_P_1 */
8603 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
8604 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
8607 /* VEX_LEN_0F5C_P_3 */
8609 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
8610 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
8613 /* VEX_LEN_0F5D_P_1 */
8615 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
8616 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
8619 /* VEX_LEN_0F5D_P_3 */
8621 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
8622 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
8625 /* VEX_LEN_0F5E_P_1 */
8627 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
8628 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
8631 /* VEX_LEN_0F5E_P_3 */
8633 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
8634 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
8637 /* VEX_LEN_0F5F_P_1 */
8639 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
8640 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
8643 /* VEX_LEN_0F5F_P_3 */
8645 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
8646 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
8649 /* VEX_LEN_0F6E_P_2 */
8651 { "vmovK", { XMScalar, Edq } },
8652 { "vmovK", { XMScalar, Edq } },
8655 /* VEX_LEN_0F7E_P_1 */
8657 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
8658 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
8661 /* VEX_LEN_0F7E_P_2 */
8663 { "vmovK", { Edq, XMScalar } },
8664 { "vmovK", { Edq, XMScalar } },
8667 /* VEX_LEN_0FAE_R_2_M_0 */
8669 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
8672 /* VEX_LEN_0FAE_R_3_M_0 */
8674 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
8677 /* VEX_LEN_0FC2_P_1 */
8679 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
8680 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
8683 /* VEX_LEN_0FC2_P_3 */
8685 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
8686 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
8689 /* VEX_LEN_0FC4_P_2 */
8691 { VEX_W_TABLE (VEX_W_0FC4_P_2) },
8694 /* VEX_LEN_0FC5_P_2 */
8696 { VEX_W_TABLE (VEX_W_0FC5_P_2) },
8699 /* VEX_LEN_0FD6_P_2 */
8701 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
8702 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
8705 /* VEX_LEN_0FF7_P_2 */
8707 { VEX_W_TABLE (VEX_W_0FF7_P_2) },
8710 /* VEX_LEN_0F3816_P_2 */
8713 { VEX_W_TABLE (VEX_W_0F3816_P_2) },
8716 /* VEX_LEN_0F3819_P_2 */
8719 { VEX_W_TABLE (VEX_W_0F3819_P_2) },
8722 /* VEX_LEN_0F381A_P_2_M_0 */
8725 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
8728 /* VEX_LEN_0F3836_P_2 */
8731 { VEX_W_TABLE (VEX_W_0F3836_P_2) },
8734 /* VEX_LEN_0F3841_P_2 */
8736 { VEX_W_TABLE (VEX_W_0F3841_P_2) },
8739 /* VEX_LEN_0F385A_P_2_M_0 */
8742 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
8745 /* VEX_LEN_0F38DB_P_2 */
8747 { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
8750 /* VEX_LEN_0F38DC_P_2 */
8752 { VEX_W_TABLE (VEX_W_0F38DC_P_2) },
8755 /* VEX_LEN_0F38DD_P_2 */
8757 { VEX_W_TABLE (VEX_W_0F38DD_P_2) },
8760 /* VEX_LEN_0F38DE_P_2 */
8762 { VEX_W_TABLE (VEX_W_0F38DE_P_2) },
8765 /* VEX_LEN_0F38DF_P_2 */
8767 { VEX_W_TABLE (VEX_W_0F38DF_P_2) },
8770 /* VEX_LEN_0F38F2_P_0 */
8772 { "andnS", { Gdq, VexGdq, Edq } },
8775 /* VEX_LEN_0F38F3_R_1_P_0 */
8777 { "blsrS", { VexGdq, Edq } },
8780 /* VEX_LEN_0F38F3_R_2_P_0 */
8782 { "blsmskS", { VexGdq, Edq } },
8785 /* VEX_LEN_0F38F3_R_3_P_0 */
8787 { "blsiS", { VexGdq, Edq } },
8790 /* VEX_LEN_0F38F5_P_0 */
8792 { "bzhiS", { Gdq, Edq, VexGdq } },
8795 /* VEX_LEN_0F38F5_P_1 */
8797 { "pextS", { Gdq, VexGdq, Edq } },
8800 /* VEX_LEN_0F38F5_P_3 */
8802 { "pdepS", { Gdq, VexGdq, Edq } },
8805 /* VEX_LEN_0F38F6_P_3 */
8807 { "mulxS", { Gdq, VexGdq, Edq } },
8810 /* VEX_LEN_0F38F7_P_0 */
8812 { "bextrS", { Gdq, Edq, VexGdq } },
8815 /* VEX_LEN_0F38F7_P_1 */
8817 { "sarxS", { Gdq, Edq, VexGdq } },
8820 /* VEX_LEN_0F38F7_P_2 */
8822 { "shlxS", { Gdq, Edq, VexGdq } },
8825 /* VEX_LEN_0F38F7_P_3 */
8827 { "shrxS", { Gdq, Edq, VexGdq } },
8830 /* VEX_LEN_0F3A00_P_2 */
8833 { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
8836 /* VEX_LEN_0F3A01_P_2 */
8839 { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
8842 /* VEX_LEN_0F3A06_P_2 */
8845 { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
8848 /* VEX_LEN_0F3A0A_P_2 */
8850 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
8851 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
8854 /* VEX_LEN_0F3A0B_P_2 */
8856 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
8857 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
8860 /* VEX_LEN_0F3A14_P_2 */
8862 { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
8865 /* VEX_LEN_0F3A15_P_2 */
8867 { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
8870 /* VEX_LEN_0F3A16_P_2 */
8872 { "vpextrK", { Edq, XM, Ib } },
8875 /* VEX_LEN_0F3A17_P_2 */
8877 { "vextractps", { Edqd, XM, Ib } },
8880 /* VEX_LEN_0F3A18_P_2 */
8883 { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
8886 /* VEX_LEN_0F3A19_P_2 */
8889 { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
8892 /* VEX_LEN_0F3A20_P_2 */
8894 { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
8897 /* VEX_LEN_0F3A21_P_2 */
8899 { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
8902 /* VEX_LEN_0F3A22_P_2 */
8904 { "vpinsrK", { XM, Vex128, Edq, Ib } },
8907 /* VEX_LEN_0F3A38_P_2 */
8910 { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
8913 /* VEX_LEN_0F3A39_P_2 */
8916 { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
8919 /* VEX_LEN_0F3A41_P_2 */
8921 { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
8924 /* VEX_LEN_0F3A44_P_2 */
8926 { VEX_W_TABLE (VEX_W_0F3A44_P_2) },
8929 /* VEX_LEN_0F3A46_P_2 */
8932 { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
8935 /* VEX_LEN_0F3A60_P_2 */
8937 { VEX_W_TABLE (VEX_W_0F3A60_P_2) },
8940 /* VEX_LEN_0F3A61_P_2 */
8942 { VEX_W_TABLE (VEX_W_0F3A61_P_2) },
8945 /* VEX_LEN_0F3A62_P_2 */
8947 { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
8950 /* VEX_LEN_0F3A63_P_2 */
8952 { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
8955 /* VEX_LEN_0F3A6A_P_2 */
8957 { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
8960 /* VEX_LEN_0F3A6B_P_2 */
8962 { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
8965 /* VEX_LEN_0F3A6E_P_2 */
8967 { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
8970 /* VEX_LEN_0F3A6F_P_2 */
8972 { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
8975 /* VEX_LEN_0F3A7A_P_2 */
8977 { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
8980 /* VEX_LEN_0F3A7B_P_2 */
8982 { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
8985 /* VEX_LEN_0F3A7E_P_2 */
8987 { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 } },
8990 /* VEX_LEN_0F3A7F_P_2 */
8992 { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 } },
8995 /* VEX_LEN_0F3ADF_P_2 */
8997 { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
9000 /* VEX_LEN_0F3AF0_P_3 */
9002 { "rorxS", { Gdq, Edq, Ib } },
9005 /* VEX_LEN_0FXOP_09_80 */
9007 { "vfrczps", { XM, EXxmm } },
9008 { "vfrczps", { XM, EXymmq } },
9011 /* VEX_LEN_0FXOP_09_81 */
9013 { "vfrczpd", { XM, EXxmm } },
9014 { "vfrczpd", { XM, EXymmq } },
9018 static const struct dis386 vex_w_table[][2] = {
9020 /* VEX_W_0F10_P_0 */
9021 { "vmovups", { XM, EXx } },
9024 /* VEX_W_0F10_P_1 */
9025 { "vmovss", { XMVexScalar, VexScalar, EXdScalar } },
9028 /* VEX_W_0F10_P_2 */
9029 { "vmovupd", { XM, EXx } },
9032 /* VEX_W_0F10_P_3 */
9033 { "vmovsd", { XMVexScalar, VexScalar, EXqScalar } },
9036 /* VEX_W_0F11_P_0 */
9037 { "vmovups", { EXxS, XM } },
9040 /* VEX_W_0F11_P_1 */
9041 { "vmovss", { EXdVexScalarS, VexScalar, XMScalar } },
9044 /* VEX_W_0F11_P_2 */
9045 { "vmovupd", { EXxS, XM } },
9048 /* VEX_W_0F11_P_3 */
9049 { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar } },
9052 /* VEX_W_0F12_P_0_M_0 */
9053 { "vmovlps", { XM, Vex128, EXq } },
9056 /* VEX_W_0F12_P_0_M_1 */
9057 { "vmovhlps", { XM, Vex128, EXq } },
9060 /* VEX_W_0F12_P_1 */
9061 { "vmovsldup", { XM, EXx } },
9064 /* VEX_W_0F12_P_2 */
9065 { "vmovlpd", { XM, Vex128, EXq } },
9068 /* VEX_W_0F12_P_3 */
9069 { "vmovddup", { XM, EXymmq } },
9072 /* VEX_W_0F13_M_0 */
9073 { "vmovlpX", { EXq, XM } },
9077 { "vunpcklpX", { XM, Vex, EXx } },
9081 { "vunpckhpX", { XM, Vex, EXx } },
9084 /* VEX_W_0F16_P_0_M_0 */
9085 { "vmovhps", { XM, Vex128, EXq } },
9088 /* VEX_W_0F16_P_0_M_1 */
9089 { "vmovlhps", { XM, Vex128, EXq } },
9092 /* VEX_W_0F16_P_1 */
9093 { "vmovshdup", { XM, EXx } },
9096 /* VEX_W_0F16_P_2 */
9097 { "vmovhpd", { XM, Vex128, EXq } },
9100 /* VEX_W_0F17_M_0 */
9101 { "vmovhpX", { EXq, XM } },
9105 { "vmovapX", { XM, EXx } },
9109 { "vmovapX", { EXxS, XM } },
9112 /* VEX_W_0F2B_M_0 */
9113 { "vmovntpX", { Mx, XM } },
9116 /* VEX_W_0F2E_P_0 */
9117 { "vucomiss", { XMScalar, EXdScalar } },
9120 /* VEX_W_0F2E_P_2 */
9121 { "vucomisd", { XMScalar, EXqScalar } },
9124 /* VEX_W_0F2F_P_0 */
9125 { "vcomiss", { XMScalar, EXdScalar } },
9128 /* VEX_W_0F2F_P_2 */
9129 { "vcomisd", { XMScalar, EXqScalar } },
9132 /* VEX_W_0F50_M_0 */
9133 { "vmovmskpX", { Gdq, XS } },
9136 /* VEX_W_0F51_P_0 */
9137 { "vsqrtps", { XM, EXx } },
9140 /* VEX_W_0F51_P_1 */
9141 { "vsqrtss", { XMScalar, VexScalar, EXdScalar } },
9144 /* VEX_W_0F51_P_2 */
9145 { "vsqrtpd", { XM, EXx } },
9148 /* VEX_W_0F51_P_3 */
9149 { "vsqrtsd", { XMScalar, VexScalar, EXqScalar } },
9152 /* VEX_W_0F52_P_0 */
9153 { "vrsqrtps", { XM, EXx } },
9156 /* VEX_W_0F52_P_1 */
9157 { "vrsqrtss", { XMScalar, VexScalar, EXdScalar } },
9160 /* VEX_W_0F53_P_0 */
9161 { "vrcpps", { XM, EXx } },
9164 /* VEX_W_0F53_P_1 */
9165 { "vrcpss", { XMScalar, VexScalar, EXdScalar } },
9168 /* VEX_W_0F58_P_0 */
9169 { "vaddps", { XM, Vex, EXx } },
9172 /* VEX_W_0F58_P_1 */
9173 { "vaddss", { XMScalar, VexScalar, EXdScalar } },
9176 /* VEX_W_0F58_P_2 */
9177 { "vaddpd", { XM, Vex, EXx } },
9180 /* VEX_W_0F58_P_3 */
9181 { "vaddsd", { XMScalar, VexScalar, EXqScalar } },
9184 /* VEX_W_0F59_P_0 */
9185 { "vmulps", { XM, Vex, EXx } },
9188 /* VEX_W_0F59_P_1 */
9189 { "vmulss", { XMScalar, VexScalar, EXdScalar } },
9192 /* VEX_W_0F59_P_2 */
9193 { "vmulpd", { XM, Vex, EXx } },
9196 /* VEX_W_0F59_P_3 */
9197 { "vmulsd", { XMScalar, VexScalar, EXqScalar } },
9200 /* VEX_W_0F5A_P_0 */
9201 { "vcvtps2pd", { XM, EXxmmq } },
9204 /* VEX_W_0F5A_P_1 */
9205 { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar } },
9208 /* VEX_W_0F5A_P_3 */
9209 { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar } },
9212 /* VEX_W_0F5B_P_0 */
9213 { "vcvtdq2ps", { XM, EXx } },
9216 /* VEX_W_0F5B_P_1 */
9217 { "vcvttps2dq", { XM, EXx } },
9220 /* VEX_W_0F5B_P_2 */
9221 { "vcvtps2dq", { XM, EXx } },
9224 /* VEX_W_0F5C_P_0 */
9225 { "vsubps", { XM, Vex, EXx } },
9228 /* VEX_W_0F5C_P_1 */
9229 { "vsubss", { XMScalar, VexScalar, EXdScalar } },
9232 /* VEX_W_0F5C_P_2 */
9233 { "vsubpd", { XM, Vex, EXx } },
9236 /* VEX_W_0F5C_P_3 */
9237 { "vsubsd", { XMScalar, VexScalar, EXqScalar } },
9240 /* VEX_W_0F5D_P_0 */
9241 { "vminps", { XM, Vex, EXx } },
9244 /* VEX_W_0F5D_P_1 */
9245 { "vminss", { XMScalar, VexScalar, EXdScalar } },
9248 /* VEX_W_0F5D_P_2 */
9249 { "vminpd", { XM, Vex, EXx } },
9252 /* VEX_W_0F5D_P_3 */
9253 { "vminsd", { XMScalar, VexScalar, EXqScalar } },
9256 /* VEX_W_0F5E_P_0 */
9257 { "vdivps", { XM, Vex, EXx } },
9260 /* VEX_W_0F5E_P_1 */
9261 { "vdivss", { XMScalar, VexScalar, EXdScalar } },
9264 /* VEX_W_0F5E_P_2 */
9265 { "vdivpd", { XM, Vex, EXx } },
9268 /* VEX_W_0F5E_P_3 */
9269 { "vdivsd", { XMScalar, VexScalar, EXqScalar } },
9272 /* VEX_W_0F5F_P_0 */
9273 { "vmaxps", { XM, Vex, EXx } },
9276 /* VEX_W_0F5F_P_1 */
9277 { "vmaxss", { XMScalar, VexScalar, EXdScalar } },
9280 /* VEX_W_0F5F_P_2 */
9281 { "vmaxpd", { XM, Vex, EXx } },
9284 /* VEX_W_0F5F_P_3 */
9285 { "vmaxsd", { XMScalar, VexScalar, EXqScalar } },
9288 /* VEX_W_0F60_P_2 */
9289 { "vpunpcklbw", { XM, Vex, EXx } },
9292 /* VEX_W_0F61_P_2 */
9293 { "vpunpcklwd", { XM, Vex, EXx } },
9296 /* VEX_W_0F62_P_2 */
9297 { "vpunpckldq", { XM, Vex, EXx } },
9300 /* VEX_W_0F63_P_2 */
9301 { "vpacksswb", { XM, Vex, EXx } },
9304 /* VEX_W_0F64_P_2 */
9305 { "vpcmpgtb", { XM, Vex, EXx } },
9308 /* VEX_W_0F65_P_2 */
9309 { "vpcmpgtw", { XM, Vex, EXx } },
9312 /* VEX_W_0F66_P_2 */
9313 { "vpcmpgtd", { XM, Vex, EXx } },
9316 /* VEX_W_0F67_P_2 */
9317 { "vpackuswb", { XM, Vex, EXx } },
9320 /* VEX_W_0F68_P_2 */
9321 { "vpunpckhbw", { XM, Vex, EXx } },
9324 /* VEX_W_0F69_P_2 */
9325 { "vpunpckhwd", { XM, Vex, EXx } },
9328 /* VEX_W_0F6A_P_2 */
9329 { "vpunpckhdq", { XM, Vex, EXx } },
9332 /* VEX_W_0F6B_P_2 */
9333 { "vpackssdw", { XM, Vex, EXx } },
9336 /* VEX_W_0F6C_P_2 */
9337 { "vpunpcklqdq", { XM, Vex, EXx } },
9340 /* VEX_W_0F6D_P_2 */
9341 { "vpunpckhqdq", { XM, Vex, EXx } },
9344 /* VEX_W_0F6F_P_1 */
9345 { "vmovdqu", { XM, EXx } },
9348 /* VEX_W_0F6F_P_2 */
9349 { "vmovdqa", { XM, EXx } },
9352 /* VEX_W_0F70_P_1 */
9353 { "vpshufhw", { XM, EXx, Ib } },
9356 /* VEX_W_0F70_P_2 */
9357 { "vpshufd", { XM, EXx, Ib } },
9360 /* VEX_W_0F70_P_3 */
9361 { "vpshuflw", { XM, EXx, Ib } },
9364 /* VEX_W_0F71_R_2_P_2 */
9365 { "vpsrlw", { Vex, XS, Ib } },
9368 /* VEX_W_0F71_R_4_P_2 */
9369 { "vpsraw", { Vex, XS, Ib } },
9372 /* VEX_W_0F71_R_6_P_2 */
9373 { "vpsllw", { Vex, XS, Ib } },
9376 /* VEX_W_0F72_R_2_P_2 */
9377 { "vpsrld", { Vex, XS, Ib } },
9380 /* VEX_W_0F72_R_4_P_2 */
9381 { "vpsrad", { Vex, XS, Ib } },
9384 /* VEX_W_0F72_R_6_P_2 */
9385 { "vpslld", { Vex, XS, Ib } },
9388 /* VEX_W_0F73_R_2_P_2 */
9389 { "vpsrlq", { Vex, XS, Ib } },
9392 /* VEX_W_0F73_R_3_P_2 */
9393 { "vpsrldq", { Vex, XS, Ib } },
9396 /* VEX_W_0F73_R_6_P_2 */
9397 { "vpsllq", { Vex, XS, Ib } },
9400 /* VEX_W_0F73_R_7_P_2 */
9401 { "vpslldq", { Vex, XS, Ib } },
9404 /* VEX_W_0F74_P_2 */
9405 { "vpcmpeqb", { XM, Vex, EXx } },
9408 /* VEX_W_0F75_P_2 */
9409 { "vpcmpeqw", { XM, Vex, EXx } },
9412 /* VEX_W_0F76_P_2 */
9413 { "vpcmpeqd", { XM, Vex, EXx } },
9416 /* VEX_W_0F77_P_0 */
9420 /* VEX_W_0F7C_P_2 */
9421 { "vhaddpd", { XM, Vex, EXx } },
9424 /* VEX_W_0F7C_P_3 */
9425 { "vhaddps", { XM, Vex, EXx } },
9428 /* VEX_W_0F7D_P_2 */
9429 { "vhsubpd", { XM, Vex, EXx } },
9432 /* VEX_W_0F7D_P_3 */
9433 { "vhsubps", { XM, Vex, EXx } },
9436 /* VEX_W_0F7E_P_1 */
9437 { "vmovq", { XMScalar, EXqScalar } },
9440 /* VEX_W_0F7F_P_1 */
9441 { "vmovdqu", { EXxS, XM } },
9444 /* VEX_W_0F7F_P_2 */
9445 { "vmovdqa", { EXxS, XM } },
9448 /* VEX_W_0FAE_R_2_M_0 */
9449 { "vldmxcsr", { Md } },
9452 /* VEX_W_0FAE_R_3_M_0 */
9453 { "vstmxcsr", { Md } },
9456 /* VEX_W_0FC2_P_0 */
9457 { "vcmpps", { XM, Vex, EXx, VCMP } },
9460 /* VEX_W_0FC2_P_1 */
9461 { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP } },
9464 /* VEX_W_0FC2_P_2 */
9465 { "vcmppd", { XM, Vex, EXx, VCMP } },
9468 /* VEX_W_0FC2_P_3 */
9469 { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP } },
9472 /* VEX_W_0FC4_P_2 */
9473 { "vpinsrw", { XM, Vex128, Edqw, Ib } },
9476 /* VEX_W_0FC5_P_2 */
9477 { "vpextrw", { Gdq, XS, Ib } },
9480 /* VEX_W_0FD0_P_2 */
9481 { "vaddsubpd", { XM, Vex, EXx } },
9484 /* VEX_W_0FD0_P_3 */
9485 { "vaddsubps", { XM, Vex, EXx } },
9488 /* VEX_W_0FD1_P_2 */
9489 { "vpsrlw", { XM, Vex, EXxmm } },
9492 /* VEX_W_0FD2_P_2 */
9493 { "vpsrld", { XM, Vex, EXxmm } },
9496 /* VEX_W_0FD3_P_2 */
9497 { "vpsrlq", { XM, Vex, EXxmm } },
9500 /* VEX_W_0FD4_P_2 */
9501 { "vpaddq", { XM, Vex, EXx } },
9504 /* VEX_W_0FD5_P_2 */
9505 { "vpmullw", { XM, Vex, EXx } },
9508 /* VEX_W_0FD6_P_2 */
9509 { "vmovq", { EXqScalarS, XMScalar } },
9512 /* VEX_W_0FD7_P_2_M_1 */
9513 { "vpmovmskb", { Gdq, XS } },
9516 /* VEX_W_0FD8_P_2 */
9517 { "vpsubusb", { XM, Vex, EXx } },
9520 /* VEX_W_0FD9_P_2 */
9521 { "vpsubusw", { XM, Vex, EXx } },
9524 /* VEX_W_0FDA_P_2 */
9525 { "vpminub", { XM, Vex, EXx } },
9528 /* VEX_W_0FDB_P_2 */
9529 { "vpand", { XM, Vex, EXx } },
9532 /* VEX_W_0FDC_P_2 */
9533 { "vpaddusb", { XM, Vex, EXx } },
9536 /* VEX_W_0FDD_P_2 */
9537 { "vpaddusw", { XM, Vex, EXx } },
9540 /* VEX_W_0FDE_P_2 */
9541 { "vpmaxub", { XM, Vex, EXx } },
9544 /* VEX_W_0FDF_P_2 */
9545 { "vpandn", { XM, Vex, EXx } },
9548 /* VEX_W_0FE0_P_2 */
9549 { "vpavgb", { XM, Vex, EXx } },
9552 /* VEX_W_0FE1_P_2 */
9553 { "vpsraw", { XM, Vex, EXxmm } },
9556 /* VEX_W_0FE2_P_2 */
9557 { "vpsrad", { XM, Vex, EXxmm } },
9560 /* VEX_W_0FE3_P_2 */
9561 { "vpavgw", { XM, Vex, EXx } },
9564 /* VEX_W_0FE4_P_2 */
9565 { "vpmulhuw", { XM, Vex, EXx } },
9568 /* VEX_W_0FE5_P_2 */
9569 { "vpmulhw", { XM, Vex, EXx } },
9572 /* VEX_W_0FE6_P_1 */
9573 { "vcvtdq2pd", { XM, EXxmmq } },
9576 /* VEX_W_0FE6_P_2 */
9577 { "vcvttpd2dq%XY", { XMM, EXx } },
9580 /* VEX_W_0FE6_P_3 */
9581 { "vcvtpd2dq%XY", { XMM, EXx } },
9584 /* VEX_W_0FE7_P_2_M_0 */
9585 { "vmovntdq", { Mx, XM } },
9588 /* VEX_W_0FE8_P_2 */
9589 { "vpsubsb", { XM, Vex, EXx } },
9592 /* VEX_W_0FE9_P_2 */
9593 { "vpsubsw", { XM, Vex, EXx } },
9596 /* VEX_W_0FEA_P_2 */
9597 { "vpminsw", { XM, Vex, EXx } },
9600 /* VEX_W_0FEB_P_2 */
9601 { "vpor", { XM, Vex, EXx } },
9604 /* VEX_W_0FEC_P_2 */
9605 { "vpaddsb", { XM, Vex, EXx } },
9608 /* VEX_W_0FED_P_2 */
9609 { "vpaddsw", { XM, Vex, EXx } },
9612 /* VEX_W_0FEE_P_2 */
9613 { "vpmaxsw", { XM, Vex, EXx } },
9616 /* VEX_W_0FEF_P_2 */
9617 { "vpxor", { XM, Vex, EXx } },
9620 /* VEX_W_0FF0_P_3_M_0 */
9621 { "vlddqu", { XM, M } },
9624 /* VEX_W_0FF1_P_2 */
9625 { "vpsllw", { XM, Vex, EXxmm } },
9628 /* VEX_W_0FF2_P_2 */
9629 { "vpslld", { XM, Vex, EXxmm } },
9632 /* VEX_W_0FF3_P_2 */
9633 { "vpsllq", { XM, Vex, EXxmm } },
9636 /* VEX_W_0FF4_P_2 */
9637 { "vpmuludq", { XM, Vex, EXx } },
9640 /* VEX_W_0FF5_P_2 */
9641 { "vpmaddwd", { XM, Vex, EXx } },
9644 /* VEX_W_0FF6_P_2 */
9645 { "vpsadbw", { XM, Vex, EXx } },
9648 /* VEX_W_0FF7_P_2 */
9649 { "vmaskmovdqu", { XM, XS } },
9652 /* VEX_W_0FF8_P_2 */
9653 { "vpsubb", { XM, Vex, EXx } },
9656 /* VEX_W_0FF9_P_2 */
9657 { "vpsubw", { XM, Vex, EXx } },
9660 /* VEX_W_0FFA_P_2 */
9661 { "vpsubd", { XM, Vex, EXx } },
9664 /* VEX_W_0FFB_P_2 */
9665 { "vpsubq", { XM, Vex, EXx } },
9668 /* VEX_W_0FFC_P_2 */
9669 { "vpaddb", { XM, Vex, EXx } },
9672 /* VEX_W_0FFD_P_2 */
9673 { "vpaddw", { XM, Vex, EXx } },
9676 /* VEX_W_0FFE_P_2 */
9677 { "vpaddd", { XM, Vex, EXx } },
9680 /* VEX_W_0F3800_P_2 */
9681 { "vpshufb", { XM, Vex, EXx } },
9684 /* VEX_W_0F3801_P_2 */
9685 { "vphaddw", { XM, Vex, EXx } },
9688 /* VEX_W_0F3802_P_2 */
9689 { "vphaddd", { XM, Vex, EXx } },
9692 /* VEX_W_0F3803_P_2 */
9693 { "vphaddsw", { XM, Vex, EXx } },
9696 /* VEX_W_0F3804_P_2 */
9697 { "vpmaddubsw", { XM, Vex, EXx } },
9700 /* VEX_W_0F3805_P_2 */
9701 { "vphsubw", { XM, Vex, EXx } },
9704 /* VEX_W_0F3806_P_2 */
9705 { "vphsubd", { XM, Vex, EXx } },
9708 /* VEX_W_0F3807_P_2 */
9709 { "vphsubsw", { XM, Vex, EXx } },
9712 /* VEX_W_0F3808_P_2 */
9713 { "vpsignb", { XM, Vex, EXx } },
9716 /* VEX_W_0F3809_P_2 */
9717 { "vpsignw", { XM, Vex, EXx } },
9720 /* VEX_W_0F380A_P_2 */
9721 { "vpsignd", { XM, Vex, EXx } },
9724 /* VEX_W_0F380B_P_2 */
9725 { "vpmulhrsw", { XM, Vex, EXx } },
9728 /* VEX_W_0F380C_P_2 */
9729 { "vpermilps", { XM, Vex, EXx } },
9732 /* VEX_W_0F380D_P_2 */
9733 { "vpermilpd", { XM, Vex, EXx } },
9736 /* VEX_W_0F380E_P_2 */
9737 { "vtestps", { XM, EXx } },
9740 /* VEX_W_0F380F_P_2 */
9741 { "vtestpd", { XM, EXx } },
9744 /* VEX_W_0F3816_P_2 */
9745 { "vpermps", { XM, Vex, EXx } },
9748 /* VEX_W_0F3817_P_2 */
9749 { "vptest", { XM, EXx } },
9752 /* VEX_W_0F3818_P_2 */
9753 { "vbroadcastss", { XM, EXxmm_md } },
9756 /* VEX_W_0F3819_P_2 */
9757 { "vbroadcastsd", { XM, EXxmm_mq } },
9760 /* VEX_W_0F381A_P_2_M_0 */
9761 { "vbroadcastf128", { XM, Mxmm } },
9764 /* VEX_W_0F381C_P_2 */
9765 { "vpabsb", { XM, EXx } },
9768 /* VEX_W_0F381D_P_2 */
9769 { "vpabsw", { XM, EXx } },
9772 /* VEX_W_0F381E_P_2 */
9773 { "vpabsd", { XM, EXx } },
9776 /* VEX_W_0F3820_P_2 */
9777 { "vpmovsxbw", { XM, EXxmmq } },
9780 /* VEX_W_0F3821_P_2 */
9781 { "vpmovsxbd", { XM, EXxmmqd } },
9784 /* VEX_W_0F3822_P_2 */
9785 { "vpmovsxbq", { XM, EXxmmdw } },
9788 /* VEX_W_0F3823_P_2 */
9789 { "vpmovsxwd", { XM, EXxmmq } },
9792 /* VEX_W_0F3824_P_2 */
9793 { "vpmovsxwq", { XM, EXxmmqd } },
9796 /* VEX_W_0F3825_P_2 */
9797 { "vpmovsxdq", { XM, EXxmmq } },
9800 /* VEX_W_0F3828_P_2 */
9801 { "vpmuldq", { XM, Vex, EXx } },
9804 /* VEX_W_0F3829_P_2 */
9805 { "vpcmpeqq", { XM, Vex, EXx } },
9808 /* VEX_W_0F382A_P_2_M_0 */
9809 { "vmovntdqa", { XM, Mx } },
9812 /* VEX_W_0F382B_P_2 */
9813 { "vpackusdw", { XM, Vex, EXx } },
9816 /* VEX_W_0F382C_P_2_M_0 */
9817 { "vmaskmovps", { XM, Vex, Mx } },
9820 /* VEX_W_0F382D_P_2_M_0 */
9821 { "vmaskmovpd", { XM, Vex, Mx } },
9824 /* VEX_W_0F382E_P_2_M_0 */
9825 { "vmaskmovps", { Mx, Vex, XM } },
9828 /* VEX_W_0F382F_P_2_M_0 */
9829 { "vmaskmovpd", { Mx, Vex, XM } },
9832 /* VEX_W_0F3830_P_2 */
9833 { "vpmovzxbw", { XM, EXxmmq } },
9836 /* VEX_W_0F3831_P_2 */
9837 { "vpmovzxbd", { XM, EXxmmqd } },
9840 /* VEX_W_0F3832_P_2 */
9841 { "vpmovzxbq", { XM, EXxmmdw } },
9844 /* VEX_W_0F3833_P_2 */
9845 { "vpmovzxwd", { XM, EXxmmq } },
9848 /* VEX_W_0F3834_P_2 */
9849 { "vpmovzxwq", { XM, EXxmmqd } },
9852 /* VEX_W_0F3835_P_2 */
9853 { "vpmovzxdq", { XM, EXxmmq } },
9856 /* VEX_W_0F3836_P_2 */
9857 { "vpermd", { XM, Vex, EXx } },
9860 /* VEX_W_0F3837_P_2 */
9861 { "vpcmpgtq", { XM, Vex, EXx } },
9864 /* VEX_W_0F3838_P_2 */
9865 { "vpminsb", { XM, Vex, EXx } },
9868 /* VEX_W_0F3839_P_2 */
9869 { "vpminsd", { XM, Vex, EXx } },
9872 /* VEX_W_0F383A_P_2 */
9873 { "vpminuw", { XM, Vex, EXx } },
9876 /* VEX_W_0F383B_P_2 */
9877 { "vpminud", { XM, Vex, EXx } },
9880 /* VEX_W_0F383C_P_2 */
9881 { "vpmaxsb", { XM, Vex, EXx } },
9884 /* VEX_W_0F383D_P_2 */
9885 { "vpmaxsd", { XM, Vex, EXx } },
9888 /* VEX_W_0F383E_P_2 */
9889 { "vpmaxuw", { XM, Vex, EXx } },
9892 /* VEX_W_0F383F_P_2 */
9893 { "vpmaxud", { XM, Vex, EXx } },
9896 /* VEX_W_0F3840_P_2 */
9897 { "vpmulld", { XM, Vex, EXx } },
9900 /* VEX_W_0F3841_P_2 */
9901 { "vphminposuw", { XM, EXx } },
9904 /* VEX_W_0F3846_P_2 */
9905 { "vpsravd", { XM, Vex, EXx } },
9908 /* VEX_W_0F3858_P_2 */
9909 { "vpbroadcastd", { XM, EXxmm_md } },
9912 /* VEX_W_0F3859_P_2 */
9913 { "vpbroadcastq", { XM, EXxmm_mq } },
9916 /* VEX_W_0F385A_P_2_M_0 */
9917 { "vbroadcasti128", { XM, Mxmm } },
9920 /* VEX_W_0F3878_P_2 */
9921 { "vpbroadcastb", { XM, EXxmm_mb } },
9924 /* VEX_W_0F3879_P_2 */
9925 { "vpbroadcastw", { XM, EXxmm_mw } },
9928 /* VEX_W_0F38DB_P_2 */
9929 { "vaesimc", { XM, EXx } },
9932 /* VEX_W_0F38DC_P_2 */
9933 { "vaesenc", { XM, Vex128, EXx } },
9936 /* VEX_W_0F38DD_P_2 */
9937 { "vaesenclast", { XM, Vex128, EXx } },
9940 /* VEX_W_0F38DE_P_2 */
9941 { "vaesdec", { XM, Vex128, EXx } },
9944 /* VEX_W_0F38DF_P_2 */
9945 { "vaesdeclast", { XM, Vex128, EXx } },
9948 /* VEX_W_0F3A00_P_2 */
9950 { "vpermq", { XM, EXx, Ib } },
9953 /* VEX_W_0F3A01_P_2 */
9955 { "vpermpd", { XM, EXx, Ib } },
9958 /* VEX_W_0F3A02_P_2 */
9959 { "vpblendd", { XM, Vex, EXx, Ib } },
9962 /* VEX_W_0F3A04_P_2 */
9963 { "vpermilps", { XM, EXx, Ib } },
9966 /* VEX_W_0F3A05_P_2 */
9967 { "vpermilpd", { XM, EXx, Ib } },
9970 /* VEX_W_0F3A06_P_2 */
9971 { "vperm2f128", { XM, Vex256, EXx, Ib } },
9974 /* VEX_W_0F3A08_P_2 */
9975 { "vroundps", { XM, EXx, Ib } },
9978 /* VEX_W_0F3A09_P_2 */
9979 { "vroundpd", { XM, EXx, Ib } },
9982 /* VEX_W_0F3A0A_P_2 */
9983 { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib } },
9986 /* VEX_W_0F3A0B_P_2 */
9987 { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib } },
9990 /* VEX_W_0F3A0C_P_2 */
9991 { "vblendps", { XM, Vex, EXx, Ib } },
9994 /* VEX_W_0F3A0D_P_2 */
9995 { "vblendpd", { XM, Vex, EXx, Ib } },
9998 /* VEX_W_0F3A0E_P_2 */
9999 { "vpblendw", { XM, Vex, EXx, Ib } },
10002 /* VEX_W_0F3A0F_P_2 */
10003 { "vpalignr", { XM, Vex, EXx, Ib } },
10006 /* VEX_W_0F3A14_P_2 */
10007 { "vpextrb", { Edqb, XM, Ib } },
10010 /* VEX_W_0F3A15_P_2 */
10011 { "vpextrw", { Edqw, XM, Ib } },
10014 /* VEX_W_0F3A18_P_2 */
10015 { "vinsertf128", { XM, Vex256, EXxmm, Ib } },
10018 /* VEX_W_0F3A19_P_2 */
10019 { "vextractf128", { EXxmm, XM, Ib } },
10022 /* VEX_W_0F3A20_P_2 */
10023 { "vpinsrb", { XM, Vex128, Edqb, Ib } },
10026 /* VEX_W_0F3A21_P_2 */
10027 { "vinsertps", { XM, Vex128, EXd, Ib } },
10030 /* VEX_W_0F3A38_P_2 */
10031 { "vinserti128", { XM, Vex256, EXxmm, Ib } },
10034 /* VEX_W_0F3A39_P_2 */
10035 { "vextracti128", { EXxmm, XM, Ib } },
10038 /* VEX_W_0F3A40_P_2 */
10039 { "vdpps", { XM, Vex, EXx, Ib } },
10042 /* VEX_W_0F3A41_P_2 */
10043 { "vdppd", { XM, Vex128, EXx, Ib } },
10046 /* VEX_W_0F3A42_P_2 */
10047 { "vmpsadbw", { XM, Vex, EXx, Ib } },
10050 /* VEX_W_0F3A44_P_2 */
10051 { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL } },
10054 /* VEX_W_0F3A46_P_2 */
10055 { "vperm2i128", { XM, Vex256, EXx, Ib } },
10058 /* VEX_W_0F3A48_P_2 */
10059 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10060 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10063 /* VEX_W_0F3A49_P_2 */
10064 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10065 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW } },
10068 /* VEX_W_0F3A4A_P_2 */
10069 { "vblendvps", { XM, Vex, EXx, XMVexI4 } },
10072 /* VEX_W_0F3A4B_P_2 */
10073 { "vblendvpd", { XM, Vex, EXx, XMVexI4 } },
10076 /* VEX_W_0F3A4C_P_2 */
10077 { "vpblendvb", { XM, Vex, EXx, XMVexI4 } },
10080 /* VEX_W_0F3A60_P_2 */
10081 { "vpcmpestrm", { XM, EXx, Ib } },
10084 /* VEX_W_0F3A61_P_2 */
10085 { "vpcmpestri", { XM, EXx, Ib } },
10088 /* VEX_W_0F3A62_P_2 */
10089 { "vpcmpistrm", { XM, EXx, Ib } },
10092 /* VEX_W_0F3A63_P_2 */
10093 { "vpcmpistri", { XM, EXx, Ib } },
10096 /* VEX_W_0F3ADF_P_2 */
10097 { "vaeskeygenassist", { XM, EXx, Ib } },
10101 static const struct dis386 mod_table[][2] = {
10104 { "leaS", { Gv, M } },
10109 { RM_TABLE (RM_C6_REG_7) },
10114 { RM_TABLE (RM_C7_REG_7) },
10117 /* MOD_0F01_REG_0 */
10118 { X86_64_TABLE (X86_64_0F01_REG_0) },
10119 { RM_TABLE (RM_0F01_REG_0) },
10122 /* MOD_0F01_REG_1 */
10123 { X86_64_TABLE (X86_64_0F01_REG_1) },
10124 { RM_TABLE (RM_0F01_REG_1) },
10127 /* MOD_0F01_REG_2 */
10128 { X86_64_TABLE (X86_64_0F01_REG_2) },
10129 { RM_TABLE (RM_0F01_REG_2) },
10132 /* MOD_0F01_REG_3 */
10133 { X86_64_TABLE (X86_64_0F01_REG_3) },
10134 { RM_TABLE (RM_0F01_REG_3) },
10137 /* MOD_0F01_REG_7 */
10138 { "invlpg", { Mb } },
10139 { RM_TABLE (RM_0F01_REG_7) },
10142 /* MOD_0F12_PREFIX_0 */
10143 { "movlps", { XM, EXq } },
10144 { "movhlps", { XM, EXq } },
10148 { "movlpX", { EXq, XM } },
10151 /* MOD_0F16_PREFIX_0 */
10152 { "movhps", { XM, EXq } },
10153 { "movlhps", { XM, EXq } },
10157 { "movhpX", { EXq, XM } },
10160 /* MOD_0F18_REG_0 */
10161 { "prefetchnta", { Mb } },
10164 /* MOD_0F18_REG_1 */
10165 { "prefetcht0", { Mb } },
10168 /* MOD_0F18_REG_2 */
10169 { "prefetcht1", { Mb } },
10172 /* MOD_0F18_REG_3 */
10173 { "prefetcht2", { Mb } },
10178 { "movZ", { Rm, Cm } },
10183 { "movZ", { Rm, Dm } },
10188 { "movZ", { Cm, Rm } },
10193 { "movZ", { Dm, Rm } },
10198 { "movL", { Rd, Td } },
10203 { "movL", { Td, Rd } },
10206 /* MOD_0F2B_PREFIX_0 */
10207 {"movntps", { Mx, XM } },
10210 /* MOD_0F2B_PREFIX_1 */
10211 {"movntss", { Md, XM } },
10214 /* MOD_0F2B_PREFIX_2 */
10215 {"movntpd", { Mx, XM } },
10218 /* MOD_0F2B_PREFIX_3 */
10219 {"movntsd", { Mq, XM } },
10224 { "movmskpX", { Gdq, XS } },
10227 /* MOD_0F71_REG_2 */
10229 { "psrlw", { MS, Ib } },
10232 /* MOD_0F71_REG_4 */
10234 { "psraw", { MS, Ib } },
10237 /* MOD_0F71_REG_6 */
10239 { "psllw", { MS, Ib } },
10242 /* MOD_0F72_REG_2 */
10244 { "psrld", { MS, Ib } },
10247 /* MOD_0F72_REG_4 */
10249 { "psrad", { MS, Ib } },
10252 /* MOD_0F72_REG_6 */
10254 { "pslld", { MS, Ib } },
10257 /* MOD_0F73_REG_2 */
10259 { "psrlq", { MS, Ib } },
10262 /* MOD_0F73_REG_3 */
10264 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
10267 /* MOD_0F73_REG_6 */
10269 { "psllq", { MS, Ib } },
10272 /* MOD_0F73_REG_7 */
10274 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
10277 /* MOD_0FAE_REG_0 */
10278 { "fxsave", { FXSAVE } },
10279 { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
10282 /* MOD_0FAE_REG_1 */
10283 { "fxrstor", { FXSAVE } },
10284 { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
10287 /* MOD_0FAE_REG_2 */
10288 { "ldmxcsr", { Md } },
10289 { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
10292 /* MOD_0FAE_REG_3 */
10293 { "stmxcsr", { Md } },
10294 { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
10297 /* MOD_0FAE_REG_4 */
10298 { "xsave", { FXSAVE } },
10301 /* MOD_0FAE_REG_5 */
10302 { "xrstor", { FXSAVE } },
10303 { RM_TABLE (RM_0FAE_REG_5) },
10306 /* MOD_0FAE_REG_6 */
10307 { "xsaveopt", { FXSAVE } },
10308 { RM_TABLE (RM_0FAE_REG_6) },
10311 /* MOD_0FAE_REG_7 */
10312 { "clflush", { Mb } },
10313 { RM_TABLE (RM_0FAE_REG_7) },
10317 { "lssS", { Gv, Mp } },
10321 { "lfsS", { Gv, Mp } },
10325 { "lgsS", { Gv, Mp } },
10328 /* MOD_0FC7_REG_6 */
10329 { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
10330 { "rdrand", { Ev } },
10333 /* MOD_0FC7_REG_7 */
10334 { "vmptrst", { Mq } },
10335 { "rdseed", { Ev } },
10340 { "pmovmskb", { Gdq, MS } },
10343 /* MOD_0FE7_PREFIX_2 */
10344 { "movntdq", { Mx, XM } },
10347 /* MOD_0FF0_PREFIX_3 */
10348 { "lddqu", { XM, M } },
10351 /* MOD_0F382A_PREFIX_2 */
10352 { "movntdqa", { XM, Mx } },
10356 { "bound{S|}", { Gv, Ma } },
10360 { "lesS", { Gv, Mp } },
10361 { VEX_C4_TABLE (VEX_0F) },
10365 { "ldsS", { Gv, Mp } },
10366 { VEX_C5_TABLE (VEX_0F) },
10369 /* MOD_VEX_0F12_PREFIX_0 */
10370 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
10371 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
10375 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
10378 /* MOD_VEX_0F16_PREFIX_0 */
10379 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
10380 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
10384 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
10388 { VEX_W_TABLE (VEX_W_0F2B_M_0) },
10393 { VEX_W_TABLE (VEX_W_0F50_M_0) },
10396 /* MOD_VEX_0F71_REG_2 */
10398 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
10401 /* MOD_VEX_0F71_REG_4 */
10403 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
10406 /* MOD_VEX_0F71_REG_6 */
10408 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
10411 /* MOD_VEX_0F72_REG_2 */
10413 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
10416 /* MOD_VEX_0F72_REG_4 */
10418 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
10421 /* MOD_VEX_0F72_REG_6 */
10423 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
10426 /* MOD_VEX_0F73_REG_2 */
10428 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
10431 /* MOD_VEX_0F73_REG_3 */
10433 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
10436 /* MOD_VEX_0F73_REG_6 */
10438 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
10441 /* MOD_VEX_0F73_REG_7 */
10443 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
10446 /* MOD_VEX_0FAE_REG_2 */
10447 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
10450 /* MOD_VEX_0FAE_REG_3 */
10451 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
10454 /* MOD_VEX_0FD7_PREFIX_2 */
10456 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
10459 /* MOD_VEX_0FE7_PREFIX_2 */
10460 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
10463 /* MOD_VEX_0FF0_PREFIX_3 */
10464 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
10467 /* MOD_VEX_0F381A_PREFIX_2 */
10468 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
10471 /* MOD_VEX_0F382A_PREFIX_2 */
10472 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
10475 /* MOD_VEX_0F382C_PREFIX_2 */
10476 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
10479 /* MOD_VEX_0F382D_PREFIX_2 */
10480 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
10483 /* MOD_VEX_0F382E_PREFIX_2 */
10484 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
10487 /* MOD_VEX_0F382F_PREFIX_2 */
10488 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
10491 /* MOD_VEX_0F385A_PREFIX_2 */
10492 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
10495 /* MOD_VEX_0F388C_PREFIX_2 */
10496 { "vpmaskmov%LW", { XM, Vex, Mx } },
10499 /* MOD_VEX_0F388E_PREFIX_2 */
10500 { "vpmaskmov%LW", { Mx, Vex, XM } },
10504 static const struct dis386 rm_table[][8] = {
10507 { "xabort", { Skip_MODRM, Ib } },
10511 { "xbeginT", { Skip_MODRM, Jv } },
10514 /* RM_0F01_REG_0 */
10516 { "vmcall", { Skip_MODRM } },
10517 { "vmlaunch", { Skip_MODRM } },
10518 { "vmresume", { Skip_MODRM } },
10519 { "vmxoff", { Skip_MODRM } },
10522 /* RM_0F01_REG_1 */
10523 { "monitor", { { OP_Monitor, 0 } } },
10524 { "mwait", { { OP_Mwait, 0 } } },
10527 /* RM_0F01_REG_2 */
10528 { "xgetbv", { Skip_MODRM } },
10529 { "xsetbv", { Skip_MODRM } },
10532 { "vmfunc", { Skip_MODRM } },
10533 { "xend", { Skip_MODRM } },
10534 { "xtest", { Skip_MODRM } },
10538 /* RM_0F01_REG_3 */
10539 { "vmrun", { Skip_MODRM } },
10540 { "vmmcall", { Skip_MODRM } },
10541 { "vmload", { Skip_MODRM } },
10542 { "vmsave", { Skip_MODRM } },
10543 { "stgi", { Skip_MODRM } },
10544 { "clgi", { Skip_MODRM } },
10545 { "skinit", { Skip_MODRM } },
10546 { "invlpga", { Skip_MODRM } },
10549 /* RM_0F01_REG_7 */
10550 { "swapgs", { Skip_MODRM } },
10551 { "rdtscp", { Skip_MODRM } },
10554 /* RM_0FAE_REG_5 */
10555 { "lfence", { Skip_MODRM } },
10558 /* RM_0FAE_REG_6 */
10559 { "mfence", { Skip_MODRM } },
10562 /* RM_0FAE_REG_7 */
10563 { "sfence", { Skip_MODRM } },
10567 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
10569 /* We use the high bit to indicate different name for the same
10571 #define ADDR16_PREFIX (0x67 | 0x100)
10572 #define ADDR32_PREFIX (0x67 | 0x200)
10573 #define DATA16_PREFIX (0x66 | 0x100)
10574 #define DATA32_PREFIX (0x66 | 0x200)
10575 #define REP_PREFIX (0xf3 | 0x100)
10576 #define XACQUIRE_PREFIX (0xf2 | 0x200)
10577 #define XRELEASE_PREFIX (0xf3 | 0x400)
10582 int newrex, i, length;
10588 last_lock_prefix = -1;
10589 last_repz_prefix = -1;
10590 last_repnz_prefix = -1;
10591 last_data_prefix = -1;
10592 last_addr_prefix = -1;
10593 last_rex_prefix = -1;
10594 last_seg_prefix = -1;
10595 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
10596 all_prefixes[i] = 0;
10599 /* The maximum instruction length is 15bytes. */
10600 while (length < MAX_CODE_LENGTH - 1)
10602 FETCH_DATA (the_info, codep + 1);
10606 /* REX prefixes family. */
10623 if (address_mode == mode_64bit)
10627 last_rex_prefix = i;
10630 prefixes |= PREFIX_REPZ;
10631 last_repz_prefix = i;
10634 prefixes |= PREFIX_REPNZ;
10635 last_repnz_prefix = i;
10638 prefixes |= PREFIX_LOCK;
10639 last_lock_prefix = i;
10642 prefixes |= PREFIX_CS;
10643 last_seg_prefix = i;
10646 prefixes |= PREFIX_SS;
10647 last_seg_prefix = i;
10650 prefixes |= PREFIX_DS;
10651 last_seg_prefix = i;
10654 prefixes |= PREFIX_ES;
10655 last_seg_prefix = i;
10658 prefixes |= PREFIX_FS;
10659 last_seg_prefix = i;
10662 prefixes |= PREFIX_GS;
10663 last_seg_prefix = i;
10666 prefixes |= PREFIX_DATA;
10667 last_data_prefix = i;
10670 prefixes |= PREFIX_ADDR;
10671 last_addr_prefix = i;
10674 /* fwait is really an instruction. If there are prefixes
10675 before the fwait, they belong to the fwait, *not* to the
10676 following instruction. */
10677 if (prefixes || rex)
10679 prefixes |= PREFIX_FWAIT;
10683 prefixes = PREFIX_FWAIT;
10688 /* Rex is ignored when followed by another prefix. */
10694 if (*codep != FWAIT_OPCODE)
10695 all_prefixes[i++] = *codep;
10704 seg_prefix (int pref)
10725 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
10728 static const char *
10729 prefix_name (int pref, int sizeflag)
10731 static const char *rexes [16] =
10734 "rex.B", /* 0x41 */
10735 "rex.X", /* 0x42 */
10736 "rex.XB", /* 0x43 */
10737 "rex.R", /* 0x44 */
10738 "rex.RB", /* 0x45 */
10739 "rex.RX", /* 0x46 */
10740 "rex.RXB", /* 0x47 */
10741 "rex.W", /* 0x48 */
10742 "rex.WB", /* 0x49 */
10743 "rex.WX", /* 0x4a */
10744 "rex.WXB", /* 0x4b */
10745 "rex.WR", /* 0x4c */
10746 "rex.WRB", /* 0x4d */
10747 "rex.WRX", /* 0x4e */
10748 "rex.WRXB", /* 0x4f */
10753 /* REX prefixes family. */
10770 return rexes [pref - 0x40];
10790 return (sizeflag & DFLAG) ? "data16" : "data32";
10792 if (address_mode == mode_64bit)
10793 return (sizeflag & AFLAG) ? "addr32" : "addr64";
10795 return (sizeflag & AFLAG) ? "addr16" : "addr32";
10798 case ADDR16_PREFIX:
10800 case ADDR32_PREFIX:
10802 case DATA16_PREFIX:
10804 case DATA32_PREFIX:
10808 case XACQUIRE_PREFIX:
10810 case XRELEASE_PREFIX:
10817 static char op_out[MAX_OPERANDS][100];
10818 static int op_ad, op_index[MAX_OPERANDS];
10819 static int two_source_ops;
10820 static bfd_vma op_address[MAX_OPERANDS];
10821 static bfd_vma op_riprel[MAX_OPERANDS];
10822 static bfd_vma start_pc;
10825 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
10826 * (see topic "Redundant prefixes" in the "Differences from 8086"
10827 * section of the "Virtual 8086 Mode" chapter.)
10828 * 'pc' should be the address of this instruction, it will
10829 * be used to print the target address if this is a relative jump or call
10830 * The function returns the length of this instruction in bytes.
10833 static char intel_syntax;
10834 static char intel_mnemonic = !SYSV386_COMPAT;
10835 static char open_char;
10836 static char close_char;
10837 static char separator_char;
10838 static char scale_char;
10840 /* Here for backwards compatibility. When gdb stops using
10841 print_insn_i386_att and print_insn_i386_intel these functions can
10842 disappear, and print_insn_i386 be merged into print_insn. */
10844 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
10848 return print_insn (pc, info);
10852 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
10856 return print_insn (pc, info);
10860 print_insn_i386 (bfd_vma pc, disassemble_info *info)
10864 return print_insn (pc, info);
10868 print_i386_disassembler_options (FILE *stream)
10870 fprintf (stream, _("\n\
10871 The following i386/x86-64 specific disassembler options are supported for use\n\
10872 with the -M switch (multiple options should be separated by commas):\n"));
10874 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
10875 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
10876 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
10877 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
10878 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
10879 fprintf (stream, _(" att-mnemonic\n"
10880 " Display instruction in AT&T mnemonic\n"));
10881 fprintf (stream, _(" intel-mnemonic\n"
10882 " Display instruction in Intel mnemonic\n"));
10883 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
10884 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
10885 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
10886 fprintf (stream, _(" data32 Assume 32bit data size\n"));
10887 fprintf (stream, _(" data16 Assume 16bit data size\n"));
10888 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
10892 static const struct dis386 bad_opcode = { "(bad)", { XX } };
10894 /* Get a pointer to struct dis386 with a valid name. */
10896 static const struct dis386 *
10897 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
10899 int vindex, vex_table_index;
10901 if (dp->name != NULL)
10904 switch (dp->op[0].bytemode)
10906 case USE_REG_TABLE:
10907 dp = ®_table[dp->op[1].bytemode][modrm.reg];
10910 case USE_MOD_TABLE:
10911 vindex = modrm.mod == 0x3 ? 1 : 0;
10912 dp = &mod_table[dp->op[1].bytemode][vindex];
10916 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
10919 case USE_PREFIX_TABLE:
10922 /* The prefix in VEX is implicit. */
10923 switch (vex.prefix)
10928 case REPE_PREFIX_OPCODE:
10931 case DATA_PREFIX_OPCODE:
10934 case REPNE_PREFIX_OPCODE:
10945 used_prefixes |= (prefixes & PREFIX_REPZ);
10946 if (prefixes & PREFIX_REPZ)
10949 all_prefixes[last_repz_prefix] = 0;
10953 /* We should check PREFIX_REPNZ and PREFIX_REPZ before
10955 used_prefixes |= (prefixes & PREFIX_REPNZ);
10956 if (prefixes & PREFIX_REPNZ)
10959 all_prefixes[last_repnz_prefix] = 0;
10963 used_prefixes |= (prefixes & PREFIX_DATA);
10964 if (prefixes & PREFIX_DATA)
10967 all_prefixes[last_data_prefix] = 0;
10972 dp = &prefix_table[dp->op[1].bytemode][vindex];
10975 case USE_X86_64_TABLE:
10976 vindex = address_mode == mode_64bit ? 1 : 0;
10977 dp = &x86_64_table[dp->op[1].bytemode][vindex];
10980 case USE_3BYTE_TABLE:
10981 FETCH_DATA (info, codep + 2);
10983 dp = &three_byte_table[dp->op[1].bytemode][vindex];
10984 modrm.mod = (*codep >> 6) & 3;
10985 modrm.reg = (*codep >> 3) & 7;
10986 modrm.rm = *codep & 7;
10989 case USE_VEX_LEN_TABLE:
10993 switch (vex.length)
11006 dp = &vex_len_table[dp->op[1].bytemode][vindex];
11009 case USE_XOP_8F_TABLE:
11010 FETCH_DATA (info, codep + 3);
11011 /* All bits in the REX prefix are ignored. */
11013 rex = ~(*codep >> 5) & 0x7;
11015 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
11016 switch ((*codep & 0x1f))
11022 vex_table_index = XOP_08;
11025 vex_table_index = XOP_09;
11028 vex_table_index = XOP_0A;
11032 vex.w = *codep & 0x80;
11033 if (vex.w && address_mode == mode_64bit)
11036 vex.register_specifier = (~(*codep >> 3)) & 0xf;
11037 if (address_mode != mode_64bit
11038 && vex.register_specifier > 0x7)
11044 vex.length = (*codep & 0x4) ? 256 : 128;
11045 switch ((*codep & 0x3))
11051 vex.prefix = DATA_PREFIX_OPCODE;
11054 vex.prefix = REPE_PREFIX_OPCODE;
11057 vex.prefix = REPNE_PREFIX_OPCODE;
11064 dp = &xop_table[vex_table_index][vindex];
11066 FETCH_DATA (info, codep + 1);
11067 modrm.mod = (*codep >> 6) & 3;
11068 modrm.reg = (*codep >> 3) & 7;
11069 modrm.rm = *codep & 7;
11072 case USE_VEX_C4_TABLE:
11073 FETCH_DATA (info, codep + 3);
11074 /* All bits in the REX prefix are ignored. */
11076 rex = ~(*codep >> 5) & 0x7;
11077 switch ((*codep & 0x1f))
11083 vex_table_index = VEX_0F;
11086 vex_table_index = VEX_0F38;
11089 vex_table_index = VEX_0F3A;
11093 vex.w = *codep & 0x80;
11094 if (vex.w && address_mode == mode_64bit)
11097 vex.register_specifier = (~(*codep >> 3)) & 0xf;
11098 if (address_mode != mode_64bit
11099 && vex.register_specifier > 0x7)
11105 vex.length = (*codep & 0x4) ? 256 : 128;
11106 switch ((*codep & 0x3))
11112 vex.prefix = DATA_PREFIX_OPCODE;
11115 vex.prefix = REPE_PREFIX_OPCODE;
11118 vex.prefix = REPNE_PREFIX_OPCODE;
11125 dp = &vex_table[vex_table_index][vindex];
11126 /* There is no MODRM byte for VEX [82|77]. */
11127 if (vindex != 0x77 && vindex != 0x82)
11129 FETCH_DATA (info, codep + 1);
11130 modrm.mod = (*codep >> 6) & 3;
11131 modrm.reg = (*codep >> 3) & 7;
11132 modrm.rm = *codep & 7;
11136 case USE_VEX_C5_TABLE:
11137 FETCH_DATA (info, codep + 2);
11138 /* All bits in the REX prefix are ignored. */
11140 rex = (*codep & 0x80) ? 0 : REX_R;
11142 vex.register_specifier = (~(*codep >> 3)) & 0xf;
11143 if (address_mode != mode_64bit
11144 && vex.register_specifier > 0x7)
11152 vex.length = (*codep & 0x4) ? 256 : 128;
11153 switch ((*codep & 0x3))
11159 vex.prefix = DATA_PREFIX_OPCODE;
11162 vex.prefix = REPE_PREFIX_OPCODE;
11165 vex.prefix = REPNE_PREFIX_OPCODE;
11172 dp = &vex_table[dp->op[1].bytemode][vindex];
11173 /* There is no MODRM byte for VEX [82|77]. */
11174 if (vindex != 0x77 && vindex != 0x82)
11176 FETCH_DATA (info, codep + 1);
11177 modrm.mod = (*codep >> 6) & 3;
11178 modrm.reg = (*codep >> 3) & 7;
11179 modrm.rm = *codep & 7;
11183 case USE_VEX_W_TABLE:
11187 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
11198 if (dp->name != NULL)
11201 return get_valid_dis386 (dp, info);
11205 get_sib (disassemble_info *info)
11207 /* If modrm.mod == 3, operand must be register. */
11209 && address_mode != mode_16bit
11213 FETCH_DATA (info, codep + 2);
11214 sib.index = (codep [1] >> 3) & 7;
11215 sib.scale = (codep [1] >> 6) & 3;
11216 sib.base = codep [1] & 7;
11221 print_insn (bfd_vma pc, disassemble_info *info)
11223 const struct dis386 *dp;
11225 char *op_txt[MAX_OPERANDS];
11229 struct dis_private priv;
11231 int default_prefixes;
11233 priv.orig_sizeflag = AFLAG | DFLAG;
11234 if ((info->mach & bfd_mach_i386_i386) != 0)
11235 address_mode = mode_32bit;
11236 else if (info->mach == bfd_mach_i386_i8086)
11238 address_mode = mode_16bit;
11239 priv.orig_sizeflag = 0;
11242 address_mode = mode_64bit;
11244 if (intel_syntax == (char) -1)
11245 intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
11247 for (p = info->disassembler_options; p != NULL; )
11249 if (CONST_STRNEQ (p, "x86-64"))
11251 address_mode = mode_64bit;
11252 priv.orig_sizeflag = AFLAG | DFLAG;
11254 else if (CONST_STRNEQ (p, "i386"))
11256 address_mode = mode_32bit;
11257 priv.orig_sizeflag = AFLAG | DFLAG;
11259 else if (CONST_STRNEQ (p, "i8086"))
11261 address_mode = mode_16bit;
11262 priv.orig_sizeflag = 0;
11264 else if (CONST_STRNEQ (p, "intel"))
11267 if (CONST_STRNEQ (p + 5, "-mnemonic"))
11268 intel_mnemonic = 1;
11270 else if (CONST_STRNEQ (p, "att"))
11273 if (CONST_STRNEQ (p + 3, "-mnemonic"))
11274 intel_mnemonic = 0;
11276 else if (CONST_STRNEQ (p, "addr"))
11278 if (address_mode == mode_64bit)
11280 if (p[4] == '3' && p[5] == '2')
11281 priv.orig_sizeflag &= ~AFLAG;
11282 else if (p[4] == '6' && p[5] == '4')
11283 priv.orig_sizeflag |= AFLAG;
11287 if (p[4] == '1' && p[5] == '6')
11288 priv.orig_sizeflag &= ~AFLAG;
11289 else if (p[4] == '3' && p[5] == '2')
11290 priv.orig_sizeflag |= AFLAG;
11293 else if (CONST_STRNEQ (p, "data"))
11295 if (p[4] == '1' && p[5] == '6')
11296 priv.orig_sizeflag &= ~DFLAG;
11297 else if (p[4] == '3' && p[5] == '2')
11298 priv.orig_sizeflag |= DFLAG;
11300 else if (CONST_STRNEQ (p, "suffix"))
11301 priv.orig_sizeflag |= SUFFIX_ALWAYS;
11303 p = strchr (p, ',');
11310 names64 = intel_names64;
11311 names32 = intel_names32;
11312 names16 = intel_names16;
11313 names8 = intel_names8;
11314 names8rex = intel_names8rex;
11315 names_seg = intel_names_seg;
11316 names_mm = intel_names_mm;
11317 names_xmm = intel_names_xmm;
11318 names_ymm = intel_names_ymm;
11319 index64 = intel_index64;
11320 index32 = intel_index32;
11321 index16 = intel_index16;
11324 separator_char = '+';
11329 names64 = att_names64;
11330 names32 = att_names32;
11331 names16 = att_names16;
11332 names8 = att_names8;
11333 names8rex = att_names8rex;
11334 names_seg = att_names_seg;
11335 names_mm = att_names_mm;
11336 names_xmm = att_names_xmm;
11337 names_ymm = att_names_ymm;
11338 index64 = att_index64;
11339 index32 = att_index32;
11340 index16 = att_index16;
11343 separator_char = ',';
11347 /* The output looks better if we put 7 bytes on a line, since that
11348 puts most long word instructions on a single line. Use 8 bytes
11350 if ((info->mach & bfd_mach_l1om) != 0)
11351 info->bytes_per_line = 8;
11353 info->bytes_per_line = 7;
11355 info->private_data = &priv;
11356 priv.max_fetched = priv.the_buffer;
11357 priv.insn_start = pc;
11360 for (i = 0; i < MAX_OPERANDS; ++i)
11368 start_codep = priv.the_buffer;
11369 codep = priv.the_buffer;
11371 if (setjmp (priv.bailout) != 0)
11375 /* Getting here means we tried for data but didn't get it. That
11376 means we have an incomplete instruction of some sort. Just
11377 print the first byte as a prefix or a .byte pseudo-op. */
11378 if (codep > priv.the_buffer)
11380 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
11382 (*info->fprintf_func) (info->stream, "%s", name);
11385 /* Just print the first byte as a .byte instruction. */
11386 (*info->fprintf_func) (info->stream, ".byte 0x%x",
11387 (unsigned int) priv.the_buffer[0]);
11397 sizeflag = priv.orig_sizeflag;
11399 if (!ckprefix () || rex_used)
11401 /* Too many prefixes or unused REX prefixes. */
11403 i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
11405 (*info->fprintf_func) (info->stream, "%s",
11406 prefix_name (all_prefixes[i], sizeflag));
11410 insn_codep = codep;
11412 FETCH_DATA (info, codep + 1);
11413 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
11415 if (((prefixes & PREFIX_FWAIT)
11416 && ((*codep < 0xd8) || (*codep > 0xdf))))
11418 (*info->fprintf_func) (info->stream, "fwait");
11422 if (*codep == 0x0f)
11424 unsigned char threebyte;
11425 FETCH_DATA (info, codep + 2);
11426 threebyte = *++codep;
11427 dp = &dis386_twobyte[threebyte];
11428 need_modrm = twobyte_has_modrm[*codep];
11433 dp = &dis386[*codep];
11434 need_modrm = onebyte_has_modrm[*codep];
11438 if ((prefixes & PREFIX_REPZ))
11439 used_prefixes |= PREFIX_REPZ;
11440 if ((prefixes & PREFIX_REPNZ))
11441 used_prefixes |= PREFIX_REPNZ;
11442 if ((prefixes & PREFIX_LOCK))
11443 used_prefixes |= PREFIX_LOCK;
11445 default_prefixes = 0;
11446 if (prefixes & PREFIX_ADDR)
11449 if (dp->op[2].bytemode != loop_jcxz_mode || intel_syntax)
11451 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
11452 all_prefixes[last_addr_prefix] = ADDR32_PREFIX;
11454 all_prefixes[last_addr_prefix] = ADDR16_PREFIX;
11455 default_prefixes |= PREFIX_ADDR;
11459 if ((prefixes & PREFIX_DATA))
11462 if (dp->op[2].bytemode == cond_jump_mode
11463 && dp->op[0].bytemode == v_mode
11466 if (sizeflag & DFLAG)
11467 all_prefixes[last_data_prefix] = DATA32_PREFIX;
11469 all_prefixes[last_data_prefix] = DATA16_PREFIX;
11470 default_prefixes |= PREFIX_DATA;
11472 else if (rex & REX_W)
11474 /* REX_W will override PREFIX_DATA. */
11475 default_prefixes |= PREFIX_DATA;
11481 FETCH_DATA (info, codep + 1);
11482 modrm.mod = (*codep >> 6) & 3;
11483 modrm.reg = (*codep >> 3) & 7;
11484 modrm.rm = *codep & 7;
11491 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
11494 dofloat (sizeflag);
11498 dp = get_valid_dis386 (dp, info);
11499 if (dp != NULL && putop (dp->name, sizeflag) == 0)
11502 for (i = 0; i < MAX_OPERANDS; ++i)
11505 op_ad = MAX_OPERANDS - 1 - i;
11507 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
11512 /* See if any prefixes were not used. If so, print the first one
11513 separately. If we don't do this, we'll wind up printing an
11514 instruction stream which does not precisely correspond to the
11515 bytes we are disassembling. */
11516 if ((prefixes & ~(used_prefixes | default_prefixes)) != 0)
11518 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11519 if (all_prefixes[i])
11522 name = prefix_name (all_prefixes[i], priv.orig_sizeflag);
11524 name = INTERNAL_DISASSEMBLER_ERROR;
11525 (*info->fprintf_func) (info->stream, "%s", name);
11530 /* Check if the REX prefix is used. */
11531 if (rex_ignored == 0 && (rex ^ rex_used) == 0)
11532 all_prefixes[last_rex_prefix] = 0;
11534 /* Check if the SEG prefix is used. */
11535 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
11536 | PREFIX_FS | PREFIX_GS)) != 0
11538 & seg_prefix (all_prefixes[last_seg_prefix])) != 0)
11539 all_prefixes[last_seg_prefix] = 0;
11541 /* Check if the ADDR prefix is used. */
11542 if ((prefixes & PREFIX_ADDR) != 0
11543 && (used_prefixes & PREFIX_ADDR) != 0)
11544 all_prefixes[last_addr_prefix] = 0;
11546 /* Check if the DATA prefix is used. */
11547 if ((prefixes & PREFIX_DATA) != 0
11548 && (used_prefixes & PREFIX_DATA) != 0)
11549 all_prefixes[last_data_prefix] = 0;
11552 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
11553 if (all_prefixes[i])
11556 name = prefix_name (all_prefixes[i], sizeflag);
11559 prefix_length += strlen (name) + 1;
11560 (*info->fprintf_func) (info->stream, "%s ", name);
11563 /* Check maximum code length. */
11564 if ((codep - start_codep) > MAX_CODE_LENGTH)
11566 (*info->fprintf_func) (info->stream, "(bad)");
11567 return MAX_CODE_LENGTH;
11570 obufp = mnemonicendp;
11571 for (i = strlen (obuf) + prefix_length; i < 6; i++)
11574 (*info->fprintf_func) (info->stream, "%s", obuf);
11576 /* The enter and bound instructions are printed with operands in the same
11577 order as the intel book; everything else is printed in reverse order. */
11578 if (intel_syntax || two_source_ops)
11582 for (i = 0; i < MAX_OPERANDS; ++i)
11583 op_txt[i] = op_out[i];
11585 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
11587 op_ad = op_index[i];
11588 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
11589 op_index[MAX_OPERANDS - 1 - i] = op_ad;
11590 riprel = op_riprel[i];
11591 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
11592 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
11597 for (i = 0; i < MAX_OPERANDS; ++i)
11598 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
11602 for (i = 0; i < MAX_OPERANDS; ++i)
11606 (*info->fprintf_func) (info->stream, ",");
11607 if (op_index[i] != -1 && !op_riprel[i])
11608 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
11610 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
11614 for (i = 0; i < MAX_OPERANDS; i++)
11615 if (op_index[i] != -1 && op_riprel[i])
11617 (*info->fprintf_func) (info->stream, " # ");
11618 (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep
11619 + op_address[op_index[i]]), info);
11622 return codep - priv.the_buffer;
11625 static const char *float_mem[] = {
11700 static const unsigned char float_mem_mode[] = {
11775 #define ST { OP_ST, 0 }
11776 #define STi { OP_STi, 0 }
11778 #define FGRPd9_2 NULL, { { NULL, 0 } }
11779 #define FGRPd9_4 NULL, { { NULL, 1 } }
11780 #define FGRPd9_5 NULL, { { NULL, 2 } }
11781 #define FGRPd9_6 NULL, { { NULL, 3 } }
11782 #define FGRPd9_7 NULL, { { NULL, 4 } }
11783 #define FGRPda_5 NULL, { { NULL, 5 } }
11784 #define FGRPdb_4 NULL, { { NULL, 6 } }
11785 #define FGRPde_3 NULL, { { NULL, 7 } }
11786 #define FGRPdf_4 NULL, { { NULL, 8 } }
11788 static const struct dis386 float_reg[][8] = {
11791 { "fadd", { ST, STi } },
11792 { "fmul", { ST, STi } },
11793 { "fcom", { STi } },
11794 { "fcomp", { STi } },
11795 { "fsub", { ST, STi } },
11796 { "fsubr", { ST, STi } },
11797 { "fdiv", { ST, STi } },
11798 { "fdivr", { ST, STi } },
11802 { "fld", { STi } },
11803 { "fxch", { STi } },
11813 { "fcmovb", { ST, STi } },
11814 { "fcmove", { ST, STi } },
11815 { "fcmovbe",{ ST, STi } },
11816 { "fcmovu", { ST, STi } },
11824 { "fcmovnb",{ ST, STi } },
11825 { "fcmovne",{ ST, STi } },
11826 { "fcmovnbe",{ ST, STi } },
11827 { "fcmovnu",{ ST, STi } },
11829 { "fucomi", { ST, STi } },
11830 { "fcomi", { ST, STi } },
11835 { "fadd", { STi, ST } },
11836 { "fmul", { STi, ST } },
11839 { "fsub!M", { STi, ST } },
11840 { "fsubM", { STi, ST } },
11841 { "fdiv!M", { STi, ST } },
11842 { "fdivM", { STi, ST } },
11846 { "ffree", { STi } },
11848 { "fst", { STi } },
11849 { "fstp", { STi } },
11850 { "fucom", { STi } },
11851 { "fucomp", { STi } },
11857 { "faddp", { STi, ST } },
11858 { "fmulp", { STi, ST } },
11861 { "fsub!Mp", { STi, ST } },
11862 { "fsubMp", { STi, ST } },
11863 { "fdiv!Mp", { STi, ST } },
11864 { "fdivMp", { STi, ST } },
11868 { "ffreep", { STi } },
11873 { "fucomip", { ST, STi } },
11874 { "fcomip", { ST, STi } },
11879 static char *fgrps[][8] = {
11882 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11887 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
11892 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
11897 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
11902 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
11907 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11912 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
11913 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
11918 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11923 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
11928 swap_operand (void)
11930 mnemonicendp[0] = '.';
11931 mnemonicendp[1] = 's';
11936 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
11937 int sizeflag ATTRIBUTE_UNUSED)
11939 /* Skip mod/rm byte. */
11945 dofloat (int sizeflag)
11947 const struct dis386 *dp;
11948 unsigned char floatop;
11950 floatop = codep[-1];
11952 if (modrm.mod != 3)
11954 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
11956 putop (float_mem[fp_indx], sizeflag);
11959 OP_E (float_mem_mode[fp_indx], sizeflag);
11962 /* Skip mod/rm byte. */
11966 dp = &float_reg[floatop - 0xd8][modrm.reg];
11967 if (dp->name == NULL)
11969 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
11971 /* Instruction fnstsw is only one with strange arg. */
11972 if (floatop == 0xdf && codep[-1] == 0xe0)
11973 strcpy (op_out[0], names16[0]);
11977 putop (dp->name, sizeflag);
11982 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
11987 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
11992 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
11994 oappend ("%st" + intel_syntax);
11998 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
12000 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
12001 oappend (scratchbuf + intel_syntax);
12004 /* Capital letters in template are macros. */
12006 putop (const char *in_template, int sizeflag)
12011 unsigned int l = 0, len = 1;
12014 #define SAVE_LAST(c) \
12015 if (l < len && l < sizeof (last)) \
12020 for (p = in_template; *p; p++)
12037 while (*++p != '|')
12038 if (*p == '}' || *p == '\0')
12041 /* Fall through. */
12046 while (*++p != '}')
12057 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12061 if (l == 0 && len == 1)
12066 if (sizeflag & SUFFIX_ALWAYS)
12079 if (address_mode == mode_64bit
12080 && !(prefixes & PREFIX_ADDR))
12091 if (intel_syntax && !alt)
12093 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
12095 if (sizeflag & DFLAG)
12096 *obufp++ = intel_syntax ? 'd' : 'l';
12098 *obufp++ = intel_syntax ? 'w' : 's';
12099 used_prefixes |= (prefixes & PREFIX_DATA);
12103 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12106 if (modrm.mod == 3)
12112 if (sizeflag & DFLAG)
12113 *obufp++ = intel_syntax ? 'd' : 'l';
12116 used_prefixes |= (prefixes & PREFIX_DATA);
12122 case 'E': /* For jcxz/jecxz */
12123 if (address_mode == mode_64bit)
12125 if (sizeflag & AFLAG)
12131 if (sizeflag & AFLAG)
12133 used_prefixes |= (prefixes & PREFIX_ADDR);
12138 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
12140 if (sizeflag & AFLAG)
12141 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
12143 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
12144 used_prefixes |= (prefixes & PREFIX_ADDR);
12148 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
12150 if ((rex & REX_W) || (sizeflag & DFLAG))
12154 if (!(rex & REX_W))
12155 used_prefixes |= (prefixes & PREFIX_DATA);
12160 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
12161 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
12163 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
12166 if (prefixes & PREFIX_DS)
12187 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
12192 /* Fall through. */
12195 if (l != 0 || len != 1)
12203 if (sizeflag & SUFFIX_ALWAYS)
12207 if (intel_mnemonic != cond)
12211 if ((prefixes & PREFIX_FWAIT) == 0)
12214 used_prefixes |= PREFIX_FWAIT;
12220 else if (intel_syntax && (sizeflag & DFLAG))
12224 if (!(rex & REX_W))
12225 used_prefixes |= (prefixes & PREFIX_DATA);
12229 && address_mode == mode_64bit
12230 && (sizeflag & DFLAG))
12235 /* Fall through. */
12239 if ((rex & REX_W) == 0
12240 && (prefixes & PREFIX_DATA))
12242 if ((sizeflag & DFLAG) == 0)
12244 used_prefixes |= (prefixes & PREFIX_DATA);
12248 if ((prefixes & PREFIX_DATA)
12250 || (sizeflag & SUFFIX_ALWAYS))
12257 if (sizeflag & DFLAG)
12261 used_prefixes |= (prefixes & PREFIX_DATA);
12268 if (address_mode == mode_64bit && (sizeflag & DFLAG))
12270 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12274 /* Fall through. */
12277 if (l == 0 && len == 1)
12280 if (intel_syntax && !alt)
12283 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
12289 if (sizeflag & DFLAG)
12290 *obufp++ = intel_syntax ? 'd' : 'l';
12293 used_prefixes |= (prefixes & PREFIX_DATA);
12299 if (l != 1 || len != 2 || last[0] != 'L')
12305 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12320 else if (sizeflag & DFLAG)
12329 if (intel_syntax && !p[1]
12330 && ((rex & REX_W) || (sizeflag & DFLAG)))
12332 if (!(rex & REX_W))
12333 used_prefixes |= (prefixes & PREFIX_DATA);
12336 if (l == 0 && len == 1)
12340 if (address_mode == mode_64bit && (sizeflag & DFLAG))
12342 if (sizeflag & SUFFIX_ALWAYS)
12364 /* Fall through. */
12367 if (l == 0 && len == 1)
12372 if (sizeflag & SUFFIX_ALWAYS)
12378 if (sizeflag & DFLAG)
12382 used_prefixes |= (prefixes & PREFIX_DATA);
12396 if (address_mode == mode_64bit
12397 && !(prefixes & PREFIX_ADDR))
12408 if (l != 0 || len != 1)
12413 if (need_vex && vex.prefix)
12415 if (vex.prefix == DATA_PREFIX_OPCODE)
12422 if (prefixes & PREFIX_DATA)
12426 used_prefixes |= (prefixes & PREFIX_DATA);
12430 if (l == 0 && len == 1)
12432 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
12443 if (l != 1 || len != 2 || last[0] != 'X')
12451 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
12453 switch (vex.length)
12467 if (l == 0 && len == 1)
12469 /* operand size flag for cwtl, cbtw */
12478 else if (sizeflag & DFLAG)
12482 if (!(rex & REX_W))
12483 used_prefixes |= (prefixes & PREFIX_DATA);
12490 && last[0] != 'L'))
12497 if (last[0] == 'X')
12498 *obufp++ = vex.w ? 'd': 's';
12500 *obufp++ = vex.w ? 'q': 'd';
12507 mnemonicendp = obufp;
12512 oappend (const char *s)
12514 obufp = stpcpy (obufp, s);
12520 if (prefixes & PREFIX_CS)
12522 used_prefixes |= PREFIX_CS;
12523 oappend ("%cs:" + intel_syntax);
12525 if (prefixes & PREFIX_DS)
12527 used_prefixes |= PREFIX_DS;
12528 oappend ("%ds:" + intel_syntax);
12530 if (prefixes & PREFIX_SS)
12532 used_prefixes |= PREFIX_SS;
12533 oappend ("%ss:" + intel_syntax);
12535 if (prefixes & PREFIX_ES)
12537 used_prefixes |= PREFIX_ES;
12538 oappend ("%es:" + intel_syntax);
12540 if (prefixes & PREFIX_FS)
12542 used_prefixes |= PREFIX_FS;
12543 oappend ("%fs:" + intel_syntax);
12545 if (prefixes & PREFIX_GS)
12547 used_prefixes |= PREFIX_GS;
12548 oappend ("%gs:" + intel_syntax);
12553 OP_indirE (int bytemode, int sizeflag)
12557 OP_E (bytemode, sizeflag);
12561 print_operand_value (char *buf, int hex, bfd_vma disp)
12563 if (address_mode == mode_64bit)
12571 sprintf_vma (tmp, disp);
12572 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
12573 strcpy (buf + 2, tmp + i);
12577 bfd_signed_vma v = disp;
12584 /* Check for possible overflow on 0x8000000000000000. */
12587 strcpy (buf, "9223372036854775808");
12601 tmp[28 - i] = (v % 10) + '0';
12605 strcpy (buf, tmp + 29 - i);
12611 sprintf (buf, "0x%x", (unsigned int) disp);
12613 sprintf (buf, "%d", (int) disp);
12617 /* Put DISP in BUF as signed hex number. */
12620 print_displacement (char *buf, bfd_vma disp)
12622 bfd_signed_vma val = disp;
12631 /* Check for possible overflow. */
12634 switch (address_mode)
12637 strcpy (buf + j, "0x8000000000000000");
12640 strcpy (buf + j, "0x80000000");
12643 strcpy (buf + j, "0x8000");
12653 sprintf_vma (tmp, (bfd_vma) val);
12654 for (i = 0; tmp[i] == '0'; i++)
12656 if (tmp[i] == '\0')
12658 strcpy (buf + j, tmp + i);
12662 intel_operand_size (int bytemode, int sizeflag)
12669 oappend ("BYTE PTR ");
12673 oappend ("WORD PTR ");
12676 if (address_mode == mode_64bit && (sizeflag & DFLAG))
12678 oappend ("QWORD PTR ");
12687 oappend ("QWORD PTR ");
12690 if ((sizeflag & DFLAG) || bytemode == dq_mode)
12691 oappend ("DWORD PTR ");
12693 oappend ("WORD PTR ");
12694 used_prefixes |= (prefixes & PREFIX_DATA);
12698 if ((rex & REX_W) || (sizeflag & DFLAG))
12700 oappend ("WORD PTR ");
12701 if (!(rex & REX_W))
12702 used_prefixes |= (prefixes & PREFIX_DATA);
12705 if (sizeflag & DFLAG)
12706 oappend ("QWORD PTR ");
12708 oappend ("DWORD PTR ");
12709 used_prefixes |= (prefixes & PREFIX_DATA);
12712 case d_scalar_mode:
12713 case d_scalar_swap_mode:
12716 oappend ("DWORD PTR ");
12719 case q_scalar_mode:
12720 case q_scalar_swap_mode:
12722 oappend ("QWORD PTR ");
12725 if (address_mode == mode_64bit)
12726 oappend ("QWORD PTR ");
12728 oappend ("DWORD PTR ");
12731 if (sizeflag & DFLAG)
12732 oappend ("FWORD PTR ");
12734 oappend ("DWORD PTR ");
12735 used_prefixes |= (prefixes & PREFIX_DATA);
12738 oappend ("TBYTE PTR ");
12744 switch (vex.length)
12747 oappend ("XMMWORD PTR ");
12750 oappend ("YMMWORD PTR ");
12757 oappend ("XMMWORD PTR ");
12760 oappend ("XMMWORD PTR ");
12766 switch (vex.length)
12769 oappend ("QWORD PTR ");
12772 oappend ("XMMWORD PTR ");
12782 switch (vex.length)
12786 oappend ("BYTE PTR ");
12796 switch (vex.length)
12800 oappend ("WORD PTR ");
12810 switch (vex.length)
12814 oappend ("DWORD PTR ");
12824 switch (vex.length)
12828 oappend ("QWORD PTR ");
12838 switch (vex.length)
12841 oappend ("WORD PTR ");
12844 oappend ("DWORD PTR ");
12854 switch (vex.length)
12857 oappend ("DWORD PTR ");
12860 oappend ("QWORD PTR ");
12870 switch (vex.length)
12873 oappend ("QWORD PTR ");
12876 oappend ("YMMWORD PTR ");
12886 switch (vex.length)
12890 oappend ("XMMWORD PTR ");
12897 oappend ("OWORD PTR ");
12899 case vex_w_dq_mode:
12900 case vex_scalar_w_dq_mode:
12901 case vex_vsib_d_w_dq_mode:
12902 case vex_vsib_q_w_dq_mode:
12907 oappend ("QWORD PTR ");
12909 oappend ("DWORD PTR ");
12917 OP_E_register (int bytemode, int sizeflag)
12919 int reg = modrm.rm;
12920 const char **names;
12926 if ((sizeflag & SUFFIX_ALWAYS)
12927 && (bytemode == b_swap_mode || bytemode == v_swap_mode))
12950 names = address_mode == mode_64bit ? names64 : names32;
12953 if (address_mode == mode_64bit && (sizeflag & DFLAG))
12971 if ((sizeflag & DFLAG)
12972 || (bytemode != v_mode
12973 && bytemode != v_swap_mode))
12977 used_prefixes |= (prefixes & PREFIX_DATA);
12983 oappend (INTERNAL_DISASSEMBLER_ERROR);
12986 oappend (names[reg]);
12990 OP_E_memory (int bytemode, int sizeflag)
12993 int add = (rex & REX_B) ? 8 : 0;
12998 intel_operand_size (bytemode, sizeflag);
13001 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13003 /* 32/64 bit address mode */
13012 const char **indexes64 = names64;
13013 const char **indexes32 = names32;
13023 vindex = sib.index;
13029 case vex_vsib_d_w_dq_mode:
13030 case vex_vsib_q_w_dq_mode:
13035 switch (vex.length)
13038 indexes64 = indexes32 = names_xmm;
13041 if (!vex.w || bytemode == vex_vsib_q_w_dq_mode)
13042 indexes64 = indexes32 = names_ymm;
13044 indexes64 = indexes32 = names_xmm;
13051 haveindex = vindex != 4;
13058 rbase = base + add;
13066 if (address_mode == mode_64bit && !havesib)
13072 FETCH_DATA (the_info, codep + 1);
13074 if ((disp & 0x80) != 0)
13082 /* In 32bit mode, we need index register to tell [offset] from
13083 [eiz*1 + offset]. */
13084 needindex = (havesib
13087 && address_mode == mode_32bit);
13088 havedisp = (havebase
13090 || (havesib && (haveindex || scale != 0)));
13093 if (modrm.mod != 0 || base == 5)
13095 if (havedisp || riprel)
13096 print_displacement (scratchbuf, disp);
13098 print_operand_value (scratchbuf, 1, disp);
13099 oappend (scratchbuf);
13103 oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)");
13107 if (havebase || haveindex || riprel)
13108 used_prefixes |= PREFIX_ADDR;
13110 if (havedisp || (intel_syntax && riprel))
13112 *obufp++ = open_char;
13113 if (intel_syntax && riprel)
13116 oappend (sizeflag & AFLAG ? "rip" : "eip");
13120 oappend (address_mode == mode_64bit && (sizeflag & AFLAG)
13121 ? names64[rbase] : names32[rbase]);
13124 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
13125 print index to tell base + index from base. */
13129 || (havebase && base != ESP_REG_NUM))
13131 if (!intel_syntax || havebase)
13133 *obufp++ = separator_char;
13137 oappend (address_mode == mode_64bit
13138 && (sizeflag & AFLAG)
13139 ? indexes64[vindex] : indexes32[vindex]);
13141 oappend (address_mode == mode_64bit
13142 && (sizeflag & AFLAG)
13143 ? index64 : index32);
13145 *obufp++ = scale_char;
13147 sprintf (scratchbuf, "%d", 1 << scale);
13148 oappend (scratchbuf);
13152 && (disp || modrm.mod != 0 || base == 5))
13154 if (!havedisp || (bfd_signed_vma) disp >= 0)
13159 else if (modrm.mod != 1 && disp != -disp)
13163 disp = - (bfd_signed_vma) disp;
13167 print_displacement (scratchbuf, disp);
13169 print_operand_value (scratchbuf, 1, disp);
13170 oappend (scratchbuf);
13173 *obufp++ = close_char;
13176 else if (intel_syntax)
13178 if (modrm.mod != 0 || base == 5)
13180 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13181 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13185 oappend (names_seg[ds_reg - es_reg]);
13188 print_operand_value (scratchbuf, 1, disp);
13189 oappend (scratchbuf);
13195 /* 16 bit address mode */
13196 used_prefixes |= prefixes & PREFIX_ADDR;
13203 if ((disp & 0x8000) != 0)
13208 FETCH_DATA (the_info, codep + 1);
13210 if ((disp & 0x80) != 0)
13215 if ((disp & 0x8000) != 0)
13221 if (modrm.mod != 0 || modrm.rm == 6)
13223 print_displacement (scratchbuf, disp);
13224 oappend (scratchbuf);
13227 if (modrm.mod != 0 || modrm.rm != 6)
13229 *obufp++ = open_char;
13231 oappend (index16[modrm.rm]);
13233 && (disp || modrm.mod != 0 || modrm.rm == 6))
13235 if ((bfd_signed_vma) disp >= 0)
13240 else if (modrm.mod != 1)
13244 disp = - (bfd_signed_vma) disp;
13247 print_displacement (scratchbuf, disp);
13248 oappend (scratchbuf);
13251 *obufp++ = close_char;
13254 else if (intel_syntax)
13256 if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13257 | PREFIX_ES | PREFIX_FS | PREFIX_GS))
13261 oappend (names_seg[ds_reg - es_reg]);
13264 print_operand_value (scratchbuf, 1, disp & 0xffff);
13265 oappend (scratchbuf);
13271 OP_E (int bytemode, int sizeflag)
13273 /* Skip mod/rm byte. */
13277 if (modrm.mod == 3)
13278 OP_E_register (bytemode, sizeflag);
13280 OP_E_memory (bytemode, sizeflag);
13284 OP_G (int bytemode, int sizeflag)
13295 oappend (names8rex[modrm.reg + add]);
13297 oappend (names8[modrm.reg + add]);
13300 oappend (names16[modrm.reg + add]);
13303 oappend (names32[modrm.reg + add]);
13306 oappend (names64[modrm.reg + add]);
13315 oappend (names64[modrm.reg + add]);
13318 if ((sizeflag & DFLAG) || bytemode != v_mode)
13319 oappend (names32[modrm.reg + add]);
13321 oappend (names16[modrm.reg + add]);
13322 used_prefixes |= (prefixes & PREFIX_DATA);
13326 if (address_mode == mode_64bit)
13327 oappend (names64[modrm.reg + add]);
13329 oappend (names32[modrm.reg + add]);
13332 oappend (INTERNAL_DISASSEMBLER_ERROR);
13345 FETCH_DATA (the_info, codep + 8);
13346 a = *codep++ & 0xff;
13347 a |= (*codep++ & 0xff) << 8;
13348 a |= (*codep++ & 0xff) << 16;
13349 a |= (*codep++ & 0xff) << 24;
13350 b = *codep++ & 0xff;
13351 b |= (*codep++ & 0xff) << 8;
13352 b |= (*codep++ & 0xff) << 16;
13353 b |= (*codep++ & 0xff) << 24;
13354 x = a + ((bfd_vma) b << 32);
13362 static bfd_signed_vma
13365 bfd_signed_vma x = 0;
13367 FETCH_DATA (the_info, codep + 4);
13368 x = *codep++ & (bfd_signed_vma) 0xff;
13369 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
13370 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
13371 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
13375 static bfd_signed_vma
13378 bfd_signed_vma x = 0;
13380 FETCH_DATA (the_info, codep + 4);
13381 x = *codep++ & (bfd_signed_vma) 0xff;
13382 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
13383 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
13384 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
13386 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
13396 FETCH_DATA (the_info, codep + 2);
13397 x = *codep++ & 0xff;
13398 x |= (*codep++ & 0xff) << 8;
13403 set_op (bfd_vma op, int riprel)
13405 op_index[op_ad] = op_ad;
13406 if (address_mode == mode_64bit)
13408 op_address[op_ad] = op;
13409 op_riprel[op_ad] = riprel;
13413 /* Mask to get a 32-bit address. */
13414 op_address[op_ad] = op & 0xffffffff;
13415 op_riprel[op_ad] = riprel & 0xffffffff;
13420 OP_REG (int code, int sizeflag)
13432 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
13433 case sp_reg: case bp_reg: case si_reg: case di_reg:
13434 s = names16[code - ax_reg + add];
13436 case es_reg: case ss_reg: case cs_reg:
13437 case ds_reg: case fs_reg: case gs_reg:
13438 s = names_seg[code - es_reg + add];
13440 case al_reg: case ah_reg: case cl_reg: case ch_reg:
13441 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
13444 s = names8rex[code - al_reg + add];
13446 s = names8[code - al_reg];
13448 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
13449 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
13450 if (address_mode == mode_64bit && (sizeflag & DFLAG))
13452 s = names64[code - rAX_reg + add];
13455 code += eAX_reg - rAX_reg;
13456 /* Fall through. */
13457 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
13458 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
13461 s = names64[code - eAX_reg + add];
13464 if (sizeflag & DFLAG)
13465 s = names32[code - eAX_reg + add];
13467 s = names16[code - eAX_reg + add];
13468 used_prefixes |= (prefixes & PREFIX_DATA);
13472 s = INTERNAL_DISASSEMBLER_ERROR;
13479 OP_IMREG (int code, int sizeflag)
13491 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
13492 case sp_reg: case bp_reg: case si_reg: case di_reg:
13493 s = names16[code - ax_reg];
13495 case es_reg: case ss_reg: case cs_reg:
13496 case ds_reg: case fs_reg: case gs_reg:
13497 s = names_seg[code - es_reg];
13499 case al_reg: case ah_reg: case cl_reg: case ch_reg:
13500 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
13503 s = names8rex[code - al_reg];
13505 s = names8[code - al_reg];
13507 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
13508 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
13511 s = names64[code - eAX_reg];
13514 if (sizeflag & DFLAG)
13515 s = names32[code - eAX_reg];
13517 s = names16[code - eAX_reg];
13518 used_prefixes |= (prefixes & PREFIX_DATA);
13521 case z_mode_ax_reg:
13522 if ((rex & REX_W) || (sizeflag & DFLAG))
13526 if (!(rex & REX_W))
13527 used_prefixes |= (prefixes & PREFIX_DATA);
13530 s = INTERNAL_DISASSEMBLER_ERROR;
13537 OP_I (int bytemode, int sizeflag)
13540 bfd_signed_vma mask = -1;
13545 FETCH_DATA (the_info, codep + 1);
13550 if (address_mode == mode_64bit)
13555 /* Fall through. */
13562 if (sizeflag & DFLAG)
13572 used_prefixes |= (prefixes & PREFIX_DATA);
13584 oappend (INTERNAL_DISASSEMBLER_ERROR);
13589 scratchbuf[0] = '$';
13590 print_operand_value (scratchbuf + 1, 1, op);
13591 oappend (scratchbuf + intel_syntax);
13592 scratchbuf[0] = '\0';
13596 OP_I64 (int bytemode, int sizeflag)
13599 bfd_signed_vma mask = -1;
13601 if (address_mode != mode_64bit)
13603 OP_I (bytemode, sizeflag);
13610 FETCH_DATA (the_info, codep + 1);
13620 if (sizeflag & DFLAG)
13630 used_prefixes |= (prefixes & PREFIX_DATA);
13638 oappend (INTERNAL_DISASSEMBLER_ERROR);
13643 scratchbuf[0] = '$';
13644 print_operand_value (scratchbuf + 1, 1, op);
13645 oappend (scratchbuf + intel_syntax);
13646 scratchbuf[0] = '\0';
13650 OP_sI (int bytemode, int sizeflag)
13658 FETCH_DATA (the_info, codep + 1);
13660 if ((op & 0x80) != 0)
13662 if (bytemode == b_T_mode)
13664 if (address_mode != mode_64bit
13665 || !(sizeflag & DFLAG))
13667 if (sizeflag & DFLAG)
13675 if (!(rex & REX_W))
13677 if (sizeflag & DFLAG)
13685 if (sizeflag & DFLAG)
13691 oappend (INTERNAL_DISASSEMBLER_ERROR);
13695 scratchbuf[0] = '$';
13696 print_operand_value (scratchbuf + 1, 1, op);
13697 oappend (scratchbuf + intel_syntax);
13701 OP_J (int bytemode, int sizeflag)
13705 bfd_vma segment = 0;
13710 FETCH_DATA (the_info, codep + 1);
13712 if ((disp & 0x80) != 0)
13717 if ((sizeflag & DFLAG) || (rex & REX_W))
13722 if ((disp & 0x8000) != 0)
13724 /* In 16bit mode, address is wrapped around at 64k within
13725 the same segment. Otherwise, a data16 prefix on a jump
13726 instruction means that the pc is masked to 16 bits after
13727 the displacement is added! */
13729 if ((prefixes & PREFIX_DATA) == 0)
13730 segment = ((start_pc + codep - start_codep)
13731 & ~((bfd_vma) 0xffff));
13733 if (!(rex & REX_W))
13734 used_prefixes |= (prefixes & PREFIX_DATA);
13737 oappend (INTERNAL_DISASSEMBLER_ERROR);
13740 disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
13742 print_operand_value (scratchbuf, 1, disp);
13743 oappend (scratchbuf);
13747 OP_SEG (int bytemode, int sizeflag)
13749 if (bytemode == w_mode)
13750 oappend (names_seg[modrm.reg]);
13752 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
13756 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
13760 if (sizeflag & DFLAG)
13770 used_prefixes |= (prefixes & PREFIX_DATA);
13772 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
13774 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
13775 oappend (scratchbuf);
13779 OP_OFF (int bytemode, int sizeflag)
13783 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13784 intel_operand_size (bytemode, sizeflag);
13787 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
13794 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13795 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
13797 oappend (names_seg[ds_reg - es_reg]);
13801 print_operand_value (scratchbuf, 1, off);
13802 oappend (scratchbuf);
13806 OP_OFF64 (int bytemode, int sizeflag)
13810 if (address_mode != mode_64bit
13811 || (prefixes & PREFIX_ADDR))
13813 OP_OFF (bytemode, sizeflag);
13817 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
13818 intel_operand_size (bytemode, sizeflag);
13825 if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS
13826 | PREFIX_ES | PREFIX_FS | PREFIX_GS)))
13828 oappend (names_seg[ds_reg - es_reg]);
13832 print_operand_value (scratchbuf, 1, off);
13833 oappend (scratchbuf);
13837 ptr_reg (int code, int sizeflag)
13841 *obufp++ = open_char;
13842 used_prefixes |= (prefixes & PREFIX_ADDR);
13843 if (address_mode == mode_64bit)
13845 if (!(sizeflag & AFLAG))
13846 s = names32[code - eAX_reg];
13848 s = names64[code - eAX_reg];
13850 else if (sizeflag & AFLAG)
13851 s = names32[code - eAX_reg];
13853 s = names16[code - eAX_reg];
13855 *obufp++ = close_char;
13860 OP_ESreg (int code, int sizeflag)
13866 case 0x6d: /* insw/insl */
13867 intel_operand_size (z_mode, sizeflag);
13869 case 0xa5: /* movsw/movsl/movsq */
13870 case 0xa7: /* cmpsw/cmpsl/cmpsq */
13871 case 0xab: /* stosw/stosl */
13872 case 0xaf: /* scasw/scasl */
13873 intel_operand_size (v_mode, sizeflag);
13876 intel_operand_size (b_mode, sizeflag);
13879 oappend ("%es:" + intel_syntax);
13880 ptr_reg (code, sizeflag);
13884 OP_DSreg (int code, int sizeflag)
13890 case 0x6f: /* outsw/outsl */
13891 intel_operand_size (z_mode, sizeflag);
13893 case 0xa5: /* movsw/movsl/movsq */
13894 case 0xa7: /* cmpsw/cmpsl/cmpsq */
13895 case 0xad: /* lodsw/lodsl/lodsq */
13896 intel_operand_size (v_mode, sizeflag);
13899 intel_operand_size (b_mode, sizeflag);
13908 | PREFIX_GS)) == 0)
13909 prefixes |= PREFIX_DS;
13911 ptr_reg (code, sizeflag);
13915 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13923 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
13925 all_prefixes[last_lock_prefix] = 0;
13926 used_prefixes |= PREFIX_LOCK;
13931 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
13932 oappend (scratchbuf + intel_syntax);
13936 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13945 sprintf (scratchbuf, "db%d", modrm.reg + add);
13947 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
13948 oappend (scratchbuf);
13952 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13954 sprintf (scratchbuf, "%%tr%d", modrm.reg);
13955 oappend (scratchbuf + intel_syntax);
13959 OP_R (int bytemode, int sizeflag)
13961 if (modrm.mod == 3)
13962 OP_E (bytemode, sizeflag);
13968 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13970 int reg = modrm.reg;
13971 const char **names;
13973 used_prefixes |= (prefixes & PREFIX_DATA);
13974 if (prefixes & PREFIX_DATA)
13983 oappend (names[reg]);
13987 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13989 int reg = modrm.reg;
13990 const char **names;
13996 && bytemode != xmm_mode
13997 && bytemode != scalar_mode)
13999 switch (vex.length)
14005 if (vex.w || bytemode != vex_vsib_q_w_dq_mode)
14016 oappend (names[reg]);
14020 OP_EM (int bytemode, int sizeflag)
14023 const char **names;
14025 if (modrm.mod != 3)
14028 && (bytemode == v_mode || bytemode == v_swap_mode))
14030 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14031 used_prefixes |= (prefixes & PREFIX_DATA);
14033 OP_E (bytemode, sizeflag);
14037 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
14040 /* Skip mod/rm byte. */
14043 used_prefixes |= (prefixes & PREFIX_DATA);
14045 if (prefixes & PREFIX_DATA)
14054 oappend (names[reg]);
14057 /* cvt* are the only instructions in sse2 which have
14058 both SSE and MMX operands and also have 0x66 prefix
14059 in their opcode. 0x66 was originally used to differentiate
14060 between SSE and MMX instruction(operands). So we have to handle the
14061 cvt* separately using OP_EMC and OP_MXC */
14063 OP_EMC (int bytemode, int sizeflag)
14065 if (modrm.mod != 3)
14067 if (intel_syntax && bytemode == v_mode)
14069 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14070 used_prefixes |= (prefixes & PREFIX_DATA);
14072 OP_E (bytemode, sizeflag);
14076 /* Skip mod/rm byte. */
14079 used_prefixes |= (prefixes & PREFIX_DATA);
14080 oappend (names_mm[modrm.rm]);
14084 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14086 used_prefixes |= (prefixes & PREFIX_DATA);
14087 oappend (names_mm[modrm.reg]);
14091 OP_EX (int bytemode, int sizeflag)
14094 const char **names;
14096 /* Skip mod/rm byte. */
14100 if (modrm.mod != 3)
14102 OP_E_memory (bytemode, sizeflag);
14111 if ((sizeflag & SUFFIX_ALWAYS)
14112 && (bytemode == x_swap_mode
14113 || bytemode == d_swap_mode
14114 || bytemode == d_scalar_swap_mode
14115 || bytemode == q_swap_mode
14116 || bytemode == q_scalar_swap_mode))
14120 && bytemode != xmm_mode
14121 && bytemode != xmmdw_mode
14122 && bytemode != xmmqd_mode
14123 && bytemode != xmm_mb_mode
14124 && bytemode != xmm_mw_mode
14125 && bytemode != xmm_md_mode
14126 && bytemode != xmm_mq_mode
14127 && bytemode != xmmq_mode
14128 && bytemode != d_scalar_mode
14129 && bytemode != d_scalar_swap_mode
14130 && bytemode != q_scalar_mode
14131 && bytemode != q_scalar_swap_mode
14132 && bytemode != vex_scalar_w_dq_mode)
14134 switch (vex.length)
14148 oappend (names[reg]);
14152 OP_MS (int bytemode, int sizeflag)
14154 if (modrm.mod == 3)
14155 OP_EM (bytemode, sizeflag);
14161 OP_XS (int bytemode, int sizeflag)
14163 if (modrm.mod == 3)
14164 OP_EX (bytemode, sizeflag);
14170 OP_M (int bytemode, int sizeflag)
14172 if (modrm.mod == 3)
14173 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
14176 OP_E (bytemode, sizeflag);
14180 OP_0f07 (int bytemode, int sizeflag)
14182 if (modrm.mod != 3 || modrm.rm != 0)
14185 OP_E (bytemode, sizeflag);
14188 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
14189 32bit mode and "xchg %rax,%rax" in 64bit mode. */
14192 NOP_Fixup1 (int bytemode, int sizeflag)
14194 if ((prefixes & PREFIX_DATA) != 0
14197 && address_mode == mode_64bit))
14198 OP_REG (bytemode, sizeflag);
14200 strcpy (obuf, "nop");
14204 NOP_Fixup2 (int bytemode, int sizeflag)
14206 if ((prefixes & PREFIX_DATA) != 0
14209 && address_mode == mode_64bit))
14210 OP_IMREG (bytemode, sizeflag);
14213 static const char *const Suffix3DNow[] = {
14214 /* 00 */ NULL, NULL, NULL, NULL,
14215 /* 04 */ NULL, NULL, NULL, NULL,
14216 /* 08 */ NULL, NULL, NULL, NULL,
14217 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
14218 /* 10 */ NULL, NULL, NULL, NULL,
14219 /* 14 */ NULL, NULL, NULL, NULL,
14220 /* 18 */ NULL, NULL, NULL, NULL,
14221 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
14222 /* 20 */ NULL, NULL, NULL, NULL,
14223 /* 24 */ NULL, NULL, NULL, NULL,
14224 /* 28 */ NULL, NULL, NULL, NULL,
14225 /* 2C */ NULL, NULL, NULL, NULL,
14226 /* 30 */ NULL, NULL, NULL, NULL,
14227 /* 34 */ NULL, NULL, NULL, NULL,
14228 /* 38 */ NULL, NULL, NULL, NULL,
14229 /* 3C */ NULL, NULL, NULL, NULL,
14230 /* 40 */ NULL, NULL, NULL, NULL,
14231 /* 44 */ NULL, NULL, NULL, NULL,
14232 /* 48 */ NULL, NULL, NULL, NULL,
14233 /* 4C */ NULL, NULL, NULL, NULL,
14234 /* 50 */ NULL, NULL, NULL, NULL,
14235 /* 54 */ NULL, NULL, NULL, NULL,
14236 /* 58 */ NULL, NULL, NULL, NULL,
14237 /* 5C */ NULL, NULL, NULL, NULL,
14238 /* 60 */ NULL, NULL, NULL, NULL,
14239 /* 64 */ NULL, NULL, NULL, NULL,
14240 /* 68 */ NULL, NULL, NULL, NULL,
14241 /* 6C */ NULL, NULL, NULL, NULL,
14242 /* 70 */ NULL, NULL, NULL, NULL,
14243 /* 74 */ NULL, NULL, NULL, NULL,
14244 /* 78 */ NULL, NULL, NULL, NULL,
14245 /* 7C */ NULL, NULL, NULL, NULL,
14246 /* 80 */ NULL, NULL, NULL, NULL,
14247 /* 84 */ NULL, NULL, NULL, NULL,
14248 /* 88 */ NULL, NULL, "pfnacc", NULL,
14249 /* 8C */ NULL, NULL, "pfpnacc", NULL,
14250 /* 90 */ "pfcmpge", NULL, NULL, NULL,
14251 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
14252 /* 98 */ NULL, NULL, "pfsub", NULL,
14253 /* 9C */ NULL, NULL, "pfadd", NULL,
14254 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
14255 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
14256 /* A8 */ NULL, NULL, "pfsubr", NULL,
14257 /* AC */ NULL, NULL, "pfacc", NULL,
14258 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
14259 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
14260 /* B8 */ NULL, NULL, NULL, "pswapd",
14261 /* BC */ NULL, NULL, NULL, "pavgusb",
14262 /* C0 */ NULL, NULL, NULL, NULL,
14263 /* C4 */ NULL, NULL, NULL, NULL,
14264 /* C8 */ NULL, NULL, NULL, NULL,
14265 /* CC */ NULL, NULL, NULL, NULL,
14266 /* D0 */ NULL, NULL, NULL, NULL,
14267 /* D4 */ NULL, NULL, NULL, NULL,
14268 /* D8 */ NULL, NULL, NULL, NULL,
14269 /* DC */ NULL, NULL, NULL, NULL,
14270 /* E0 */ NULL, NULL, NULL, NULL,
14271 /* E4 */ NULL, NULL, NULL, NULL,
14272 /* E8 */ NULL, NULL, NULL, NULL,
14273 /* EC */ NULL, NULL, NULL, NULL,
14274 /* F0 */ NULL, NULL, NULL, NULL,
14275 /* F4 */ NULL, NULL, NULL, NULL,
14276 /* F8 */ NULL, NULL, NULL, NULL,
14277 /* FC */ NULL, NULL, NULL, NULL,
14281 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14283 const char *mnemonic;
14285 FETCH_DATA (the_info, codep + 1);
14286 /* AMD 3DNow! instructions are specified by an opcode suffix in the
14287 place where an 8-bit immediate would normally go. ie. the last
14288 byte of the instruction. */
14289 obufp = mnemonicendp;
14290 mnemonic = Suffix3DNow[*codep++ & 0xff];
14292 oappend (mnemonic);
14295 /* Since a variable sized modrm/sib chunk is between the start
14296 of the opcode (0x0f0f) and the opcode suffix, we need to do
14297 all the modrm processing first, and don't know until now that
14298 we have a bad opcode. This necessitates some cleaning up. */
14299 op_out[0][0] = '\0';
14300 op_out[1][0] = '\0';
14303 mnemonicendp = obufp;
14306 static struct op simd_cmp_op[] =
14308 { STRING_COMMA_LEN ("eq") },
14309 { STRING_COMMA_LEN ("lt") },
14310 { STRING_COMMA_LEN ("le") },
14311 { STRING_COMMA_LEN ("unord") },
14312 { STRING_COMMA_LEN ("neq") },
14313 { STRING_COMMA_LEN ("nlt") },
14314 { STRING_COMMA_LEN ("nle") },
14315 { STRING_COMMA_LEN ("ord") }
14319 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14321 unsigned int cmp_type;
14323 FETCH_DATA (the_info, codep + 1);
14324 cmp_type = *codep++ & 0xff;
14325 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
14328 char *p = mnemonicendp - 2;
14332 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
14333 mnemonicendp += simd_cmp_op[cmp_type].len;
14337 /* We have a reserved extension byte. Output it directly. */
14338 scratchbuf[0] = '$';
14339 print_operand_value (scratchbuf + 1, 1, cmp_type);
14340 oappend (scratchbuf + intel_syntax);
14341 scratchbuf[0] = '\0';
14346 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
14347 int sizeflag ATTRIBUTE_UNUSED)
14349 /* mwait %eax,%ecx */
14352 const char **names = (address_mode == mode_64bit
14353 ? names64 : names32);
14354 strcpy (op_out[0], names[0]);
14355 strcpy (op_out[1], names[1]);
14356 two_source_ops = 1;
14358 /* Skip mod/rm byte. */
14364 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
14365 int sizeflag ATTRIBUTE_UNUSED)
14367 /* monitor %eax,%ecx,%edx" */
14370 const char **op1_names;
14371 const char **names = (address_mode == mode_64bit
14372 ? names64 : names32);
14374 if (!(prefixes & PREFIX_ADDR))
14375 op1_names = (address_mode == mode_16bit
14376 ? names16 : names);
14379 /* Remove "addr16/addr32". */
14380 all_prefixes[last_addr_prefix] = 0;
14381 op1_names = (address_mode != mode_32bit
14382 ? names32 : names16);
14383 used_prefixes |= PREFIX_ADDR;
14385 strcpy (op_out[0], op1_names[0]);
14386 strcpy (op_out[1], names[1]);
14387 strcpy (op_out[2], names[2]);
14388 two_source_ops = 1;
14390 /* Skip mod/rm byte. */
14398 /* Throw away prefixes and 1st. opcode byte. */
14399 codep = insn_codep + 1;
14404 REP_Fixup (int bytemode, int sizeflag)
14406 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
14408 if (prefixes & PREFIX_REPZ)
14409 all_prefixes[last_repz_prefix] = REP_PREFIX;
14416 OP_IMREG (bytemode, sizeflag);
14419 OP_ESreg (bytemode, sizeflag);
14422 OP_DSreg (bytemode, sizeflag);
14430 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
14431 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
14435 HLE_Fixup1 (int bytemode, int sizeflag)
14438 && (prefixes & PREFIX_LOCK) != 0)
14440 if (prefixes & PREFIX_REPZ)
14441 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
14442 if (prefixes & PREFIX_REPNZ)
14443 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
14446 OP_E (bytemode, sizeflag);
14449 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
14450 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
14454 HLE_Fixup2 (int bytemode, int sizeflag)
14456 if (modrm.mod != 3)
14458 if (prefixes & PREFIX_REPZ)
14459 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
14460 if (prefixes & PREFIX_REPNZ)
14461 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
14464 OP_E (bytemode, sizeflag);
14467 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
14468 "xrelease" for memory operand. No check for LOCK prefix. */
14471 HLE_Fixup3 (int bytemode, int sizeflag)
14474 && last_repz_prefix > last_repnz_prefix
14475 && (prefixes & PREFIX_REPZ) != 0)
14476 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
14478 OP_E (bytemode, sizeflag);
14482 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
14487 /* Change cmpxchg8b to cmpxchg16b. */
14488 char *p = mnemonicendp - 2;
14489 mnemonicendp = stpcpy (p, "16b");
14492 else if ((prefixes & PREFIX_LOCK) != 0)
14494 if (prefixes & PREFIX_REPZ)
14495 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
14496 if (prefixes & PREFIX_REPNZ)
14497 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
14500 OP_M (bytemode, sizeflag);
14504 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
14506 const char **names;
14510 switch (vex.length)
14524 oappend (names[reg]);
14528 CRC32_Fixup (int bytemode, int sizeflag)
14530 /* Add proper suffix to "crc32". */
14531 char *p = mnemonicendp;
14550 if (sizeflag & DFLAG)
14554 used_prefixes |= (prefixes & PREFIX_DATA);
14558 oappend (INTERNAL_DISASSEMBLER_ERROR);
14565 if (modrm.mod == 3)
14569 /* Skip mod/rm byte. */
14574 add = (rex & REX_B) ? 8 : 0;
14575 if (bytemode == b_mode)
14579 oappend (names8rex[modrm.rm + add]);
14581 oappend (names8[modrm.rm + add]);
14587 oappend (names64[modrm.rm + add]);
14588 else if ((prefixes & PREFIX_DATA))
14589 oappend (names16[modrm.rm + add]);
14591 oappend (names32[modrm.rm + add]);
14595 OP_E (bytemode, sizeflag);
14599 FXSAVE_Fixup (int bytemode, int sizeflag)
14601 /* Add proper suffix to "fxsave" and "fxrstor". */
14605 char *p = mnemonicendp;
14611 OP_M (bytemode, sizeflag);
14614 /* Display the destination register operand for instructions with
14618 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14621 const char **names;
14629 reg = vex.register_specifier;
14630 if (bytemode == vex_scalar_mode)
14632 oappend (names_xmm[reg]);
14636 switch (vex.length)
14643 case vex_vsib_q_w_dq_mode:
14664 case vex_vsib_q_w_dq_mode:
14665 names = vex.w ? names_ymm : names_xmm;
14676 oappend (names[reg]);
14679 /* Get the VEX immediate byte without moving codep. */
14681 static unsigned char
14682 get_vex_imm8 (int sizeflag, int opnum)
14684 int bytes_before_imm = 0;
14686 if (modrm.mod != 3)
14688 /* There are SIB/displacement bytes. */
14689 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
14691 /* 32/64 bit address mode */
14692 int base = modrm.rm;
14694 /* Check SIB byte. */
14697 FETCH_DATA (the_info, codep + 1);
14699 /* When decoding the third source, don't increase
14700 bytes_before_imm as this has already been incremented
14701 by one in OP_E_memory while decoding the second
14704 bytes_before_imm++;
14707 /* Don't increase bytes_before_imm when decoding the third source,
14708 it has already been incremented by OP_E_memory while decoding
14709 the second source operand. */
14715 /* When modrm.rm == 5 or modrm.rm == 4 and base in
14716 SIB == 5, there is a 4 byte displacement. */
14718 /* No displacement. */
14721 /* 4 byte displacement. */
14722 bytes_before_imm += 4;
14725 /* 1 byte displacement. */
14726 bytes_before_imm++;
14733 /* 16 bit address mode */
14734 /* Don't increase bytes_before_imm when decoding the third source,
14735 it has already been incremented by OP_E_memory while decoding
14736 the second source operand. */
14742 /* When modrm.rm == 6, there is a 2 byte displacement. */
14744 /* No displacement. */
14747 /* 2 byte displacement. */
14748 bytes_before_imm += 2;
14751 /* 1 byte displacement: when decoding the third source,
14752 don't increase bytes_before_imm as this has already
14753 been incremented by one in OP_E_memory while decoding
14754 the second source operand. */
14756 bytes_before_imm++;
14764 FETCH_DATA (the_info, codep + bytes_before_imm + 1);
14765 return codep [bytes_before_imm];
14769 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
14771 const char **names;
14773 if (reg == -1 && modrm.mod != 3)
14775 OP_E_memory (bytemode, sizeflag);
14787 else if (reg > 7 && address_mode != mode_64bit)
14791 switch (vex.length)
14802 oappend (names[reg]);
14806 OP_EX_VexImmW (int bytemode, int sizeflag)
14809 static unsigned char vex_imm8;
14811 if (vex_w_done == 0)
14815 /* Skip mod/rm byte. */
14819 vex_imm8 = get_vex_imm8 (sizeflag, 0);
14822 reg = vex_imm8 >> 4;
14824 OP_EX_VexReg (bytemode, sizeflag, reg);
14826 else if (vex_w_done == 1)
14831 reg = vex_imm8 >> 4;
14833 OP_EX_VexReg (bytemode, sizeflag, reg);
14837 /* Output the imm8 directly. */
14838 scratchbuf[0] = '$';
14839 print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
14840 oappend (scratchbuf + intel_syntax);
14841 scratchbuf[0] = '\0';
14847 OP_Vex_2src (int bytemode, int sizeflag)
14849 if (modrm.mod == 3)
14851 int reg = modrm.rm;
14855 oappend (names_xmm[reg]);
14860 && (bytemode == v_mode || bytemode == v_swap_mode))
14862 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
14863 used_prefixes |= (prefixes & PREFIX_DATA);
14865 OP_E (bytemode, sizeflag);
14870 OP_Vex_2src_1 (int bytemode, int sizeflag)
14872 if (modrm.mod == 3)
14874 /* Skip mod/rm byte. */
14880 oappend (names_xmm[vex.register_specifier]);
14882 OP_Vex_2src (bytemode, sizeflag);
14886 OP_Vex_2src_2 (int bytemode, int sizeflag)
14889 OP_Vex_2src (bytemode, sizeflag);
14891 oappend (names_xmm[vex.register_specifier]);
14895 OP_EX_VexW (int bytemode, int sizeflag)
14903 /* Skip mod/rm byte. */
14908 reg = get_vex_imm8 (sizeflag, 0) >> 4;
14913 reg = get_vex_imm8 (sizeflag, 1) >> 4;
14916 OP_EX_VexReg (bytemode, sizeflag, reg);
14920 VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED,
14921 int sizeflag ATTRIBUTE_UNUSED)
14923 /* Skip the immediate byte and check for invalid bits. */
14924 FETCH_DATA (the_info, codep + 1);
14925 if (*codep++ & 0xf)
14930 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
14933 const char **names;
14935 FETCH_DATA (the_info, codep + 1);
14938 if (bytemode != x_mode)
14945 if (reg > 7 && address_mode != mode_64bit)
14948 switch (vex.length)
14959 oappend (names[reg]);
14963 OP_XMM_VexW (int bytemode, int sizeflag)
14965 /* Turn off the REX.W bit since it is used for swapping operands
14968 OP_XMM (bytemode, sizeflag);
14972 OP_EX_Vex (int bytemode, int sizeflag)
14974 if (modrm.mod != 3)
14976 if (vex.register_specifier != 0)
14980 OP_EX (bytemode, sizeflag);
14984 OP_XMM_Vex (int bytemode, int sizeflag)
14986 if (modrm.mod != 3)
14988 if (vex.register_specifier != 0)
14992 OP_XMM (bytemode, sizeflag);
14996 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
14998 switch (vex.length)
15001 mnemonicendp = stpcpy (obuf, "vzeroupper");
15004 mnemonicendp = stpcpy (obuf, "vzeroall");
15011 static struct op vex_cmp_op[] =
15013 { STRING_COMMA_LEN ("eq") },
15014 { STRING_COMMA_LEN ("lt") },
15015 { STRING_COMMA_LEN ("le") },
15016 { STRING_COMMA_LEN ("unord") },
15017 { STRING_COMMA_LEN ("neq") },
15018 { STRING_COMMA_LEN ("nlt") },
15019 { STRING_COMMA_LEN ("nle") },
15020 { STRING_COMMA_LEN ("ord") },
15021 { STRING_COMMA_LEN ("eq_uq") },
15022 { STRING_COMMA_LEN ("nge") },
15023 { STRING_COMMA_LEN ("ngt") },
15024 { STRING_COMMA_LEN ("false") },
15025 { STRING_COMMA_LEN ("neq_oq") },
15026 { STRING_COMMA_LEN ("ge") },
15027 { STRING_COMMA_LEN ("gt") },
15028 { STRING_COMMA_LEN ("true") },
15029 { STRING_COMMA_LEN ("eq_os") },
15030 { STRING_COMMA_LEN ("lt_oq") },
15031 { STRING_COMMA_LEN ("le_oq") },
15032 { STRING_COMMA_LEN ("unord_s") },
15033 { STRING_COMMA_LEN ("neq_us") },
15034 { STRING_COMMA_LEN ("nlt_uq") },
15035 { STRING_COMMA_LEN ("nle_uq") },
15036 { STRING_COMMA_LEN ("ord_s") },
15037 { STRING_COMMA_LEN ("eq_us") },
15038 { STRING_COMMA_LEN ("nge_uq") },
15039 { STRING_COMMA_LEN ("ngt_uq") },
15040 { STRING_COMMA_LEN ("false_os") },
15041 { STRING_COMMA_LEN ("neq_os") },
15042 { STRING_COMMA_LEN ("ge_oq") },
15043 { STRING_COMMA_LEN ("gt_oq") },
15044 { STRING_COMMA_LEN ("true_us") },
15048 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15050 unsigned int cmp_type;
15052 FETCH_DATA (the_info, codep + 1);
15053 cmp_type = *codep++ & 0xff;
15054 if (cmp_type < ARRAY_SIZE (vex_cmp_op))
15057 char *p = mnemonicendp - 2;
15061 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
15062 mnemonicendp += vex_cmp_op[cmp_type].len;
15066 /* We have a reserved extension byte. Output it directly. */
15067 scratchbuf[0] = '$';
15068 print_operand_value (scratchbuf + 1, 1, cmp_type);
15069 oappend (scratchbuf + intel_syntax);
15070 scratchbuf[0] = '\0';
15074 static const struct op pclmul_op[] =
15076 { STRING_COMMA_LEN ("lql") },
15077 { STRING_COMMA_LEN ("hql") },
15078 { STRING_COMMA_LEN ("lqh") },
15079 { STRING_COMMA_LEN ("hqh") }
15083 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
15084 int sizeflag ATTRIBUTE_UNUSED)
15086 unsigned int pclmul_type;
15088 FETCH_DATA (the_info, codep + 1);
15089 pclmul_type = *codep++ & 0xff;
15090 switch (pclmul_type)
15101 if (pclmul_type < ARRAY_SIZE (pclmul_op))
15104 char *p = mnemonicendp - 3;
15109 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
15110 mnemonicendp += pclmul_op[pclmul_type].len;
15114 /* We have a reserved extension byte. Output it directly. */
15115 scratchbuf[0] = '$';
15116 print_operand_value (scratchbuf + 1, 1, pclmul_type);
15117 oappend (scratchbuf + intel_syntax);
15118 scratchbuf[0] = '\0';
15123 MOVBE_Fixup (int bytemode, int sizeflag)
15125 /* Add proper suffix to "movbe". */
15126 char *p = mnemonicendp;
15135 if (sizeflag & SUFFIX_ALWAYS)
15141 if (sizeflag & DFLAG)
15145 used_prefixes |= (prefixes & PREFIX_DATA);
15150 oappend (INTERNAL_DISASSEMBLER_ERROR);
15157 OP_M (bytemode, sizeflag);
15161 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15164 const char **names;
15166 /* Skip mod/rm byte. */
15180 oappend (names[reg]);
15184 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
15186 const char **names;
15193 oappend (names[vex.register_specifier]);