1 /* Print i386 instructions for GDB, the GNU debugger.
2 Copyright (C) 1988-2018 Free Software Foundation, Inc.
4 This file is part of the GNU opcodes library.
6 This library is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 It is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
24 modified by John Hassey (hassey@dg-rtp.dg.com)
25 x86-64 support added by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */
28 /* The main tables describing the instructions is essentially a copy
29 of the "Opcode Map" chapter (Appendix A) of the Intel 80386
30 Programmers Manual. Usually, there is a capital letter, followed
31 by a small letter. The capital letter tell the addressing mode,
32 and the small letter tells about the operand size. Refer to
33 the Intel manual for details. */
36 #include "disassemble.h"
38 #include "opcode/i386.h"
39 #include "libiberty.h"
43 static int print_insn (bfd_vma, disassemble_info *);
44 static void dofloat (int);
45 static void OP_ST (int, int);
46 static void OP_STi (int, int);
47 static int putop (const char *, int);
48 static void oappend (const char *);
49 static void append_seg (void);
50 static void OP_indirE (int, int);
51 static void print_operand_value (char *, int, bfd_vma);
52 static void OP_E_register (int, int);
53 static void OP_E_memory (int, int);
54 static void print_displacement (char *, bfd_vma);
55 static void OP_E (int, int);
56 static void OP_G (int, int);
57 static bfd_vma get64 (void);
58 static bfd_signed_vma get32 (void);
59 static bfd_signed_vma get32s (void);
60 static int get16 (void);
61 static void set_op (bfd_vma, int);
62 static void OP_Skip_MODRM (int, int);
63 static void OP_REG (int, int);
64 static void OP_IMREG (int, int);
65 static void OP_I (int, int);
66 static void OP_I64 (int, int);
67 static void OP_sI (int, int);
68 static void OP_J (int, int);
69 static void OP_SEG (int, int);
70 static void OP_DIR (int, int);
71 static void OP_OFF (int, int);
72 static void OP_OFF64 (int, int);
73 static void ptr_reg (int, int);
74 static void OP_ESreg (int, int);
75 static void OP_DSreg (int, int);
76 static void OP_C (int, int);
77 static void OP_D (int, int);
78 static void OP_T (int, int);
79 static void OP_R (int, int);
80 static void OP_MMX (int, int);
81 static void OP_XMM (int, int);
82 static void OP_EM (int, int);
83 static void OP_EX (int, int);
84 static void OP_EMC (int,int);
85 static void OP_MXC (int,int);
86 static void OP_MS (int, int);
87 static void OP_XS (int, int);
88 static void OP_M (int, int);
89 static void OP_VEX (int, int);
90 static void OP_EX_Vex (int, int);
91 static void OP_EX_VexW (int, int);
92 static void OP_EX_VexImmW (int, int);
93 static void OP_XMM_Vex (int, int);
94 static void OP_XMM_VexW (int, int);
95 static void OP_Rounding (int, int);
96 static void OP_REG_VexI4 (int, int);
97 static void PCLMUL_Fixup (int, int);
98 static void VZERO_Fixup (int, int);
99 static void VCMP_Fixup (int, int);
100 static void VPCMP_Fixup (int, int);
101 static void VPCOM_Fixup (int, int);
102 static void OP_0f07 (int, int);
103 static void OP_Monitor (int, int);
104 static void OP_Mwait (int, int);
105 static void OP_Mwaitx (int, int);
106 static void NOP_Fixup1 (int, int);
107 static void NOP_Fixup2 (int, int);
108 static void OP_3DNowSuffix (int, int);
109 static void CMP_Fixup (int, int);
110 static void BadOp (void);
111 static void REP_Fixup (int, int);
112 static void BND_Fixup (int, int);
113 static void NOTRACK_Fixup (int, int);
114 static void HLE_Fixup1 (int, int);
115 static void HLE_Fixup2 (int, int);
116 static void HLE_Fixup3 (int, int);
117 static void CMPXCHG8B_Fixup (int, int);
118 static void XMM_Fixup (int, int);
119 static void CRC32_Fixup (int, int);
120 static void FXSAVE_Fixup (int, int);
121 static void PCMPESTR_Fixup (int, int);
122 static void OP_LWPCB_E (int, int);
123 static void OP_LWP_E (int, int);
124 static void OP_Vex_2src_1 (int, int);
125 static void OP_Vex_2src_2 (int, int);
127 static void MOVBE_Fixup (int, int);
129 static void OP_Mask (int, int);
132 /* Points to first byte not fetched. */
133 bfd_byte *max_fetched;
134 bfd_byte the_buffer[MAX_MNEM_SIZE];
137 OPCODES_SIGJMP_BUF bailout;
147 enum address_mode address_mode;
149 /* Flags for the prefixes for the current instruction. See below. */
152 /* REX prefix the current instruction. See below. */
154 /* Bits of REX we've already used. */
156 /* REX bits in original REX prefix ignored. */
157 static int rex_ignored;
158 /* Mark parts used in the REX prefix. When we are testing for
159 empty prefix (for 8bit register REX extension), just mask it
160 out. Otherwise test for REX bit is excuse for existence of REX
161 only in case value is nonzero. */
162 #define USED_REX(value) \
167 rex_used |= (value) | REX_OPCODE; \
170 rex_used |= REX_OPCODE; \
173 /* Flags for prefixes which we somehow handled when printing the
174 current instruction. */
175 static int used_prefixes;
177 /* Flags stored in PREFIXES. */
178 #define PREFIX_REPZ 1
179 #define PREFIX_REPNZ 2
180 #define PREFIX_LOCK 4
182 #define PREFIX_SS 0x10
183 #define PREFIX_DS 0x20
184 #define PREFIX_ES 0x40
185 #define PREFIX_FS 0x80
186 #define PREFIX_GS 0x100
187 #define PREFIX_DATA 0x200
188 #define PREFIX_ADDR 0x400
189 #define PREFIX_FWAIT 0x800
191 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
192 to ADDR (exclusive) are valid. Returns 1 for success, longjmps
194 #define FETCH_DATA(info, addr) \
195 ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \
196 ? 1 : fetch_data ((info), (addr)))
199 fetch_data (struct disassemble_info *info, bfd_byte *addr)
202 struct dis_private *priv = (struct dis_private *) info->private_data;
203 bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);
205 if (addr <= priv->the_buffer + MAX_MNEM_SIZE)
206 status = (*info->read_memory_func) (start,
208 addr - priv->max_fetched,
214 /* If we did manage to read at least one byte, then
215 print_insn_i386 will do something sensible. Otherwise, print
216 an error. We do that here because this is where we know
218 if (priv->max_fetched == priv->the_buffer)
219 (*info->memory_error_func) (status, start, info);
220 OPCODES_SIGLONGJMP (priv->bailout, 1);
223 priv->max_fetched = addr;
227 /* Possible values for prefix requirement. */
228 #define PREFIX_IGNORED_SHIFT 16
229 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
230 #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
231 #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
232 #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
233 #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
235 /* Opcode prefixes. */
236 #define PREFIX_OPCODE (PREFIX_REPZ \
240 /* Prefixes ignored. */
241 #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \
242 | PREFIX_IGNORED_REPNZ \
243 | PREFIX_IGNORED_DATA)
245 #define XX { NULL, 0 }
246 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
248 #define Eb { OP_E, b_mode }
249 #define Ebnd { OP_E, bnd_mode }
250 #define EbS { OP_E, b_swap_mode }
251 #define EbndS { OP_E, bnd_swap_mode }
252 #define Ev { OP_E, v_mode }
253 #define Eva { OP_E, va_mode }
254 #define Ev_bnd { OP_E, v_bnd_mode }
255 #define EvS { OP_E, v_swap_mode }
256 #define Ed { OP_E, d_mode }
257 #define Edq { OP_E, dq_mode }
258 #define Edqw { OP_E, dqw_mode }
259 #define Edqb { OP_E, dqb_mode }
260 #define Edb { OP_E, db_mode }
261 #define Edw { OP_E, dw_mode }
262 #define Edqd { OP_E, dqd_mode }
263 #define Edqa { OP_E, dqa_mode }
264 #define Eq { OP_E, q_mode }
265 #define indirEv { OP_indirE, indir_v_mode }
266 #define indirEp { OP_indirE, f_mode }
267 #define stackEv { OP_E, stack_v_mode }
268 #define Em { OP_E, m_mode }
269 #define Ew { OP_E, w_mode }
270 #define M { OP_M, 0 } /* lea, lgdt, etc. */
271 #define Ma { OP_M, a_mode }
272 #define Mb { OP_M, b_mode }
273 #define Md { OP_M, d_mode }
274 #define Mo { OP_M, o_mode }
275 #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
276 #define Mq { OP_M, q_mode }
277 #define Mv_bnd { OP_M, v_bndmk_mode }
278 #define Mx { OP_M, x_mode }
279 #define Mxmm { OP_M, xmm_mode }
280 #define Gb { OP_G, b_mode }
281 #define Gbnd { OP_G, bnd_mode }
282 #define Gv { OP_G, v_mode }
283 #define Gd { OP_G, d_mode }
284 #define Gdq { OP_G, dq_mode }
285 #define Gm { OP_G, m_mode }
286 #define Gva { OP_G, va_mode }
287 #define Gw { OP_G, w_mode }
288 #define Rd { OP_R, d_mode }
289 #define Rdq { OP_R, dq_mode }
290 #define Rm { OP_R, m_mode }
291 #define Ib { OP_I, b_mode }
292 #define sIb { OP_sI, b_mode } /* sign extened byte */
293 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
294 #define Iv { OP_I, v_mode }
295 #define sIv { OP_sI, v_mode }
296 #define Iq { OP_I, q_mode }
297 #define Iv64 { OP_I64, v_mode }
298 #define Iw { OP_I, w_mode }
299 #define I1 { OP_I, const_1_mode }
300 #define Jb { OP_J, b_mode }
301 #define Jv { OP_J, v_mode }
302 #define Cm { OP_C, m_mode }
303 #define Dm { OP_D, m_mode }
304 #define Td { OP_T, d_mode }
305 #define Skip_MODRM { OP_Skip_MODRM, 0 }
307 #define RMeAX { OP_REG, eAX_reg }
308 #define RMeBX { OP_REG, eBX_reg }
309 #define RMeCX { OP_REG, eCX_reg }
310 #define RMeDX { OP_REG, eDX_reg }
311 #define RMeSP { OP_REG, eSP_reg }
312 #define RMeBP { OP_REG, eBP_reg }
313 #define RMeSI { OP_REG, eSI_reg }
314 #define RMeDI { OP_REG, eDI_reg }
315 #define RMrAX { OP_REG, rAX_reg }
316 #define RMrBX { OP_REG, rBX_reg }
317 #define RMrCX { OP_REG, rCX_reg }
318 #define RMrDX { OP_REG, rDX_reg }
319 #define RMrSP { OP_REG, rSP_reg }
320 #define RMrBP { OP_REG, rBP_reg }
321 #define RMrSI { OP_REG, rSI_reg }
322 #define RMrDI { OP_REG, rDI_reg }
323 #define RMAL { OP_REG, al_reg }
324 #define RMCL { OP_REG, cl_reg }
325 #define RMDL { OP_REG, dl_reg }
326 #define RMBL { OP_REG, bl_reg }
327 #define RMAH { OP_REG, ah_reg }
328 #define RMCH { OP_REG, ch_reg }
329 #define RMDH { OP_REG, dh_reg }
330 #define RMBH { OP_REG, bh_reg }
331 #define RMAX { OP_REG, ax_reg }
332 #define RMDX { OP_REG, dx_reg }
334 #define eAX { OP_IMREG, eAX_reg }
335 #define eBX { OP_IMREG, eBX_reg }
336 #define eCX { OP_IMREG, eCX_reg }
337 #define eDX { OP_IMREG, eDX_reg }
338 #define eSP { OP_IMREG, eSP_reg }
339 #define eBP { OP_IMREG, eBP_reg }
340 #define eSI { OP_IMREG, eSI_reg }
341 #define eDI { OP_IMREG, eDI_reg }
342 #define AL { OP_IMREG, al_reg }
343 #define CL { OP_IMREG, cl_reg }
344 #define DL { OP_IMREG, dl_reg }
345 #define BL { OP_IMREG, bl_reg }
346 #define AH { OP_IMREG, ah_reg }
347 #define CH { OP_IMREG, ch_reg }
348 #define DH { OP_IMREG, dh_reg }
349 #define BH { OP_IMREG, bh_reg }
350 #define AX { OP_IMREG, ax_reg }
351 #define DX { OP_IMREG, dx_reg }
352 #define zAX { OP_IMREG, z_mode_ax_reg }
353 #define indirDX { OP_IMREG, indir_dx_reg }
355 #define Sw { OP_SEG, w_mode }
356 #define Sv { OP_SEG, v_mode }
357 #define Ap { OP_DIR, 0 }
358 #define Ob { OP_OFF64, b_mode }
359 #define Ov { OP_OFF64, v_mode }
360 #define Xb { OP_DSreg, eSI_reg }
361 #define Xv { OP_DSreg, eSI_reg }
362 #define Xz { OP_DSreg, eSI_reg }
363 #define Yb { OP_ESreg, eDI_reg }
364 #define Yv { OP_ESreg, eDI_reg }
365 #define DSBX { OP_DSreg, eBX_reg }
367 #define es { OP_REG, es_reg }
368 #define ss { OP_REG, ss_reg }
369 #define cs { OP_REG, cs_reg }
370 #define ds { OP_REG, ds_reg }
371 #define fs { OP_REG, fs_reg }
372 #define gs { OP_REG, gs_reg }
374 #define MX { OP_MMX, 0 }
375 #define XM { OP_XMM, 0 }
376 #define XMScalar { OP_XMM, scalar_mode }
377 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
378 #define XMM { OP_XMM, xmm_mode }
379 #define XMxmmq { OP_XMM, xmmq_mode }
380 #define EM { OP_EM, v_mode }
381 #define EMS { OP_EM, v_swap_mode }
382 #define EMd { OP_EM, d_mode }
383 #define EMx { OP_EM, x_mode }
384 #define EXbScalar { OP_EX, b_scalar_mode }
385 #define EXw { OP_EX, w_mode }
386 #define EXwScalar { OP_EX, w_scalar_mode }
387 #define EXd { OP_EX, d_mode }
388 #define EXdScalar { OP_EX, d_scalar_mode }
389 #define EXdS { OP_EX, d_swap_mode }
390 #define EXdScalarS { OP_EX, d_scalar_swap_mode }
391 #define EXq { OP_EX, q_mode }
392 #define EXqScalar { OP_EX, q_scalar_mode }
393 #define EXqScalarS { OP_EX, q_scalar_swap_mode }
394 #define EXqS { OP_EX, q_swap_mode }
395 #define EXx { OP_EX, x_mode }
396 #define EXxS { OP_EX, x_swap_mode }
397 #define EXxmm { OP_EX, xmm_mode }
398 #define EXymm { OP_EX, ymm_mode }
399 #define EXxmmq { OP_EX, xmmq_mode }
400 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
401 #define EXxmm_mb { OP_EX, xmm_mb_mode }
402 #define EXxmm_mw { OP_EX, xmm_mw_mode }
403 #define EXxmm_md { OP_EX, xmm_md_mode }
404 #define EXxmm_mq { OP_EX, xmm_mq_mode }
405 #define EXxmm_mdq { OP_EX, xmm_mdq_mode }
406 #define EXxmmdw { OP_EX, xmmdw_mode }
407 #define EXxmmqd { OP_EX, xmmqd_mode }
408 #define EXymmq { OP_EX, ymmq_mode }
409 #define EXVexWdq { OP_EX, vex_w_dq_mode }
410 #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
411 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
412 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
413 #define MS { OP_MS, v_mode }
414 #define XS { OP_XS, v_mode }
415 #define EMCq { OP_EMC, q_mode }
416 #define MXC { OP_MXC, 0 }
417 #define OPSUF { OP_3DNowSuffix, 0 }
418 #define CMP { CMP_Fixup, 0 }
419 #define XMM0 { XMM_Fixup, 0 }
420 #define FXSAVE { FXSAVE_Fixup, 0 }
421 #define Vex_2src_1 { OP_Vex_2src_1, 0 }
422 #define Vex_2src_2 { OP_Vex_2src_2, 0 }
424 #define Vex { OP_VEX, vex_mode }
425 #define VexScalar { OP_VEX, vex_scalar_mode }
426 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
427 #define Vex128 { OP_VEX, vex128_mode }
428 #define Vex256 { OP_VEX, vex256_mode }
429 #define VexGdq { OP_VEX, dq_mode }
430 #define EXdVex { OP_EX_Vex, d_mode }
431 #define EXdVexS { OP_EX_Vex, d_swap_mode }
432 #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
433 #define EXqVex { OP_EX_Vex, q_mode }
434 #define EXqVexS { OP_EX_Vex, q_swap_mode }
435 #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
436 #define EXVexW { OP_EX_VexW, x_mode }
437 #define EXdVexW { OP_EX_VexW, d_mode }
438 #define EXqVexW { OP_EX_VexW, q_mode }
439 #define EXVexImmW { OP_EX_VexImmW, x_mode }
440 #define XMVex { OP_XMM_Vex, 0 }
441 #define XMVexScalar { OP_XMM_Vex, scalar_mode }
442 #define XMVexW { OP_XMM_VexW, 0 }
443 #define XMVexI4 { OP_REG_VexI4, x_mode }
444 #define PCLMUL { PCLMUL_Fixup, 0 }
445 #define VZERO { VZERO_Fixup, 0 }
446 #define VCMP { VCMP_Fixup, 0 }
447 #define VPCMP { VPCMP_Fixup, 0 }
448 #define VPCOM { VPCOM_Fixup, 0 }
450 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
451 #define EXxEVexS { OP_Rounding, evex_sae_mode }
453 #define XMask { OP_Mask, mask_mode }
454 #define MaskG { OP_G, mask_mode }
455 #define MaskE { OP_E, mask_mode }
456 #define MaskBDE { OP_E, mask_bd_mode }
457 #define MaskR { OP_R, mask_mode }
458 #define MaskVex { OP_VEX, mask_mode }
460 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
461 #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode }
462 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
463 #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
465 /* Used handle "rep" prefix for string instructions. */
466 #define Xbr { REP_Fixup, eSI_reg }
467 #define Xvr { REP_Fixup, eSI_reg }
468 #define Ybr { REP_Fixup, eDI_reg }
469 #define Yvr { REP_Fixup, eDI_reg }
470 #define Yzr { REP_Fixup, eDI_reg }
471 #define indirDXr { REP_Fixup, indir_dx_reg }
472 #define ALr { REP_Fixup, al_reg }
473 #define eAXr { REP_Fixup, eAX_reg }
475 /* Used handle HLE prefix for lockable instructions. */
476 #define Ebh1 { HLE_Fixup1, b_mode }
477 #define Evh1 { HLE_Fixup1, v_mode }
478 #define Ebh2 { HLE_Fixup2, b_mode }
479 #define Evh2 { HLE_Fixup2, v_mode }
480 #define Ebh3 { HLE_Fixup3, b_mode }
481 #define Evh3 { HLE_Fixup3, v_mode }
483 #define BND { BND_Fixup, 0 }
484 #define NOTRACK { NOTRACK_Fixup, 0 }
486 #define cond_jump_flag { NULL, cond_jump_mode }
487 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
489 /* bits in sizeflag */
490 #define SUFFIX_ALWAYS 4
498 /* byte operand with operand swapped */
500 /* byte operand, sign extend like 'T' suffix */
502 /* operand size depends on prefixes */
504 /* operand size depends on prefixes with operand swapped */
506 /* operand size depends on address prefix */
510 /* double word operand */
512 /* double word operand with operand swapped */
514 /* quad word operand */
516 /* quad word operand with operand swapped */
518 /* ten-byte operand */
520 /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with
521 broadcast enabled. */
523 /* Similar to x_mode, but with different EVEX mem shifts. */
525 /* Similar to x_mode, but with disabled broadcast. */
527 /* Similar to x_mode, but with operands swapped and disabled broadcast
530 /* 16-byte XMM operand */
532 /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
533 memory operand (depending on vector length). Broadcast isn't
536 /* Same as xmmq_mode, but broadcast is allowed. */
537 evex_half_bcst_xmmq_mode,
538 /* XMM register or byte memory operand */
540 /* XMM register or word memory operand */
542 /* XMM register or double word memory operand */
544 /* XMM register or quad word memory operand */
546 /* XMM register or double/quad word memory operand, depending on
549 /* 16-byte XMM, word, double word or quad word operand. */
551 /* 16-byte XMM, double word, quad word operand or xmm word operand. */
553 /* 32-byte YMM operand */
555 /* quad word, ymmword or zmmword memory operand. */
557 /* 32-byte YMM or 16-byte word operand */
559 /* d_mode in 32bit, q_mode in 64bit mode. */
561 /* pair of v_mode operands */
566 /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
568 /* operand size depends on REX prefixes. */
570 /* registers like dq_mode, memory like w_mode. */
574 /* bounds operand with operand swapped */
576 /* 4- or 6-byte pointer operand */
579 /* v_mode for indirect branch opcodes. */
581 /* v_mode for stack-related opcodes. */
583 /* non-quad operand size depends on prefixes */
585 /* 16-byte operand */
587 /* registers like dq_mode, memory like b_mode. */
589 /* registers like d_mode, memory like b_mode. */
591 /* registers like d_mode, memory like w_mode. */
593 /* registers like dq_mode, memory like d_mode. */
595 /* operand size depends on the W bit as well as address mode. */
597 /* normal vex mode */
599 /* 128bit vex mode */
601 /* 256bit vex mode */
603 /* operand size depends on the VEX.W bit. */
606 /* Similar to vex_w_dq_mode, with VSIB dword indices. */
607 vex_vsib_d_w_dq_mode,
608 /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
610 /* Similar to vex_w_dq_mode, with VSIB qword indices. */
611 vex_vsib_q_w_dq_mode,
612 /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
615 /* scalar, ignore vector length. */
617 /* like b_mode, ignore vector length. */
619 /* like w_mode, ignore vector length. */
621 /* like d_mode, ignore vector length. */
623 /* like d_swap_mode, ignore vector length. */
625 /* like q_mode, ignore vector length. */
627 /* like q_swap_mode, ignore vector length. */
629 /* like vex_mode, ignore vector length. */
631 /* like vex_w_dq_mode, ignore vector length. */
632 vex_scalar_w_dq_mode,
634 /* Static rounding. */
636 /* Supress all exceptions. */
639 /* Mask register operand. */
641 /* Mask register operand. */
708 #define FLOAT NULL, { { NULL, FLOATCODE } }, 0
710 #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0
711 #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P
712 #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I))
713 #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I))
714 #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I))
715 #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I))
716 #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I))
717 #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I))
718 #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P)
719 #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I))
720 #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I))
721 #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I))
722 #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
723 #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
724 #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
850 MOD_VEX_0F12_PREFIX_0,
852 MOD_VEX_0F16_PREFIX_0,
855 MOD_VEX_W_0_0F41_P_0_LEN_1,
856 MOD_VEX_W_1_0F41_P_0_LEN_1,
857 MOD_VEX_W_0_0F41_P_2_LEN_1,
858 MOD_VEX_W_1_0F41_P_2_LEN_1,
859 MOD_VEX_W_0_0F42_P_0_LEN_1,
860 MOD_VEX_W_1_0F42_P_0_LEN_1,
861 MOD_VEX_W_0_0F42_P_2_LEN_1,
862 MOD_VEX_W_1_0F42_P_2_LEN_1,
863 MOD_VEX_W_0_0F44_P_0_LEN_1,
864 MOD_VEX_W_1_0F44_P_0_LEN_1,
865 MOD_VEX_W_0_0F44_P_2_LEN_1,
866 MOD_VEX_W_1_0F44_P_2_LEN_1,
867 MOD_VEX_W_0_0F45_P_0_LEN_1,
868 MOD_VEX_W_1_0F45_P_0_LEN_1,
869 MOD_VEX_W_0_0F45_P_2_LEN_1,
870 MOD_VEX_W_1_0F45_P_2_LEN_1,
871 MOD_VEX_W_0_0F46_P_0_LEN_1,
872 MOD_VEX_W_1_0F46_P_0_LEN_1,
873 MOD_VEX_W_0_0F46_P_2_LEN_1,
874 MOD_VEX_W_1_0F46_P_2_LEN_1,
875 MOD_VEX_W_0_0F47_P_0_LEN_1,
876 MOD_VEX_W_1_0F47_P_0_LEN_1,
877 MOD_VEX_W_0_0F47_P_2_LEN_1,
878 MOD_VEX_W_1_0F47_P_2_LEN_1,
879 MOD_VEX_W_0_0F4A_P_0_LEN_1,
880 MOD_VEX_W_1_0F4A_P_0_LEN_1,
881 MOD_VEX_W_0_0F4A_P_2_LEN_1,
882 MOD_VEX_W_1_0F4A_P_2_LEN_1,
883 MOD_VEX_W_0_0F4B_P_0_LEN_1,
884 MOD_VEX_W_1_0F4B_P_0_LEN_1,
885 MOD_VEX_W_0_0F4B_P_2_LEN_1,
897 MOD_VEX_W_0_0F91_P_0_LEN_0,
898 MOD_VEX_W_1_0F91_P_0_LEN_0,
899 MOD_VEX_W_0_0F91_P_2_LEN_0,
900 MOD_VEX_W_1_0F91_P_2_LEN_0,
901 MOD_VEX_W_0_0F92_P_0_LEN_0,
902 MOD_VEX_W_0_0F92_P_2_LEN_0,
903 MOD_VEX_W_0_0F92_P_3_LEN_0,
904 MOD_VEX_W_1_0F92_P_3_LEN_0,
905 MOD_VEX_W_0_0F93_P_0_LEN_0,
906 MOD_VEX_W_0_0F93_P_2_LEN_0,
907 MOD_VEX_W_0_0F93_P_3_LEN_0,
908 MOD_VEX_W_1_0F93_P_3_LEN_0,
909 MOD_VEX_W_0_0F98_P_0_LEN_0,
910 MOD_VEX_W_1_0F98_P_0_LEN_0,
911 MOD_VEX_W_0_0F98_P_2_LEN_0,
912 MOD_VEX_W_1_0F98_P_2_LEN_0,
913 MOD_VEX_W_0_0F99_P_0_LEN_0,
914 MOD_VEX_W_1_0F99_P_0_LEN_0,
915 MOD_VEX_W_0_0F99_P_2_LEN_0,
916 MOD_VEX_W_1_0F99_P_2_LEN_0,
919 MOD_VEX_0FD7_PREFIX_2,
920 MOD_VEX_0FE7_PREFIX_2,
921 MOD_VEX_0FF0_PREFIX_3,
922 MOD_VEX_0F381A_PREFIX_2,
923 MOD_VEX_0F382A_PREFIX_2,
924 MOD_VEX_0F382C_PREFIX_2,
925 MOD_VEX_0F382D_PREFIX_2,
926 MOD_VEX_0F382E_PREFIX_2,
927 MOD_VEX_0F382F_PREFIX_2,
928 MOD_VEX_0F385A_PREFIX_2,
929 MOD_VEX_0F388C_PREFIX_2,
930 MOD_VEX_0F388E_PREFIX_2,
931 MOD_VEX_W_0_0F3A30_P_2_LEN_0,
932 MOD_VEX_W_1_0F3A30_P_2_LEN_0,
933 MOD_VEX_W_0_0F3A31_P_2_LEN_0,
934 MOD_VEX_W_1_0F3A31_P_2_LEN_0,
935 MOD_VEX_W_0_0F3A32_P_2_LEN_0,
936 MOD_VEX_W_1_0F3A32_P_2_LEN_0,
937 MOD_VEX_W_0_0F3A33_P_2_LEN_0,
938 MOD_VEX_W_1_0F3A33_P_2_LEN_0,
940 MOD_EVEX_0F10_PREFIX_1,
941 MOD_EVEX_0F10_PREFIX_3,
942 MOD_EVEX_0F11_PREFIX_1,
943 MOD_EVEX_0F11_PREFIX_3,
944 MOD_EVEX_0F12_PREFIX_0,
945 MOD_EVEX_0F16_PREFIX_0,
946 MOD_EVEX_0F38C6_REG_1,
947 MOD_EVEX_0F38C6_REG_2,
948 MOD_EVEX_0F38C6_REG_5,
949 MOD_EVEX_0F38C6_REG_6,
950 MOD_EVEX_0F38C7_REG_1,
951 MOD_EVEX_0F38C7_REG_2,
952 MOD_EVEX_0F38C7_REG_5,
953 MOD_EVEX_0F38C7_REG_6
974 PREFIX_MOD_0_0F01_REG_5,
975 PREFIX_MOD_3_0F01_REG_5_RM_0,
976 PREFIX_MOD_3_0F01_REG_5_RM_2,
1022 PREFIX_MOD_0_0FAE_REG_4,
1023 PREFIX_MOD_3_0FAE_REG_4,
1024 PREFIX_MOD_0_0FAE_REG_5,
1025 PREFIX_MOD_3_0FAE_REG_5,
1026 PREFIX_MOD_0_0FAE_REG_6,
1027 PREFIX_MOD_1_0FAE_REG_6,
1034 PREFIX_MOD_0_0FC7_REG_6,
1035 PREFIX_MOD_3_0FC7_REG_6,
1036 PREFIX_MOD_3_0FC7_REG_7,
1166 PREFIX_VEX_0F71_REG_2,
1167 PREFIX_VEX_0F71_REG_4,
1168 PREFIX_VEX_0F71_REG_6,
1169 PREFIX_VEX_0F72_REG_2,
1170 PREFIX_VEX_0F72_REG_4,
1171 PREFIX_VEX_0F72_REG_6,
1172 PREFIX_VEX_0F73_REG_2,
1173 PREFIX_VEX_0F73_REG_3,
1174 PREFIX_VEX_0F73_REG_6,
1175 PREFIX_VEX_0F73_REG_7,
1348 PREFIX_VEX_0F38F3_REG_1,
1349 PREFIX_VEX_0F38F3_REG_2,
1350 PREFIX_VEX_0F38F3_REG_3,
1469 PREFIX_EVEX_0F71_REG_2,
1470 PREFIX_EVEX_0F71_REG_4,
1471 PREFIX_EVEX_0F71_REG_6,
1472 PREFIX_EVEX_0F72_REG_0,
1473 PREFIX_EVEX_0F72_REG_1,
1474 PREFIX_EVEX_0F72_REG_2,
1475 PREFIX_EVEX_0F72_REG_4,
1476 PREFIX_EVEX_0F72_REG_6,
1477 PREFIX_EVEX_0F73_REG_2,
1478 PREFIX_EVEX_0F73_REG_3,
1479 PREFIX_EVEX_0F73_REG_6,
1480 PREFIX_EVEX_0F73_REG_7,
1676 PREFIX_EVEX_0F38C6_REG_1,
1677 PREFIX_EVEX_0F38C6_REG_2,
1678 PREFIX_EVEX_0F38C6_REG_5,
1679 PREFIX_EVEX_0F38C6_REG_6,
1680 PREFIX_EVEX_0F38C7_REG_1,
1681 PREFIX_EVEX_0F38C7_REG_2,
1682 PREFIX_EVEX_0F38C7_REG_5,
1683 PREFIX_EVEX_0F38C7_REG_6,
1785 THREE_BYTE_0F38 = 0,
1812 VEX_LEN_0F10_P_1 = 0,
1816 VEX_LEN_0F12_P_0_M_0,
1817 VEX_LEN_0F12_P_0_M_1,
1820 VEX_LEN_0F16_P_0_M_0,
1821 VEX_LEN_0F16_P_0_M_1,
1885 VEX_LEN_0FAE_R_2_M_0,
1886 VEX_LEN_0FAE_R_3_M_0,
1895 VEX_LEN_0F381A_P_2_M_0,
1898 VEX_LEN_0F385A_P_2_M_0,
1901 VEX_LEN_0F38F3_R_1_P_0,
1902 VEX_LEN_0F38F3_R_2_P_0,
1903 VEX_LEN_0F38F3_R_3_P_0,
1948 VEX_LEN_0FXOP_08_CC,
1949 VEX_LEN_0FXOP_08_CD,
1950 VEX_LEN_0FXOP_08_CE,
1951 VEX_LEN_0FXOP_08_CF,
1952 VEX_LEN_0FXOP_08_EC,
1953 VEX_LEN_0FXOP_08_ED,
1954 VEX_LEN_0FXOP_08_EE,
1955 VEX_LEN_0FXOP_08_EF,
1956 VEX_LEN_0FXOP_09_80,
1990 VEX_W_0F41_P_0_LEN_1,
1991 VEX_W_0F41_P_2_LEN_1,
1992 VEX_W_0F42_P_0_LEN_1,
1993 VEX_W_0F42_P_2_LEN_1,
1994 VEX_W_0F44_P_0_LEN_0,
1995 VEX_W_0F44_P_2_LEN_0,
1996 VEX_W_0F45_P_0_LEN_1,
1997 VEX_W_0F45_P_2_LEN_1,
1998 VEX_W_0F46_P_0_LEN_1,
1999 VEX_W_0F46_P_2_LEN_1,
2000 VEX_W_0F47_P_0_LEN_1,
2001 VEX_W_0F47_P_2_LEN_1,
2002 VEX_W_0F4A_P_0_LEN_1,
2003 VEX_W_0F4A_P_2_LEN_1,
2004 VEX_W_0F4B_P_0_LEN_1,
2005 VEX_W_0F4B_P_2_LEN_1,
2085 VEX_W_0F90_P_0_LEN_0,
2086 VEX_W_0F90_P_2_LEN_0,
2087 VEX_W_0F91_P_0_LEN_0,
2088 VEX_W_0F91_P_2_LEN_0,
2089 VEX_W_0F92_P_0_LEN_0,
2090 VEX_W_0F92_P_2_LEN_0,
2091 VEX_W_0F92_P_3_LEN_0,
2092 VEX_W_0F93_P_0_LEN_0,
2093 VEX_W_0F93_P_2_LEN_0,
2094 VEX_W_0F93_P_3_LEN_0,
2095 VEX_W_0F98_P_0_LEN_0,
2096 VEX_W_0F98_P_2_LEN_0,
2097 VEX_W_0F99_P_0_LEN_0,
2098 VEX_W_0F99_P_2_LEN_0,
2177 VEX_W_0F381A_P_2_M_0,
2189 VEX_W_0F382A_P_2_M_0,
2191 VEX_W_0F382C_P_2_M_0,
2192 VEX_W_0F382D_P_2_M_0,
2193 VEX_W_0F382E_P_2_M_0,
2194 VEX_W_0F382F_P_2_M_0,
2216 VEX_W_0F385A_P_2_M_0,
2241 VEX_W_0F3A30_P_2_LEN_0,
2242 VEX_W_0F3A31_P_2_LEN_0,
2243 VEX_W_0F3A32_P_2_LEN_0,
2244 VEX_W_0F3A33_P_2_LEN_0,
2263 EVEX_W_0F10_P_1_M_0,
2264 EVEX_W_0F10_P_1_M_1,
2266 EVEX_W_0F10_P_3_M_0,
2267 EVEX_W_0F10_P_3_M_1,
2269 EVEX_W_0F11_P_1_M_0,
2270 EVEX_W_0F11_P_1_M_1,
2272 EVEX_W_0F11_P_3_M_0,
2273 EVEX_W_0F11_P_3_M_1,
2274 EVEX_W_0F12_P_0_M_0,
2275 EVEX_W_0F12_P_0_M_1,
2285 EVEX_W_0F16_P_0_M_0,
2286 EVEX_W_0F16_P_0_M_1,
2357 EVEX_W_0F72_R_2_P_2,
2358 EVEX_W_0F72_R_6_P_2,
2359 EVEX_W_0F73_R_2_P_2,
2360 EVEX_W_0F73_R_6_P_2,
2468 EVEX_W_0F38C7_R_1_P_2,
2469 EVEX_W_0F38C7_R_2_P_2,
2470 EVEX_W_0F38C7_R_5_P_2,
2471 EVEX_W_0F38C7_R_6_P_2,
2512 typedef void (*op_rtn) (int bytemode, int sizeflag);
2521 unsigned int prefix_requirement;
2524 /* Upper case letters in the instruction names here are macros.
2525 'A' => print 'b' if no register operands or suffix_always is true
2526 'B' => print 'b' if suffix_always is true
2527 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
2529 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
2530 suffix_always is true
2531 'E' => print 'e' if 32-bit form of jcxz
2532 'F' => print 'w' or 'l' depending on address size prefix (loop insns)
2533 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
2534 'H' => print ",pt" or ",pn" branch hint
2535 'I' => honor following macro letter even in Intel mode (implemented only
2536 for some of the macro letters)
2538 'K' => print 'd' or 'q' if rex prefix is present.
2539 'L' => print 'l' if suffix_always is true
2540 'M' => print 'r' if intel_mnemonic is false.
2541 'N' => print 'n' if instruction has no wait "prefix"
2542 'O' => print 'd' or 'o' (or 'q' in Intel mode)
2543 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
2544 or suffix_always is true. print 'q' if rex prefix is present.
2545 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
2547 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
2548 'S' => print 'w', 'l' or 'q' if suffix_always is true
2549 'T' => print 'q' in 64bit mode if instruction has no operand size
2550 prefix and behave as 'P' otherwise
2551 'U' => print 'q' in 64bit mode if instruction has no operand size
2552 prefix and behave as 'Q' otherwise
2553 'V' => print 'q' in 64bit mode if instruction has no operand size
2554 prefix and behave as 'S' otherwise
2555 'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
2556 'X' => print 's', 'd' depending on data16 prefix (for XMM)
2558 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
2559 '!' => change condition from true to false or from false to true.
2560 '%' => add 1 upper case letter to the macro.
2561 '^' => print 'w' or 'l' depending on operand size prefix or
2562 suffix_always is true (lcall/ljmp).
2563 '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
2564 on operand size prefix.
2565 '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
2566 has no operand size prefix for AMD64 ISA, behave as 'P'
2569 2 upper case letter macros:
2570 "XY" => print 'x' or 'y' if suffix_always is true or no register
2571 operands and no broadcast.
2572 "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
2573 register operands and no broadcast.
2574 "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
2575 "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
2576 or suffix_always is true
2577 "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
2578 "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
2579 "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
2580 "LW" => print 'd', 'q' depending on the VEX.W bit
2581 "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
2582 an operand size prefix, or suffix_always is true. print
2583 'q' if rex prefix is present.
2585 Many of the above letters print nothing in Intel mode. See "putop"
2588 Braces '{' and '}', and vertical bars '|', indicate alternative
2589 mnemonic strings for AT&T and Intel. */
2591 static const struct dis386 dis386[] = {
2593 { "addB", { Ebh1, Gb }, 0 },
2594 { "addS", { Evh1, Gv }, 0 },
2595 { "addB", { Gb, EbS }, 0 },
2596 { "addS", { Gv, EvS }, 0 },
2597 { "addB", { AL, Ib }, 0 },
2598 { "addS", { eAX, Iv }, 0 },
2599 { X86_64_TABLE (X86_64_06) },
2600 { X86_64_TABLE (X86_64_07) },
2602 { "orB", { Ebh1, Gb }, 0 },
2603 { "orS", { Evh1, Gv }, 0 },
2604 { "orB", { Gb, EbS }, 0 },
2605 { "orS", { Gv, EvS }, 0 },
2606 { "orB", { AL, Ib }, 0 },
2607 { "orS", { eAX, Iv }, 0 },
2608 { X86_64_TABLE (X86_64_0D) },
2609 { Bad_Opcode }, /* 0x0f extended opcode escape */
2611 { "adcB", { Ebh1, Gb }, 0 },
2612 { "adcS", { Evh1, Gv }, 0 },
2613 { "adcB", { Gb, EbS }, 0 },
2614 { "adcS", { Gv, EvS }, 0 },
2615 { "adcB", { AL, Ib }, 0 },
2616 { "adcS", { eAX, Iv }, 0 },
2617 { X86_64_TABLE (X86_64_16) },
2618 { X86_64_TABLE (X86_64_17) },
2620 { "sbbB", { Ebh1, Gb }, 0 },
2621 { "sbbS", { Evh1, Gv }, 0 },
2622 { "sbbB", { Gb, EbS }, 0 },
2623 { "sbbS", { Gv, EvS }, 0 },
2624 { "sbbB", { AL, Ib }, 0 },
2625 { "sbbS", { eAX, Iv }, 0 },
2626 { X86_64_TABLE (X86_64_1E) },
2627 { X86_64_TABLE (X86_64_1F) },
2629 { "andB", { Ebh1, Gb }, 0 },
2630 { "andS", { Evh1, Gv }, 0 },
2631 { "andB", { Gb, EbS }, 0 },
2632 { "andS", { Gv, EvS }, 0 },
2633 { "andB", { AL, Ib }, 0 },
2634 { "andS", { eAX, Iv }, 0 },
2635 { Bad_Opcode }, /* SEG ES prefix */
2636 { X86_64_TABLE (X86_64_27) },
2638 { "subB", { Ebh1, Gb }, 0 },
2639 { "subS", { Evh1, Gv }, 0 },
2640 { "subB", { Gb, EbS }, 0 },
2641 { "subS", { Gv, EvS }, 0 },
2642 { "subB", { AL, Ib }, 0 },
2643 { "subS", { eAX, Iv }, 0 },
2644 { Bad_Opcode }, /* SEG CS prefix */
2645 { X86_64_TABLE (X86_64_2F) },
2647 { "xorB", { Ebh1, Gb }, 0 },
2648 { "xorS", { Evh1, Gv }, 0 },
2649 { "xorB", { Gb, EbS }, 0 },
2650 { "xorS", { Gv, EvS }, 0 },
2651 { "xorB", { AL, Ib }, 0 },
2652 { "xorS", { eAX, Iv }, 0 },
2653 { Bad_Opcode }, /* SEG SS prefix */
2654 { X86_64_TABLE (X86_64_37) },
2656 { "cmpB", { Eb, Gb }, 0 },
2657 { "cmpS", { Ev, Gv }, 0 },
2658 { "cmpB", { Gb, EbS }, 0 },
2659 { "cmpS", { Gv, EvS }, 0 },
2660 { "cmpB", { AL, Ib }, 0 },
2661 { "cmpS", { eAX, Iv }, 0 },
2662 { Bad_Opcode }, /* SEG DS prefix */
2663 { X86_64_TABLE (X86_64_3F) },
2665 { "inc{S|}", { RMeAX }, 0 },
2666 { "inc{S|}", { RMeCX }, 0 },
2667 { "inc{S|}", { RMeDX }, 0 },
2668 { "inc{S|}", { RMeBX }, 0 },
2669 { "inc{S|}", { RMeSP }, 0 },
2670 { "inc{S|}", { RMeBP }, 0 },
2671 { "inc{S|}", { RMeSI }, 0 },
2672 { "inc{S|}", { RMeDI }, 0 },
2674 { "dec{S|}", { RMeAX }, 0 },
2675 { "dec{S|}", { RMeCX }, 0 },
2676 { "dec{S|}", { RMeDX }, 0 },
2677 { "dec{S|}", { RMeBX }, 0 },
2678 { "dec{S|}", { RMeSP }, 0 },
2679 { "dec{S|}", { RMeBP }, 0 },
2680 { "dec{S|}", { RMeSI }, 0 },
2681 { "dec{S|}", { RMeDI }, 0 },
2683 { "pushV", { RMrAX }, 0 },
2684 { "pushV", { RMrCX }, 0 },
2685 { "pushV", { RMrDX }, 0 },
2686 { "pushV", { RMrBX }, 0 },
2687 { "pushV", { RMrSP }, 0 },
2688 { "pushV", { RMrBP }, 0 },
2689 { "pushV", { RMrSI }, 0 },
2690 { "pushV", { RMrDI }, 0 },
2692 { "popV", { RMrAX }, 0 },
2693 { "popV", { RMrCX }, 0 },
2694 { "popV", { RMrDX }, 0 },
2695 { "popV", { RMrBX }, 0 },
2696 { "popV", { RMrSP }, 0 },
2697 { "popV", { RMrBP }, 0 },
2698 { "popV", { RMrSI }, 0 },
2699 { "popV", { RMrDI }, 0 },
2701 { X86_64_TABLE (X86_64_60) },
2702 { X86_64_TABLE (X86_64_61) },
2703 { X86_64_TABLE (X86_64_62) },
2704 { X86_64_TABLE (X86_64_63) },
2705 { Bad_Opcode }, /* seg fs */
2706 { Bad_Opcode }, /* seg gs */
2707 { Bad_Opcode }, /* op size prefix */
2708 { Bad_Opcode }, /* adr size prefix */
2710 { "pushT", { sIv }, 0 },
2711 { "imulS", { Gv, Ev, Iv }, 0 },
2712 { "pushT", { sIbT }, 0 },
2713 { "imulS", { Gv, Ev, sIb }, 0 },
2714 { "ins{b|}", { Ybr, indirDX }, 0 },
2715 { X86_64_TABLE (X86_64_6D) },
2716 { "outs{b|}", { indirDXr, Xb }, 0 },
2717 { X86_64_TABLE (X86_64_6F) },
2719 { "joH", { Jb, BND, cond_jump_flag }, 0 },
2720 { "jnoH", { Jb, BND, cond_jump_flag }, 0 },
2721 { "jbH", { Jb, BND, cond_jump_flag }, 0 },
2722 { "jaeH", { Jb, BND, cond_jump_flag }, 0 },
2723 { "jeH", { Jb, BND, cond_jump_flag }, 0 },
2724 { "jneH", { Jb, BND, cond_jump_flag }, 0 },
2725 { "jbeH", { Jb, BND, cond_jump_flag }, 0 },
2726 { "jaH", { Jb, BND, cond_jump_flag }, 0 },
2728 { "jsH", { Jb, BND, cond_jump_flag }, 0 },
2729 { "jnsH", { Jb, BND, cond_jump_flag }, 0 },
2730 { "jpH", { Jb, BND, cond_jump_flag }, 0 },
2731 { "jnpH", { Jb, BND, cond_jump_flag }, 0 },
2732 { "jlH", { Jb, BND, cond_jump_flag }, 0 },
2733 { "jgeH", { Jb, BND, cond_jump_flag }, 0 },
2734 { "jleH", { Jb, BND, cond_jump_flag }, 0 },
2735 { "jgH", { Jb, BND, cond_jump_flag }, 0 },
2737 { REG_TABLE (REG_80) },
2738 { REG_TABLE (REG_81) },
2739 { X86_64_TABLE (X86_64_82) },
2740 { REG_TABLE (REG_83) },
2741 { "testB", { Eb, Gb }, 0 },
2742 { "testS", { Ev, Gv }, 0 },
2743 { "xchgB", { Ebh2, Gb }, 0 },
2744 { "xchgS", { Evh2, Gv }, 0 },
2746 { "movB", { Ebh3, Gb }, 0 },
2747 { "movS", { Evh3, Gv }, 0 },
2748 { "movB", { Gb, EbS }, 0 },
2749 { "movS", { Gv, EvS }, 0 },
2750 { "movD", { Sv, Sw }, 0 },
2751 { MOD_TABLE (MOD_8D) },
2752 { "movD", { Sw, Sv }, 0 },
2753 { REG_TABLE (REG_8F) },
2755 { PREFIX_TABLE (PREFIX_90) },
2756 { "xchgS", { RMeCX, eAX }, 0 },
2757 { "xchgS", { RMeDX, eAX }, 0 },
2758 { "xchgS", { RMeBX, eAX }, 0 },
2759 { "xchgS", { RMeSP, eAX }, 0 },
2760 { "xchgS", { RMeBP, eAX }, 0 },
2761 { "xchgS", { RMeSI, eAX }, 0 },
2762 { "xchgS", { RMeDI, eAX }, 0 },
2764 { "cW{t|}R", { XX }, 0 },
2765 { "cR{t|}O", { XX }, 0 },
2766 { X86_64_TABLE (X86_64_9A) },
2767 { Bad_Opcode }, /* fwait */
2768 { "pushfT", { XX }, 0 },
2769 { "popfT", { XX }, 0 },
2770 { "sahf", { XX }, 0 },
2771 { "lahf", { XX }, 0 },
2773 { "mov%LB", { AL, Ob }, 0 },
2774 { "mov%LS", { eAX, Ov }, 0 },
2775 { "mov%LB", { Ob, AL }, 0 },
2776 { "mov%LS", { Ov, eAX }, 0 },
2777 { "movs{b|}", { Ybr, Xb }, 0 },
2778 { "movs{R|}", { Yvr, Xv }, 0 },
2779 { "cmps{b|}", { Xb, Yb }, 0 },
2780 { "cmps{R|}", { Xv, Yv }, 0 },
2782 { "testB", { AL, Ib }, 0 },
2783 { "testS", { eAX, Iv }, 0 },
2784 { "stosB", { Ybr, AL }, 0 },
2785 { "stosS", { Yvr, eAX }, 0 },
2786 { "lodsB", { ALr, Xb }, 0 },
2787 { "lodsS", { eAXr, Xv }, 0 },
2788 { "scasB", { AL, Yb }, 0 },
2789 { "scasS", { eAX, Yv }, 0 },
2791 { "movB", { RMAL, Ib }, 0 },
2792 { "movB", { RMCL, Ib }, 0 },
2793 { "movB", { RMDL, Ib }, 0 },
2794 { "movB", { RMBL, Ib }, 0 },
2795 { "movB", { RMAH, Ib }, 0 },
2796 { "movB", { RMCH, Ib }, 0 },
2797 { "movB", { RMDH, Ib }, 0 },
2798 { "movB", { RMBH, Ib }, 0 },
2800 { "mov%LV", { RMeAX, Iv64 }, 0 },
2801 { "mov%LV", { RMeCX, Iv64 }, 0 },
2802 { "mov%LV", { RMeDX, Iv64 }, 0 },
2803 { "mov%LV", { RMeBX, Iv64 }, 0 },
2804 { "mov%LV", { RMeSP, Iv64 }, 0 },
2805 { "mov%LV", { RMeBP, Iv64 }, 0 },
2806 { "mov%LV", { RMeSI, Iv64 }, 0 },
2807 { "mov%LV", { RMeDI, Iv64 }, 0 },
2809 { REG_TABLE (REG_C0) },
2810 { REG_TABLE (REG_C1) },
2811 { "retT", { Iw, BND }, 0 },
2812 { "retT", { BND }, 0 },
2813 { X86_64_TABLE (X86_64_C4) },
2814 { X86_64_TABLE (X86_64_C5) },
2815 { REG_TABLE (REG_C6) },
2816 { REG_TABLE (REG_C7) },
2818 { "enterT", { Iw, Ib }, 0 },
2819 { "leaveT", { XX }, 0 },
2820 { "Jret{|f}P", { Iw }, 0 },
2821 { "Jret{|f}P", { XX }, 0 },
2822 { "int3", { XX }, 0 },
2823 { "int", { Ib }, 0 },
2824 { X86_64_TABLE (X86_64_CE) },
2825 { "iret%LP", { XX }, 0 },
2827 { REG_TABLE (REG_D0) },
2828 { REG_TABLE (REG_D1) },
2829 { REG_TABLE (REG_D2) },
2830 { REG_TABLE (REG_D3) },
2831 { X86_64_TABLE (X86_64_D4) },
2832 { X86_64_TABLE (X86_64_D5) },
2834 { "xlat", { DSBX }, 0 },
2845 { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 },
2846 { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 },
2847 { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 },
2848 { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 },
2849 { "inB", { AL, Ib }, 0 },
2850 { "inG", { zAX, Ib }, 0 },
2851 { "outB", { Ib, AL }, 0 },
2852 { "outG", { Ib, zAX }, 0 },
2854 { X86_64_TABLE (X86_64_E8) },
2855 { X86_64_TABLE (X86_64_E9) },
2856 { X86_64_TABLE (X86_64_EA) },
2857 { "jmp", { Jb, BND }, 0 },
2858 { "inB", { AL, indirDX }, 0 },
2859 { "inG", { zAX, indirDX }, 0 },
2860 { "outB", { indirDX, AL }, 0 },
2861 { "outG", { indirDX, zAX }, 0 },
2863 { Bad_Opcode }, /* lock prefix */
2864 { "icebp", { XX }, 0 },
2865 { Bad_Opcode }, /* repne */
2866 { Bad_Opcode }, /* repz */
2867 { "hlt", { XX }, 0 },
2868 { "cmc", { XX }, 0 },
2869 { REG_TABLE (REG_F6) },
2870 { REG_TABLE (REG_F7) },
2872 { "clc", { XX }, 0 },
2873 { "stc", { XX }, 0 },
2874 { "cli", { XX }, 0 },
2875 { "sti", { XX }, 0 },
2876 { "cld", { XX }, 0 },
2877 { "std", { XX }, 0 },
2878 { REG_TABLE (REG_FE) },
2879 { REG_TABLE (REG_FF) },
2882 static const struct dis386 dis386_twobyte[] = {
2884 { REG_TABLE (REG_0F00 ) },
2885 { REG_TABLE (REG_0F01 ) },
2886 { "larS", { Gv, Ew }, 0 },
2887 { "lslS", { Gv, Ew }, 0 },
2889 { "syscall", { XX }, 0 },
2890 { "clts", { XX }, 0 },
2891 { "sysret%LP", { XX }, 0 },
2893 { "invd", { XX }, 0 },
2894 { PREFIX_TABLE (PREFIX_0F09) },
2896 { "ud2", { XX }, 0 },
2898 { REG_TABLE (REG_0F0D) },
2899 { "femms", { XX }, 0 },
2900 { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */
2902 { PREFIX_TABLE (PREFIX_0F10) },
2903 { PREFIX_TABLE (PREFIX_0F11) },
2904 { PREFIX_TABLE (PREFIX_0F12) },
2905 { MOD_TABLE (MOD_0F13) },
2906 { "unpcklpX", { XM, EXx }, PREFIX_OPCODE },
2907 { "unpckhpX", { XM, EXx }, PREFIX_OPCODE },
2908 { PREFIX_TABLE (PREFIX_0F16) },
2909 { MOD_TABLE (MOD_0F17) },
2911 { REG_TABLE (REG_0F18) },
2912 { "nopQ", { Ev }, 0 },
2913 { PREFIX_TABLE (PREFIX_0F1A) },
2914 { PREFIX_TABLE (PREFIX_0F1B) },
2915 { PREFIX_TABLE (PREFIX_0F1C) },
2916 { "nopQ", { Ev }, 0 },
2917 { PREFIX_TABLE (PREFIX_0F1E) },
2918 { "nopQ", { Ev }, 0 },
2920 { "movZ", { Rm, Cm }, 0 },
2921 { "movZ", { Rm, Dm }, 0 },
2922 { "movZ", { Cm, Rm }, 0 },
2923 { "movZ", { Dm, Rm }, 0 },
2924 { MOD_TABLE (MOD_0F24) },
2926 { MOD_TABLE (MOD_0F26) },
2929 { "movapX", { XM, EXx }, PREFIX_OPCODE },
2930 { "movapX", { EXxS, XM }, PREFIX_OPCODE },
2931 { PREFIX_TABLE (PREFIX_0F2A) },
2932 { PREFIX_TABLE (PREFIX_0F2B) },
2933 { PREFIX_TABLE (PREFIX_0F2C) },
2934 { PREFIX_TABLE (PREFIX_0F2D) },
2935 { PREFIX_TABLE (PREFIX_0F2E) },
2936 { PREFIX_TABLE (PREFIX_0F2F) },
2938 { "wrmsr", { XX }, 0 },
2939 { "rdtsc", { XX }, 0 },
2940 { "rdmsr", { XX }, 0 },
2941 { "rdpmc", { XX }, 0 },
2942 { "sysenter", { XX }, 0 },
2943 { "sysexit", { XX }, 0 },
2945 { "getsec", { XX }, 0 },
2947 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) },
2949 { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) },
2956 { "cmovoS", { Gv, Ev }, 0 },
2957 { "cmovnoS", { Gv, Ev }, 0 },
2958 { "cmovbS", { Gv, Ev }, 0 },
2959 { "cmovaeS", { Gv, Ev }, 0 },
2960 { "cmoveS", { Gv, Ev }, 0 },
2961 { "cmovneS", { Gv, Ev }, 0 },
2962 { "cmovbeS", { Gv, Ev }, 0 },
2963 { "cmovaS", { Gv, Ev }, 0 },
2965 { "cmovsS", { Gv, Ev }, 0 },
2966 { "cmovnsS", { Gv, Ev }, 0 },
2967 { "cmovpS", { Gv, Ev }, 0 },
2968 { "cmovnpS", { Gv, Ev }, 0 },
2969 { "cmovlS", { Gv, Ev }, 0 },
2970 { "cmovgeS", { Gv, Ev }, 0 },
2971 { "cmovleS", { Gv, Ev }, 0 },
2972 { "cmovgS", { Gv, Ev }, 0 },
2974 { MOD_TABLE (MOD_0F51) },
2975 { PREFIX_TABLE (PREFIX_0F51) },
2976 { PREFIX_TABLE (PREFIX_0F52) },
2977 { PREFIX_TABLE (PREFIX_0F53) },
2978 { "andpX", { XM, EXx }, PREFIX_OPCODE },
2979 { "andnpX", { XM, EXx }, PREFIX_OPCODE },
2980 { "orpX", { XM, EXx }, PREFIX_OPCODE },
2981 { "xorpX", { XM, EXx }, PREFIX_OPCODE },
2983 { PREFIX_TABLE (PREFIX_0F58) },
2984 { PREFIX_TABLE (PREFIX_0F59) },
2985 { PREFIX_TABLE (PREFIX_0F5A) },
2986 { PREFIX_TABLE (PREFIX_0F5B) },
2987 { PREFIX_TABLE (PREFIX_0F5C) },
2988 { PREFIX_TABLE (PREFIX_0F5D) },
2989 { PREFIX_TABLE (PREFIX_0F5E) },
2990 { PREFIX_TABLE (PREFIX_0F5F) },
2992 { PREFIX_TABLE (PREFIX_0F60) },
2993 { PREFIX_TABLE (PREFIX_0F61) },
2994 { PREFIX_TABLE (PREFIX_0F62) },
2995 { "packsswb", { MX, EM }, PREFIX_OPCODE },
2996 { "pcmpgtb", { MX, EM }, PREFIX_OPCODE },
2997 { "pcmpgtw", { MX, EM }, PREFIX_OPCODE },
2998 { "pcmpgtd", { MX, EM }, PREFIX_OPCODE },
2999 { "packuswb", { MX, EM }, PREFIX_OPCODE },
3001 { "punpckhbw", { MX, EM }, PREFIX_OPCODE },
3002 { "punpckhwd", { MX, EM }, PREFIX_OPCODE },
3003 { "punpckhdq", { MX, EM }, PREFIX_OPCODE },
3004 { "packssdw", { MX, EM }, PREFIX_OPCODE },
3005 { PREFIX_TABLE (PREFIX_0F6C) },
3006 { PREFIX_TABLE (PREFIX_0F6D) },
3007 { "movK", { MX, Edq }, PREFIX_OPCODE },
3008 { PREFIX_TABLE (PREFIX_0F6F) },
3010 { PREFIX_TABLE (PREFIX_0F70) },
3011 { REG_TABLE (REG_0F71) },
3012 { REG_TABLE (REG_0F72) },
3013 { REG_TABLE (REG_0F73) },
3014 { "pcmpeqb", { MX, EM }, PREFIX_OPCODE },
3015 { "pcmpeqw", { MX, EM }, PREFIX_OPCODE },
3016 { "pcmpeqd", { MX, EM }, PREFIX_OPCODE },
3017 { "emms", { XX }, PREFIX_OPCODE },
3019 { PREFIX_TABLE (PREFIX_0F78) },
3020 { PREFIX_TABLE (PREFIX_0F79) },
3023 { PREFIX_TABLE (PREFIX_0F7C) },
3024 { PREFIX_TABLE (PREFIX_0F7D) },
3025 { PREFIX_TABLE (PREFIX_0F7E) },
3026 { PREFIX_TABLE (PREFIX_0F7F) },
3028 { "joH", { Jv, BND, cond_jump_flag }, 0 },
3029 { "jnoH", { Jv, BND, cond_jump_flag }, 0 },
3030 { "jbH", { Jv, BND, cond_jump_flag }, 0 },
3031 { "jaeH", { Jv, BND, cond_jump_flag }, 0 },
3032 { "jeH", { Jv, BND, cond_jump_flag }, 0 },
3033 { "jneH", { Jv, BND, cond_jump_flag }, 0 },
3034 { "jbeH", { Jv, BND, cond_jump_flag }, 0 },
3035 { "jaH", { Jv, BND, cond_jump_flag }, 0 },
3037 { "jsH", { Jv, BND, cond_jump_flag }, 0 },
3038 { "jnsH", { Jv, BND, cond_jump_flag }, 0 },
3039 { "jpH", { Jv, BND, cond_jump_flag }, 0 },
3040 { "jnpH", { Jv, BND, cond_jump_flag }, 0 },
3041 { "jlH", { Jv, BND, cond_jump_flag }, 0 },
3042 { "jgeH", { Jv, BND, cond_jump_flag }, 0 },
3043 { "jleH", { Jv, BND, cond_jump_flag }, 0 },
3044 { "jgH", { Jv, BND, cond_jump_flag }, 0 },
3046 { "seto", { Eb }, 0 },
3047 { "setno", { Eb }, 0 },
3048 { "setb", { Eb }, 0 },
3049 { "setae", { Eb }, 0 },
3050 { "sete", { Eb }, 0 },
3051 { "setne", { Eb }, 0 },
3052 { "setbe", { Eb }, 0 },
3053 { "seta", { Eb }, 0 },
3055 { "sets", { Eb }, 0 },
3056 { "setns", { Eb }, 0 },
3057 { "setp", { Eb }, 0 },
3058 { "setnp", { Eb }, 0 },
3059 { "setl", { Eb }, 0 },
3060 { "setge", { Eb }, 0 },
3061 { "setle", { Eb }, 0 },
3062 { "setg", { Eb }, 0 },
3064 { "pushT", { fs }, 0 },
3065 { "popT", { fs }, 0 },
3066 { "cpuid", { XX }, 0 },
3067 { "btS", { Ev, Gv }, 0 },
3068 { "shldS", { Ev, Gv, Ib }, 0 },
3069 { "shldS", { Ev, Gv, CL }, 0 },
3070 { REG_TABLE (REG_0FA6) },
3071 { REG_TABLE (REG_0FA7) },
3073 { "pushT", { gs }, 0 },
3074 { "popT", { gs }, 0 },
3075 { "rsm", { XX }, 0 },
3076 { "btsS", { Evh1, Gv }, 0 },
3077 { "shrdS", { Ev, Gv, Ib }, 0 },
3078 { "shrdS", { Ev, Gv, CL }, 0 },
3079 { REG_TABLE (REG_0FAE) },
3080 { "imulS", { Gv, Ev }, 0 },
3082 { "cmpxchgB", { Ebh1, Gb }, 0 },
3083 { "cmpxchgS", { Evh1, Gv }, 0 },
3084 { MOD_TABLE (MOD_0FB2) },
3085 { "btrS", { Evh1, Gv }, 0 },
3086 { MOD_TABLE (MOD_0FB4) },
3087 { MOD_TABLE (MOD_0FB5) },
3088 { "movz{bR|x}", { Gv, Eb }, 0 },
3089 { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
3091 { PREFIX_TABLE (PREFIX_0FB8) },
3092 { "ud1S", { Gv, Ev }, 0 },
3093 { REG_TABLE (REG_0FBA) },
3094 { "btcS", { Evh1, Gv }, 0 },
3095 { PREFIX_TABLE (PREFIX_0FBC) },
3096 { PREFIX_TABLE (PREFIX_0FBD) },
3097 { "movs{bR|x}", { Gv, Eb }, 0 },
3098 { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
3100 { "xaddB", { Ebh1, Gb }, 0 },
3101 { "xaddS", { Evh1, Gv }, 0 },
3102 { PREFIX_TABLE (PREFIX_0FC2) },
3103 { MOD_TABLE (MOD_0FC3) },
3104 { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE },
3105 { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE },
3106 { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE },
3107 { REG_TABLE (REG_0FC7) },
3109 { "bswap", { RMeAX }, 0 },
3110 { "bswap", { RMeCX }, 0 },
3111 { "bswap", { RMeDX }, 0 },
3112 { "bswap", { RMeBX }, 0 },
3113 { "bswap", { RMeSP }, 0 },
3114 { "bswap", { RMeBP }, 0 },
3115 { "bswap", { RMeSI }, 0 },
3116 { "bswap", { RMeDI }, 0 },
3118 { PREFIX_TABLE (PREFIX_0FD0) },
3119 { "psrlw", { MX, EM }, PREFIX_OPCODE },
3120 { "psrld", { MX, EM }, PREFIX_OPCODE },
3121 { "psrlq", { MX, EM }, PREFIX_OPCODE },
3122 { "paddq", { MX, EM }, PREFIX_OPCODE },
3123 { "pmullw", { MX, EM }, PREFIX_OPCODE },
3124 { PREFIX_TABLE (PREFIX_0FD6) },
3125 { MOD_TABLE (MOD_0FD7) },
3127 { "psubusb", { MX, EM }, PREFIX_OPCODE },
3128 { "psubusw", { MX, EM }, PREFIX_OPCODE },
3129 { "pminub", { MX, EM }, PREFIX_OPCODE },
3130 { "pand", { MX, EM }, PREFIX_OPCODE },
3131 { "paddusb", { MX, EM }, PREFIX_OPCODE },
3132 { "paddusw", { MX, EM }, PREFIX_OPCODE },
3133 { "pmaxub", { MX, EM }, PREFIX_OPCODE },
3134 { "pandn", { MX, EM }, PREFIX_OPCODE },
3136 { "pavgb", { MX, EM }, PREFIX_OPCODE },
3137 { "psraw", { MX, EM }, PREFIX_OPCODE },
3138 { "psrad", { MX, EM }, PREFIX_OPCODE },
3139 { "pavgw", { MX, EM }, PREFIX_OPCODE },
3140 { "pmulhuw", { MX, EM }, PREFIX_OPCODE },
3141 { "pmulhw", { MX, EM }, PREFIX_OPCODE },
3142 { PREFIX_TABLE (PREFIX_0FE6) },
3143 { PREFIX_TABLE (PREFIX_0FE7) },
3145 { "psubsb", { MX, EM }, PREFIX_OPCODE },
3146 { "psubsw", { MX, EM }, PREFIX_OPCODE },
3147 { "pminsw", { MX, EM }, PREFIX_OPCODE },
3148 { "por", { MX, EM }, PREFIX_OPCODE },
3149 { "paddsb", { MX, EM }, PREFIX_OPCODE },
3150 { "paddsw", { MX, EM }, PREFIX_OPCODE },
3151 { "pmaxsw", { MX, EM }, PREFIX_OPCODE },
3152 { "pxor", { MX, EM }, PREFIX_OPCODE },
3154 { PREFIX_TABLE (PREFIX_0FF0) },
3155 { "psllw", { MX, EM }, PREFIX_OPCODE },
3156 { "pslld", { MX, EM }, PREFIX_OPCODE },
3157 { "psllq", { MX, EM }, PREFIX_OPCODE },
3158 { "pmuludq", { MX, EM }, PREFIX_OPCODE },
3159 { "pmaddwd", { MX, EM }, PREFIX_OPCODE },
3160 { "psadbw", { MX, EM }, PREFIX_OPCODE },
3161 { PREFIX_TABLE (PREFIX_0FF7) },
3163 { "psubb", { MX, EM }, PREFIX_OPCODE },
3164 { "psubw", { MX, EM }, PREFIX_OPCODE },
3165 { "psubd", { MX, EM }, PREFIX_OPCODE },
3166 { "psubq", { MX, EM }, PREFIX_OPCODE },
3167 { "paddb", { MX, EM }, PREFIX_OPCODE },
3168 { "paddw", { MX, EM }, PREFIX_OPCODE },
3169 { "paddd", { MX, EM }, PREFIX_OPCODE },
3170 { "ud0S", { Gv, Ev }, 0 },
3173 static const unsigned char onebyte_has_modrm[256] = {
3174 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3175 /* ------------------------------- */
3176 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
3177 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
3178 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
3179 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
3180 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
3181 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
3182 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
3183 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
3184 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
3185 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
3186 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
3187 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
3188 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
3189 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
3190 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
3191 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
3192 /* ------------------------------- */
3193 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3196 static const unsigned char twobyte_has_modrm[256] = {
3197 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3198 /* ------------------------------- */
3199 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
3200 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
3201 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
3202 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
3203 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
3204 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
3205 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
3206 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
3207 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
3208 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
3209 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
3210 /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
3211 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
3212 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
3213 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
3214 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
3215 /* ------------------------------- */
3216 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
3219 static char obuf[100];
3221 static char *mnemonicendp;
3222 static char scratchbuf[100];
3223 static unsigned char *start_codep;
3224 static unsigned char *insn_codep;
3225 static unsigned char *codep;
3226 static unsigned char *end_codep;
3227 static int last_lock_prefix;
3228 static int last_repz_prefix;
3229 static int last_repnz_prefix;
3230 static int last_data_prefix;
3231 static int last_addr_prefix;
3232 static int last_rex_prefix;
3233 static int last_seg_prefix;
3234 static int fwait_prefix;
3235 /* The active segment register prefix. */
3236 static int active_seg_prefix;
3237 #define MAX_CODE_LENGTH 15
3238 /* We can up to 14 prefixes since the maximum instruction length is
3240 static int all_prefixes[MAX_CODE_LENGTH - 1];
3241 static disassemble_info *the_info;
3249 static unsigned char need_modrm;
3259 int register_specifier;
3266 int mask_register_specifier;
3272 static unsigned char need_vex;
3273 static unsigned char need_vex_reg;
3274 static unsigned char vex_w_done;
3282 /* If we are accessing mod/rm/reg without need_modrm set, then the
3283 values are stale. Hitting this abort likely indicates that you
3284 need to update onebyte_has_modrm or twobyte_has_modrm. */
3285 #define MODRM_CHECK if (!need_modrm) abort ()
3287 static const char **names64;
3288 static const char **names32;
3289 static const char **names16;
3290 static const char **names8;
3291 static const char **names8rex;
3292 static const char **names_seg;
3293 static const char *index64;
3294 static const char *index32;
3295 static const char **index16;
3296 static const char **names_bnd;
3298 static const char *intel_names64[] = {
3299 "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
3300 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3302 static const char *intel_names32[] = {
3303 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
3304 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
3306 static const char *intel_names16[] = {
3307 "ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
3308 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
3310 static const char *intel_names8[] = {
3311 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh",
3313 static const char *intel_names8rex[] = {
3314 "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
3315 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
3317 static const char *intel_names_seg[] = {
3318 "es", "cs", "ss", "ds", "fs", "gs", "?", "?",
3320 static const char *intel_index64 = "riz";
3321 static const char *intel_index32 = "eiz";
3322 static const char *intel_index16[] = {
3323 "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
3326 static const char *att_names64[] = {
3327 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
3328 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15"
3330 static const char *att_names32[] = {
3331 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
3332 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d"
3334 static const char *att_names16[] = {
3335 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
3336 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w"
3338 static const char *att_names8[] = {
3339 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
3341 static const char *att_names8rex[] = {
3342 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
3343 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b"
3345 static const char *att_names_seg[] = {
3346 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
3348 static const char *att_index64 = "%riz";
3349 static const char *att_index32 = "%eiz";
3350 static const char *att_index16[] = {
3351 "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
3354 static const char **names_mm;
3355 static const char *intel_names_mm[] = {
3356 "mm0", "mm1", "mm2", "mm3",
3357 "mm4", "mm5", "mm6", "mm7"
3359 static const char *att_names_mm[] = {
3360 "%mm0", "%mm1", "%mm2", "%mm3",
3361 "%mm4", "%mm5", "%mm6", "%mm7"
3364 static const char *intel_names_bnd[] = {
3365 "bnd0", "bnd1", "bnd2", "bnd3"
3368 static const char *att_names_bnd[] = {
3369 "%bnd0", "%bnd1", "%bnd2", "%bnd3"
3372 static const char **names_xmm;
3373 static const char *intel_names_xmm[] = {
3374 "xmm0", "xmm1", "xmm2", "xmm3",
3375 "xmm4", "xmm5", "xmm6", "xmm7",
3376 "xmm8", "xmm9", "xmm10", "xmm11",
3377 "xmm12", "xmm13", "xmm14", "xmm15",
3378 "xmm16", "xmm17", "xmm18", "xmm19",
3379 "xmm20", "xmm21", "xmm22", "xmm23",
3380 "xmm24", "xmm25", "xmm26", "xmm27",
3381 "xmm28", "xmm29", "xmm30", "xmm31"
3383 static const char *att_names_xmm[] = {
3384 "%xmm0", "%xmm1", "%xmm2", "%xmm3",
3385 "%xmm4", "%xmm5", "%xmm6", "%xmm7",
3386 "%xmm8", "%xmm9", "%xmm10", "%xmm11",
3387 "%xmm12", "%xmm13", "%xmm14", "%xmm15",
3388 "%xmm16", "%xmm17", "%xmm18", "%xmm19",
3389 "%xmm20", "%xmm21", "%xmm22", "%xmm23",
3390 "%xmm24", "%xmm25", "%xmm26", "%xmm27",
3391 "%xmm28", "%xmm29", "%xmm30", "%xmm31"
3394 static const char **names_ymm;
3395 static const char *intel_names_ymm[] = {
3396 "ymm0", "ymm1", "ymm2", "ymm3",
3397 "ymm4", "ymm5", "ymm6", "ymm7",
3398 "ymm8", "ymm9", "ymm10", "ymm11",
3399 "ymm12", "ymm13", "ymm14", "ymm15",
3400 "ymm16", "ymm17", "ymm18", "ymm19",
3401 "ymm20", "ymm21", "ymm22", "ymm23",
3402 "ymm24", "ymm25", "ymm26", "ymm27",
3403 "ymm28", "ymm29", "ymm30", "ymm31"
3405 static const char *att_names_ymm[] = {
3406 "%ymm0", "%ymm1", "%ymm2", "%ymm3",
3407 "%ymm4", "%ymm5", "%ymm6", "%ymm7",
3408 "%ymm8", "%ymm9", "%ymm10", "%ymm11",
3409 "%ymm12", "%ymm13", "%ymm14", "%ymm15",
3410 "%ymm16", "%ymm17", "%ymm18", "%ymm19",
3411 "%ymm20", "%ymm21", "%ymm22", "%ymm23",
3412 "%ymm24", "%ymm25", "%ymm26", "%ymm27",
3413 "%ymm28", "%ymm29", "%ymm30", "%ymm31"
3416 static const char **names_zmm;
3417 static const char *intel_names_zmm[] = {
3418 "zmm0", "zmm1", "zmm2", "zmm3",
3419 "zmm4", "zmm5", "zmm6", "zmm7",
3420 "zmm8", "zmm9", "zmm10", "zmm11",
3421 "zmm12", "zmm13", "zmm14", "zmm15",
3422 "zmm16", "zmm17", "zmm18", "zmm19",
3423 "zmm20", "zmm21", "zmm22", "zmm23",
3424 "zmm24", "zmm25", "zmm26", "zmm27",
3425 "zmm28", "zmm29", "zmm30", "zmm31"
3427 static const char *att_names_zmm[] = {
3428 "%zmm0", "%zmm1", "%zmm2", "%zmm3",
3429 "%zmm4", "%zmm5", "%zmm6", "%zmm7",
3430 "%zmm8", "%zmm9", "%zmm10", "%zmm11",
3431 "%zmm12", "%zmm13", "%zmm14", "%zmm15",
3432 "%zmm16", "%zmm17", "%zmm18", "%zmm19",
3433 "%zmm20", "%zmm21", "%zmm22", "%zmm23",
3434 "%zmm24", "%zmm25", "%zmm26", "%zmm27",
3435 "%zmm28", "%zmm29", "%zmm30", "%zmm31"
3438 static const char **names_mask;
3439 static const char *intel_names_mask[] = {
3440 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
3442 static const char *att_names_mask[] = {
3443 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
3446 static const char *names_rounding[] =
3454 static const struct dis386 reg_table[][8] = {
3457 { "addA", { Ebh1, Ib }, 0 },
3458 { "orA", { Ebh1, Ib }, 0 },
3459 { "adcA", { Ebh1, Ib }, 0 },
3460 { "sbbA", { Ebh1, Ib }, 0 },
3461 { "andA", { Ebh1, Ib }, 0 },
3462 { "subA", { Ebh1, Ib }, 0 },
3463 { "xorA", { Ebh1, Ib }, 0 },
3464 { "cmpA", { Eb, Ib }, 0 },
3468 { "addQ", { Evh1, Iv }, 0 },
3469 { "orQ", { Evh1, Iv }, 0 },
3470 { "adcQ", { Evh1, Iv }, 0 },
3471 { "sbbQ", { Evh1, Iv }, 0 },
3472 { "andQ", { Evh1, Iv }, 0 },
3473 { "subQ", { Evh1, Iv }, 0 },
3474 { "xorQ", { Evh1, Iv }, 0 },
3475 { "cmpQ", { Ev, Iv }, 0 },
3479 { "addQ", { Evh1, sIb }, 0 },
3480 { "orQ", { Evh1, sIb }, 0 },
3481 { "adcQ", { Evh1, sIb }, 0 },
3482 { "sbbQ", { Evh1, sIb }, 0 },
3483 { "andQ", { Evh1, sIb }, 0 },
3484 { "subQ", { Evh1, sIb }, 0 },
3485 { "xorQ", { Evh1, sIb }, 0 },
3486 { "cmpQ", { Ev, sIb }, 0 },
3490 { "popU", { stackEv }, 0 },
3491 { XOP_8F_TABLE (XOP_09) },
3495 { XOP_8F_TABLE (XOP_09) },
3499 { "rolA", { Eb, Ib }, 0 },
3500 { "rorA", { Eb, Ib }, 0 },
3501 { "rclA", { Eb, Ib }, 0 },
3502 { "rcrA", { Eb, Ib }, 0 },
3503 { "shlA", { Eb, Ib }, 0 },
3504 { "shrA", { Eb, Ib }, 0 },
3505 { "shlA", { Eb, Ib }, 0 },
3506 { "sarA", { Eb, Ib }, 0 },
3510 { "rolQ", { Ev, Ib }, 0 },
3511 { "rorQ", { Ev, Ib }, 0 },
3512 { "rclQ", { Ev, Ib }, 0 },
3513 { "rcrQ", { Ev, Ib }, 0 },
3514 { "shlQ", { Ev, Ib }, 0 },
3515 { "shrQ", { Ev, Ib }, 0 },
3516 { "shlQ", { Ev, Ib }, 0 },
3517 { "sarQ", { Ev, Ib }, 0 },
3521 { "movA", { Ebh3, Ib }, 0 },
3528 { MOD_TABLE (MOD_C6_REG_7) },
3532 { "movQ", { Evh3, Iv }, 0 },
3539 { MOD_TABLE (MOD_C7_REG_7) },
3543 { "rolA", { Eb, I1 }, 0 },
3544 { "rorA", { Eb, I1 }, 0 },
3545 { "rclA", { Eb, I1 }, 0 },
3546 { "rcrA", { Eb, I1 }, 0 },
3547 { "shlA", { Eb, I1 }, 0 },
3548 { "shrA", { Eb, I1 }, 0 },
3549 { "shlA", { Eb, I1 }, 0 },
3550 { "sarA", { Eb, I1 }, 0 },
3554 { "rolQ", { Ev, I1 }, 0 },
3555 { "rorQ", { Ev, I1 }, 0 },
3556 { "rclQ", { Ev, I1 }, 0 },
3557 { "rcrQ", { Ev, I1 }, 0 },
3558 { "shlQ", { Ev, I1 }, 0 },
3559 { "shrQ", { Ev, I1 }, 0 },
3560 { "shlQ", { Ev, I1 }, 0 },
3561 { "sarQ", { Ev, I1 }, 0 },
3565 { "rolA", { Eb, CL }, 0 },
3566 { "rorA", { Eb, CL }, 0 },
3567 { "rclA", { Eb, CL }, 0 },
3568 { "rcrA", { Eb, CL }, 0 },
3569 { "shlA", { Eb, CL }, 0 },
3570 { "shrA", { Eb, CL }, 0 },
3571 { "shlA", { Eb, CL }, 0 },
3572 { "sarA", { Eb, CL }, 0 },
3576 { "rolQ", { Ev, CL }, 0 },
3577 { "rorQ", { Ev, CL }, 0 },
3578 { "rclQ", { Ev, CL }, 0 },
3579 { "rcrQ", { Ev, CL }, 0 },
3580 { "shlQ", { Ev, CL }, 0 },
3581 { "shrQ", { Ev, CL }, 0 },
3582 { "shlQ", { Ev, CL }, 0 },
3583 { "sarQ", { Ev, CL }, 0 },
3587 { "testA", { Eb, Ib }, 0 },
3588 { "testA", { Eb, Ib }, 0 },
3589 { "notA", { Ebh1 }, 0 },
3590 { "negA", { Ebh1 }, 0 },
3591 { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */
3592 { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */
3593 { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */
3594 { "idivA", { Eb }, 0 }, /* and idiv for consistency. */
3598 { "testQ", { Ev, Iv }, 0 },
3599 { "testQ", { Ev, Iv }, 0 },
3600 { "notQ", { Evh1 }, 0 },
3601 { "negQ", { Evh1 }, 0 },
3602 { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */
3603 { "imulQ", { Ev }, 0 },
3604 { "divQ", { Ev }, 0 },
3605 { "idivQ", { Ev }, 0 },
3609 { "incA", { Ebh1 }, 0 },
3610 { "decA", { Ebh1 }, 0 },
3614 { "incQ", { Evh1 }, 0 },
3615 { "decQ", { Evh1 }, 0 },
3616 { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
3617 { MOD_TABLE (MOD_FF_REG_3) },
3618 { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
3619 { MOD_TABLE (MOD_FF_REG_5) },
3620 { "pushU", { stackEv }, 0 },
3625 { "sldtD", { Sv }, 0 },
3626 { "strD", { Sv }, 0 },
3627 { "lldt", { Ew }, 0 },
3628 { "ltr", { Ew }, 0 },
3629 { "verr", { Ew }, 0 },
3630 { "verw", { Ew }, 0 },
3636 { MOD_TABLE (MOD_0F01_REG_0) },
3637 { MOD_TABLE (MOD_0F01_REG_1) },
3638 { MOD_TABLE (MOD_0F01_REG_2) },
3639 { MOD_TABLE (MOD_0F01_REG_3) },
3640 { "smswD", { Sv }, 0 },
3641 { MOD_TABLE (MOD_0F01_REG_5) },
3642 { "lmsw", { Ew }, 0 },
3643 { MOD_TABLE (MOD_0F01_REG_7) },
3647 { "prefetch", { Mb }, 0 },
3648 { "prefetchw", { Mb }, 0 },
3649 { "prefetchwt1", { Mb }, 0 },
3650 { "prefetch", { Mb }, 0 },
3651 { "prefetch", { Mb }, 0 },
3652 { "prefetch", { Mb }, 0 },
3653 { "prefetch", { Mb }, 0 },
3654 { "prefetch", { Mb }, 0 },
3658 { MOD_TABLE (MOD_0F18_REG_0) },
3659 { MOD_TABLE (MOD_0F18_REG_1) },
3660 { MOD_TABLE (MOD_0F18_REG_2) },
3661 { MOD_TABLE (MOD_0F18_REG_3) },
3662 { MOD_TABLE (MOD_0F18_REG_4) },
3663 { MOD_TABLE (MOD_0F18_REG_5) },
3664 { MOD_TABLE (MOD_0F18_REG_6) },
3665 { MOD_TABLE (MOD_0F18_REG_7) },
3667 /* REG_0F1C_MOD_0 */
3669 { "cldemote", { Mb }, 0 },
3670 { "nopQ", { Ev }, 0 },
3671 { "nopQ", { Ev }, 0 },
3672 { "nopQ", { Ev }, 0 },
3673 { "nopQ", { Ev }, 0 },
3674 { "nopQ", { Ev }, 0 },
3675 { "nopQ", { Ev }, 0 },
3676 { "nopQ", { Ev }, 0 },
3678 /* REG_0F1E_MOD_3 */
3680 { "nopQ", { Ev }, 0 },
3681 { "rdsspK", { Rdq }, PREFIX_OPCODE },
3682 { "nopQ", { Ev }, 0 },
3683 { "nopQ", { Ev }, 0 },
3684 { "nopQ", { Ev }, 0 },
3685 { "nopQ", { Ev }, 0 },
3686 { "nopQ", { Ev }, 0 },
3687 { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
3693 { MOD_TABLE (MOD_0F71_REG_2) },
3695 { MOD_TABLE (MOD_0F71_REG_4) },
3697 { MOD_TABLE (MOD_0F71_REG_6) },
3703 { MOD_TABLE (MOD_0F72_REG_2) },
3705 { MOD_TABLE (MOD_0F72_REG_4) },
3707 { MOD_TABLE (MOD_0F72_REG_6) },
3713 { MOD_TABLE (MOD_0F73_REG_2) },
3714 { MOD_TABLE (MOD_0F73_REG_3) },
3717 { MOD_TABLE (MOD_0F73_REG_6) },
3718 { MOD_TABLE (MOD_0F73_REG_7) },
3722 { "montmul", { { OP_0f07, 0 } }, 0 },
3723 { "xsha1", { { OP_0f07, 0 } }, 0 },
3724 { "xsha256", { { OP_0f07, 0 } }, 0 },
3728 { "xstore-rng", { { OP_0f07, 0 } }, 0 },
3729 { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 },
3730 { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 },
3731 { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 },
3732 { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 },
3733 { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 },
3737 { MOD_TABLE (MOD_0FAE_REG_0) },
3738 { MOD_TABLE (MOD_0FAE_REG_1) },
3739 { MOD_TABLE (MOD_0FAE_REG_2) },
3740 { MOD_TABLE (MOD_0FAE_REG_3) },
3741 { MOD_TABLE (MOD_0FAE_REG_4) },
3742 { MOD_TABLE (MOD_0FAE_REG_5) },
3743 { MOD_TABLE (MOD_0FAE_REG_6) },
3744 { MOD_TABLE (MOD_0FAE_REG_7) },
3752 { "btQ", { Ev, Ib }, 0 },
3753 { "btsQ", { Evh1, Ib }, 0 },
3754 { "btrQ", { Evh1, Ib }, 0 },
3755 { "btcQ", { Evh1, Ib }, 0 },
3760 { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
3762 { MOD_TABLE (MOD_0FC7_REG_3) },
3763 { MOD_TABLE (MOD_0FC7_REG_4) },
3764 { MOD_TABLE (MOD_0FC7_REG_5) },
3765 { MOD_TABLE (MOD_0FC7_REG_6) },
3766 { MOD_TABLE (MOD_0FC7_REG_7) },
3772 { MOD_TABLE (MOD_VEX_0F71_REG_2) },
3774 { MOD_TABLE (MOD_VEX_0F71_REG_4) },
3776 { MOD_TABLE (MOD_VEX_0F71_REG_6) },
3782 { MOD_TABLE (MOD_VEX_0F72_REG_2) },
3784 { MOD_TABLE (MOD_VEX_0F72_REG_4) },
3786 { MOD_TABLE (MOD_VEX_0F72_REG_6) },
3792 { MOD_TABLE (MOD_VEX_0F73_REG_2) },
3793 { MOD_TABLE (MOD_VEX_0F73_REG_3) },
3796 { MOD_TABLE (MOD_VEX_0F73_REG_6) },
3797 { MOD_TABLE (MOD_VEX_0F73_REG_7) },
3803 { MOD_TABLE (MOD_VEX_0FAE_REG_2) },
3804 { MOD_TABLE (MOD_VEX_0FAE_REG_3) },
3806 /* REG_VEX_0F38F3 */
3809 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
3810 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
3811 { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
3815 { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3816 { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
3820 { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3821 { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
3823 /* REG_XOP_TBM_01 */
3826 { "blcfill", { { OP_LWP_E, 0 }, Ev }, 0 },
3827 { "blsfill", { { OP_LWP_E, 0 }, Ev }, 0 },
3828 { "blcs", { { OP_LWP_E, 0 }, Ev }, 0 },
3829 { "tzmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3830 { "blcic", { { OP_LWP_E, 0 }, Ev }, 0 },
3831 { "blsic", { { OP_LWP_E, 0 }, Ev }, 0 },
3832 { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
3834 /* REG_XOP_TBM_02 */
3837 { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
3842 { "blci", { { OP_LWP_E, 0 }, Ev }, 0 },
3844 #define NEED_REG_TABLE
3845 #include "i386-dis-evex.h"
3846 #undef NEED_REG_TABLE
3849 static const struct dis386 prefix_table[][4] = {
3852 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3853 { "pause", { XX }, 0 },
3854 { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 },
3855 { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
3858 /* PREFIX_MOD_0_0F01_REG_5 */
3861 { "rstorssp", { Mq }, PREFIX_OPCODE },
3864 /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
3867 { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE },
3870 /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
3873 { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE },
3878 { "wbinvd", { XX }, 0 },
3879 { "wbnoinvd", { XX }, 0 },
3884 { "movups", { XM, EXx }, PREFIX_OPCODE },
3885 { "movss", { XM, EXd }, PREFIX_OPCODE },
3886 { "movupd", { XM, EXx }, PREFIX_OPCODE },
3887 { "movsd", { XM, EXq }, PREFIX_OPCODE },
3892 { "movups", { EXxS, XM }, PREFIX_OPCODE },
3893 { "movss", { EXdS, XM }, PREFIX_OPCODE },
3894 { "movupd", { EXxS, XM }, PREFIX_OPCODE },
3895 { "movsd", { EXqS, XM }, PREFIX_OPCODE },
3900 { MOD_TABLE (MOD_0F12_PREFIX_0) },
3901 { "movsldup", { XM, EXx }, PREFIX_OPCODE },
3902 { "movlpd", { XM, EXq }, PREFIX_OPCODE },
3903 { "movddup", { XM, EXq }, PREFIX_OPCODE },
3908 { MOD_TABLE (MOD_0F16_PREFIX_0) },
3909 { "movshdup", { XM, EXx }, PREFIX_OPCODE },
3910 { "movhpd", { XM, EXq }, PREFIX_OPCODE },
3915 { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3916 { "bndcl", { Gbnd, Ev_bnd }, 0 },
3917 { "bndmov", { Gbnd, Ebnd }, 0 },
3918 { "bndcu", { Gbnd, Ev_bnd }, 0 },
3923 { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3924 { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3925 { "bndmov", { EbndS, Gbnd }, 0 },
3926 { "bndcn", { Gbnd, Ev_bnd }, 0 },
3931 { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3932 { "nopQ", { Ev }, PREFIX_OPCODE },
3933 { "nopQ", { Ev }, PREFIX_OPCODE },
3934 { "nopQ", { Ev }, PREFIX_OPCODE },
3939 { "nopQ", { Ev }, PREFIX_OPCODE },
3940 { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3941 { "nopQ", { Ev }, PREFIX_OPCODE },
3942 { "nopQ", { Ev }, PREFIX_OPCODE },
3947 { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3948 { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
3949 { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3950 { "cvtsi2sd%LQ", { XM, Ev }, 0 },
3955 { MOD_TABLE (MOD_0F2B_PREFIX_0) },
3956 { MOD_TABLE (MOD_0F2B_PREFIX_1) },
3957 { MOD_TABLE (MOD_0F2B_PREFIX_2) },
3958 { MOD_TABLE (MOD_0F2B_PREFIX_3) },
3963 { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3964 { "cvttss2si", { Gv, EXd }, PREFIX_OPCODE },
3965 { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3966 { "cvttsd2si", { Gv, EXq }, PREFIX_OPCODE },
3971 { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3972 { "cvtss2si", { Gv, EXd }, PREFIX_OPCODE },
3973 { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3974 { "cvtsd2si", { Gv, EXq }, PREFIX_OPCODE },
3979 { "ucomiss",{ XM, EXd }, 0 },
3981 { "ucomisd",{ XM, EXq }, 0 },
3986 { "comiss", { XM, EXd }, 0 },
3988 { "comisd", { XM, EXq }, 0 },
3993 { "sqrtps", { XM, EXx }, PREFIX_OPCODE },
3994 { "sqrtss", { XM, EXd }, PREFIX_OPCODE },
3995 { "sqrtpd", { XM, EXx }, PREFIX_OPCODE },
3996 { "sqrtsd", { XM, EXq }, PREFIX_OPCODE },
4001 { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE },
4002 { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE },
4007 { "rcpps", { XM, EXx }, PREFIX_OPCODE },
4008 { "rcpss", { XM, EXd }, PREFIX_OPCODE },
4013 { "addps", { XM, EXx }, PREFIX_OPCODE },
4014 { "addss", { XM, EXd }, PREFIX_OPCODE },
4015 { "addpd", { XM, EXx }, PREFIX_OPCODE },
4016 { "addsd", { XM, EXq }, PREFIX_OPCODE },
4021 { "mulps", { XM, EXx }, PREFIX_OPCODE },
4022 { "mulss", { XM, EXd }, PREFIX_OPCODE },
4023 { "mulpd", { XM, EXx }, PREFIX_OPCODE },
4024 { "mulsd", { XM, EXq }, PREFIX_OPCODE },
4029 { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE },
4030 { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE },
4031 { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE },
4032 { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE },
4037 { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE },
4038 { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE },
4039 { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE },
4044 { "subps", { XM, EXx }, PREFIX_OPCODE },
4045 { "subss", { XM, EXd }, PREFIX_OPCODE },
4046 { "subpd", { XM, EXx }, PREFIX_OPCODE },
4047 { "subsd", { XM, EXq }, PREFIX_OPCODE },
4052 { "minps", { XM, EXx }, PREFIX_OPCODE },
4053 { "minss", { XM, EXd }, PREFIX_OPCODE },
4054 { "minpd", { XM, EXx }, PREFIX_OPCODE },
4055 { "minsd", { XM, EXq }, PREFIX_OPCODE },
4060 { "divps", { XM, EXx }, PREFIX_OPCODE },
4061 { "divss", { XM, EXd }, PREFIX_OPCODE },
4062 { "divpd", { XM, EXx }, PREFIX_OPCODE },
4063 { "divsd", { XM, EXq }, PREFIX_OPCODE },
4068 { "maxps", { XM, EXx }, PREFIX_OPCODE },
4069 { "maxss", { XM, EXd }, PREFIX_OPCODE },
4070 { "maxpd", { XM, EXx }, PREFIX_OPCODE },
4071 { "maxsd", { XM, EXq }, PREFIX_OPCODE },
4076 { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
4078 { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
4083 { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
4085 { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
4090 { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
4092 { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
4099 { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
4106 { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
4111 { "movq", { MX, EM }, PREFIX_OPCODE },
4112 { "movdqu", { XM, EXx }, PREFIX_OPCODE },
4113 { "movdqa", { XM, EXx }, PREFIX_OPCODE },
4118 { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
4119 { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4120 { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
4121 { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
4124 /* PREFIX_0F73_REG_3 */
4128 { "psrldq", { XS, Ib }, 0 },
4131 /* PREFIX_0F73_REG_7 */
4135 { "pslldq", { XS, Ib }, 0 },
4140 {"vmread", { Em, Gm }, 0 },
4142 {"extrq", { XS, Ib, Ib }, 0 },
4143 {"insertq", { XM, XS, Ib, Ib }, 0 },
4148 {"vmwrite", { Gm, Em }, 0 },
4150 {"extrq", { XM, XS }, 0 },
4151 {"insertq", { XM, XS }, 0 },
4158 { "haddpd", { XM, EXx }, PREFIX_OPCODE },
4159 { "haddps", { XM, EXx }, PREFIX_OPCODE },
4166 { "hsubpd", { XM, EXx }, PREFIX_OPCODE },
4167 { "hsubps", { XM, EXx }, PREFIX_OPCODE },
4172 { "movK", { Edq, MX }, PREFIX_OPCODE },
4173 { "movq", { XM, EXq }, PREFIX_OPCODE },
4174 { "movK", { Edq, XM }, PREFIX_OPCODE },
4179 { "movq", { EMS, MX }, PREFIX_OPCODE },
4180 { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
4181 { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
4184 /* PREFIX_0FAE_REG_0 */
4187 { "rdfsbase", { Ev }, 0 },
4190 /* PREFIX_0FAE_REG_1 */
4193 { "rdgsbase", { Ev }, 0 },
4196 /* PREFIX_0FAE_REG_2 */
4199 { "wrfsbase", { Ev }, 0 },
4202 /* PREFIX_0FAE_REG_3 */
4205 { "wrgsbase", { Ev }, 0 },
4208 /* PREFIX_MOD_0_0FAE_REG_4 */
4210 { "xsave", { FXSAVE }, 0 },
4211 { "ptwrite%LQ", { Edq }, 0 },
4214 /* PREFIX_MOD_3_0FAE_REG_4 */
4217 { "ptwrite%LQ", { Edq }, 0 },
4220 /* PREFIX_MOD_0_0FAE_REG_5 */
4222 { "xrstor", { FXSAVE }, PREFIX_OPCODE },
4225 /* PREFIX_MOD_3_0FAE_REG_5 */
4227 { "lfence", { Skip_MODRM }, 0 },
4228 { "incsspK", { Rdq }, PREFIX_OPCODE },
4231 /* PREFIX_MOD_0_0FAE_REG_6 */
4233 { "xsaveopt", { FXSAVE }, PREFIX_OPCODE },
4234 { "clrssbsy", { Mq }, PREFIX_OPCODE },
4235 { "clwb", { Mb }, PREFIX_OPCODE },
4238 /* PREFIX_MOD_1_0FAE_REG_6 */
4240 { RM_TABLE (RM_0FAE_REG_6) },
4241 { "umonitor", { Eva }, PREFIX_OPCODE },
4242 { "tpause", { Edq }, PREFIX_OPCODE },
4243 { "umwait", { Edq }, PREFIX_OPCODE },
4246 /* PREFIX_0FAE_REG_7 */
4248 { "clflush", { Mb }, 0 },
4250 { "clflushopt", { Mb }, 0 },
4256 { "popcntS", { Gv, Ev }, 0 },
4261 { "bsfS", { Gv, Ev }, 0 },
4262 { "tzcntS", { Gv, Ev }, 0 },
4263 { "bsfS", { Gv, Ev }, 0 },
4268 { "bsrS", { Gv, Ev }, 0 },
4269 { "lzcntS", { Gv, Ev }, 0 },
4270 { "bsrS", { Gv, Ev }, 0 },
4275 { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE },
4276 { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE },
4277 { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE },
4278 { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE },
4281 /* PREFIX_MOD_0_0FC3 */
4283 { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
4286 /* PREFIX_MOD_0_0FC7_REG_6 */
4288 { "vmptrld",{ Mq }, 0 },
4289 { "vmxon", { Mq }, 0 },
4290 { "vmclear",{ Mq }, 0 },
4293 /* PREFIX_MOD_3_0FC7_REG_6 */
4295 { "rdrand", { Ev }, 0 },
4297 { "rdrand", { Ev }, 0 }
4300 /* PREFIX_MOD_3_0FC7_REG_7 */
4302 { "rdseed", { Ev }, 0 },
4303 { "rdpid", { Em }, 0 },
4304 { "rdseed", { Ev }, 0 },
4311 { "addsubpd", { XM, EXx }, 0 },
4312 { "addsubps", { XM, EXx }, 0 },
4318 { "movq2dq",{ XM, MS }, 0 },
4319 { "movq", { EXqS, XM }, 0 },
4320 { "movdq2q",{ MX, XS }, 0 },
4326 { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE },
4327 { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE },
4328 { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE },
4333 { "movntq", { Mq, MX }, PREFIX_OPCODE },
4335 { MOD_TABLE (MOD_0FE7_PREFIX_2) },
4343 { MOD_TABLE (MOD_0FF0_PREFIX_3) },
4348 { "maskmovq", { MX, MS }, PREFIX_OPCODE },
4350 { "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
4357 { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4364 { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4371 { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
4378 { "ptest", { XM, EXx }, PREFIX_OPCODE },
4385 { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
4392 { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
4399 { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
4406 { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
4413 { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
4420 { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
4427 { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
4434 { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
4441 { MOD_TABLE (MOD_0F382A_PREFIX_2) },
4448 { "packusdw", { XM, EXx }, PREFIX_OPCODE },
4455 { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
4462 { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
4469 { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
4476 { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
4483 { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
4490 { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
4497 { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
4504 { "pminsb", { XM, EXx }, PREFIX_OPCODE },
4511 { "pminsd", { XM, EXx }, PREFIX_OPCODE },
4518 { "pminuw", { XM, EXx }, PREFIX_OPCODE },
4525 { "pminud", { XM, EXx }, PREFIX_OPCODE },
4532 { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
4539 { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
4546 { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
4553 { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
4560 { "pmulld", { XM, EXx }, PREFIX_OPCODE },
4567 { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
4574 { "invept", { Gm, Mo }, PREFIX_OPCODE },
4581 { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
4588 { "invpcid", { Gm, M }, PREFIX_OPCODE },
4593 { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4598 { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4603 { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4608 { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4613 { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4618 { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4625 { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
4632 { "aesimc", { XM, EXx }, PREFIX_OPCODE },
4639 { "aesenc", { XM, EXx }, PREFIX_OPCODE },
4646 { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
4653 { "aesdec", { XM, EXx }, PREFIX_OPCODE },
4660 { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
4665 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4667 { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
4668 { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
4673 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4675 { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
4676 { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
4683 { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
4688 { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
4689 { "adoxS", { Gdq, Edq}, PREFIX_OPCODE },
4690 { "adcxS", { Gdq, Edq}, PREFIX_OPCODE },
4698 { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
4703 { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
4710 { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
4717 { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4724 { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
4731 { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
4738 { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
4745 { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
4752 { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
4759 { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
4766 { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
4773 { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
4780 { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
4787 { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
4794 { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
4801 { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
4808 { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE },
4815 { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE },
4822 { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
4829 { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
4836 { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4843 { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
4850 { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
4857 { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
4862 { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4869 { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4876 { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
4883 { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
4886 /* PREFIX_VEX_0F10 */
4888 { VEX_W_TABLE (VEX_W_0F10_P_0) },
4889 { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
4890 { VEX_W_TABLE (VEX_W_0F10_P_2) },
4891 { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
4894 /* PREFIX_VEX_0F11 */
4896 { VEX_W_TABLE (VEX_W_0F11_P_0) },
4897 { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
4898 { VEX_W_TABLE (VEX_W_0F11_P_2) },
4899 { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
4902 /* PREFIX_VEX_0F12 */
4904 { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
4905 { VEX_W_TABLE (VEX_W_0F12_P_1) },
4906 { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
4907 { VEX_W_TABLE (VEX_W_0F12_P_3) },
4910 /* PREFIX_VEX_0F16 */
4912 { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
4913 { VEX_W_TABLE (VEX_W_0F16_P_1) },
4914 { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
4917 /* PREFIX_VEX_0F2A */
4920 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
4922 { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
4925 /* PREFIX_VEX_0F2C */
4928 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
4930 { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
4933 /* PREFIX_VEX_0F2D */
4936 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
4938 { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
4941 /* PREFIX_VEX_0F2E */
4943 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
4945 { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
4948 /* PREFIX_VEX_0F2F */
4950 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
4952 { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
4955 /* PREFIX_VEX_0F41 */
4957 { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
4959 { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
4962 /* PREFIX_VEX_0F42 */
4964 { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
4966 { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
4969 /* PREFIX_VEX_0F44 */
4971 { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
4973 { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
4976 /* PREFIX_VEX_0F45 */
4978 { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
4980 { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
4983 /* PREFIX_VEX_0F46 */
4985 { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
4987 { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
4990 /* PREFIX_VEX_0F47 */
4992 { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
4994 { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
4997 /* PREFIX_VEX_0F4A */
4999 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
5001 { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
5004 /* PREFIX_VEX_0F4B */
5006 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
5008 { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
5011 /* PREFIX_VEX_0F51 */
5013 { VEX_W_TABLE (VEX_W_0F51_P_0) },
5014 { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
5015 { VEX_W_TABLE (VEX_W_0F51_P_2) },
5016 { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
5019 /* PREFIX_VEX_0F52 */
5021 { VEX_W_TABLE (VEX_W_0F52_P_0) },
5022 { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
5025 /* PREFIX_VEX_0F53 */
5027 { VEX_W_TABLE (VEX_W_0F53_P_0) },
5028 { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
5031 /* PREFIX_VEX_0F58 */
5033 { VEX_W_TABLE (VEX_W_0F58_P_0) },
5034 { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
5035 { VEX_W_TABLE (VEX_W_0F58_P_2) },
5036 { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
5039 /* PREFIX_VEX_0F59 */
5041 { VEX_W_TABLE (VEX_W_0F59_P_0) },
5042 { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
5043 { VEX_W_TABLE (VEX_W_0F59_P_2) },
5044 { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
5047 /* PREFIX_VEX_0F5A */
5049 { VEX_W_TABLE (VEX_W_0F5A_P_0) },
5050 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
5051 { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
5052 { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
5055 /* PREFIX_VEX_0F5B */
5057 { VEX_W_TABLE (VEX_W_0F5B_P_0) },
5058 { VEX_W_TABLE (VEX_W_0F5B_P_1) },
5059 { VEX_W_TABLE (VEX_W_0F5B_P_2) },
5062 /* PREFIX_VEX_0F5C */
5064 { VEX_W_TABLE (VEX_W_0F5C_P_0) },
5065 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
5066 { VEX_W_TABLE (VEX_W_0F5C_P_2) },
5067 { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
5070 /* PREFIX_VEX_0F5D */
5072 { VEX_W_TABLE (VEX_W_0F5D_P_0) },
5073 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
5074 { VEX_W_TABLE (VEX_W_0F5D_P_2) },
5075 { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
5078 /* PREFIX_VEX_0F5E */
5080 { VEX_W_TABLE (VEX_W_0F5E_P_0) },
5081 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
5082 { VEX_W_TABLE (VEX_W_0F5E_P_2) },
5083 { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
5086 /* PREFIX_VEX_0F5F */
5088 { VEX_W_TABLE (VEX_W_0F5F_P_0) },
5089 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
5090 { VEX_W_TABLE (VEX_W_0F5F_P_2) },
5091 { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
5094 /* PREFIX_VEX_0F60 */
5098 { VEX_W_TABLE (VEX_W_0F60_P_2) },
5101 /* PREFIX_VEX_0F61 */
5105 { VEX_W_TABLE (VEX_W_0F61_P_2) },
5108 /* PREFIX_VEX_0F62 */
5112 { VEX_W_TABLE (VEX_W_0F62_P_2) },
5115 /* PREFIX_VEX_0F63 */
5119 { VEX_W_TABLE (VEX_W_0F63_P_2) },
5122 /* PREFIX_VEX_0F64 */
5126 { VEX_W_TABLE (VEX_W_0F64_P_2) },
5129 /* PREFIX_VEX_0F65 */
5133 { VEX_W_TABLE (VEX_W_0F65_P_2) },
5136 /* PREFIX_VEX_0F66 */
5140 { VEX_W_TABLE (VEX_W_0F66_P_2) },
5143 /* PREFIX_VEX_0F67 */
5147 { VEX_W_TABLE (VEX_W_0F67_P_2) },
5150 /* PREFIX_VEX_0F68 */
5154 { VEX_W_TABLE (VEX_W_0F68_P_2) },
5157 /* PREFIX_VEX_0F69 */
5161 { VEX_W_TABLE (VEX_W_0F69_P_2) },
5164 /* PREFIX_VEX_0F6A */
5168 { VEX_W_TABLE (VEX_W_0F6A_P_2) },
5171 /* PREFIX_VEX_0F6B */
5175 { VEX_W_TABLE (VEX_W_0F6B_P_2) },
5178 /* PREFIX_VEX_0F6C */
5182 { VEX_W_TABLE (VEX_W_0F6C_P_2) },
5185 /* PREFIX_VEX_0F6D */
5189 { VEX_W_TABLE (VEX_W_0F6D_P_2) },
5192 /* PREFIX_VEX_0F6E */
5196 { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
5199 /* PREFIX_VEX_0F6F */
5202 { VEX_W_TABLE (VEX_W_0F6F_P_1) },
5203 { VEX_W_TABLE (VEX_W_0F6F_P_2) },
5206 /* PREFIX_VEX_0F70 */
5209 { VEX_W_TABLE (VEX_W_0F70_P_1) },
5210 { VEX_W_TABLE (VEX_W_0F70_P_2) },
5211 { VEX_W_TABLE (VEX_W_0F70_P_3) },
5214 /* PREFIX_VEX_0F71_REG_2 */
5218 { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
5221 /* PREFIX_VEX_0F71_REG_4 */
5225 { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
5228 /* PREFIX_VEX_0F71_REG_6 */
5232 { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
5235 /* PREFIX_VEX_0F72_REG_2 */
5239 { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
5242 /* PREFIX_VEX_0F72_REG_4 */
5246 { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
5249 /* PREFIX_VEX_0F72_REG_6 */
5253 { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
5256 /* PREFIX_VEX_0F73_REG_2 */
5260 { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
5263 /* PREFIX_VEX_0F73_REG_3 */
5267 { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
5270 /* PREFIX_VEX_0F73_REG_6 */
5274 { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
5277 /* PREFIX_VEX_0F73_REG_7 */
5281 { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
5284 /* PREFIX_VEX_0F74 */
5288 { VEX_W_TABLE (VEX_W_0F74_P_2) },
5291 /* PREFIX_VEX_0F75 */
5295 { VEX_W_TABLE (VEX_W_0F75_P_2) },
5298 /* PREFIX_VEX_0F76 */
5302 { VEX_W_TABLE (VEX_W_0F76_P_2) },
5305 /* PREFIX_VEX_0F77 */
5307 { VEX_W_TABLE (VEX_W_0F77_P_0) },
5310 /* PREFIX_VEX_0F7C */
5314 { VEX_W_TABLE (VEX_W_0F7C_P_2) },
5315 { VEX_W_TABLE (VEX_W_0F7C_P_3) },
5318 /* PREFIX_VEX_0F7D */
5322 { VEX_W_TABLE (VEX_W_0F7D_P_2) },
5323 { VEX_W_TABLE (VEX_W_0F7D_P_3) },
5326 /* PREFIX_VEX_0F7E */
5329 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
5330 { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
5333 /* PREFIX_VEX_0F7F */
5336 { VEX_W_TABLE (VEX_W_0F7F_P_1) },
5337 { VEX_W_TABLE (VEX_W_0F7F_P_2) },
5340 /* PREFIX_VEX_0F90 */
5342 { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
5344 { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
5347 /* PREFIX_VEX_0F91 */
5349 { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
5351 { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
5354 /* PREFIX_VEX_0F92 */
5356 { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
5358 { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
5359 { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
5362 /* PREFIX_VEX_0F93 */
5364 { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
5366 { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
5367 { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
5370 /* PREFIX_VEX_0F98 */
5372 { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
5374 { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
5377 /* PREFIX_VEX_0F99 */
5379 { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
5381 { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
5384 /* PREFIX_VEX_0FC2 */
5386 { VEX_W_TABLE (VEX_W_0FC2_P_0) },
5387 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
5388 { VEX_W_TABLE (VEX_W_0FC2_P_2) },
5389 { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
5392 /* PREFIX_VEX_0FC4 */
5396 { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
5399 /* PREFIX_VEX_0FC5 */
5403 { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
5406 /* PREFIX_VEX_0FD0 */
5410 { VEX_W_TABLE (VEX_W_0FD0_P_2) },
5411 { VEX_W_TABLE (VEX_W_0FD0_P_3) },
5414 /* PREFIX_VEX_0FD1 */
5418 { VEX_W_TABLE (VEX_W_0FD1_P_2) },
5421 /* PREFIX_VEX_0FD2 */
5425 { VEX_W_TABLE (VEX_W_0FD2_P_2) },
5428 /* PREFIX_VEX_0FD3 */
5432 { VEX_W_TABLE (VEX_W_0FD3_P_2) },
5435 /* PREFIX_VEX_0FD4 */
5439 { VEX_W_TABLE (VEX_W_0FD4_P_2) },
5442 /* PREFIX_VEX_0FD5 */
5446 { VEX_W_TABLE (VEX_W_0FD5_P_2) },
5449 /* PREFIX_VEX_0FD6 */
5453 { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
5456 /* PREFIX_VEX_0FD7 */
5460 { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
5463 /* PREFIX_VEX_0FD8 */
5467 { VEX_W_TABLE (VEX_W_0FD8_P_2) },
5470 /* PREFIX_VEX_0FD9 */
5474 { VEX_W_TABLE (VEX_W_0FD9_P_2) },
5477 /* PREFIX_VEX_0FDA */
5481 { VEX_W_TABLE (VEX_W_0FDA_P_2) },
5484 /* PREFIX_VEX_0FDB */
5488 { VEX_W_TABLE (VEX_W_0FDB_P_2) },
5491 /* PREFIX_VEX_0FDC */
5495 { VEX_W_TABLE (VEX_W_0FDC_P_2) },
5498 /* PREFIX_VEX_0FDD */
5502 { VEX_W_TABLE (VEX_W_0FDD_P_2) },
5505 /* PREFIX_VEX_0FDE */
5509 { VEX_W_TABLE (VEX_W_0FDE_P_2) },
5512 /* PREFIX_VEX_0FDF */
5516 { VEX_W_TABLE (VEX_W_0FDF_P_2) },
5519 /* PREFIX_VEX_0FE0 */
5523 { VEX_W_TABLE (VEX_W_0FE0_P_2) },
5526 /* PREFIX_VEX_0FE1 */
5530 { VEX_W_TABLE (VEX_W_0FE1_P_2) },
5533 /* PREFIX_VEX_0FE2 */
5537 { VEX_W_TABLE (VEX_W_0FE2_P_2) },
5540 /* PREFIX_VEX_0FE3 */
5544 { VEX_W_TABLE (VEX_W_0FE3_P_2) },
5547 /* PREFIX_VEX_0FE4 */
5551 { VEX_W_TABLE (VEX_W_0FE4_P_2) },
5554 /* PREFIX_VEX_0FE5 */
5558 { VEX_W_TABLE (VEX_W_0FE5_P_2) },
5561 /* PREFIX_VEX_0FE6 */
5564 { VEX_W_TABLE (VEX_W_0FE6_P_1) },
5565 { VEX_W_TABLE (VEX_W_0FE6_P_2) },
5566 { VEX_W_TABLE (VEX_W_0FE6_P_3) },
5569 /* PREFIX_VEX_0FE7 */
5573 { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
5576 /* PREFIX_VEX_0FE8 */
5580 { VEX_W_TABLE (VEX_W_0FE8_P_2) },
5583 /* PREFIX_VEX_0FE9 */
5587 { VEX_W_TABLE (VEX_W_0FE9_P_2) },
5590 /* PREFIX_VEX_0FEA */
5594 { VEX_W_TABLE (VEX_W_0FEA_P_2) },
5597 /* PREFIX_VEX_0FEB */
5601 { VEX_W_TABLE (VEX_W_0FEB_P_2) },
5604 /* PREFIX_VEX_0FEC */
5608 { VEX_W_TABLE (VEX_W_0FEC_P_2) },
5611 /* PREFIX_VEX_0FED */
5615 { VEX_W_TABLE (VEX_W_0FED_P_2) },
5618 /* PREFIX_VEX_0FEE */
5622 { VEX_W_TABLE (VEX_W_0FEE_P_2) },
5625 /* PREFIX_VEX_0FEF */
5629 { VEX_W_TABLE (VEX_W_0FEF_P_2) },
5632 /* PREFIX_VEX_0FF0 */
5637 { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
5640 /* PREFIX_VEX_0FF1 */
5644 { VEX_W_TABLE (VEX_W_0FF1_P_2) },
5647 /* PREFIX_VEX_0FF2 */
5651 { VEX_W_TABLE (VEX_W_0FF2_P_2) },
5654 /* PREFIX_VEX_0FF3 */
5658 { VEX_W_TABLE (VEX_W_0FF3_P_2) },
5661 /* PREFIX_VEX_0FF4 */
5665 { VEX_W_TABLE (VEX_W_0FF4_P_2) },
5668 /* PREFIX_VEX_0FF5 */
5672 { VEX_W_TABLE (VEX_W_0FF5_P_2) },
5675 /* PREFIX_VEX_0FF6 */
5679 { VEX_W_TABLE (VEX_W_0FF6_P_2) },
5682 /* PREFIX_VEX_0FF7 */
5686 { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
5689 /* PREFIX_VEX_0FF8 */
5693 { VEX_W_TABLE (VEX_W_0FF8_P_2) },
5696 /* PREFIX_VEX_0FF9 */
5700 { VEX_W_TABLE (VEX_W_0FF9_P_2) },
5703 /* PREFIX_VEX_0FFA */
5707 { VEX_W_TABLE (VEX_W_0FFA_P_2) },
5710 /* PREFIX_VEX_0FFB */
5714 { VEX_W_TABLE (VEX_W_0FFB_P_2) },
5717 /* PREFIX_VEX_0FFC */
5721 { VEX_W_TABLE (VEX_W_0FFC_P_2) },
5724 /* PREFIX_VEX_0FFD */
5728 { VEX_W_TABLE (VEX_W_0FFD_P_2) },
5731 /* PREFIX_VEX_0FFE */
5735 { VEX_W_TABLE (VEX_W_0FFE_P_2) },
5738 /* PREFIX_VEX_0F3800 */
5742 { VEX_W_TABLE (VEX_W_0F3800_P_2) },
5745 /* PREFIX_VEX_0F3801 */
5749 { VEX_W_TABLE (VEX_W_0F3801_P_2) },
5752 /* PREFIX_VEX_0F3802 */
5756 { VEX_W_TABLE (VEX_W_0F3802_P_2) },
5759 /* PREFIX_VEX_0F3803 */
5763 { VEX_W_TABLE (VEX_W_0F3803_P_2) },
5766 /* PREFIX_VEX_0F3804 */
5770 { VEX_W_TABLE (VEX_W_0F3804_P_2) },
5773 /* PREFIX_VEX_0F3805 */
5777 { VEX_W_TABLE (VEX_W_0F3805_P_2) },
5780 /* PREFIX_VEX_0F3806 */
5784 { VEX_W_TABLE (VEX_W_0F3806_P_2) },
5787 /* PREFIX_VEX_0F3807 */
5791 { VEX_W_TABLE (VEX_W_0F3807_P_2) },
5794 /* PREFIX_VEX_0F3808 */
5798 { VEX_W_TABLE (VEX_W_0F3808_P_2) },
5801 /* PREFIX_VEX_0F3809 */
5805 { VEX_W_TABLE (VEX_W_0F3809_P_2) },
5808 /* PREFIX_VEX_0F380A */
5812 { VEX_W_TABLE (VEX_W_0F380A_P_2) },
5815 /* PREFIX_VEX_0F380B */
5819 { VEX_W_TABLE (VEX_W_0F380B_P_2) },
5822 /* PREFIX_VEX_0F380C */
5826 { VEX_W_TABLE (VEX_W_0F380C_P_2) },
5829 /* PREFIX_VEX_0F380D */
5833 { VEX_W_TABLE (VEX_W_0F380D_P_2) },
5836 /* PREFIX_VEX_0F380E */
5840 { VEX_W_TABLE (VEX_W_0F380E_P_2) },
5843 /* PREFIX_VEX_0F380F */
5847 { VEX_W_TABLE (VEX_W_0F380F_P_2) },
5850 /* PREFIX_VEX_0F3813 */
5854 { "vcvtph2ps", { XM, EXxmmq }, 0 },
5857 /* PREFIX_VEX_0F3816 */
5861 { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
5864 /* PREFIX_VEX_0F3817 */
5868 { VEX_W_TABLE (VEX_W_0F3817_P_2) },
5871 /* PREFIX_VEX_0F3818 */
5875 { VEX_W_TABLE (VEX_W_0F3818_P_2) },
5878 /* PREFIX_VEX_0F3819 */
5882 { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
5885 /* PREFIX_VEX_0F381A */
5889 { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
5892 /* PREFIX_VEX_0F381C */
5896 { VEX_W_TABLE (VEX_W_0F381C_P_2) },
5899 /* PREFIX_VEX_0F381D */
5903 { VEX_W_TABLE (VEX_W_0F381D_P_2) },
5906 /* PREFIX_VEX_0F381E */
5910 { VEX_W_TABLE (VEX_W_0F381E_P_2) },
5913 /* PREFIX_VEX_0F3820 */
5917 { VEX_W_TABLE (VEX_W_0F3820_P_2) },
5920 /* PREFIX_VEX_0F3821 */
5924 { VEX_W_TABLE (VEX_W_0F3821_P_2) },
5927 /* PREFIX_VEX_0F3822 */
5931 { VEX_W_TABLE (VEX_W_0F3822_P_2) },
5934 /* PREFIX_VEX_0F3823 */
5938 { VEX_W_TABLE (VEX_W_0F3823_P_2) },
5941 /* PREFIX_VEX_0F3824 */
5945 { VEX_W_TABLE (VEX_W_0F3824_P_2) },
5948 /* PREFIX_VEX_0F3825 */
5952 { VEX_W_TABLE (VEX_W_0F3825_P_2) },
5955 /* PREFIX_VEX_0F3828 */
5959 { VEX_W_TABLE (VEX_W_0F3828_P_2) },
5962 /* PREFIX_VEX_0F3829 */
5966 { VEX_W_TABLE (VEX_W_0F3829_P_2) },
5969 /* PREFIX_VEX_0F382A */
5973 { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
5976 /* PREFIX_VEX_0F382B */
5980 { VEX_W_TABLE (VEX_W_0F382B_P_2) },
5983 /* PREFIX_VEX_0F382C */
5987 { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
5990 /* PREFIX_VEX_0F382D */
5994 { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
5997 /* PREFIX_VEX_0F382E */
6001 { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
6004 /* PREFIX_VEX_0F382F */
6008 { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
6011 /* PREFIX_VEX_0F3830 */
6015 { VEX_W_TABLE (VEX_W_0F3830_P_2) },
6018 /* PREFIX_VEX_0F3831 */
6022 { VEX_W_TABLE (VEX_W_0F3831_P_2) },
6025 /* PREFIX_VEX_0F3832 */
6029 { VEX_W_TABLE (VEX_W_0F3832_P_2) },
6032 /* PREFIX_VEX_0F3833 */
6036 { VEX_W_TABLE (VEX_W_0F3833_P_2) },
6039 /* PREFIX_VEX_0F3834 */
6043 { VEX_W_TABLE (VEX_W_0F3834_P_2) },
6046 /* PREFIX_VEX_0F3835 */
6050 { VEX_W_TABLE (VEX_W_0F3835_P_2) },
6053 /* PREFIX_VEX_0F3836 */
6057 { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
6060 /* PREFIX_VEX_0F3837 */
6064 { VEX_W_TABLE (VEX_W_0F3837_P_2) },
6067 /* PREFIX_VEX_0F3838 */
6071 { VEX_W_TABLE (VEX_W_0F3838_P_2) },
6074 /* PREFIX_VEX_0F3839 */
6078 { VEX_W_TABLE (VEX_W_0F3839_P_2) },
6081 /* PREFIX_VEX_0F383A */
6085 { VEX_W_TABLE (VEX_W_0F383A_P_2) },
6088 /* PREFIX_VEX_0F383B */
6092 { VEX_W_TABLE (VEX_W_0F383B_P_2) },
6095 /* PREFIX_VEX_0F383C */
6099 { VEX_W_TABLE (VEX_W_0F383C_P_2) },
6102 /* PREFIX_VEX_0F383D */
6106 { VEX_W_TABLE (VEX_W_0F383D_P_2) },
6109 /* PREFIX_VEX_0F383E */
6113 { VEX_W_TABLE (VEX_W_0F383E_P_2) },
6116 /* PREFIX_VEX_0F383F */
6120 { VEX_W_TABLE (VEX_W_0F383F_P_2) },
6123 /* PREFIX_VEX_0F3840 */
6127 { VEX_W_TABLE (VEX_W_0F3840_P_2) },
6130 /* PREFIX_VEX_0F3841 */
6134 { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
6137 /* PREFIX_VEX_0F3845 */
6141 { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
6144 /* PREFIX_VEX_0F3846 */
6148 { VEX_W_TABLE (VEX_W_0F3846_P_2) },
6151 /* PREFIX_VEX_0F3847 */
6155 { "vpsllv%LW", { XM, Vex, EXx }, 0 },
6158 /* PREFIX_VEX_0F3858 */
6162 { VEX_W_TABLE (VEX_W_0F3858_P_2) },
6165 /* PREFIX_VEX_0F3859 */
6169 { VEX_W_TABLE (VEX_W_0F3859_P_2) },
6172 /* PREFIX_VEX_0F385A */
6176 { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
6179 /* PREFIX_VEX_0F3878 */
6183 { VEX_W_TABLE (VEX_W_0F3878_P_2) },
6186 /* PREFIX_VEX_0F3879 */
6190 { VEX_W_TABLE (VEX_W_0F3879_P_2) },
6193 /* PREFIX_VEX_0F388C */
6197 { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
6200 /* PREFIX_VEX_0F388E */
6204 { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
6207 /* PREFIX_VEX_0F3890 */
6211 { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
6214 /* PREFIX_VEX_0F3891 */
6218 { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6221 /* PREFIX_VEX_0F3892 */
6225 { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
6228 /* PREFIX_VEX_0F3893 */
6232 { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
6235 /* PREFIX_VEX_0F3896 */
6239 { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
6242 /* PREFIX_VEX_0F3897 */
6246 { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
6249 /* PREFIX_VEX_0F3898 */
6253 { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
6256 /* PREFIX_VEX_0F3899 */
6260 { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6263 /* PREFIX_VEX_0F389A */
6267 { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
6270 /* PREFIX_VEX_0F389B */
6274 { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6277 /* PREFIX_VEX_0F389C */
6281 { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
6284 /* PREFIX_VEX_0F389D */
6288 { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6291 /* PREFIX_VEX_0F389E */
6295 { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
6298 /* PREFIX_VEX_0F389F */
6302 { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6305 /* PREFIX_VEX_0F38A6 */
6309 { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
6313 /* PREFIX_VEX_0F38A7 */
6317 { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
6320 /* PREFIX_VEX_0F38A8 */
6324 { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
6327 /* PREFIX_VEX_0F38A9 */
6331 { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6334 /* PREFIX_VEX_0F38AA */
6338 { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
6341 /* PREFIX_VEX_0F38AB */
6345 { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6348 /* PREFIX_VEX_0F38AC */
6352 { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
6355 /* PREFIX_VEX_0F38AD */
6359 { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6362 /* PREFIX_VEX_0F38AE */
6366 { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
6369 /* PREFIX_VEX_0F38AF */
6373 { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6376 /* PREFIX_VEX_0F38B6 */
6380 { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
6383 /* PREFIX_VEX_0F38B7 */
6387 { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
6390 /* PREFIX_VEX_0F38B8 */
6394 { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
6397 /* PREFIX_VEX_0F38B9 */
6401 { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6404 /* PREFIX_VEX_0F38BA */
6408 { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
6411 /* PREFIX_VEX_0F38BB */
6415 { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6418 /* PREFIX_VEX_0F38BC */
6422 { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
6425 /* PREFIX_VEX_0F38BD */
6429 { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6432 /* PREFIX_VEX_0F38BE */
6436 { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
6439 /* PREFIX_VEX_0F38BF */
6443 { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
6446 /* PREFIX_VEX_0F38CF */
6450 { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
6453 /* PREFIX_VEX_0F38DB */
6457 { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
6460 /* PREFIX_VEX_0F38DC */
6464 { "vaesenc", { XM, Vex, EXx }, 0 },
6467 /* PREFIX_VEX_0F38DD */
6471 { "vaesenclast", { XM, Vex, EXx }, 0 },
6474 /* PREFIX_VEX_0F38DE */
6478 { "vaesdec", { XM, Vex, EXx }, 0 },
6481 /* PREFIX_VEX_0F38DF */
6485 { "vaesdeclast", { XM, Vex, EXx }, 0 },
6488 /* PREFIX_VEX_0F38F2 */
6490 { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
6493 /* PREFIX_VEX_0F38F3_REG_1 */
6495 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
6498 /* PREFIX_VEX_0F38F3_REG_2 */
6500 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
6503 /* PREFIX_VEX_0F38F3_REG_3 */
6505 { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
6508 /* PREFIX_VEX_0F38F5 */
6510 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
6511 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
6513 { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
6516 /* PREFIX_VEX_0F38F6 */
6521 { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
6524 /* PREFIX_VEX_0F38F7 */
6526 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
6527 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
6528 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
6529 { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
6532 /* PREFIX_VEX_0F3A00 */
6536 { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
6539 /* PREFIX_VEX_0F3A01 */
6543 { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
6546 /* PREFIX_VEX_0F3A02 */
6550 { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
6553 /* PREFIX_VEX_0F3A04 */
6557 { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
6560 /* PREFIX_VEX_0F3A05 */
6564 { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
6567 /* PREFIX_VEX_0F3A06 */
6571 { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
6574 /* PREFIX_VEX_0F3A08 */
6578 { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
6581 /* PREFIX_VEX_0F3A09 */
6585 { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
6588 /* PREFIX_VEX_0F3A0A */
6592 { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
6595 /* PREFIX_VEX_0F3A0B */
6599 { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
6602 /* PREFIX_VEX_0F3A0C */
6606 { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
6609 /* PREFIX_VEX_0F3A0D */
6613 { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
6616 /* PREFIX_VEX_0F3A0E */
6620 { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
6623 /* PREFIX_VEX_0F3A0F */
6627 { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
6630 /* PREFIX_VEX_0F3A14 */
6634 { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
6637 /* PREFIX_VEX_0F3A15 */
6641 { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
6644 /* PREFIX_VEX_0F3A16 */
6648 { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
6651 /* PREFIX_VEX_0F3A17 */
6655 { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
6658 /* PREFIX_VEX_0F3A18 */
6662 { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
6665 /* PREFIX_VEX_0F3A19 */
6669 { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
6672 /* PREFIX_VEX_0F3A1D */
6676 { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
6679 /* PREFIX_VEX_0F3A20 */
6683 { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
6686 /* PREFIX_VEX_0F3A21 */
6690 { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
6693 /* PREFIX_VEX_0F3A22 */
6697 { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
6700 /* PREFIX_VEX_0F3A30 */
6704 { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
6707 /* PREFIX_VEX_0F3A31 */
6711 { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
6714 /* PREFIX_VEX_0F3A32 */
6718 { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
6721 /* PREFIX_VEX_0F3A33 */
6725 { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
6728 /* PREFIX_VEX_0F3A38 */
6732 { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
6735 /* PREFIX_VEX_0F3A39 */
6739 { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
6742 /* PREFIX_VEX_0F3A40 */
6746 { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
6749 /* PREFIX_VEX_0F3A41 */
6753 { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
6756 /* PREFIX_VEX_0F3A42 */
6760 { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
6763 /* PREFIX_VEX_0F3A44 */
6767 { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, 0 },
6770 /* PREFIX_VEX_0F3A46 */
6774 { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
6777 /* PREFIX_VEX_0F3A48 */
6781 { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
6784 /* PREFIX_VEX_0F3A49 */
6788 { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
6791 /* PREFIX_VEX_0F3A4A */
6795 { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
6798 /* PREFIX_VEX_0F3A4B */
6802 { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
6805 /* PREFIX_VEX_0F3A4C */
6809 { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
6812 /* PREFIX_VEX_0F3A5C */
6816 { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6819 /* PREFIX_VEX_0F3A5D */
6823 { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6826 /* PREFIX_VEX_0F3A5E */
6830 { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6833 /* PREFIX_VEX_0F3A5F */
6837 { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6840 /* PREFIX_VEX_0F3A60 */
6844 { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
6848 /* PREFIX_VEX_0F3A61 */
6852 { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
6855 /* PREFIX_VEX_0F3A62 */
6859 { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
6862 /* PREFIX_VEX_0F3A63 */
6866 { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
6869 /* PREFIX_VEX_0F3A68 */
6873 { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6876 /* PREFIX_VEX_0F3A69 */
6880 { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6883 /* PREFIX_VEX_0F3A6A */
6887 { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
6890 /* PREFIX_VEX_0F3A6B */
6894 { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
6897 /* PREFIX_VEX_0F3A6C */
6901 { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6904 /* PREFIX_VEX_0F3A6D */
6908 { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6911 /* PREFIX_VEX_0F3A6E */
6915 { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
6918 /* PREFIX_VEX_0F3A6F */
6922 { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
6925 /* PREFIX_VEX_0F3A78 */
6929 { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6932 /* PREFIX_VEX_0F3A79 */
6936 { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6939 /* PREFIX_VEX_0F3A7A */
6943 { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
6946 /* PREFIX_VEX_0F3A7B */
6950 { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
6953 /* PREFIX_VEX_0F3A7C */
6957 { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6961 /* PREFIX_VEX_0F3A7D */
6965 { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
6968 /* PREFIX_VEX_0F3A7E */
6972 { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
6975 /* PREFIX_VEX_0F3A7F */
6979 { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
6982 /* PREFIX_VEX_0F3ACE */
6986 { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
6989 /* PREFIX_VEX_0F3ACF */
6993 { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
6996 /* PREFIX_VEX_0F3ADF */
7000 { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
7003 /* PREFIX_VEX_0F3AF0 */
7008 { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
7011 #define NEED_PREFIX_TABLE
7012 #include "i386-dis-evex.h"
7013 #undef NEED_PREFIX_TABLE
7016 static const struct dis386 x86_64_table[][2] = {
7019 { "pushP", { es }, 0 },
7024 { "popP", { es }, 0 },
7029 { "pushP", { cs }, 0 },
7034 { "pushP", { ss }, 0 },
7039 { "popP", { ss }, 0 },
7044 { "pushP", { ds }, 0 },
7049 { "popP", { ds }, 0 },
7054 { "daa", { XX }, 0 },
7059 { "das", { XX }, 0 },
7064 { "aaa", { XX }, 0 },
7069 { "aas", { XX }, 0 },
7074 { "pushaP", { XX }, 0 },
7079 { "popaP", { XX }, 0 },
7084 { MOD_TABLE (MOD_62_32BIT) },
7085 { EVEX_TABLE (EVEX_0F) },
7090 { "arpl", { Ew, Gw }, 0 },
7091 { "movs{lq|xd}", { Gv, Ed }, 0 },
7096 { "ins{R|}", { Yzr, indirDX }, 0 },
7097 { "ins{G|}", { Yzr, indirDX }, 0 },
7102 { "outs{R|}", { indirDXr, Xz }, 0 },
7103 { "outs{G|}", { indirDXr, Xz }, 0 },
7108 /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
7109 { REG_TABLE (REG_80) },
7114 { "Jcall{T|}", { Ap }, 0 },
7119 { MOD_TABLE (MOD_C4_32BIT) },
7120 { VEX_C4_TABLE (VEX_0F) },
7125 { MOD_TABLE (MOD_C5_32BIT) },
7126 { VEX_C5_TABLE (VEX_0F) },
7131 { "into", { XX }, 0 },
7136 { "aam", { Ib }, 0 },
7141 { "aad", { Ib }, 0 },
7146 { "callP", { Jv, BND }, 0 },
7147 { "call@", { Jv, BND }, 0 }
7152 { "jmpP", { Jv, BND }, 0 },
7153 { "jmp@", { Jv, BND }, 0 }
7158 { "Jjmp{T|}", { Ap }, 0 },
7161 /* X86_64_0F01_REG_0 */
7163 { "sgdt{Q|IQ}", { M }, 0 },
7164 { "sgdt", { M }, 0 },
7167 /* X86_64_0F01_REG_1 */
7169 { "sidt{Q|IQ}", { M }, 0 },
7170 { "sidt", { M }, 0 },
7173 /* X86_64_0F01_REG_2 */
7175 { "lgdt{Q|Q}", { M }, 0 },
7176 { "lgdt", { M }, 0 },
7179 /* X86_64_0F01_REG_3 */
7181 { "lidt{Q|Q}", { M }, 0 },
7182 { "lidt", { M }, 0 },
7186 static const struct dis386 three_byte_table[][256] = {
7188 /* THREE_BYTE_0F38 */
7191 { "pshufb", { MX, EM }, PREFIX_OPCODE },
7192 { "phaddw", { MX, EM }, PREFIX_OPCODE },
7193 { "phaddd", { MX, EM }, PREFIX_OPCODE },
7194 { "phaddsw", { MX, EM }, PREFIX_OPCODE },
7195 { "pmaddubsw", { MX, EM }, PREFIX_OPCODE },
7196 { "phsubw", { MX, EM }, PREFIX_OPCODE },
7197 { "phsubd", { MX, EM }, PREFIX_OPCODE },
7198 { "phsubsw", { MX, EM }, PREFIX_OPCODE },
7200 { "psignb", { MX, EM }, PREFIX_OPCODE },
7201 { "psignw", { MX, EM }, PREFIX_OPCODE },
7202 { "psignd", { MX, EM }, PREFIX_OPCODE },
7203 { "pmulhrsw", { MX, EM }, PREFIX_OPCODE },
7209 { PREFIX_TABLE (PREFIX_0F3810) },
7213 { PREFIX_TABLE (PREFIX_0F3814) },
7214 { PREFIX_TABLE (PREFIX_0F3815) },
7216 { PREFIX_TABLE (PREFIX_0F3817) },
7222 { "pabsb", { MX, EM }, PREFIX_OPCODE },
7223 { "pabsw", { MX, EM }, PREFIX_OPCODE },
7224 { "pabsd", { MX, EM }, PREFIX_OPCODE },
7227 { PREFIX_TABLE (PREFIX_0F3820) },
7228 { PREFIX_TABLE (PREFIX_0F3821) },
7229 { PREFIX_TABLE (PREFIX_0F3822) },
7230 { PREFIX_TABLE (PREFIX_0F3823) },
7231 { PREFIX_TABLE (PREFIX_0F3824) },
7232 { PREFIX_TABLE (PREFIX_0F3825) },
7236 { PREFIX_TABLE (PREFIX_0F3828) },
7237 { PREFIX_TABLE (PREFIX_0F3829) },
7238 { PREFIX_TABLE (PREFIX_0F382A) },
7239 { PREFIX_TABLE (PREFIX_0F382B) },
7245 { PREFIX_TABLE (PREFIX_0F3830) },
7246 { PREFIX_TABLE (PREFIX_0F3831) },
7247 { PREFIX_TABLE (PREFIX_0F3832) },
7248 { PREFIX_TABLE (PREFIX_0F3833) },
7249 { PREFIX_TABLE (PREFIX_0F3834) },
7250 { PREFIX_TABLE (PREFIX_0F3835) },
7252 { PREFIX_TABLE (PREFIX_0F3837) },
7254 { PREFIX_TABLE (PREFIX_0F3838) },
7255 { PREFIX_TABLE (PREFIX_0F3839) },
7256 { PREFIX_TABLE (PREFIX_0F383A) },
7257 { PREFIX_TABLE (PREFIX_0F383B) },
7258 { PREFIX_TABLE (PREFIX_0F383C) },
7259 { PREFIX_TABLE (PREFIX_0F383D) },
7260 { PREFIX_TABLE (PREFIX_0F383E) },
7261 { PREFIX_TABLE (PREFIX_0F383F) },
7263 { PREFIX_TABLE (PREFIX_0F3840) },
7264 { PREFIX_TABLE (PREFIX_0F3841) },
7335 { PREFIX_TABLE (PREFIX_0F3880) },
7336 { PREFIX_TABLE (PREFIX_0F3881) },
7337 { PREFIX_TABLE (PREFIX_0F3882) },
7416 { PREFIX_TABLE (PREFIX_0F38C8) },
7417 { PREFIX_TABLE (PREFIX_0F38C9) },
7418 { PREFIX_TABLE (PREFIX_0F38CA) },
7419 { PREFIX_TABLE (PREFIX_0F38CB) },
7420 { PREFIX_TABLE (PREFIX_0F38CC) },
7421 { PREFIX_TABLE (PREFIX_0F38CD) },
7423 { PREFIX_TABLE (PREFIX_0F38CF) },
7437 { PREFIX_TABLE (PREFIX_0F38DB) },
7438 { PREFIX_TABLE (PREFIX_0F38DC) },
7439 { PREFIX_TABLE (PREFIX_0F38DD) },
7440 { PREFIX_TABLE (PREFIX_0F38DE) },
7441 { PREFIX_TABLE (PREFIX_0F38DF) },
7461 { PREFIX_TABLE (PREFIX_0F38F0) },
7462 { PREFIX_TABLE (PREFIX_0F38F1) },
7466 { PREFIX_TABLE (PREFIX_0F38F5) },
7467 { PREFIX_TABLE (PREFIX_0F38F6) },
7470 { PREFIX_TABLE (PREFIX_0F38F8) },
7471 { PREFIX_TABLE (PREFIX_0F38F9) },
7479 /* THREE_BYTE_0F3A */
7491 { PREFIX_TABLE (PREFIX_0F3A08) },
7492 { PREFIX_TABLE (PREFIX_0F3A09) },
7493 { PREFIX_TABLE (PREFIX_0F3A0A) },
7494 { PREFIX_TABLE (PREFIX_0F3A0B) },
7495 { PREFIX_TABLE (PREFIX_0F3A0C) },
7496 { PREFIX_TABLE (PREFIX_0F3A0D) },
7497 { PREFIX_TABLE (PREFIX_0F3A0E) },
7498 { "palignr", { MX, EM, Ib }, PREFIX_OPCODE },
7504 { PREFIX_TABLE (PREFIX_0F3A14) },
7505 { PREFIX_TABLE (PREFIX_0F3A15) },
7506 { PREFIX_TABLE (PREFIX_0F3A16) },
7507 { PREFIX_TABLE (PREFIX_0F3A17) },
7518 { PREFIX_TABLE (PREFIX_0F3A20) },
7519 { PREFIX_TABLE (PREFIX_0F3A21) },
7520 { PREFIX_TABLE (PREFIX_0F3A22) },
7554 { PREFIX_TABLE (PREFIX_0F3A40) },
7555 { PREFIX_TABLE (PREFIX_0F3A41) },
7556 { PREFIX_TABLE (PREFIX_0F3A42) },
7558 { PREFIX_TABLE (PREFIX_0F3A44) },
7590 { PREFIX_TABLE (PREFIX_0F3A60) },
7591 { PREFIX_TABLE (PREFIX_0F3A61) },
7592 { PREFIX_TABLE (PREFIX_0F3A62) },
7593 { PREFIX_TABLE (PREFIX_0F3A63) },
7711 { PREFIX_TABLE (PREFIX_0F3ACC) },
7713 { PREFIX_TABLE (PREFIX_0F3ACE) },
7714 { PREFIX_TABLE (PREFIX_0F3ACF) },
7732 { PREFIX_TABLE (PREFIX_0F3ADF) },
7772 static const struct dis386 xop_table[][256] = {
7925 { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7926 { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7927 { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7935 { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7936 { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7943 { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7944 { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7945 { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7953 { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7954 { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7958 { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7959 { "vpperm", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7962 { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7980 { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
7992 { "vprotb", { XM, Vex_2src_1, Ib }, 0 },
7993 { "vprotw", { XM, Vex_2src_1, Ib }, 0 },
7994 { "vprotd", { XM, Vex_2src_1, Ib }, 0 },
7995 { "vprotq", { XM, Vex_2src_1, Ib }, 0 },
8005 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
8006 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
8007 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
8008 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
8041 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
8042 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
8043 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
8044 { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
8068 { REG_TABLE (REG_XOP_TBM_01) },
8069 { REG_TABLE (REG_XOP_TBM_02) },
8087 { REG_TABLE (REG_XOP_LWPCB) },
8211 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
8212 { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
8213 { "vfrczss", { XM, EXd }, 0 },
8214 { "vfrczsd", { XM, EXq }, 0 },
8229 { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8230 { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8231 { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8232 { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8233 { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8234 { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8235 { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8236 { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8238 { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8239 { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8240 { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8241 { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
8284 { "vphaddbw", { XM, EXxmm }, 0 },
8285 { "vphaddbd", { XM, EXxmm }, 0 },
8286 { "vphaddbq", { XM, EXxmm }, 0 },
8289 { "vphaddwd", { XM, EXxmm }, 0 },
8290 { "vphaddwq", { XM, EXxmm }, 0 },
8295 { "vphadddq", { XM, EXxmm }, 0 },
8302 { "vphaddubw", { XM, EXxmm }, 0 },
8303 { "vphaddubd", { XM, EXxmm }, 0 },
8304 { "vphaddubq", { XM, EXxmm }, 0 },
8307 { "vphadduwd", { XM, EXxmm }, 0 },
8308 { "vphadduwq", { XM, EXxmm }, 0 },
8313 { "vphaddudq", { XM, EXxmm }, 0 },
8320 { "vphsubbw", { XM, EXxmm }, 0 },
8321 { "vphsubwd", { XM, EXxmm }, 0 },
8322 { "vphsubdq", { XM, EXxmm }, 0 },
8376 { "bextr", { Gv, Ev, Iq }, 0 },
8378 { REG_TABLE (REG_XOP_LWP) },
8648 static const struct dis386 vex_table[][256] = {
8670 { PREFIX_TABLE (PREFIX_VEX_0F10) },
8671 { PREFIX_TABLE (PREFIX_VEX_0F11) },
8672 { PREFIX_TABLE (PREFIX_VEX_0F12) },
8673 { MOD_TABLE (MOD_VEX_0F13) },
8674 { VEX_W_TABLE (VEX_W_0F14) },
8675 { VEX_W_TABLE (VEX_W_0F15) },
8676 { PREFIX_TABLE (PREFIX_VEX_0F16) },
8677 { MOD_TABLE (MOD_VEX_0F17) },
8697 { VEX_W_TABLE (VEX_W_0F28) },
8698 { VEX_W_TABLE (VEX_W_0F29) },
8699 { PREFIX_TABLE (PREFIX_VEX_0F2A) },
8700 { MOD_TABLE (MOD_VEX_0F2B) },
8701 { PREFIX_TABLE (PREFIX_VEX_0F2C) },
8702 { PREFIX_TABLE (PREFIX_VEX_0F2D) },
8703 { PREFIX_TABLE (PREFIX_VEX_0F2E) },
8704 { PREFIX_TABLE (PREFIX_VEX_0F2F) },
8725 { PREFIX_TABLE (PREFIX_VEX_0F41) },
8726 { PREFIX_TABLE (PREFIX_VEX_0F42) },
8728 { PREFIX_TABLE (PREFIX_VEX_0F44) },
8729 { PREFIX_TABLE (PREFIX_VEX_0F45) },
8730 { PREFIX_TABLE (PREFIX_VEX_0F46) },
8731 { PREFIX_TABLE (PREFIX_VEX_0F47) },
8735 { PREFIX_TABLE (PREFIX_VEX_0F4A) },
8736 { PREFIX_TABLE (PREFIX_VEX_0F4B) },
8742 { MOD_TABLE (MOD_VEX_0F50) },
8743 { PREFIX_TABLE (PREFIX_VEX_0F51) },
8744 { PREFIX_TABLE (PREFIX_VEX_0F52) },
8745 { PREFIX_TABLE (PREFIX_VEX_0F53) },
8746 { "vandpX", { XM, Vex, EXx }, 0 },
8747 { "vandnpX", { XM, Vex, EXx }, 0 },
8748 { "vorpX", { XM, Vex, EXx }, 0 },
8749 { "vxorpX", { XM, Vex, EXx }, 0 },
8751 { PREFIX_TABLE (PREFIX_VEX_0F58) },
8752 { PREFIX_TABLE (PREFIX_VEX_0F59) },
8753 { PREFIX_TABLE (PREFIX_VEX_0F5A) },
8754 { PREFIX_TABLE (PREFIX_VEX_0F5B) },
8755 { PREFIX_TABLE (PREFIX_VEX_0F5C) },
8756 { PREFIX_TABLE (PREFIX_VEX_0F5D) },
8757 { PREFIX_TABLE (PREFIX_VEX_0F5E) },
8758 { PREFIX_TABLE (PREFIX_VEX_0F5F) },
8760 { PREFIX_TABLE (PREFIX_VEX_0F60) },
8761 { PREFIX_TABLE (PREFIX_VEX_0F61) },
8762 { PREFIX_TABLE (PREFIX_VEX_0F62) },
8763 { PREFIX_TABLE (PREFIX_VEX_0F63) },
8764 { PREFIX_TABLE (PREFIX_VEX_0F64) },
8765 { PREFIX_TABLE (PREFIX_VEX_0F65) },
8766 { PREFIX_TABLE (PREFIX_VEX_0F66) },
8767 { PREFIX_TABLE (PREFIX_VEX_0F67) },
8769 { PREFIX_TABLE (PREFIX_VEX_0F68) },
8770 { PREFIX_TABLE (PREFIX_VEX_0F69) },
8771 { PREFIX_TABLE (PREFIX_VEX_0F6A) },
8772 { PREFIX_TABLE (PREFIX_VEX_0F6B) },
8773 { PREFIX_TABLE (PREFIX_VEX_0F6C) },
8774 { PREFIX_TABLE (PREFIX_VEX_0F6D) },
8775 { PREFIX_TABLE (PREFIX_VEX_0F6E) },
8776 { PREFIX_TABLE (PREFIX_VEX_0F6F) },
8778 { PREFIX_TABLE (PREFIX_VEX_0F70) },
8779 { REG_TABLE (REG_VEX_0F71) },
8780 { REG_TABLE (REG_VEX_0F72) },
8781 { REG_TABLE (REG_VEX_0F73) },
8782 { PREFIX_TABLE (PREFIX_VEX_0F74) },
8783 { PREFIX_TABLE (PREFIX_VEX_0F75) },
8784 { PREFIX_TABLE (PREFIX_VEX_0F76) },
8785 { PREFIX_TABLE (PREFIX_VEX_0F77) },
8791 { PREFIX_TABLE (PREFIX_VEX_0F7C) },
8792 { PREFIX_TABLE (PREFIX_VEX_0F7D) },
8793 { PREFIX_TABLE (PREFIX_VEX_0F7E) },
8794 { PREFIX_TABLE (PREFIX_VEX_0F7F) },
8814 { PREFIX_TABLE (PREFIX_VEX_0F90) },
8815 { PREFIX_TABLE (PREFIX_VEX_0F91) },
8816 { PREFIX_TABLE (PREFIX_VEX_0F92) },
8817 { PREFIX_TABLE (PREFIX_VEX_0F93) },
8823 { PREFIX_TABLE (PREFIX_VEX_0F98) },
8824 { PREFIX_TABLE (PREFIX_VEX_0F99) },
8847 { REG_TABLE (REG_VEX_0FAE) },
8870 { PREFIX_TABLE (PREFIX_VEX_0FC2) },
8872 { PREFIX_TABLE (PREFIX_VEX_0FC4) },
8873 { PREFIX_TABLE (PREFIX_VEX_0FC5) },
8874 { "vshufpX", { XM, Vex, EXx, Ib }, 0 },
8886 { PREFIX_TABLE (PREFIX_VEX_0FD0) },
8887 { PREFIX_TABLE (PREFIX_VEX_0FD1) },
8888 { PREFIX_TABLE (PREFIX_VEX_0FD2) },
8889 { PREFIX_TABLE (PREFIX_VEX_0FD3) },
8890 { PREFIX_TABLE (PREFIX_VEX_0FD4) },
8891 { PREFIX_TABLE (PREFIX_VEX_0FD5) },
8892 { PREFIX_TABLE (PREFIX_VEX_0FD6) },
8893 { PREFIX_TABLE (PREFIX_VEX_0FD7) },
8895 { PREFIX_TABLE (PREFIX_VEX_0FD8) },
8896 { PREFIX_TABLE (PREFIX_VEX_0FD9) },
8897 { PREFIX_TABLE (PREFIX_VEX_0FDA) },
8898 { PREFIX_TABLE (PREFIX_VEX_0FDB) },
8899 { PREFIX_TABLE (PREFIX_VEX_0FDC) },
8900 { PREFIX_TABLE (PREFIX_VEX_0FDD) },
8901 { PREFIX_TABLE (PREFIX_VEX_0FDE) },
8902 { PREFIX_TABLE (PREFIX_VEX_0FDF) },
8904 { PREFIX_TABLE (PREFIX_VEX_0FE0) },
8905 { PREFIX_TABLE (PREFIX_VEX_0FE1) },
8906 { PREFIX_TABLE (PREFIX_VEX_0FE2) },
8907 { PREFIX_TABLE (PREFIX_VEX_0FE3) },
8908 { PREFIX_TABLE (PREFIX_VEX_0FE4) },
8909 { PREFIX_TABLE (PREFIX_VEX_0FE5) },
8910 { PREFIX_TABLE (PREFIX_VEX_0FE6) },
8911 { PREFIX_TABLE (PREFIX_VEX_0FE7) },
8913 { PREFIX_TABLE (PREFIX_VEX_0FE8) },
8914 { PREFIX_TABLE (PREFIX_VEX_0FE9) },
8915 { PREFIX_TABLE (PREFIX_VEX_0FEA) },
8916 { PREFIX_TABLE (PREFIX_VEX_0FEB) },
8917 { PREFIX_TABLE (PREFIX_VEX_0FEC) },
8918 { PREFIX_TABLE (PREFIX_VEX_0FED) },
8919 { PREFIX_TABLE (PREFIX_VEX_0FEE) },
8920 { PREFIX_TABLE (PREFIX_VEX_0FEF) },
8922 { PREFIX_TABLE (PREFIX_VEX_0FF0) },
8923 { PREFIX_TABLE (PREFIX_VEX_0FF1) },
8924 { PREFIX_TABLE (PREFIX_VEX_0FF2) },
8925 { PREFIX_TABLE (PREFIX_VEX_0FF3) },
8926 { PREFIX_TABLE (PREFIX_VEX_0FF4) },
8927 { PREFIX_TABLE (PREFIX_VEX_0FF5) },
8928 { PREFIX_TABLE (PREFIX_VEX_0FF6) },
8929 { PREFIX_TABLE (PREFIX_VEX_0FF7) },
8931 { PREFIX_TABLE (PREFIX_VEX_0FF8) },
8932 { PREFIX_TABLE (PREFIX_VEX_0FF9) },
8933 { PREFIX_TABLE (PREFIX_VEX_0FFA) },
8934 { PREFIX_TABLE (PREFIX_VEX_0FFB) },
8935 { PREFIX_TABLE (PREFIX_VEX_0FFC) },
8936 { PREFIX_TABLE (PREFIX_VEX_0FFD) },
8937 { PREFIX_TABLE (PREFIX_VEX_0FFE) },
8943 { PREFIX_TABLE (PREFIX_VEX_0F3800) },
8944 { PREFIX_TABLE (PREFIX_VEX_0F3801) },
8945 { PREFIX_TABLE (PREFIX_VEX_0F3802) },
8946 { PREFIX_TABLE (PREFIX_VEX_0F3803) },
8947 { PREFIX_TABLE (PREFIX_VEX_0F3804) },
8948 { PREFIX_TABLE (PREFIX_VEX_0F3805) },
8949 { PREFIX_TABLE (PREFIX_VEX_0F3806) },
8950 { PREFIX_TABLE (PREFIX_VEX_0F3807) },
8952 { PREFIX_TABLE (PREFIX_VEX_0F3808) },
8953 { PREFIX_TABLE (PREFIX_VEX_0F3809) },
8954 { PREFIX_TABLE (PREFIX_VEX_0F380A) },
8955 { PREFIX_TABLE (PREFIX_VEX_0F380B) },
8956 { PREFIX_TABLE (PREFIX_VEX_0F380C) },
8957 { PREFIX_TABLE (PREFIX_VEX_0F380D) },
8958 { PREFIX_TABLE (PREFIX_VEX_0F380E) },
8959 { PREFIX_TABLE (PREFIX_VEX_0F380F) },
8964 { PREFIX_TABLE (PREFIX_VEX_0F3813) },
8967 { PREFIX_TABLE (PREFIX_VEX_0F3816) },
8968 { PREFIX_TABLE (PREFIX_VEX_0F3817) },
8970 { PREFIX_TABLE (PREFIX_VEX_0F3818) },
8971 { PREFIX_TABLE (PREFIX_VEX_0F3819) },
8972 { PREFIX_TABLE (PREFIX_VEX_0F381A) },
8974 { PREFIX_TABLE (PREFIX_VEX_0F381C) },
8975 { PREFIX_TABLE (PREFIX_VEX_0F381D) },
8976 { PREFIX_TABLE (PREFIX_VEX_0F381E) },
8979 { PREFIX_TABLE (PREFIX_VEX_0F3820) },
8980 { PREFIX_TABLE (PREFIX_VEX_0F3821) },
8981 { PREFIX_TABLE (PREFIX_VEX_0F3822) },
8982 { PREFIX_TABLE (PREFIX_VEX_0F3823) },
8983 { PREFIX_TABLE (PREFIX_VEX_0F3824) },
8984 { PREFIX_TABLE (PREFIX_VEX_0F3825) },
8988 { PREFIX_TABLE (PREFIX_VEX_0F3828) },
8989 { PREFIX_TABLE (PREFIX_VEX_0F3829) },
8990 { PREFIX_TABLE (PREFIX_VEX_0F382A) },
8991 { PREFIX_TABLE (PREFIX_VEX_0F382B) },
8992 { PREFIX_TABLE (PREFIX_VEX_0F382C) },
8993 { PREFIX_TABLE (PREFIX_VEX_0F382D) },
8994 { PREFIX_TABLE (PREFIX_VEX_0F382E) },
8995 { PREFIX_TABLE (PREFIX_VEX_0F382F) },
8997 { PREFIX_TABLE (PREFIX_VEX_0F3830) },
8998 { PREFIX_TABLE (PREFIX_VEX_0F3831) },
8999 { PREFIX_TABLE (PREFIX_VEX_0F3832) },
9000 { PREFIX_TABLE (PREFIX_VEX_0F3833) },
9001 { PREFIX_TABLE (PREFIX_VEX_0F3834) },
9002 { PREFIX_TABLE (PREFIX_VEX_0F3835) },
9003 { PREFIX_TABLE (PREFIX_VEX_0F3836) },
9004 { PREFIX_TABLE (PREFIX_VEX_0F3837) },
9006 { PREFIX_TABLE (PREFIX_VEX_0F3838) },
9007 { PREFIX_TABLE (PREFIX_VEX_0F3839) },
9008 { PREFIX_TABLE (PREFIX_VEX_0F383A) },
9009 { PREFIX_TABLE (PREFIX_VEX_0F383B) },
9010 { PREFIX_TABLE (PREFIX_VEX_0F383C) },
9011 { PREFIX_TABLE (PREFIX_VEX_0F383D) },
9012 { PREFIX_TABLE (PREFIX_VEX_0F383E) },
9013 { PREFIX_TABLE (PREFIX_VEX_0F383F) },
9015 { PREFIX_TABLE (PREFIX_VEX_0F3840) },
9016 { PREFIX_TABLE (PREFIX_VEX_0F3841) },
9020 { PREFIX_TABLE (PREFIX_VEX_0F3845) },
9021 { PREFIX_TABLE (PREFIX_VEX_0F3846) },
9022 { PREFIX_TABLE (PREFIX_VEX_0F3847) },
9042 { PREFIX_TABLE (PREFIX_VEX_0F3858) },
9043 { PREFIX_TABLE (PREFIX_VEX_0F3859) },
9044 { PREFIX_TABLE (PREFIX_VEX_0F385A) },
9078 { PREFIX_TABLE (PREFIX_VEX_0F3878) },
9079 { PREFIX_TABLE (PREFIX_VEX_0F3879) },
9100 { PREFIX_TABLE (PREFIX_VEX_0F388C) },
9102 { PREFIX_TABLE (PREFIX_VEX_0F388E) },
9105 { PREFIX_TABLE (PREFIX_VEX_0F3890) },
9106 { PREFIX_TABLE (PREFIX_VEX_0F3891) },
9107 { PREFIX_TABLE (PREFIX_VEX_0F3892) },
9108 { PREFIX_TABLE (PREFIX_VEX_0F3893) },
9111 { PREFIX_TABLE (PREFIX_VEX_0F3896) },
9112 { PREFIX_TABLE (PREFIX_VEX_0F3897) },
9114 { PREFIX_TABLE (PREFIX_VEX_0F3898) },
9115 { PREFIX_TABLE (PREFIX_VEX_0F3899) },
9116 { PREFIX_TABLE (PREFIX_VEX_0F389A) },
9117 { PREFIX_TABLE (PREFIX_VEX_0F389B) },
9118 { PREFIX_TABLE (PREFIX_VEX_0F389C) },
9119 { PREFIX_TABLE (PREFIX_VEX_0F389D) },
9120 { PREFIX_TABLE (PREFIX_VEX_0F389E) },
9121 { PREFIX_TABLE (PREFIX_VEX_0F389F) },
9129 { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
9130 { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
9132 { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
9133 { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
9134 { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
9135 { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
9136 { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
9137 { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
9138 { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
9139 { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
9147 { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
9148 { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
9150 { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
9151 { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
9152 { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
9153 { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
9154 { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
9155 { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
9156 { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
9157 { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
9175 { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
9189 { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
9190 { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
9191 { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
9192 { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
9193 { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
9215 { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
9216 { REG_TABLE (REG_VEX_0F38F3) },
9218 { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
9219 { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
9220 { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
9234 { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
9235 { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
9236 { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
9238 { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
9239 { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
9240 { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
9243 { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
9244 { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
9245 { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
9246 { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
9247 { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
9248 { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
9249 { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
9250 { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
9256 { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
9257 { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
9258 { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
9259 { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
9261 { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
9262 { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
9266 { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
9270 { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
9271 { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
9272 { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
9288 { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
9289 { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
9290 { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
9291 { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
9297 { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
9298 { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
9306 { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
9307 { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
9308 { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
9310 { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
9312 { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
9315 { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
9316 { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
9317 { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
9318 { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
9319 { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
9337 { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
9338 { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
9339 { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
9340 { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
9342 { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
9343 { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
9344 { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
9345 { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
9351 { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
9352 { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
9353 { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
9354 { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
9355 { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
9356 { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
9357 { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
9358 { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
9369 { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
9370 { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
9371 { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
9372 { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
9373 { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
9374 { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
9375 { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
9376 { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
9465 { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
9466 { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
9484 { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
9504 { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
9524 #define NEED_OPCODE_TABLE
9525 #include "i386-dis-evex.h"
9526 #undef NEED_OPCODE_TABLE
9527 static const struct dis386 vex_len_table[][2] = {
9528 /* VEX_LEN_0F10_P_1 */
9530 { VEX_W_TABLE (VEX_W_0F10_P_1) },
9531 { VEX_W_TABLE (VEX_W_0F10_P_1) },
9534 /* VEX_LEN_0F10_P_3 */
9536 { VEX_W_TABLE (VEX_W_0F10_P_3) },
9537 { VEX_W_TABLE (VEX_W_0F10_P_3) },
9540 /* VEX_LEN_0F11_P_1 */
9542 { VEX_W_TABLE (VEX_W_0F11_P_1) },
9543 { VEX_W_TABLE (VEX_W_0F11_P_1) },
9546 /* VEX_LEN_0F11_P_3 */
9548 { VEX_W_TABLE (VEX_W_0F11_P_3) },
9549 { VEX_W_TABLE (VEX_W_0F11_P_3) },
9552 /* VEX_LEN_0F12_P_0_M_0 */
9554 { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
9557 /* VEX_LEN_0F12_P_0_M_1 */
9559 { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
9562 /* VEX_LEN_0F12_P_2 */
9564 { VEX_W_TABLE (VEX_W_0F12_P_2) },
9567 /* VEX_LEN_0F13_M_0 */
9569 { VEX_W_TABLE (VEX_W_0F13_M_0) },
9572 /* VEX_LEN_0F16_P_0_M_0 */
9574 { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
9577 /* VEX_LEN_0F16_P_0_M_1 */
9579 { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
9582 /* VEX_LEN_0F16_P_2 */
9584 { VEX_W_TABLE (VEX_W_0F16_P_2) },
9587 /* VEX_LEN_0F17_M_0 */
9589 { VEX_W_TABLE (VEX_W_0F17_M_0) },
9592 /* VEX_LEN_0F2A_P_1 */
9594 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
9595 { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
9598 /* VEX_LEN_0F2A_P_3 */
9600 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
9601 { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
9604 /* VEX_LEN_0F2C_P_1 */
9606 { "vcvttss2si", { Gv, EXdScalar }, 0 },
9607 { "vcvttss2si", { Gv, EXdScalar }, 0 },
9610 /* VEX_LEN_0F2C_P_3 */
9612 { "vcvttsd2si", { Gv, EXqScalar }, 0 },
9613 { "vcvttsd2si", { Gv, EXqScalar }, 0 },
9616 /* VEX_LEN_0F2D_P_1 */
9618 { "vcvtss2si", { Gv, EXdScalar }, 0 },
9619 { "vcvtss2si", { Gv, EXdScalar }, 0 },
9622 /* VEX_LEN_0F2D_P_3 */
9624 { "vcvtsd2si", { Gv, EXqScalar }, 0 },
9625 { "vcvtsd2si", { Gv, EXqScalar }, 0 },
9628 /* VEX_LEN_0F2E_P_0 */
9630 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9631 { VEX_W_TABLE (VEX_W_0F2E_P_0) },
9634 /* VEX_LEN_0F2E_P_2 */
9636 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9637 { VEX_W_TABLE (VEX_W_0F2E_P_2) },
9640 /* VEX_LEN_0F2F_P_0 */
9642 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9643 { VEX_W_TABLE (VEX_W_0F2F_P_0) },
9646 /* VEX_LEN_0F2F_P_2 */
9648 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9649 { VEX_W_TABLE (VEX_W_0F2F_P_2) },
9652 /* VEX_LEN_0F41_P_0 */
9655 { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
9657 /* VEX_LEN_0F41_P_2 */
9660 { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
9662 /* VEX_LEN_0F42_P_0 */
9665 { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
9667 /* VEX_LEN_0F42_P_2 */
9670 { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
9672 /* VEX_LEN_0F44_P_0 */
9674 { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
9676 /* VEX_LEN_0F44_P_2 */
9678 { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
9680 /* VEX_LEN_0F45_P_0 */
9683 { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
9685 /* VEX_LEN_0F45_P_2 */
9688 { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
9690 /* VEX_LEN_0F46_P_0 */
9693 { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
9695 /* VEX_LEN_0F46_P_2 */
9698 { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
9700 /* VEX_LEN_0F47_P_0 */
9703 { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
9705 /* VEX_LEN_0F47_P_2 */
9708 { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
9710 /* VEX_LEN_0F4A_P_0 */
9713 { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
9715 /* VEX_LEN_0F4A_P_2 */
9718 { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
9720 /* VEX_LEN_0F4B_P_0 */
9723 { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
9725 /* VEX_LEN_0F4B_P_2 */
9728 { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
9731 /* VEX_LEN_0F51_P_1 */
9733 { VEX_W_TABLE (VEX_W_0F51_P_1) },
9734 { VEX_W_TABLE (VEX_W_0F51_P_1) },
9737 /* VEX_LEN_0F51_P_3 */
9739 { VEX_W_TABLE (VEX_W_0F51_P_3) },
9740 { VEX_W_TABLE (VEX_W_0F51_P_3) },
9743 /* VEX_LEN_0F52_P_1 */
9745 { VEX_W_TABLE (VEX_W_0F52_P_1) },
9746 { VEX_W_TABLE (VEX_W_0F52_P_1) },
9749 /* VEX_LEN_0F53_P_1 */
9751 { VEX_W_TABLE (VEX_W_0F53_P_1) },
9752 { VEX_W_TABLE (VEX_W_0F53_P_1) },
9755 /* VEX_LEN_0F58_P_1 */
9757 { VEX_W_TABLE (VEX_W_0F58_P_1) },
9758 { VEX_W_TABLE (VEX_W_0F58_P_1) },
9761 /* VEX_LEN_0F58_P_3 */
9763 { VEX_W_TABLE (VEX_W_0F58_P_3) },
9764 { VEX_W_TABLE (VEX_W_0F58_P_3) },
9767 /* VEX_LEN_0F59_P_1 */
9769 { VEX_W_TABLE (VEX_W_0F59_P_1) },
9770 { VEX_W_TABLE (VEX_W_0F59_P_1) },
9773 /* VEX_LEN_0F59_P_3 */
9775 { VEX_W_TABLE (VEX_W_0F59_P_3) },
9776 { VEX_W_TABLE (VEX_W_0F59_P_3) },
9779 /* VEX_LEN_0F5A_P_1 */
9781 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9782 { VEX_W_TABLE (VEX_W_0F5A_P_1) },
9785 /* VEX_LEN_0F5A_P_3 */
9787 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9788 { VEX_W_TABLE (VEX_W_0F5A_P_3) },
9791 /* VEX_LEN_0F5C_P_1 */
9793 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9794 { VEX_W_TABLE (VEX_W_0F5C_P_1) },
9797 /* VEX_LEN_0F5C_P_3 */
9799 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9800 { VEX_W_TABLE (VEX_W_0F5C_P_3) },
9803 /* VEX_LEN_0F5D_P_1 */
9805 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9806 { VEX_W_TABLE (VEX_W_0F5D_P_1) },
9809 /* VEX_LEN_0F5D_P_3 */
9811 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9812 { VEX_W_TABLE (VEX_W_0F5D_P_3) },
9815 /* VEX_LEN_0F5E_P_1 */
9817 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9818 { VEX_W_TABLE (VEX_W_0F5E_P_1) },
9821 /* VEX_LEN_0F5E_P_3 */
9823 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9824 { VEX_W_TABLE (VEX_W_0F5E_P_3) },
9827 /* VEX_LEN_0F5F_P_1 */
9829 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9830 { VEX_W_TABLE (VEX_W_0F5F_P_1) },
9833 /* VEX_LEN_0F5F_P_3 */
9835 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9836 { VEX_W_TABLE (VEX_W_0F5F_P_3) },
9839 /* VEX_LEN_0F6E_P_2 */
9841 { "vmovK", { XMScalar, Edq }, 0 },
9842 { "vmovK", { XMScalar, Edq }, 0 },
9845 /* VEX_LEN_0F7E_P_1 */
9847 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9848 { VEX_W_TABLE (VEX_W_0F7E_P_1) },
9851 /* VEX_LEN_0F7E_P_2 */
9853 { "vmovK", { Edq, XMScalar }, 0 },
9854 { "vmovK", { Edq, XMScalar }, 0 },
9857 /* VEX_LEN_0F90_P_0 */
9859 { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
9862 /* VEX_LEN_0F90_P_2 */
9864 { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
9867 /* VEX_LEN_0F91_P_0 */
9869 { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
9872 /* VEX_LEN_0F91_P_2 */
9874 { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
9877 /* VEX_LEN_0F92_P_0 */
9879 { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
9882 /* VEX_LEN_0F92_P_2 */
9884 { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
9887 /* VEX_LEN_0F92_P_3 */
9889 { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
9892 /* VEX_LEN_0F93_P_0 */
9894 { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
9897 /* VEX_LEN_0F93_P_2 */
9899 { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
9902 /* VEX_LEN_0F93_P_3 */
9904 { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
9907 /* VEX_LEN_0F98_P_0 */
9909 { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
9912 /* VEX_LEN_0F98_P_2 */
9914 { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
9917 /* VEX_LEN_0F99_P_0 */
9919 { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
9922 /* VEX_LEN_0F99_P_2 */
9924 { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
9927 /* VEX_LEN_0FAE_R_2_M_0 */
9929 { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
9932 /* VEX_LEN_0FAE_R_3_M_0 */
9934 { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
9937 /* VEX_LEN_0FC2_P_1 */
9939 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9940 { VEX_W_TABLE (VEX_W_0FC2_P_1) },
9943 /* VEX_LEN_0FC2_P_3 */
9945 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9946 { VEX_W_TABLE (VEX_W_0FC2_P_3) },
9949 /* VEX_LEN_0FC4_P_2 */
9951 { VEX_W_TABLE (VEX_W_0FC4_P_2) },
9954 /* VEX_LEN_0FC5_P_2 */
9956 { VEX_W_TABLE (VEX_W_0FC5_P_2) },
9959 /* VEX_LEN_0FD6_P_2 */
9961 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9962 { VEX_W_TABLE (VEX_W_0FD6_P_2) },
9965 /* VEX_LEN_0FF7_P_2 */
9967 { VEX_W_TABLE (VEX_W_0FF7_P_2) },
9970 /* VEX_LEN_0F3816_P_2 */
9973 { VEX_W_TABLE (VEX_W_0F3816_P_2) },
9976 /* VEX_LEN_0F3819_P_2 */
9979 { VEX_W_TABLE (VEX_W_0F3819_P_2) },
9982 /* VEX_LEN_0F381A_P_2_M_0 */
9985 { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
9988 /* VEX_LEN_0F3836_P_2 */
9991 { VEX_W_TABLE (VEX_W_0F3836_P_2) },
9994 /* VEX_LEN_0F3841_P_2 */
9996 { VEX_W_TABLE (VEX_W_0F3841_P_2) },
9999 /* VEX_LEN_0F385A_P_2_M_0 */
10002 { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
10005 /* VEX_LEN_0F38DB_P_2 */
10007 { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
10010 /* VEX_LEN_0F38F2_P_0 */
10012 { "andnS", { Gdq, VexGdq, Edq }, 0 },
10015 /* VEX_LEN_0F38F3_R_1_P_0 */
10017 { "blsrS", { VexGdq, Edq }, 0 },
10020 /* VEX_LEN_0F38F3_R_2_P_0 */
10022 { "blsmskS", { VexGdq, Edq }, 0 },
10025 /* VEX_LEN_0F38F3_R_3_P_0 */
10027 { "blsiS", { VexGdq, Edq }, 0 },
10030 /* VEX_LEN_0F38F5_P_0 */
10032 { "bzhiS", { Gdq, Edq, VexGdq }, 0 },
10035 /* VEX_LEN_0F38F5_P_1 */
10037 { "pextS", { Gdq, VexGdq, Edq }, 0 },
10040 /* VEX_LEN_0F38F5_P_3 */
10042 { "pdepS", { Gdq, VexGdq, Edq }, 0 },
10045 /* VEX_LEN_0F38F6_P_3 */
10047 { "mulxS", { Gdq, VexGdq, Edq }, 0 },
10050 /* VEX_LEN_0F38F7_P_0 */
10052 { "bextrS", { Gdq, Edq, VexGdq }, 0 },
10055 /* VEX_LEN_0F38F7_P_1 */
10057 { "sarxS", { Gdq, Edq, VexGdq }, 0 },
10060 /* VEX_LEN_0F38F7_P_2 */
10062 { "shlxS", { Gdq, Edq, VexGdq }, 0 },
10065 /* VEX_LEN_0F38F7_P_3 */
10067 { "shrxS", { Gdq, Edq, VexGdq }, 0 },
10070 /* VEX_LEN_0F3A00_P_2 */
10073 { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
10076 /* VEX_LEN_0F3A01_P_2 */
10079 { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
10082 /* VEX_LEN_0F3A06_P_2 */
10085 { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
10088 /* VEX_LEN_0F3A0A_P_2 */
10090 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10091 { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
10094 /* VEX_LEN_0F3A0B_P_2 */
10096 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10097 { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
10100 /* VEX_LEN_0F3A14_P_2 */
10102 { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
10105 /* VEX_LEN_0F3A15_P_2 */
10107 { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
10110 /* VEX_LEN_0F3A16_P_2 */
10112 { "vpextrK", { Edq, XM, Ib }, 0 },
10115 /* VEX_LEN_0F3A17_P_2 */
10117 { "vextractps", { Edqd, XM, Ib }, 0 },
10120 /* VEX_LEN_0F3A18_P_2 */
10123 { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
10126 /* VEX_LEN_0F3A19_P_2 */
10129 { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
10132 /* VEX_LEN_0F3A20_P_2 */
10134 { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
10137 /* VEX_LEN_0F3A21_P_2 */
10139 { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
10142 /* VEX_LEN_0F3A22_P_2 */
10144 { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 },
10147 /* VEX_LEN_0F3A30_P_2 */
10149 { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
10152 /* VEX_LEN_0F3A31_P_2 */
10154 { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
10157 /* VEX_LEN_0F3A32_P_2 */
10159 { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
10162 /* VEX_LEN_0F3A33_P_2 */
10164 { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
10167 /* VEX_LEN_0F3A38_P_2 */
10170 { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
10173 /* VEX_LEN_0F3A39_P_2 */
10176 { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
10179 /* VEX_LEN_0F3A41_P_2 */
10181 { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
10184 /* VEX_LEN_0F3A46_P_2 */
10187 { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
10190 /* VEX_LEN_0F3A60_P_2 */
10192 { "vpcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10195 /* VEX_LEN_0F3A61_P_2 */
10197 { "vpcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
10200 /* VEX_LEN_0F3A62_P_2 */
10202 { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
10205 /* VEX_LEN_0F3A63_P_2 */
10207 { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
10210 /* VEX_LEN_0F3A6A_P_2 */
10212 { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10215 /* VEX_LEN_0F3A6B_P_2 */
10217 { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10220 /* VEX_LEN_0F3A6E_P_2 */
10222 { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10225 /* VEX_LEN_0F3A6F_P_2 */
10227 { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10230 /* VEX_LEN_0F3A7A_P_2 */
10232 { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10235 /* VEX_LEN_0F3A7B_P_2 */
10237 { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10240 /* VEX_LEN_0F3A7E_P_2 */
10242 { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
10245 /* VEX_LEN_0F3A7F_P_2 */
10247 { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
10250 /* VEX_LEN_0F3ADF_P_2 */
10252 { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
10255 /* VEX_LEN_0F3AF0_P_3 */
10257 { "rorxS", { Gdq, Edq, Ib }, 0 },
10260 /* VEX_LEN_0FXOP_08_CC */
10262 { "vpcomb", { XM, Vex128, EXx, VPCOM }, 0 },
10265 /* VEX_LEN_0FXOP_08_CD */
10267 { "vpcomw", { XM, Vex128, EXx, VPCOM }, 0 },
10270 /* VEX_LEN_0FXOP_08_CE */
10272 { "vpcomd", { XM, Vex128, EXx, VPCOM }, 0 },
10275 /* VEX_LEN_0FXOP_08_CF */
10277 { "vpcomq", { XM, Vex128, EXx, VPCOM }, 0 },
10280 /* VEX_LEN_0FXOP_08_EC */
10282 { "vpcomub", { XM, Vex128, EXx, VPCOM }, 0 },
10285 /* VEX_LEN_0FXOP_08_ED */
10287 { "vpcomuw", { XM, Vex128, EXx, VPCOM }, 0 },
10290 /* VEX_LEN_0FXOP_08_EE */
10292 { "vpcomud", { XM, Vex128, EXx, VPCOM }, 0 },
10295 /* VEX_LEN_0FXOP_08_EF */
10297 { "vpcomuq", { XM, Vex128, EXx, VPCOM }, 0 },
10300 /* VEX_LEN_0FXOP_09_80 */
10302 { "vfrczps", { XM, EXxmm }, 0 },
10303 { "vfrczps", { XM, EXymmq }, 0 },
10306 /* VEX_LEN_0FXOP_09_81 */
10308 { "vfrczpd", { XM, EXxmm }, 0 },
10309 { "vfrczpd", { XM, EXymmq }, 0 },
10313 static const struct dis386 vex_w_table[][2] = {
10315 /* VEX_W_0F10_P_0 */
10316 { "vmovups", { XM, EXx }, 0 },
10319 /* VEX_W_0F10_P_1 */
10320 { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 },
10323 /* VEX_W_0F10_P_2 */
10324 { "vmovupd", { XM, EXx }, 0 },
10327 /* VEX_W_0F10_P_3 */
10328 { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 },
10331 /* VEX_W_0F11_P_0 */
10332 { "vmovups", { EXxS, XM }, 0 },
10335 /* VEX_W_0F11_P_1 */
10336 { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 },
10339 /* VEX_W_0F11_P_2 */
10340 { "vmovupd", { EXxS, XM }, 0 },
10343 /* VEX_W_0F11_P_3 */
10344 { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 },
10347 /* VEX_W_0F12_P_0_M_0 */
10348 { "vmovlps", { XM, Vex128, EXq }, 0 },
10351 /* VEX_W_0F12_P_0_M_1 */
10352 { "vmovhlps", { XM, Vex128, EXq }, 0 },
10355 /* VEX_W_0F12_P_1 */
10356 { "vmovsldup", { XM, EXx }, 0 },
10359 /* VEX_W_0F12_P_2 */
10360 { "vmovlpd", { XM, Vex128, EXq }, 0 },
10363 /* VEX_W_0F12_P_3 */
10364 { "vmovddup", { XM, EXymmq }, 0 },
10367 /* VEX_W_0F13_M_0 */
10368 { "vmovlpX", { EXq, XM }, 0 },
10372 { "vunpcklpX", { XM, Vex, EXx }, 0 },
10376 { "vunpckhpX", { XM, Vex, EXx }, 0 },
10379 /* VEX_W_0F16_P_0_M_0 */
10380 { "vmovhps", { XM, Vex128, EXq }, 0 },
10383 /* VEX_W_0F16_P_0_M_1 */
10384 { "vmovlhps", { XM, Vex128, EXq }, 0 },
10387 /* VEX_W_0F16_P_1 */
10388 { "vmovshdup", { XM, EXx }, 0 },
10391 /* VEX_W_0F16_P_2 */
10392 { "vmovhpd", { XM, Vex128, EXq }, 0 },
10395 /* VEX_W_0F17_M_0 */
10396 { "vmovhpX", { EXq, XM }, 0 },
10400 { "vmovapX", { XM, EXx }, 0 },
10404 { "vmovapX", { EXxS, XM }, 0 },
10407 /* VEX_W_0F2B_M_0 */
10408 { "vmovntpX", { Mx, XM }, 0 },
10411 /* VEX_W_0F2E_P_0 */
10412 { "vucomiss", { XMScalar, EXdScalar }, 0 },
10415 /* VEX_W_0F2E_P_2 */
10416 { "vucomisd", { XMScalar, EXqScalar }, 0 },
10419 /* VEX_W_0F2F_P_0 */
10420 { "vcomiss", { XMScalar, EXdScalar }, 0 },
10423 /* VEX_W_0F2F_P_2 */
10424 { "vcomisd", { XMScalar, EXqScalar }, 0 },
10427 /* VEX_W_0F41_P_0_LEN_1 */
10428 { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
10429 { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
10432 /* VEX_W_0F41_P_2_LEN_1 */
10433 { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
10434 { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
10437 /* VEX_W_0F42_P_0_LEN_1 */
10438 { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
10439 { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
10442 /* VEX_W_0F42_P_2_LEN_1 */
10443 { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
10444 { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
10447 /* VEX_W_0F44_P_0_LEN_0 */
10448 { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
10449 { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
10452 /* VEX_W_0F44_P_2_LEN_0 */
10453 { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
10454 { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
10457 /* VEX_W_0F45_P_0_LEN_1 */
10458 { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
10459 { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
10462 /* VEX_W_0F45_P_2_LEN_1 */
10463 { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
10464 { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
10467 /* VEX_W_0F46_P_0_LEN_1 */
10468 { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
10469 { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
10472 /* VEX_W_0F46_P_2_LEN_1 */
10473 { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
10474 { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
10477 /* VEX_W_0F47_P_0_LEN_1 */
10478 { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
10479 { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
10482 /* VEX_W_0F47_P_2_LEN_1 */
10483 { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
10484 { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
10487 /* VEX_W_0F4A_P_0_LEN_1 */
10488 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
10489 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
10492 /* VEX_W_0F4A_P_2_LEN_1 */
10493 { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
10494 { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
10497 /* VEX_W_0F4B_P_0_LEN_1 */
10498 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
10499 { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
10502 /* VEX_W_0F4B_P_2_LEN_1 */
10503 { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
10506 /* VEX_W_0F50_M_0 */
10507 { "vmovmskpX", { Gdq, XS }, 0 },
10510 /* VEX_W_0F51_P_0 */
10511 { "vsqrtps", { XM, EXx }, 0 },
10514 /* VEX_W_0F51_P_1 */
10515 { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
10518 /* VEX_W_0F51_P_2 */
10519 { "vsqrtpd", { XM, EXx }, 0 },
10522 /* VEX_W_0F51_P_3 */
10523 { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10526 /* VEX_W_0F52_P_0 */
10527 { "vrsqrtps", { XM, EXx }, 0 },
10530 /* VEX_W_0F52_P_1 */
10531 { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
10534 /* VEX_W_0F53_P_0 */
10535 { "vrcpps", { XM, EXx }, 0 },
10538 /* VEX_W_0F53_P_1 */
10539 { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 },
10542 /* VEX_W_0F58_P_0 */
10543 { "vaddps", { XM, Vex, EXx }, 0 },
10546 /* VEX_W_0F58_P_1 */
10547 { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 },
10550 /* VEX_W_0F58_P_2 */
10551 { "vaddpd", { XM, Vex, EXx }, 0 },
10554 /* VEX_W_0F58_P_3 */
10555 { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10558 /* VEX_W_0F59_P_0 */
10559 { "vmulps", { XM, Vex, EXx }, 0 },
10562 /* VEX_W_0F59_P_1 */
10563 { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 },
10566 /* VEX_W_0F59_P_2 */
10567 { "vmulpd", { XM, Vex, EXx }, 0 },
10570 /* VEX_W_0F59_P_3 */
10571 { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10574 /* VEX_W_0F5A_P_0 */
10575 { "vcvtps2pd", { XM, EXxmmq }, 0 },
10578 /* VEX_W_0F5A_P_1 */
10579 { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 },
10582 /* VEX_W_0F5A_P_3 */
10583 { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 },
10586 /* VEX_W_0F5B_P_0 */
10587 { "vcvtdq2ps", { XM, EXx }, 0 },
10590 /* VEX_W_0F5B_P_1 */
10591 { "vcvttps2dq", { XM, EXx }, 0 },
10594 /* VEX_W_0F5B_P_2 */
10595 { "vcvtps2dq", { XM, EXx }, 0 },
10598 /* VEX_W_0F5C_P_0 */
10599 { "vsubps", { XM, Vex, EXx }, 0 },
10602 /* VEX_W_0F5C_P_1 */
10603 { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 },
10606 /* VEX_W_0F5C_P_2 */
10607 { "vsubpd", { XM, Vex, EXx }, 0 },
10610 /* VEX_W_0F5C_P_3 */
10611 { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10614 /* VEX_W_0F5D_P_0 */
10615 { "vminps", { XM, Vex, EXx }, 0 },
10618 /* VEX_W_0F5D_P_1 */
10619 { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 },
10622 /* VEX_W_0F5D_P_2 */
10623 { "vminpd", { XM, Vex, EXx }, 0 },
10626 /* VEX_W_0F5D_P_3 */
10627 { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10630 /* VEX_W_0F5E_P_0 */
10631 { "vdivps", { XM, Vex, EXx }, 0 },
10634 /* VEX_W_0F5E_P_1 */
10635 { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 },
10638 /* VEX_W_0F5E_P_2 */
10639 { "vdivpd", { XM, Vex, EXx }, 0 },
10642 /* VEX_W_0F5E_P_3 */
10643 { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10646 /* VEX_W_0F5F_P_0 */
10647 { "vmaxps", { XM, Vex, EXx }, 0 },
10650 /* VEX_W_0F5F_P_1 */
10651 { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 },
10654 /* VEX_W_0F5F_P_2 */
10655 { "vmaxpd", { XM, Vex, EXx }, 0 },
10658 /* VEX_W_0F5F_P_3 */
10659 { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 },
10662 /* VEX_W_0F60_P_2 */
10663 { "vpunpcklbw", { XM, Vex, EXx }, 0 },
10666 /* VEX_W_0F61_P_2 */
10667 { "vpunpcklwd", { XM, Vex, EXx }, 0 },
10670 /* VEX_W_0F62_P_2 */
10671 { "vpunpckldq", { XM, Vex, EXx }, 0 },
10674 /* VEX_W_0F63_P_2 */
10675 { "vpacksswb", { XM, Vex, EXx }, 0 },
10678 /* VEX_W_0F64_P_2 */
10679 { "vpcmpgtb", { XM, Vex, EXx }, 0 },
10682 /* VEX_W_0F65_P_2 */
10683 { "vpcmpgtw", { XM, Vex, EXx }, 0 },
10686 /* VEX_W_0F66_P_2 */
10687 { "vpcmpgtd", { XM, Vex, EXx }, 0 },
10690 /* VEX_W_0F67_P_2 */
10691 { "vpackuswb", { XM, Vex, EXx }, 0 },
10694 /* VEX_W_0F68_P_2 */
10695 { "vpunpckhbw", { XM, Vex, EXx }, 0 },
10698 /* VEX_W_0F69_P_2 */
10699 { "vpunpckhwd", { XM, Vex, EXx }, 0 },
10702 /* VEX_W_0F6A_P_2 */
10703 { "vpunpckhdq", { XM, Vex, EXx }, 0 },
10706 /* VEX_W_0F6B_P_2 */
10707 { "vpackssdw", { XM, Vex, EXx }, 0 },
10710 /* VEX_W_0F6C_P_2 */
10711 { "vpunpcklqdq", { XM, Vex, EXx }, 0 },
10714 /* VEX_W_0F6D_P_2 */
10715 { "vpunpckhqdq", { XM, Vex, EXx }, 0 },
10718 /* VEX_W_0F6F_P_1 */
10719 { "vmovdqu", { XM, EXx }, 0 },
10722 /* VEX_W_0F6F_P_2 */
10723 { "vmovdqa", { XM, EXx }, 0 },
10726 /* VEX_W_0F70_P_1 */
10727 { "vpshufhw", { XM, EXx, Ib }, 0 },
10730 /* VEX_W_0F70_P_2 */
10731 { "vpshufd", { XM, EXx, Ib }, 0 },
10734 /* VEX_W_0F70_P_3 */
10735 { "vpshuflw", { XM, EXx, Ib }, 0 },
10738 /* VEX_W_0F71_R_2_P_2 */
10739 { "vpsrlw", { Vex, XS, Ib }, 0 },
10742 /* VEX_W_0F71_R_4_P_2 */
10743 { "vpsraw", { Vex, XS, Ib }, 0 },
10746 /* VEX_W_0F71_R_6_P_2 */
10747 { "vpsllw", { Vex, XS, Ib }, 0 },
10750 /* VEX_W_0F72_R_2_P_2 */
10751 { "vpsrld", { Vex, XS, Ib }, 0 },
10754 /* VEX_W_0F72_R_4_P_2 */
10755 { "vpsrad", { Vex, XS, Ib }, 0 },
10758 /* VEX_W_0F72_R_6_P_2 */
10759 { "vpslld", { Vex, XS, Ib }, 0 },
10762 /* VEX_W_0F73_R_2_P_2 */
10763 { "vpsrlq", { Vex, XS, Ib }, 0 },
10766 /* VEX_W_0F73_R_3_P_2 */
10767 { "vpsrldq", { Vex, XS, Ib }, 0 },
10770 /* VEX_W_0F73_R_6_P_2 */
10771 { "vpsllq", { Vex, XS, Ib }, 0 },
10774 /* VEX_W_0F73_R_7_P_2 */
10775 { "vpslldq", { Vex, XS, Ib }, 0 },
10778 /* VEX_W_0F74_P_2 */
10779 { "vpcmpeqb", { XM, Vex, EXx }, 0 },
10782 /* VEX_W_0F75_P_2 */
10783 { "vpcmpeqw", { XM, Vex, EXx }, 0 },
10786 /* VEX_W_0F76_P_2 */
10787 { "vpcmpeqd", { XM, Vex, EXx }, 0 },
10790 /* VEX_W_0F77_P_0 */
10791 { "", { VZERO }, 0 },
10794 /* VEX_W_0F7C_P_2 */
10795 { "vhaddpd", { XM, Vex, EXx }, 0 },
10798 /* VEX_W_0F7C_P_3 */
10799 { "vhaddps", { XM, Vex, EXx }, 0 },
10802 /* VEX_W_0F7D_P_2 */
10803 { "vhsubpd", { XM, Vex, EXx }, 0 },
10806 /* VEX_W_0F7D_P_3 */
10807 { "vhsubps", { XM, Vex, EXx }, 0 },
10810 /* VEX_W_0F7E_P_1 */
10811 { "vmovq", { XMScalar, EXqScalar }, 0 },
10814 /* VEX_W_0F7F_P_1 */
10815 { "vmovdqu", { EXxS, XM }, 0 },
10818 /* VEX_W_0F7F_P_2 */
10819 { "vmovdqa", { EXxS, XM }, 0 },
10822 /* VEX_W_0F90_P_0_LEN_0 */
10823 { "kmovw", { MaskG, MaskE }, 0 },
10824 { "kmovq", { MaskG, MaskE }, 0 },
10827 /* VEX_W_0F90_P_2_LEN_0 */
10828 { "kmovb", { MaskG, MaskBDE }, 0 },
10829 { "kmovd", { MaskG, MaskBDE }, 0 },
10832 /* VEX_W_0F91_P_0_LEN_0 */
10833 { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
10834 { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
10837 /* VEX_W_0F91_P_2_LEN_0 */
10838 { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
10839 { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
10842 /* VEX_W_0F92_P_0_LEN_0 */
10843 { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
10846 /* VEX_W_0F92_P_2_LEN_0 */
10847 { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
10850 /* VEX_W_0F92_P_3_LEN_0 */
10851 { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
10852 { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
10855 /* VEX_W_0F93_P_0_LEN_0 */
10856 { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
10859 /* VEX_W_0F93_P_2_LEN_0 */
10860 { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
10863 /* VEX_W_0F93_P_3_LEN_0 */
10864 { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
10865 { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
10868 /* VEX_W_0F98_P_0_LEN_0 */
10869 { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
10870 { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
10873 /* VEX_W_0F98_P_2_LEN_0 */
10874 { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
10875 { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
10878 /* VEX_W_0F99_P_0_LEN_0 */
10879 { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
10880 { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
10883 /* VEX_W_0F99_P_2_LEN_0 */
10884 { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
10885 { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
10888 /* VEX_W_0FAE_R_2_M_0 */
10889 { "vldmxcsr", { Md }, 0 },
10892 /* VEX_W_0FAE_R_3_M_0 */
10893 { "vstmxcsr", { Md }, 0 },
10896 /* VEX_W_0FC2_P_0 */
10897 { "vcmpps", { XM, Vex, EXx, VCMP }, 0 },
10900 /* VEX_W_0FC2_P_1 */
10901 { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
10904 /* VEX_W_0FC2_P_2 */
10905 { "vcmppd", { XM, Vex, EXx, VCMP }, 0 },
10908 /* VEX_W_0FC2_P_3 */
10909 { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
10912 /* VEX_W_0FC4_P_2 */
10913 { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 },
10916 /* VEX_W_0FC5_P_2 */
10917 { "vpextrw", { Gdq, XS, Ib }, 0 },
10920 /* VEX_W_0FD0_P_2 */
10921 { "vaddsubpd", { XM, Vex, EXx }, 0 },
10924 /* VEX_W_0FD0_P_3 */
10925 { "vaddsubps", { XM, Vex, EXx }, 0 },
10928 /* VEX_W_0FD1_P_2 */
10929 { "vpsrlw", { XM, Vex, EXxmm }, 0 },
10932 /* VEX_W_0FD2_P_2 */
10933 { "vpsrld", { XM, Vex, EXxmm }, 0 },
10936 /* VEX_W_0FD3_P_2 */
10937 { "vpsrlq", { XM, Vex, EXxmm }, 0 },
10940 /* VEX_W_0FD4_P_2 */
10941 { "vpaddq", { XM, Vex, EXx }, 0 },
10944 /* VEX_W_0FD5_P_2 */
10945 { "vpmullw", { XM, Vex, EXx }, 0 },
10948 /* VEX_W_0FD6_P_2 */
10949 { "vmovq", { EXqScalarS, XMScalar }, 0 },
10952 /* VEX_W_0FD7_P_2_M_1 */
10953 { "vpmovmskb", { Gdq, XS }, 0 },
10956 /* VEX_W_0FD8_P_2 */
10957 { "vpsubusb", { XM, Vex, EXx }, 0 },
10960 /* VEX_W_0FD9_P_2 */
10961 { "vpsubusw", { XM, Vex, EXx }, 0 },
10964 /* VEX_W_0FDA_P_2 */
10965 { "vpminub", { XM, Vex, EXx }, 0 },
10968 /* VEX_W_0FDB_P_2 */
10969 { "vpand", { XM, Vex, EXx }, 0 },
10972 /* VEX_W_0FDC_P_2 */
10973 { "vpaddusb", { XM, Vex, EXx }, 0 },
10976 /* VEX_W_0FDD_P_2 */
10977 { "vpaddusw", { XM, Vex, EXx }, 0 },
10980 /* VEX_W_0FDE_P_2 */
10981 { "vpmaxub", { XM, Vex, EXx }, 0 },
10984 /* VEX_W_0FDF_P_2 */
10985 { "vpandn", { XM, Vex, EXx }, 0 },
10988 /* VEX_W_0FE0_P_2 */
10989 { "vpavgb", { XM, Vex, EXx }, 0 },
10992 /* VEX_W_0FE1_P_2 */
10993 { "vpsraw", { XM, Vex, EXxmm }, 0 },
10996 /* VEX_W_0FE2_P_2 */
10997 { "vpsrad", { XM, Vex, EXxmm }, 0 },
11000 /* VEX_W_0FE3_P_2 */
11001 { "vpavgw", { XM, Vex, EXx }, 0 },
11004 /* VEX_W_0FE4_P_2 */
11005 { "vpmulhuw", { XM, Vex, EXx }, 0 },
11008 /* VEX_W_0FE5_P_2 */
11009 { "vpmulhw", { XM, Vex, EXx }, 0 },
11012 /* VEX_W_0FE6_P_1 */
11013 { "vcvtdq2pd", { XM, EXxmmq }, 0 },
11016 /* VEX_W_0FE6_P_2 */
11017 { "vcvttpd2dq%XY", { XMM, EXx }, 0 },
11020 /* VEX_W_0FE6_P_3 */
11021 { "vcvtpd2dq%XY", { XMM, EXx }, 0 },
11024 /* VEX_W_0FE7_P_2_M_0 */
11025 { "vmovntdq", { Mx, XM }, 0 },
11028 /* VEX_W_0FE8_P_2 */
11029 { "vpsubsb", { XM, Vex, EXx }, 0 },
11032 /* VEX_W_0FE9_P_2 */
11033 { "vpsubsw", { XM, Vex, EXx }, 0 },
11036 /* VEX_W_0FEA_P_2 */
11037 { "vpminsw", { XM, Vex, EXx }, 0 },
11040 /* VEX_W_0FEB_P_2 */
11041 { "vpor", { XM, Vex, EXx }, 0 },
11044 /* VEX_W_0FEC_P_2 */
11045 { "vpaddsb", { XM, Vex, EXx }, 0 },
11048 /* VEX_W_0FED_P_2 */
11049 { "vpaddsw", { XM, Vex, EXx }, 0 },
11052 /* VEX_W_0FEE_P_2 */
11053 { "vpmaxsw", { XM, Vex, EXx }, 0 },
11056 /* VEX_W_0FEF_P_2 */
11057 { "vpxor", { XM, Vex, EXx }, 0 },
11060 /* VEX_W_0FF0_P_3_M_0 */
11061 { "vlddqu", { XM, M }, 0 },
11064 /* VEX_W_0FF1_P_2 */
11065 { "vpsllw", { XM, Vex, EXxmm }, 0 },
11068 /* VEX_W_0FF2_P_2 */
11069 { "vpslld", { XM, Vex, EXxmm }, 0 },
11072 /* VEX_W_0FF3_P_2 */
11073 { "vpsllq", { XM, Vex, EXxmm }, 0 },
11076 /* VEX_W_0FF4_P_2 */
11077 { "vpmuludq", { XM, Vex, EXx }, 0 },
11080 /* VEX_W_0FF5_P_2 */
11081 { "vpmaddwd", { XM, Vex, EXx }, 0 },
11084 /* VEX_W_0FF6_P_2 */
11085 { "vpsadbw", { XM, Vex, EXx }, 0 },
11088 /* VEX_W_0FF7_P_2 */
11089 { "vmaskmovdqu", { XM, XS }, 0 },
11092 /* VEX_W_0FF8_P_2 */
11093 { "vpsubb", { XM, Vex, EXx }, 0 },
11096 /* VEX_W_0FF9_P_2 */
11097 { "vpsubw", { XM, Vex, EXx }, 0 },
11100 /* VEX_W_0FFA_P_2 */
11101 { "vpsubd", { XM, Vex, EXx }, 0 },
11104 /* VEX_W_0FFB_P_2 */
11105 { "vpsubq", { XM, Vex, EXx }, 0 },
11108 /* VEX_W_0FFC_P_2 */
11109 { "vpaddb", { XM, Vex, EXx }, 0 },
11112 /* VEX_W_0FFD_P_2 */
11113 { "vpaddw", { XM, Vex, EXx }, 0 },
11116 /* VEX_W_0FFE_P_2 */
11117 { "vpaddd", { XM, Vex, EXx }, 0 },
11120 /* VEX_W_0F3800_P_2 */
11121 { "vpshufb", { XM, Vex, EXx }, 0 },
11124 /* VEX_W_0F3801_P_2 */
11125 { "vphaddw", { XM, Vex, EXx }, 0 },
11128 /* VEX_W_0F3802_P_2 */
11129 { "vphaddd", { XM, Vex, EXx }, 0 },
11132 /* VEX_W_0F3803_P_2 */
11133 { "vphaddsw", { XM, Vex, EXx }, 0 },
11136 /* VEX_W_0F3804_P_2 */
11137 { "vpmaddubsw", { XM, Vex, EXx }, 0 },
11140 /* VEX_W_0F3805_P_2 */
11141 { "vphsubw", { XM, Vex, EXx }, 0 },
11144 /* VEX_W_0F3806_P_2 */
11145 { "vphsubd", { XM, Vex, EXx }, 0 },
11148 /* VEX_W_0F3807_P_2 */
11149 { "vphsubsw", { XM, Vex, EXx }, 0 },
11152 /* VEX_W_0F3808_P_2 */
11153 { "vpsignb", { XM, Vex, EXx }, 0 },
11156 /* VEX_W_0F3809_P_2 */
11157 { "vpsignw", { XM, Vex, EXx }, 0 },
11160 /* VEX_W_0F380A_P_2 */
11161 { "vpsignd", { XM, Vex, EXx }, 0 },
11164 /* VEX_W_0F380B_P_2 */
11165 { "vpmulhrsw", { XM, Vex, EXx }, 0 },
11168 /* VEX_W_0F380C_P_2 */
11169 { "vpermilps", { XM, Vex, EXx }, 0 },
11172 /* VEX_W_0F380D_P_2 */
11173 { "vpermilpd", { XM, Vex, EXx }, 0 },
11176 /* VEX_W_0F380E_P_2 */
11177 { "vtestps", { XM, EXx }, 0 },
11180 /* VEX_W_0F380F_P_2 */
11181 { "vtestpd", { XM, EXx }, 0 },
11184 /* VEX_W_0F3816_P_2 */
11185 { "vpermps", { XM, Vex, EXx }, 0 },
11188 /* VEX_W_0F3817_P_2 */
11189 { "vptest", { XM, EXx }, 0 },
11192 /* VEX_W_0F3818_P_2 */
11193 { "vbroadcastss", { XM, EXxmm_md }, 0 },
11196 /* VEX_W_0F3819_P_2 */
11197 { "vbroadcastsd", { XM, EXxmm_mq }, 0 },
11200 /* VEX_W_0F381A_P_2_M_0 */
11201 { "vbroadcastf128", { XM, Mxmm }, 0 },
11204 /* VEX_W_0F381C_P_2 */
11205 { "vpabsb", { XM, EXx }, 0 },
11208 /* VEX_W_0F381D_P_2 */
11209 { "vpabsw", { XM, EXx }, 0 },
11212 /* VEX_W_0F381E_P_2 */
11213 { "vpabsd", { XM, EXx }, 0 },
11216 /* VEX_W_0F3820_P_2 */
11217 { "vpmovsxbw", { XM, EXxmmq }, 0 },
11220 /* VEX_W_0F3821_P_2 */
11221 { "vpmovsxbd", { XM, EXxmmqd }, 0 },
11224 /* VEX_W_0F3822_P_2 */
11225 { "vpmovsxbq", { XM, EXxmmdw }, 0 },
11228 /* VEX_W_0F3823_P_2 */
11229 { "vpmovsxwd", { XM, EXxmmq }, 0 },
11232 /* VEX_W_0F3824_P_2 */
11233 { "vpmovsxwq", { XM, EXxmmqd }, 0 },
11236 /* VEX_W_0F3825_P_2 */
11237 { "vpmovsxdq", { XM, EXxmmq }, 0 },
11240 /* VEX_W_0F3828_P_2 */
11241 { "vpmuldq", { XM, Vex, EXx }, 0 },
11244 /* VEX_W_0F3829_P_2 */
11245 { "vpcmpeqq", { XM, Vex, EXx }, 0 },
11248 /* VEX_W_0F382A_P_2_M_0 */
11249 { "vmovntdqa", { XM, Mx }, 0 },
11252 /* VEX_W_0F382B_P_2 */
11253 { "vpackusdw", { XM, Vex, EXx }, 0 },
11256 /* VEX_W_0F382C_P_2_M_0 */
11257 { "vmaskmovps", { XM, Vex, Mx }, 0 },
11260 /* VEX_W_0F382D_P_2_M_0 */
11261 { "vmaskmovpd", { XM, Vex, Mx }, 0 },
11264 /* VEX_W_0F382E_P_2_M_0 */
11265 { "vmaskmovps", { Mx, Vex, XM }, 0 },
11268 /* VEX_W_0F382F_P_2_M_0 */
11269 { "vmaskmovpd", { Mx, Vex, XM }, 0 },
11272 /* VEX_W_0F3830_P_2 */
11273 { "vpmovzxbw", { XM, EXxmmq }, 0 },
11276 /* VEX_W_0F3831_P_2 */
11277 { "vpmovzxbd", { XM, EXxmmqd }, 0 },
11280 /* VEX_W_0F3832_P_2 */
11281 { "vpmovzxbq", { XM, EXxmmdw }, 0 },
11284 /* VEX_W_0F3833_P_2 */
11285 { "vpmovzxwd", { XM, EXxmmq }, 0 },
11288 /* VEX_W_0F3834_P_2 */
11289 { "vpmovzxwq", { XM, EXxmmqd }, 0 },
11292 /* VEX_W_0F3835_P_2 */
11293 { "vpmovzxdq", { XM, EXxmmq }, 0 },
11296 /* VEX_W_0F3836_P_2 */
11297 { "vpermd", { XM, Vex, EXx }, 0 },
11300 /* VEX_W_0F3837_P_2 */
11301 { "vpcmpgtq", { XM, Vex, EXx }, 0 },
11304 /* VEX_W_0F3838_P_2 */
11305 { "vpminsb", { XM, Vex, EXx }, 0 },
11308 /* VEX_W_0F3839_P_2 */
11309 { "vpminsd", { XM, Vex, EXx }, 0 },
11312 /* VEX_W_0F383A_P_2 */
11313 { "vpminuw", { XM, Vex, EXx }, 0 },
11316 /* VEX_W_0F383B_P_2 */
11317 { "vpminud", { XM, Vex, EXx }, 0 },
11320 /* VEX_W_0F383C_P_2 */
11321 { "vpmaxsb", { XM, Vex, EXx }, 0 },
11324 /* VEX_W_0F383D_P_2 */
11325 { "vpmaxsd", { XM, Vex, EXx }, 0 },
11328 /* VEX_W_0F383E_P_2 */
11329 { "vpmaxuw", { XM, Vex, EXx }, 0 },
11332 /* VEX_W_0F383F_P_2 */
11333 { "vpmaxud", { XM, Vex, EXx }, 0 },
11336 /* VEX_W_0F3840_P_2 */
11337 { "vpmulld", { XM, Vex, EXx }, 0 },
11340 /* VEX_W_0F3841_P_2 */
11341 { "vphminposuw", { XM, EXx }, 0 },
11344 /* VEX_W_0F3846_P_2 */
11345 { "vpsravd", { XM, Vex, EXx }, 0 },
11348 /* VEX_W_0F3858_P_2 */
11349 { "vpbroadcastd", { XM, EXxmm_md }, 0 },
11352 /* VEX_W_0F3859_P_2 */
11353 { "vpbroadcastq", { XM, EXxmm_mq }, 0 },
11356 /* VEX_W_0F385A_P_2_M_0 */
11357 { "vbroadcasti128", { XM, Mxmm }, 0 },
11360 /* VEX_W_0F3878_P_2 */
11361 { "vpbroadcastb", { XM, EXxmm_mb }, 0 },
11364 /* VEX_W_0F3879_P_2 */
11365 { "vpbroadcastw", { XM, EXxmm_mw }, 0 },
11368 /* VEX_W_0F38CF_P_2 */
11369 { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
11372 /* VEX_W_0F38DB_P_2 */
11373 { "vaesimc", { XM, EXx }, 0 },
11376 /* VEX_W_0F3A00_P_2 */
11378 { "vpermq", { XM, EXx, Ib }, 0 },
11381 /* VEX_W_0F3A01_P_2 */
11383 { "vpermpd", { XM, EXx, Ib }, 0 },
11386 /* VEX_W_0F3A02_P_2 */
11387 { "vpblendd", { XM, Vex, EXx, Ib }, 0 },
11390 /* VEX_W_0F3A04_P_2 */
11391 { "vpermilps", { XM, EXx, Ib }, 0 },
11394 /* VEX_W_0F3A05_P_2 */
11395 { "vpermilpd", { XM, EXx, Ib }, 0 },
11398 /* VEX_W_0F3A06_P_2 */
11399 { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 },
11402 /* VEX_W_0F3A08_P_2 */
11403 { "vroundps", { XM, EXx, Ib }, 0 },
11406 /* VEX_W_0F3A09_P_2 */
11407 { "vroundpd", { XM, EXx, Ib }, 0 },
11410 /* VEX_W_0F3A0A_P_2 */
11411 { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
11414 /* VEX_W_0F3A0B_P_2 */
11415 { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
11418 /* VEX_W_0F3A0C_P_2 */
11419 { "vblendps", { XM, Vex, EXx, Ib }, 0 },
11422 /* VEX_W_0F3A0D_P_2 */
11423 { "vblendpd", { XM, Vex, EXx, Ib }, 0 },
11426 /* VEX_W_0F3A0E_P_2 */
11427 { "vpblendw", { XM, Vex, EXx, Ib }, 0 },
11430 /* VEX_W_0F3A0F_P_2 */
11431 { "vpalignr", { XM, Vex, EXx, Ib }, 0 },
11434 /* VEX_W_0F3A14_P_2 */
11435 { "vpextrb", { Edqb, XM, Ib }, 0 },
11438 /* VEX_W_0F3A15_P_2 */
11439 { "vpextrw", { Edqw, XM, Ib }, 0 },
11442 /* VEX_W_0F3A18_P_2 */
11443 { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 },
11446 /* VEX_W_0F3A19_P_2 */
11447 { "vextractf128", { EXxmm, XM, Ib }, 0 },
11450 /* VEX_W_0F3A20_P_2 */
11451 { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 },
11454 /* VEX_W_0F3A21_P_2 */
11455 { "vinsertps", { XM, Vex128, EXd, Ib }, 0 },
11458 /* VEX_W_0F3A30_P_2_LEN_0 */
11459 { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
11460 { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
11463 /* VEX_W_0F3A31_P_2_LEN_0 */
11464 { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
11465 { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
11468 /* VEX_W_0F3A32_P_2_LEN_0 */
11469 { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
11470 { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
11473 /* VEX_W_0F3A33_P_2_LEN_0 */
11474 { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
11475 { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
11478 /* VEX_W_0F3A38_P_2 */
11479 { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 },
11482 /* VEX_W_0F3A39_P_2 */
11483 { "vextracti128", { EXxmm, XM, Ib }, 0 },
11486 /* VEX_W_0F3A40_P_2 */
11487 { "vdpps", { XM, Vex, EXx, Ib }, 0 },
11490 /* VEX_W_0F3A41_P_2 */
11491 { "vdppd", { XM, Vex128, EXx, Ib }, 0 },
11494 /* VEX_W_0F3A42_P_2 */
11495 { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 },
11498 /* VEX_W_0F3A46_P_2 */
11499 { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 },
11502 /* VEX_W_0F3A48_P_2 */
11503 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11504 { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11507 /* VEX_W_0F3A49_P_2 */
11508 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11509 { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
11512 /* VEX_W_0F3A4A_P_2 */
11513 { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 },
11516 /* VEX_W_0F3A4B_P_2 */
11517 { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 },
11520 /* VEX_W_0F3A4C_P_2 */
11521 { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 },
11524 /* VEX_W_0F3A62_P_2 */
11525 { "vpcmpistrm", { XM, EXx, Ib }, 0 },
11528 /* VEX_W_0F3A63_P_2 */
11529 { "vpcmpistri", { XM, EXx, Ib }, 0 },
11532 /* VEX_W_0F3ACE_P_2 */
11534 { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
11537 /* VEX_W_0F3ACF_P_2 */
11539 { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, 0 },
11542 /* VEX_W_0F3ADF_P_2 */
11543 { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
11545 #define NEED_VEX_W_TABLE
11546 #include "i386-dis-evex.h"
11547 #undef NEED_VEX_W_TABLE
11550 static const struct dis386 mod_table[][2] = {
11553 { "leaS", { Gv, M }, 0 },
11558 { RM_TABLE (RM_C6_REG_7) },
11563 { RM_TABLE (RM_C7_REG_7) },
11567 { "Jcall^", { indirEp }, 0 },
11571 { "Jjmp^", { indirEp }, 0 },
11574 /* MOD_0F01_REG_0 */
11575 { X86_64_TABLE (X86_64_0F01_REG_0) },
11576 { RM_TABLE (RM_0F01_REG_0) },
11579 /* MOD_0F01_REG_1 */
11580 { X86_64_TABLE (X86_64_0F01_REG_1) },
11581 { RM_TABLE (RM_0F01_REG_1) },
11584 /* MOD_0F01_REG_2 */
11585 { X86_64_TABLE (X86_64_0F01_REG_2) },
11586 { RM_TABLE (RM_0F01_REG_2) },
11589 /* MOD_0F01_REG_3 */
11590 { X86_64_TABLE (X86_64_0F01_REG_3) },
11591 { RM_TABLE (RM_0F01_REG_3) },
11594 /* MOD_0F01_REG_5 */
11595 { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
11596 { RM_TABLE (RM_0F01_REG_5) },
11599 /* MOD_0F01_REG_7 */
11600 { "invlpg", { Mb }, 0 },
11601 { RM_TABLE (RM_0F01_REG_7) },
11604 /* MOD_0F12_PREFIX_0 */
11605 { "movlps", { XM, EXq }, PREFIX_OPCODE },
11606 { "movhlps", { XM, EXq }, PREFIX_OPCODE },
11610 { "movlpX", { EXq, XM }, PREFIX_OPCODE },
11613 /* MOD_0F16_PREFIX_0 */
11614 { "movhps", { XM, EXq }, 0 },
11615 { "movlhps", { XM, EXq }, 0 },
11619 { "movhpX", { EXq, XM }, PREFIX_OPCODE },
11622 /* MOD_0F18_REG_0 */
11623 { "prefetchnta", { Mb }, 0 },
11626 /* MOD_0F18_REG_1 */
11627 { "prefetcht0", { Mb }, 0 },
11630 /* MOD_0F18_REG_2 */
11631 { "prefetcht1", { Mb }, 0 },
11634 /* MOD_0F18_REG_3 */
11635 { "prefetcht2", { Mb }, 0 },
11638 /* MOD_0F18_REG_4 */
11639 { "nop/reserved", { Mb }, 0 },
11642 /* MOD_0F18_REG_5 */
11643 { "nop/reserved", { Mb }, 0 },
11646 /* MOD_0F18_REG_6 */
11647 { "nop/reserved", { Mb }, 0 },
11650 /* MOD_0F18_REG_7 */
11651 { "nop/reserved", { Mb }, 0 },
11654 /* MOD_0F1A_PREFIX_0 */
11655 { "bndldx", { Gbnd, Mv_bnd }, 0 },
11656 { "nopQ", { Ev }, 0 },
11659 /* MOD_0F1B_PREFIX_0 */
11660 { "bndstx", { Mv_bnd, Gbnd }, 0 },
11661 { "nopQ", { Ev }, 0 },
11664 /* MOD_0F1B_PREFIX_1 */
11665 { "bndmk", { Gbnd, Mv_bnd }, 0 },
11666 { "nopQ", { Ev }, 0 },
11669 /* MOD_0F1C_PREFIX_0 */
11670 { REG_TABLE (REG_0F1C_MOD_0) },
11671 { "nopQ", { Ev }, 0 },
11674 /* MOD_0F1E_PREFIX_1 */
11675 { "nopQ", { Ev }, 0 },
11676 { REG_TABLE (REG_0F1E_MOD_3) },
11681 { "movL", { Rd, Td }, 0 },
11686 { "movL", { Td, Rd }, 0 },
11689 /* MOD_0F2B_PREFIX_0 */
11690 {"movntps", { Mx, XM }, PREFIX_OPCODE },
11693 /* MOD_0F2B_PREFIX_1 */
11694 {"movntss", { Md, XM }, PREFIX_OPCODE },
11697 /* MOD_0F2B_PREFIX_2 */
11698 {"movntpd", { Mx, XM }, PREFIX_OPCODE },
11701 /* MOD_0F2B_PREFIX_3 */
11702 {"movntsd", { Mq, XM }, PREFIX_OPCODE },
11707 { "movmskpX", { Gdq, XS }, PREFIX_OPCODE },
11710 /* MOD_0F71_REG_2 */
11712 { "psrlw", { MS, Ib }, 0 },
11715 /* MOD_0F71_REG_4 */
11717 { "psraw", { MS, Ib }, 0 },
11720 /* MOD_0F71_REG_6 */
11722 { "psllw", { MS, Ib }, 0 },
11725 /* MOD_0F72_REG_2 */
11727 { "psrld", { MS, Ib }, 0 },
11730 /* MOD_0F72_REG_4 */
11732 { "psrad", { MS, Ib }, 0 },
11735 /* MOD_0F72_REG_6 */
11737 { "pslld", { MS, Ib }, 0 },
11740 /* MOD_0F73_REG_2 */
11742 { "psrlq", { MS, Ib }, 0 },
11745 /* MOD_0F73_REG_3 */
11747 { PREFIX_TABLE (PREFIX_0F73_REG_3) },
11750 /* MOD_0F73_REG_6 */
11752 { "psllq", { MS, Ib }, 0 },
11755 /* MOD_0F73_REG_7 */
11757 { PREFIX_TABLE (PREFIX_0F73_REG_7) },
11760 /* MOD_0FAE_REG_0 */
11761 { "fxsave", { FXSAVE }, 0 },
11762 { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
11765 /* MOD_0FAE_REG_1 */
11766 { "fxrstor", { FXSAVE }, 0 },
11767 { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
11770 /* MOD_0FAE_REG_2 */
11771 { "ldmxcsr", { Md }, 0 },
11772 { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
11775 /* MOD_0FAE_REG_3 */
11776 { "stmxcsr", { Md }, 0 },
11777 { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
11780 /* MOD_0FAE_REG_4 */
11781 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
11782 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
11785 /* MOD_0FAE_REG_5 */
11786 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
11787 { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
11790 /* MOD_0FAE_REG_6 */
11791 { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6) },
11792 { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6) },
11795 /* MOD_0FAE_REG_7 */
11796 { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
11797 { RM_TABLE (RM_0FAE_REG_7) },
11801 { "lssS", { Gv, Mp }, 0 },
11805 { "lfsS", { Gv, Mp }, 0 },
11809 { "lgsS", { Gv, Mp }, 0 },
11813 { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
11816 /* MOD_0FC7_REG_3 */
11817 { "xrstors", { FXSAVE }, 0 },
11820 /* MOD_0FC7_REG_4 */
11821 { "xsavec", { FXSAVE }, 0 },
11824 /* MOD_0FC7_REG_5 */
11825 { "xsaves", { FXSAVE }, 0 },
11828 /* MOD_0FC7_REG_6 */
11829 { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
11830 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
11833 /* MOD_0FC7_REG_7 */
11834 { "vmptrst", { Mq }, 0 },
11835 { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
11840 { "pmovmskb", { Gdq, MS }, 0 },
11843 /* MOD_0FE7_PREFIX_2 */
11844 { "movntdq", { Mx, XM }, 0 },
11847 /* MOD_0FF0_PREFIX_3 */
11848 { "lddqu", { XM, M }, 0 },
11851 /* MOD_0F382A_PREFIX_2 */
11852 { "movntdqa", { XM, Mx }, 0 },
11855 /* MOD_0F38F5_PREFIX_2 */
11856 { "wrussK", { M, Gdq }, PREFIX_OPCODE },
11859 /* MOD_0F38F6_PREFIX_0 */
11860 { "wrssK", { M, Gdq }, PREFIX_OPCODE },
11863 /* MOD_0F38F8_PREFIX_2 */
11864 { "movdir64b", { Gva, M }, PREFIX_OPCODE },
11867 /* MOD_0F38F9_PREFIX_0 */
11868 { "movdiri", { Em, Gv }, PREFIX_OPCODE },
11872 { "bound{S|}", { Gv, Ma }, 0 },
11873 { EVEX_TABLE (EVEX_0F) },
11877 { "lesS", { Gv, Mp }, 0 },
11878 { VEX_C4_TABLE (VEX_0F) },
11882 { "ldsS", { Gv, Mp }, 0 },
11883 { VEX_C5_TABLE (VEX_0F) },
11886 /* MOD_VEX_0F12_PREFIX_0 */
11887 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
11888 { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
11892 { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
11895 /* MOD_VEX_0F16_PREFIX_0 */
11896 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
11897 { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
11901 { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
11905 { VEX_W_TABLE (VEX_W_0F2B_M_0) },
11908 /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
11910 { "kandw", { MaskG, MaskVex, MaskR }, 0 },
11913 /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
11915 { "kandq", { MaskG, MaskVex, MaskR }, 0 },
11918 /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
11920 { "kandb", { MaskG, MaskVex, MaskR }, 0 },
11923 /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
11925 { "kandd", { MaskG, MaskVex, MaskR }, 0 },
11928 /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
11930 { "kandnw", { MaskG, MaskVex, MaskR }, 0 },
11933 /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
11935 { "kandnq", { MaskG, MaskVex, MaskR }, 0 },
11938 /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
11940 { "kandnb", { MaskG, MaskVex, MaskR }, 0 },
11943 /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
11945 { "kandnd", { MaskG, MaskVex, MaskR }, 0 },
11948 /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
11950 { "knotw", { MaskG, MaskR }, 0 },
11953 /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
11955 { "knotq", { MaskG, MaskR }, 0 },
11958 /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
11960 { "knotb", { MaskG, MaskR }, 0 },
11963 /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
11965 { "knotd", { MaskG, MaskR }, 0 },
11968 /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
11970 { "korw", { MaskG, MaskVex, MaskR }, 0 },
11973 /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
11975 { "korq", { MaskG, MaskVex, MaskR }, 0 },
11978 /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
11980 { "korb", { MaskG, MaskVex, MaskR }, 0 },
11983 /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
11985 { "kord", { MaskG, MaskVex, MaskR }, 0 },
11988 /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
11990 { "kxnorw", { MaskG, MaskVex, MaskR }, 0 },
11993 /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
11995 { "kxnorq", { MaskG, MaskVex, MaskR }, 0 },
11998 /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
12000 { "kxnorb", { MaskG, MaskVex, MaskR }, 0 },
12003 /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
12005 { "kxnord", { MaskG, MaskVex, MaskR }, 0 },
12008 /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
12010 { "kxorw", { MaskG, MaskVex, MaskR }, 0 },
12013 /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
12015 { "kxorq", { MaskG, MaskVex, MaskR }, 0 },
12018 /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
12020 { "kxorb", { MaskG, MaskVex, MaskR }, 0 },
12023 /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
12025 { "kxord", { MaskG, MaskVex, MaskR }, 0 },
12028 /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
12030 { "kaddw", { MaskG, MaskVex, MaskR }, 0 },
12033 /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
12035 { "kaddq", { MaskG, MaskVex, MaskR }, 0 },
12038 /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
12040 { "kaddb", { MaskG, MaskVex, MaskR }, 0 },
12043 /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
12045 { "kaddd", { MaskG, MaskVex, MaskR }, 0 },
12048 /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
12050 { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 },
12053 /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
12055 { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 },
12058 /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
12060 { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 },
12065 { VEX_W_TABLE (VEX_W_0F50_M_0) },
12068 /* MOD_VEX_0F71_REG_2 */
12070 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
12073 /* MOD_VEX_0F71_REG_4 */
12075 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
12078 /* MOD_VEX_0F71_REG_6 */
12080 { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
12083 /* MOD_VEX_0F72_REG_2 */
12085 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
12088 /* MOD_VEX_0F72_REG_4 */
12090 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
12093 /* MOD_VEX_0F72_REG_6 */
12095 { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
12098 /* MOD_VEX_0F73_REG_2 */
12100 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
12103 /* MOD_VEX_0F73_REG_3 */
12105 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
12108 /* MOD_VEX_0F73_REG_6 */
12110 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
12113 /* MOD_VEX_0F73_REG_7 */
12115 { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
12118 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12119 { "kmovw", { Ew, MaskG }, 0 },
12123 /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
12124 { "kmovq", { Eq, MaskG }, 0 },
12128 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12129 { "kmovb", { Eb, MaskG }, 0 },
12133 /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
12134 { "kmovd", { Ed, MaskG }, 0 },
12138 /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
12140 { "kmovw", { MaskG, Rdq }, 0 },
12143 /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
12145 { "kmovb", { MaskG, Rdq }, 0 },
12148 /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
12150 { "kmovd", { MaskG, Rdq }, 0 },
12153 /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
12155 { "kmovq", { MaskG, Rdq }, 0 },
12158 /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
12160 { "kmovw", { Gdq, MaskR }, 0 },
12163 /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
12165 { "kmovb", { Gdq, MaskR }, 0 },
12168 /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
12170 { "kmovd", { Gdq, MaskR }, 0 },
12173 /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
12175 { "kmovq", { Gdq, MaskR }, 0 },
12178 /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
12180 { "kortestw", { MaskG, MaskR }, 0 },
12183 /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
12185 { "kortestq", { MaskG, MaskR }, 0 },
12188 /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
12190 { "kortestb", { MaskG, MaskR }, 0 },
12193 /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
12195 { "kortestd", { MaskG, MaskR }, 0 },
12198 /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
12200 { "ktestw", { MaskG, MaskR }, 0 },
12203 /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
12205 { "ktestq", { MaskG, MaskR }, 0 },
12208 /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
12210 { "ktestb", { MaskG, MaskR }, 0 },
12213 /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
12215 { "ktestd", { MaskG, MaskR }, 0 },
12218 /* MOD_VEX_0FAE_REG_2 */
12219 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
12222 /* MOD_VEX_0FAE_REG_3 */
12223 { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
12226 /* MOD_VEX_0FD7_PREFIX_2 */
12228 { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
12231 /* MOD_VEX_0FE7_PREFIX_2 */
12232 { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
12235 /* MOD_VEX_0FF0_PREFIX_3 */
12236 { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
12239 /* MOD_VEX_0F381A_PREFIX_2 */
12240 { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
12243 /* MOD_VEX_0F382A_PREFIX_2 */
12244 { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
12247 /* MOD_VEX_0F382C_PREFIX_2 */
12248 { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
12251 /* MOD_VEX_0F382D_PREFIX_2 */
12252 { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
12255 /* MOD_VEX_0F382E_PREFIX_2 */
12256 { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
12259 /* MOD_VEX_0F382F_PREFIX_2 */
12260 { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
12263 /* MOD_VEX_0F385A_PREFIX_2 */
12264 { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
12267 /* MOD_VEX_0F388C_PREFIX_2 */
12268 { "vpmaskmov%LW", { XM, Vex, Mx }, 0 },
12271 /* MOD_VEX_0F388E_PREFIX_2 */
12272 { "vpmaskmov%LW", { Mx, Vex, XM }, 0 },
12275 /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
12277 { "kshiftrb", { MaskG, MaskR, Ib }, 0 },
12280 /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
12282 { "kshiftrw", { MaskG, MaskR, Ib }, 0 },
12285 /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
12287 { "kshiftrd", { MaskG, MaskR, Ib }, 0 },
12290 /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
12292 { "kshiftrq", { MaskG, MaskR, Ib }, 0 },
12295 /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
12297 { "kshiftlb", { MaskG, MaskR, Ib }, 0 },
12300 /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
12302 { "kshiftlw", { MaskG, MaskR, Ib }, 0 },
12305 /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
12307 { "kshiftld", { MaskG, MaskR, Ib }, 0 },
12310 /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
12312 { "kshiftlq", { MaskG, MaskR, Ib }, 0 },
12314 #define NEED_MOD_TABLE
12315 #include "i386-dis-evex.h"
12316 #undef NEED_MOD_TABLE
12319 static const struct dis386 rm_table[][8] = {
12322 { "xabort", { Skip_MODRM, Ib }, 0 },
12326 { "xbeginT", { Skip_MODRM, Jv }, 0 },
12329 /* RM_0F01_REG_0 */
12331 { "vmcall", { Skip_MODRM }, 0 },
12332 { "vmlaunch", { Skip_MODRM }, 0 },
12333 { "vmresume", { Skip_MODRM }, 0 },
12334 { "vmxoff", { Skip_MODRM }, 0 },
12335 { "pconfig", { Skip_MODRM }, 0 },
12338 /* RM_0F01_REG_1 */
12339 { "monitor", { { OP_Monitor, 0 } }, 0 },
12340 { "mwait", { { OP_Mwait, 0 } }, 0 },
12341 { "clac", { Skip_MODRM }, 0 },
12342 { "stac", { Skip_MODRM }, 0 },
12346 { "encls", { Skip_MODRM }, 0 },
12349 /* RM_0F01_REG_2 */
12350 { "xgetbv", { Skip_MODRM }, 0 },
12351 { "xsetbv", { Skip_MODRM }, 0 },
12354 { "vmfunc", { Skip_MODRM }, 0 },
12355 { "xend", { Skip_MODRM }, 0 },
12356 { "xtest", { Skip_MODRM }, 0 },
12357 { "enclu", { Skip_MODRM }, 0 },
12360 /* RM_0F01_REG_3 */
12361 { "vmrun", { Skip_MODRM }, 0 },
12362 { "vmmcall", { Skip_MODRM }, 0 },
12363 { "vmload", { Skip_MODRM }, 0 },
12364 { "vmsave", { Skip_MODRM }, 0 },
12365 { "stgi", { Skip_MODRM }, 0 },
12366 { "clgi", { Skip_MODRM }, 0 },
12367 { "skinit", { Skip_MODRM }, 0 },
12368 { "invlpga", { Skip_MODRM }, 0 },
12371 /* RM_0F01_REG_5 */
12372 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
12374 { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
12378 { "rdpkru", { Skip_MODRM }, 0 },
12379 { "wrpkru", { Skip_MODRM }, 0 },
12382 /* RM_0F01_REG_7 */
12383 { "swapgs", { Skip_MODRM }, 0 },
12384 { "rdtscp", { Skip_MODRM }, 0 },
12385 { "monitorx", { { OP_Monitor, 0 } }, 0 },
12386 { "mwaitx", { { OP_Mwaitx, 0 } }, 0 },
12387 { "clzero", { Skip_MODRM }, 0 },
12390 /* RM_0F1E_MOD_3_REG_7 */
12391 { "nopQ", { Ev }, 0 },
12392 { "nopQ", { Ev }, 0 },
12393 { "endbr64", { Skip_MODRM }, PREFIX_OPCODE },
12394 { "endbr32", { Skip_MODRM }, PREFIX_OPCODE },
12395 { "nopQ", { Ev }, 0 },
12396 { "nopQ", { Ev }, 0 },
12397 { "nopQ", { Ev }, 0 },
12398 { "nopQ", { Ev }, 0 },
12401 /* RM_0FAE_REG_6 */
12402 { "mfence", { Skip_MODRM }, 0 },
12405 /* RM_0FAE_REG_7 */
12406 { "sfence", { Skip_MODRM }, 0 },
12411 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
12413 /* We use the high bit to indicate different name for the same
12415 #define REP_PREFIX (0xf3 | 0x100)
12416 #define XACQUIRE_PREFIX (0xf2 | 0x200)
12417 #define XRELEASE_PREFIX (0xf3 | 0x400)
12418 #define BND_PREFIX (0xf2 | 0x400)
12419 #define NOTRACK_PREFIX (0x3e | 0x100)
12424 int newrex, i, length;
12430 last_lock_prefix = -1;
12431 last_repz_prefix = -1;
12432 last_repnz_prefix = -1;
12433 last_data_prefix = -1;
12434 last_addr_prefix = -1;
12435 last_rex_prefix = -1;
12436 last_seg_prefix = -1;
12438 active_seg_prefix = 0;
12439 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
12440 all_prefixes[i] = 0;
12443 /* The maximum instruction length is 15bytes. */
12444 while (length < MAX_CODE_LENGTH - 1)
12446 FETCH_DATA (the_info, codep + 1);
12450 /* REX prefixes family. */
12467 if (address_mode == mode_64bit)
12471 last_rex_prefix = i;
12474 prefixes |= PREFIX_REPZ;
12475 last_repz_prefix = i;
12478 prefixes |= PREFIX_REPNZ;
12479 last_repnz_prefix = i;
12482 prefixes |= PREFIX_LOCK;
12483 last_lock_prefix = i;
12486 prefixes |= PREFIX_CS;
12487 last_seg_prefix = i;
12488 active_seg_prefix = PREFIX_CS;
12491 prefixes |= PREFIX_SS;
12492 last_seg_prefix = i;
12493 active_seg_prefix = PREFIX_SS;
12496 prefixes |= PREFIX_DS;
12497 last_seg_prefix = i;
12498 active_seg_prefix = PREFIX_DS;
12501 prefixes |= PREFIX_ES;
12502 last_seg_prefix = i;
12503 active_seg_prefix = PREFIX_ES;
12506 prefixes |= PREFIX_FS;
12507 last_seg_prefix = i;
12508 active_seg_prefix = PREFIX_FS;
12511 prefixes |= PREFIX_GS;
12512 last_seg_prefix = i;
12513 active_seg_prefix = PREFIX_GS;
12516 prefixes |= PREFIX_DATA;
12517 last_data_prefix = i;
12520 prefixes |= PREFIX_ADDR;
12521 last_addr_prefix = i;
12524 /* fwait is really an instruction. If there are prefixes
12525 before the fwait, they belong to the fwait, *not* to the
12526 following instruction. */
12528 if (prefixes || rex)
12530 prefixes |= PREFIX_FWAIT;
12532 /* This ensures that the previous REX prefixes are noticed
12533 as unused prefixes, as in the return case below. */
12537 prefixes = PREFIX_FWAIT;
12542 /* Rex is ignored when followed by another prefix. */
12548 if (*codep != FWAIT_OPCODE)
12549 all_prefixes[i++] = *codep;
12557 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
12560 static const char *
12561 prefix_name (int pref, int sizeflag)
12563 static const char *rexes [16] =
12566 "rex.B", /* 0x41 */
12567 "rex.X", /* 0x42 */
12568 "rex.XB", /* 0x43 */
12569 "rex.R", /* 0x44 */
12570 "rex.RB", /* 0x45 */
12571 "rex.RX", /* 0x46 */
12572 "rex.RXB", /* 0x47 */
12573 "rex.W", /* 0x48 */
12574 "rex.WB", /* 0x49 */
12575 "rex.WX", /* 0x4a */
12576 "rex.WXB", /* 0x4b */
12577 "rex.WR", /* 0x4c */
12578 "rex.WRB", /* 0x4d */
12579 "rex.WRX", /* 0x4e */
12580 "rex.WRXB", /* 0x4f */
12585 /* REX prefixes family. */
12602 return rexes [pref - 0x40];
12622 return (sizeflag & DFLAG) ? "data16" : "data32";
12624 if (address_mode == mode_64bit)
12625 return (sizeflag & AFLAG) ? "addr32" : "addr64";
12627 return (sizeflag & AFLAG) ? "addr16" : "addr32";
12632 case XACQUIRE_PREFIX:
12634 case XRELEASE_PREFIX:
12638 case NOTRACK_PREFIX:
12645 static char op_out[MAX_OPERANDS][100];
12646 static int op_ad, op_index[MAX_OPERANDS];
12647 static int two_source_ops;
12648 static bfd_vma op_address[MAX_OPERANDS];
12649 static bfd_vma op_riprel[MAX_OPERANDS];
12650 static bfd_vma start_pc;
12653 * On the 386's of 1988, the maximum length of an instruction is 15 bytes.
12654 * (see topic "Redundant prefixes" in the "Differences from 8086"
12655 * section of the "Virtual 8086 Mode" chapter.)
12656 * 'pc' should be the address of this instruction, it will
12657 * be used to print the target address if this is a relative jump or call
12658 * The function returns the length of this instruction in bytes.
12661 static char intel_syntax;
12662 static char intel_mnemonic = !SYSV386_COMPAT;
12663 static char open_char;
12664 static char close_char;
12665 static char separator_char;
12666 static char scale_char;
12674 static enum x86_64_isa isa64;
12676 /* Here for backwards compatibility. When gdb stops using
12677 print_insn_i386_att and print_insn_i386_intel these functions can
12678 disappear, and print_insn_i386 be merged into print_insn. */
12680 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
12684 return print_insn (pc, info);
12688 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
12692 return print_insn (pc, info);
12696 print_insn_i386 (bfd_vma pc, disassemble_info *info)
12700 return print_insn (pc, info);
12704 print_i386_disassembler_options (FILE *stream)
12706 fprintf (stream, _("\n\
12707 The following i386/x86-64 specific disassembler options are supported for use\n\
12708 with the -M switch (multiple options should be separated by commas):\n"));
12710 fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n"));
12711 fprintf (stream, _(" i386 Disassemble in 32bit mode\n"));
12712 fprintf (stream, _(" i8086 Disassemble in 16bit mode\n"));
12713 fprintf (stream, _(" att Display instruction in AT&T syntax\n"));
12714 fprintf (stream, _(" intel Display instruction in Intel syntax\n"));
12715 fprintf (stream, _(" att-mnemonic\n"
12716 " Display instruction in AT&T mnemonic\n"));
12717 fprintf (stream, _(" intel-mnemonic\n"
12718 " Display instruction in Intel mnemonic\n"));
12719 fprintf (stream, _(" addr64 Assume 64bit address size\n"));
12720 fprintf (stream, _(" addr32 Assume 32bit address size\n"));
12721 fprintf (stream, _(" addr16 Assume 16bit address size\n"));
12722 fprintf (stream, _(" data32 Assume 32bit data size\n"));
12723 fprintf (stream, _(" data16 Assume 16bit data size\n"));
12724 fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n"));
12725 fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n"));
12726 fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n"));
12730 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
12732 /* Get a pointer to struct dis386 with a valid name. */
12734 static const struct dis386 *
12735 get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
12737 int vindex, vex_table_index;
12739 if (dp->name != NULL)
12742 switch (dp->op[0].bytemode)
12744 case USE_REG_TABLE:
12745 dp = ®_table[dp->op[1].bytemode][modrm.reg];
12748 case USE_MOD_TABLE:
12749 vindex = modrm.mod == 0x3 ? 1 : 0;
12750 dp = &mod_table[dp->op[1].bytemode][vindex];
12754 dp = &rm_table[dp->op[1].bytemode][modrm.rm];
12757 case USE_PREFIX_TABLE:
12760 /* The prefix in VEX is implicit. */
12761 switch (vex.prefix)
12766 case REPE_PREFIX_OPCODE:
12769 case DATA_PREFIX_OPCODE:
12772 case REPNE_PREFIX_OPCODE:
12782 int last_prefix = -1;
12785 /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
12786 When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
12788 if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
12790 if (last_repz_prefix > last_repnz_prefix)
12793 prefix = PREFIX_REPZ;
12794 last_prefix = last_repz_prefix;
12799 prefix = PREFIX_REPNZ;
12800 last_prefix = last_repnz_prefix;
12803 /* Check if prefix should be ignored. */
12804 if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
12805 & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
12810 if (vindex == 0 && (prefixes & PREFIX_DATA) != 0)
12813 prefix = PREFIX_DATA;
12814 last_prefix = last_data_prefix;
12819 used_prefixes |= prefix;
12820 all_prefixes[last_prefix] = 0;
12823 dp = &prefix_table[dp->op[1].bytemode][vindex];
12826 case USE_X86_64_TABLE:
12827 vindex = address_mode == mode_64bit ? 1 : 0;
12828 dp = &x86_64_table[dp->op[1].bytemode][vindex];
12831 case USE_3BYTE_TABLE:
12832 FETCH_DATA (info, codep + 2);
12834 dp = &three_byte_table[dp->op[1].bytemode][vindex];
12836 modrm.mod = (*codep >> 6) & 3;
12837 modrm.reg = (*codep >> 3) & 7;
12838 modrm.rm = *codep & 7;
12841 case USE_VEX_LEN_TABLE:
12845 switch (vex.length)
12858 dp = &vex_len_table[dp->op[1].bytemode][vindex];
12861 case USE_XOP_8F_TABLE:
12862 FETCH_DATA (info, codep + 3);
12863 /* All bits in the REX prefix are ignored. */
12865 rex = ~(*codep >> 5) & 0x7;
12867 /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
12868 switch ((*codep & 0x1f))
12874 vex_table_index = XOP_08;
12877 vex_table_index = XOP_09;
12880 vex_table_index = XOP_0A;
12884 vex.w = *codep & 0x80;
12885 if (vex.w && address_mode == mode_64bit)
12888 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12889 if (address_mode != mode_64bit)
12891 /* In 16/32-bit mode REX_B is silently ignored. */
12895 vex.length = (*codep & 0x4) ? 256 : 128;
12896 switch ((*codep & 0x3))
12901 vex.prefix = DATA_PREFIX_OPCODE;
12904 vex.prefix = REPE_PREFIX_OPCODE;
12907 vex.prefix = REPNE_PREFIX_OPCODE;
12914 dp = &xop_table[vex_table_index][vindex];
12917 FETCH_DATA (info, codep + 1);
12918 modrm.mod = (*codep >> 6) & 3;
12919 modrm.reg = (*codep >> 3) & 7;
12920 modrm.rm = *codep & 7;
12923 case USE_VEX_C4_TABLE:
12925 FETCH_DATA (info, codep + 3);
12926 /* All bits in the REX prefix are ignored. */
12928 rex = ~(*codep >> 5) & 0x7;
12929 switch ((*codep & 0x1f))
12935 vex_table_index = VEX_0F;
12938 vex_table_index = VEX_0F38;
12941 vex_table_index = VEX_0F3A;
12945 vex.w = *codep & 0x80;
12946 if (address_mode == mode_64bit)
12953 /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
12954 is ignored, other REX bits are 0 and the highest bit in
12955 VEX.vvvv is also ignored (but we mustn't clear it here). */
12958 vex.register_specifier = (~(*codep >> 3)) & 0xf;
12959 vex.length = (*codep & 0x4) ? 256 : 128;
12960 switch ((*codep & 0x3))
12965 vex.prefix = DATA_PREFIX_OPCODE;
12968 vex.prefix = REPE_PREFIX_OPCODE;
12971 vex.prefix = REPNE_PREFIX_OPCODE;
12978 dp = &vex_table[vex_table_index][vindex];
12980 /* There is no MODRM byte for VEX0F 77. */
12981 if (vex_table_index != VEX_0F || vindex != 0x77)
12983 FETCH_DATA (info, codep + 1);
12984 modrm.mod = (*codep >> 6) & 3;
12985 modrm.reg = (*codep >> 3) & 7;
12986 modrm.rm = *codep & 7;
12990 case USE_VEX_C5_TABLE:
12992 FETCH_DATA (info, codep + 2);
12993 /* All bits in the REX prefix are ignored. */
12995 rex = (*codep & 0x80) ? 0 : REX_R;
12997 /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
12999 vex.register_specifier = (~(*codep >> 3)) & 0xf;
13000 vex.length = (*codep & 0x4) ? 256 : 128;
13001 switch ((*codep & 0x3))
13006 vex.prefix = DATA_PREFIX_OPCODE;
13009 vex.prefix = REPE_PREFIX_OPCODE;
13012 vex.prefix = REPNE_PREFIX_OPCODE;
13019 dp = &vex_table[dp->op[1].bytemode][vindex];
13021 /* There is no MODRM byte for VEX 77. */
13022 if (vindex != 0x77)
13024 FETCH_DATA (info, codep + 1);
13025 modrm.mod = (*codep >> 6) & 3;
13026 modrm.reg = (*codep >> 3) & 7;
13027 modrm.rm = *codep & 7;
13031 case USE_VEX_W_TABLE:
13035 dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0];
13038 case USE_EVEX_TABLE:
13039 two_source_ops = 0;
13042 FETCH_DATA (info, codep + 4);
13043 /* All bits in the REX prefix are ignored. */
13045 /* The first byte after 0x62. */
13046 rex = ~(*codep >> 5) & 0x7;
13047 vex.r = *codep & 0x10;
13048 switch ((*codep & 0xf))
13051 return &bad_opcode;
13053 vex_table_index = EVEX_0F;
13056 vex_table_index = EVEX_0F38;
13059 vex_table_index = EVEX_0F3A;
13063 /* The second byte after 0x62. */
13065 vex.w = *codep & 0x80;
13066 if (vex.w && address_mode == mode_64bit)
13069 vex.register_specifier = (~(*codep >> 3)) & 0xf;
13072 if (!(*codep & 0x4))
13073 return &bad_opcode;
13075 switch ((*codep & 0x3))
13080 vex.prefix = DATA_PREFIX_OPCODE;
13083 vex.prefix = REPE_PREFIX_OPCODE;
13086 vex.prefix = REPNE_PREFIX_OPCODE;
13090 /* The third byte after 0x62. */
13093 /* Remember the static rounding bits. */
13094 vex.ll = (*codep >> 5) & 3;
13095 vex.b = (*codep & 0x10) != 0;
13097 vex.v = *codep & 0x8;
13098 vex.mask_register_specifier = *codep & 0x7;
13099 vex.zeroing = *codep & 0x80;
13101 if (address_mode != mode_64bit)
13103 /* In 16/32-bit mode silently ignore following bits. */
13113 dp = &evex_table[vex_table_index][vindex];
13115 FETCH_DATA (info, codep + 1);
13116 modrm.mod = (*codep >> 6) & 3;
13117 modrm.reg = (*codep >> 3) & 7;
13118 modrm.rm = *codep & 7;
13120 /* Set vector length. */
13121 if (modrm.mod == 3 && vex.b)
13137 return &bad_opcode;
13150 if (dp->name != NULL)
13153 return get_valid_dis386 (dp, info);
13157 get_sib (disassemble_info *info, int sizeflag)
13159 /* If modrm.mod == 3, operand must be register. */
13161 && ((sizeflag & AFLAG) || address_mode == mode_64bit)
13165 FETCH_DATA (info, codep + 2);
13166 sib.index = (codep [1] >> 3) & 7;
13167 sib.scale = (codep [1] >> 6) & 3;
13168 sib.base = codep [1] & 7;
13173 print_insn (bfd_vma pc, disassemble_info *info)
13175 const struct dis386 *dp;
13177 char *op_txt[MAX_OPERANDS];
13179 int sizeflag, orig_sizeflag;
13181 struct dis_private priv;
13184 priv.orig_sizeflag = AFLAG | DFLAG;
13185 if ((info->mach & bfd_mach_i386_i386) != 0)
13186 address_mode = mode_32bit;
13187 else if (info->mach == bfd_mach_i386_i8086)
13189 address_mode = mode_16bit;
13190 priv.orig_sizeflag = 0;
13193 address_mode = mode_64bit;
13195 if (intel_syntax == (char) -1)
13196 intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0;
13198 for (p = info->disassembler_options; p != NULL; )
13200 if (CONST_STRNEQ (p, "amd64"))
13202 else if (CONST_STRNEQ (p, "intel64"))
13204 else if (CONST_STRNEQ (p, "x86-64"))
13206 address_mode = mode_64bit;
13207 priv.orig_sizeflag = AFLAG | DFLAG;
13209 else if (CONST_STRNEQ (p, "i386"))
13211 address_mode = mode_32bit;
13212 priv.orig_sizeflag = AFLAG | DFLAG;
13214 else if (CONST_STRNEQ (p, "i8086"))
13216 address_mode = mode_16bit;
13217 priv.orig_sizeflag = 0;
13219 else if (CONST_STRNEQ (p, "intel"))
13222 if (CONST_STRNEQ (p + 5, "-mnemonic"))
13223 intel_mnemonic = 1;
13225 else if (CONST_STRNEQ (p, "att"))
13228 if (CONST_STRNEQ (p + 3, "-mnemonic"))
13229 intel_mnemonic = 0;
13231 else if (CONST_STRNEQ (p, "addr"))
13233 if (address_mode == mode_64bit)
13235 if (p[4] == '3' && p[5] == '2')
13236 priv.orig_sizeflag &= ~AFLAG;
13237 else if (p[4] == '6' && p[5] == '4')
13238 priv.orig_sizeflag |= AFLAG;
13242 if (p[4] == '1' && p[5] == '6')
13243 priv.orig_sizeflag &= ~AFLAG;
13244 else if (p[4] == '3' && p[5] == '2')
13245 priv.orig_sizeflag |= AFLAG;
13248 else if (CONST_STRNEQ (p, "data"))
13250 if (p[4] == '1' && p[5] == '6')
13251 priv.orig_sizeflag &= ~DFLAG;
13252 else if (p[4] == '3' && p[5] == '2')
13253 priv.orig_sizeflag |= DFLAG;
13255 else if (CONST_STRNEQ (p, "suffix"))
13256 priv.orig_sizeflag |= SUFFIX_ALWAYS;
13258 p = strchr (p, ',');
13263 if (address_mode == mode_64bit && sizeof (bfd_vma) < 8)
13265 (*info->fprintf_func) (info->stream,
13266 _("64-bit address is disabled"));
13272 names64 = intel_names64;
13273 names32 = intel_names32;
13274 names16 = intel_names16;
13275 names8 = intel_names8;
13276 names8rex = intel_names8rex;
13277 names_seg = intel_names_seg;
13278 names_mm = intel_names_mm;
13279 names_bnd = intel_names_bnd;
13280 names_xmm = intel_names_xmm;
13281 names_ymm = intel_names_ymm;
13282 names_zmm = intel_names_zmm;
13283 index64 = intel_index64;
13284 index32 = intel_index32;
13285 names_mask = intel_names_mask;
13286 index16 = intel_index16;
13289 separator_char = '+';
13294 names64 = att_names64;
13295 names32 = att_names32;
13296 names16 = att_names16;
13297 names8 = att_names8;
13298 names8rex = att_names8rex;
13299 names_seg = att_names_seg;
13300 names_mm = att_names_mm;
13301 names_bnd = att_names_bnd;
13302 names_xmm = att_names_xmm;
13303 names_ymm = att_names_ymm;
13304 names_zmm = att_names_zmm;
13305 index64 = att_index64;
13306 index32 = att_index32;
13307 names_mask = att_names_mask;
13308 index16 = att_index16;
13311 separator_char = ',';
13315 /* The output looks better if we put 7 bytes on a line, since that
13316 puts most long word instructions on a single line. Use 8 bytes
13318 if ((info->mach & bfd_mach_l1om) != 0)
13319 info->bytes_per_line = 8;
13321 info->bytes_per_line = 7;
13323 info->private_data = &priv;
13324 priv.max_fetched = priv.the_buffer;
13325 priv.insn_start = pc;
13328 for (i = 0; i < MAX_OPERANDS; ++i)
13336 start_codep = priv.the_buffer;
13337 codep = priv.the_buffer;
13339 if (OPCODES_SIGSETJMP (priv.bailout) != 0)
13343 /* Getting here means we tried for data but didn't get it. That
13344 means we have an incomplete instruction of some sort. Just
13345 print the first byte as a prefix or a .byte pseudo-op. */
13346 if (codep > priv.the_buffer)
13348 name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag);
13350 (*info->fprintf_func) (info->stream, "%s", name);
13353 /* Just print the first byte as a .byte instruction. */
13354 (*info->fprintf_func) (info->stream, ".byte 0x%x",
13355 (unsigned int) priv.the_buffer[0]);
13365 sizeflag = priv.orig_sizeflag;
13367 if (!ckprefix () || rex_used)
13369 /* Too many prefixes or unused REX prefixes. */
13371 i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i];
13373 (*info->fprintf_func) (info->stream, "%s%s",
13375 prefix_name (all_prefixes[i], sizeflag));
13379 insn_codep = codep;
13381 FETCH_DATA (info, codep + 1);
13382 two_source_ops = (*codep == 0x62) || (*codep == 0xc8);
13384 if (((prefixes & PREFIX_FWAIT)
13385 && ((*codep < 0xd8) || (*codep > 0xdf))))
13387 /* Handle prefixes before fwait. */
13388 for (i = 0; i < fwait_prefix && all_prefixes[i];
13390 (*info->fprintf_func) (info->stream, "%s ",
13391 prefix_name (all_prefixes[i], sizeflag));
13392 (*info->fprintf_func) (info->stream, "fwait");
13396 if (*codep == 0x0f)
13398 unsigned char threebyte;
13401 FETCH_DATA (info, codep + 1);
13402 threebyte = *codep;
13403 dp = &dis386_twobyte[threebyte];
13404 need_modrm = twobyte_has_modrm[*codep];
13409 dp = &dis386[*codep];
13410 need_modrm = onebyte_has_modrm[*codep];
13414 /* Save sizeflag for printing the extra prefixes later before updating
13415 it for mnemonic and operand processing. The prefix names depend
13416 only on the address mode. */
13417 orig_sizeflag = sizeflag;
13418 if (prefixes & PREFIX_ADDR)
13420 if ((prefixes & PREFIX_DATA))
13426 FETCH_DATA (info, codep + 1);
13427 modrm.mod = (*codep >> 6) & 3;
13428 modrm.reg = (*codep >> 3) & 7;
13429 modrm.rm = *codep & 7;
13435 memset (&vex, 0, sizeof (vex));
13437 if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
13439 get_sib (info, sizeflag);
13440 dofloat (sizeflag);
13444 dp = get_valid_dis386 (dp, info);
13445 if (dp != NULL && putop (dp->name, sizeflag) == 0)
13447 get_sib (info, sizeflag);
13448 for (i = 0; i < MAX_OPERANDS; ++i)
13451 op_ad = MAX_OPERANDS - 1 - i;
13453 (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag);
13454 /* For EVEX instruction after the last operand masking
13455 should be printed. */
13456 if (i == 0 && vex.evex)
13458 /* Don't print {%k0}. */
13459 if (vex.mask_register_specifier)
13462 oappend (names_mask[vex.mask_register_specifier]);
13472 /* Check if the REX prefix is used. */
13473 if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
13474 all_prefixes[last_rex_prefix] = 0;
13476 /* Check if the SEG prefix is used. */
13477 if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
13478 | PREFIX_FS | PREFIX_GS)) != 0
13479 && (used_prefixes & active_seg_prefix) != 0)
13480 all_prefixes[last_seg_prefix] = 0;
13482 /* Check if the ADDR prefix is used. */
13483 if ((prefixes & PREFIX_ADDR) != 0
13484 && (used_prefixes & PREFIX_ADDR) != 0)
13485 all_prefixes[last_addr_prefix] = 0;
13487 /* Check if the DATA prefix is used. */
13488 if ((prefixes & PREFIX_DATA) != 0
13489 && (used_prefixes & PREFIX_DATA) != 0)
13490 all_prefixes[last_data_prefix] = 0;
13492 /* Print the extra prefixes. */
13494 for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++)
13495 if (all_prefixes[i])
13498 name = prefix_name (all_prefixes[i], orig_sizeflag);
13501 prefix_length += strlen (name) + 1;
13502 (*info->fprintf_func) (info->stream, "%s ", name);
13505 /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
13506 unused, opcode is invalid. Since the PREFIX_DATA prefix may be
13507 used by putop and MMX/SSE operand and may be overriden by the
13508 PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
13510 if (dp->prefix_requirement == PREFIX_OPCODE
13511 && dp != &bad_opcode
13513 & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
13515 & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
13517 & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
13519 && (used_prefixes & PREFIX_DATA) == 0))))
13521 (*info->fprintf_func) (info->stream, "(bad)");
13522 return end_codep - priv.the_buffer;
13525 /* Check maximum code length. */
13526 if ((codep - start_codep) > MAX_CODE_LENGTH)
13528 (*info->fprintf_func) (info->stream, "(bad)");
13529 return MAX_CODE_LENGTH;
13532 obufp = mnemonicendp;
13533 for (i = strlen (obuf) + prefix_length; i < 6; i++)
13536 (*info->fprintf_func) (info->stream, "%s", obuf);
13538 /* The enter and bound instructions are printed with operands in the same
13539 order as the intel book; everything else is printed in reverse order. */
13540 if (intel_syntax || two_source_ops)
13544 for (i = 0; i < MAX_OPERANDS; ++i)
13545 op_txt[i] = op_out[i];
13547 if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding
13548 && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
13550 op_txt[2] = op_out[3];
13551 op_txt[3] = op_out[2];
13554 for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
13556 op_ad = op_index[i];
13557 op_index[i] = op_index[MAX_OPERANDS - 1 - i];
13558 op_index[MAX_OPERANDS - 1 - i] = op_ad;
13559 riprel = op_riprel[i];
13560 op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i];
13561 op_riprel[MAX_OPERANDS - 1 - i] = riprel;
13566 for (i = 0; i < MAX_OPERANDS; ++i)
13567 op_txt[MAX_OPERANDS - 1 - i] = op_out[i];
13571 for (i = 0; i < MAX_OPERANDS; ++i)
13575 (*info->fprintf_func) (info->stream, ",");
13576 if (op_index[i] != -1 && !op_riprel[i])
13577 (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
13579 (*info->fprintf_func) (info->stream, "%s", op_txt[i]);
13583 for (i = 0; i < MAX_OPERANDS; i++)
13584 if (op_index[i] != -1 && op_riprel[i])
13586 (*info->fprintf_func) (info->stream, " # ");
13587 (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep)
13588 + op_address[op_index[i]]), info);
13591 return codep - priv.the_buffer;
13594 static const char *float_mem[] = {
13669 static const unsigned char float_mem_mode[] = {
13744 #define ST { OP_ST, 0 }
13745 #define STi { OP_STi, 0 }
13747 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
13748 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
13749 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
13750 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
13751 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
13752 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
13753 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
13754 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
13755 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
13757 static const struct dis386 float_reg[][8] = {
13760 { "fadd", { ST, STi }, 0 },
13761 { "fmul", { ST, STi }, 0 },
13762 { "fcom", { STi }, 0 },
13763 { "fcomp", { STi }, 0 },
13764 { "fsub", { ST, STi }, 0 },
13765 { "fsubr", { ST, STi }, 0 },
13766 { "fdiv", { ST, STi }, 0 },
13767 { "fdivr", { ST, STi }, 0 },
13771 { "fld", { STi }, 0 },
13772 { "fxch", { STi }, 0 },
13782 { "fcmovb", { ST, STi }, 0 },
13783 { "fcmove", { ST, STi }, 0 },
13784 { "fcmovbe",{ ST, STi }, 0 },
13785 { "fcmovu", { ST, STi }, 0 },
13793 { "fcmovnb",{ ST, STi }, 0 },
13794 { "fcmovne",{ ST, STi }, 0 },
13795 { "fcmovnbe",{ ST, STi }, 0 },
13796 { "fcmovnu",{ ST, STi }, 0 },
13798 { "fucomi", { ST, STi }, 0 },
13799 { "fcomi", { ST, STi }, 0 },
13804 { "fadd", { STi, ST }, 0 },
13805 { "fmul", { STi, ST }, 0 },
13808 { "fsub{!M|r}", { STi, ST }, 0 },
13809 { "fsub{M|}", { STi, ST }, 0 },
13810 { "fdiv{!M|r}", { STi, ST }, 0 },
13811 { "fdiv{M|}", { STi, ST }, 0 },
13815 { "ffree", { STi }, 0 },
13817 { "fst", { STi }, 0 },
13818 { "fstp", { STi }, 0 },
13819 { "fucom", { STi }, 0 },
13820 { "fucomp", { STi }, 0 },
13826 { "faddp", { STi, ST }, 0 },
13827 { "fmulp", { STi, ST }, 0 },
13830 { "fsub{!M|r}p", { STi, ST }, 0 },
13831 { "fsub{M|}p", { STi, ST }, 0 },
13832 { "fdiv{!M|r}p", { STi, ST }, 0 },
13833 { "fdiv{M|}p", { STi, ST }, 0 },
13837 { "ffreep", { STi }, 0 },
13842 { "fucomip", { ST, STi }, 0 },
13843 { "fcomip", { ST, STi }, 0 },
13848 static char *fgrps[][8] = {
13851 "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13856 "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13861 "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
13866 "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
13871 "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
13876 "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
13881 "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13886 "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
13887 "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
13892 "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13897 "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
13902 swap_operand (void)
13904 mnemonicendp[0] = '.';
13905 mnemonicendp[1] = 's';
13910 OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
13911 int sizeflag ATTRIBUTE_UNUSED)
13913 /* Skip mod/rm byte. */
13919 dofloat (int sizeflag)
13921 const struct dis386 *dp;
13922 unsigned char floatop;
13924 floatop = codep[-1];
13926 if (modrm.mod != 3)
13928 int fp_indx = (floatop - 0xd8) * 8 + modrm.reg;
13930 putop (float_mem[fp_indx], sizeflag);
13933 OP_E (float_mem_mode[fp_indx], sizeflag);
13936 /* Skip mod/rm byte. */
13940 dp = &float_reg[floatop - 0xd8][modrm.reg];
13941 if (dp->name == NULL)
13943 putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag);
13945 /* Instruction fnstsw is only one with strange arg. */
13946 if (floatop == 0xdf && codep[-1] == 0xe0)
13947 strcpy (op_out[0], names16[0]);
13951 putop (dp->name, sizeflag);
13956 (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag);
13961 (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag);
13965 /* Like oappend (below), but S is a string starting with '%'.
13966 In Intel syntax, the '%' is elided. */
13968 oappend_maybe_intel (const char *s)
13970 oappend (s + intel_syntax);
13974 OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13976 oappend_maybe_intel ("%st");
13980 OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
13982 sprintf (scratchbuf, "%%st(%d)", modrm.rm);
13983 oappend_maybe_intel (scratchbuf);
13986 /* Capital letters in template are macros. */
13988 putop (const char *in_template, int sizeflag)
13993 unsigned int l = 0, len = 1;
13996 #define SAVE_LAST(c) \
13997 if (l < len && l < sizeof (last)) \
14002 for (p = in_template; *p; p++)
14018 while (*++p != '|')
14019 if (*p == '}' || *p == '\0')
14022 /* Fall through. */
14027 while (*++p != '}')
14038 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14042 if (l == 0 && len == 1)
14047 if (sizeflag & SUFFIX_ALWAYS)
14060 if (address_mode == mode_64bit
14061 && !(prefixes & PREFIX_ADDR))
14072 if (intel_syntax && !alt)
14074 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14076 if (sizeflag & DFLAG)
14077 *obufp++ = intel_syntax ? 'd' : 'l';
14079 *obufp++ = intel_syntax ? 'w' : 's';
14080 used_prefixes |= (prefixes & PREFIX_DATA);
14084 if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
14087 if (modrm.mod == 3)
14093 if (sizeflag & DFLAG)
14094 *obufp++ = intel_syntax ? 'd' : 'l';
14097 used_prefixes |= (prefixes & PREFIX_DATA);
14103 case 'E': /* For jcxz/jecxz */
14104 if (address_mode == mode_64bit)
14106 if (sizeflag & AFLAG)
14112 if (sizeflag & AFLAG)
14114 used_prefixes |= (prefixes & PREFIX_ADDR);
14119 if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
14121 if (sizeflag & AFLAG)
14122 *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
14124 *obufp++ = address_mode == mode_64bit ? 'l' : 'w';
14125 used_prefixes |= (prefixes & PREFIX_ADDR);
14129 if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS)))
14131 if ((rex & REX_W) || (sizeflag & DFLAG))
14135 if (!(rex & REX_W))
14136 used_prefixes |= (prefixes & PREFIX_DATA);
14141 if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
14142 || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
14144 used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
14147 if (prefixes & PREFIX_DS)
14166 if (l != 0 || len != 1)
14168 if (l != 1 || len != 2 || last[0] != 'X')
14173 if (!need_vex || !vex.evex)
14176 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14178 switch (vex.length)
14196 if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
14201 /* Fall through. */
14204 if (l != 0 || len != 1)
14212 if (sizeflag & SUFFIX_ALWAYS)
14216 if (intel_mnemonic != cond)
14220 if ((prefixes & PREFIX_FWAIT) == 0)
14223 used_prefixes |= PREFIX_FWAIT;
14229 else if (intel_syntax && (sizeflag & DFLAG))
14233 if (!(rex & REX_W))
14234 used_prefixes |= (prefixes & PREFIX_DATA);
14238 && address_mode == mode_64bit
14239 && isa64 == intel64)
14244 /* Fall through. */
14247 && address_mode == mode_64bit
14248 && ((sizeflag & DFLAG) || (rex & REX_W)))
14253 /* Fall through. */
14256 if (l == 0 && len == 1)
14261 if ((rex & REX_W) == 0
14262 && (prefixes & PREFIX_DATA))
14264 if ((sizeflag & DFLAG) == 0)
14266 used_prefixes |= (prefixes & PREFIX_DATA);
14270 if ((prefixes & PREFIX_DATA)
14272 || (sizeflag & SUFFIX_ALWAYS))
14279 if (sizeflag & DFLAG)
14283 used_prefixes |= (prefixes & PREFIX_DATA);
14289 if (l != 1 || len != 2 || last[0] != 'L')
14295 if ((prefixes & PREFIX_DATA)
14297 || (sizeflag & SUFFIX_ALWAYS))
14304 if (sizeflag & DFLAG)
14305 *obufp++ = intel_syntax ? 'd' : 'l';
14308 used_prefixes |= (prefixes & PREFIX_DATA);
14316 if (address_mode == mode_64bit
14317 && ((sizeflag & DFLAG) || (rex & REX_W)))
14319 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14323 /* Fall through. */
14326 if (l == 0 && len == 1)
14329 if (intel_syntax && !alt)
14332 if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
14338 if (sizeflag & DFLAG)
14339 *obufp++ = intel_syntax ? 'd' : 'l';
14342 used_prefixes |= (prefixes & PREFIX_DATA);
14348 if (l != 1 || len != 2 || last[0] != 'L')
14354 || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
14369 else if (sizeflag & DFLAG)
14378 if (intel_syntax && !p[1]
14379 && ((rex & REX_W) || (sizeflag & DFLAG)))
14381 if (!(rex & REX_W))
14382 used_prefixes |= (prefixes & PREFIX_DATA);
14385 if (l == 0 && len == 1)
14389 if (address_mode == mode_64bit
14390 && ((sizeflag & DFLAG) || (rex & REX_W)))
14392 if (sizeflag & SUFFIX_ALWAYS)
14414 /* Fall through. */
14417 if (l == 0 && len == 1)
14422 if (sizeflag & SUFFIX_ALWAYS)
14428 if (sizeflag & DFLAG)
14432 used_prefixes |= (prefixes & PREFIX_DATA);
14446 if (address_mode == mode_64bit
14447 && !(prefixes & PREFIX_ADDR))
14458 if (l != 0 || len != 1)
14463 if (need_vex && vex.prefix)
14465 if (vex.prefix == DATA_PREFIX_OPCODE)
14472 if (prefixes & PREFIX_DATA)
14476 used_prefixes |= (prefixes & PREFIX_DATA);
14480 if (l == 0 && len == 1)
14484 if (l != 1 || len != 2 || last[0] != 'X')
14492 || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
14494 switch (vex.length)
14510 if (l == 0 && len == 1)
14512 /* operand size flag for cwtl, cbtw */
14521 else if (sizeflag & DFLAG)
14525 if (!(rex & REX_W))
14526 used_prefixes |= (prefixes & PREFIX_DATA);
14533 && last[0] != 'L'))
14540 if (last[0] == 'X')
14541 *obufp++ = vex.w ? 'd': 's';
14543 *obufp++ = vex.w ? 'q': 'd';
14549 if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
14551 if (sizeflag & DFLAG)
14555 used_prefixes |= (prefixes & PREFIX_DATA);
14561 if (address_mode == mode_64bit
14562 && (isa64 == intel64
14563 || ((sizeflag & DFLAG) || (rex & REX_W))))
14565 else if ((prefixes & PREFIX_DATA))
14567 if (!(sizeflag & DFLAG))
14569 used_prefixes |= (prefixes & PREFIX_DATA);
14576 mnemonicendp = obufp;
14581 oappend (const char *s)
14583 obufp = stpcpy (obufp, s);
14589 /* Only print the active segment register. */
14590 if (!active_seg_prefix)
14593 used_prefixes |= active_seg_prefix;
14594 switch (active_seg_prefix)
14597 oappend_maybe_intel ("%cs:");
14600 oappend_maybe_intel ("%ds:");
14603 oappend_maybe_intel ("%ss:");
14606 oappend_maybe_intel ("%es:");
14609 oappend_maybe_intel ("%fs:");
14612 oappend_maybe_intel ("%gs:");
14620 OP_indirE (int bytemode, int sizeflag)
14624 OP_E (bytemode, sizeflag);
14628 print_operand_value (char *buf, int hex, bfd_vma disp)
14630 if (address_mode == mode_64bit)
14638 sprintf_vma (tmp, disp);
14639 for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++);
14640 strcpy (buf + 2, tmp + i);
14644 bfd_signed_vma v = disp;
14651 /* Check for possible overflow on 0x8000000000000000. */
14654 strcpy (buf, "9223372036854775808");
14668 tmp[28 - i] = (v % 10) + '0';
14672 strcpy (buf, tmp + 29 - i);
14678 sprintf (buf, "0x%x", (unsigned int) disp);
14680 sprintf (buf, "%d", (int) disp);
14684 /* Put DISP in BUF as signed hex number. */
14687 print_displacement (char *buf, bfd_vma disp)
14689 bfd_signed_vma val = disp;
14698 /* Check for possible overflow. */
14701 switch (address_mode)
14704 strcpy (buf + j, "0x8000000000000000");
14707 strcpy (buf + j, "0x80000000");
14710 strcpy (buf + j, "0x8000");
14720 sprintf_vma (tmp, (bfd_vma) val);
14721 for (i = 0; tmp[i] == '0'; i++)
14723 if (tmp[i] == '\0')
14725 strcpy (buf + j, tmp + i);
14729 intel_operand_size (int bytemode, int sizeflag)
14733 && (bytemode == x_mode
14734 || bytemode == evex_half_bcst_xmmq_mode))
14737 oappend ("QWORD PTR ");
14739 oappend ("DWORD PTR ");
14748 oappend ("BYTE PTR ");
14753 oappend ("WORD PTR ");
14756 if (address_mode == mode_64bit && isa64 == intel64)
14758 oappend ("QWORD PTR ");
14761 /* Fall through. */
14763 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
14765 oappend ("QWORD PTR ");
14768 /* Fall through. */
14774 oappend ("QWORD PTR ");
14777 if ((sizeflag & DFLAG) || bytemode == dq_mode)
14778 oappend ("DWORD PTR ");
14780 oappend ("WORD PTR ");
14781 used_prefixes |= (prefixes & PREFIX_DATA);
14785 if ((rex & REX_W) || (sizeflag & DFLAG))
14787 oappend ("WORD PTR ");
14788 if (!(rex & REX_W))
14789 used_prefixes |= (prefixes & PREFIX_DATA);
14792 if (sizeflag & DFLAG)
14793 oappend ("QWORD PTR ");
14795 oappend ("DWORD PTR ");
14796 used_prefixes |= (prefixes & PREFIX_DATA);
14799 case d_scalar_mode:
14800 case d_scalar_swap_mode:
14803 oappend ("DWORD PTR ");
14806 case q_scalar_mode:
14807 case q_scalar_swap_mode:
14809 oappend ("QWORD PTR ");
14813 if (address_mode == mode_64bit)
14814 oappend ("QWORD PTR ");
14816 oappend ("DWORD PTR ");
14819 if (sizeflag & DFLAG)
14820 oappend ("FWORD PTR ");
14822 oappend ("DWORD PTR ");
14823 used_prefixes |= (prefixes & PREFIX_DATA);
14826 oappend ("TBYTE PTR ");
14830 case evex_x_gscat_mode:
14831 case evex_x_nobcst_mode:
14832 case b_scalar_mode:
14833 case w_scalar_mode:
14836 switch (vex.length)
14839 oappend ("XMMWORD PTR ");
14842 oappend ("YMMWORD PTR ");
14845 oappend ("ZMMWORD PTR ");
14852 oappend ("XMMWORD PTR ");
14855 oappend ("XMMWORD PTR ");
14858 oappend ("YMMWORD PTR ");
14861 case evex_half_bcst_xmmq_mode:
14865 switch (vex.length)
14868 oappend ("QWORD PTR ");
14871 oappend ("XMMWORD PTR ");
14874 oappend ("YMMWORD PTR ");
14884 switch (vex.length)
14889 oappend ("BYTE PTR ");
14899 switch (vex.length)
14904 oappend ("WORD PTR ");
14914 switch (vex.length)
14919 oappend ("DWORD PTR ");
14929 switch (vex.length)
14934 oappend ("QWORD PTR ");
14944 switch (vex.length)
14947 oappend ("WORD PTR ");
14950 oappend ("DWORD PTR ");
14953 oappend ("QWORD PTR ");
14963 switch (vex.length)
14966 oappend ("DWORD PTR ");
14969 oappend ("QWORD PTR ");
14972 oappend ("XMMWORD PTR ");
14982 switch (vex.length)
14985 oappend ("QWORD PTR ");
14988 oappend ("YMMWORD PTR ");
14991 oappend ("ZMMWORD PTR ");
15001 switch (vex.length)
15005 oappend ("XMMWORD PTR ");
15012 oappend ("OWORD PTR ");
15015 case vex_w_dq_mode:
15016 case vex_scalar_w_dq_mode:
15021 oappend ("QWORD PTR ");
15023 oappend ("DWORD PTR ");
15025 case vex_vsib_d_w_dq_mode:
15026 case vex_vsib_q_w_dq_mode:
15033 oappend ("QWORD PTR ");
15035 oappend ("DWORD PTR ");
15039 switch (vex.length)
15042 oappend ("XMMWORD PTR ");
15045 oappend ("YMMWORD PTR ");
15048 oappend ("ZMMWORD PTR ");
15055 case vex_vsib_q_w_d_mode:
15056 case vex_vsib_d_w_d_mode:
15057 if (!need_vex || !vex.evex)
15060 switch (vex.length)
15063 oappend ("QWORD PTR ");
15066 oappend ("XMMWORD PTR ");
15069 oappend ("YMMWORD PTR ");
15077 if (!need_vex || vex.length != 128)
15080 oappend ("DWORD PTR ");
15082 oappend ("BYTE PTR ");
15088 oappend ("QWORD PTR ");
15090 oappend ("WORD PTR ");
15100 OP_E_register (int bytemode, int sizeflag)
15102 int reg = modrm.rm;
15103 const char **names;
15109 if ((sizeflag & SUFFIX_ALWAYS)
15110 && (bytemode == b_swap_mode
15111 || bytemode == bnd_swap_mode
15112 || bytemode == v_swap_mode))
15138 names = address_mode == mode_64bit ? names64 : names32;
15141 case bnd_swap_mode:
15150 if (address_mode == mode_64bit && isa64 == intel64)
15155 /* Fall through. */
15157 if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W)))
15163 /* Fall through. */
15176 if ((sizeflag & DFLAG)
15177 || (bytemode != v_mode
15178 && bytemode != v_swap_mode))
15182 used_prefixes |= (prefixes & PREFIX_DATA);
15186 names = (address_mode == mode_64bit
15187 ? names64 : names32);
15188 if (!(prefixes & PREFIX_ADDR))
15189 names = (address_mode == mode_16bit
15190 ? names16 : names);
15193 /* Remove "addr16/addr32". */
15194 all_prefixes[last_addr_prefix] = 0;
15195 names = (address_mode != mode_32bit
15196 ? names32 : names16);
15197 used_prefixes |= PREFIX_ADDR;
15207 names = names_mask;
15212 oappend (INTERNAL_DISASSEMBLER_ERROR);
15215 oappend (names[reg]);
15219 OP_E_memory (int bytemode, int sizeflag)
15222 int add = (rex & REX_B) ? 8 : 0;
15228 /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */
15230 && bytemode != x_mode
15231 && bytemode != xmmq_mode
15232 && bytemode != evex_half_bcst_xmmq_mode)
15247 case vex_vsib_d_w_dq_mode:
15248 case vex_vsib_d_w_d_mode:
15249 case vex_vsib_q_w_dq_mode:
15250 case vex_vsib_q_w_d_mode:
15251 case evex_x_gscat_mode:
15253 shift = vex.w ? 3 : 2;
15256 case evex_half_bcst_xmmq_mode:
15260 shift = vex.w ? 3 : 2;
15263 /* Fall through. */
15267 case evex_x_nobcst_mode:
15269 switch (vex.length)
15292 case q_scalar_mode:
15294 case q_scalar_swap_mode:
15300 case d_scalar_mode:
15302 case d_scalar_swap_mode:
15305 case w_scalar_mode:
15309 case b_scalar_mode:
15314 shift = address_mode == mode_64bit ? 3 : 2;
15319 /* Make necessary corrections to shift for modes that need it.
15320 For these modes we currently have shift 4, 5 or 6 depending on
15321 vex.length (it corresponds to xmmword, ymmword or zmmword
15322 operand). We might want to make it 3, 4 or 5 (e.g. for
15323 xmmq_mode). In case of broadcast enabled the corrections
15324 aren't needed, as element size is always 32 or 64 bits. */
15326 && (bytemode == xmmq_mode
15327 || bytemode == evex_half_bcst_xmmq_mode))
15329 else if (bytemode == xmmqd_mode)
15331 else if (bytemode == xmmdw_mode)
15333 else if (bytemode == ymmq_mode && vex.length == 128)
15341 intel_operand_size (bytemode, sizeflag);
15344 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
15346 /* 32/64 bit address mode */
15356 int addr32flag = !((sizeflag & AFLAG)
15357 || bytemode == v_bnd_mode
15358 || bytemode == v_bndmk_mode
15359 || bytemode == bnd_mode
15360 || bytemode == bnd_swap_mode);
15361 const char **indexes64 = names64;
15362 const char **indexes32 = names32;
15372 vindex = sib.index;
15378 case vex_vsib_d_w_dq_mode:
15379 case vex_vsib_d_w_d_mode:
15380 case vex_vsib_q_w_dq_mode:
15381 case vex_vsib_q_w_d_mode:
15391 switch (vex.length)
15394 indexes64 = indexes32 = names_xmm;
15398 || bytemode == vex_vsib_q_w_dq_mode
15399 || bytemode == vex_vsib_q_w_d_mode)
15400 indexes64 = indexes32 = names_ymm;
15402 indexes64 = indexes32 = names_xmm;
15406 || bytemode == vex_vsib_q_w_dq_mode
15407 || bytemode == vex_vsib_q_w_d_mode)
15408 indexes64 = indexes32 = names_zmm;
15410 indexes64 = indexes32 = names_ymm;
15417 haveindex = vindex != 4;
15424 rbase = base + add;
15432 if (address_mode == mode_64bit && !havesib)
15435 if (riprel && bytemode == v_bndmk_mode)
15443 FETCH_DATA (the_info, codep + 1);
15445 if ((disp & 0x80) != 0)
15447 if (vex.evex && shift > 0)
15460 && address_mode != mode_16bit)
15462 if (address_mode == mode_64bit)
15464 /* Display eiz instead of addr32. */
15465 needindex = addr32flag;
15470 /* In 32-bit mode, we need index register to tell [offset]
15471 from [eiz*1 + offset]. */
15476 havedisp = (havebase
15478 || (havesib && (haveindex || scale != 0)));
15481 if (modrm.mod != 0 || base == 5)
15483 if (havedisp || riprel)
15484 print_displacement (scratchbuf, disp);
15486 print_operand_value (scratchbuf, 1, disp);
15487 oappend (scratchbuf);
15491 oappend (!addr32flag ? "(%rip)" : "(%eip)");
15495 if ((havebase || haveindex || needaddr32 || riprel)
15496 && (bytemode != v_bnd_mode)
15497 && (bytemode != v_bndmk_mode)
15498 && (bytemode != bnd_mode)
15499 && (bytemode != bnd_swap_mode))
15500 used_prefixes |= PREFIX_ADDR;
15502 if (havedisp || (intel_syntax && riprel))
15504 *obufp++ = open_char;
15505 if (intel_syntax && riprel)
15508 oappend (!addr32flag ? "rip" : "eip");
15512 oappend (address_mode == mode_64bit && !addr32flag
15513 ? names64[rbase] : names32[rbase]);
15516 /* ESP/RSP won't allow index. If base isn't ESP/RSP,
15517 print index to tell base + index from base. */
15521 || (havebase && base != ESP_REG_NUM))
15523 if (!intel_syntax || havebase)
15525 *obufp++ = separator_char;
15529 oappend (address_mode == mode_64bit && !addr32flag
15530 ? indexes64[vindex] : indexes32[vindex]);
15532 oappend (address_mode == mode_64bit && !addr32flag
15533 ? index64 : index32);
15535 *obufp++ = scale_char;
15537 sprintf (scratchbuf, "%d", 1 << scale);
15538 oappend (scratchbuf);
15542 && (disp || modrm.mod != 0 || base == 5))
15544 if (!havedisp || (bfd_signed_vma) disp >= 0)
15549 else if (modrm.mod != 1 && disp != -disp)
15553 disp = - (bfd_signed_vma) disp;
15557 print_displacement (scratchbuf, disp);
15559 print_operand_value (scratchbuf, 1, disp);
15560 oappend (scratchbuf);
15563 *obufp++ = close_char;
15566 else if (intel_syntax)
15568 if (modrm.mod != 0 || base == 5)
15570 if (!active_seg_prefix)
15572 oappend (names_seg[ds_reg - es_reg]);
15575 print_operand_value (scratchbuf, 1, disp);
15576 oappend (scratchbuf);
15582 /* 16 bit address mode */
15583 used_prefixes |= prefixes & PREFIX_ADDR;
15590 if ((disp & 0x8000) != 0)
15595 FETCH_DATA (the_info, codep + 1);
15597 if ((disp & 0x80) != 0)
15599 if (vex.evex && shift > 0)
15604 if ((disp & 0x8000) != 0)
15610 if (modrm.mod != 0 || modrm.rm == 6)
15612 print_displacement (scratchbuf, disp);
15613 oappend (scratchbuf);
15616 if (modrm.mod != 0 || modrm.rm != 6)
15618 *obufp++ = open_char;
15620 oappend (index16[modrm.rm]);
15622 && (disp || modrm.mod != 0 || modrm.rm == 6))
15624 if ((bfd_signed_vma) disp >= 0)
15629 else if (modrm.mod != 1)
15633 disp = - (bfd_signed_vma) disp;
15636 print_displacement (scratchbuf, disp);
15637 oappend (scratchbuf);
15640 *obufp++ = close_char;
15643 else if (intel_syntax)
15645 if (!active_seg_prefix)
15647 oappend (names_seg[ds_reg - es_reg]);
15650 print_operand_value (scratchbuf, 1, disp & 0xffff);
15651 oappend (scratchbuf);
15654 if (vex.evex && vex.b
15655 && (bytemode == x_mode
15656 || bytemode == xmmq_mode
15657 || bytemode == evex_half_bcst_xmmq_mode))
15660 || bytemode == xmmq_mode
15661 || bytemode == evex_half_bcst_xmmq_mode)
15663 switch (vex.length)
15666 oappend ("{1to2}");
15669 oappend ("{1to4}");
15672 oappend ("{1to8}");
15680 switch (vex.length)
15683 oappend ("{1to4}");
15686 oappend ("{1to8}");
15689 oappend ("{1to16}");
15699 OP_E (int bytemode, int sizeflag)
15701 /* Skip mod/rm byte. */
15705 if (modrm.mod == 3)
15706 OP_E_register (bytemode, sizeflag);
15708 OP_E_memory (bytemode, sizeflag);
15712 OP_G (int bytemode, int sizeflag)
15715 const char **names;
15724 oappend (names8rex[modrm.reg + add]);
15726 oappend (names8[modrm.reg + add]);
15729 oappend (names16[modrm.reg + add]);
15734 oappend (names32[modrm.reg + add]);
15737 oappend (names64[modrm.reg + add]);
15740 if (modrm.reg > 0x3)
15745 oappend (names_bnd[modrm.reg]);
15754 oappend (names64[modrm.reg + add]);
15757 if ((sizeflag & DFLAG) || bytemode != v_mode)
15758 oappend (names32[modrm.reg + add]);
15760 oappend (names16[modrm.reg + add]);
15761 used_prefixes |= (prefixes & PREFIX_DATA);
15765 names = (address_mode == mode_64bit
15766 ? names64 : names32);
15767 if (!(prefixes & PREFIX_ADDR))
15769 if (address_mode == mode_16bit)
15774 /* Remove "addr16/addr32". */
15775 all_prefixes[last_addr_prefix] = 0;
15776 names = (address_mode != mode_32bit
15777 ? names32 : names16);
15778 used_prefixes |= PREFIX_ADDR;
15780 oappend (names[modrm.reg + add]);
15783 if (address_mode == mode_64bit)
15784 oappend (names64[modrm.reg + add]);
15786 oappend (names32[modrm.reg + add]);
15790 if ((modrm.reg + add) > 0x7)
15795 oappend (names_mask[modrm.reg + add]);
15798 oappend (INTERNAL_DISASSEMBLER_ERROR);
15811 FETCH_DATA (the_info, codep + 8);
15812 a = *codep++ & 0xff;
15813 a |= (*codep++ & 0xff) << 8;
15814 a |= (*codep++ & 0xff) << 16;
15815 a |= (*codep++ & 0xffu) << 24;
15816 b = *codep++ & 0xff;
15817 b |= (*codep++ & 0xff) << 8;
15818 b |= (*codep++ & 0xff) << 16;
15819 b |= (*codep++ & 0xffu) << 24;
15820 x = a + ((bfd_vma) b << 32);
15828 static bfd_signed_vma
15831 bfd_signed_vma x = 0;
15833 FETCH_DATA (the_info, codep + 4);
15834 x = *codep++ & (bfd_signed_vma) 0xff;
15835 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15836 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15837 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15841 static bfd_signed_vma
15844 bfd_signed_vma x = 0;
15846 FETCH_DATA (the_info, codep + 4);
15847 x = *codep++ & (bfd_signed_vma) 0xff;
15848 x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
15849 x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
15850 x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
15852 x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
15862 FETCH_DATA (the_info, codep + 2);
15863 x = *codep++ & 0xff;
15864 x |= (*codep++ & 0xff) << 8;
15869 set_op (bfd_vma op, int riprel)
15871 op_index[op_ad] = op_ad;
15872 if (address_mode == mode_64bit)
15874 op_address[op_ad] = op;
15875 op_riprel[op_ad] = riprel;
15879 /* Mask to get a 32-bit address. */
15880 op_address[op_ad] = op & 0xffffffff;
15881 op_riprel[op_ad] = riprel & 0xffffffff;
15886 OP_REG (int code, int sizeflag)
15893 case es_reg: case ss_reg: case cs_reg:
15894 case ds_reg: case fs_reg: case gs_reg:
15895 oappend (names_seg[code - es_reg]);
15907 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15908 case sp_reg: case bp_reg: case si_reg: case di_reg:
15909 s = names16[code - ax_reg + add];
15911 case al_reg: case ah_reg: case cl_reg: case ch_reg:
15912 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15915 s = names8rex[code - al_reg + add];
15917 s = names8[code - al_reg];
15919 case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
15920 case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
15921 if (address_mode == mode_64bit
15922 && ((sizeflag & DFLAG) || (rex & REX_W)))
15924 s = names64[code - rAX_reg + add];
15927 code += eAX_reg - rAX_reg;
15928 /* Fall through. */
15929 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15930 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15933 s = names64[code - eAX_reg + add];
15936 if (sizeflag & DFLAG)
15937 s = names32[code - eAX_reg + add];
15939 s = names16[code - eAX_reg + add];
15940 used_prefixes |= (prefixes & PREFIX_DATA);
15944 s = INTERNAL_DISASSEMBLER_ERROR;
15951 OP_IMREG (int code, int sizeflag)
15963 case ax_reg: case cx_reg: case dx_reg: case bx_reg:
15964 case sp_reg: case bp_reg: case si_reg: case di_reg:
15965 s = names16[code - ax_reg];
15967 case es_reg: case ss_reg: case cs_reg:
15968 case ds_reg: case fs_reg: case gs_reg:
15969 s = names_seg[code - es_reg];
15971 case al_reg: case ah_reg: case cl_reg: case ch_reg:
15972 case dl_reg: case dh_reg: case bl_reg: case bh_reg:
15975 s = names8rex[code - al_reg];
15977 s = names8[code - al_reg];
15979 case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
15980 case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
15983 s = names64[code - eAX_reg];
15986 if (sizeflag & DFLAG)
15987 s = names32[code - eAX_reg];
15989 s = names16[code - eAX_reg];
15990 used_prefixes |= (prefixes & PREFIX_DATA);
15993 case z_mode_ax_reg:
15994 if ((rex & REX_W) || (sizeflag & DFLAG))
15998 if (!(rex & REX_W))
15999 used_prefixes |= (prefixes & PREFIX_DATA);
16002 s = INTERNAL_DISASSEMBLER_ERROR;
16009 OP_I (int bytemode, int sizeflag)
16012 bfd_signed_vma mask = -1;
16017 FETCH_DATA (the_info, codep + 1);
16022 if (address_mode == mode_64bit)
16027 /* Fall through. */
16034 if (sizeflag & DFLAG)
16044 used_prefixes |= (prefixes & PREFIX_DATA);
16056 oappend (INTERNAL_DISASSEMBLER_ERROR);
16061 scratchbuf[0] = '$';
16062 print_operand_value (scratchbuf + 1, 1, op);
16063 oappend_maybe_intel (scratchbuf);
16064 scratchbuf[0] = '\0';
16068 OP_I64 (int bytemode, int sizeflag)
16071 bfd_signed_vma mask = -1;
16073 if (address_mode != mode_64bit)
16075 OP_I (bytemode, sizeflag);
16082 FETCH_DATA (the_info, codep + 1);
16092 if (sizeflag & DFLAG)
16102 used_prefixes |= (prefixes & PREFIX_DATA);
16110 oappend (INTERNAL_DISASSEMBLER_ERROR);
16115 scratchbuf[0] = '$';
16116 print_operand_value (scratchbuf + 1, 1, op);
16117 oappend_maybe_intel (scratchbuf);
16118 scratchbuf[0] = '\0';
16122 OP_sI (int bytemode, int sizeflag)
16130 FETCH_DATA (the_info, codep + 1);
16132 if ((op & 0x80) != 0)
16134 if (bytemode == b_T_mode)
16136 if (address_mode != mode_64bit
16137 || !((sizeflag & DFLAG) || (rex & REX_W)))
16139 /* The operand-size prefix is overridden by a REX prefix. */
16140 if ((sizeflag & DFLAG) || (rex & REX_W))
16148 if (!(rex & REX_W))
16150 if (sizeflag & DFLAG)
16158 /* The operand-size prefix is overridden by a REX prefix. */
16159 if ((sizeflag & DFLAG) || (rex & REX_W))
16165 oappend (INTERNAL_DISASSEMBLER_ERROR);
16169 scratchbuf[0] = '$';
16170 print_operand_value (scratchbuf + 1, 1, op);
16171 oappend_maybe_intel (scratchbuf);
16175 OP_J (int bytemode, int sizeflag)
16179 bfd_vma segment = 0;
16184 FETCH_DATA (the_info, codep + 1);
16186 if ((disp & 0x80) != 0)
16190 if (isa64 == amd64)
16192 if ((sizeflag & DFLAG)
16193 || (address_mode == mode_64bit
16194 && (isa64 != amd64 || (rex & REX_W))))
16199 if ((disp & 0x8000) != 0)
16201 /* In 16bit mode, address is wrapped around at 64k within
16202 the same segment. Otherwise, a data16 prefix on a jump
16203 instruction means that the pc is masked to 16 bits after
16204 the displacement is added! */
16206 if ((prefixes & PREFIX_DATA) == 0)
16207 segment = ((start_pc + (codep - start_codep))
16208 & ~((bfd_vma) 0xffff));
16210 if (address_mode != mode_64bit
16211 || (isa64 == amd64 && !(rex & REX_W)))
16212 used_prefixes |= (prefixes & PREFIX_DATA);
16215 oappend (INTERNAL_DISASSEMBLER_ERROR);
16218 disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment;
16220 print_operand_value (scratchbuf, 1, disp);
16221 oappend (scratchbuf);
16225 OP_SEG (int bytemode, int sizeflag)
16227 if (bytemode == w_mode)
16228 oappend (names_seg[modrm.reg]);
16230 OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag);
16234 OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag)
16238 if (sizeflag & DFLAG)
16248 used_prefixes |= (prefixes & PREFIX_DATA);
16250 sprintf (scratchbuf, "0x%x:0x%x", seg, offset);
16252 sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset);
16253 oappend (scratchbuf);
16257 OP_OFF (int bytemode, int sizeflag)
16261 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16262 intel_operand_size (bytemode, sizeflag);
16265 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
16272 if (!active_seg_prefix)
16274 oappend (names_seg[ds_reg - es_reg]);
16278 print_operand_value (scratchbuf, 1, off);
16279 oappend (scratchbuf);
16283 OP_OFF64 (int bytemode, int sizeflag)
16287 if (address_mode != mode_64bit
16288 || (prefixes & PREFIX_ADDR))
16290 OP_OFF (bytemode, sizeflag);
16294 if (intel_syntax && (sizeflag & SUFFIX_ALWAYS))
16295 intel_operand_size (bytemode, sizeflag);
16302 if (!active_seg_prefix)
16304 oappend (names_seg[ds_reg - es_reg]);
16308 print_operand_value (scratchbuf, 1, off);
16309 oappend (scratchbuf);
16313 ptr_reg (int code, int sizeflag)
16317 *obufp++ = open_char;
16318 used_prefixes |= (prefixes & PREFIX_ADDR);
16319 if (address_mode == mode_64bit)
16321 if (!(sizeflag & AFLAG))
16322 s = names32[code - eAX_reg];
16324 s = names64[code - eAX_reg];
16326 else if (sizeflag & AFLAG)
16327 s = names32[code - eAX_reg];
16329 s = names16[code - eAX_reg];
16331 *obufp++ = close_char;
16336 OP_ESreg (int code, int sizeflag)
16342 case 0x6d: /* insw/insl */
16343 intel_operand_size (z_mode, sizeflag);
16345 case 0xa5: /* movsw/movsl/movsq */
16346 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16347 case 0xab: /* stosw/stosl */
16348 case 0xaf: /* scasw/scasl */
16349 intel_operand_size (v_mode, sizeflag);
16352 intel_operand_size (b_mode, sizeflag);
16355 oappend_maybe_intel ("%es:");
16356 ptr_reg (code, sizeflag);
16360 OP_DSreg (int code, int sizeflag)
16366 case 0x6f: /* outsw/outsl */
16367 intel_operand_size (z_mode, sizeflag);
16369 case 0xa5: /* movsw/movsl/movsq */
16370 case 0xa7: /* cmpsw/cmpsl/cmpsq */
16371 case 0xad: /* lodsw/lodsl/lodsq */
16372 intel_operand_size (v_mode, sizeflag);
16375 intel_operand_size (b_mode, sizeflag);
16378 /* Set active_seg_prefix to PREFIX_DS if it is unset so that the
16379 default segment register DS is printed. */
16380 if (!active_seg_prefix)
16381 active_seg_prefix = PREFIX_DS;
16383 ptr_reg (code, sizeflag);
16387 OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16395 else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK))
16397 all_prefixes[last_lock_prefix] = 0;
16398 used_prefixes |= PREFIX_LOCK;
16403 sprintf (scratchbuf, "%%cr%d", modrm.reg + add);
16404 oappend_maybe_intel (scratchbuf);
16408 OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16417 sprintf (scratchbuf, "db%d", modrm.reg + add);
16419 sprintf (scratchbuf, "%%db%d", modrm.reg + add);
16420 oappend (scratchbuf);
16424 OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16426 sprintf (scratchbuf, "%%tr%d", modrm.reg);
16427 oappend_maybe_intel (scratchbuf);
16431 OP_R (int bytemode, int sizeflag)
16433 /* Skip mod/rm byte. */
16436 OP_E_register (bytemode, sizeflag);
16440 OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16442 int reg = modrm.reg;
16443 const char **names;
16445 used_prefixes |= (prefixes & PREFIX_DATA);
16446 if (prefixes & PREFIX_DATA)
16455 oappend (names[reg]);
16459 OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
16461 int reg = modrm.reg;
16462 const char **names;
16474 && bytemode != xmm_mode
16475 && bytemode != xmmq_mode
16476 && bytemode != evex_half_bcst_xmmq_mode
16477 && bytemode != ymm_mode
16478 && bytemode != scalar_mode)
16480 switch (vex.length)
16487 || (bytemode != vex_vsib_q_w_dq_mode
16488 && bytemode != vex_vsib_q_w_d_mode))
16500 else if (bytemode == xmmq_mode
16501 || bytemode == evex_half_bcst_xmmq_mode)
16503 switch (vex.length)
16516 else if (bytemode == ymm_mode)
16520 oappend (names[reg]);
16524 OP_EM (int bytemode, int sizeflag)
16527 const char **names;
16529 if (modrm.mod != 3)
16532 && (bytemode == v_mode || bytemode == v_swap_mode))
16534 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16535 used_prefixes |= (prefixes & PREFIX_DATA);
16537 OP_E (bytemode, sizeflag);
16541 if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
16544 /* Skip mod/rm byte. */
16547 used_prefixes |= (prefixes & PREFIX_DATA);
16549 if (prefixes & PREFIX_DATA)
16558 oappend (names[reg]);
16561 /* cvt* are the only instructions in sse2 which have
16562 both SSE and MMX operands and also have 0x66 prefix
16563 in their opcode. 0x66 was originally used to differentiate
16564 between SSE and MMX instruction(operands). So we have to handle the
16565 cvt* separately using OP_EMC and OP_MXC */
16567 OP_EMC (int bytemode, int sizeflag)
16569 if (modrm.mod != 3)
16571 if (intel_syntax && bytemode == v_mode)
16573 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
16574 used_prefixes |= (prefixes & PREFIX_DATA);
16576 OP_E (bytemode, sizeflag);
16580 /* Skip mod/rm byte. */
16583 used_prefixes |= (prefixes & PREFIX_DATA);
16584 oappend (names_mm[modrm.rm]);
16588 OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16590 used_prefixes |= (prefixes & PREFIX_DATA);
16591 oappend (names_mm[modrm.reg]);
16595 OP_EX (int bytemode, int sizeflag)
16598 const char **names;
16600 /* Skip mod/rm byte. */
16604 if (modrm.mod != 3)
16606 OP_E_memory (bytemode, sizeflag);
16621 if ((sizeflag & SUFFIX_ALWAYS)
16622 && (bytemode == x_swap_mode
16623 || bytemode == d_swap_mode
16624 || bytemode == d_scalar_swap_mode
16625 || bytemode == q_swap_mode
16626 || bytemode == q_scalar_swap_mode))
16630 && bytemode != xmm_mode
16631 && bytemode != xmmdw_mode
16632 && bytemode != xmmqd_mode
16633 && bytemode != xmm_mb_mode
16634 && bytemode != xmm_mw_mode
16635 && bytemode != xmm_md_mode
16636 && bytemode != xmm_mq_mode
16637 && bytemode != xmm_mdq_mode
16638 && bytemode != xmmq_mode
16639 && bytemode != evex_half_bcst_xmmq_mode
16640 && bytemode != ymm_mode
16641 && bytemode != d_scalar_mode
16642 && bytemode != d_scalar_swap_mode
16643 && bytemode != q_scalar_mode
16644 && bytemode != q_scalar_swap_mode
16645 && bytemode != vex_scalar_w_dq_mode)
16647 switch (vex.length)
16662 else if (bytemode == xmmq_mode
16663 || bytemode == evex_half_bcst_xmmq_mode)
16665 switch (vex.length)
16678 else if (bytemode == ymm_mode)
16682 oappend (names[reg]);
16686 OP_MS (int bytemode, int sizeflag)
16688 if (modrm.mod == 3)
16689 OP_EM (bytemode, sizeflag);
16695 OP_XS (int bytemode, int sizeflag)
16697 if (modrm.mod == 3)
16698 OP_EX (bytemode, sizeflag);
16704 OP_M (int bytemode, int sizeflag)
16706 if (modrm.mod == 3)
16707 /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
16710 OP_E (bytemode, sizeflag);
16714 OP_0f07 (int bytemode, int sizeflag)
16716 if (modrm.mod != 3 || modrm.rm != 0)
16719 OP_E (bytemode, sizeflag);
16722 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
16723 32bit mode and "xchg %rax,%rax" in 64bit mode. */
16726 NOP_Fixup1 (int bytemode, int sizeflag)
16728 if ((prefixes & PREFIX_DATA) != 0
16731 && address_mode == mode_64bit))
16732 OP_REG (bytemode, sizeflag);
16734 strcpy (obuf, "nop");
16738 NOP_Fixup2 (int bytemode, int sizeflag)
16740 if ((prefixes & PREFIX_DATA) != 0
16743 && address_mode == mode_64bit))
16744 OP_IMREG (bytemode, sizeflag);
16747 static const char *const Suffix3DNow[] = {
16748 /* 00 */ NULL, NULL, NULL, NULL,
16749 /* 04 */ NULL, NULL, NULL, NULL,
16750 /* 08 */ NULL, NULL, NULL, NULL,
16751 /* 0C */ "pi2fw", "pi2fd", NULL, NULL,
16752 /* 10 */ NULL, NULL, NULL, NULL,
16753 /* 14 */ NULL, NULL, NULL, NULL,
16754 /* 18 */ NULL, NULL, NULL, NULL,
16755 /* 1C */ "pf2iw", "pf2id", NULL, NULL,
16756 /* 20 */ NULL, NULL, NULL, NULL,
16757 /* 24 */ NULL, NULL, NULL, NULL,
16758 /* 28 */ NULL, NULL, NULL, NULL,
16759 /* 2C */ NULL, NULL, NULL, NULL,
16760 /* 30 */ NULL, NULL, NULL, NULL,
16761 /* 34 */ NULL, NULL, NULL, NULL,
16762 /* 38 */ NULL, NULL, NULL, NULL,
16763 /* 3C */ NULL, NULL, NULL, NULL,
16764 /* 40 */ NULL, NULL, NULL, NULL,
16765 /* 44 */ NULL, NULL, NULL, NULL,
16766 /* 48 */ NULL, NULL, NULL, NULL,
16767 /* 4C */ NULL, NULL, NULL, NULL,
16768 /* 50 */ NULL, NULL, NULL, NULL,
16769 /* 54 */ NULL, NULL, NULL, NULL,
16770 /* 58 */ NULL, NULL, NULL, NULL,
16771 /* 5C */ NULL, NULL, NULL, NULL,
16772 /* 60 */ NULL, NULL, NULL, NULL,
16773 /* 64 */ NULL, NULL, NULL, NULL,
16774 /* 68 */ NULL, NULL, NULL, NULL,
16775 /* 6C */ NULL, NULL, NULL, NULL,
16776 /* 70 */ NULL, NULL, NULL, NULL,
16777 /* 74 */ NULL, NULL, NULL, NULL,
16778 /* 78 */ NULL, NULL, NULL, NULL,
16779 /* 7C */ NULL, NULL, NULL, NULL,
16780 /* 80 */ NULL, NULL, NULL, NULL,
16781 /* 84 */ NULL, NULL, NULL, NULL,
16782 /* 88 */ NULL, NULL, "pfnacc", NULL,
16783 /* 8C */ NULL, NULL, "pfpnacc", NULL,
16784 /* 90 */ "pfcmpge", NULL, NULL, NULL,
16785 /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt",
16786 /* 98 */ NULL, NULL, "pfsub", NULL,
16787 /* 9C */ NULL, NULL, "pfadd", NULL,
16788 /* A0 */ "pfcmpgt", NULL, NULL, NULL,
16789 /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1",
16790 /* A8 */ NULL, NULL, "pfsubr", NULL,
16791 /* AC */ NULL, NULL, "pfacc", NULL,
16792 /* B0 */ "pfcmpeq", NULL, NULL, NULL,
16793 /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw",
16794 /* B8 */ NULL, NULL, NULL, "pswapd",
16795 /* BC */ NULL, NULL, NULL, "pavgusb",
16796 /* C0 */ NULL, NULL, NULL, NULL,
16797 /* C4 */ NULL, NULL, NULL, NULL,
16798 /* C8 */ NULL, NULL, NULL, NULL,
16799 /* CC */ NULL, NULL, NULL, NULL,
16800 /* D0 */ NULL, NULL, NULL, NULL,
16801 /* D4 */ NULL, NULL, NULL, NULL,
16802 /* D8 */ NULL, NULL, NULL, NULL,
16803 /* DC */ NULL, NULL, NULL, NULL,
16804 /* E0 */ NULL, NULL, NULL, NULL,
16805 /* E4 */ NULL, NULL, NULL, NULL,
16806 /* E8 */ NULL, NULL, NULL, NULL,
16807 /* EC */ NULL, NULL, NULL, NULL,
16808 /* F0 */ NULL, NULL, NULL, NULL,
16809 /* F4 */ NULL, NULL, NULL, NULL,
16810 /* F8 */ NULL, NULL, NULL, NULL,
16811 /* FC */ NULL, NULL, NULL, NULL,
16815 OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16817 const char *mnemonic;
16819 FETCH_DATA (the_info, codep + 1);
16820 /* AMD 3DNow! instructions are specified by an opcode suffix in the
16821 place where an 8-bit immediate would normally go. ie. the last
16822 byte of the instruction. */
16823 obufp = mnemonicendp;
16824 mnemonic = Suffix3DNow[*codep++ & 0xff];
16826 oappend (mnemonic);
16829 /* Since a variable sized modrm/sib chunk is between the start
16830 of the opcode (0x0f0f) and the opcode suffix, we need to do
16831 all the modrm processing first, and don't know until now that
16832 we have a bad opcode. This necessitates some cleaning up. */
16833 op_out[0][0] = '\0';
16834 op_out[1][0] = '\0';
16837 mnemonicendp = obufp;
16840 static struct op simd_cmp_op[] =
16842 { STRING_COMMA_LEN ("eq") },
16843 { STRING_COMMA_LEN ("lt") },
16844 { STRING_COMMA_LEN ("le") },
16845 { STRING_COMMA_LEN ("unord") },
16846 { STRING_COMMA_LEN ("neq") },
16847 { STRING_COMMA_LEN ("nlt") },
16848 { STRING_COMMA_LEN ("nle") },
16849 { STRING_COMMA_LEN ("ord") }
16853 CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16855 unsigned int cmp_type;
16857 FETCH_DATA (the_info, codep + 1);
16858 cmp_type = *codep++ & 0xff;
16859 if (cmp_type < ARRAY_SIZE (simd_cmp_op))
16862 char *p = mnemonicendp - 2;
16866 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
16867 mnemonicendp += simd_cmp_op[cmp_type].len;
16871 /* We have a reserved extension byte. Output it directly. */
16872 scratchbuf[0] = '$';
16873 print_operand_value (scratchbuf + 1, 1, cmp_type);
16874 oappend_maybe_intel (scratchbuf);
16875 scratchbuf[0] = '\0';
16880 OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
16881 int sizeflag ATTRIBUTE_UNUSED)
16883 /* mwaitx %eax,%ecx,%ebx */
16886 const char **names = (address_mode == mode_64bit
16887 ? names64 : names32);
16888 strcpy (op_out[0], names[0]);
16889 strcpy (op_out[1], names[1]);
16890 strcpy (op_out[2], names[3]);
16891 two_source_ops = 1;
16893 /* Skip mod/rm byte. */
16899 OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
16900 int sizeflag ATTRIBUTE_UNUSED)
16902 /* mwait %eax,%ecx */
16905 const char **names = (address_mode == mode_64bit
16906 ? names64 : names32);
16907 strcpy (op_out[0], names[0]);
16908 strcpy (op_out[1], names[1]);
16909 two_source_ops = 1;
16911 /* Skip mod/rm byte. */
16917 OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
16918 int sizeflag ATTRIBUTE_UNUSED)
16920 /* monitor %eax,%ecx,%edx" */
16923 const char **op1_names;
16924 const char **names = (address_mode == mode_64bit
16925 ? names64 : names32);
16927 if (!(prefixes & PREFIX_ADDR))
16928 op1_names = (address_mode == mode_16bit
16929 ? names16 : names);
16932 /* Remove "addr16/addr32". */
16933 all_prefixes[last_addr_prefix] = 0;
16934 op1_names = (address_mode != mode_32bit
16935 ? names32 : names16);
16936 used_prefixes |= PREFIX_ADDR;
16938 strcpy (op_out[0], op1_names[0]);
16939 strcpy (op_out[1], names[1]);
16940 strcpy (op_out[2], names[2]);
16941 two_source_ops = 1;
16943 /* Skip mod/rm byte. */
16951 /* Throw away prefixes and 1st. opcode byte. */
16952 codep = insn_codep + 1;
16957 REP_Fixup (int bytemode, int sizeflag)
16959 /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
16961 if (prefixes & PREFIX_REPZ)
16962 all_prefixes[last_repz_prefix] = REP_PREFIX;
16969 OP_IMREG (bytemode, sizeflag);
16972 OP_ESreg (bytemode, sizeflag);
16975 OP_DSreg (bytemode, sizeflag);
16983 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
16987 BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
16989 if (prefixes & PREFIX_REPNZ)
16990 all_prefixes[last_repnz_prefix] = BND_PREFIX;
16993 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
16997 NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
16998 int sizeflag ATTRIBUTE_UNUSED)
17000 if (active_seg_prefix == PREFIX_DS
17001 && (address_mode != mode_64bit || last_data_prefix < 0))
17003 /* NOTRACK prefix is only valid on indirect branch instructions.
17004 NB: DATA prefix is unsupported for Intel64. */
17005 active_seg_prefix = 0;
17006 all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
17010 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
17011 "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
17015 HLE_Fixup1 (int bytemode, int sizeflag)
17018 && (prefixes & PREFIX_LOCK) != 0)
17020 if (prefixes & PREFIX_REPZ)
17021 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17022 if (prefixes & PREFIX_REPNZ)
17023 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
17026 OP_E (bytemode, sizeflag);
17029 /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
17030 "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
17034 HLE_Fixup2 (int bytemode, int sizeflag)
17036 if (modrm.mod != 3)
17038 if (prefixes & PREFIX_REPZ)
17039 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17040 if (prefixes & PREFIX_REPNZ)
17041 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
17044 OP_E (bytemode, sizeflag);
17047 /* Similar to OP_E. But the 0xf3 prefixes should be displayed as
17048 "xrelease" for memory operand. No check for LOCK prefix. */
17051 HLE_Fixup3 (int bytemode, int sizeflag)
17054 && last_repz_prefix > last_repnz_prefix
17055 && (prefixes & PREFIX_REPZ) != 0)
17056 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17058 OP_E (bytemode, sizeflag);
17062 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
17067 /* Change cmpxchg8b to cmpxchg16b. */
17068 char *p = mnemonicendp - 2;
17069 mnemonicendp = stpcpy (p, "16b");
17072 else if ((prefixes & PREFIX_LOCK) != 0)
17074 if (prefixes & PREFIX_REPZ)
17075 all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
17076 if (prefixes & PREFIX_REPNZ)
17077 all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
17080 OP_M (bytemode, sizeflag);
17084 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
17086 const char **names;
17090 switch (vex.length)
17104 oappend (names[reg]);
17108 CRC32_Fixup (int bytemode, int sizeflag)
17110 /* Add proper suffix to "crc32". */
17111 char *p = mnemonicendp;
17130 if (sizeflag & DFLAG)
17134 used_prefixes |= (prefixes & PREFIX_DATA);
17138 oappend (INTERNAL_DISASSEMBLER_ERROR);
17145 if (modrm.mod == 3)
17149 /* Skip mod/rm byte. */
17154 add = (rex & REX_B) ? 8 : 0;
17155 if (bytemode == b_mode)
17159 oappend (names8rex[modrm.rm + add]);
17161 oappend (names8[modrm.rm + add]);
17167 oappend (names64[modrm.rm + add]);
17168 else if ((prefixes & PREFIX_DATA))
17169 oappend (names16[modrm.rm + add]);
17171 oappend (names32[modrm.rm + add]);
17175 OP_E (bytemode, sizeflag);
17179 FXSAVE_Fixup (int bytemode, int sizeflag)
17181 /* Add proper suffix to "fxsave" and "fxrstor". */
17185 char *p = mnemonicendp;
17191 OP_M (bytemode, sizeflag);
17195 PCMPESTR_Fixup (int bytemode, int sizeflag)
17197 /* Add proper suffix to "{,v}pcmpestr{i,m}". */
17200 char *p = mnemonicendp;
17205 else if (sizeflag & SUFFIX_ALWAYS)
17212 OP_EX (bytemode, sizeflag);
17215 /* Display the destination register operand for instructions with
17219 OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17222 const char **names;
17230 reg = vex.register_specifier;
17231 if (address_mode != mode_64bit)
17233 else if (vex.evex && !vex.v)
17236 if (bytemode == vex_scalar_mode)
17238 oappend (names_xmm[reg]);
17242 switch (vex.length)
17249 case vex_vsib_q_w_dq_mode:
17250 case vex_vsib_q_w_d_mode:
17266 names = names_mask;
17280 case vex_vsib_q_w_dq_mode:
17281 case vex_vsib_q_w_d_mode:
17282 names = vex.w ? names_ymm : names_xmm;
17291 names = names_mask;
17294 /* See PR binutils/20893 for a reproducer. */
17306 oappend (names[reg]);
17309 /* Get the VEX immediate byte without moving codep. */
17311 static unsigned char
17312 get_vex_imm8 (int sizeflag, int opnum)
17314 int bytes_before_imm = 0;
17316 if (modrm.mod != 3)
17318 /* There are SIB/displacement bytes. */
17319 if ((sizeflag & AFLAG) || address_mode == mode_64bit)
17321 /* 32/64 bit address mode */
17322 int base = modrm.rm;
17324 /* Check SIB byte. */
17327 FETCH_DATA (the_info, codep + 1);
17329 /* When decoding the third source, don't increase
17330 bytes_before_imm as this has already been incremented
17331 by one in OP_E_memory while decoding the second
17334 bytes_before_imm++;
17337 /* Don't increase bytes_before_imm when decoding the third source,
17338 it has already been incremented by OP_E_memory while decoding
17339 the second source operand. */
17345 /* When modrm.rm == 5 or modrm.rm == 4 and base in
17346 SIB == 5, there is a 4 byte displacement. */
17348 /* No displacement. */
17350 /* Fall through. */
17352 /* 4 byte displacement. */
17353 bytes_before_imm += 4;
17356 /* 1 byte displacement. */
17357 bytes_before_imm++;
17364 /* 16 bit address mode */
17365 /* Don't increase bytes_before_imm when decoding the third source,
17366 it has already been incremented by OP_E_memory while decoding
17367 the second source operand. */
17373 /* When modrm.rm == 6, there is a 2 byte displacement. */
17375 /* No displacement. */
17377 /* Fall through. */
17379 /* 2 byte displacement. */
17380 bytes_before_imm += 2;
17383 /* 1 byte displacement: when decoding the third source,
17384 don't increase bytes_before_imm as this has already
17385 been incremented by one in OP_E_memory while decoding
17386 the second source operand. */
17388 bytes_before_imm++;
17396 FETCH_DATA (the_info, codep + bytes_before_imm + 1);
17397 return codep [bytes_before_imm];
17401 OP_EX_VexReg (int bytemode, int sizeflag, int reg)
17403 const char **names;
17405 if (reg == -1 && modrm.mod != 3)
17407 OP_E_memory (bytemode, sizeflag);
17419 if (address_mode != mode_64bit)
17423 switch (vex.length)
17434 oappend (names[reg]);
17438 OP_EX_VexImmW (int bytemode, int sizeflag)
17441 static unsigned char vex_imm8;
17443 if (vex_w_done == 0)
17447 /* Skip mod/rm byte. */
17451 vex_imm8 = get_vex_imm8 (sizeflag, 0);
17454 reg = vex_imm8 >> 4;
17456 OP_EX_VexReg (bytemode, sizeflag, reg);
17458 else if (vex_w_done == 1)
17463 reg = vex_imm8 >> 4;
17465 OP_EX_VexReg (bytemode, sizeflag, reg);
17469 /* Output the imm8 directly. */
17470 scratchbuf[0] = '$';
17471 print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
17472 oappend_maybe_intel (scratchbuf);
17473 scratchbuf[0] = '\0';
17479 OP_Vex_2src (int bytemode, int sizeflag)
17481 if (modrm.mod == 3)
17483 int reg = modrm.rm;
17487 oappend (names_xmm[reg]);
17492 && (bytemode == v_mode || bytemode == v_swap_mode))
17494 bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
17495 used_prefixes |= (prefixes & PREFIX_DATA);
17497 OP_E (bytemode, sizeflag);
17502 OP_Vex_2src_1 (int bytemode, int sizeflag)
17504 if (modrm.mod == 3)
17506 /* Skip mod/rm byte. */
17513 unsigned int reg = vex.register_specifier;
17515 if (address_mode != mode_64bit)
17517 oappend (names_xmm[reg]);
17520 OP_Vex_2src (bytemode, sizeflag);
17524 OP_Vex_2src_2 (int bytemode, int sizeflag)
17527 OP_Vex_2src (bytemode, sizeflag);
17530 unsigned int reg = vex.register_specifier;
17532 if (address_mode != mode_64bit)
17534 oappend (names_xmm[reg]);
17539 OP_EX_VexW (int bytemode, int sizeflag)
17545 /* Skip mod/rm byte. */
17550 reg = get_vex_imm8 (sizeflag, 0) >> 4;
17555 reg = get_vex_imm8 (sizeflag, 1) >> 4;
17558 OP_EX_VexReg (bytemode, sizeflag, reg);
17566 OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17569 const char **names;
17571 FETCH_DATA (the_info, codep + 1);
17574 if (bytemode != x_mode)
17578 if (address_mode != mode_64bit)
17581 switch (vex.length)
17592 oappend (names[reg]);
17596 OP_XMM_VexW (int bytemode, int sizeflag)
17598 /* Turn off the REX.W bit since it is used for swapping operands
17601 OP_XMM (bytemode, sizeflag);
17605 OP_EX_Vex (int bytemode, int sizeflag)
17607 if (modrm.mod != 3)
17609 if (vex.register_specifier != 0)
17613 OP_EX (bytemode, sizeflag);
17617 OP_XMM_Vex (int bytemode, int sizeflag)
17619 if (modrm.mod != 3)
17621 if (vex.register_specifier != 0)
17625 OP_XMM (bytemode, sizeflag);
17629 VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17631 switch (vex.length)
17634 mnemonicendp = stpcpy (obuf, "vzeroupper");
17637 mnemonicendp = stpcpy (obuf, "vzeroall");
17644 static struct op vex_cmp_op[] =
17646 { STRING_COMMA_LEN ("eq") },
17647 { STRING_COMMA_LEN ("lt") },
17648 { STRING_COMMA_LEN ("le") },
17649 { STRING_COMMA_LEN ("unord") },
17650 { STRING_COMMA_LEN ("neq") },
17651 { STRING_COMMA_LEN ("nlt") },
17652 { STRING_COMMA_LEN ("nle") },
17653 { STRING_COMMA_LEN ("ord") },
17654 { STRING_COMMA_LEN ("eq_uq") },
17655 { STRING_COMMA_LEN ("nge") },
17656 { STRING_COMMA_LEN ("ngt") },
17657 { STRING_COMMA_LEN ("false") },
17658 { STRING_COMMA_LEN ("neq_oq") },
17659 { STRING_COMMA_LEN ("ge") },
17660 { STRING_COMMA_LEN ("gt") },
17661 { STRING_COMMA_LEN ("true") },
17662 { STRING_COMMA_LEN ("eq_os") },
17663 { STRING_COMMA_LEN ("lt_oq") },
17664 { STRING_COMMA_LEN ("le_oq") },
17665 { STRING_COMMA_LEN ("unord_s") },
17666 { STRING_COMMA_LEN ("neq_us") },
17667 { STRING_COMMA_LEN ("nlt_uq") },
17668 { STRING_COMMA_LEN ("nle_uq") },
17669 { STRING_COMMA_LEN ("ord_s") },
17670 { STRING_COMMA_LEN ("eq_us") },
17671 { STRING_COMMA_LEN ("nge_uq") },
17672 { STRING_COMMA_LEN ("ngt_uq") },
17673 { STRING_COMMA_LEN ("false_os") },
17674 { STRING_COMMA_LEN ("neq_os") },
17675 { STRING_COMMA_LEN ("ge_oq") },
17676 { STRING_COMMA_LEN ("gt_oq") },
17677 { STRING_COMMA_LEN ("true_us") },
17681 VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17683 unsigned int cmp_type;
17685 FETCH_DATA (the_info, codep + 1);
17686 cmp_type = *codep++ & 0xff;
17687 if (cmp_type < ARRAY_SIZE (vex_cmp_op))
17690 char *p = mnemonicendp - 2;
17694 sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
17695 mnemonicendp += vex_cmp_op[cmp_type].len;
17699 /* We have a reserved extension byte. Output it directly. */
17700 scratchbuf[0] = '$';
17701 print_operand_value (scratchbuf + 1, 1, cmp_type);
17702 oappend_maybe_intel (scratchbuf);
17703 scratchbuf[0] = '\0';
17708 VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
17709 int sizeflag ATTRIBUTE_UNUSED)
17711 unsigned int cmp_type;
17716 FETCH_DATA (the_info, codep + 1);
17717 cmp_type = *codep++ & 0xff;
17718 /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
17719 If it's the case, print suffix, otherwise - print the immediate. */
17720 if (cmp_type < ARRAY_SIZE (simd_cmp_op)
17725 char *p = mnemonicendp - 2;
17727 /* vpcmp* can have both one- and two-lettered suffix. */
17741 sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
17742 mnemonicendp += simd_cmp_op[cmp_type].len;
17746 /* We have a reserved extension byte. Output it directly. */
17747 scratchbuf[0] = '$';
17748 print_operand_value (scratchbuf + 1, 1, cmp_type);
17749 oappend_maybe_intel (scratchbuf);
17750 scratchbuf[0] = '\0';
17754 static const struct op xop_cmp_op[] =
17756 { STRING_COMMA_LEN ("lt") },
17757 { STRING_COMMA_LEN ("le") },
17758 { STRING_COMMA_LEN ("gt") },
17759 { STRING_COMMA_LEN ("ge") },
17760 { STRING_COMMA_LEN ("eq") },
17761 { STRING_COMMA_LEN ("neq") },
17762 { STRING_COMMA_LEN ("false") },
17763 { STRING_COMMA_LEN ("true") }
17767 VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED,
17768 int sizeflag ATTRIBUTE_UNUSED)
17770 unsigned int cmp_type;
17772 FETCH_DATA (the_info, codep + 1);
17773 cmp_type = *codep++ & 0xff;
17774 if (cmp_type < ARRAY_SIZE (xop_cmp_op))
17777 char *p = mnemonicendp - 2;
17779 /* vpcom* can have both one- and two-lettered suffix. */
17793 sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
17794 mnemonicendp += xop_cmp_op[cmp_type].len;
17798 /* We have a reserved extension byte. Output it directly. */
17799 scratchbuf[0] = '$';
17800 print_operand_value (scratchbuf + 1, 1, cmp_type);
17801 oappend_maybe_intel (scratchbuf);
17802 scratchbuf[0] = '\0';
17806 static const struct op pclmul_op[] =
17808 { STRING_COMMA_LEN ("lql") },
17809 { STRING_COMMA_LEN ("hql") },
17810 { STRING_COMMA_LEN ("lqh") },
17811 { STRING_COMMA_LEN ("hqh") }
17815 PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED,
17816 int sizeflag ATTRIBUTE_UNUSED)
17818 unsigned int pclmul_type;
17820 FETCH_DATA (the_info, codep + 1);
17821 pclmul_type = *codep++ & 0xff;
17822 switch (pclmul_type)
17833 if (pclmul_type < ARRAY_SIZE (pclmul_op))
17836 char *p = mnemonicendp - 3;
17841 sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
17842 mnemonicendp += pclmul_op[pclmul_type].len;
17846 /* We have a reserved extension byte. Output it directly. */
17847 scratchbuf[0] = '$';
17848 print_operand_value (scratchbuf + 1, 1, pclmul_type);
17849 oappend_maybe_intel (scratchbuf);
17850 scratchbuf[0] = '\0';
17855 MOVBE_Fixup (int bytemode, int sizeflag)
17857 /* Add proper suffix to "movbe". */
17858 char *p = mnemonicendp;
17867 if (sizeflag & SUFFIX_ALWAYS)
17873 if (sizeflag & DFLAG)
17877 used_prefixes |= (prefixes & PREFIX_DATA);
17882 oappend (INTERNAL_DISASSEMBLER_ERROR);
17889 OP_M (bytemode, sizeflag);
17893 OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17896 const char **names;
17898 /* Skip mod/rm byte. */
17912 oappend (names[reg]);
17916 OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
17918 const char **names;
17919 unsigned int reg = vex.register_specifier;
17926 if (address_mode != mode_64bit)
17928 oappend (names[reg]);
17932 OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17935 || (bytemode != mask_mode && bytemode != mask_bd_mode))
17939 if ((rex & REX_R) != 0 || !vex.r)
17945 oappend (names_mask [modrm.reg]);
17949 OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
17952 || (bytemode != evex_rounding_mode
17953 && bytemode != evex_sae_mode))
17955 if (modrm.mod == 3 && vex.b)
17958 case evex_rounding_mode:
17959 oappend (names_rounding[vex.ll]);
17961 case evex_sae_mode: